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Table of contents for the manual
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Page 1
MF297-07 Core CPU Manual CMOS 4 - BIT SINGLE CHIP MICROCOMPUTER S1C6200/6200A[...]
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NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its appl[...]
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Page 3
The information of the product number change Configuration of product number Devices Comparison table between new and previous number S1C60 Family processors Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales r[...]
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S1C6200/6200A CORE CPU MANUAL EPSON i CONTENTS CONTENTS 1D ESCRIPTION ____________________________________________________ 1 1.1 System Features ........................................................................................................ 1 1.2 Instruction Set Features .....................................................................[...]
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[...]
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S1C6200/6200A CORE CPU MANUAL EPSON 1 1 DESCRIPTION 1D ESCRIPTION The S1C6200/6200A is the Core CPU of the S1C62 Family of CMOS 4-bit single-chip microcomput- ers. The CPU features a highly-integrated architecture. Memory-mapped peripheral circuits can include RAM, ROM, I/O ports, interrupt controllers, timers and LCD drivers, depending upon the ap[...]
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Page 8
2 EPSON S1C6200/6200A CORE CPU MANUAL 1 DESCRIPTION Fig. 1.1 Block diagram I DZC ALU S1C6200 CORE CPU 4-bit address bus 8-bit address bus 13-bit address bus 4-bit data bus 12-bit data bus Stack Pointer (8) XHL (8) YHL (8) RP (4) Program Counter Block Micro-Instructions Instruction Decorder Instruction Register (12) Program Memory ROM (8,192 12-bit [...]
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Page 9
S1C6200/6200A CORE CPU MANUAL EPSON 3 2 MEMORY AND OPERATIONS 2M EMOR Y AND O PERA TIONS A single-chip microcomputer using the S1C6200/6200A Core CPU has four major blocks: the program memory (ROM), the data memory (RAM and I/O), the arithmetic logic unit (ALU) and the timing generator circuit. This section describes each of these blocks in detail.[...]
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4 EPSON S1C6200/6200A CORE CPU MANUAL 2 MEMORY AND OPERATIONS 2.1.1 Program counter block The program counter is used to point to the next instruction step to be executed by the CPU. See Figure 2.1.1.1. The program counter has the following registers. Table 2.1.1.1 Program counter registers PCB (Program Counter-Bank) PCP (Program Counter-Page) PCS [...]
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Page 11
S1C6200/6200A CORE CPU MANUAL EPSON 5 2 MEMORY AND OPERATIONS 2.1.3 Jump instructions A jump can be made using the instructions in Table 2.1.3.1. Table 2.1.3.1 Jump instructions Unconditional Conditional Subroutine call Return Page set Indirect Type of jump Instruction JP JP C, JP NC, JP Z, JP NZ CALL, CALZ RET, RETS, RETD PSET JPBA The differences[...]
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Page 12
6 EPSON S1C6200/6200A CORE CPU MANUAL 2 MEMORY AND OPERATIONS 2.1.6 PSET instruction Jump or call instructions must follow PSET immediately in order for PSET to affect the destination address. When a jump or call is not immediately preceded by PSET, the destination address is within the current page. Some examples using PSET are shown in Table 2.1.[...]
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Page 13
S1C6200/6200A CORE CPU MANUAL EPSON 7 2 MEMORY AND OPERATIONS The difference between CALL and CALZ is shown in Figure 2.1.7.2. Page 15 Bank 0 Page 14 PSET CALL Bank 0 Step 0 Step 1 Step 254 Step 255 Bank 0 Page 1 Bank 0 Page 0 Bank 0 Step 0 Step 1 Step 254 Step 255 Page 15 Bank 1 Bank 1 Step 0 Step 1 Step 254 Step 255 Page 3 CALZ Bank 1 Bank 0 Bank[...]
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Page 14
8 EPSON S1C6200/6200A CORE CPU MANUAL 2 MEMORY AND OPERATIONS 2.2 Data Memory The data memory area comprises 4,096 4-bit words. The RAM, timer, I/O and other peripheral circuits are mapped into this memory according to the designer's specifications. Figure 2.2.1 shows the data memory configuration. Page 15 Page 14 Step 0 Step 1 Step 254 Step 2[...]
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S1C6200/6200A CORE CPU MANUAL EPSON 9 2 MEMORY AND OPERATIONS • Index register IY Index register IY is like the index register IX: it has a 4-bit page part (YP), an 8-bit register (YHL), and can address any location in the data memory. See Figure 2.2.1.2. YHL is divided into two 4-bit groups: the four high- order bits (YH) and the four low-order [...]
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10 EPSON S1C6200/6200A CORE CPU MANUAL 2 MEMORY AND OPERATIONS 2.3 ALU (Arithmetic Logic Unit) and Registers Table 2.3.1 shows ALU operations between the 4-bit registers, TEMPA and TEMPB. Table 2.3.1 ALU register operation Add, without carry Add, with carry Subtract, without borrow Subtract, with borrow Logical-AND Logical-OR Exclusive-OR Compariso[...]
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Page 17
S1C6200/6200A CORE CPU MANUAL EPSON 11 2 MEMORY AND OPERATIONS Hexadecimal operations will not always produce the correct result if performed in decimal mode. Note that: • An add instruction with carry (for example, ADC XH, i ) which uses index registers XH, XL, YH and YL, does not involve decimal correction even if it is performed in the decimal[...]
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12 EPSON S1C6200/6200A CORE CPU MANUAL 2 MEMORY AND OPERATIONS 2.5 Interrupts The S1C6200/6200A can have up to 15 interrupt vectors. When used with peripheral circuits, these allow internal and external interrupts to be processed easily. See Figure 2.5.3.1 through 2.5.3.4. 2.5.1 Interrupt vectors The interrupt vectors are assigned to steps 1 to 15 [...]
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S1C6200/6200A CORE CPU MANUAL EPSON 13 2 MEMORY AND OPERATIONS Fig. 2.5.3.1 Interrupt timing during execution Clock Status Instruction Fetch 5-clock Instrruction Interrupt INT1 ( *1) INT2 ( *1) JP ( *2) 12-clock instruction 7-clock instruction 5-clock instruction ... 13 to 25 clock cycles ... 13 to 20 clock cycles ... 13 to 18 clock cycles Interrup[...]
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14 EPSON S1C6200/6200A CORE CPU MANUAL 2 MEMORY AND OPERATIONS Fig. 2.5.3.3 Interrupt timing in SLEEP mode Fig. 2.5.3.4 Interrupt timing with PSET Fetch System clock CPU clock Status Instruction 5-clock Instrruction Interrupt INT1 ( *1) INT2 ( *1) JP ( *2) Interrupt processing: 14 to 15 clock cycles S1C6200/6200A Execute Note: (*1) (*2) INT1 and IN[...]
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Page 21
S1C6200/6200A CORE CPU MANUAL EPSON 15 2 MEMORY AND OPERATIONS Program Counter Step Program Counter Page Program Counter Bank New Page Pointer New Bank Pointer Stack Pointer Index Register Index Register Register Pointer General Register General Register Interrupt Flag Decimal Flag Zero Flag Carry Flag Value 00H 01H 00H 01H Undefined Undefined Unde[...]
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16 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET 3I NSTR UCTION S ET This chapter describes the entire instruction set of the S1C6200/6200A Core CPU. A subset is allocated to each device within the S1C62 Family according to the configuration of the device. Therefore not all instructions are available in every device. The relevant informatio[...]
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Page 23
S1C6200/6200A CORE CPU MANUAL EPSON 17 3 INSTRUCTION SET 3.1.1 By function B 1 0 0 0 0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A 1 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 9 1 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 0 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0[...]
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Page 24
18 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET B 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1[...]
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S1C6200/6200A CORE CPU MANUAL EPSON 19 3 INSTRUCTION SET ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ B 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A 1 1 1 1 1 1 1 1 0 1 0 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 9 1 1 1 1 1 1 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1[...]
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20 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET 3.1.2 In alphabetical order B 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 A 1 1 1 0 0 0 0 0 1 0 1 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 9 1 1 0 1 1 1 1 1 0 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 8 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1[...]
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Page 27
S1C6200/6200A CORE CPU MANUAL EPSON 21 3 INSTRUCTION SET B 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 8 1 1 1 1 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 1[...]
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22 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET B 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 0 9 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 8 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 0 1 1 0 7 0 1 1 1 1 1 1 1 1 0 0 1 e7 1 1 1 0 0 0 1 0 [...]
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S1C6200/6200A CORE CPU MANUAL EPSON 23 3 INSTRUCTION SET 3.1.3 By operation code B 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 9 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 8 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0[...]
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24 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET B 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1[...]
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S1C6200/6200A CORE CPU MANUAL EPSON 25 3 INSTRUCTION SET B 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1[...]
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26 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET 3.2 Operands This section describes the operands used in the instructions. p 5-bit immediate data or labels 00H to 1FH. Used to specify a destination address. s 8-bit immediate data or labels 00H to FFH. Used to specify a destination address. e 8-bit immediate data 00H to FFH. i 4-bit immedia[...]
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Page 33
S1C6200/6200A CORE CPU MANUAL EPSON 27 3 INSTRUCTION SET 3.4 Instruction T ypes Instructions are divided into six types according to the size of the operand. (I) MSB LSB ex: JP CALL LBPX s s MX,e etc. Op-code 8-bit operand (II) MSB LSB ex: ADD LD FAN r, i r, i r, i etc. Op-code 6-bit operand (III) MSB LSB ex: PSET p Op-code 4-bit operand (IV) MSB L[...]
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Page 34
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 28 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET ACPX MX,r Add with carry r-register to M(X), increment X by 1 A[...]
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Page 35
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 29 3 INSTRUCTION SET ADC r,i Add with carry immediate data i to r-register ADC r,q A[...]
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Page 36
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 30 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET ADC XH,i Add with carry immediate data i to XH ADC XH,i XH ← [...]
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Page 37
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 31 3 INSTRUCTION SET ADC YH,i Add with carry immediate data i to YH ADC YH,i YH ← [...]
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Page 38
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 32 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET ADD r,i Add immediate data i to r-register ADD r,i r ← r + i [...]
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Page 39
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 33 3 INSTRUCTION SET AND r,i Logical AND immediate data i with r-register AND r,i r [...]
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Page 40
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 34 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET CALL s Call subroutine CALZ s Call subroutine at page zero Sour[...]
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Page 41
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 35 3 INSTRUCTION SET CP r,i Compare immediate data i with r-register CP r,i r - i 3 [...]
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Page 42
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 36 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET CP XH,i Compare immediate data i with XH CP XH,i XH - i 3 to i [...]
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Page 43
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 37 3 INSTRUCTION SET CP YH,i Compare immediate data i with YH CP YH,i YH - i 3 to i [...]
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Page 44
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 38 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET DEC Mn DEC SP Decrement stack pointer Decrement memory DEC Mn M[...]
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Page 45
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 39 3 INSTRUCTION SET DI Disable interrupts DI I ← 0 111101010111 F 5 7 H VI 7 Not [...]
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Page 46
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 40 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET FAN r,i Logical AND immediate data i with r-register for flag c[...]
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Page 47
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 41 3 INSTRUCTION SET INC Mn Increment memory by 1 HALT Halt HALT Stops CPU 111111111[...]
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Page 48
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 42 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET Increment stack pointer by 1 INC SP INC SP SP ← SP + 1 111111[...]
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Page 49
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 43 3 INSTRUCTION SET INC Y Increment Y-register by 1 INC Y Y ← Y + 1 111011110000 [...]
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Page 50
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 44 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET JP C,s Jump if carry flag is set JP C,s PCB ← NBP, PCP ← NP[...]
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Page 51
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 45 3 INSTRUCTION SET JP NZ,s Jump if not zero JP NZ,s PCB ← NBP, PCP ← NPP, PCS [...]
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Page 52
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 46 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET JP Z,s Jump if zero JP Z,s PCB ← NBP, PCP ← NPP, PCS ← s [...]
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Page 53
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 47 3 INSTRUCTION SET LD A,Mn Load memory into A-register LD A,Mn A ← M(n 3 to n 0 [...]
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Page 54
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 48 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET LD Mn,A Load A-register into memory LD Mn,A M(n 3 to n 0 ) ← [...]
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Page 55
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 49 3 INSTRUCTION SET LDPX MX,i Load immediate data i into MX, increment X by 1 LDPX [...]
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Page 56
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 50 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET LDPY MY,i Load immediate data i into MY, increment Y by 1 LDPY [...]
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Page 57
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 51 3 INSTRUCTION SET LD r,i Load immediate data i into r-register LD r,i r ← i 3 t[...]
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Page 58
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 52 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET LD r,SPH Load SPH into r-register LD r,SPH r ← SPH 1111111001[...]
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Page 59
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 53 3 INSTRUCTION SET LD r,XH Load XH into r-register LD r,XH r ← XH 1110101001 r 1[...]
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Page 60
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 54 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET LD r,XP Load XP into r-register LD r,XP r ← XP 1110101000 r 1[...]
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Page 61
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 55 3 INSTRUCTION SET LD r,YL Load YL into r-register LD r,YL r ← YL 1110101110 r 1[...]
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Page 62
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 56 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET LD SPH,r Load r-register into SPH LD SPH,r SPH ← r 1111111000[...]
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Page 63
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 57 3 INSTRUCTION SET LD X,e Load immediate data e into X-register LD X,e XH ← e 7 [...]
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Page 64
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 58 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET LD XL,r Load r-register into XL LD XL,r XL ← r 1110100010 r 1[...]
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Page 65
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 59 3 INSTRUCTION SET LD Y,e Load immediate data e into Y-register LD Y,e YH ← e 7 [...]
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Page 66
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 60 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET LD YL,r Load r-register into YL LD YL,r YL ← r 1110100110 r 1[...]
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Page 67
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 61 3 INSTRUCTION SET NOP5 No operation for 5 clock cycles NOP5 No operation (5 clock[...]
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Page 68
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 62 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET NOT r NOT r-register (one's complement) NOT r r ← r 1101[...]
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Page 69
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 63 3 INSTRUCTION SET OR r,q Logical OR q-register with r-register OR r,q r ← r ∨[...]
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Page 70
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 64 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET POP r Pop stack data into r-register POP r r ← M(SP), SP ← [...]
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Page 71
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 65 3 INSTRUCTION SET POP XL Pop stack data into XL POP XL XL ← M(SP), SP ← SP + [...]
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Page 72
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 66 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET POP YH Pop stack data into YH POP YH YH ← M(SP), SP ← SP + [...]
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Page 73
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 67 3 INSTRUCTION SET POP YP Pop stack data into YP POP YP YP ← M(SP), SP ← SP + [...]
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Page 74
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 68 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET PUSH F Push flag onto stack PUSH F SP' ← SP - 1, M(SP&ap[...]
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Page 75
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 69 3 INSTRUCTION SET PUSH XH Push XH onto stack PUSH XH SP' ← SP - 1, M(SP&ap[...]
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Page 76
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 70 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET PUSH XP Push XP onto stack PUSH XP SP' ← SP - 1, M(SP&ap[...]
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Page 77
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 71 3 INSTRUCTION SET PUSH YL Push YL onto stack PUSH YL SP' ← SP - 1, M(SP&ap[...]
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Page 78
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 72 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET RCF Reset carry flag RCF C ← 0 11110101 1 1 10 F5EH VI 7 Rese[...]
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Page 79
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 73 3 INSTRUCTION SET RET Return from subroutine RET PCSL ← M(SP), PCSH ← M(SP+1)[...]
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Page 80
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 74 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET RETS Return then skip an instruction RETS PCSL ← M(SP), PCSH [...]
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Page 81
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 75 3 INSTRUCTION SET RRC r Rotate r-register right with carry RRC r d 3 ← C, d 2 ?[...]
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Page 82
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 76 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET RZF Reset zero flag RZF Z ← 0 11110101 1 1 01 F5DH VI 7 Not a[...]
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Page 83
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 77 3 INSTRUCTION SET SBC r,q Subtract with carry q-register from r-register SBC r,q [...]
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Page 84
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 78 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET SCPX MX,r Subtract with carry r-register from M(X) and incremen[...]
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Page 85
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 79 3 INSTRUCTION SET SDF Set decimal flag SDF D ← 1 11110100 0 1 00 F 4 4 H VI 7 N[...]
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Page 86
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 80 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET SLP Sleep SLP Stop CPU and peripheral oscillator 11111111 1 0 0[...]
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Page 87
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 81 3 INSTRUCTION SET SZF Set zero flag SZF Z ← 1 11110100 0 0 10 F 4 2 H VI 7 Not [...]
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Page 88
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – 82 EPSON S1C6200/6200A CORE CPU MANUAL 3 INSTRUCTION SET XOR r,q Exclusive-OR q-register with r-register XOR r,q r ← r[...]
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Page 89
Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: Source Format: Operation: OP-Code: Type: Clock Cycles: Flag: Description: Example: MSB LSB MSB LSB C – Z – D – I – C – Z – D – I – S1C6200/6200A CORE CPU MANUAL EPSON 83 3 INSTRUCTION SET ABBREVIATIONS A ............. A register (4 bits) B ...........[...]
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Page 90
84 EPSON S1C6200/6200A CORE CPU MANUAL APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU APPENDIX A . S1C6200A (A D V ANCED S1C6200) C ORE CPU S1C6200A is an improved version of the S1C6200. In this section, S1C6200A is described only in terms of its differences with S1C6200. It is recommended that users of S1C6200A read this section. S1C6200A is a [...]
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Page 91
S1C6200/6200A CORE CPU MANUAL EPSON 85 APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU b) At HALT mode c) During "PSET" instruction execution Fig. A2.2.1 Timing chart of S1C6200A interrupt a) During instruction execution Fetch Clock Status Instruction PSET Interrupt INT1 ( *1) INT2 ( *1) JP ( *2) PSET + CALL PSET + JP ... 12.5 to 24.5 cl[...]
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Page 92
86 EPSON S1C6200/6200A CORE CPU MANUAL APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU <Reference 1> Writing on the interrupt mask register during EI This section describes the operation for writing on the interrupt mask register during EI (enable interrupt flag) in the regular 1-chip micro controller which uses S1C6200 Core CPU and in the r[...]
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Page 93
S1C6200/6200A CORE CPU MANUAL EPSON 87 APPENDIX B. INSTRUCTION INDEX APPENDIX B. I NSTRUCTION I NDEX ACPX MX,r Add with carry r-register to M(X), increment X by 1 ........................... 28 ACPY MY,r Add with carry r-register to M(Y), increment Y by 1 ........................... 28 ADC r,i Add with carry immediate data i to r-register .........[...]
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Page 94
88 EPSON S1C6200/6200A CORE CPU MANUAL APPENDIX B. INSTRUCTION INDEX LBPX MX,e Load immediate data e to memory, and increment X by 2 ................... 46 LD A,Mn Load memory into A-register ............................................................... 47 LD B,Mn Load memory into B-register .......................................................[...]
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Page 95
S1C6200/6200A CORE CPU MANUAL EPSON 89 APPENDIX B. INSTRUCTION INDEX PUSH r Push r-register onto stack .................................................................... 68 PUSH XH Push XH onto stack .............................................................................. 69 PUSH XL Push XL onto stack .......................................[...]
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Page 96
AMERICA EPSON ELECTRONICS AMERICA, INC. - HEADQUARTERS - 1960 E. Grand Avenue EI Segundo, CA 90245, U.S.A. Phone: +1-310-955-5300 Fax: +1-310-955-5400 - SALES OFFICES - West 150 River Oaks Parkway San Jose, CA 95134, U.S.A. Phone: +1-408-922-0200 Fax: +1-408-922-0238 Central 101 Virginia Street, Suite 290 Crystal Lake, IL 60014, U.S.A. Phone: +1-81[...]
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In pursuit of “Saving” T echnology , Epson electronic de vices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings .[...]
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http://www.epson.co.jp/device/ Core CPU Manual S1C6200/6200A EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION First issue February, 1 989 Printed February, 2001 in Japan A M[...]