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Freescale Semiconductor Block Guide manual

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Table of contents for the manual

  • Page 1

    Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims an[...]

  • Page 2

    Block Guide — S12EETX4KV0 V00.04 2 Revision History Frees cale Semiconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc. ..[...]

  • Page 3

    Block Guide — S12EETX4KV0 V00.04 3 Table of Contents Section 1 Introduction 1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 Feature[...]

  • Page 4

    Block Guide — S12EETX4KV0 V00.04 4 4.4 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5 EEPROM Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5.1 Unsecuring the MCU in Special Single Chip Mode via the BDM . . . . . .[...]

  • Page 5

    Block Guide — S12EETX4KV0 V00.04 5 List of Figures Figure 1-1 Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 3-1 EEPROM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 3-2 EEPROM Clock Divider Register (ECLKDIV) . . . . . . . [...]

  • Page 6

    Block Guide — S12EETX4KV0 V00.04 6 Frees cale Semiconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc. ..[...]

  • Page 7

    Block Guide — S12EETX4KV0 V00.04 7 List of Tables Table 3-1 EEPROM Configuration Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3-2 EEPROM Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3-3 EEPROM Protection Address Range . . . . . . . . . . . . .[...]

  • Page 8

    Block Guide — S12EETX4KV0 V00.04 8 Frees cale Semiconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc. ..[...]

  • Page 9

    Block Guide — S12EETX4KV0 V00.04 9 Frees cale Semiconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc. ..[...]

  • Page 10

    Block Guide — S12EETX4KV0 V00.04 10 Frees cale Semiconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc. ..[...]

  • Page 11

    Block Guide — S12EETX4KV0 V00.04 11 Section 1 Introduction 1.1 Overview This document describes the EETX4K module which includes a 4K byte EEPROM (Non-Volatile) memory. The EEPROM memory may be read as either bytes, aligned words or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned [...]

  • Page 12

    Block Guide — S12EETX4KV0 V00.04 12 1.4 Block Diagram A block diagram of the EEPROM module is shown in Figure 1-1 . Figure 1-1 Module Block Diagram EETX4K EEPROM 2K * 16 Bits sector 0 sector 1 sector 1023 Oscillator Clock Divider Clock Command Interrupt Request EECLK Protection Command Pipeline cmd2 addr2 data2 cmd1 addr1 data1 Registers EEPROM I[...]

  • Page 13

    Block Guide — S12EETX4KV0 V00.04 13 Section 2 External Signal Description 2.1 Overview The EEPROM module contains no signals that connect off-chip. Frees cale Semiconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc. ..[...]

  • Page 14

    Block Guide — S12EETX4KV0 V00.04 14 Section 3 Memory Map and Registers 3.1 Overview This section describes the memory map and registers for the EEPROM module. 3.2 Module Memory Map A linear EEPROM memory map is shown in Figure 3-1 . The HCS12X architecture actually places the EEPROM memory addresses between logical addresses $0800 and $1000 with [...]

  • Page 15

    Block Guide — S12EETX4KV0 V00.04 15 Figure 3-1 EEPROM Memory Map EEPROM Registers ADDRESS OFFSET = $_00 EEPROM Configuration Field ADDRESS OFFSET = $_0B EEPROM BASE + $_000 EEPROM BASE + $_FFF + $_FC0 + $_F80 EEPROM Memory Protected Region 64, 128, 192, 256, 320, 384, 448, 512 bytes EEPROM Memory 3584 bytes (up to 4032 b ytes) 12 bytes 16 bytes [...]

  • Page 16

    Block Guide — S12EETX4KV0 V00.04 16 The EEPROM module also contains a set of 12 control and status registers located between EEPROM register address offsets $_00 and $_0B. A summary of the EEPROM module registers is given in Table 3-2 while their accessibility is detailed in section 3.3 . NOTE: Register Address = EEPROM Control Register Base Addr[...]

  • Page 17

    Block Guide — S12EETX4KV0 V00.04 17 3.3 Register Descriptions 3.3.1 ECLKDIV — EEPROM Clock Divider Register The ECLKDIV register is used to control timed events in program and erase algorithms. Figure 3-2 EEPROM Clock Divider Register (ECLKDIV) All bits in the ECLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable. EDI[...]

  • Page 18

    Block Guide — S12EETX4KV0 V00.04 18 3.3.3 RESERVED2 This register is reserved for factory testing and is not accessible. Figure 3-4 RESERVED2 All bits read zero and are not writable. 3.3.4 ECNFG — EEPROM Configuration Register The ECNFG register enables the EEPROM interrupts. Figure 3-5 EEPROM Configuration Register (ECNFG) CBEIE and CCIE bits [...]

  • Page 19

    Block Guide — S12EETX4KV0 V00.04 19 3.3.5 EPROT — EEPROM Protection Register The EPROT register defines which EEPROM sectors are protected against program or erase operations. Figure 3-6 EEPROM Protection Register (EPROT) All bits in the EPROT register are readable and writable except for RNV[6:4] which are only readable. The EPOPEN and EPDIS b[...]

  • Page 20

    Block Guide — S12EETX4KV0 V00.04 20 3.3.6 ESTAT — EEPROM Status Register The ESTAT register defines the operational status of the module. Figure 3-7 EEPROM Status Register (ESTAT) CBEIF, PVIOL and ACCERR are readable and writable, CCIF and BLANK are readable and not writable, remaining bits read zero and are not writable. CBEIF — Command Buff[...]

  • Page 21

    Block Guide — S12EETX4KV0 V00.04 21 The CCIF flag indicates that there are no more commands pending. The CCIF flag is cleared when CBEIF is clear and sets automatically upon completion of all active and pending commands. The CCIF flag does not set when an active commands completes and a pending command is fetched from the command buffer. Writing [...]

  • Page 22

    Block Guide — S12EETX4KV0 V00.04 22 Figure 3-8 EEPROM Command Register (ECMD) All CMDB bits are readable and writable during a command write sequence while bit 7 reads zero and is not writable. CMDB[6:0] — Valid EEPROM commands are shown in Table 3-4 . Writing any command other than those listed in Table 3-4 sets the ACCERR flag in the ESTAT re[...]

  • Page 23

    Block Guide — S12EETX4KV0 V00.04 23 3.3.9 EADDR — EEPROM Address Registers The EADDRHI and EADDRLO registers are the EEPROM address registers. Figure 3-10 EEPROM Address High Register (EADDRHI) Figure 3-11 EEPROM Address Low Register (EADDRLO) All EABHI and EABLO bits read zero and are not writable in normal modes. All EABHI and EABLO bits are [...]

  • Page 24

    Block Guide — S12EETX4KV0 V00.04 24 Figure 3-13 EEPROM Data Low Register (EDATALO) All EDHI and EDLO bits read zero and are not writable in normal modes. All EDHI and EDLO bits are readable and writable in special modes. Address Offset: $_0B 76543210 R EDLO W Reset: 00000000 = Unimplemented or Reserved Frees cale Semiconductor, I Freescale Semico[...]

  • Page 25

    Block Guide — S12EETX4KV0 V00.04 25 Section 4 Functional Description 4.1 EEPROM Command Operations Write and read operations are both used for the program, erase, erase verify, sector erase abort, and sector modify algorithms described in this section. The program, erase, and sector modify algorithms are controlled by a state machine whose timeba[...]

  • Page 26

    Block Guide — S12EETX4KV0 V00.04 26 then 182kHz. In this case, the EEPROM program and erase algorithm timings are increased over the optimum target by: NOTE: "4"Program and erase command execution time will increase proportionally with the period of EECLK. NOTE: Because of the impact of clock synchronization on the accuracy of the funct[...]

  • Page 27

    Block Guide — S12EETX4KV0 V00.04 27 Figure 4-1 Determination Procedure for PRDIV8 and EDIV Bits PRDIV8=1 yes no PRDIV8=0 (reset) 12.8MHz? EECLK=(PRDCLK)/(1+EDIV[5:0]) PRDCLK=oscillator_clock PRDCLK=oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[ µ s]) no EDIV[5:0]=PRDCLK[MHz]*(5+Tbus[ µ s])-1 yes START Tbus < 1 µ s? an integer? EDIV[5:0]=INT(PRDCLK[...]

  • Page 28

    Block Guide — S12EETX4KV0 V00.04 28 4.1.2 Command Write Sequence The EEPROM command controller is used to supervise the command write sequence to execute program, erase, erase verify, sector erase abort, and sector modify algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the ESTAT register must be clear (see sect[...]

  • Page 29

    Block Guide — S12EETX4KV0 V00.04 29 NOTE: The user should not program an EEPROM word without first erasing the sector in which that word resides. 4.1.3.1 Erase Verify Command The erase verify operation will verify that the EEPROM memory is erased. An example flow to execute the erase verify operation is shown in Figure 4-2 . The erase verify comm[...]

  • Page 30

    Block Guide — S12EETX4KV0 V00.04 30 Figure 4-2 Example Erase Verify Command Flow 4.1.3.2 Program Command The program operation will program a previously erased word in the EEPROM memory using an embedded algorithm. An example flow to execute the program operation is shown in Figure 4-3 . The program command write sequence is as follows: 1. Write [...]

  • Page 31

    Block Guide — S12EETX4KV0 V00.04 31 2. Write the program command, $20, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a “1” to CBEIF to launch the program command. If a word to be programmed is in a protected area of the EEPROM memory, the PVIOL flag in the ESTAT register will set and the program command will n[...]

  • Page 32

    Block Guide — S12EETX4KV0 V00.04 32 Figure 4-3 Example Program Command Flow 4.1.3.3 Sector Erase Command The sector erase operation will erase both words in a sector of EEPROM memory using an embedded algorithm. Write: EEPROM Address Write: ECMD register Program Command $20 Write: EST A T register Clear CBEIF $80 1. 2. 3. Clear ACCERR/PVIOL $30 W[...]

  • Page 33

    Block Guide — S12EETX4KV0 V00.04 33 An example flow to execute the sector erase operation is shown in Figure 4-4 . The sector erase command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the sector erase command. The EEPROM address written determines the sector to be erased while global [...]

  • Page 34

    Block Guide — S12EETX4KV0 V00.04 34 Figure 4-4 Example Sector Erase Command Flow 4.1.3.4 Mass Erase Command The mass erase operation will erase all addresses in an EEPROM block using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 4-5 . The mass erase command write sequence is as follows: 1. Write to [...]

  • Page 35

    Block Guide — S12EETX4KV0 V00.04 35 If the EEPROM memory to be erased contains any protected area, the PVIOL flag in the ESTAT register will set and the mass erase command will not launch. Once the mass erase command has successfully launched, the CCIF flag in the ESTAT register will set after the mass erase operation has completed unless a new c[...]

  • Page 36

    Block Guide — S12EETX4KV0 V00.04 36 1. Write to any EEPROM memory address to start the command write sequence for the sector erase abort command. The address and data written are ignored. 2. Write the sector erase abort command, $47, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a “1” to CBEIF to launch the se[...]

  • Page 37

    Block Guide — S12EETX4KV0 V00.04 37 Figure 4-6 Example Sector Erase Abort Command Flow 4.1.3.6 Sector Modify Command The sector modify operation will erase both words in a sector of EEPROM memory followed by a reprogram of the addressed word using an embedded algorithm. An example flow to execute the sector modify operation is shown in Figure 4-7[...]

  • Page 38

    Block Guide — S12EETX4KV0 V00.04 38 2. Write the sector modify command, $60, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a “1” to CBEIF to launch the sector erase command. If an EEPROM sector to be modified is in a protected area of the EEPROM memory, the PVIOL flag in the ESTAT register will set and the sec[...]

  • Page 39

    Block Guide — S12EETX4KV0 V00.04 39 1. Writing to an EEPROM address before initializing the ECLKDIV register. 2. Writing a byte or misaligned word to a valid EEPROM address. 3. Starting a command write sequence while a sector erase abort operation is active. 4. Writing to any EEPROM register other than ECMD after writing to an EEPROM address. 5. [...]

  • Page 40

    Block Guide — S12EETX4KV0 V00.04 40 4.2 Wait Mode If a command is active (CCIF=0) when the MCU enters the WAIT mode, the active command and any buffered command will be completed. The EEPROM module can recover the MCU from WAIT if the CBEIF and CCIF interrupts are enabled (see section 4.7 ). 4.3 Stop Mode If a command is active (CCIF = 0) when th[...]

  • Page 41

    Block Guide — S12EETX4KV0 V00.04 41 BDM status register. This BDM action will cause the MCU to override the Flash security state and the MCU will be unsecured. Once the MCU is unsecured, BDM commands will be enabled and the Flash security byte may be programmed to the unsecure state. 4.6 Resets 4.6.1 EEPROM Reset Sequence On each reset, the EEPRO[...]

  • Page 42

    Block Guide — S12EETX4KV0 V00.04 42 Figure 4-8 EEPROM Interrupt Implementation For a detailed description of the register bits, refer to the EEPROM Configuration register and EEPROM Status register sections (see sections 3.3.4 and 3.3.6 respectively). EEPROM Command Interrupt Request CBEIE CBEIF CCIE CCIF Frees cale Semiconductor, I Freescale Sem[...]

  • Page 43

    Block Guide — S12EETX4KV0 V00.04 43 Index –A– ACCERR 21 –B– Background Debug Mode 40 BLANK 21 –C– CBEIE 18 CBEIF 20 CCIE 18 CCIF 20 CMDB 22 Command Write Sequence 11 –E– EDIV 17 EDIVLD 17 EPDIS 19 EPOPEN 19 EPS 19 –I– Illegal EEPROM Operations 38 –K– KEYACC 19 –P– PRDIV8 17 PVIOL 21 –R– Registers EADDR 23 ECLKDIV 1[...]

  • Page 44

    Block Guide — S12EETX4KV0 V00.04 44 Frees cale Semiconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc. ..[...]

  • Page 45

    Block Guide — S12EETX4KV0 V00.04 45 Block Guide End Sheet Frees cale Semiconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc. ..[...]

  • Page 46

    Block Guide — S12EETX4KV0 V00.04 46 FINAL PAGE OF 46 PAGES Frees cale Semiconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc. ..[...]