Freescale Semiconductor MC9S12XDP512 manual

HCS12X Micr ocontr ollers freescale.com MC9S12XDP512 Data Sheet MC9S12XDP512 Rev. 2.11 5/2005[...]

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MC9S12XDP512 Data Sheet covers MC9S12XDT384 & MC9S12XA512 MC9S12XDP512V2 Rev. 2.11 7/2005[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 4 F reescale Semiconductor To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history tab[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 5 Contents Section Number Title Page Chapter 1 Device Overview (MC9S12XDP512V2) . . . . . . . . . . . . . . . . . . . 23 Chapter 2 512 Kbyte Flash Module (S12XFTX512K4V2). . . . . . . . . . . . . 101 Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) . . . . . . . . . . . . . 145 Chapter 4 Po[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 6 F reescale Semiconductor Section Number Title Page Chapter 23 Memory Mapping Control (S12XMMCV2) . . . . . . . . . . . . . . . . 881 Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919 Appendix B Package Information . . . . . . . . . . . . . . . . . . . . . . . . .[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 7 Contents Section Number Title Page Chapter 1 Device Overview (MC9S12XDP512V2) 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.1.1 Features . . . . . . . . . . . . . . . . . . . . . [...]

MC9S12XDP512 Data Sheet, Rev . 2.11 8 F reescale Semiconductor Section Number Title Page 2.3.2 Re gister Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 9 Section Number Title Page 3.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 3.8.1 Description of EEPR OM Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 10 F reescale Semiconductor Section Number Title Page 5.5.4 Po wer On Reset, Lo w V oltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 11 Section Number Title Page 7.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

MC9S12XDP512 Data Sheet, Rev . 2.11 12 F reescale Semiconductor Section Number Title Page 9.6 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 9.6.1 Deb ug Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 13 Section Number Title Page 11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

MC9S12XDP512 Data Sheet, Rev . 2.11 14 F reescale Semiconductor Section Number Title Page 13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 15 Section Number Title Page Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 15.1.1 Features . . . . . . . . . . . . . . . [...]

MC9S12XDP512 Data Sheet, Rev . 2.11 16 F reescale Semiconductor Section Number Title Page 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 16.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 17 Section Number Title Page 18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 18.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

MC9S12XDP512 Data Sheet, Rev . 2.11 18 F reescale Semiconductor Section Number Title Page 20.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792 20.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 19 Section Number Title Page 22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 22.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

MC9S12XDP512 Data Sheet, Rev . 2.11 20 F reescale Semiconductor Section Number Title Page A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 21 Section Number Title Page Appendix C Recommended PCB Layout Appendix D Derivative Differences D.1 Memory Sizes and Package Options S12XD - Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974 D.2 Memory Sizes and Package Options S12XA - Family . . . . . . . . . [...]

MC9S12XDP512 Data Sheet, Rev . 2.11 22 F reescale Semiconductor Section Number Title Page[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 23 Chapter 1 De vice Overview (MC9S12XDP512V2) 1.1 Intr oduction The MC9S12XD family will retain the lo w cost, po wer consumption, EMC and code-size ef ficienc y adv antages currently enjoyed by users of Freescale's e xisting 16-Bit MC9S12 MCU Family. Based around an enhanced S12 c[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 24 F reescale Semiconductor 1.1.1 Features • HCS12X Core — 16-bit HCS12X CPU – Upward compatible with MC9S12 instruction set – Interrupt stacking and programmer’ s model identical to MC9S12 – Instruction queue – Enhanced index ed addressing – Enhanced ins[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 25 • Fi ve 1 M bit per second, CAN 2.0 A, B softw are compatible modules — Fiv e recei ve and three transmit b uf fers — Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit — Four separate interrupt channels [...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 26 F reescale Semiconductor • De velopment support — Single-wire background debug™ mode (BDM) — Four on-chip hardware breakpoints 1.1.2 Modes of Operation User modes: • Normal and emulation operating modes — Normal single-chip mode — Normal expanded mode ?[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 27 Figure 1-1. MC9S12XD-Famil y Block Dia gram 512/384/256/128/64-Kbyte Flash 32/20/16/14/10/8/4-Kbyte RAM Enhanced Capture RESET EXT AL XT AL SCI0 4/2/1-Kbyte EEPR OM BKGD R/ W/ WE MODB/T AGHI XIRQ ECLKX2/ XCLKS CPU12X P eriodic Interrupt COP W [...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 28 F reescale Semiconductor 1.1.4 Device Memory Map T able 1-1 sho ws the device re gister memory map of the MC9S12XDP512. T able 1-1. Device Register Memory Map Address Module Size (Bytes) 0x0000–0x0009 PIM (por t integration module ) 10 0x000A–0x000B MMC (memor y m[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 29 NO TE Reserved re gister space sho wn in T able 1-1 is not allocated to any module. This register space is reserv ed for future use. Writing to these locations ha ve no ef fect. Read access to these locations returns zero. 0x0180–0x01BF CAN1[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 30 F reescale Semiconductor 1.1.5 Address Mapping 1.1.5.1 Local-to-Global Address Mapping Figure 1-2. Local-to-Global Address Mapping S12X_CPU/S12X_BDM $7F_FFFF $00_0000 $7F_C000 $14_0000 $13_FC00 $10_0000 $FFFF V ectors $C000 $8000 Unpaged Flash $4000 $1000 $0000 2K Reg[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 31 Figure 1-3. Local-to-Global Address Mapping XGA TE $7F_FFFF $00_0000 $10_0000 $FFFF $0000 2K Registers $0800 2K Registers $00_0800 $00_1000 RAM XGA TE Local Memory Map Device Global Memory Map RAM FLASH 30KB FLASH $78_0800 Not Used by XGA TE $[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 32 F reescale Semiconductor 1.1.5.2 Logical Address Map Figure 1-4. Memory Map $0000 $FFFF $C000 $8000 $4000 $0800 $1000 $FF00 EXT Normal Single Chip Expanded Special Single Chip V ectors V ectors V ectors $FF00 $FFFF BDM (If Active , except f or specific BDM hardware $[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 33 1.1.6 Detailed Register Map The follo wing tables sho w the detailed register map of the MC9S12XDP512. 0x0000–0x0009 Port Integration Module (PIM) Map 1 of 5 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0000 POR T A R P A7 [...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 34 F reescale Semiconductor 0x0010–0x0017 Module Mapping Control (S12XMMC) Map 2 of 4 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0010 GP A GE R0 GP6 GP5 GP4 GP3 GP2 GP1 GP0 W 0x0011 DIRECT R DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 W 0x0012 Reser ved R[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 35 0x0020–0x0027 Debug Module (S12XDBG) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0020 DBGC1 R ARM 0 XGSBPE BDM DBGBRK COMR V W TRIG 0x0021 DBGSR R TBF EXTF 0 0 0 SSF2 SSF1 SSF0 W 0x0022 DBGTCR R TSOURCE TRANGE TRCMOD T[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 36 F reescale Semiconductor 0x0030–0x0031 Module Mapping Control (S12XMMC) Map 3 of 4 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0030 PP AGE R PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 W 0x0031 Reser ved R 00000000 W 0x0032–0x0033 Port Integration M[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 37 0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 1 of 3) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0040 TIOS R IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 W 0x0041 CFORC R 00000000 W FOC7 FOC6 FOC5 FOC[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 38 F reescale Semiconductor 0x0056 TC3 (hi) R Bit 15 14 13 12 11 10 9 Bit 8 W 0x0057 TC3 (lo) R Bit 7 654321 Bit 0 W 0x0058 TC4 (hi) R Bit 15 14 13 12 11 10 9 Bit 8 W 0x0059 TC4 (lo) R Bit 7 654321 Bit 0 W 0x005A TC5 (hi) R Bit 15 14 13 12 11 10 9 Bit 8 W 0x005B TC5 (lo)[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 39 0x006D TIMTST R 00000000 W Reser ved F or F actor y T est 0x006E PTPSR R PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 W 0x006F PTMCPSR R PTMPS7 PTMPS6 PTMPS5 PTMPS4 PTMPS3 PTMPS2 PTMPS1 PTMPS0 W 0x0070 PBCTL R0 PBEN 0000 PBO VI 0 W 0x0071 P[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 40 F reescale Semiconductor 0x0080–0x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD1) Map (Sheet 1 of 3) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0080 A TD1CTL0 R 0000 WRAP3 WRAP2 WRAP1 WRAP0 W 0x0081 A TD1CTL1 R ETRIG SEL 000 ETRIG CH3 [...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 41 0x0096 A TD1DR3H R Bit15 14 13 12 11 10 9 Bit8 W 0x0097 A TD1DR3L R Bit7 Bit6 000000 W 0x0098 A TD1DR4H R Bit15 14 13 12 11 10 9 Bit8 W 0x0099 A TD1DR4L R Bit7 Bit6 000000 W 0x009A A TD1DR5H R Bit15 14 13 12 11 10 9 Bit8 W 0x009B A TD1DR5L R B[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 42 F reescale Semiconductor 0x00A C A TD1DR14H R Bit15 14 13 12 11 10 9 Bit8 W 0x00AD A TD1DR14L R Bit7 Bit6 000000 W 0x00AE A TD1DR15H R Bit15 14 13 12 11 10 9 Bit8 W 0x00AF A TD1DR15L R Bit7 Bit6 000000 W 0x00B0–0x00B7 Inter IC Bus (IIC1) Map Address Name Bit 7 Bit 6[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 43 0x00BB SCI2CR2 R TIE TCIE RIE ILIE TE RE RWU SBK W 0x00BC SCI2SR1 R TDRE TC RDRF IDLE OR NF FE PF W 0x00BD SCI2SR2 R AMAP 00 TXPOL RXPOL BRK13 TXDIR RAF W 0x00BE SCI2DRH RR 8 T8 000000 W 0x00BF SCI2DRL R R 7R 6R 5R 4R 3R 2R 1R 0 W T 7T 6T 5T 4[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 44 F reescale Semiconductor 0x00C8–0x00CF Asynchronous Serial Interface (SCI0) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00C8 SCI0BDH 1 1 Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to z ero R IREN TNP1 TNP0 SB[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 45 0x00D5 SCI1SR2 R AMAP 00 TXPOL RXPOL BRK13 TXDIR RAF W 0x00D6 SCI1DRH RR 8 T8 000000 W 0x00D7 SCI1DRL R R 7R 6R 5R 4R 3R 2R 1R 0 W T 7T 6T 5T 4T 3T 2T 1T 0 1 Those registers are accessible if the AMAP bit in the SCI1SR2 register is set to z er[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 46 F reescale Semiconductor 0x00E5 Reser ved R 0 0 0 0 0 0 0 0 W 0x00E6 Reser ved R 00000000 W 0x00E7 Reser ved R 00000000 W 0x00E8–0x00EF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00E8 Reser ved R 00000000 W 0x00E9 Reser ved R 00000000 W [...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 47 0x00F8–0x00FF Serial Peripheral Interface (SPI2) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00F8 SPI2CR1 R SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE W 0x00F9 SPI2CR2 R0 0 0 MODFEN BIDIROE 0 SPISW AI SPC0 W 0x00F A SPI2[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 48 F reescale Semiconductor 0x010C Reserved R 00000000 W 0x010D Reserved R 00000000 W 0x010E Reser ved R 00000000 W 0x010F Reser ved R 00000000 W 0x0110–0x011B EEPROM Control Register (EETX4K) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0110 ECLK[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 49 0x011C–0x011F Memory Map Control (S12XMMC) Map 4 of 4 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x011C RAMWPC R RPWE 00000 A VIE A VIF W 0x011D RAMXGU R1 XGU6 XGU5 XGU4 XGU3 XGU2 XGU1 XGU0 W 0x011E RAMSHL R1 SHL6 SHL5 SHL4[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 50 F reescale Semiconductor 0x00130–0x0137 Asynchronous Serial Interface (SCI4) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0130 SCI4BDH 1 1 Those registers are accessible if the AMAP bit in the SCI4SR2 register is set to z ero R IREN TNP1 TNP0 S[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 51 0x013D SCI5SR2 R AMAP 00 TXPOL RXPOL BRK13 TXDIR RAF W 0x013E SCI5DRH RR 8 T8 000000 W 0x013F SCI5DRL R R 7R 6R 5R 4R 3R 2R 1R 0 W T 7T 6T 5T 4T 3T 2T 1T 0 1 Those registers are accessible if the AMAP bit in the SCI5SR2 register is set to z er[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 52 F reescale Semiconductor 0x0150– 0x0153 CAN0ID AR0– CAN0ID AR3 R AC 7 AC 6 AC 5 AC4 AC 3 AC 2 AC 1 AC 0 W 0x0154– 0x0157 CAN0IDMR0– CAN0IDMR3 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x0158– 0x015B CAN0ID AR4– CAN0ID AR7 R AC 7 AC 6 AC 5 AC4 AC 3 AC 2 AC 1 AC 0[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 53 0xXX0x XX10 Extended ID R ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15 CANxTIDR1 W Standard ID R ID2 ID1 ID0 R TR IDE=0 W 0xXX12 Extended ID R ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 CANxTIDR2 W Standard ID R W 0xXX13 Extended ID R ID6 ID5 ID4 ID3 I[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 54 F reescale Semiconductor 0x0189 CAN1T AAK R 00000 A B T A K 2 A B T A K 1 A B T A K 0 W 0x018A CAN1TBSEL R 00000 TX2 TX1 TX0 W 0x018B CAN1ID A C R0 0 IDAM1 ID AM0 0 IDHIT2 IDHIT1 IDHIT0 W 0x018C Reserved R 00000000 W 0x018D CAN1MISC R 0000000 BOHOLD W 0x018E CAN1RXERR[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 55 0x019F CAN1IDMR7 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x01A0– 0x01AF CAN1RXFG R FOREGROUND RECEIVE B UFFER (See Detailed MSCAN F oreground Receiv e and T ransmit Buffer La yout ) W 0x01B0– 0x01BF CAN1TXFG R FOREGROUND TRANSMIT B UFFER (See [...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 56 F reescale Semiconductor 0x01D1 CAN2ID AR1 R AC7 AC 6 AC 5 AC 4 AC 3 AC 2 AC 1 AC 0 W 0x01D2 CAN2ID AR2 R AC7 AC 6 AC 5 AC 4 AC 3 AC 2 AC 1 AC 0 W 0x01D3 CAN2ID AR3 R AC7 AC 6 AC 5 AC 4 AC 3 AC 2 AC 1 AC 0 W 0x01D4 CAN2IDMR0 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x01D5 [...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 57 0x0200–0x023F Freescale Scalable CAN — MSCAN (CAN3) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0200 CAN3CTL0 R RXFRM RXA CT CSW AI SYNCH TIME WUPE SLPRQ INITRQ W 0x0201 CAN3CTL1 R CANE CLKSRC LOOPB LISTEN BORM WUPM SLP [...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 58 F reescale Semiconductor 0x0216 CAN3IDMR2 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x0217 CAN3IDMR3 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x0218 CAN3ID AR4 R AC 7 AC 6 AC 5 AC 4 AC 3 AC 2 AC 1 AC 0 W 0x0219 CAN3ID AR5 R AC 7 AC 6 AC 5 AC 4 AC 3 AC 2 AC 1 AC 0 W 0x021A CAN3ID[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 59 0x0248 PTS R PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 W 0x0249 PTIS R PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 W 0x024A DDRS R DDRS7 DDRS7 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 W 0x024B RDRS R RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 60 F reescale Semiconductor 0x0260 PTH R PTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0 W 0x0261 PTIH R PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0 W 0x0262 DDRH R DDRH7 DDRH7 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 W 0x0263 RDRH R RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 61 0x0278 PT0AD1 R PT0AD1 23 PT0AD1 22 PT0AD1 21 PT0AD1 20 PT0AD1 19 PT0AD1 18 PT0AD1 17 PT0AD1 16 W 0x0279 PT1AD1 R PT1AD1 15 PT1AD1 14 PT1AD1 13 PT1AD1 12 PT1AD1 11 PT1AD1 10 PT1AD1 9 PT1AD1 8 W 0x027A DDR0AD1 R DDR0AD1 23 DDR0AD1 22 DDR0AD1 21[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 62 F reescale Semiconductor 0x028D CAN4MISC R 0000000 BOHOLD W 0x028E CAN4RXERR R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 W 0x028F CAN4TXERR R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 W 0x0290 CAN4ID AR0 R AC 7 AC 6 AC 5 AC 4 AC 3 AC 2 AC 1[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 63 0x02C0–0x02DF Analog-to-Digital Converter 10-Bit 8-Channel (ATD0) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x02C0 A TD0CTL0 R 00000 WRAP2 WRAP1 WRAP0 W 0x02C1 A TD0CTL1 R ETRIG SEL 0000 ETRIG CH2 ETRIG CH1 ETRIG CH0 W[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 64 F reescale Semiconductor 0x02D6 A TD0DR3H R Bit15 14 13 12 11 10 9 Bit8 W 0x02D7 A TD0DR3L R Bit7 Bit6 000000 W 0x02D8 A TD0DR4H R Bit15 14 13 12 11 10 9 Bit8 W 0x02D9 A TD0DR4L R Bit7 Bit6 000000 W 0x02D A A TD0DR5H R Bit15 14 13 12 11 10 9 Bit8 W 0x02DB A TD0DR5L R [...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 65 0x02F8–0x02FF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x02F8– 0x02FF Reser ved R 00000000 W 0x0300–0x0327 Pulse Width Modulator 8-Bit 8-Channel (PWM) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit [...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 66 F reescale Semiconductor 0x0314 PWMPER0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0315 PWMPER1 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0316 PWMPER2 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0317 PWMPER3 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0318 PWMPER4 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0319 PWMPER5 R Bit 7 6 5 4[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 67 0x0328–0x033F Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0328– 0x033F Reser ved R 00000000 W 0x0340–0x0367 Periodic Interrupt Timer (PIT) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x034[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 68 F reescale Semiconductor 0x0354 PITLD3 (hi) R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 W 0x0355 PITLD3 (lo) R PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W 0x0356 PITCNT3 (hi) R PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 W 0x0357 PITCNT3 (lo) R PCNT7 PCNT6[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 69 0x038D XGIF R XGIF_57 XGIF_56 XGIF_55 XGIF_54 XGIF_53 XGIF_52 XGIF_51 XGIF_50 W 0x038E XGIF R XGIF_4F XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 XGIF_48 W 0x038F XGIF R XGIF_47 XGIF_46 XGIF_45 XGIF_44 XGIF_43 XGIF_42 XGIF_41 XGIF_40 W 0x0[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 70 F reescale Semiconductor 0x03A4 XGR2 (hi) R XGR2[15:8] W 0x03A5 XGR2 (lo) R XGR2[7:0] W 0x03A6 XGR3 (hi) R XGR3[15:8] W 0x03A7 XGR3 (lo) R XGR3[7:0] W 0x03A8 XGR4 (hi) R XGR4[15:8] W 0x03A9 XGR4 (lo) R XGR4[7:0] W 0x03AA XGR5 (hi) R XGR5[15:8] W 0x03AB XGR5(lo) R XGR5[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 71 1.1.7 P ar t ID Assignments The part ID is located in two 8-bit re gisters P AR TIDH and P AR TIDL (addresses 0x001A and 0x001B). The read-only v alue is a unique part ID for each re vision of the chip. T able 1-2 shows the assigned part ID nu[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 72 F reescale Semiconductor Figure 1-5. MC9S12XD-Famil y Pin Assignment 144-Pin LQFP P acka ge SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 CS1/KWJ2/PJ2 A CC2/ADDR22/PK6 IQST A T3/ADDR19/PK3 IQST A T2/ADDR18/PK2 IQST A T1/ADDR17/PK1 IQST A[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 73 Figure 1-6. MC9S12XD-Famil y Pin Assignments 112-Pin LQFP P acka ge V RH V DDA P AD15/AN15 P AD07/AN07 P AD14/AN14 P AD06/AN06 P AD13/AN13 P AD05/AN05 P AD12/AN12 P AD04/AN04 P AD11/AN11 P AD03/AN03 P AD10/AN10 P AD02/AN02 P AD09/AN09 P AD01/A[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 74 F reescale Semiconductor Figure 1-7. MC9S12XD-Famil y Pin Assignments 80-Pin QFP P acka ge 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 MC9S12[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 75 1.2.2 Signal Pr oper ties Summary T able 1-3 summarizes the pin functionality. T able 1-3. Signal Pr oper ties Summary (Sheet 1 of 4) Pin Name Function 1 Pin Name Function 2 Pin Name Function 3 Pin Name Function 4 Pin Name Function 5 P ower Su[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 76 F reescale Semiconductor PH7 KWH7 SS2 TXD5 — V DDR PERH/PPSH Disabled P or t H I/O, interrupt, SS of SPI2, TXD of SCI5 PH6 KWH6 SCK2 RXD5 — V DDR PERH/ PPSH Disabled P or t H I/O, interrupt, SCK of SPI2, RXD of SCI5 PH5 KWH5 MOSI2 TXD4 — V DDR PERH/ PPSH Disable[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 77 PK0 ADDR16 IQST A T0 — — V DDX PUCR Up Extended address, PIPE status PM7 TXCAN3 TXD3 TXCAN4 — V DDX PERM/ PPSM Disabled P or t M I/O, TX of CAN3 and CAN4, TXD of SCI3 PM6 RXCAN3 RXD3 RXCAN4 — V DDX PERM/PPSM Disabled Port M I/O RX of C[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 78 F reescale Semiconductor NO TE For de vices assembled in 80-pin and 112-pin packages all non-bonded out pins should be configured as outputs after reset in order to a void current drawn from floating inputs. Refer to T able 1-3 for af fected pins. 1.2.3 Detailed Sig[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 79 1.2.3.5 XFC — PLL Loop Filter Pin Please ask your Freescale representati ve for the interacti ve application note to compute PLL loop filter elements. Any current leakage on this pin must be a voided. Figure 1-8. PLL Loop Filter Connections[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 80 F reescale Semiconductor 1.2.3.11 PB0 / ADDR0 / UDS / IVD[0] — P or t B I/O Pin 0 PB0 is a general-purpose input or output pin. In MCU expanded modes of operation, this pin is used for the external address b us ADDR0 or as upper data strobe signal. In MCU emulation [...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 81 Figure 1-9. Loop Controlled Pier ce Oscillator Connections (PE7 = 1) Figure 1-10. Full Swing Pierce Oscillator Connections (PE7 = 0) Figure 1-11. External Clock Connections (PE7 = 0) 1.2.3.15 PE6 / MODB / T A GHI — P ort E I/O Pin 6 PE6 is a[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 82 F reescale Semiconductor 1.2.3.16 PE5 / MOD A / T A GLO / RE — P or t E I/O Pin 5 PE5 is a general-purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MOD A bit at the rising edge of RESET.[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 83 1.2.3.23 PH6 / KWH6 / SCK2 / RXD5 — P or t H I/O Pin 6 PH6 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or w ait mode. It can be configured as serial clock pin SCK of [...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 84 F reescale Semiconductor 1.2.3.30 PJ7 / KWJ7 / TXCAN4 / SCL0 / TXCAN0— PORT J I/O Pin 7 PJ7 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or w ait mode. It can be configured as the transmit pin[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 85 maintains the external b us access until the external de vice is ready to capture data (write) or provide data (read). The input voltage threshold for PK7 can be configured to reduced le vels, to allo w data from an external 3.3-V peripheral [...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 86 F reescale Semiconductor 1.2.3.44 PM3 / TXCAN1 / TXCAN0 / SS0 — P or t M I/O Pin 3 PM3 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN of the scalable controller area network controllers 1 or 0 (CAN1 or CAN0). It can be con?[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 87 be configured as master input (during master mode) or slav e output (during slave mode) pin MISO of the serial peripheral interface 2 (SPI2). 1.2.3.52 PP3 / KWP3 / PWM3 / SS1 — P or t P I/O Pin 3 PP3 is a general-purpose input or output pin[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 88 F reescale Semiconductor 1.2.3.59 PS4 / MISO0 — P or t S I/O Pin 4 PS4 is a general-purpose input or output pin. It can be configured as master input (during master mode) or slav e output pin (during slav e mode) MOSI of the serial peripheral interface 0 (SPI0). 1.[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 89 1.2.4.2 V DDR1 , V DDR2 , V SSR1 , V SSR2 — P ower and Gr ound Pins for I/O Driver s and f or Internal V oltage Regulator External po wer and ground for I/O dri vers and input to the internal v oltage regulator. Because fast signal transitio[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 90 F reescale Semiconductor T able 1-4. MC9S12XDP512 P ower and Ground Connection Summary Mnemonic Pin Number Nominal V oltage Description 144-Pin LQFP 112-Pin LQFP 80-Pin QFP V DD1, 2 15, 87 13, 65 9, 49 2.5 V Inter nal power and ground generated b y internal regulator [...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 91 1.3 System Clock Description The clock and reset generator module (CRG) provides the internal clock signals for the core and all peripheral modules. Figure 1-12 shows the clock connections from the CRG to all modules. Consult the CRG Block Use[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 92 F reescale Semiconductor The program Flash memory and the EEPR OM are supplied by the bus clock and the oscillator clock.The oscillator clock is used as a time base to deri ve the program and erase times for the NVM’ s. Consult the FTX512k4 Block Guide and the EETX4[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 93 The configuration of the oscillator can be selected using the XCLKS signal (see T able 1-6 ). For a detailed description please refer to the CRG Block Guide. The logic le vel on the v oltage regulator enable pin V REGEN determines whether the[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 94 F reescale Semiconductor 1.5 Modes of Operation 1.5.1 User Modes 1.5.1.1 Normal Expanded Mode Ports K, A, and B are configured as a 23-bit address bus, ports C and D are configured as a 16-bit data b us, and port E provides b us control and status signals. This mode[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 95 1.5.2.1 System Stop Modes The system stop modes are entered if the CPU ex ecutes the STOP instruction and the XGA TE doesn’t ex ecute a thread and the XGF A CT bit in the XGMCTL register is cleared. Depending on the state of the PSTP bit in [...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 96 F reescale Semiconductor T able 1-8. Interrupt V ector Locations (Sheet 1 of 3) V ector Address 1 XGA TE Channel ID 2 Interrupt Source CCR Mask Local Enable $FFFE — System reset or illegal access reset None None $FFFC — Clock monitor reset None PLLCTL (CME, SCME) [...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 97 V ector base + $BC $5E SPI2 I bit SPI2CR1 (SPIE, SPTIE) V ector base + $BA $5D EEPROM I bit ECNFG (CCIE, CBEIE) V ector base + $B8 $5C FLASH I bit FCNFG (CCIE, CBEIE) V ector base + $B6 $5B CAN0 wak e-up I bit CAN0RIER (WUPIE) V ector base + $[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 98 F reescale Semiconductor 1.6.2 Effects of Reset When a reset occurs, MCU registers and control bits are changed to kno wn start-up states. Refer to the respecti ve module Block Guides for re gister reset states. 1.6.2.1 I/O Pins Refer to the PIM Block Guide for reset [...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 99 1.7 COP Configuration The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge of RESET from the Flash control register FCTL ($0107) located in the Flash EEPR OM block. See T able 1-9 and T able 1-10[...]

Chapter 1 Device Overview (MC9S12XDP512V2) MC9S12XDP512 Data Sheet, Rev . 2.11 100 F reescale Semiconductor Consult the A TD_10B8C Block Guide for information about the analog-to-digital con verter module. When the A TD_10B8C Block Guide refers to freeze mode this is equiv alent to activ e BDM mode. 1.9 A TD1 External T rigger Input Connection The [...]

BookTitle, Rev . 2.4 F reescale Semiconductor 101 Chapter 2 512 Kb yte Flash Module (S12XFTX512K4V2) 2.1 Intr oduction This document describes the FTX512K4 module that includes a 512K Kbyte Flash (non volatile) memory. The Flash memory may be read as either bytes, aligned words or misaligned w ords. Read access time is one bus c ycle for bytes and [...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 102 F reescale Semiconductor • Security feature to pre vent unauthorized access to the Flash memory • Code integrity check using b uilt-in data compression 2.1.3 Modes of Operation Program, erase, erase verify , and data compress operations (please refer to Section 2.4.1, “Flash Com[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 103 Figure 2-1. FTX512K4 Block Dia gram 2.2 External Signal Description The Flash module contains no signals that connect of f-chip. FTX512K4 Flash Block 0 64K * 16 Bits Flash Block 1 64K * 16 Bits Flash Block 2 64K * 16 Bits 64K * 16 Bits Flash Block 3 sector 0 s[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 104 F reescale Semiconductor 2.3 Memor y Map and Register Definition This section describes the memory map and registers for the Flash module. 2.3.1 Module Memory Map The Flash memory map is sho wn in Figure 2-2 . The HCS12X architecture places the Flash memory addresses between global a[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 105 Figure 2-2. Flash Memory Map Flash Registers Flash Configuration Field 0x7F_C000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x7F_8000 0x7F_9000 0x7F_8400 0x7F_8800 0x7F_A000 FLASH END = 0x7F_FFFF 0x7F_F800 0x7F_F000 0x7F_E000 Flash Protected/U[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 106 F reescale Semiconductor The Flash module also contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is gi ven in T able 2-2 while their accessibility is detailed in Section 2.3.2, “Re gister Descri[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 107 2.3.2 Register Descriptions Register Name Bit 7 654321 Bit 0 0x0000 FCLKDIV R FDIVLD PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 W 0x0001 FSEC R KEYEN RNV5 RNV4 RNV3 RNV2 SEC W 0x0002 FTSTMOD R0 MRDS 00000 W 0x0003 FCNFG R CBEIE CCIE KEY A CC 00000 W 0x0004 FPR[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 108 F reescale Semiconductor 2.3.2.1 Flash Cloc k Divider Register (FCLKDIV) The FCLKDIV register is used to control timed e vents in program and erase algorithms. All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable. 0x000D RESER VED2 R 0000000[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 109 2.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. All bits in the FSEC register are readable b ut are not writable. The FSEC register is loaded from the Flash Configuration Field [...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 110 F reescale Semiconductor 2.3.2.3 Flash T est Mode Register (FTSTMOD) The FTSTMOD register is used to control Flash test features. MRDS bits are readable and writable while all remaining bits read 0 and are not writable in normal mode. The WRALL bit is writable only in special mode to [...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 111 2.3.2.4 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash interrupts and g ates the security backdoor writes. CBEIE, CCIE and KEY A CC bits are readable and writable while all remaining bits read 0 and are not writable in normal mode. [...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 112 F reescale Semiconductor 2.3.2.5 Flash Pr otection Register (FPRO T) The FPROT register defines which Flash sectors are protected against program or erase operations. All bits in the FPR O T register are readable and writable with restrictions (see Section 2.3.2.5.1, “Flash Protecti[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 113 5 FPHDIS Flash Protection Higher Ad dress Range Disable — The FPHDIS bit deter mines whether there is a protected/unprotected area in a specific region of the Flash memor y ending with global address 0x7F_FFFF. 0 Protection/Unprotection enabled. 1 Protectio[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 114 F reescale Semiconductor All possible Flash protection scenarios are sho wn in Figure 2-11 . Although the protection scheme is loaded from the Flash array at global address 0x7F_FF0D during the reset sequence, it can be changed by the user. This protection scheme can be used by applic[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 115 Figure 2-11. Flash Protection Scenarios 7654 3210 FPHDIS=1 FPLDIS=1 FPHDIS=1 FPLDIS=0 FPHDIS=0 FPLDIS=1 FPHDIS=0 FPLDIS=0 Scenario Scenario Unprotected region Protected region with size Protected region Protected region with size defined by FPLS defined by FPH[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 116 F reescale Semiconductor 2.3.2.5.1 Flash Protection Restrictions The general guideline is that Flash protection can only be added and not remov ed. T able 2-15 specifies all v alid transitions between Flash protection scenarios. Any attempt to write an in valid scenario to the FPR O [...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 117 CBEIF , PVIOL, and A CCERR are readable and writable, CCIF and BLANK are readable and not writable, remaining bits read 0 and are not writable in normal mode. F AIL is readable and writable in special mode. F AIL must be clear in special mode when starting a c[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 118 F reescale Semiconductor 2.3.2.7 Flash Command Register (FCMD) The FCMD register is the Flash command register. All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable. 2.3.2.8 Flash Contr ol Register (FCTL) The FCTL register is [...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 119 All bits in the FCTL register are readable b ut are not writable. The FCTL register is loaded from the Flash Configuration Field byte at global address 0x7F_FF0E during the reset sequence, indicated by F in Figure 2-15 . 2.3.2.9 Flash Address Register s (F AD[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 120 F reescale Semiconductor All FD A T AHI and FD A T ALO bits are readable b ut are not writable. At the completion of a data compress operation, the resulting 16-bit signature is stored in the FD A T A registers. The data compression signature is readable in the FD A T A registers unti[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 121 All bits read 0 and are not writable. 2.3.2.13 RESER VED3 This register is reserv ed for factory testing and is not accessible. All bits read 0 and are not writable. 2.3.2.14 RESER VED4 This register is reserv ed for factory testing and is not accessible. All [...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 122 F reescale Semiconductor 2.4 Functional Description 2.4.1 Flash Command Operations Write operations are used to ex ecute program, erase, erase verify , erase abort, and data compress algorithms described in this section. The program and erase algorithms are controlled by a state machi[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 123 182kHz. In this case, the Flash program and erase algorithm timings are increased ov er the optimum target by: CA UTION Program and erase command ex ecution time will increase proportionally with the period of FCLK. Because of the impact of clock synchronizati[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 124 F reescale Semiconductor Figure 2-24. Determination Procedure f or PRDIV8 and FDIV Bits PRDIV8=1 yes no PRDIV8=0 (reset) 12.8MHz? FCLK=(PRDCLK)/(1+FDIV[5:0]) PRDCLK=oscillator_clock PRDCLK=oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[ µ s]) no FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[ µ s])-1 yes ST[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 125 2.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to ex ecute program, erase, erase verify , erase abort, and data compress algorithms. Before starting a command write sequence, the A CCERR and PVIOL ?[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 126 F reescale Semiconductor CA UTION A Flash word must be in the erased state before being programmed. Cumulati ve programming of bits within a Flash w ord is not allo wed. 0x06 Data Compress Compress data from a selected por tion of the Flash bloc k. The resulting signature is stored in[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 127 2.4.2.1 Erase V erify Command The erase verify operation will v erify that a Flash block is erased. An example flo w to execute the erase v erify operation is shown in Figure 2-25 . The erase v erify command write sequence is as follo ws: 1. Write to a Flash [...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 128 F reescale Semiconductor Figure 2-25. Example Erase V erify Command Flow Write: Flash Block Address Write: FCMD register Erase V erify Command 0x05 Write: FST A T register Clear CBEIF 0x80 1. 2. 3. Clear ACCERR/PVIOL 0x30 Write: FST A T register yes no Access Error and Protection Viol[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 129 2.4.2.2 Data Compress Command The data compress operation will check Flash code integrity by compressing data from a selected portion of the Flash memory into a signature analyzer. An example flo w to ex ecute the data compress operation is sho wn in Figure 2[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 130 F reescale Semiconductor Figure 2-26. Example Data Compress Command Flow Write: Flash Address to star t Write: FCMD register Data Compress Command 0x06 Write: FST A T register Clear CBEIF 0x80 1. 2. 3. Clear ACCERR/PVIOL 0x30 Write: FST A T register yes no Access Error and Protection [...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 131 2.4.2.2.1 Data Compress Operation The Flash module contains a 16-bit multiple-input signature register (MISR) for each Flash block to generate a 16-bit signature based on selected Flash array data. If multiple Flash blocks are selected for simultaneous compres[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 132 F reescale Semiconductor 2.4.2.3 Pr ogram Command The program operation will program a pre viously erased word in the Flash memory using an embedded algorithm. An example flo w to execute the program operation is sho wn in Figure 2-28 . The program command write sequence is as follo [...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 133 Figure 2-28. Example Program Command Flo w Write: Flash Address Write: FCMD register Program Command 0x20 Write: FST A T register Clear CBEIF 0x80 1. 2. 3. Clear ACCERR/PVIOL 0x30 Write: FST A T register yes no Access Error and Protection Violation no and prog[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 134 F reescale Semiconductor 2.4.2.4 Sector Erase Command The sector erase operation will erase all addresses in a 1 Kbyte sector of Flash memory using an embedded algorithm. An example flo w to ex ecute the sector erase operation is shown in Figure 2-29 . The sector erase command write [...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 135 Figure 2-29. Example Sector Erase Command Flow Write: Flash Sector Address Write: FCMD register Sector Erase Command 0x40 Write: FST A T register Clear CBEIF 0x80 1. 2. 3. Clear ACCERR/PVIOL 0x30 Write: FST A T register yes no Access Error and Protection Viola[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 136 F reescale Semiconductor 2.4.2.5 Mass Erase Command The mass erase operation will erase all addresses in a Flash block using an embedded algorithm. An example flo w to ex ecute the mass erase operation is shown in Figure 2-30 . The mass erase command write sequence is as follo ws: 1.[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 137 Figure 2-30. Example Mass Erase Command Flow Write: Flash Block Address Write: FCMD register Mass Erase Command 0x41 Write: FST A T register Clear CBEIF 0x80 1. 2. 3. Clear ACCERR/PVIOL 0x30 Write: FST A T register yes no Access Error and Protection Violation [...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 138 F reescale Semiconductor 2.4.2.6 Sector Erase Abor t Command The sector erase abort operation will terminate the acti ve sector erase operation so that other sectors in a Flash block are av ailable for read and program operations without waiting for the sector erase operation to compl[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 139 Figure 2-31. Example Sector Erase Abort Command Flow Write: Dummy Flash Address Write: FCMD register Sector Erase Abor t Cmd 0x47 Write: FST A T register Clear CBEIF 0x80 1. 2. 3. Read: FST A T register and Dummy Data Bit P olling for Command Completion Check [...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 140 F reescale Semiconductor 2.4.3 Illegal Flash Operations The A CCERR flag will be set during the command write sequence if any of the follo wing illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to a Flash address before initializing the [...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 141 If the PVIOL flag is set in the FST A T register , the user must clear the PVIOL flag before starting another command write sequence (see Section 2.3.2.6, “Flash Status Register (FST A T)” ). 2.5 Operating Modes 2.5.1 W ait Mode If a command is acti ve ([...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 142 F reescale Semiconductor 2.6.1 Unsecuring the MCU using Bac kdoor Ke y Access The MCU may be unsecured by using the backdoor ke y access feature which requires kno wledge of the contents of the backdoor ke ys (four 16-bit words programmed at addresses 0x7F_FF00–0x7F_FF07). If the KE[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 F reescale Semiconductor 143 unaf fected by the backdoor ke y access sequence. After the next reset of the MCU, the security state of the Flash module is determined by the Flash security byte (0x7F_FF0F). The backdoor ke y access sequence has no ef fect on the program and erase protection[...]

512 Kbyte Flash Module (S12XFTX512K4V2) BookTitle, Rev . 2.4 144 F reescale Semiconductor NO TE V ector addresses and their relativ e interrupt priority are determined at the MCU le vel. 2.8.1 Description of Flash Interrupt Operation The logic used for generating interrupts is sho wn in Figure 2-32 . The Flash module uses the CBEIF and CCIF flags [...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 145 Chapter 3 4 Kb yte EEPROM Module (S12XEETX4KV2) 3.1 Intr oduction This document describes the module which includes a Kbyte EEPR OM (non volatile) memory. The EEPR OM memory may be read as either bytes, aligned words, or misaligned words. Read access time is one bus c ycle for bytes a[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 146 F reescale Semiconductor 3.1.4 Bloc k Diagram A block diagram of the EEPR OM module is shown in . 3.2 External Signal Description The EEPR OM module contains no signals that connect off-chip. 3.3 Memor y Map and Register Definition This section describes the me[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 147 The EEPR OM module also contains a set of 12 control and status registers located between EEPR OM module base + 0x0000 and 0x000B. A summary of the EEPR OM module registers is gi ven in T able 3-2 while their accessibility is detailed in[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 148 F reescale Semiconductor 3.3.2 Register Descriptions 3.3.2.1 EEPR OM Clock Divider Register (ECLKDIV) The ECLKDIV register is used to control timed e vents in program and erase algorithms. Register Name Bit 7 654321 Bit 0 0x0000 ECLKDIV R EDIVLD PRDIV8 EDIV5 EDI[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 149 All bits in the ECLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable. 3.3.2.2 RESER VED1 This register is reserv ed for factory testing and is not accessible. All bits read 0 and are not writable. 3.3.2.3 RE[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 150 F reescale Semiconductor All bits read 0 and are not writable. 3.3.2.4 EEPR OM Configuration Register (ECNFG) The ECNFG register enables the EEPR OM interrupts. CBEIE and CCIE bits are readable and writable while all remaining bits read 0 and are not writable. [...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 151 3.3.2.5 EEPR OM Protection Register (EPR O T) The EPR O T register defines which EEPR OM sectors are protected against program or erase operations. During the reset sequence, the EPR O T register is loaded from the EEPR OM Protection by[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 152 F reescale Semiconductor 3.3.2.6 EEPR OM Status Register (EST A T) The EST A T register defines the operational status of the module. CBEIF , PVIOL, and A CCERR are readable and writable, CCIF and BLANK are readable and not writable, remaining bits read 0 and a[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 153 T able 3-7. EST A T Field Descriptions Field Description 7 CBEIF Command Buffer Empty Interrupt Flag — The CBEIF flag indicates that the address , data, and command buff ers are empty so that a new command write sequence can be star t[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 154 F reescale Semiconductor 3.3.2.7 EEPR OM Command Register (ECMD) The ECMD register is the EEPR OM command register. All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable. 3.3.2.8 RESER VED3 This register [...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 155 All bits read 0 and are not writable. EEPROM Address Registers (EADDR) The EADDRHI and EADDRLO registers are the EEPR OM address registers. All EABHI and EABLO bits read 0 and are not writable in normal modes. All EABHI and EABLO bits ar[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 156 F reescale Semiconductor 3.4 Functional Description 3.4.1 EEPR OM Command Operations Write operations are used to ex ecute program, erase, erase verify , sector erase abort, and sector modify algorithms described in this section. The program, erase, and sector m[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 157 CA UTION Program and erase command ex ecution time will increase proportionally with the period of EECLK. Because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the EEPR OM memory[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 158 F reescale Semiconductor Figure 3-14. Determination Procedure f or PRDIV8 and EDIV Bits PRDIV8 = 1 yes no PRDIV8 = 0 (reset) >12.8 MHz? EECLK = (PRDCLK)/(1+EDIV[5:0]) PRDCLK = oscillator_clock PRDCLK = oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[ µ s]) no EDIV[5:[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 159 3.4.1.2 Command Write Sequence The EEPR OM command controller is used to supervise the command write sequence to execute program, erase, erase verify , sector erase abort, and sector modify algorithms. Before starting a command write seq[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 160 F reescale Semiconductor CA UTION An EEPR OM word (2 bytes) must be in the erased state before being programmed. Cumulati ve programming of bits within a w ord is not allowed. 0x41 Mass Erase Erase all memory bytes in the EEPROM b lock. A mass erase of the full [...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 161 3.4.2.1 Erase V erify Command The erase verify operation will v erify that the EEPR OM memory is erased. An example flo w to execute the erase v erify operation is shown in Figure 3-15 . The erase v erify command write sequence is as fo[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 162 F reescale Semiconductor Figure 3-15. Example Erase V erify Command Flow Write: EEPROM Address Write: ECMD register Erase V erify Command 0x05 Write: EST A T register Clear CBEIF 0x80 1. 2. 3. Clear ACCERR/PVIOL 0x30 Write: EST A T register yes no Access Error a[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 163 3.4.2.2 Pr ogram Command The program operation will program a pre viously erased word in the EEPR OM memory using an embedded algorithm. An example flo w to execute the program operation is sho wn in Figure 3-16 . The program command wr[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 164 F reescale Semiconductor Figure 3-16. Example Program Command Flo w Write: EEPROM Address Write: ECMD register Program Command 0x20 Write: EST A T register Clear CBEIF 0x80 1. 2. 3. Clear ACCERR/PVIOL 0x30 Write: EST A T register yes no Access Error and Protecti[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 165 3.4.2.3 Sector Erase Command The sector erase operation will erase both words in a sector of EEPR OM memory using an embedded algorithm. An example flo w to ex ecute the sector erase operation is shown in Figure 3-17 . The sector erase [...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 166 F reescale Semiconductor Figure 3-17. Example Sector Erase Command Flow Write: EEPROM Sector Address Write: ECMD register Sector Erase Command 0x40 Write: EST A T register Clear CBEIF 0x80 1. 2. 3. Clear ACCERR/PVIOL 0x30 Write: EST A T register yes no Access Er[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 167 3.4.2.4 Mass Erase Command The mass erase operation will erase all addresses in an EEPR OM block using an embedded algorithm. An example flo w to ex ecute the mass erase operation is shown in Figure 3-18 . The mass erase command write s[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 168 F reescale Semiconductor Figure 3-18. Example Mass Erase Command Flow Write: EEPROM Address Write: ECMD register Mass Erase Command 0x41 Write: EST A T register Clear CBEIF 0x80 1. 2. 3. Clear ACCERR/PVIOL 0x30 Write: EST A T register yes no Access Error and Pro[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 169 3.4.2.5 Sector Erase Abor t Command The sector erase abort operation will terminate the acti ve sector erase or sector modify operation so that other sectors in an EEPR OM block are av ailable for read and program operations without wait[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 170 F reescale Semiconductor Figure 3-19. Example Sector Erase Abort Command Flow Write: Dummy EEPROM Address Write: ECMD register Sector Erase Abort Cmd 0x47 Write: EST A T register Clear CBEIF 0x80 1. 2. 3. Read: EST A T register and Dummy Data Bit P olling for Co[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 171 3.4.2.6 Sector Modify Command The sector modify operation will erase both words in a sector of EEPR OM memory followed by a reprogram of the addressed word using an embedded algorithm. An example flo w to ex ecute the sector modify oper[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 172 F reescale Semiconductor Figure 3-20. Example Sector Modify Command Flow Write: EEPROM W ord Address Write: ECMD register Sector Modify Command 0x60 Write: EST A T register Clear CBEIF 0x80 1. 2. 3. Clear ACCERR/PVIOL 0x30 Write: EST A T register yes no Access E[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 173 3.4.3 Illegal EEPR OM Operations The A CCERR flag will be set during the command write sequence if any of the follo wing illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to an EEPR OM addr[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 174 F reescale Semiconductor 3.5 Operating Modes 3.5.1 W ait Mode If a command is acti ve (CCIF = 0) when the MCU enters the w ait mode, the acti ve command and an y buf fered command will be completed. The EEPR OM module can recover the MCU from wait mode if the CB[...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 175 3.6.1 Unsecuring the MCU in Special Single Chip Mode using BDM Before the MCU can be unsecured in special single chip mode, the EEPR OM memory must be erased using the follo wing method : • Reset the MCU into special single chip mode, [...]

Chapter 3 4 Kbyte EEPR OM Module (S12XEETX4KV2) MC9S12XDP512 Data Sheet, Rev . 2.11 176 F reescale Semiconductor 3.8.1 Description of EEPR OM Interrupt Operation The logic used for generating interrupts is sho wn in Figure 3-21 . The EEPR OM module uses the CBEIF and CCIF flags in combination with the CBIE and CCIE enable bits to generate the EEPR[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 177 Chapter 4 P or t Integration Module (S12XDP512PIMV2) 4.1 Intr oduction The S12XD family port inte gration module (belo w referred to as PIM) establishes the interface between the peripheral modules including the non-multiplex ed external b us interface module (S12X_EBI) and the I/O pi[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 178 F reescale Semiconductor 4.1.1 Features A full-featured PIM module includes these distinctive registers: • Data and data direction registers for Ports A, B, C, D, E, K, T, S, M, P, H, J, AD0, and AD1 when used as general-purpose I/O • Control registers t[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 179 Figure 4-1. MC9S12XDP512 Block Dia gram Po r t T PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 ECT IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 Po r t P PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PWM PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 Po r t S PS0 PS1 PS2 PS[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 180 F reescale Semiconductor 4.2 External Signal Description This section lists and describes the signals that do connect off-chip. 4.2.1 Signal Pr oper ties Table 4-1 shows all the pins and their functions that are controlled by the MC9S12XDP512. Refer to Secti[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 181 E PE[7] XCLKS 1 I Exter nal clock selection input during RESET Mode dependent 3 ECLKX2 I F ree-running clock output at Core Clock r ate (ECLK x 2) GPIO I/O General-purpose I/O PE[6] MODB 1 I MODB input dur ing RESET T AGHI I Instr uc[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 182 F reescale Semiconductor K PK[7] ROMCTL 1 I ROMON bit control input during RESET Mode dependent 3 EW AIT I External Wait signal Configurab le for reduced input threshold GPIO I/O General-purpose I/O PK[6:4] ADDR[22:20] mux A CC[2:0] 2 O Extended e xter nal [...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 183 M PM7 TXCAN3 O MSCAN3 transmit pin GPIO TXCAN4 O MSCAN4 transmit pin TXD3 O Ser ial Communication Interf ace 3 transmit pin GPIO I/O General-purpose I/O PM6 RXCAN3 I MSCAN3 receiv e pin RXCAN4 I MSCAN4 receiv e pin RXD3 I Serial Comm[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 184 F reescale Semiconductor P PP7 PWM7 I/O Pulse Width Modulator input/output channel 7 GPIO SCK2 I/O Serial Peripheral Interf ace 2 ser ial clock pin GPIO/KWP7 I/O General-pur pose I/O with interrupt PP6 PWM6 O Pulse Width Modulator output channel 6 SS2 I/O Se[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 185 H PH7 SS2 I/O Serial Peripheral Interf ace 2 slav e select output in master mode, input f or slave mode or master mode GPIO TXD5 O Ser ial Communication Interf ace 5 transmit pin GPIO/KWH7 I/O General-purpose I/O with interrupt PH6 S[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 186 F reescale Semiconductor J PJ7 TXCAN4 O MSCAN4 transmit pin GPIO SCL0 O Inter Integ rated Circuit 0 serial clock line TXCAN0 O MSCAN0 transmit pin GPIO/KWJ7 I/O General-purpose I/O with interr upt PJ6 RXCAN4 I MSCAN4 receiv e pin SD A0 I/O Inter Integrated C[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 187 4.3 Memor y Map and Register Definition This section provides a detailed description of all MC9S12XDP512 registers. 4.3.1 Module Memory Map Table 4-2 shows the register map of the port integration module. T able 4-2. PIM Memory Map [...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 188 F reescale Semiconductor 0x0241 P or t T Input Register (PTIT) Read 0x0242 P or t T Data Direction Register (DDRT) Read / Write 0x0243 P or t T Reduced Drive Register (RDR T) Read / Write 0x0244 P or t T Pull Device Enab le Register (PERT) Read / Write 0x024[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 189 0x0264 P or t H Pull Device Enab le Register (PERH) Read / Write 0x0265 P or t H P olar ity Select Register (PPSH) Read / Write 0x0266 P or t H Interrupt Enable Register (PIEH) Read / Write 0x0267 P or t H Interrupt Flag Register (PI[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 190 F reescale Semiconductor 4.3.2 Register Descriptions Table 4-3 summarizes the effect on the various configuration bits, data direction (DDR), output level (IO), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the ports.[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 191 Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 POR T A R P A7 P A6 P A5 P A4 P A3 P A2 P A1 P A0 W 0x0001 POR TB R PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 W 0x0002 DDRA R DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 W 0x0003 DDRB R DDRB7 DD[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 192 F reescale Semiconductor 0x000E– 0x001B Non-PIM Address Range R Non-PIM Address Range W 0x001C ECLKCTL R NECLK NCLKX2 0000 EDIV1 EDIV0 W 0x001D Reser ved R 00000000 W 0x001E IRQCR R IRQE IRQEN 000000 W 0x001F Reser ved R 00000000 W 0x0020– 0x0031 Non-PIM[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 193 0x0244 PER T R PER T7 PERT6 PER T5 PERT4 PER T3 PERT2 PER T1 PERT0 W 0x0245 PPST R PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 W 0x0246 Reser ved R 00000000 W 0x0247 Reser ved R 00000000 W 0x0248 PTS R PTS7 PTS6 PTS5 PTS4 PTS3 PT[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 194 F reescale Semiconductor 0x0253 RDRM R RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0 W 0x0254 PERM R PERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0 W 0x0255 PPSM R PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0 W 0x0256 WOMM R WOMM7 W OMM6 WOMM5 WOMM4 W [...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 195 0x0262 DDRH R DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 W 0x0263 RDRH R RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0 W 0x0264 PERH R PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0 W 0x0265 PPSH R PPSH7 PPSH6 PPSH5 PPSH4 PPS[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 196 F reescale Semiconductor 0x0271 PT1AD0 R PT1AD07 PT1AD06 PT1AD05 PT1AD04 PT1AD03 PT1AD02 PT1AD01 PT1AD00 W 0x0272 Reser ved R 00000000 W 0x0273 Name R DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00 W 0x0274 Reser ved R 00000000 W 0x0[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 197 4.3.2.1 P or t A Data Register (PORT A) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In em[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 198 F reescale Semiconductor Write: Anytime. In emulation modes, write operations will also be directed to the external bus. T able 4-5. POR TB Field Descriptions Field Description 7–0 PB[7:0] Po r t B — P or t B pins 7–0 are associated with address output[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 199 4.3.2.3 P or t A Data Direction Register (DDRA) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime. In emulation mode[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 200 F reescale Semiconductor T able 4-7. DDRB Field Descriptions Field Description 7–0 DDRB[7:0] Data Direction P or t B — This register controls the data direction for por t B. When Port B is operating as a general purpose I/O port, DDRB determines whether [...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 201 4.3.2.5 P or t C Data Register (PORTC) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emu[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 202 F reescale Semiconductor 4.3.2.7 P or t C Data Direction Register (DDRC) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime. In emulation mode[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 203 T able 4-11. DDRD Field Descriptions Field Description 7–0 DDRD[7:0] Data Direction P or t D — This register controls the data direction for por t D. When Port D is operating as a general purpose I/O port, DDRD determines whether[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 204 F reescale Semiconductor 4.3.2.9 P or t E Data Register (PORTE) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emu[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 205 4.3.2.10 P or t E Data Direction Register (DDRE) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime. In emulation mod[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 206 F reescale Semiconductor 4.3.2.11 S12X_EBI P or ts, BKGD, VREGEN Pin Pull-up Contr ol Register (PUCR) Read: Anytime in single-chip modes. Write: Anytime, except BKPUE which is writable in special test mode only. This register is used to enable pull-up device[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 207 4.3.2.12 S12X_EBI P or ts Reduced Drive Register (RDRIV) Read: Anytime. In emulation modes, read operations will return the data from the e xternal bus, in all other modes the data are read from this register. Write: Anytime. In emul[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 208 F reescale Semiconductor 4.3.2.13 ECLK Control Register (ECLKCTL) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime. In emulation modes, writ[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 209 4.3.2.14 IRQ Control Register (IRQCR) Read: See individual bit descriptions below. Write: See individual bit descriptions below. 6 NCLKX2 No ECLKX2 — This bit controls the av ailability of a free-r unning clock on the ECLKX2 pin. T[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 210 F reescale Semiconductor T able 4-18. IRQCR Field Descriptions Field Description 7 IRQE IRQ Select Edge Sensitive Only Special modes: Read or write anytime. Normal and emulation modes: Read anytime, write once. 0 IRQ configured f or low le vel recognition. [...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 211 4.3.2.15 P or t K Data Register (PORTK) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In em[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 212 F reescale Semiconductor T able 4-20. DDRK Field Descriptions Field Description 7–0 DDRK[7:0] Data Direction P or t K 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it ca[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 213 4.3.2.17 P or t T Data Register (PTT) Read: Anytime. Write: Anytime. 4.3.2.18 P or t T Input Register (PTIT) Read: Anytime. Write: Never, writes to this register have no effect. 0x0240 76543210 R PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PT[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 214 F reescale Semiconductor 4.3.2.19 P or t T Data Direction Register (DDRT) Read: Anytime. Write: Anytime. This register configures each port T pin as either input or output. The ECT forces the I/O state to be an output for each timer port associated with an [...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 215 4.3.2.20 P or t T Reduced Drive Register (RDRT) Read: Anytime. Write: Anytime. This register configures the drive strength of each port T output pin as either full or reduced. If the port is used as input this bit is ignored. 4.3.2.2[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 216 F reescale Semiconductor 4.3.2.22 P or t T P olarity Select Register (PPST) Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin. 4.3.2.23 P or t S Data Register (PTS) Read: Anytime. Write: Anyt[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 217 If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read.[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 218 F reescale Semiconductor 4.3.2.24 P or t S Input Register (PTIS) Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the buffered state of the associated pins. This also can be used to detect overload or short[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 219 4.3.2.25 P or t S Data Direction Register (DDRS) Read: Anytime. Write: Anytime. This register configures each port S pin as either input or output. If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for d[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 220 F reescale Semiconductor 4.3.2.26 P or t S Reduced Drive Register (RDRS) Read: Anytime. Write: Anytime. This register configures the drive strength of each port S output pin as either full or reduced. If the port is used as input this bit is ignored. 4.3.2.2[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 221 4.3.2.28 P or t S P olarity Select Register (PPSS) Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin. 4.3.2.29 P or t S Wired-OR Mode Register (WOMS) Read: Anytime. W[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 222 F reescale Semiconductor 4.3.2.30 P or t M Data Register (PTM) Read: Anytime. Write: Anytime. Port M pins 75–0 are associated with the CAN0, CAN1, CAN2, CAN3, SCI3, as well as the routed CAN0, CAN4, and SPI0 modules. When not used with any of the periphera[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 223 3–2 PTM[3:2] The CAN1 function (TXCAN1 and RXCAN1) takes precedence o ver the routed CAN0, the routed SPI0 and the general purpose I/O function if the CAN1 module is enabled. The routed CAN0 function (TXCAN0 and RXCAN0) takes prece[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 224 F reescale Semiconductor 4.3.2.31 P or t M Input Register (PTIM) Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 225 4.3.2.32 P or t M Data Direction Register (DDRM) Read: Anytime. Write: Anytime. This register configures each port M pin as either input or output. The CAN/SCI3 forces the I/O state to be an output for each port line associated with [...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 226 F reescale Semiconductor 4.3.2.33 P or t M Reduced Drive Register (RDRM) Read: Anytime. Write: Anytime. This register configures the drive strength of each Port M output pin as either full or reduced. If the port is used as input this bit is ignored. 4.3.2.3[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 227 4.3.2.35 P or t M P olarity Select Register (PPSM) Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin. If CAN is active a pull-up device can be activated on the RXCAN[[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 228 F reescale Semiconductor T able 4-37. W OMM Field Descriptions Field Description 7–0 WOMM[7:0] Wired-OR Mode P or t M 0 Output buffers oper ate as push-pull outputs. 1 Output buffers oper ate as open-drain outputs.[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 229 4.3.2.37 Module Routing Register (MODRR) Read: Anytime. Write: Anytime. This register configures the re-routing of CAN0, CAN4, SPI0, SPI1, and SPI2 on alternative ports. 0x0257 76543210 R0 MODRR6 MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MO[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 230 F reescale Semiconductor 4.3.2.38 P or t P Data Register (PTP) Read: Anytime. Write: Anytime. Port P pins 7, and 5–0 are associated with the PWM as well as the SPI1 and SPI2 modules. These pins can be used as general purpose I/O when not used with any of t[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 231 4.3.2.39 P or t P Input Register (PTIP) Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 232 F reescale Semiconductor 4.3.2.40 P or t P Data Direction Register (DDRP) Read: Anytime. Write: Anytime. This register configures each port P pin as either input or output. If the associated PWM channel or SPI module is enabled this register has no effect on[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 233 4.3.2.41 P or t P Reduced Drive Register (RDRP) Read: Anytime. Write: Anytime. This register configures the drive strength of each port P output pin as either full or reduced. If the port is used as input this bit is ignored. 4.3.2.4[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 234 F reescale Semiconductor 4.3.2.43 P or t P P olarity Select Register (PPSP) Read: Anytime. Write: Anytime. This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enable[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 235 T able 4-43. PIEP Field Descriptions Field Description 7–0 PIEP[7:0] Interrupt Enable P or t P 0 Interr upt is disabled (interrupt flag masked). 1 Interr upt is enabled.[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 236 F reescale Semiconductor 4.3.2.45 P or t P Interrupt Flag Register (PIFP) Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSP register. To clea[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 237 4.3.2.46 P or t H Data Register (PTH) Read: Anytime. Write: Anytime. Port H pins 7–0 are associated with the SCI4 and SCI5 as well as the routed SPI1 and SPI2 modules. These pins can be used as general purpose I/O when not used wit[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 238 F reescale Semiconductor 4.3.2.47 P or t H Input Register (PTIH) Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 239 4.3.2.48 P or t H Data Direction Register (DDRH) Read: Anytime. Write: Anytime. This register configures each port H pin as either input or output. If the associated SCI channel or routed SPI module is enabled this register has no ef[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 240 F reescale Semiconductor 4.3.2.49 P or t H Reduced Drive Register (RDRH) Read: Anytime. Write: Anytime. This register configures the drive strength of each Port H output pin as either full or reduced. If the port is used as input this bit is ignored. 4.3.2.5[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 241 4.3.2.51 P or t H P olarity Select Register (PPSH) Read: Anytime. Write: Anytime. This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enable[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 242 F reescale Semiconductor T able 4-49. PIEH Field Descriptions Field Description 7–0 PIEH[7:0] Interrupt Enable P or t H 0 Interr upt is disabled (interrupt flag masked). 1 Interr upt is enabled.[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 243 4.3.2.53 P or t H Interrupt Flag Register (PIFH) Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSH register. To clea[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 244 F reescale Semiconductor 4.3.2.54 P or t J Data Register (PTJ) Read: Anytime. Write: Anytime. Port J pins 7–4 and 2–0 are associated with the CAN4, SCI2, IIC0 and IIC1, the routed CAN0 modules and chip select signals ( CS0, CS1, CS2, CS3). These pins can[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 245 1 PJ1 The SCI2 function takes precedence o ver the gener al pur pose I/O function if the SCI2 module is enabled. Ref er to SCI section f or details. 0 PJ0 The SCI2 function takes precedence o ver the chip select ( CS3) and the gener [...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 246 F reescale Semiconductor 4.3.2.55 P or t J Input Register (PTIJ) Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the buffered state of the associated pins. This can be used to detect overload or short circ[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 247 4.3.2.56 P or t J Data Direction Register (DDRJ) Read: Anytime. Write: Anytime. This register configures each port J pin as either input or output. The CAN forces the I/O state to be an output on PJ7 (TXCAN4) and an input on pin PJ6 [...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 248 F reescale Semiconductor 4.3.2.57 P or t J Reduced Drive Register (RDRJ) Read: Anytime. Write: Anytime. This register configures the drive strength of each port J output pin as either full or reduced. If the port is used as input this bit is ignored. 4.3.2.5[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 249 T able 4-54. PERJ Field Descriptions Field Description 7–0 PERJ[7:4] PERJ[2:0] Pull Device Enable P ort J 0 Pull-up or pull-down device is disab led. 1 Either a pull-up or pull-down device is enab led.[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 250 F reescale Semiconductor 4.3.2.59 P or t J P olarity Select Register (PPSJ) Read: Anytime. Write: Anytime. This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enable[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 251 T able 4-56. PIEJ Field Descriptions Field Description 7–0 PIEJ[7:4] PIEJ[2:0] Interrupt Enable P or t J 0 Interr upt is disabled (interrupt flag masked). 1 Interr upt is enabled.[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 252 F reescale Semiconductor 4.3.2.61 P or t J Interrupt Flag Register (PIFJ) Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSJ register. To clea[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 253 4.3.2.63 P or t AD0 Data Direction Register 1 (DDR1AD0) Read: Anytime. Write: Anytime. This register configures pins PAD[07:00] as either input or output. 0x0273 76543210 R DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 254 F reescale Semiconductor 4.3.2.64 P or t AD0 Reduced Drive Register 1 (RDR1AD0) Read: Anytime. Write: Anytime. This register configures the drive strength of each output pin PAD[07:00] as either full or reduced. If the port is used as input this bit is ignor[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 255 4.3.2.66 P or t AD1 Data Register 0 (PT0AD1) Read: Anytime. Write: Anytime. This register is associated with AD1 pins PAD[23:16]. These pins can also be used as general purpose I/O. If the data direction bits of the associated I/O pi[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 256 F reescale Semiconductor 4.3.2.68 P or t AD1 Data Direction Register 0 (DDR0AD1) Read: Anytime. Write: Anytime. This register configures pin PAD[23:16] as either input or output. 0x027A 76543210 R DDR0AD123 DDR0AD122 DDR0AD121 DDR0AD120 DDR0AD119 DDR0AD118 D[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 257 4.3.2.69 P or t AD1 Data Direction Register 1 (DDR1AD1) Read: Anytime. Write: Anytime. This register configures pins PAD[15:08] as either input or output. 0x027B 76543210 R DDR1AD115 DDR1AD114 DDR1AD113 DDR1AD112 DDR1AD111 DDR1AD110 [...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 258 F reescale Semiconductor 4.3.2.70 P or t AD1 Reduced Drive Register 0 (RDR0AD1) Read: Anytime. Write: Anytime. This register configures the drive strength of each PAD[23:16] output pin as either full or reduced. If the port is used as input this bit is ignor[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 259 4.3.2.72 P or t AD1 Pull Up Enable Register 0 (PER0AD1) Read: Anytime. Write: Anytime. This register activates a pull-up device on the respective PAD[23:16] pin if the port is used as input. This bit has no effect if the port is used[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 260 F reescale Semiconductor 4.4 Functional Description Each pin except PE0, PE1, and BKGD can act as general purpose I/O. In addition each pin can act as an output from the external bus interface module or a peripheral module or an input to the external bus int[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 261 4.4.1.2 Input Register This is a read-only register and always returns the buffered state of the pin ( Figure 4-76 ). 4.4.1.3 Data Direction Register This register defines whether the pin is used as an input or an output. If a periph[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 262 F reescale Semiconductor 4.4.1.8 Interrupt Enable Register If the pin is used as an interrupt input this register serves as a mask to the interrupt flag to enable/disable the interrupt. 4.4.1.9 Interrupt Flag Register If the pin is used as an interrupt input[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 263 4.4.2.3 P or t C and D Port C pins PC[7:0] and port D pins PD[7:0] can be used for either general-purpose I/O, or, in 144-pin packages, also with the external bus interface. In this case port C and port D are associated with the exte[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 264 F reescale Semiconductor 4.4.2.6 P or t T This port is associated with the ECT module. Port T pins PT[7:0] can be used for either general-purpose I/O, or with the channels of the enhanced capture timer. 4.4.2.7 P or t S This port is associated with SCI0, SCI[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 265 4.4.2.10 P or t H This port is associated with the SPI1, SPI2, SCI4, and SCI5. Port H pins PH[7:0] can be used for either general purpose I/O, or with the SPI and SCI subsystems. Port H pins can be used with the routed SPI1 and SPI2 [...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 266 F reescale Semiconductor 4.4.3 Pin Interrupts Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or falling edges can be individually configured on per-pin basis. All bits/pins in a port share the same [...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 267 A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level directly or indirectly. The filters are continuously clocked by the bus clock in run and wait m[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 268 F reescale Semiconductor 4.4.5 Low-P ower Options 4.4.5.1 Run Mode No low-power options exist for this module in run mode. 4.4.5.2 W ait Mode No low-power options exist for this module in wait mode. 4.4.5.3 Stop Mode All clocks are stopped. There are asynchr[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 269 • Po wer consumption will increase the more the voltages on general purpose input pins de viate from the supply voltages to wards mid-range because the digital input b uf fers operate in the linear region.[...]

Chapter 4 P ort Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 270 F reescale Semiconductor[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 271 Chapter 5 Cloc ks and Reset Generator (S12CRGV6) 5.1 Intr oduction This specification describes the function of the clocks and reset generator (MC9S12XDP512). 5.1.1 Features The main features of this block are: • Phase locked loop (PLL) frequenc y multiplier — Reference divider ?[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 272 F reescale Semiconductor 5.1.2 Modes of Operation This subsection lists and briefly describes all operating modes supported by the CRG. • Run mode All functional parts of the CRG are running during normal run mode. If R TI or COP functionality is required, th[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 273 5.1.3 Bloc k Diagram Figure 5-1 sho ws a block diagram of the MC9S12XDP512. Figure 5-1. CRG Block Dia gram CRG Registers Clock and Reset COP RESET RTI PLL XFC V DDPLL V SSPLL Oscillator EXTAL XTAL Control Bus Clock System Reset Oscillato[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 274 F reescale Semiconductor 5.2 External Signal Description This section lists and describes the signals that connect of f chip. 5.2.1 V DDPLL and V SSPLL — Operating and Gr ound V oltage Pins These pins provide operating v oltage (V DDPLL ) and ground (V SSPLL )[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 275 5.3.1 Module Memory Map T able 5-1 gi ves an ov erview on all MC9S12XDP512 re gisters. NO TE Register Address = Base Address + Address Of fset, where the Base Address is defined at the MCU le vel and the Address Of fset is defined at t[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 276 F reescale Semiconductor 5.3.2 Register Descriptions This section describes in address order all the MC9S12XDP512 registers and their indi vidual bits. Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x_00 SYNR R0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 W 0x_01 REFD V R0 0 REFD V[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 277 5.3.2.1 CRG Synthesizer Register (SYNR) The SYNR register controls the multiplication f actor of the PLL. If the PLL is on, the count in the loop di vider (SYNR) register ef fectiv ely multiplies up the PLL clock (PLLCLK) from the refere[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 278 F reescale Semiconductor NO TE Write to this register initializes the lock detector bit and the track detector bit. 5.3.2.3 Reserved Register (CTFLG) This register is reserv ed for factory testing of the MC9S12XDP512 module and is not av ailable in normal modes.[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 279 T able 5-2. CRGFLG Field Descriptions Field Description 7 R TIF Real Time Interrupt Flag — R TIF is set to 1 at the end of the R TI period. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enab led (R TIE = [...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 280 F reescale Semiconductor 5.3.2.5 CRG Interrupt Enable Register (CRGINT) This register enables CRG interrupt requests. Read: Anytime Write: Anytime Module Base +0x_04 76543210 R R TIE ILAF 0 LOCKIE 00 SCMIE 0 W Reset 0 1 000000 1. ILAF is set to 1 when an illegal[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 281 5.3.2.6 CRG Cloc k Select Register (CLKSEL) This register controls CRG clock selection. Refer to Figure 5-17 for more details on the ef fect of each bit. Read: Anytime Write: Refer to each bit for indi vidual write conditions Module Base[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 282 F reescale Semiconductor 5.3.2.7 CRG PLL Contr ol Register (PLLCTL) This register controls the PLL functionality. Read: Anytime Write: Refer to each bit for indi vidual write conditions Module Base +0x_06 76543210 R CME PLLON A UTO ACQ FSTWKP PRE PCE SCME W Rese[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 283 5.3.2.8 CRG R TI Control Register (R TICTL) This register selects the timeout period for the real time interrupt. Read: Anytime Write: Anytime NO TE A write to this register initializes the R TI counter. 2 PRE RTI Enab le during Pseudo S[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 284 F reescale Semiconductor T able 5-7. R TI Frequency Divide Rates for R TDEC = 0 RTR[3:0] RTR[6:4] = 000 (OFF) 001 (2 10 ) 010 (2 11 ) 011 (2 12 ) 100 (2 13 ) 101 (2 14 ) 110 (2 15 ) 111 (2 16 ) 0000 ( ÷ 1) OFF * 2 10 2 11 2 12 2 13 2 14 2 15 2 16 0001 ( ÷ 2) O[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 285 T able 5-8. R TI Frequency Divide Rates for R TDEC = 1 RTR[3:0] RTR[6:4] = 000 (1x10 3 ) 001 (2x10 3 ) 010 (5x10 3 ) 011 (10x10 3 ) 100 (20x10 3 ) 101 (50x10 3 ) 110 (100x10 3 ) 111 (200x10 3 ) 0000 ( ÷ 1) 1x10 3 2x10 3 5x10 3 10x10 3 2[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 286 F reescale Semiconductor 5.3.2.9 CRG COP Contr ol Register (COPCTL) This register controls the COP (computer operating properly) w atchdog. Read: Anytime Write: 1. RSBCK: Anytime in special modes; write to “1” b ut not to “0” in all other modes 2. WCOP ,[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 287 5 WR TMASK Write Mask for WCOP and CR[2:0] Bit — This write-only bit ser ves as a mask f or the WCOP and CR[2:0] bits while writing the COPCTL register. It is intended for BDM writing the RSBCK without touching the contents of WCOP and[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 288 F reescale Semiconductor 5.3.2.10 Reser ved Register (FORBYP) NO TE This reserved re gister is designed for factory test purposes only , and is not intended for general user access. Writing to this register when in special modes can alter the CRG’ s functional[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 289 5.3.2.12 CRG COP Timer Arm/Reset Register (ARMCOP) This register is used to restart the COP time-out period. Read: Always reads 0x_00 Write: Anytime When the COP is disabled (CR[2:0] = “000”) writing to this register has no ef fect. [...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 290 F reescale Semiconductor 5.4 Functional Description 5.4.1 Functional Bloc ks 5.4.1.1 Phase Loc ked Loop (PLL) The PLL is used to run the MCU from a dif ferent time base than the incoming OSCCLK. For increased flexibility , OSCCLK can be di vided in a range of 1[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 291 5.4.1.1.1 PLL Operation The oscillator output clock signal (OSCCLK) is fed through the reference programmable di vider and is di vided in a range of 1 to 64 (REFD V + 1) to output the REFERENCE clock. The VCO output clock, (PLLCLK) is fe[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 292 F reescale Semiconductor The follo wing conditions apply when the PLL is in automatic bandwidth control mode (A UTO = 1): • The TRA CK bit is a read-only indicator of the mode of the filter. • The TRA CK bit is set when the VCO frequency is within a certain[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 293 The clock generator creates the clocks used in the MCU (see Figure 5-17 ). The gating condition placed on top of the indi vidual clock gates indicates the dependencies of dif ferent modes (STOP , W AIT) and the setting of the respecti ve[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 294 F reescale Semiconductor A number greater equal than 4096 rising OSCCLK edges within a chec k window is called osc ok . Note that osc ok immediately terminates the current check window . See Figure 5-19 as an example. Figure 5-19. Check Windo w Example The seque[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 295 NO TE Remember that in parallel to additional actions caused by self clock mode or clock monitor reset 1 handling the clock quality checker continues to check the OSCCLK signal. The clock quality checker enables the PLL and the v oltage [...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 296 F reescale Semiconductor 5.4.2.2 Self Cloc k Mode The VCO has a minimum operating frequency , f SCM . If the e xternal clock frequency is not a vailable due to a failure or due to long crystal start-up time, the b us clock and the core clock are deriv ed from th[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 297 Figure 5-21. W ait Mode Entr y/Exit Sequence Enter Wait Mode PLL W AI=1 ? Exit Wait w. CMRESET Exit Wait w. ext.RESET Exit Wait Mode Enter SCM Exit Wait Mode CPU Req’ s W ait Mode. Clear PLLSEL, Disable PLL CME=1 ? INT ? CM Fail ? SCME[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 298 F reescale Semiconductor There are four dif ferent scenarios for the CRG to restart the MCU from wait mode: • External reset • Clock monitor reset • COP reset • Any interrupt If the MCU gets an external reset or COP reset during w ait mode acti ve, the C[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 299 T able 5-12. Outcome of Clock Loss in W ait Mode CME SCME SCMIE CRG Actions 0X X Clock f ailure --> No action, clock loss not detected. 10 X Clock f ailure --> CRG perf or ms Clock Monitor Reset immediately 11 0 Clock f ailure --&g[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 300 F reescale Semiconductor Figure 5-22. Stop Mode Entry/Exit Sequence Exit Stop w. CMRESET Exit Stop Mode Enter SCM Exit Stop Mode Core req’s Stop Mode. Clear PLLSEL, Disable PLL CME=1 ? INT ? CM fail ? SCME=1 ? SCMIE=1 ? Continue w. normal OP No No no No Yes Ye[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 301 5.4.3.3.1 Wake-up fr om Pseudo Stop Mode (PSTP=1) W ake-up from pseudo stop mode is the same as w ake-up from wait mode. There are also four dif ferent scenarios for the CRG to restart the MCU from pseudo stop mode: • External reset ?[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 302 F reescale Semiconductor T able 5-13. Outcome of Clock Loss in Pseudo Stop Mode CME SCME SCMIE CRG Actions 0X X Clock f ailure --> No action, clock loss not detected. 10 X Clock f ailure --> CRG perf or ms Clock Monitor Reset immediately 11 0 Clock Monitor[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 303 5.4.3.3.2 Wake-up fr om Full Stop (PSTP = 0) The MCU requires an external interrupt or an e xternal reset in order to wake-up from stop-mode. If the MCU gets an external reset during full stop mode acti ve, the CRG asynchronously restore[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 304 F reescale Semiconductor Figure 5-23. Fast W ake-up from Full Stop Mode: Example 1 . Figure 5-24. Fast W ake-up from Full Stop Mode: Example 2 Oscillator Clock PLL Clock Core Clock Instruction ST OP IRQ Ser vice FSTWKP=1 Interrupt IRQ Ser vice Interrupt Interr u[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 305 5.5 Resets This section describes ho w to reset the MC9S12XDP512, and how the MC9S12XDP512 itself controls the reset of the MCU. It explains all special reset requirements. Since the reset generator for the MCU is part of the CRG, this s[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 306 F reescale Semiconductor NO TE External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a v alid logic 1 within 64 SYSCLK cycles after the lo w driv e is released. The in[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 307 5.5.2 Cloc k Monitor Reset The MC9S12XDP512 generates a clock monitor reset in case all of the follo wing conditions are true: • Clock monitor is enabled (CME = 1) • Loss of clock is detected • Self-clock mode is disabled (SCME = 0[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 308 F reescale Semiconductor Figure 5-26. RESET Pin Tied to V DD (by a pull-up resistor) Figure 5-27. RESET Pin Held Low Externall y 5.6 Interrupts The interrupts/reset vectors requested by the CRG are listed in T able 5-16 . Refer to MCU specification for related [...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 309 5.6.2 PLL Loc k Interrupt The MC9S12XDP512 generates a PLL Lock interrupt when the LOCK condition of the PLL has changed, either from a locked state to an unlock ed state or vice versa. Lock interrupts are locally disabled by setting the[...]

Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev . 2.11 310 F reescale Semiconductor[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 311 Chapter 6 Pier ce Oscillator (S12XOSCLCPV1) 6.1 Intr oduction The Pierce oscillator (XOSC) module provides a rob ust, low-noise and lo w-power clock source. The module will be operated from the V DDPLL supply rail (2.5 V nominal) and require the minimum number of external components. [...]

Chapter 6 Pierce Oscillator (S12XOSCLCPV1) MC9S12XDP512 Data Sheet, Rev . 2.11 312 F reescale Semiconductor 6.1.3 Bloc k Diagram Figure 6-1 sho ws a block diagram of the XOSC. Figure 6-1. XOSC Block Dia gram 6.2 External Signal Description This section lists and describes the signals that connect of f chip 6.2.1 V DDPLL and V SSPLL — Operating an[...]

Chapter 6 Pierce Oscillator (S12XOSCLCPV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 313 EXT AL input frequency. In full stop mode (PSTP = 0), the EXT AL pin is pulled down by an internal resistor of typical 200 k Ω . NO TE Freescale recommends an e v aluation of the application board and chosen resonator or crystal by the reso[...]

Chapter 6 Pierce Oscillator (S12XOSCLCPV1) MC9S12XDP512 Data Sheet, Rev . 2.11 314 F reescale Semiconductor 6.2.3 XCLKS — Input Signal The XCLKS is an input signal which controls whether a crystal in combination with the internal loop controlled (lo w po wer) Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuit[...]

Chapter 6 Pierce Oscillator (S12XOSCLCPV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 315 6.4.3 W ait Mode Operation During wait mode, XOSC is not impacted. 6.4.4 Stop Mode Operation XOSC is placed in a static state when the part is in stop mode except when pseudo-stop mode is enabled. During pseudo-stop mode, XOSC is not impacted[...]

Chapter 6 Pierce Oscillator (S12XOSCLCPV1) MC9S12XDP512 Data Sheet, Rev . 2.11 316 F reescale Semiconductor[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 317 Chapter 7 Analog-to-Digital Con ver ter (A TD10B16CV4) 7.1 Intr oduction The A TD10B16C is a 16-channel, 10-bit, multiplexed input successi ve approximation analog-to-digital con verter . Refer to the Electrical Specifications chapter for A TD accuracy. 7.1.1 Features • 8-/10-bit r[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 318 F reescale Semiconductor Figure 7-1. A TD10B16C Block Dia gram V SSA AN8 A TD10B16C Analog MUX Mode and Successive Appro ximation Register (SAR) Results A TD 0 A TD 1 A TD 2 A TD 3 A TD 4 A TD 5 A TD 6 A TD 7 and D AC Sample & Hold 1 1 V DD A V RL V RH[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 319 7.2 External Signal Description This section lists all inputs to the A TD10B16C block. 7.2.1 AN x ( x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — Analog Input Channel x Pins This pin serves as the analog input chann[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 320 F reescale Semiconductor . NO TE Register Address = Base Address + Address Of fset, where the Base Address is defined at the MCU le vel and the Address Of fset is defined at the module le vel. T able 7-1. MC9S12XDP512 Memory Map Address Offset Use Access[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 321 7.3.2 Register Descriptions This section describes in address order all the A TD10B16C registers and their indi vidual bits. Register Name Bit 7 6 5 4321 Bit 0 0x0000 A TDCTL0 R 0000 WRAP3 WRAP2 WRAP1 WRAP0 W 0x0001 A TDCTL1 R ETRI[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 322 F reescale Semiconductor 7.3.2.1 A TD Control Register 0 (A TDCTL0) Writes to this register will abort current con version sequence b ut will not start a new sequence. Read: Anytime Write: Anytime 0x000D A TDDIEN1 R IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 [...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 323 7.3.2.2 A TD Control Register 1 (A TDCTL1) Writes to this register will abort current con version sequence b ut will not start a new sequence. Read: Anytime Write: Anytime T able 7-3. Multi-Channel Wrap Around Coding WRAP3 WRAP2 WR[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 324 F reescale Semiconductor 7.3.2.3 A TD Control Register 2 (A TDCTL2) This register controls po wer down, interrupt and e xternal trigger. Writes to this register will abort current con version sequence b ut will not start a ne w sequence. T able 7-5. Extern[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 325 Read: Anytime Write: Anytime Module Base + 0x0002 76543210 R ADPU AFFC A W AI ETRIGLE ETRIGP ETRIGE ASCIE ASCIF W Reset 00000000 = Unimplemented or Reser ved Figure 7-5. A TD Contr ol Register 2 (A TDCTL2) T able 7-6. A TDCTL2 Fiel[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 326 F reescale Semiconductor 1 ASCIE A TD Sequence Complete Interrupt Enable 0 A TD Sequence Complete interrupt requests are disabled. 1 A TD Interrupt will be requested whenev er ASCIF = 1 is set. 0 ASCIF A TD Sequence Complete Interrupt Flag — If ASCIE = 1[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 327 7.3.2.4 A TD Control Register 3 (A TDCTL3) This register controls the con version sequence length, FIFO for results registers and beha vior in Freeze Mode. Writes to this register will abort current con version sequence b ut will n[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 328 F reescale Semiconductor T able 7-9. Con version Sequence Length Coding S8C S4C S2C S1C Number of Con versions per Sequence 0000 1 6 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 1 0 1011 1 1 1100 1 2 1101 1 3 1110 1 4 1111 1 5 T able[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 329 7.3.2.5 A TD Control Register 4 (A TDCTL4) This register selects the con version clock frequency , the length of the second phase of the sample time and the resolution of the A/D con version (i.e., 8-bits or 10-bits). Writes to thi[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 330 F reescale Semiconductor T able 7-13. Cloc k Prescaler V alues Prescale V alue T otal Divisor V alue Max. Bus Clock 1 1 Maximum A TD conv ersion clock frequency is 2 MHz. The maxim um allowed b us clock frequency is shown in this column. Min. Bus Clock 2 2[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 331 7.3.2.6 A TD Control Register 5 (A TDCTL5) This register selects the type of con version sequence and the analog input channels sampled. Writes to this register will abort current con version sequence and start a ne w con version s[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 332 F reescale Semiconductor 3:0 C[D:A} Analog Input Channel Select Code — These bits select the analog input channel(s) whose signals are sampled and conv er ted to digital codes. T able 7-17 lists the coding used to select the v arious analog input channel[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 333 T able 7-17. Analog Input Channel Select Coding CD CC CB CA Analog Input Channel 0 0 0 0 AN0 0 0 0 1 AN1 0 0 1 0 AN2 0 0 1 1 AN3 0 1 0 0 AN4 0 1 0 1 AN5 0 1 1 0 AN6 0 1 1 1 AN7 1 0 0 0 AN8 1 0 0 1 AN9 1 0 1 0 AN10 1 0 1 1 AN11 1 1 [...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 334 F reescale Semiconductor 7.3.2.7 A TD Status Register 0 (A TDST A T0) This read-only register contains the Sequence Complete Flag, o verrun flags for external trigger and FIFO mode, and the con version counter. Read: Anytime Write: Anytime (No ef fect on [...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 335 7.3.2.8 Reserved Register 0 (A TDTEST0) Read: Anytime, returns unpredictable v alues Write: Anytime in special modes, unimplemented in normal modes NO TE Writing to this register when in special modes can alter functionality . 7.3.[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 336 F reescale Semiconductor 7.3.2.10 A TD Status Register 2 (A TDST A T2) This read-only register contains the Con version Complete Flags CCF15 to CCF8. Read: Anytime Write: Anytime, no ef fect T able 7-20. Special Channel Select Coding SC CD CC CB CA Analog [...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 337 7.3.2.11 A TD Status Register 1 (A TDST A T1) This read-only register contains the Con version Complete Flags CCF7 to CCF0 Read: Anytime Write: Anytime, no ef fect Module Base + 0x000B 76543210 R CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 [...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 338 F reescale Semiconductor 7.3.2.12 A TD Input Enable Register 0 (A TDDIEN0) Read: Anytime Write: anytime 7.3.2.13 A TD Input Enable Register 1 (A TDDIEN1) Read: Anytime Write: Anytime Module Base + 0x000C 76543210 R IEN15 IEN14 IEN13 IEN12 IEN11 IEN10 IEN9 [...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 339 7.3.2.14 P or t Data Register 0 (PORT AD0) The data port associated with the A TD is input-only. The port pins are shared with the analog A/D inputs AN[15:8]. Read: Anytime Write: Anytime, no ef fect The A/D input channels may be u[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 340 F reescale Semiconductor 7.3.2.15 P or t Data Register 1 (PORT AD1) The data port associated with the A TD is input-only. The port pins are shared with the analog A/D inputs AN7-0. Read: Anytime Write: Anytime, no ef fect The A/D input channels may be used[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 341 7.3.2.16 A TD Con version Result Register s (A TDDRx) The A/D con version results are stored in 16 read-only result re gisters. The result data is formatted in the result registers bases on tw o criteria. First there is left and ri[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 342 F reescale Semiconductor 7.3.2.16.2 Right J ustified Result Data 7.4 Functional Description The A TD10B16C is structured in an analog and a digital sub-block. 7.4.1 Analog Sub-bloc k The analog sub-block contains all analog electronics required to perform[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 343 When not sampling, the sample and hold machine disables its o wn clocks. The analog electronics continue drawing their quiescent current. The po wer down (ADPU) bit must be set to disable both the digital clocks and the analog po w[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 344 F reescale Semiconductor During a con version, if additional acti ve edges are detected the ov errun error flag ETORF is set. In either le vel or edge triggered modes, the first con version begins when the trigger is recei ved. In both cases, the maximum[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 345 Entering wait mode, the A TD con version either continues or halts for lo w power depending on the logical v alue of the A W AIT bit. • Freeze Mode Writing ADPU = 0 (Note that all A TD registers remain accessible.): This aborts a[...]

Chapter 7 Analog-to-Digital Con verter (A TD10B16CV4) MC9S12XDP512 Data Sheet, Rev . 2.11 346 F reescale Semiconductor[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 347 Chapter 8 Analog-to-Digital Con ver ter (A TD10B8CV3) 8.1 Intr oduction The A TD10B8C is an 8-channel, 10-bit, multiplexed input successi ve approximation analog-to-digital con verter . Refer to device electrical specifications for A TD accuracy. 8.1.1 Features • 8/10-bit resolutio[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 348 F reescale Semiconductor 8.1.2.2 MCU Operating Modes • Stop mode Entering stop mode causes all clocks to halt and thus the system is placed in a minimum po wer standby mode. This aborts any con version sequence in progress. During recov ery from stop mode[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 349 Figure 8-1. A TD Bloc k Diagram V SSA A TD10B8C Analog MUX Mode and Successive Appro ximation Register (SAR) Results A TD 0 A TD 1 A TD 2 A TD 3 A TD 4 A TD 5 A TD 6 A TD 7 and D AC Sample & Hold 1 1 V DD A V RL V RH Sequence Co[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 350 F reescale Semiconductor 8.3 Memor y Map and Register Definition This section provides a detailed description of all re gisters accessible in the A TD. 8.3.1 Module Memory Map Figure 8-2 gi ves an o vervie w of all A TD registers. NO TE Register Address = [...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 351 0x000A Unimplemente d R W 0x000B A TDST A T1 R CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 W 0x000C Unimplemente d R W 0x000D A TDDIEN R IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 W 0x000E Unimplemente d R W 0x000F POR T AD R PT AD7 PT AD6[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 352 F reescale Semiconductor 0x0016 A TDDR3H 10-BIT BIT 9 MSB BIT 7 MSB BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 8-BIT W 0x0017 A TDDR3L 10-BIT BIT 1 U BIT 0 U 0 0 0 0 0 0 0 0 0 0 0 0 8-BIT W 0x0018 A TDDR4H 10-BIT BIT[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 353 0x0011 A TDDR0L 10-BIT BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 8-BIT W 0x0012 A TDDR1H 10-BIT 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 8-BIT W 0x0013 A TDDR1L 10-BIT BIT[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 354 F reescale Semiconductor 8.3.2.1 A TD Control Register 0 (A TDCTL0) Writes to this register will abort current con version sequence b ut will not start a new sequence. Read: Anytime Write: Anytime 0x001D A TDDR6L 10-BIT BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 355 1 1 0 AN6 1 1 1 AN7 T able 8-2. Multi-Channel Wrap Around Coding WRAP2 WRAP1 WRAP0 Multiple Channel Con versions (MUL T = 1) Wrap Around to AN0 after Con verting[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 356 F reescale Semiconductor 8.3.2.2 A TD Control Register 1 (A TDCTL1) Writes to this register will abort current con version sequence b ut will not start a new sequence. Read: Anytime Write: Anytime Module Base + 0x0001 76543210 R ETRIGSEL 0000 ETRIGCH2 ETRIG[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 357 8.3.2.3 A TD Control Register 2 (A TDCTL2) This register controls po wer down, interrupt and e xternal trigger. Writes to this register will abort current con version sequence b ut will not start a ne w sequence. Read: Anytime Write[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 358 F reescale Semiconductor 8.3.2.4 A TD Control Register 3 (A TDCTL3) This register controls the conversion sequence length, FIFO for results registers and behavior in freeze mode. Writes to this register will abort current conversion sequence but will not st[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 359 2 FIFO Result Register FIFO Mode — If this bit is zero (non-FIFO mode), the A/D con version results map into the result registers based on the conv ersion sequence; the result of the first conversion appears in the first result [...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 360 F reescale Semiconductor 8.3.2.5 A TD Control Register 4 (A TDCTL4) This register selects the con version clock frequency , the length of the second phase of the sample time and the resolution of the A/D con version (i.e.: 8-bits or 10-bits). Writes to this[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 361 T able 8-12. Cloc k Prescaler V alues Prescale V alue T otal Divisor V alue Max. Bus Clock 1 1 Maximum A TD conv ersion clock frequency is 2 MHz. The maxim um allowed b us clock frequency is shown in this column. Min. Bus Clock 2 2 [...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 362 F reescale Semiconductor 8.3.2.6 A TD Control Register 5 (A TDCTL5) This register selects the type of con version sequence and the analog input channels sampled. Writes to this register will abort current con version sequence and start a ne w con version se[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 363 T able 8-14. A vailable Result Data Formats SRES8 DJM DSGN Result Data Formats Description and Bus Bit Mapping 1 1 1 0 0 0 0 0 1 0 0 1 0 1 X 0 1 X 8-bit / left justified / unsigned — bits 8–15 8-bit / left justified / signed ?[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 364 F reescale Semiconductor 8.3.2.7 A TD Status Register 0 (A TDST A T0) This read-only register contains the sequence complete flag, o verrun flags for external trigger and FIFO mode, and the con version counter . Read: Anytime Write: Anytime (No ef fect on[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 365 8.3.2.8 Reserved Register (A TDTEST0) Read: Anytime, returns unpredictable v alues Write: Anytime in special modes, unimplemented in normal modes NO TE Writing to this register when in special modes can alter functionality . 8.3.2.9[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 366 F reescale Semiconductor 8.3.2.10 A TD Status Register 1 (A TDST A T1) This read-only register contains the con version complete flags. Read: Anytime Write: Anytime, no ef fect T able 8-19. Special Channel Select Coding SC CC CB CA Analog Input Channel 1 0[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 367 8.3.2.11 A TD Input Enable Register (A TDDIEN) Read: Anytime Write: Anytime 8.3.2.12 P or t Data Register (PORT AD) The data port associated with the A TD can be configured as general-purpose I/O or input only , as specified in th[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 368 F reescale Semiconductor 8.3.2.13 A TD Con version Result Register s (A TDDRx) The A/D con version results are stored in 8 read-only result re gisters. The result data is formatted in the result registers based on tw o criteria. First there is left and righ[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 369 8.3.2.13.2 Right J ustified Result Data 8.4 Functional Description The A TD is structured in an analog and a digital sub-block. 8.4.1 Analog Sub-Bloc k The analog sub-block contains all analog electronics required to perform a sing[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 370 F reescale Semiconductor 8.4.1.2 Analog Input Multiplex er The analog input multiplex er connects one of the 8 external analog input channels to the sample and hold machine. 8.4.1.3 Sample Buffer Amplifier The sample amplifier is used to b uffer the input[...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 371 During a con version, if additional acti ve edges are detected the ov errun error flag ETORF is set. In either le vel or edge triggered modes, the first con version begins when the trigger is recei ved. In both cases, the maximum [...]

Chapter 8 Analog-to-Digital Con verter (A TD10B8CV3) MC9S12XDP512 Data Sheet, Rev . 2.11 372 F reescale Semiconductor 8.4.2.3 Low P ower Modes The A TD can be configured for lower MCU po wer consumption in 3 different ways: 1. Stop mode: This halts A/D con version. Exit from stop mode will resume A/D con version, b ut due to the recov ery time the[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 373 Chapter 9 XGA TE (S12XGA TEV2) 9.1 Intr oduction The XGA TE module is a peripheral co-processor that allows autonomous data transfers between the MCU’ s peripherals and the internal memories. It has a built in RISC core that is able to pre-process the transferred data and perform co[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 374 F reescale Semiconductor 9.1.2 Modes of Operation There are four run modes on S12X de vices. • Run mode, wait mode, stop mode The XGA TE is able to operate in all of these three system modes. Clock activity will be automatically stopped when the XGA TE module is idle. • Free[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 375 9.3 Memor y Map and Register Definition This section provides a detailed description of address space and re gisters used by the XGA TE module. The memory map for the XGA TE module is giv en belo w in T able 9-1 .The address listed for each register is [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 376 F reescale Semiconductor 9.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard re gister diagram with an associated figure number. Details of register bit and field function follo w the register diagra[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 377 Register Name 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 0x0010 XGIF R XGIF_3F XGIF_3E XGIF_3D XGIF_3C XGIF_3B XGIF_3A XGIF_39 XGIF_38 XGF _37 XGIF_36 XGIF_35 XGIF_34 XGIF_33 XGIF_32 XGIF_31 XGIF_30 W 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 378 F reescale Semiconductor Register Name 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 0x0026 XGR3 R XGR3 W 0x0028 XGR4 R XGR4 W 0x002A XGR5 R XGR5 W 0x002C XGR6 R XGR6 W 0x002E XGR7 R XGR7 W = Unimplemented or Reser ved Figure 9-2. XGA TE Register Summary (Sheet 3 of 3)[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 379 9.3.2.1 XGA TE Control Register (XGMCTL) All module level switches and flags are located in the module control register Figure 9-3 . Read: Anytime Write: Anytime Module Base +0x00000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 00000000 XGE XGFRZ XGDBG XGSS X[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 380 F reescale Semiconductor 11 XGF ACTM XGF ACT Mask — This bit controls the write access to the XGF ACT bit. The XGF A CT bit can only be set or cleared if a "1" is written to the XGF A CTM bit in the same register access. Read: This bit will alwa ys read "0"[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 381 4 XGSS XGA TE Single Step — This bit forces the e xecution of a single instruction if the XGA TE is in DEBUG Mode and no software error has occurred (XGSWEIF cleared). Read: 0 No single step in progress 1 Single step in progress Write 0 No effect 1 Exe[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 382 F reescale Semiconductor 9.3.2.2 XGA TE Channel ID Register (XGCHID) The XGA TE channel ID register ( Figure 9-4 ) sho ws the identifier of the XGA TE channel that is currently acti ve. This re gister will read “$00” if the XGA TE module is idle. In deb ug mode this registe[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 383 9.3.2.4 XGA TE Channel Interrupt Flag V ector (XGIF) The interrupt flag vector ( Figure 9-6 ) pro vides access to the interrupt flags bits of each channel. Each flag may be cleared by writing a "1" to its bit location. Read: Anytime Module B[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 384 F reescale Semiconductor Write: Anytime NO TE Suggested Mnemonics for accessing the interrupt flag vector on a w ord basis are: XGIF_7F_70 (XGIF[127:112]), XGIF_6F_60 (XGIF[111:96]), XGIF_5F_50 (XGIF[95:80]), XGIF_4F_40 (XGIF[79:64]), XGIF_3F_30 (XGIF[63:48]), XGIF_2F_20 (XGIF[[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 385 9.3.2.5 XGA TE Software T rig ger Register (XGSWT) The eight software triggers of the XGA TE module can be set and cleared through the XGA TE software trigger register ( Figure 9-7 ). The upper byte of this re gister , the software trigger mask, controls[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 386 F reescale Semiconductor 9.3.2.6 XGA TE Semaphore Register (XGSEM) The XGA TE provides a set of eight hardware semaphores that can be shared between the S12X_CPU and the XGA TE RISC core. Each semaphore can either be unlocked, locked by the S12X_CPU or locked by the RISC core. T[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 387 9.3.2.7 XGA TE Condition Code Register (XGCCR) The XGCCR register ( Figure 9-9 ) pro vides access to the RISC core’ s condition code register. Read: In debug mode if unsecured Write: In debug mode if unsecured Module Base +0x001D 76543210 R 0000 XGN XG[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 388 F reescale Semiconductor 9.3.2.8 XGA TE Program Counter Register (XGPC) The XGPC register ( Figure 9-10 ) pro vides access to the RISC core’ s program counter. Read: In debug mode if unsecured Write: In debug mode if unsecured 9.3.2.9 XGA TE Register 1 (XGR1) The XGR1 register[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 389 9.3.2.10 XGA TE Register 2 (XGR2) The XGR2 register ( Figure 9-13 ) pro vides access to the RISC core’ s register 2. Read: In debug mode if unsecured Write: In debug mode if unsecured 9.3.2.11 XGA TE Register 3 (XGR3) The XGR3 register ( Figure 9-14 ) [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 390 F reescale Semiconductor 9.3.2.12 XGA TE Register 4 (XGR4) The XGR4 register ( Figure 9-15 ) pro vides access to the RISC core’ s register 4. Read: In debug mode if unsecured Write: In debug mode if unsecured 9.3.2.13 XGA TE Register 5 (XGR5) The XGR5 register ( Figure 9-16 ) [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 391 9.3.2.14 XGA TE Register 6 (XGR6) The XGR6 register ( Figure 9-17 ) pro vides access to the RISC core’ s register 6. Read: In debug mode if unsecured Write: In debug mode if unsecured 9.3.2.15 XGA TE Register 7 (XGR7) The XGR7 register ( Figure 9-18 ) [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 392 F reescale Semiconductor 9.4 Functional Description The core of the XGA TE module is a RISC processor which is able to access the MCU’ s internal memories and peripherals (see Figure 9-1 ). The RISC processor always remains in an idle state until it is triggered by an XGA TE r[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 393 9.4.2 Pr ogrammer’ s Model Figure 9-19. Programmer’ s Model The programmer’ s model of the XGA TE RISC core is shown in Figure 9-19 . The processor of fers a set of se ven general purpose re gisters (R1 - R7), which serve as accumulators and inde x[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 394 F reescale Semiconductor Figure 9-20. XGA TE V ector Block 9.4.4 Semaphores The XGA TE module offers a set of eight hardware semaphores. These semaphores pro vide a mechanism to protect system resources that are shared between two concurrent threads of program e xecution; one th[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 395 Figure 9-21. Semaphore State T ransitions UNLOCKED LOCKED BY S12X_CPU LOCKED BY XGATE CSEM Instruction %0 ⇒ XGSEM CSEM Instruction SSEM Instruction %1 ⇒ XGSEM SSEM Instruction %0 ⇒ XGSEM %1 ⇒ XGSEM CSEM Instruction %0 ⇒ XGSEM %1 ⇒ XGSEM SSEM [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 396 F reescale Semiconductor Figure 9-22 gi ves an e xample of the typical usage of the XGA TE hardware semaphores. T wo concurrent threads are running on the system. One is running on the S12X_CPU and the other is running on the RISC core. They both ha ve a critical section of code[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 397 9.5 Interrupts 9.5.1 Incoming Interrupt Requests XGA TE threads are triggered by interrupt requests which are routed to the XGA TE module (see S12X_INT Section). Only a subset of the MCU’ s interrupt requests can be routed to the XGA TE. Which specifi[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 398 F reescale Semiconductor • Single Stepping Writing a "1" to the XGSS bit will call the RISC core to execute a single instruction. All RISC core registers will be updated accordingly. • Write accesses to the XGCHID register Three operations can be performed by writi[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 399 3. T agged Breakpoints The S12X_DBG module is able to place tags on fetched opcodes. The XGATE is able to enter debug mode right before a tagged opcode is executed (see section 4.9 of the S12X_DBG Section ). Upon entering debug mode, the program counter [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 400 F reescale Semiconductor 9.8.1.1 Naming Con ventions RD Destination register , allowed range is R0–R7 RD.L Lo w byte of the destination register , bits [7:0] RD.H High byte of the destination register , bits [15:8] RS, RS1, RS2 Source register , allowed range is R0–R7 RS.L, [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 401 9.8.1.4 Immediate 4-Bit Wide (IMM4) The 4-bit wide immediate addressing mode is supported by all shift instructions. RD = RD ∗ imm4 Examples: LSL R4,#1 ; R4 = R4 << 1; shift register R4 by 1 bit to the left LSR R4,#3 ; R4 = R4 >> 3; shift r[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 402 F reescale Semiconductor 9.8.1.8 Dy adic Addressing (D Y A) In this mode the result of an operation between two re gisters is stored in one of the registers used as operands. RD = RD ∗ RS is the general register to register format, with re gister RD being the first operand an[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 403 9.8.1.13 Index Register plus Register Offset (IDR) For load and store instructions (RS, RI) pro vides a variable of fset in a register. Examples: LDB R4,(R1,R2) ; loads a byte from R1+R2 into R4 STW R4,(R1,R2) ; stores R4 as a word to R1+R2 9.8.1.14 Inde[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 404 F reescale Semiconductor 9.8.2.2 Logic and Arithmetic Instructions All logic and arithmetic instructions support the 8-bit immediate addressing mode (IMM8: RD = RD ∗ #IMM8) and the triadic addressing mode (TRI: RD = RS1 ∗ RS2). All arithmetic is considered as signed, sign, o[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 405 9.8.2.5 Bit Field Operations This addressing mode is used to identify the position and size of a bit field for insertion or extraction. The width and of fset are coded in the lo wer byte of the source register 2, RS2. The content of the upper byte is ig[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 406 F reescale Semiconductor 9.8.3 Cyc le Notation T able 9-17 show the XGA TE access detail notation. Each code letter equals one XGA TE cycle. Each letter implies additional wait c ycles if memories or peripherals are not accessible. Memories or peripherals are not accessible if t[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 407 Operation RS1 + RS2 + C ⇒ RD Adds the content of register RS1, the content of re gister RS2 and the value of the Carry bit using binary addition and stores the result in the destination register RD. The Zero Flag is also carried forw ard from the pre v[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 408 F reescale Semiconductor Operation RS1 + RS2 ⇒ RDRD + IMM16 ⇒ RD (translates to ADDL RD, #IMM16[7:0]; ADDH RD, #[15:8]) Performs a 16-bit addition and stores the result in the destination register RD. CCR Effects Code and CPU Cycles ADD Add without Carry ADD NZ V C ∆∆∆[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 409 Operation RD + IMM8:$00 ⇒ RD Adds the content of high byte of register RD and a signed immediate 8-Bit constant using binary addition and stores the result in the high byte of the destination register RD. This instruction can be used after an ADDL for [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 410 F reescale Semiconductor Operation RD + $00:IMM8 ⇒ RD Adds the content of register RD and an unsigned immediate 8-Bit constant using binary addition and stores the result in the destination register RD. This instruction must be used first for a 16-bit immediate addition in co[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 411 Operation RS1 & RS2 ⇒ RDRD & IMM16 ⇒ RD (translates to ANDL RD, #IMM[7:0]; ANDH RD, #IMM16[15:8]) Performs a bit wise logical AND of two 16-bit v alues and stores the result in the destination register RD. Remark: There is no complement to th[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 412 F reescale Semiconductor Operation RD.H & IMM8 ⇒ RD.H Performs a bit wise logical AND between the high byte of register RD and an immediate 8-Bit constant and stores the result in the destination register RD.H. The lo w byte of RD is not affected. CCR Effects Code and CPU [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 413 Operation RD.L & IMM8 ⇒ RD.L Performs a bit wise logical AND between the lo w byte of register RD and an immediate 8-Bit constant and stores the result in the destination register RD.L. The high byte of RD is not af fected. CCR Effects Code and CPU[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 414 F reescale Semiconductor Operation n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with the sign bit (RD[15]). The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 415 Operation If C = 0, then PC + $0002 + (REL9 << 1) ⇒ PC T ests the Carry flag and branches if C = 0. CCR Effects Code and CPU Cycles BCC Branch if Carry Cleared (Same as BHS) BCC NZ V C ———— N: Not affected. Z: Not aff ected. V: Not aff e[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 416 F reescale Semiconductor Operation If C = 1, then PC + $0002 + (REL9 << 1) ⇒ PC T ests the Carry flag and branches if C = 1. CCR Effects Code and CPU Cycles BCS Branch if Carry Set (Same as BLO) BCS NZ V C ———— N: Not affected. Z: Not aff ected. V: Not aff ected[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 417 Operation If Z = 1, then PC + $0002 + (REL9 << 1) ⇒ PC T ests the Zero flag and branches if Z = 1. CCR Effects Code and CPU Cycles BEQ Branch if Equal BEQ NZ V C ———— N: Not affected. Z: Not aff ected. V: Not aff ected. C: Not affected. [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 418 F reescale Semiconductor Operation RS1[( o + w ): o ] ⇒ RD[ w :0]; 0 ⇒ RD[15:( w +1)] w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position o and writes them right aligned into re gister RD. The remaining bits in RD will be cleared. If (o+w) [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 419 Operation FirstOne (RS) ⇒ RD; Searches the first “1” beginning from the MSB=15 do wn to LSB=0 in register RS and places the result into the destination register RD. The upper bits of RD are cleared. In case the content of RS is equal to $0000, RD [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 420 F reescale Semiconductor Operation RS1[ w : 0 ] ⇒ RD[( w+o ):o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0 and writes them into re gister RD at position o . The remaining bits in RD are not af fected. If (o+w) > 15 the upper bi[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 421 Operation !RS1[ w : 0 ] ⇒ RD[ w +o:o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0, in verts them and writes into register RD at position o . The remaining bits in RD are not af fected. If (o+w) > 15 the [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 422 F reescale Semiconductor Operation !(RS1[ w : 0 ] ^ RD[w+o:o]) ⇒ RD[ w +o:o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0, performs an XNOR with RD[w+o:o] and writes the bits back. The remaining bits in RD are not af fected. If (o+w[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 423 Operation If N ^ V = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 ≥ RS2: SUB R0,RS1,RS2 BGE REL9 CCR Effects Code and CPU Cycles BGE Branch if Greater than or Equal to Zero BGE NZ V C ——?[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 424 F reescale Semiconductor Operation If Z | (N ^ V) = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 > RS2: SUB R0,RS1,RS2 BGE REL9 CCR Effects Code and CPU Cycles BGT Branch if Greater than Zero BGT NZ V C ————[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 425 Operation If C | Z = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 > RS2: SUB R0,RS1,RS2 BHI REL9 CCR Effects Code and CPU Cycles BHI Branch if Higher BHI NZ V C ———— N: Not affecte[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 426 F reescale Semiconductor Operation If C = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 ≥ RS2: SUB R0,RS1,RS2 BHS REL9 CCR Effects Code and CPU Cycles BHS Branch if Higher or Same (Same as BCC) BHS NZ V C ———?[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 427 Operation RD.H & IMM8 ⇒ NONE Performs a bit wise logical AND between the high byte of register RD and an immediate 8-Bit constant. Only the condition code flags get updated, b ut no result is written back CCR Effects Code and CPU Cycles BITH Bit T[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 428 F reescale Semiconductor Operation RD.L & IMM8 ⇒ NONE Performs a bit wise logical AND between the lo w byte of register RD and an immediate 8-Bit constant. Only the condition code flags get updated, b ut no result is written back . CCR Effects Code and CPU Cycles BITL Bit[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 429 Operation If Z | (N ^ V) = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 ≤ RS2: SUB R0,RS1,RS2 BLE REL9 CCR Effects Code and CPU Cycles BLE Branch if Less or Equal to Zero BLE NZ V C ———[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 430 F reescale Semiconductor Operation If C = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 < RS2: SUB R0,RS1,RS2 BLO REL9 CCR Effects Code and CPU Cycles BLO Branch if Carry Set (Same as BCS) BLO NZ V C ———— N[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 431 Operation If C | Z = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 ≤ RS2: SUB R0,RS1,RS2 BLS REL9 CCR Effects Code and CPU Cycles BLS Branch if Lower or Same BLS NZ V C ———— N: Not a[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 432 F reescale Semiconductor Operation If N ^ V = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 < RS2: SUB R0,RS1,RS2 BLT REL9 CCR Effects Code and CPU Cycles BL T Branch if Lower than Zero BLT NZ V C ———— N: Not[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 433 Operation If N = 1, then PC + $0002 + (REL9 << 1) ⇒ PC T ests the Sign flag and branches if N = 1. CCR Effects Code and CPU Cycles BMI Branch if Minus BMI NZ V C ———— N: Not affected. Z: Not aff ected. V: Not aff ected. C: Not affected. [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 434 F reescale Semiconductor Operation If Z = 0, then PC + $0002 + (REL9 << 1) ⇒ PC T ests the Zero flag and branches if Z = 0. CCR Effects Code and CPU Cycles BNE Branch if Not Equal BNE NZ V C ———— N: Not affected. Z: Not aff ected. V: Not aff ected. C: Not affect[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 435 Operation If N = 0, then PC + $0002 + (REL9 << 1) ⇒ PC T ests the Sign flag and branches if N = 0. CCR Effects Code and CPU Cycles BPL Branch if Plus BPL NZ V C ———— N: Not affected. Z: Not aff ected. V: Not aff ected. C: Not affected. S[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 436 F reescale Semiconductor Operation PC + $0002 + (REL10 << 1) ⇒ PC Branches always CCR Effects Code and CPU Cycles BRA Branch Always BRA NZ V C ———— N: Not affected. Z: Not aff ected. V: Not aff ected. C: Not affected. Source Form Address Mode Machine Code Cycles [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 437 Operation Put XGA TE into Debug Mode (see Section 9.6.2, “Entering Debug Mode” )and signals a Softw are breakpoint to the S12X_DBG module (see section 4.9 of the S12X_DBG Section ). CCR Effects Code and CPU Cycles BRK Break BRK NZ V C ———— N:[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 438 F reescale Semiconductor Operation If V = 0, then PC + $0002 + (REL9 << 1) ⇒ PC T ests the Overflo w flag and branches if V = 0. CCR Effects Code and CPU Cycles BVC Branch if Overflow Cleared BVC NZ V C ———— N: Not affected. Z: Not aff ected. V: Not aff ected. [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 439 Operation If V = 1, then PC + $0002 + (REL9 << 1) ⇒ PC T ests the Overflo w flag and branches if V = 1. CCR Effects Code and CPU Cycles BVS Branch if Overflow Set BVS NZ V C ———— N: Not affected. Z: Not aff ected. V: Not aff ected. C: N[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 440 F reescale Semiconductor Operation RS2 – RS1 ⇒ NONE (translates to SUB R0, RS1, RS2) RD – IMM16 ⇒ NONE (translates to CMPL RD, #IMM16[7:0]; CPCH RD, #IMM16[15:8]) Subtracts two 16-bit v alues and discards the result. CCR Effects Code and CPU Cycles CMP Compare CMP NZ V C[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 441 Operation RS.L – IMM8 ⇒ NONE, only condition code flags get updated Subtracts the 8-Bit constant IMM8 contained in the instruction code from the lo w byte of the source register RS.L using binary subtraction and updates the condition code re gister [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 442 F reescale Semiconductor Operation ~RS ⇒ RD (translates to XNOR RD, R0, RS) ~RD ⇒ RD (translates to XNOR RD, R0, RD) Performs a one’ s complement on a general purpose register. CCR Effects Code and CPU Cycles COM One’s Complement COM NZ V C ∆∆ 0— N: Set if bit 15 o[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 443 Operation RS2 – RS1 − Χ ⇒ NONE (translates to SBC R0, RS1, RS2) Subtracts the carry bit and the content of register RS2 from the content of re gister RS1 using binary subtraction and discards the result. CCR Effects Code and CPU Cycles CPC Compare[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 444 F reescale Semiconductor Operation RS.H - IMM8 - C ⇒ NONE, only condition code flags get updated Subtracts the carry bit and the 8-Bit constant IMM8 contained in the instruction code from the high byte of the source re gister RD using binary subtraction and updates the condit[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 445 Operation Unlocks a semaphore that was lock ed by the RISC core. In monadic address mode, bits RS[2:0] select the semaphore to be cleared. CCR Effects Code and CPU Cycles CSEM Clear Semaphore CSEM NZ V C ———— N: Not affected. Z: Not aff ected. V:[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 446 F reescale Semiconductor Operation n = RS or IMM4 Shifts the bits in register RD n positions to the left. The lo wer n bits of the register RD become filled with the carry flag. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0. n c[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 447 Operation n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with the carry flag. The carry flag will be updated to the bit contained in RD[n-1] before the shift for n >0 . n c[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 448 F reescale Semiconductor Operation PC + $0002 ⇒ RD; RD ⇒ PC Jumps to the address stored in RD and sa ves the return address in RD. CCR Effects Code and CPU Cycles JA L Jump and Link JAL NZ V C ———— N: Not affected. Z: Not aff ected. V: Not aff ected. C: Not affected.[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 449 Operation M[RB, #OFFS5 ] ⇒ RD.L; $00 ⇒ RD.H M[RB, RI ] ⇒ RD.L; $00 ⇒ RD.H M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H; RI+1 ⇒ RI; 1 RI-1 ⇒ RI; M[RS, RI] ⇒ RD.L; $00 ⇒ RD.H Loads a byte from memory into the lo w byte of register RD. The high byte is [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 450 F reescale Semiconductor Operation IMM8 ⇒ RD.H; Loads an eight bit immediate constant into the high byte of register RD. The lo w byte is not affected. CCR Effects Code and CPU Cycles LDH Load Immediate 8-Bit Constant (High Byte) LDH NZ V C ———— N: Not affected. Z: Not[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 451 Operation IMM8 ⇒ RD.L; $00 ⇒ RD.H Loads an eight bit immediate constant into the lo w byte of register RD. The high byte is cleared. CCR Effects Code and CPU Cycles LDL Load Immediate 8-Bit Constant (Low Byte) LDL NZ V C ———— N: Not affected.[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 452 F reescale Semiconductor Operation M[RB, #OFFS5 ] ⇒ RD M[RB, RI ] ⇒ RD M[RB, RI] ⇒ RD; RI+2 ⇒ RI 1 RI-2 ⇒ RI; M[RS, RI] ⇒ RD IMM16 ⇒ RD (translates to LDL RD, #IMM16[7:0]; LDH RD, #IMM16[15:8]) Loads a 16-bit v alue into the register RD. CCR Effects Code and CPU Cy[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 453 Operation n = RS or IMM4 Shifts the bits in register RD n positions to the left. The lo wer n bits of the register RD become filled with zeros. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0. n can range f[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 454 F reescale Semiconductor Operation n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with zeros. The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0. n can range f[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 455 Operation RS ⇒ RD (translates to OR RD, R0, RS) Copies the content of RS to RD. CCR Effects Code and CPU Cycles MO V Move Register Content MOV NZ V C ∆∆ 0— N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; c[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 456 F reescale Semiconductor Operation –RS ⇒ RD (translates to SUB RD, R0, RS) –RD ⇒ RD (translates to SUB RD, R0, RD) Performs a two’ s complement on a general purpose register. CCR Effects Code and CPU Cycles NEG Two’s Complement NEG NZ V C ∆∆∆∆ N: Set if bit 1[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 457 Operation No Operation for one cycle. CCR Effects Code and CPU Cycles NOP No Operation NOP NZ V C ———— N: Not affected. Z: Not aff ected. V: Not aff ected. C: Not affected. Source Form Address Mode Machine Code Cycles N O P I N H 0000000100000000[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 458 F reescale Semiconductor Operation RS1 | RS2 ⇒ RDRD | IMM16 ⇒ RD (translates to ORL RD, #IMM16[7:0]; ORH RD, #IMM16[15:8] Performs a bit wise logical OR between two 16-bit v alues and stores the result in the destination register RD. CCR Effects Code and CPU Cycles OR Logica[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 459 Operation RD.H | IMM8 ⇒ RD.H Performs a bit wise logical OR between the high byte of register RD and an immediate 8-Bit constant and stores the result in the destination register RD.H. The lo w byte of RD is not affected. CCR Effects Code and CPU Cycle[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 460 F reescale Semiconductor Operation RD.L | IMM8 ⇒ RD.L Performs a bit wise logical OR between the lo w byte of register RD and an immediate 8-Bit constant and stores the result in the destination register RD.L. The high byte of RD is not af fected. CCR Effects Code and CPU Cycl[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 461 Operation Calculates the number of ones in the register RD. The Carry flag will be set if the number is odd, otherwise it will be cleared. CCR Effects Code and CPU Cycles PA R Calculate Parity PAR NZ V C 0 ∆ 0 ∆ N: 0; cleared. Z: Set if RD is $0000;[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 462 F reescale Semiconductor Operation n = RS or IMM4 Rotates the bits in register RD n positions to the left. The lo wer n bits of the register RD are filled with the upper n bits. T wo source forms are a vailable. In the first form, the parameter n is contained in the instructio[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 463 Operation n = RS or IMM4 Rotates the bits in register RD n positions to the right. The upper n bits of the register RD are filled with the lo wer n bits. T wo source forms are a v ailable. In the first form, the parameter n is contained in the instruct[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 464 F reescale Semiconductor Operation T erminates the current thread of program ex ecution and remains idle until a new thread is started by the hardware scheduler. CCR Effects Code and CPU Cycles RT S Return to Scheduler RTS NZ V C ———— N: Not affected. Z: Not aff ected. V[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 465 Operation RS1 - RS2 - C ⇒ RD Subtracts the content of register RS2 and the v alue of the Carry bit from the content of register RS1 using binary subtraction and stores the result in the destination re gister RD. Also the zero flag is carried forward f[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 466 F reescale Semiconductor Operation Attempts to set a semaphore. The state of the semaphore will be stored in the Carry-Flag: 1 = Semaphore is locked by the RISC core 0 = Semaphore is locked by the S12X_CPU In monadic address mode, bits RS[2:0] select the semaphore to be set. CCR[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 467 Operation The result in RD is the 16-bit sign extended representation of the original tw o’ s complement number in the lo w byte of RD.L. CCR Effects Code and CPU Cycles SEX Sign Extend Byte to Word SEX NZ V C ∆∆ 0— N: Set if bit 15 of the result[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 468 F reescale Semiconductor Operation Sets the Interrupt Flag of an XGA TE Channel. This instruction supports two source forms. If inherent address mode is used, then the interrupt flag of the current channel (XGCHID) will be set. If the monadic address form is used, the interrupt [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 469 Operation RS.L ⇒ M[RB, #OFFS5 ] RS.L ⇒ M[RB, RI ] RS.L ⇒ M[RB, RI]; RI+1 ⇒ RI; RI–1 ⇒ RI; RS.L ⇒ M[RB, RI] 1 Stores the lo w byte of register RD to memory. CCR Effects Code and CPU Cycles STB Store Byte to Memory (Low Byte) STB 1. If the sa[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 470 F reescale Semiconductor Operation RS ⇒ M[RB, #OFFS5 ] RS ⇒ M[RB, RI ] RS ⇒ M[RB, RI]; RI+2 ⇒ RI; RI–2 ⇒ RI; RS ⇒ M[RB, RI] 1 Stores the content of register RS to memory. CCR Effects Code and CPU Cycles STW Store Word to Memory STW 1. If the same general pur pose r[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 471 Operation RS1 – RS2 ⇒ RDRD − IMM16 ⇒ RD (translates to SUBL RD, #IMM16[7:0]; SUBH RD, #IMM[15:8]) Subtracts two 16-bit v alues and stores the result in the destination register RD. CCR Effects Code and CPU Cycles SUB Subtract without Carry SUB NZ[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 472 F reescale Semiconductor Operation RD – IMM8:$00 ⇒ RD Subtracts a signed immediate 8-Bit constant from the content of high byte of register RD and using binary subtraction and stores the result in the high byte of destination register RD. This instruction can be used after a[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 473 Operation RD – $00:IMM8 ⇒ RD Subtracts an immediate 8 Bit constant from the content of register RD using binary subtraction and stores the result in the destination register RD. CCR Effects Code and CPU Cycles SUBL Subtract Immediate 8-Bit Constant ([...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 474 F reescale Semiconductor Operation TFR RD,CCR: CCR ⇒ RD[3:0], 0 ⇒ RD[15:4] TFR CCR,RD: RD[3:0] ⇒ CCR TFR RD,PC: PC+4 ⇒ RD T ransfers the content of one RISC core register to another. The TFR RD,PC instruction can be used to implement relati ve subroutine calls. Example: [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 475 Operation RS – 0 ⇒ NONE (translates to SUB R0, RS, R0) Subtracts zero from the content of register RS using binary subtraction and discards the result. CCR Effects Code and CPU Cycles TST Test Register TST NZ V C ∆∆∆∆ N: Set if bit 15 of the [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 476 F reescale Semiconductor Operation ~(RS1 ^ RS2) ⇒ RD~(RD ^ IMM16) ⇒ RD (translates to XNOR RD, #IMM[15:8]; XNOR RD, #IMM16[7:0]) Performs a bit wise logical exclusi ve NOR between two 16-bit v alues and stores the result in the destination register RD. Remark: Using R0 as a [...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 477 Operation ~(RD.H ^ IMM8) ⇒ RD.H Performs a bit wise logical exclusi ve NOR between the high byte of re gister RD and an immediate 8-Bit constant and stores the result in the destination register RD.H. The lo w byte of RD is not affected. CCR Effects Co[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 478 F reescale Semiconductor Operation ~(RD.L ^ IMM8) ⇒ RD.L Performs a bit wise logical exclusi ve NOR between the lo w byte of register RD and an immediate 8-Bit constant and stores the result in the destination register RD.L. The high byte of RD is not af fected. CCR Effects Co[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 479 9.8.6 Instruction Coding T able 9-18 summarizes all XGA TE instructions in the order of their machine coding. T able 9-18. Instruction Set Summary (Sheet 1 of 3) Functionality 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Return to Scheduler and Others B R K 000[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 480 F reescale Semiconductor Logical T riadic AND RD , RS1, RS2 00010 R D R S 1 R S 2 00 OR RD , RS1, RS2 00010 R D R S 1 R S 2 10 XNOR RD , RS1, RS2 00010 R D R S 1 R S 2 11 Arithmetic T riadic F or compare use SUB R0,Rs1,Rs2 SUB RD , RS1, RS2 0 0 0 1 1 RD RS1 RS2 0 0 SBC RD , RS1,[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 481 ANDH RD , #IMM8 1 0 0 0 1 RD IMM8 BITL RD , #IMM8 1 0 0 1 0 RD IMM8 BITH RD , #IMM8 1 0 0 1 1 RD IMM8 ORL RD , #IMM8 1 0 1 0 0 RD IMM8 ORH RD , #IMM8 1 0 1 0 1 RD IMM8 XNORL RD , #IMM8 1 0 1 1 0 RD IMM8 XNORH RD , #IMM8 1 0 1 1 1 RD IMM8 Arithmetic Immed[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 482 F reescale Semiconductor 9.9 Initialization and Application Information 9.9.1 Initialization The recommended initialization of the XGA TE is as follows: 1. Clear the XGE bit to suppress any incoming service requests. 2. Make sure that no thread is running on the XGA TE. This can[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 483 XGCHID EQU XGATE_REGS+$02 ;XGATE Channel ID Register XGVBR EQU XGATE_REGS+$06 ;XGATE Vector Base Register XGIF EQU XGATE_REGS+$08 ;XGATE Interrupt Flag Vector XGSWT EQU XGATE_REGS+$18 ;XGATE Software Trigger Register XGSEM EQU XGATE_REGS+$1A ;XGATE Semap[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 484 F reescale Semiconductor STD 2,X+ STD 2,X+ MOVW #$FF00, XGSWT ;clear all software triggers ;########################################### ;# INITIALIZE XGATE VECTOR SPACE # ;########################################### INIT_XGATE_VECTOR_SPACE MOVB #(RAM_START_GLOBAL>>12), RPA[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 485 STB R4,(R2,#(SCIDRL-SCI_REGS)) ;initiate SCI transmit CMPL R4,#$0D BEQ XGATE_CODE_DONE RTS XGATE_CODE_DONE LDL R4,#$00 ;disable SCI interrupts STB R4,(R2,#(SCICR2-SCI_REGS)) LDL R3,#(XGATE_DATA_MSG-XGATE_DATA_BEGIN);reset R3 STB R3,(R1,#(XGATE_DATA_MSG_I[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 486 F reescale Semiconductor[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 487[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 488 F reescale Semiconductor[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 489[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 490 F reescale Semiconductor[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 491[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 492 F reescale Semiconductor[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 493[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 494 F reescale Semiconductor[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 495[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 496 F reescale Semiconductor[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 497[...]

Chapter 9 XGA TE (S12XGA TEV2) MC9S12XDP512 Data Sheet, Rev . 2.11 498 F reescale Semiconductor[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 499 Chapter 10 Security (S12X9SECV2) 10.1 Intr oduction This specification describes the function of the security mechanism in the S12X chip family (MC9S12XDP512). 10.1.1 Features The user must be reminded that part of the security must lie with the application code. An extreme e xample [...]

Chapter 10 Security (S12X9SECV2) MC9S12XDP512 Data Sheet, Rev . 2.11 500 F reescale Semiconductor 10.1.2 Modes of Operation 10.1.3 Securing the Micr ocontr oller Once the user has programmed the Flash and EEPR OM, the chip can be secured by programming the security bits located in the options/security byte in the Flash memory array. These non-v ola[...]

Chapter 10 Security (S12X9SECV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 501 The meaning of the bits KEYEN[1:0] is sho wn in T able 10-2 . Please refer to Section 10.1.5.1, “Unsecuring the MCU Using the Backdoor K ey Access” for more information. The meaning of the security bits SEC[1:0] is sho wn in T able 10-3 . For secur[...]

Chapter 10 Security (S12X9SECV2) MC9S12XDP512 Data Sheet, Rev . 2.11 502 F reescale Semiconductor 10.1.4.1 Normal Single Chip Mode (NS) • Background debug module (BDM) operation is completely disabled. • Execution of Flash and EEPR OM commands is restricted. Please refer to the NVM block guide (FTX) for details. • T racing code execution usin[...]

Chapter 10 Security (S12X9SECV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 503 10.1.5 Unsecuring the Micr ocontr oller Unsecuring the microcontroller can be done by three dif ferent methods: 1. Backdoor ke y access 2. Reprogramming the security bits 3. Complete memory erase (special modes) 10.1.5.1 Unsecuring the MCU Using the Ba[...]

Chapter 10 Security (S12X9SECV2) MC9S12XDP512 Data Sheet, Rev . 2.11 504 F reescale Semiconductor If all four 16-bit words match the Flash contents at 0xFF00–0xFF07 (0x7F_FF00–0x7F_FF07), the microcontroller will be unsecured and the security bits SEC[1:0] in the Flash Security register FSEC will be forced to the unsecured state (‘10’). The[...]

Chapter 10 Security (S12X9SECV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 505 Special single chip erase and unsecure sequence: 1. Reset into special single chip mode. 2. Write an appropriate v alue to the ECLKDIV register for correct timing. 3. Write 0xFF to the EPR O T register to disable protection. 4. Write 0x30 to the EST A [...]

Chapter 10 Security (S12X9SECV2) MC9S12XDP512 Data Sheet, Rev . 2.11 506 F reescale Semiconductor[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 507 Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.1 Intr oduction The HCS12 enhanced capture timer module has the features of the HCS12 standard timer module enhanced by additional features in order to enlarge the field of applications, in particular for automoti ve ABS a[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 508 F reescale Semiconductor 11.1.3 Bloc k Diagram Figure 11-1. ECT Block Dia gram Prescaler 16-bit Counter 16-Bit Pulse Accumulator B IOC0 IOC2 IOC1 IOC5 IOC3 IOC4 IOC6 IOC7 PA Input Interrupt PA Overflow Interrupt Timer Overflow Interrupt Timer Channel [...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 509 11.2 External Signal Description The ECT module has a total of eight external pins. 11.2.1 IOC7 — Input Capture and Output Compare Channel 7 This pin serves as input capture or output compare for channel 7. 11.2.2 IOC6 — I[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 510 F reescale Semiconductor 11.3 Memory Map and Register Definition This section provides a detailed description of all memory and re gisters. 11.3.1 Module Memory Map The memory map for the ECT module is gi ven belo w in T able 11-1 . The address liste[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 511 0x001E Timer Input Capture/Output Compare Register 7 High (TC7) R/W 3 0x001F Timer Input Capture/Output Compare Register 7 Low (TC7) R/W 3 0x0020 16-Bit Pulse Accumulator A Control Register (P A CTL) R/W 0x0021 Pulse Accumulat[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 512 F reescale Semiconductor 11.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard re gister diagram with an associated figure number. Details of register bit and field functio[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 513 0x000D TSCR2 R TO I 000 TCRE PR2 PR1 PR0 W 0x000E TFLG1 R C7F C6F C5F C4F C3F C2F C1F C0F W 0x000F TFLG2 R TO F 00000 0 0 W 0x0010 TC0 (High) R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x0011 TC0 (Low) R Bit 7 B[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 514 F reescale Semiconductor 0x001C TC6 (High) R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x001D TC6 (Low) R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x001E TC7 (High) R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x001[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 515 0x002B ICSYS R SH37 SH26 SH15 SH04 TFMOD P ACMX BUFEN LA TQ W 0x002C Reser ved R Reser ved W 0x002D TIMTST R Timer T est Register W 0x002E PTPSR R PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 W 0x002F PTMCPSR R PTMPS7 PTMPS[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 516 F reescale Semiconductor 11.3.2.1 Timer Input Capture/Output Compare Select Register (TIOS) Read or write: Anytime All bits reset to zero. 0x003A TC1H (High) R TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 W 0x003B TC1H (Low) R TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 517 11.3.2.2 Timer Compare Force Register (CFORC) Read or write: Anytime b ut reads will always return 0x0000 (1 state is transient). All bits reset to zero. 11.3.2.3 Output Compare 7 Mask Register (OC7M) Read or write: Anytime Al[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 518 F reescale Semiconductor 11.3.2.4 Output Compare 7 Data Register (OC7D) Read or write: Anytime All bits reset to zero. Module Base + 0x0003 76543210 R OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 W Reset 00000000 Figure 11-6. Output Compare 7 Data [...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 519 11.3.2.5 Timer Count Register (TCNT) Read: Anytime Write: Has no meaning or ef fect All bits reset to zero. Module Base + 0x0004 15 14 13 12 11 10 9 8 R TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 W Reset 00000000 Fi[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 520 F reescale Semiconductor 11.3.2.6 Timer System Control Register 1 (TSCR1) Read or write: Anytime e xcept PRNT bit is write once All bits reset to zero. Module Base + 0x0006 76543210 R TEN TSW AI TSFRZ TFFCA PRNT 000 W Reset 00000000 = Unimplemented or[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 521 11.3.2.7 Timer T oggle On Overflo w Register 1 (TT O V) Read or write: Anytime All bits reset to zero. Module Base + 0x0007 76543210 R T OV7 T O V6 TO V5 TO V4 TO V3 T OV2 T O V1 TO V0 W Reset 00000000 Figure 11-10. Timer T o[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 522 F reescale Semiconductor 11.3.2.8 Timer Control Register 1/Timer Contr ol Register 2 (TCTL1/TCTL2) Read or write: Anytime All bits reset to zero. NO TE T o enable output action by OMx and OLx bits on timer port, the corresponding bit in OC7M should be[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 523 11.3.2.9 Timer Control Register 3/Timer Contr ol Register 4 (TCTL3/TCTL4) Read or write: Anytime All bits reset to zero. Module Base + 0x000A 76543210 R EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A W Reset 00000000 Figure 1[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 524 F reescale Semiconductor 11.3.2.10 Timer Interrupt Enable Register (TIE) Read or write: Anytime All bits reset to zero. The bits C7I–C0I correspond bit-for -bit with the flags in the TFLG1 status register. Module Base + 0x000C 76543210 R C7I C6I C5[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 525 11.3.2.11 Timer System Control Register 2 (TSCR2) Read or write: Anytime All bits reset to zero. Module Base + 0x000D 76543210 R TO I 000 TCRE PR2 PR1 PR0 W Reset 00000000 = Unimplemented or Reser ved Figure 11-16. Timer Syste[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 526 F reescale Semiconductor 11.3.2.12 Main Timer Interrupt Flag 1 (TFLG1) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not af fect the current status of the bit. NO TE When TFF[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 527 11.3.2.13 Main Timer Interrupt Flag 2 (TFLG2) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not af fect the current status of the bit. NO TE When TFF[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 528 F reescale Semiconductor 11.3.2.14 Timer Input Capture/Output Compare Registers 0–7 Module Base + 0x0010 15 14 13 12 11 10 9 8 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W Reset 00000000 Figure 11-19. Timer Input Capture/Output Compare [...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 529 Module Base + 0x0016 15 14 13 12 11 10 9 8 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W Reset 00000000 Figure 11-25. Timer Input Capture/Output Compare Register 3 High (TC3) Module Base + 0x0017 76543210 R Bit 7 B[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 530 F reescale Semiconductor Read: Anytime Write anytime for output compare function. Writes to these re gisters have no meaning or ef fect during input capture. All bits reset to zero. Depending on the TIOS bit for the corresponding channel, these regist[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 531 11.3.2.15 16-Bit Pulse Accumulator A Contr ol Register (P A CTL) Read: Anytime Write: Anytime All bits reset to zero. Module Base + 0x0020 76543210 R0 P AEN P AMOD PEDGE CLK1 CLK0 P A O VI P AI W Reset 00000000 = Unimplemented[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 532 F reescale Semiconductor . 11.3.2.16 Pulse Accumulator A Flag Register (P AFLG) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not af fect the current status of the bit. NO TE[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 533 P AFLG indicates when interrupt conditions hav e occurred. The flags can be cleared via the normal flag clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA bit in Section[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 534 F reescale Semiconductor When clocking pulse and write to the registers occurs simultaneously , write takes priority and the re gister is not incremented. 11.3.2.18 Pulse Accumulator s Count Registers (P A CN1 and P A CN0) Read: Anytime Write: Anytime[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 535 11.3.2.19 16-Bit Modulus Down-Counter Contr ol Register (MCCTL) Read: Anytime Write: Anytime All bits reset to zero. Module Base + 0x0026 76543210 R MCZI MODMC RDMCL 00 MCEN MCPR1 MCPR0 W ICLA T FLMC Reset 00000000 Figure 11-4[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 536 F reescale Semiconductor 11.3.2.20 16-Bit Modulus Down-Counter FLA G Register (MCFLG) Read: Anytime Write only used in the flag clearing mechanism for bit 7. Writing a one to bit 7 clears the flag. Writing a zero will not af fect the current status [...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 537 11.3.2.21 ICP AR — Input Control Pulse Accum ulators Register (ICP AR) Read: Anytime Write: Anytime. All bits reset to zero. The 8-bit pulse accumulators P A C3 and P A C2 can be enabled only if P AEN in P A CTL is cleared. [...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 538 F reescale Semiconductor 11.3.2.22 Delay Counter Contr ol Register (DL YCT) Read: Anytime Write: Anytime All bits reset to zero. Module Base + 0x0029 76543210 R DL Y7 DL Y6 DL Y5 DL Y4 DL Y3 DL Y2 DL Y1 DL Y0 W Reset 00000000 Figure 11-44. Delay Count[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 539 11.3.2.23 Input Control Overwrite Register (ICO VW) Read: Anytime Write: Anytime All bits reset to zero. 11111111 1024 b us clock cycles Module Base + 0x002A 76543210 R NO VW7 NO VW6 NO VW5 NO VW4 NO VW3 NO VW2 NO VW1 NO VW0 W[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 540 F reescale Semiconductor 11.3.2.24 Input Control System Contr ol Register (ICSYS) Read: Anytime Write: Once in normal modes All bits reset to zero. Module Base + 0x002B 76543210 R SH37 SH26 SH15 SH04 TFMOD P ACMX BUFEN LA TQ W Reset 00000000 Figure 11[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 541 11.3.2.25 Precision Timer Prescaler Select Register (PTPSR) Read: Anytime Write: Anytime All bits reset to zero. 0 LA TQ Input Control Latc h or Queue Mode Enable — The BUFEN control bit should be set in order to enab le the[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 542 F reescale Semiconductor 11.3.2.26 Precision Timer Modulus Counter Prescaler Select Register (PTMCPSR) Read: Anytime Write: Anytime All bits reset to zero. 00000110 7 00000111 8 00001111 1 6 00011111 3 2 00111111 6 4 01111111 1 2 8 11111111 2 5 6 Modu[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 543 11.3.2.27 16-Bit Pulse Accumulator B Contr ol Register (PBCTL) Read: Anytime Write: Anytime All bits reset to zero. 000001016 000001107 000001118 00001111 1 6 00011111 3 2 00111111 6 4 01111111 1 2 8 11111111 2 5 6 Module Base[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 544 F reescale Semiconductor 11.3.2.28 Pulse Accumulator B Flag Register (PBFLG) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not af fect the current status of the bit. NO TE Wh[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 545 11.3.2.29 8-Bit Pulse Accumulator s Holding Registers (P A3H–P A0H) Read: Anytime. Write: Has no ef fect. All bits reset to zero. These registers are used to latch the v alue of the corresponding pulse accumulator when the r[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 546 F reescale Semiconductor 11.3.2.30 Modulus Down-Counter Count Register (MCCNT) Read: Anytime Write: Anytime. All bits reset to one. A full access for the counter register will tak e place in one clock cycle. NO TE A separate read/write for high byte a[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 547 11.3.2.31 Timer Input Capture Holding Registers 0–3 (TCxH) Module Base + 0x0038 15 14 13 12 11 10 9 8 R TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 W Reset 00000000 = Unimplemented or Reser ved Figure 11-57. Timer Input Capture Ho[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 548 F reescale Semiconductor Read: Anytime Write: Has no ef fect. All bits reset to zero. These registers are used to latch the v alue of the input capture registers TC0–TC3. The corresponding IOSx bits in TIOS should be cleared (see Section 11.4.1.1, ?[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 549 Figure 11-65. Detailed Timer Block Dia gram in Latch Mode when PRNT = 0 16 BIT MAIN TIMER P1 Comparator TC0H Hold Reg. P0 P3 P2 P4 P5 P6 P7 EDG0 EDG1 EDG2 EDG3 MUX Modulus Prescaler Bus Clock 16-Bit Load Register 16-Bit Modulu[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 550 F reescale Semiconductor Figure 11-66. Detailed Timer Block Dia gram in Latch Mode when PRNT = 1 16 BIT MAIN TIMER P1 Comparator TC0H Hold Reg. P0 P3 P2 P4 P5 P6 P7 EDG0 EDG1 EDG2 EDG3 MUX Modulus Prescaler Bus Clock 16-Bit Load Register 16-Bit Modulu[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 551 Figure 11-67. Detailed Timer Block Dia gram in Queue Mode when PRNT = 0 16 BIT MAIN TIMER P1 TC0H Hold Reg. P0 P3 P2 P4 P5 P6 P7 EDG0 EDG1 EDG2 EDG3 MUX Bus Clock 16-Bit Load Register 16-Bit Modulus 0 RESET EDG0 EDG1 EDG2 EDG4[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 552 F reescale Semiconductor Figure 11-68. Detailed Timer Block Dia gram in Queue Mode when PRNT = 1 16 BIT MAIN TIMER P1 TC0H Hold Reg. P0 P3 P2 P4 P5 P6 P7 EDG0 EDG1 EDG2 EDG3 MUX Bus Clock 16-Bit Load Register 16-Bit Modulus 0 RESET EDG0 EDG1 EDG2 EDG4[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 553 Figure 11-69. 8-Bit Pulse Accumulator s Block Dia gram P0 Load Holding Register and Reset Pulse Accumulator 0 0 EDG3 EDG2 EDG1 EDG0 Edge Detector Dela y Counter Interrupt Interrupt P1 Edge Detector Dela y Counter P2 Edge Detec[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 554 F reescale Semiconductor Figure 11-70. 16-Bit Pulse Accumulator s Block Dia gram Figure 11-71. Block Dia gram for P ort 7 with Output Compare/Pulse Accumulator A Edge Detector P7 P0 Bus Clock Divide by 64 Clock Select CLK0 CLK1 4:1 MUX TIMCLK (Timer C[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 555 11.4.1 Enhanced Capture Timer Modes of Operation The enhanced capture timer has 8 input capture, output compare (IC/OC) channels, same as on the HC12 standard timer (timer channels TC0 to TC7). When channels are selected as in[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 556 F reescale Semiconductor If the corresponding NO VWx bit of the ICO VW register is set, the capture register or its holding register cannot be written by an e vent unless the y are empty (see Section 11.4.1.1, “IC Channels” ). This will pre vent t[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 557 11.4.1.2 OC Channel Initialization Internal register whose output dri ves OCx when TIOS is set, can be force loaded with a desired data by writing to CFORC register before OCx is configured for output compare action. This all[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 558 F reescale Semiconductor 11.4.1.6 Flag Clearing Mechanisms The flags in the ECT can be cleared one of two w ays: 1. Normal flag clearing mechanism (TFFCA = 0) Any of the ECT flags can be cleared by writing a one to the flag. 2. Fast flag clearing[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 559 11.4.3 Interrupts This section describes interrupts originated by the ECT block. The MCU must service the interrupt requests. T able 11-37 lists the interrupts generated by the ECT to communicate with the MCU. T able 11-37. EC[...]

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev . 2.11 560 F reescale Semiconductor[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 561 Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) 12.1 Intr oduction The PWM definition is based on the HC12 PWM definitions. It contains the basic features from the HC11 with some of the enhancements incorporated on the HC12: center aligned output mode and four a vailable clock sourc[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 562 F reescale Semiconductor 12.1.3 Bloc k Diagram Figure 12-1 sho ws the block diagram for the 8-bit 8-channel PWM block. Figure 12-1. PWM Block Dia gram 12.2 External Signal Description The PWM module has a total of 8 external pins. 12.2.1 PWM7 — PWM Channel 7 T[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 563 12.2.3 PWM5 — PWM Channel 5 This pin serves as w av eform output of PWM channel 5. 12.2.4 PWM4 — PWM Channel 4 This pin serves as w av eform output of PWM channel 4. 12.2.5 PWM3 — PWM Channel 3 This pin serves as w av eform output [...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 564 F reescale Semiconductor NO TE Register Address = Base Address + Address Of fset, where the Base Address is defined at the MCU le vel and the Address Of fset is defined at the module le vel. 12.3.2 Register Descriptions This section describes in detail all the[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 565 0x000B PWMSCNTB 1 R 00 0 00000 W 0x000C PWMCNT0 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 0x000D PWMCNT1 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 0x000E PWMCNT2 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 0x000F PWMCNT3 R Bit 7 6 5 4 3 2 1 Bit 0 W[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 566 F reescale Semiconductor 12.3.2.1 PWM Enable Register (PWME) Each PWM channel has an enable bit (PWMEx) to start its wa veform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output is enabled immediately. Howe ver , the actual PWM wa [...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 567 An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the lo w order PWMEx bit.In this case[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 568 F reescale Semiconductor 12.3.2.2 PWM P olarity Register (PWMPOL) The starting polarity of each PWM channel wa veform is determined by the associated PPOLx bit in the PWMPOL register. If the polarity bit is one, the PWM channel output is high at the be ginning o[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 569 Read: Anytime Write: Anytime NO TE Register bits PCLK0 to PCLK7 can be written an ytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. 12.3.2.4 PWM Pre[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 570 F reescale Semiconductor Read: Anytime Write: Anytime NO TE PCKB2–0 and PCKA2–0 register bits can be written an ytime. If the clock pre-scale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. s [...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 571 12.3.2.5 PWM Center Align Enable Register (PWMCAE) The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned outputs for each PWM channel. If the CAEx bit is set to a one, the correspondi[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 572 F reescale Semiconductor 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. See Section 12.4.2.7, “PWM 16-Bit Functions” for [...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 573 12.3.2.7 Reser ved Register (PWMTST) This register is reserv ed for factory testing of the PWM module and is not av ailable in normal modes. Read: Always read $00 in normal modes Write: Unimplemented in normal modes NO TE Writing to this[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 574 F reescale Semiconductor NO TE When PWMSCLA = $00, PWMSCLA v alue is considered a full scale value of 256. Clock A is thus di vided by 512. Any v alue written to this register will cause the scale counter to load the ne w scale value (PWMSCLA). Read: Anytime Wri[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 575 Read: Always read $00 in normal modes Write: Unimplemented in normal modes NO TE Writing to these registers when in special modes can alter the PWM functionality . 12.3.2.12 PWM Channel Counter Registers (PWMCNTx) Each channel has a dedi[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 576 F reescale Semiconductor Write: Anytime (an y value written causes PWM counter to be reset to $00). 12.3.2.13 PWM Channel Period Register s (PWMPERx) There is a dedicated period register for each channel. The v alue in this register determines the period of the [...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 577 12.3.2.14 PWM Channel Duty Registers (PWMDTYx) There is a dedicated duty register for each channel. The v alue in this register determines the duty of the associated PWM channel. The duty v alue is compared to the counter and if it is eq[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 578 F reescale Semiconductor Write: Anytime 12.3.2.15 PWM Shutdown Register (PWMSDN) The PWMSDN register pro vides for the shutdown functionality of the PWM module in the emer gency cases. For proper operation, channel 7 must be dri ven to the acti ve le vel for a m[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 579 12.4 Functional Description 12.4.1 PWM Cloc k Select There are four a vailable clocks: clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These four clocks are based on the b us clock. Clock A and B can be software selected [...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 580 F reescale Semiconductor Figure 12-18. PWM Clock Select Bloc k Diagram 128 2 4 8 16 32 64 PCKB2 PCKB1 PCKB0 M U X Clock A Clock B Clock SA Clock A/2, A/4, A/6,....A/512 Prescale Scale Divide by PFRZ F reeze Mode Signal Bus Clock Clock Select M U X PCLK0 Clock to[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 581 Clock A is used as an input to an 8-bit do wn counter. This do wn counter loads a user programmable scale v alue from the scale register (PWMSCLA). When the do wn counter reaches one, a pulse is output and the 8-bit counter is re-loaded.[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 582 F reescale Semiconductor 12.4.2 PWM Channel Timer s The main part of the PWM module are the actual timers. Each of the timer channels has a counter , a period register and a duty re gister (each are 8-bit). The wa veform output period is controlled by a match be[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 583 On the front end of the PWM timer , the clock is enabled to the PWM circuit by the PWMEx bit being high. There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge. When the channel is [...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 584 F reescale Semiconductor Each channel counter can be read at anytime without af fecting the count or the operation of the PWM channel. Any v alue written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 585 NO TE Changing the PWM output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irre gularities in the PWM output. It is recommended to program the output mode before enabling the PWM [...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 586 F reescale Semiconductor Figure 12-21. PWM Left Aligned Output Example W aveform 12.4.2.6 Center Aligned Outputs For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE re gister and the corresponding PWM output will be center aligned[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 587 T o calculate the output frequenc y in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and di vide it by twice the value in the period register for that chan[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 588 F reescale Semiconductor As an example of a center aligned output, consider the follo wing case: Clock Source = E, where E = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx Frequency = 10 MHz/8 = 1.25 MHz PWMx Period = 800 ns PWMx Duty Cycle = 3/4 [...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 589 Figure 12-24. PWM 16-Bit Mode Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the lo w order PWMEx bit. In this case, the high order bytes PW[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 590 F reescale Semiconductor Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by the lo w order CAEx bit. The high order CAEx bit has no ef fect. T able 12-11 is used to summarize which channels are used to set the[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 591 12.6 Interrupts The PWM module has only one interrupt which is generated at the time of emergenc y shutdown, if the corresponding enable bit (PWMIE) is set. This bit is the enable for the interrupt. The interrupt flag PWMIF is set whene[...]

Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 592 F reescale Semiconductor[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 593 Chapter 13 Inter -Integrated Circuit (MC9S12XDP512) Bloc k Description 13.1 Intr oduction The inter-IC b us (IIC) is a two-wire, bidirectional serial bus that pro vides a simple, efficient method of data exchange between de vices. Being a two-wire de vice, the IIC bus minimizes the n[...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 594 F reescale Semiconductor 13.1.2 Modes of Operation The IIC functions the same in normal, special, and emulation modes. It has two lo w power modes: w ait and stop modes. 13.1.3 Bloc k Diagram The block diagram of the IIC module is sho wn in[...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 595 13.2 External Signal Description The MC9S12XDP512 module has two e xternal pins. 13.2.1 IIC_SCL — Serial Cloc k Line Pin This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC b us [...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 596 F reescale Semiconductor 13.3.2 Register Descriptions This section consists of register descriptions in address order . Each description includes a standard register diagram with an associated figure number . Details of register bit and ?[...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 597 13.3.2.2 IIC Frequency Divider Register (IBFD) Read and write anytime T able 13-2. IB AD Field Descriptions Field Description 7:1 ADR[7:1] Slave Address — Bit 1 to bit 7 contain the specific sla ve address to be [...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 598 F reescale Semiconductor The number of clocks from the falling edge of SCL to the first tap (T ap[1]) is defined by the values sho wn in the scl2tap column of T able 13-4 , all subsequent tap points are separated by 2 IBC5-3 as shown in t[...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 599 Figure 13-5. SCL Divider and SD A Hold The equation used to generate the di vider v alues from the IBFD bits is: SCL Divider = MUL x {2 x (scl2tap + [(SCL_T ap -1) x tap2tap] + 2)} The SD A hold delay is equal to th[...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 600 F reescale Semiconductor 11 56 9 22 29 12 64 13 26 33 13 72 13 30 37 14 80 17 34 41 15 88 17 38 45 16 104 21 46 53 17 128 21 58 65 18 80 9 38 41 19 96 9 46 49 1A 112 17 54 57 1B 128 17 62 65 1C 144 25 70 73 1D 160 25 78 81 1E 192 33 94 97 1[...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 601 3E 3072 513 1534 1537 3F 3840 513 1918 1921 MUL=2 40 40 14 12 22 41 44 14 14 24 42 48 16 16 26 43 52 16 18 28 44 56 18 20 30 45 60 18 22 32 46 68 20 26 36 47 80 20 32 42 48 56 14 20 30 49 64 14 24 34 4A 72 18 28 38 [...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 602 F reescale Semiconductor 6A 896 130 444 450 6B 1024 130 508 514 6C 1152 194 572 578 6D 1280 194 636 642 6E 1536 258 764 770 6F 1920 258 956 962 70 1280 130 636 642 71 1536 130 764 770 72 1792 258 892 898 73 2048 258 1020 1026 74 2304 386 11[...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 603 96 416 84 184 212 97 512 84 232 260 98 320 36 152 164 99 384 36 184 196 9A 448 68 216 228 9B 512 68 248 260 9C 576 100 280 292 9D 640 100 312 324 9E 768 132 376 388 9F 960 132 472 484 A0 640 68 312 324 A1 768 68 376[...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 604 F reescale Semiconductor 13.3.2.3 IIC Control Register (IBCR) Read and write anytime Offset Module Base + 0x0002 76543210 R IBEN IBIE MS/SL Tx/Rx TXAK 00 IBSW AI W RST A Reset 00000000 = Unimplemented or Reser ved Figure 13-6. IIC Bus Contr[...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 605 W ait mode is entered via e xecution of a CPU W AI instruction. In the e vent that the IBSW AI bit is set, all clocks internal to the IIC will be stopped and any transmission currently in progress will halt.If the C[...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 606 F reescale Semiconductor 6 IAAS Addressed as a Slave Bit — When its own specific address (I-bus address register) is matched with the calling address, this bit is set.The CPU is interrupted provided the IBIE is set.Then the CPU needs to [...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 607 13.3.2.5 IIC Data I/O Register (IBDR) In master transmit mode, when data is written to the IBDR a data transfer is initiated. The most significant bit is sent first. In master recei ve mode, reading this re gister[...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 608 F reescale Semiconductor Figure 13-9. IIC-Bus T ransmission Signals 13.4.1.1 ST ART Signal When the bus is free, i.e. no master de vice is engaging the bus (both SCL and SD A lines are at logical high), a master may initiate communication b[...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 609 13.4.1.2 Slave Address T ransmission The first byte of data transfer immediately after the ST AR T signal is the slave address transmitted by the master . This is a sev en-bit calling address follo wed by a R/W bit[...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 610 F reescale Semiconductor 13.4.1.5 Repeated ST ART Signal As sho wn in Figure 13-9 , a repeated ST AR T signal is a ST AR T signal generated without first generating a STOP signal to terminate the communication. This is used by the master t[...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 611 13.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer . Slav e devices may hold the SCL lo w after completion of one byte transfer (9 bits). In such case, it halts the [...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 612 F reescale Semiconductor IIC Interrupt can be generated on 1. Arbitration lost condition (IB AL bit set) 2. Byte transfer condition (TCF bit set) 3. Address detect condition (IAAS bit set) The IIC interrupt is enabled by the IBIE bit in the[...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 613 13.7.1.3 P ost-T ransfer Software Response T ransmission or reception of a byte will set the data transferring bit (TCF) to 1, which indicates one byte communication is finished. The IIC bus interrupt bit (IBIF) is[...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 614 F reescale Semiconductor 13.7.1.5 Generation of Repeated ST ART At the end of data transfer , if the master continues to want to communicate on the b us, it can generate another ST AR T signal followed by another sla ve address without fir[...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 615 Figure 13-12. Flow-Chart of T ypical IIC Interrupt Routine Clear Master Mode ? Tx/Rx ? Last Byte Transmitted ? RXAK=0 ? End Of Addr Cycle (Master Rx) ? Write Next Byte To IBDR Switch To Rx Mode Dummy Read From IBDR [...]

Chapter 13 Inter-Integrated Cir cuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev . 2.11 616 F reescale Semiconductor[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 617 Chapter 14 Freescale’ s Scalable Contr oller Area Network (S12MSCANV3) 14.1 Intr oduction Freescale’ s scalable controller area network (S12MSCANV3) definition is based on the MSCAN12 definition, which is the specific implementation of the MSCAN concept targeted for the M68HC12[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 618 F reescale Semiconductor 14.1.2 Bloc k Diagram Figure 14-1. MSCAN Block Dia gram 14.1.3 Features The basic features of the MSCAN are as follo ws: • Implementation of the CAN protocol — V ersion 2.0A/B — Standard and extended data f[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 619 • Three lo w-po wer modes: sleep, po wer do wn, and MSCAN enable • Global initialization of configuration registers 14.1.4 Modes of Operation The follo wing modes of operation are specific to the MSCAN. See[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 620 F reescale Semiconductor Figure 14-2. CAN System 14.3 Memory Map and Register Definition This section provides a detailed description of all re gisters accessible in the MSCAN. 14.3.1 Module Memory Map T able 14-1 gi ves an ov erview on[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 621 T able 14-1. MSCAN Memory Map Offset Address Register Access 0x0000 MSCAN Control Register 0 (CANCTL0) R/W 1 1 Ref er to detailed register description for write access restrictions on per bit basis. 0x0001 MSCAN [...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 622 F reescale Semiconductor 14.3.2 Register Descriptions This section describes in detail all the registers and re gister bits in the MSCAN module. Each description includes a standard register diagram with an associated figure number. Det[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 623 3 TIME Timer Enable — This bit activ ates an inter nal 16-bit wide free running timer which is clocked b y the bit clock r ate. If the timer is enabled, a 16-bit time stamp will be assigned to each tr ansmitted[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 624 F reescale Semiconductor 14.3.2.2 MSCAN Control Register 1 (CANCTL1) The CANCTL1 register pro vides various control bits and handshake status information of the MSCAN module as described belo w . Read: Anytime Write: Anytime when INITRQ [...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 625 2 WUPM W ake-Up Mode — If WUPE in CANCTL0 is enabled, this bit defines whether the integrated lo w-pass filter is applied to protect the MSCAN from spurious wake-up (see Section 14.4.6.4, “MSCAN Sleep Mode [...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 626 F reescale Semiconductor 14.3.2.3 MSCAN Bus Timing Register 0 (CANBTR0) The CANBTR0 register configures v arious CAN bus timing parameters of the MSCAN module. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INIT AK [...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 627 14.3.2.4 MSCAN Bus Timing Register 1 (CANBTR1) The CANBTR1 register configures v arious CAN bus timing parameters of the MSCAN module. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INIT AK [...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 628 F reescale Semiconductor The bit time is determined by the oscillator frequency , the baud rate prescaler , and the number of time quanta (Tq) clock cycles per bit (as sho wn in T able 14-8 and T able 14-9 ). Eqn. 14-1 14.3.2.5 MSCAN Rec[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 629 T able 14-10. CANRFLG Register Field Descriptions Field Description 7 WUPIF W ake-Up Interrupt Flag — If the MSCAN detects CAN bus activity while in sleep mode (see Section 14.4.6.4, “MSCAN Sleep Mode , ”) [...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 630 F reescale Semiconductor 14.3.2.6 MSCAN Receiver Interrupt Enable Register (CANRIER) This register contains the interrupt enable bits for the interrupt flags described in the CANRFLG re gister. NO TE The CANRIER register is held in the [...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 631 14.3.2.7 MSCAN T ransmitter Flag Register (CANTFLG) The transmit buf fer empty flags each hav e an associated interrupt enable bit in the CANTIER register. NO TE The CANTFLG register is held in the reset state w[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 632 F reescale Semiconductor 14.3.2.8 MSCAN T ransmitter Interrupt Enable Register (CANTIER) This register contains the interrupt enable bits for the transmit b uffer empty interrupt flags. NO TE The CANTIER register is held in the reset st[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 633 14.3.2.9 MSCAN T ransmitter Message Abort Request Register (CANT ARQ) The CANT ARQ register allo ws abort request of queued messages as described below. NO TE The CANT ARQ register is held in the reset state when[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 634 F reescale Semiconductor 14.3.2.10 MSCAN T ransmitter Message Abor t Ac knowledge Register (CANT AAK) The CANT AAK register indicates the successful abort of a queued message, if requested by the appropriate bits in the CANT ARQ register[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 635 14.3.2.11 MSCAN T ransmit Buffer Selection Register (CANTBSEL) The CANTBSEL register allo ws the selection of the actual transmit message buf fer , which then will be accessible in the CANTXFG register space. NO [...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 636 F reescale Semiconductor 14.3.2.12 MSCAN Identifier Acceptance Control Register (CANID A C) The CANID A C register is used for identifier acceptance control as described belo w. Read: Anytime Write: Anytime in initialization mode (INIT[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 637 The IDHITx indicators are always related to the message in the fore ground buf fer (RxFG). When a message gets shifted into the foreground b uffer of the recei ver FIFO the indicators are updated as well. 14.3.2.[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 638 F reescale Semiconductor 14.3.2.15 MSCAN Receive Error Counter (CANRXERR) This register reflects the status of the MSCAN recei ve error counter. Read: Only when in sleep mode (SLPRQ = 1 and SLP AK = 1) or initialization mode (INITRQ = 1[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 639 14.3.2.16 MSCAN T ransmit Err or Counter (CANTXERR) This register reflects the status of the MSCAN transmit error counter. Read: Only when in sleep mode (SLPRQ = 1 and SLP AK = 1) or initialization mode (INITRQ [...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 640 F reescale Semiconductor 14.3.2.17 MSCAN Identifier Acceptance Registers (CANID AR0-7) On reception, each message is written into the background recei ve b uffer. The CPU is only signalled to read the message if it passes the criteria i[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 641 Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INIT AK = 1) Module Base + 0x0018 (CANIDAR4) 0x0019 (CANID AR5) 0x001A (CANID AR6) 0x001B (CANID AR7) 76543210 R AC 7 AC 6 AC 5 AC4 AC 3 AC 2 AC[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 642 F reescale Semiconductor 14.3.2.18 MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7) The identifier mask register specifies which of the corresponding bits in the identifier acceptance re gister are rele v ant for acceptance fil[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 643 Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INIT AK = 1) Module Base + 0x001C (CANIDMR4) 0x001D (CANIDMR5) 0x001E (CANIDMR6) 0x001F (CANIDMR7) 76543210 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W [...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 644 F reescale Semiconductor 14.3.3 Pr ogrammer’ s Model of Message Storage The follo wing section details the organization of the recei ve and transmit message b uffers and the associated control registers. T o simplify the programmer int[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 645 Read: For transmit b uffers, an ytime when TXEx flag is set (see Section 14.3.2.7, “MSCAN T ransmitter Flag Register (CANTFLG) ”) and the corresponding transmit b uffer is selected in CANTBSEL (see Section 1[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 646 F reescale Semiconductor Write: For transmit b uffers, an ytime when TXEx flag is set (see Section 14.3.2.7, “MSCAN T ransmitter Flag Register (CANTFLG) ”) and the corresponding transmit b uffer is selected in CANTBSEL (see Section [...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 647 Module Base + 0x00X1 76543210 R ID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15 W Reset: xxxxxxxx Figure 14-26. Identifier Register 1 (IDR1) — Extended Identifier Mapping T able 14-27. IDR1 Register Field Des[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 648 F reescale Semiconductor 14.3.3.1.2 IDR0–IDR3 f or Standard Identifier Mapping Module Base + 0x00X3 76543210 R ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR W Reset: xxxxxxxx Figure 14-28. Identifier Register 3 (IDR3) — Extended Identifier Mapp[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 649 Module Base + 0x00X1 76543210 R ID2 ID1 ID0 RTR IDE (=0) W Reset: xxxxxxxx = Unused; alwa ys read ‘x’ Figure 14-30. Identifier Register 1 — Standard Mapping T able 14-31. IDR1 Register Field Descriptions F[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 650 F reescale Semiconductor 14.3.3.2 Data Segment Registers (DSR0-7) The eight data segment re gisters, each with bits DB[7:0], contain the data to be transmitted or receiv ed. The number of bytes to be transmitted or recei ved is determine[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 651 14.3.3.3 Data Length Register (DLR) This register k eeps the data length field of the CAN frame. 14.3.3.4 T ransmit Buffer Priority Register (TBPR) This register defines the local priority of the associated mes[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 652 F reescale Semiconductor In cases of more than one b uf fer having the same lo west priority , the message buf fer with the lower inde x number wins. Read: Anytime when TXEx flag is set (see Section 14.3.2.7, “MSCAN T ransmitter Flag [...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 653 Read: Anytime when TXEx flag is set (see Section 14.3.2.7, “MSCAN T ransmitter Flag Register (CANTFLG) ”) and the corresponding transmit buf fer is selected in CANTBSEL (see Section 14.3.2.11, “MSCAN T ran[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 654 F reescale Semiconductor 14.4.2 Message Storage Figure 14-38. User Model for Messa ge Buffer Organization MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications.[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 655 14.4.2.1 Message T ransmit Bac kground Modern application layer software is b uilt upon two fundamental assumptions: • Any CAN node is able to send out a stream of scheduled messages without releasing the CAN b[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 656 F reescale Semiconductor The MSCAN then schedules the message for transmission and signals the successful transmission of the buf fer by setting the associated TXE flag. A transmit interrupt (see Section 14.4.8.2, “Transmit Interrupt [...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 657 field of the CAN frame, is recei ved into the ne xt av ailable RxBG. If the MSCAN recei ves an in valid message in its RxBG (wrong identifier , transmission errors, etc.) the actual contents of the buf fer will[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 658 F reescale Semiconductor • Four identifier acceptance filters, each to be applied to — a) the 14 most significant bits of the extended identifier plus the SRR and IDE bits of CAN 2.0B messages or — b) the 11 bits of the standar[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 659 Figure 14-40. 16-bit Maskable Identifier Acceptance Filters ID28 ID21 IDR0 ID10 ID3 IDR0 ID20 ID15 IDR1 ID2 IDE IDR1 ID14 ID7 IDR2 ID10 ID3 IDR2 ID6 RTR IDR3 ID10 ID3 IDR3 AC7 AC 0 CANID AR0 AM7 AM0 CANIDMR0 AC7[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 660 F reescale Semiconductor Figure 14-41. 8-bit Maskable Identifier Acceptance Filters CAN 2.0B Extended Identifier CAN 2.0A/B Standard Identifier AC7 AC 0 CID AR3 AM7 AM0 CIDMR3 ID Accepted (Filter 3 Hit) AC7 AC 0 CID AR2 AM7 AM0 CIDMR2[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 661 14.4.3.1 Protocol Violation Pr otection The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the follo wing features: • The recei [...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 662 F reescale Semiconductor If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the f aster CAN bus rates. For microcontrollers wit[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 663 The synchronization jump width (see the Bosch CAN specification for details) can be programmed in a range of 1 to 4 time quanta by setting the SJW parameter. The SYNC_SEG, TSEG1, TSEG2, and SJW parameters are se[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 664 F reescale Semiconductor 14.4.5 Modes of Operation 14.4.5.1 Normal Modes The MSCAN module beha ves as described within this specification in all normal system operation modes. 14.4.5.2 Special Modes The MSCAN module beha ves as describe[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 665 14.4.6.1 Operation in Run Mode As sho wn in T able 14-37 , only MSCAN sleep mode is a vailable as lo w power option when the CPU is in run mode. 14.4.6.2 Operation in W ait Mode The W AI instruction puts the MCU [...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 666 F reescale Semiconductor • If there are one or more message buf fers scheduled for transmission (TXEx = 0), the MSCAN will continue to transmit until all transmit message b uffers are empty (TXEx = 1, transmitted successfully or aborte[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 667 The MSCAN is able to lea ve sleep mode (wak e up) only when: • CAN bus acti vity occurs and WUPE = 1 or • the CPU clears the SLPRQ bit NO TE The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 668 F reescale Semiconductor 14.4.6.5 MSCAN Initialization Mode In initialization mode, any on-going transmission or reception is immediately aborted and synchronization to the CAN bus is lost, potentially causing CAN protocol violations. T [...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 669 14.4.6.6 MSCAN P ower Down Mode The MSCAN is in po wer do wn mode ( T able 14-37 ) when • CPU is in stop mode or • CPU is in wait mode and the CSW AI bit is set When entering the po wer do wn mode, the MSCAN [...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 670 F reescale Semiconductor 14.4.8.1 Description of Interrupt Operation The MSCAN supports four interrupt vectors (see T able 14-38 ), any of which can be indi vidually masked (for details see sections from Section 14.3.2.6, “MSCAN Recei [...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 671 Section 14.3.2.5, “MSCAN Receiv er Flag Register (CANRFLG) ” and Section 14.3.2.6, “MSCAN Recei ver Interrupt Enable Re gister (CANRIER) ”). 14.4.8.6 Interrupt Ackno wledge Interrupts are directly associa[...]

Chapter 14 Freescale’ s Scalable Controller Area Netw ork (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev . 2.11 672 F reescale Semiconductor 14.5.2 Bus-Off Reco very The bus-of f recov ery is user configurable. The b us-off state can either be left automatically or on user request. For reasons of backw ards compatibility , the MSCAN defaults to autom[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 673 Chapter 15 Serial Comm unication Interface (S12MC9S12XDP512V5) 15.1 Intr oduction This block guide provides an o vervie w of the serial communication interface (SCI) module. The SCI allo ws asynchronous serial communications with peripheral de vices and other CPUs. 15.1.1 Features The[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 674 F reescale Semiconductor • Hardware parity checking • 1/16 bit-time noise detection 15.1.2 Modes of Operation The SCI functions the same in normal, special, and emulation modes. It has two lo w power modes, w ait and stop modes. • Run mode ?[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 675 15.2 External Signal Description The SCI module has a total of two e xternal pins. 15.2.1 TXD — T ransmit Pin The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high impedance a[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 676 F reescale Semiconductor 15.3.2 Register Descriptions This section consists of register descriptions in address order . Each description includes a standard register diagram with an associated figure number . Writes to a reserved register location[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 677 15.3.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL) Read: Anytime, if AMAP = 0. If only SCIBDH is written to, a read will not return the correct data until SCIBDL is written to as well, follo wing a write to SCIBDH. Write: An[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 678 F reescale Semiconductor 15.3.2.2 SCI Control Register 1 (SCICR1) Read: Anytime, if AMAP = 0. Write: Anytime, if AMAP = 0. NO TE This register is only visible in the memory map if AMAP = 0 (reset condition). T able 15-3. IRSCI T ransmit Pulse Width[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 679 2 IL T Idle Line T ype Bit — IL T determines when the receiver star ts counting logic 1s as idle character bits. The counting begins either after the star t bit or after the stop bit. If the count begins after the star t [...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 680 F reescale Semiconductor 15.3.2.3 SCI Alternative Status Register 1 (SCIASR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Module Base + 0x000a 76543210 R RXEDGIF 0 0 0 0 BERR V BERRIF BKDIF W Reset 00000000 = Unimplemented or Reser ved F[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 681 15.3.2.4 SCI Alternative Control Register 1 (SCIA CR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Module Base + 0x001a 76543210 R RXEDGIE 00000 BERRIE BKDIE W Reset 00000000 = Unimplemented or Reser ved Figure 1[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 682 F reescale Semiconductor 15.3.2.5 SCI Alternative Control Register 2 (SCIA CR2) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Module Base + 0x002a 76543210 R 00000 BERRM1 BERRM0 BKDFE W Reset 00000000 = Unimplemented or Reser ved Figure 15[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 683 15.3.2.6 SCI Control Register 2 (SCICR2) Read: Anytime Write: Anytime Module Base + 0x0003 76543210 R TIE TCIE RIE ILIE TE RE RWU SBK W Reset 00000000 Figure 15-9. SCI Control Register 2 (SCICR2) T able 15-10. SCICR2 Field [...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 684 F reescale Semiconductor 15.3.2.7 SCI Status Register 1 (SCISR1) The SCISR1 and SCISR2 registers pro vides inputs to the MCU for generation of SCI interrupts. Also, these registers can be polled by the MCU to check the status of these bits. The fl[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 685 3 OR Overrun Flag — OR is set when software f ails to read the SCI data register before the receiv e shift register receives the ne xt frame. The OR bit is set immediately after the stop bit has been completely received f[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 686 F reescale Semiconductor 15.3.2.8 SCI Status Register 2 (SCISR2) Read: Anytime Write: Anytime Module Base + 0x0005 76543210 R AMAP 00 TXPOL RXPOL BRK13 TXDIR RAF W Reset 00000000 = Unimplemented or Reser ved Figure 15-11. SCI Status Register 2 (SCI[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 687 15.3.2.9 SCI Data Registers (SCIDRH, SCIDRL) Read: Anytime; reading accesses SCI recei ve data re gister Write: Anytime; writing accesses SCI transmit data re gister; writing to R8 has no effect NO TE If the v alue of T8 is[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 688 F reescale Semiconductor 15.4 Functional Description This section provides a complete functional description of the SCI block, detailing the operation of the design from the end user perspecti ve in a number of subsections. Figure 15-14 sho ws the [...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 689 15.4.1 Infrared Interface Submodule This module provides the capability of transmitting narro w pulses to an IR LED and receiving narro w pulses and transforming them to serial bits, which are sent to the SCI. The IrD A phy[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 690 F reescale Semiconductor 15.4.3 Data Format The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data format where zeroes are represented by light pulses and ones remain lo w . See Figure 15-15 belo w . F[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 691 15.4.4 Baud Rate Generation A 13-bit modulus counter in the baud rate generator deri ves the baud rate for both the recei ver and the transmitter . The value from 0 to 8191 written to the SBR12:SBR0 bits determines the b us[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 692 F reescale Semiconductor 15.4.5 T ransmitter Figure 15-16. T ransmitter Block Diagram 15.4.5.1 T ransmitter Character Length The SCI transmitter can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 693 The SCI also sets a flag, the transmit data register empty flag (TDRE), e very time it transfers data from the buf fer (SCIDRH/L) to the transmitter shift register .The transmit dri ver routine may respond to this flag b[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 694 F reescale Semiconductor When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1. If at any time softw are clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal goe[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 695 Figure 15-17 sho ws two cases of break detect. In trace RXD_1 the break symbol starts with the start bit, while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there will be no byte t[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 696 F reescale Semiconductor 15.4.5.5 LIN T ransmit Collision Detection This module allo ws to check for collisions on the LIN bus. Figure 15-18. Collision Detect Principle If the bit error circuit is enabled (BERRM[1:0] = 0:1 or = 1:0]), the error det[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 697 15.4.6 Receiver Figure 15-20. SCI Receiver Block Dia gram 15.4.6.1 Receiver Character Length The SCI recei ver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1)[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 698 F reescale Semiconductor indicating that the recei ved byte can be read. If the recei ve interrupt enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request. 15.4.6.3 Data Sampling The R T c[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 699 T o determine the v alue of a data bit and to detect noise, recovery logic tak es samples at R T8, R T9, and R T10. T able 15-18 summarizes the results of the data bit samples. NO TE The R T8, R T9, and R T10 samples do not[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 700 F reescale Semiconductor In Figure 15-22 the verification samples R T3 and R T5 determine that the first low detected w as noise and not the beginning of a start bit. The R T clock is reset and the start bit search be gins again. The noise flag [...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 701 In Figure 15-24 , a large b urst of noise is perceiv ed as the beginning of a start bit, although the test sample at R T5 is high. The R T5 sample sets the noise flag. Although this is a worst-case misalignment of percei v[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 702 F reescale Semiconductor Figure 15-26 shows a b urst of noise near the beginning of the start bit that resets the R T clock. The sample after the reset is lo w but is not preceded by three high samples that w ould qualify as a falling edge. Dependi[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 703 15.4.6.5 Baud Rate T olerance A transmitting de vice may be operating at a baud rate belo w or abov e the recei ver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples (R T8, R T9, [...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 704 F reescale Semiconductor 15.4.6.5.2 F ast Data T olerance Figure 15-29 sho ws ho w much a fast recei ved frame can be misaligned. The fast stop bit ends at R T10 instead of R T16 but is still sampled at R T8, R T9, and R T10. Figure 15-29. Fast Dat[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 705 15.4.6.6.1 Idle Input line W akeup (W AKE = 0) In this wakeup method, an idle condition on the RXD pin clears the R WU bit and wakes up the SCI. The initial frame or frames of e very message contain addressing information. [...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 706 F reescale Semiconductor Enable single-wire operation by setting the LOOPS bit and the receiv er source bit, RSRC, in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the recei ver. Setting the RSRC bit c[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 707 15.5.2.2 W ait Mode SCI operation in wait mode depends on the state of the SCISW AI bit in the SCI control register 1 (SCICR1). • If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode. • If SCISWAI[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 708 F reescale Semiconductor 15.5.3.1 Description of Interrupt Operation The SCI only originates interrupt requests. The follo wing is a description of ho w the SCI makes a request and ho w the MCU should ackno wledge that request. The interrupt vector[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 709 15.5.3.1.6 RXEDGIF Description The RXEDGIF interrupt is set when an acti ve edge (f alling if RXPOL = 0, rising if RXPOL = 1) on the RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternati ve st[...]

Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev . 2.11 710 F reescale Semiconductor[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 711 Chapter 16 Serial P eripheral Interface (S12SPIV4) 16.1 Intr oduction The SPI module allo ws a duplex, synchronous, serial communication between the MCU and peripheral de vices. Software can poll the SPI status flags or the SPI operation can be interrupt dri ven. 16.1.1 Features The [...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 712 F reescale Semiconductor This is a high le vel description only , detailed descriptions of operating modes are contained in Section 16.4.7, “Low Po wer Mode Options” . 16.1.3 Bloc k Diagram Figure 16-1 gi ves an o vervie w on the SPI architecture. The main[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 713 16.2 External Signal Description This section lists the name and description of all ports including inputs and outputs that do, or may , connect of f chip. The MC9S12XDP512 module has a total of four external pins. 16.2.1 MOSI — Mast[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 714 F reescale Semiconductor 16.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard re gister diagram with an associated figure number. Details of register bit and field function follo w[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 715 16.3.2.1 SPI Control Register 1 (SPICR1) Read: Anytime Write: Anytime Module Base +0x___0 76543210 R SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE W Reset 00000100 Figure 16-3. SPI Control Register 1 (SPICR1) T able 16-2. SPICR1 Field Descr[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 716 F reescale Semiconductor 16.3.2.2 SPI Control Register 2 (SPICR2) Read: Anytime Write: Anytime; writes to the reserv ed bits have no ef fect T able 16-3. SS Input / Output Selection MODFEN SSOE Master Mode Slave Mode 00 SS not used by SPI SS input 01 SS not us[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 717 16.3.2.3 SPI Baud Rate Register (SPIBR) Read: Anytime Write: Anytime; writes to the reserv ed bits have no ef fect The baud rate di visor equation is as follo ws: BaudRateDivisor = (SPPR + 1) • 2 (SPR + 1) Eqn. 16-1 The baud rate can[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 718 F reescale Semiconductor T able 16-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate 0 0 0 0 0 0 2 12.5 MHz 0 0 0 0 0 1 4 6.25 MHz 0 0 0 0 1 0 8 3.125 MHz 0 0 0 0 1 1 16 1.5625 MHz 0 0 0 1 0 0 32[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 719 1 0 0 1 1 1 1280 19.53 kHz 1 0 1 0 0 0 12 2.08333 MHz 1 0 1 0 0 1 24 1.04167 MHz 1 0 1 0 1 0 48 520.83 kHz 1 0 1 0 1 1 96 260.42 kHz 1 0 1 1 0 0 192 130.21 kHz 1 0 1 1 0 1 384 65.10 kHz 1 0 1 1 1 0 768 32.55 kHz 1 0 1 1 1 1 1536 16.28 [...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 720 F reescale Semiconductor 16.3.2.4 SPI Status Register (SPISR) Read: Anytime Write: Has no ef fect Module Base +0x___3 76543210 R SPIF 0 SPTEF MODF 0000 W Reset 00100000 = Unimplemented or Reser ved Figure 16-6. SPI Status Register (SPISR) T able 16-8. SPISR Fi[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 721 16.3.2.5 SPI Data Register (SPIDR) Read: Anytime; normally read only when SPIF is set Write: Anytime The SPI data register is both the input and output re gister for SPI data. A write to this register allo ws a data byte to be queued a[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 722 F reescale Semiconductor Figure 16-8. Reception with SPIF Serviced in Time Figure 16-9. Reception with SPIF Serviced too Late Receive Shift Register SPIF SPI Data Register Data A Data B Data A Data A Received Data B Received Data C Data C SPIF Ser viced Data C[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 723 16.4 Functional Description The SPI module allo ws a duplex, synchronous, serial communication between the MCU and peripheral de vices. Software can poll the SPI status flags or SPI operation can be interrupt dri ven. The SPI system i[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 724 F reescale Semiconductor 16.4.1 Master Mode The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by writing to the master SPI data re gister. If the shift register is empty , the b[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 725 16.4.2 Sla ve Mode The SPI operates in slav e mode when the MSTR bit in SPI control register 1 is clear. • SCK clock In slav e mode, SCK is the SPI clock input from the master. • MISO, MOSI pin In slav e mode, the function of the s[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 726 F reescale Semiconductor 16.4.3 T ransmission Formats During an SPI transmission, data is transmitted (shifted out serially) and recei ved (shifted in serially) simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 727 Data reception is double buf fered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in. After the 16th (last) SCK edge: • Dat[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 728 F reescale Semiconductor In slav e mode, if the SS line is not deasserted between the successiv e transmissions then the content of the SPI data register is not transmitted; instead the last recei ved byte is transmitted. If the SS line is deasserted for at le[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 729 Figure 16-12. SPI Clock Format 1 (CPHA = 1) The SS line can remain acti ve lo w between successiv e transfers (can be tied low at all times). This format is sometimes preferred in systems having a single fix ed master and a single sla[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 730 F reescale Semiconductor 16.4.4 SPI Baud Rate Generation Baud rate generation consists of a series of di vider stages. Six bits in the SPI baud rate register (SPPR2, SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the di visor to the SPI module clock which resul[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 731 16.4.5.2 Bidirectional Mode (MOMI or SISO) The bidirectional mode is selected when the SPC0 bit is set in SPI control register 2 (see T able 16-9 ). In this mode, the SPI uses only one serial data pin for the interface with e xternal d[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 732 F reescale Semiconductor 16.4.6 Err or Conditions The SPI has one error condition: • Mode fault error 16.4.6.1 Mode Fault Err or If the SS input becomes lo w while the SPI is configured as a master , it indicates a system error where more than one master ma[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 733 16.4.7.2 SPI in W ait Mode SPI operation in wait mode depends upon the state of the SPISW AI bit in SPI control register 2. • If SPISW AI is clear , the SPI operates normally when the CPU is in wait mode • If SPISW AI is set, SPI c[...]

Chapter 16 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev . 2.11 734 F reescale Semiconductor 16.4.7.4 Reset The reset v alues of registers and signals are described in Section 16.3, “Memory Map and Register Definition” , which details the registers and their bit fields. • If a data transmission occurs in sla ve mode af[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 735 Chapter 17 V oltage Regulator (S12VREG3V3V5) 17.1 Intr oduction Module VREG_3V3 is a dual output voltage re gulator that provides two separate 2.5V (typical) supplies dif fering in the amount of current that can be sourced. The regulator input v oltage range is from 3.3V up to 5V (typ[...]

Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 736 F reescale Semiconductor 17.1.3 Bloc k Diagram Figure 17-1 shows the function principle of VREG_3V3 by means of a block diagram. The regulator core REG consists of two parallel subblocks, REG1 and REG2, pro viding two independent output v oltages. Figure 17-1. VREG[...]

Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 737 17.2 External Signal Description Due to the nature of VREG_3V3 being a v oltage regulator pro viding the chip internal po wer supply voltages, most signals are po wer supply signals connected to pads. T able 17-1 sho ws all signals of VREG_[...]

Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 738 F reescale Semiconductor 17.2.4 VDDPLL, VSSPLL — Regulator Output2 (PLL) Pins Signals V DDPLL /V SSPLL are the secondary outputs of VREG_3V3 that provide the po wer supply for the PLL and oscillator. These signals are connected to de vice pins to allo w external [...]

Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 739 17.3.2 Register Descriptions This section describes all the VREG_3V3 registers and their indi vidual bits. 17.3.2.1 HT Control Register (VREGHTCL) The VREGHTCL is reserved for test purposes. This re gister should not be written. 17.3.2.2 Co[...]

Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 740 F reescale Semiconductor 17.3.2.3 Autonomous P eriodical Interrupt Control Register (VREGAPICL) The VREGAPICL register allo ws the configuration of the VREG_3V3 autonomous periodical interrupt features. Module Base + 0x_02 76543210 R APICLK 0000 APIFE APIE APIF W [...]

Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 741 17.3.2.4 Autonomous P eriodical Interrupt T rimming Register (VREGAPITR) The VREGAPITR register allo ws to trim the API timeout period. Module Base + 0x_03 76543210 R APITR5 APITR4 APITR3 APITR2 APITR1 APITR0 00 W Reset 0 1 0 1 0 1 0 1 0 1 [...]

Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 742 F reescale Semiconductor 17.3.2.5 Autonomous P eriodical Interrupt Rate High and Low Register (VREGAPIRH / VREGAPIRL) The VREGAPIRH and VREGAPIRL register allo ws the configuration of the VREG_3V3 autonomous periodical interrupt rate. Module Base + 0x_04 76543210 [...]

Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 743 Y ou can calculate the selected period depending of APICLK as: Period = 2*(APIR[11:0] + 1) * 0.1 ms or period = 2*(APIR[11:0] + 1) * b us clock period T able 17-8. Selectable A utonomous Periodical Interrupt P eriods APICLK APIR[11:0] Selec[...]

Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 744 F reescale Semiconductor 17.3.2.6 Reserved_06 The Reserved_06 is reserv ed for test purposes. 17.3.2.7 Reserved_07 The Reserved_07 is reserv ed for test purposes. 17.4 Functional Description 17.4.1 General Module VREG_3V3 is a voltage re gulator , as depicted in Fi[...]

Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 745 17.4.2.2 Reduced P ower Mode In Reduced Po wer Mode, the gate of the output transistor is connected directly to a reference v oltage to reduce po wer consumption. 17.4.3 Lo w-V oltage Detect (L VD) Subblock L VD is responsible for generatin[...]

Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 746 F reescale Semiconductor The API T rimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency is desired. See T able 17-6 for the trimming ef fect of APITR. NO TE The first period after enabling the counter by APIFE might be reduce[...]

Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 747 17.4.10.1 Low-V oltage Interrupt (L VI) In FPM, VREG_3V3 monitors the input v oltage V DD A . Whene ver V DD A drops belo w lev el V L VIA, the status bit L VDS is set to 1. On the other hand, L VDS is reset to 0 when V DDA rises abo ve le [...]

Chapter 17 V oltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev . 2.11 748 F reescale Semiconductor[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 749 Chapter 18 P eriodic Interrupt Timer (S12PIT24B4CV1) 18.1 Intr oduction The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules or raise periodic interrupts. Refer to Figure 18-1 for a simplified block diagram. 18.1.1 Features The [...]

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 750 F reescale Semiconductor 18.1.3 Bloc k Diagram Figure 18-1 sho ws a block diagram of the PIT . Figure 18-1. MC9S12XDP512 Block Dia gram 18.2 External Signal Description The PIT module has no external pins. Time-Out 0 Time-Out 1 Time-Out 2 Time-Out 3 16-Bit T[...]

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 751 18.3 Memory Map and Register Definition This section provides a detailed description of address space and re gisters used by the PIT. 18.3.1 Module Memory Map The memory map for the MC9S12XDP512 is gi ven belo w in T able 1-1 . The [...]

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 752 F reescale Semiconductor 18.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard re gister diagram with an associated figure number. Details of register bit and field function follo[...]

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 753 0x000D PITLD1 (Low) R PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W 0x000E PITCNT1 (High) R PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 W 0x000F PITCNT1 (Low) R PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 W 0x0010 PITLD2 (H[...]

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 754 F reescale Semiconductor 18.3.2.1 PIT Control and For ce Load Micro Timer Register (PITCFLMT) Read: Anytime Write: Anytime; writes to the reserv ed bits have no ef fect Module Base + 0x0000 76543210 R PITE PITSW AI PITFRZ 00000 W PFLMT1 PFLMT0 Reset 00000000[...]

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 755 18.3.2.2 PIT Force Load Timer Register (PITFL T) Read: Anytime Write: Anytime; writes to the reserv ed bits have no ef fect 18.3.2.3 PIT Channel Enable Register (PITCE) Read: Anytime Write: Anytime; writes to the reserv ed bits have [...]

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 756 F reescale Semiconductor 18.3.2.4 PIT Multiplex Register (PITMUX) Read: Anytime Write: Anytime; writes to the reserv ed bits have no ef fect 18.3.2.5 PIT Interrupt Enable Register (PITINTE) Read: Anytime Write: Anytime; writes to the reserv ed bits have no e[...]

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 757 18.3.2.6 PIT Time-Out Flag Register (PITTF) Read: Anytime Write: Anytime (write to clear); writes to the reserv ed bits have no ef fect 18.3.2.7 PIT Micro Timer Load Register 0 to 1 (PITMTLD0–1) Read: Anytime Write: Anytime Module [...]

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 758 F reescale Semiconductor T able 18-8. PITMTLD0–1 Field Descriptions Field Description 7:0 PMTLD[7:0] PIT Micro Timer Load Bits 7:0 — These bits set the 8-bit modulus do wn-counter load value of the micro timers. Writing a new value into the PITMTLD regis[...]

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 759 18.3.2.8 PIT Load Register 0 to 3 (PITLD0–3) Read: Anytime Write: Anytime Module Base + 0x0008, 0x0009 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W Res[...]

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 760 F reescale Semiconductor 18.3.2.9 PIT Count Register 0 to 3 (PITCNT0–3) Read: Anytime Write: Has no meaning or ef fect Module Base + 0x000A, 0x000B 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R PCNT 15 PCNT 14 PCNT 13 PCNT 12 PCNT 11 PCNT 10 PCNT 9 PCNT 8 PCNT 7 PC[...]

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 761 18.4 Functional Description Figure 18-19 sho ws a detailed block diagram of the PIT module. The main parts of the PIT are status, control and data registers, tw o 8-bit do wn-counters, four 16-bit do wn-counters and an interrupt/trig[...]

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 762 F reescale Semiconductor Whene ver a 16-bit timer counter and the connected 8-bit micro timer counter ha ve counted to zero, the PITLD register is reloaded and the corresponding time-out flag PTF in the PIT time-out flag (PITTF) register is set, as sho wn [...]

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 763 is set, an interrupt service is requested whene ver the corresponding time-out flag PTF in the PIT time-out flag (PITTF) register is set. The flag can be cleared by writing a one to the flag bit. NO TE Be careful when resetting t[...]

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev . 2.11 764 F reescale Semiconductor[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 765 Chapter 19 Bac kground Deb ug Module (S12XBDMV2) 19.1 Intr oduction This section describes the functionality of the background deb ug module (BDM) sub-block of the HCS12X core platform. The background debug module (BDM) sub-block is a single-wire, background deb ug system implemented [...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 766 F reescale Semiconductor • Software control of BDM operation during wait mode • Software selectable clocks • Global page access functionality • Enabled but not acti ve out of reset in emulation modes • CLKSW bit set out of reset in emulation mode. • [...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 767 19.1.2.3 Low-P ower Modes The BDM can be used until all b us masters (e.g., CPU or XGA TE) are in stop mode. When CPU is in a lo w po wer mode (wait or stop mode) all BDM firmware commands as well as the hardw are B A CKGR OUND command [...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 768 F reescale Semiconductor 19.2 External Signal Description A single-wire interface pin called the background deb ug interface (BKGD) pin is used to communicate with the BDM system. During reset, this pin is a mode select input which selects between normal and spe[...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 769 19.3.2 Register Descriptions A summary of the registers associated with the BDM is sho wn in Figure 19-2 . Registers are accessed by host-dri ven communications to the BDM hardw are using READ_BD and WRITE_BD commands. Global Address Reg[...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 770 F reescale Semiconductor 19.3.2.1 BDM Status Register (BDMSTS) Figure 19-3. BDM Status Register ( BDMSTS) Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured, b ut subject to the follo wing: — ENBDM sh[...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 771 6 BDMA CT BDM Active Status — This bit becomes set upon entering BDM. The standard BDM fir mware lookup table is then enabled and put into the memory map. BDMA CT is cleared by a carefully timed store instruction in the standard BDM ?[...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 772 F reescale Semiconductor 19.3.2.2 BDM CCR LO W Holding Register (BDMCCRL) Figure 19-4. BDM CCR LO W Holding Register (BDMCCRL) Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured NO TE When BDM is made a[...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 773 19.3.2.3 BDM CCR HIGH Holding Register (BDMCCRH) Figure 19-5. BDM CCR HIGH Holding Register (BDMCCRH) Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured When entering background[...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 774 F reescale Semiconductor 19.4 Functional Description The BDM recei ves and e xecutes commands from a host via a single wire serial interface. There are two types of BDM commands: hardware and firmw are commands. Hardware commands are used to read and write tar [...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 775 After being enabled, BDM is acti v ated by one of the follo wing 1 : • Hardware B A CKGR OUND command • CPU BGND instruction • External instruction tagging mechanism 2 • Breakpoint force or tag mechanism 2 When BDM is acti v ated[...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 776 F reescale Semiconductor 19.4.4 Standar d BDM Firmware Commands Firmware commands are used to access and manipulate CPU resources. The system must be in acti ve BDM to ex ecute standard BDM firmware commands, see Section 19.4.2, “Enabling and Activ ating BDM?[...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 777 T able 19-6. Firmware Commands Command 1 1 If enabled, A CK will occur when data is ready for transmission f or all BDM READ commands and will occur after the wr ite is complete f or all BDM WRITE commands. Opcode (hex) Data Description [...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 778 F reescale Semiconductor 19.4.5 BDM Command Structure Hardware and firmware BDM commands start with an 8-bit opcode follo wed by a 16-bit address and/or a 16-bit data word depending on the command. All the read commands return 16 bits of data despite the byte o[...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 779 The external host should w ait at least for 76 bus clock c ycles after a TRA CE1 or GO command before starting any ne w serial command. This is to allow the CPU to e xit gracefully from the standard BDM firmware lookup table and resume [...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 780 F reescale Semiconductor 19.4.6 BDM Serial Interface The BDM communicates with external de vices serially via the BKGD pin. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes t[...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 781 Figure 19-8. BDM Host-to-T arget Serial Bit Timing The recei ve cases are more complicated. Figure 19-9 sho ws the host recei ving a logic 1 from the target system. Since the host is asynchronous to the target, there is up to one clock-c[...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 782 F reescale Semiconductor Figure 19-10 sho ws the host recei ving a logic 0 from the target. Since the host is asynchronous to the target, there is up to a one clock-c ycle delay from the host-generated falling edge on BKGD to the start of the bit time as percei [...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 783 compared to the serial communication rate. This protocol allo ws a great flexibility for the POD designers, since it does not rely on any accurate time measurement or short response time to an y ev ent in the serial communication. Figur[...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 784 F reescale Semiconductor Dif ferently from the normal bit transfer (where the host initiates the transmission), the serial interface A CK handshake pulse is initiated by the tar get MCU by issuing a neg ativ e edge in the BKGD pin. The hardware handshake protoco[...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 785 GO_UNTIL command can not be aborted. Only the corresponding A CK pulse can be aborted by the SYNC command. Although it is not recommended, the host could abort a pending BDM command by issuing a lo w pulse in the BKGD pin shorter than 12[...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 786 F reescale Semiconductor Figure 19-14 sho ws a conflict between the A CK pulse and the SYNC request pulse. This conflict could occur if a POD de vice is connected to the target BKGD pin and the tar get is already in debug acti ve mode. Consider that the target[...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 787 The A CK_EN ABLE sends an A CK pulse when the command has been completed. This feature could be used by the host to e v aluate if the target supports the hardw are handshake protocol. If an A CK pulse is issued in response to this comman[...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 788 F reescale Semiconductor within a fe w percent of the actual target speed and the communication protocol can easily tolerate speed errors of se veral percent. As soon as the SYNC request is detected by the target, an y partially receiv ed command or bit retrie v[...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 789 19.4.11 Serial Communication Time Out The host initiates a host-to-target serial transmission by generating a f alling edge on the BKGD pin. If BKGD is kept lo w for more than 128 target clock cycles, the tar get understands that a SYNC [...]

Chapter 19 Backgr ound Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev . 2.11 790 F reescale Semiconductor[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 791 Chapter 20 Deb ug (S12XDBGV2) 20.1 Intr oduction The DBG module provides an on-chip trace buf fer with flexible triggering capability to allo w non-intrusi ve debug of application softw are. The DBG module is optimized for the HCS12X 16-bit architecture and allo ws debugging of both [...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 792 F reescale Semiconductor 20.1.2 Features • Four comparators (A, B, C, and D): — Comparators A and C compare the full address and the full 16-bit data bus — Comparators A and C feature a data bus mask re gister — Comparators B and D compare the full address bus only — Eac[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 793 XGA TE activity can still be compared, traced and can be used to generate a breakpoint to the XGA TE module. When the CPU enters acti ve BDM mode through a B ACKGR OUND command, with the DBG module armed, the DBG remains armed. The DBG module tracing is di[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 794 F reescale Semiconductor . T able 20-2. External System Pins Associated With DBG Pin Name Pin Functions Description T AGHI (See DUG) T AGHI When instruction tagging is on, tags the high half of the instruction word being read into the instruction queue. T AGLO (See DUG) T AGLO Whe[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 795 20.3 Memory Map and Register Definition A summary of the registers associated with the DBG sub-block is sho wn in Figure 20-2 . Detailed descriptions of the registers and bits are gi ven in the subsections that follo w. 20.3.1 Register Descriptions This s[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 796 F reescale Semiconductor 20.3.1.1 Debug Contr ol Register 1 (DBGC1) Read: Anytime Write: Bits 7,1,0 anytime, Bit 6 can be written an ytime but alw ays reads back as 0. Bits 5:2 anytime DBG is not armed. NO TE When disarming the DBG by clearing ARM with software, the contents of bi[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 797 T able 20-3. DBGC1 Field Descriptions Field Description 7 ARM Arm Bit — The ARM bit controls whether the DBG module is armed. This bit can be set and cleared by user software and is automatically cleared on completion of a tracing session, or if a breakp[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 798 F reescale Semiconductor 20.3.1.2 Debug Status Register (DBGSR) Read: Anytime Write: Ne ver 01 Comparator B DBGSCR2 10 Comparator C DBGSCR3 11 Comparator D DBGSCR3 0x0021 76543210 R TBF EXTF 0 0 0 SSF2 SSF1 SSF0 W Reset — 0 0 0 0000 P O R 00000000 Unimplemented or Reser ved Figu[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 799 20.3.1.3 Debug T race Control Register (DBGTCR) Read: Anytime Write: Bits 7:6 only when DBG is neither secure nor armed. Bits 5:0 anytime the module is disarmed. 0x0022 76543210 R TSOURCE TRANGE TRCMOD T ALIGN W Reset 00000000 Figure 20-5. Debug T race Con[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 800 F reescale Semiconductor 20.3.1.4 Debug Contr ol Register2 (DBGC2) Read: Anytime Write: Anytime the module is disarmed. This register configures the comparators for range matching. 11 T race only in range from comparator C to compar ator D T able 20-11. TRCMOD T race Mode Bit Enc[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 801 20.3.1.5 Debug T race Buffer Register (DBGTBH:DBGTBL) Read: Anytime when unlock ed and not secured and not armed. Write: Aligned word writes when disarmed unlock the trace b uffer for reading b ut do not af fect trace buf fer contents T able 20-14. CDCM En[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 802 F reescale Semiconductor 20.3.1.6 Debug Count Register (DBGCNT) Read: Anytime Write: Ne ver 0x0026 76543210 R 0 CNT W Reset 0 — — ————— P O R 00000000 Unimplemented or Reser ved Figure 20-9. Debug Count Register (DBGCNT) T able 20-17. DBGCNT Field Descriptions Field [...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 803 20.3.1.7 Debug State Contr ol Registers Each of the state sequencer states 1 to 3 features a dedicated control register to determine if transitions from that state are allo wed depending upon comparator matches or tag hits and to define the next state for[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 804 F reescale Semiconductor 20.3.1.9 Debug State Contr ol Register 2 (DBGSCR2) Read: Anytime Write: Anytime when DBG not armed. This register is visible at 0x0027 only with COMR V[1:0] = 01. The state control register 2 selects the targeted ne xt state while in State2. The matches re[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 805 20.3.1.10 Debug State Contr ol Register 3 (DBGSCR3) Read: Anytime Write: Anytime when DBG not armed. This register is visible at 0x0027 only with COMR V[1]=1. The state control register 3 selects the tar geted next state while in State3. The matches refer [...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 806 F reescale Semiconductor (DBGXCTL)” . Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. 20.3.1.11 Comparator Register Descriptions Each comparator has a bank of registers that are visible through an 8-byte windo w in the[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 807 20.3.1.11.1 Debug Comparator Contr ol Register (DBGXCTL) The contents of this register bits 7 and 6 dif fer depending upon which comparator registers are visible in the 8-byte windo w of the DBG module register address map Read: Anytime Write: Anytime when[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 808 F reescale Semiconductor T able 20-28 shows the ef fect for R WE and R W on the comparison conditions. These bits are not useful for tagged operations since the trigger occurs based on the tagged opcode reaching the ex ecution stage of the instruction queue. Thus, these bits are i[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 809 20.3.1.11.2 Debug Comparator Address High Register (DBGXAH) Read: Anytime Write: Anytime when DBG not armed. 20.3.1.11.3 Debug Comparator Address Mid Register (DBGXAM) Read: Anytime Write: Anytime when DBG not armed. 0x0029 76543210 R0 Bit 22 21 20 19 18 1[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 810 F reescale Semiconductor 20.3.1.11.4 Debug Comparator Address Lo w Register (DBGXAL) Read: Anytime Write: Anytime when DBG not armed. 20.3.1.11.5 Debug Comparator Data High Register (DBGXDH) Read: Anytime Write: Anytime when DBG not armed. 0x002B 76543210 R Bit 7 6 5 4 3 2 1 Bit 0[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 811 20.3.1.11.6 Debug Comparator Data Lo w Register (DBGXDL) Read: Anytime Write: Anytime when DBG not armed. 20.3.1.11.7 Debug Comparator Data High Mask Register (DBGXDHM) Read: Anytime Write: Anytime when DBG not armed. 0x002D 76543210 R Bit 7 6 5 4 3 2 1 Bi[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 812 F reescale Semiconductor 20.3.1.11.8 Debug Comparator Data Lo w Mask Register (DBGXDLM) Read: Anytime Write: Anytime when DBG not armed. 20.4 Functional Description This section provides a complete functional description of the DBG module. If the part is in secure mode, the DBG mo[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 813 Figure 20-22. DBG Overview 20.4.2 Comparator Modes The DBG contains 4 comparators, A, B, C, and D. Each comparator can be configured to monitor either CPU or XGA TE busses using the SRC bit in the corresponding comparator control register. Each comparator[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 814 F reescale Semiconductor If the T A G bit is clear (forced type trigger) a comparator match is generated when the selected address appears on the system address b us. If the selected address is an opcode address, the match is generated when the opcode is fetched from the memory . [...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 815 20.4.2.2 Exact Address Comparator Match (Comparator s B and D) Comparators B and D feature SZ and SZE control bits. If SZE is clear , then the comparator address match qualification functions the same as for comparators A and C. If the SZE bit is set the [...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 816 F reescale Semiconductor 20.4.2.3.2 Outside Range (Address < CompA C_Addr or Address > CompBD_Ad dr) In the outside range comparator mode, either comparator pair A and B or comparator pair C and D can be configured for range comparisons. A single match condition on either o[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 817 20.4.3.4 T rigger On XGA TE S/W Breakpoint Request The XGA TE S/W breakpoint request issues a forced breakpoint request to the CPU immediately independent of DBG settings. If the deb ug module is armed triggers the state sequencer into the disarmed state. [...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 818 F reescale Semiconductor 20.4.4 State Sequence Contr ol Figure 20-23. State Sequencer Diagram The state sequence control allo ws a defined sequence of e vents to pro vide a trigger point for tracing of data in the trace buf fer. Once the DBG module has been armed by setting the A[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 819 20.4.4.1 Final State On entering final state a trigger may be issued to the trace buf fer according to the trace position control as defined by the T ALIGN field (see Section 20.3.1.3, “Debug T race Control Register (DBGTCR)” ). If the TSOURCE bits [...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 820 F reescale Semiconductor is continued for another 32 lines. Upon tracing completion the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary . 20.4.5.1.3 Storing with End-T rigger Storing with end-trigger , data is stored in the trace buf [...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 821 Loop1 mode only inhibits consecuti ve duplicate source address entries that w ould typically be stored in most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these woul[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 822 F reescale Semiconductor information (R/W , S/D etc.). The numerical suffix indicates which tracing step. The information format for loop1 mode is the same as that of normal mode. Whilst tracing from XGA TE or CPU only , in normal or loop1 modes each array line contains data from[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 823 20.4.5.3.1 Inf ormation Byte Organization The format of the control information byte for both CPU and XGA TE modules is dependent upon the acti ve trace mode and tracing source as described belo w. In normal mode or loop1 mode, tracing of XGA TE activity X[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 824 F reescale Semiconductor This describes the format of the information byte used only when tracing from CPU or XGATE in detail mode. When tracing from the CPU in detail mode, information is stored to the trace buffer on all cycles except opcode fetch and free cycles. The XGATE entr[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 825 20.4.5.3.2 Reading Data fr om T race Buffer The data stored in the trace buf fer can be read using either the background debug module (BDM) module or the CPU provided the DBG module is not armed, is configured for tracing (at least one TSOURCE bit is set)[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 826 F reescale Semiconductor 20.4.5.3.3 T race Buffer Reset State The trace buf fer contents are not initialized by a system reset. Thus should a system reset occur , the trace session information from immediately before the reset occurred can be read out. The DBGCNT bits are not clea[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 827 20.4.6.1 External T ag ging using T A GHI and T A GLO External tagging using the external T A GHI and T AGLO pins can only be used to tag CPU opcodes; tagging of XGA TE code using these pins is not possible. An external tag triggers the state sequencer int[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 828 F reescale Semiconductor 20.4.7.2 Breakpoints From Internal Comparator Channel Final State T riggers Breakpoints can be generated when internal comparator channels trigger the state sequencer to the final state. If configured for tagging, then the breakpoint is generated when th[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 829 20.4.7.5 DBG Breakpoint Priorities XGA TE software breakpoints hav e the highest priority . Acti ve tracing sessions are terminated immediately . If a TRIG triggers occur after begin or mid aligned tracing has already been triggered by a comparator instiga[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 830 F reescale Semiconductor When program control returns from a tagged breakpoint using an R TI or BDM GO command without program counter modification it will return to the instruction whose tag generated the breakpoint. Thus care must be taken to a void re triggering a breakpoint a[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 831[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 832 F reescale Semiconductor[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 833[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 834 F reescale Semiconductor[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 835[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 836 F reescale Semiconductor[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 837[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 838 F reescale Semiconductor[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 839[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 840 F reescale Semiconductor[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 841[...]

Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev . 2.11 842 F reescale Semiconductor[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor PRELIMINAR Y 843 NON-DISCLOSURE A GREEMENT REQUIRED Chapter 21 Interrupt (S12MC9S12XDP512V1) 21.1 Intr oduction The XINT module decodes the priority of all system exception requests and pro vides the applicable vector for processing the exception to either the CPU or the XGA TE module. Th[...]

Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 844 PRELIMINAR Y F reescale Semiconductor NON-DISCLOSURE A GREEMENT REQUIRED 21.1.1 Glossary The follo wing terms and abbre viations are used in the document. 21.1.2 Features • Interrupt vector base re gister (IVBR) • One spurious interrupt vector (at address v ector b[...]

Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor PRELIMINAR Y 845 NON-DISCLOSURE A GREEMENT REQUIRED • W ait mode In wait mode, the XINT module is frozen. It is ho wev er capable of either waking up the CPU if an interrupt occurs or waking up the XGA TE if an XGA TE request occurs. Please refer[...]

Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 846 PRELIMINAR Y F reescale Semiconductor NON-DISCLOSURE A GREEMENT REQUIRED 21.1.4 Bloc k Diagram Figure 21-1 sho ws a block diagram of the XINT module. Figure 21-1. XINT Block Dia gram W ake Up Current RQST IVBR One Set P er Channel XGA TE Interrupts XGA TE Requests Inte[...]

Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor PRELIMINAR Y 847 NON-DISCLOSURE A GREEMENT REQUIRED 21.2 External Signal Description The XINT module has no external signals. 21.3 Memory Map and Register Definition This section provides a detailed description of all re gisters accessible in the [...]

Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 848 PRELIMINAR Y F reescale Semiconductor NON-DISCLOSURE A GREEMENT REQUIRED 21.3.1 Register Descriptions This section describes in address order all the XINT registers and their indi vidual bits. Address Register Name Bit 7 654321 Bit 0 0x0121 IVBR R IVB_ADDR[7:0] W 0x012[...]

Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor PRELIMINAR Y 849 NON-DISCLOSURE A GREEMENT REQUIRED 21.3.1.1 Interrupt V ector Base Register (IVBR) Read: Anytime Write: Anytime Address: 0x0121 76543210 R IVB_ADDR[7:0] W Reset 11111111 Figure 21-3. Interrupt V ector Base Register (IVBR) T able 21[...]

Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 850 PRELIMINAR Y F reescale Semiconductor NON-DISCLOSURE A GREEMENT REQUIRED 21.3.1.2 XGA TE Interrupt Priority Configuration Register (INT_XGPRIO) Read: Anytime Write: Anytime Address: 0x0126 76543210 R 00000 XIL VL[2:0] W Reset 00000001 = Unimplemented or Reser ved Figu[...]

Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor PRELIMINAR Y 851 NON-DISCLOSURE A GREEMENT REQUIRED 21.3.1.3 Interrupt Request Configuration Address Register (INT_CF ADDR) Read: Anytime Write: Anytime Address: 0x0127 76543210 R INT_CF ADDR[7:4] 0000 W Reset 00010000 = Unimplemented or Reser ved[...]

Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 852 PRELIMINAR Y F reescale Semiconductor NON-DISCLOSURE A GREEMENT REQUIRED 21.3.1.4 Interrupt Request Configuration Data Registers (INT_CFD A T A0–7) The eight register windo w visible at addresses INT_CFD A T A0–7 contains the configuration data for the block of e[...]

Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor PRELIMINAR Y 853 NON-DISCLOSURE A GREEMENT REQUIRED Read: Anytime Write: Anytime Address: 0x012C 76543210 R RQST 0000 PRIOL VL[2:0] W Reset 0000000 1 1 1 Please refer to the notes following the PRIOLVL[2:0] description below. = Unimplemented or Res[...]

Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 854 PRELIMINAR Y F reescale Semiconductor NON-DISCLOSURE A GREEMENT REQUIRED T able 21-6. INT_CFD A T A0–7 Field Descriptions Field Description 7 RQST XGA TE Request Enable — This bit determines if the associated interr upt request is handled by the CPU or by the XGA T[...]

Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor PRELIMINAR Y 855 NON-DISCLOSURE A GREEMENT REQUIRED 21.4 Functional Description The XINT module processes all exception requests to be serviced by the CPU module. These e xceptions include interrupt vector requests and reset v ector requests. Each [...]

Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 856 PRELIMINAR Y F reescale Semiconductor NON-DISCLOSURE A GREEMENT REQUIRED 21.4.2.1 Interrupt Priority Stack The current interrupt processing le vel (IPL) is stored in the condition code re gister (CCR) of the CPU. This way the current IPL is automatically pushed to the [...]

Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor PRELIMINAR Y 857 NON-DISCLOSURE A GREEMENT REQUIRED If the interrupt source is unkno wn (for example, in the case where an interrupt request becomes inacti ve after the interrupt has been recognized, but prior to the v ector request), the vector ad[...]

Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 858 PRELIMINAR Y F reescale Semiconductor NON-DISCLOSURE A GREEMENT REQUIRED 21.5 Initialization/Application Inf ormation 21.5.1 Initialization After system reset, software should: • Initialize the interrupt vector base re gister if the interrupt vector table is not loca[...]

Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor PRELIMINAR Y 859 NON-DISCLOSURE A GREEMENT REQUIRED Figure 21-14. Interrupt Processing Example 21.5.3 W ake Up from Stop or W ait Mode 21.5.3.1 CPU W ake Up from Stop or W ait Mode Every I bit maskable interrupt request which is configured to be h[...]

Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev . 2.11 860 PRELIMINAR Y F reescale Semiconductor NON-DISCLOSURE A GREEMENT REQUIRED[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 861 Chapter 22 External Bus Interface (S12XEBIV2) 22.1 Intr oduction This document describes the functionality of the MC9S12XDP512 block controlling the external b us interface. The MC9S12XDP512 controls the functionality of a non-multiplex ed external b us (a.k.a. ‘expansion bus’) in[...]

Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 862 F reescale Semiconductor 22.1.3 Bloc k Diagram Figure 22-1 is a block diagram of the MC9S12XDP512 with all related I/O signals. Figure 22-1. MC9S12XDP512 Block Dia gram 22.2 External Signal Description The user is advised to refer to the SoC section for port confi[...]

Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 863 T able 22-1. External System Signals Associated with MC9S12XDP512 Signal I 1 /O 1 All inputs are capable of reducing input threshold le vel EBI Signal Multiplex (T)ime 2 (F)unction 3 2 Time-multiple x means that the respective signals shar[...]

Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 864 F reescale Semiconductor 22.3 Memory Map and Register Definition This section provides a detailed description of all re gisters accessible in the MC9S12XDP512 . 22.3.1 Module Memory Map The registers associated with the MC9S12XDP512 block are shown in Figure 22-2[...]

Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 865 22.3.2.1 External Bus Interface Control Register 0 (EBICTL0) Read: Anytime. In emulation modes, read operations will return the data from the e xternal bus, in all other modes, the data are read from this register. Write: Anytime. In emula[...]

Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 866 F reescale Semiconductor T able 22-3. Input Threshold Levels on External Signals ITHRS External Signal NS SS NX ES EX ST 0 D A T A[15:8] T A GHI, T AGLO Standard Standard Standard Reduced Reduced Standard D A T A[7:0] EW AIT Standard Standard 1 D A T A[15:8] T A G[...]

Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 867 22.3.2.2 External Bus Interface Control Register 1 (EBICTL1) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime. In emulati[...]

Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 868 F reescale Semiconductor 22.4 Functional Description This section describes the functions of the external bus interface. The availability of external signals and functions in relation to the operating mode is initially summarized and described in more detail in se[...]

Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 869 22.4.2 Internal Visibility Internal visibility allows the observation of the internal MCU address and data bus as well as the determination of the access source and the CPU pipe (queue) status through the external bus interface. Internal v[...]

Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 870 F reescale Semiconductor The following terminology is used: ‘addr’ — v alue(ADDRx); small letters denote the logic v alues at the respecti ve pins ‘x’ — Undefined output pin v alues ‘z’ — T ristate pins ‘?’ — Dependent on pre vious access [...]

Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 871 22.4.2.2.2 Write Access Timing T able 22-12. Write Access (1 Cycle) Access #0 Access #1 Access #2 Bus cycle -> ... 123 ... ECLK phase ... high low high low high low ... ADDR[22:20] / A CC[2:0] ... addr 0 acc 0 addr 1 acc 1 addr 2 acc 2 [...]

Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 872 F reescale Semiconductor 22.4.2.2.3 Read-Write-Read Access Timing 22.4.2.3 Internal Visibility Data Depending on the access size and alignment, either a word of read data is made visible on the address lines or only the related data byte will be presented in the E[...]

Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 873 Stretched accesses are controlled by: 1. EXSTR[2:0] bits in the EBICTL1 register configuring fix ed amount of stretch cycles 2. Acti v ation of the external w ait feature by EW AITE in EBICTL1 register 3. Assertion of the external EW AIT[...]

Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 874 F reescale Semiconductor 22.4.5.2 Emulation Modes and Special T est Mode In emulation modes and special test mode, the external signals LSTRB, R/W , and ADDR0 indicate the access type (read/write), data size and alignment of an external b us access. Misaligned acc[...]

Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 875 22.4.6 Lo w-P ower Options The MC9S12XDP512 does not support any user-controlled options for reducing power consumption. 22.4.6.1 Run Mode The MC9S12XDP512 does not support any options for reducing power in run mode. Power consumption is r[...]

Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 876 F reescale Semiconductor 22.5.1 Normal Expanded Mode This mode allows interfacing to external memories or peripherals which are available in the commercial market. In these applications the normal bus operation requires a minimum of 1 cycle stretch for each extern[...]

Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 877 22.5.2 Em ulation Modes In emulation mode applications, the development systems use a custom PRU device to rebuild the single-chip or expanded bus functions which are lost due to the use of the external bus with an emulator. Accesses to a [...]

Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 878 F reescale Semiconductor 22.5.2.1 Example 2a: Emulation Single-Chip Mode This mode is used for emulation systems in which the target application is operating in normal single-chip mode. Figure 22-5 shows the PRU connection with the available external bus signals i[...]

Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 879 22.5.2.2 Example 2b: Emulation Expanded Mode This mode is used for emulation systems in which the target application is operating in normal expanded mode. If the external bus is used with a PRU, the external device rebuilds the data select[...]

Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev . 2.11 880 F reescale Semiconductor[...]

MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 881 Chapter 23 Memory Mapping Control (S12XMMCV2) 23.1 Intr oduction This section describes the functionality of the module mapping control (MMC) sub-block of the S12X platform. The block diagram of the MMC is sho wn in Figure 1-1 . The MMC module controls the multi-master priority access[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 882 F reescale Semiconductor • W ait mode MMC is functional during wait mode. • Stop mode MMC is inacti ve during stop mode. 23.1.2.2 Functional Modes • Single chip modes In normal and special single chip mode the internal memory is used. External b us is not ac[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 883 T able 1-2 and T able 1-3 outline the pin names and functions. It also provides a brief description of their operation. T able 23-1. External Input Signals Associated with the MMC Signal I/O Description A vailability MODC I Mode input Latc[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 884 F reescale Semiconductor 23.3 Memory Map and Registers 23.3.1 Module Memory Map A summary of the registers associated with the MMC block is sho wn in Figure 1-2 . Detailed descriptions of the registers and bits are gi ven in the subsections that follo w . Address [...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 885 23.3.2 Register Descriptions 23.3.2.1 MMC Control Register (MMCCTL0) Read: Anytime. In emulation modes read operations will return the data from the e xternal bus. In all other modes the data is read from this register . Write: Anytime. In[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 886 F reescale Semiconductor The MMCCTL0 register is used to control e xternal bus functions, i.e., a v ailability of chip selects. CA UTION XGA TE write access to this register during an CPU access which makes use of this register could lead to une xpected results. T[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 887 23.3.2.2 Mode Register (MODE) Read: Anytime. In emulation modes read operations will return the data read from the e xternal bus. In all other modes the data are read from this register . Write: Only if a transition is allo wed (see Figure[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 888 F reescale Semiconductor Figure 23-5. Mode T ransition Diagram when MCU is Unsecured Normal Single-Chip 100 Normal Expanded 101 Emulation Expanded 011 Emulation Single-Chip 001 Special T est 010 Special Single-Chip 000 101 101 011 011 101 000 010 100 001 001 100 1[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 889 23.3.2.3 Global Pa g e Index Register (GP A GE) Read: Anytime Write: Anytime The global page index re gister is used only when the CPU is executing a global instruction (GLD AA, GLD AB, GLDD, GLDS, GLDX, GLD Y ,GST AA, GST AB, GSTD, GSTS, [...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 890 F reescale Semiconductor 23.3.2.4 Direct Pa g e Register (DIRECT) Read: Anytime Write: anytime in special modes, one time only in other modes. This register determines the position of the direct page within the memory map. CA UTION XGA TE write access to this regi[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 891 23.3.2.5 MMC Control Register (MMCCTL1) Read: Anytime. In emulation modes read operations will return the data from the e xternal bus. In all other modes the data are read from this register . Write: Refer to each bit description. In emula[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 892 F reescale Semiconductor 23.3.2.6 RAM Pa g e Index Register (RP A GE) Read: Anytime Write: Anytime The RAM page index re gister allo ws accessing up to (1M minus 2K) bytes of RAM in the global memory map by using the eight page index bits to page 4 Kbyte blocks in[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 893 Figure 23-12. RP A GE Address Mapping NO TE Because RAM page 0 has the same global address as the register space, it is possible to write to registers through the RAM space when RP AGE = $00. The reset v alue of $FD ensures that there is a[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 894 F reescale Semiconductor 23.3.2.7 EEPROM P age Index Register (EP A GE) Read: Anytime Write: Anytime The EEPR OM page index re gister allows accessing up to 256 Kbyte of EEPR OM in the global memory map by using the eight page index bits to page 1 Kbyte blocks int[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 895 23.3.2.8 Program P age Index Register (PP A GE) Read: Anytime Write: Anytime The program page index re gister allows accessing up to 4 Mbyte of FLASH or R OM in the global memory map by using the eight page index bits to page 16 Kbyte bloc[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 896 F reescale Semiconductor The fixed 16K page from $4000–$7FFF (when R OMHM = 0) is the page number $FD. The reset v alue of $FE ensures that there is linear Flash space av ailable between addresses $4000 and $FFFF out of reset. The fixed 16K page from $C000-$FF[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 897 23.3.2.10 RAM XGA TE Upper Boundary Register (RAMXGU) Read: Anytime Write: Anytime when R WPE = 0 23.3.2.11 RAM Shared Region Lower Boundary Register (RAMSHL) Read: Anytime Write: Anytime when R WPE = 0 Address: 0x011D 76543210 R1 XGU6 XGU[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 898 F reescale Semiconductor 23.3.2.12 RAM Shared Region Upper Boundar y Register (RAMSHU) Read: Anytime Write: Anytime when R WPE = 0 23.4 Functional Description The MMC block performs se veral basic functions of the S12X sub-system operation: MCU operation modes, pr[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 899 • Normal expanded mode The external b us interface is configured as an up to 23-bit address bus, 8 or 16-bit data b us with dedicated bus control and status signals. This mode allo ws 8 or 16-bit external memory and peripheral de vices [...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 900 F reescale Semiconductor Figure 23-21. Expansion of the Local Address Map $7F_FFFF $00_0000 $7F_C000 $14_0000 $13_FC00 $10_0000 $FFFF Reset V ectors $C000 $8000 Unpaged Flash $4000 $1000 $0000 2K Registers 8K RAM $0F_E000 1K EEPROM 255*1K paged EEPROM 1M minus Kb [...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 901 23.4.2.1.1 Expansion of the Local Address Map Expansion of the CPU Local Address Map The program page index re gister in MMC allows accessing up to 4 Mbyte of FLASH or R OM in the global memory map by using the eight page index bits to pag[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 902 F reescale Semiconductor Expansion of the BDM Local Address Map PP A GE, RP A GE, and EP A GE registers are also used for the e xpansion of the BDM local address to the global address. These registers can be read and written by the BDM. The BDM expansion scheme is[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 903 Figure 23-22. BDMGPR Address Mapping 23.4.2.3 Implemented Memor y Map The global memory spaces reserved for the internal resources (RAM, EEPR OM, and FLASH) are not determined by the MMC module. Size of the indi vidual internal resources a[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 904 F reescale Semiconductor When the de vice is operating in expanded modes e xcept emulation single-chip mode, accesses to the global addresses which are not occupied by the on-chip resources (unimplemented areas or external space) result in accesses to the external[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 905 Figure 23-23. Local to Implemented Global Address Mapping (Without GP A GE) $7F_FFFF $00_0000 $13_FFFF $0F_FFFF $FFFF Reset V ectors $C000 $8000 Unpaged Flash $4000 $1000 $0000 2K Registers 8K RAM 1K EEPROM Unpaged Flash 16K window $0C00 1[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 906 F reescale Semiconductor 23.4.2.4 XGA TE Memor y Map Scheme 23.4.2.4.1 Expansion of the XGA TE Local Address Map The XGA TE 64 Kbyte memory space allows access to internal resources only (Re gisters, RAM, and FLASH). The 2 Kilobyte register address range is the sa[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 907 Figure 23-24. Local to Global Address Mapping (XGA TE) $7F_FFFF $00_0000 $0F_FFFF $FFFF $0000 2K Registers FLASH RAM $0800 RAM 2K Registers $00_0800 XGATE Local Memory Map Global Memory Map FLASH FLASHSIZE XGRAMSIZE XGRAMSIZE 2K RAMSIZE[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 908 F reescale Semiconductor 23.4.3 Chip Access Restrictions 23.4.3.1 Illegal XGA TE Accesses A possible access error is flagged by the MMC and signalled to XGA TE under the following conditions: • XGA TE performs misaligned word (in case of load-store or opcode or[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 909 The follo wing conditions must be satisfied to ensure correct operation of the RAM protection mechanism: • V alue stored in RAMXGU must be lower than the v alue stored in RAMSHL. • V alue stored RAMSHL must be lower or equal than the [...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 910 F reescale Semiconductor 23.4.4 Chip Bus Contr ol The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM and XGA TE) with the rest of the system (master buses). In addition the MMC handles all CPU read data b us swapping op[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 911 23.4.4.2 Access Conflicts on T arget Buses The arbitration scheme allo ws only one master to be connected to a target at an y giv en time. The follo wing rules apply when prioritizing accesses from dif ferent masters to the same target b [...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 912 F reescale Semiconductor This sequence is uninterruptable. There is no need to inhibit interrupts during the CALL instruction ex ecution. A CALL instruction can be performed from any address to any other address in the local CPU memory space. The PP A GE v alue su[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 913 Due to internal visibility of CPU accesses the CPU will be halted during XGA TE or BDM access to any PRR. This rule applies also in normal modes to ensure that operation of the de vice is the same as in emulation modes. A summary of PRR ac[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 914 F reescale Semiconductor 23.5.3 On-Chip R OM Contr ol The MCU of fers two modes to support emulation. In the first mode (called generator) the emulator provides the data instead of the internal FLASH and traces the CPU actions. In the other mode (called observer)[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 915 23.5.3.3 ROM Contr ol in Normal Expanded Mode In normal expanded mode the e xternal b us will be connected to the application. If the R OMON bit is set, the internal FLASH provides the data. If the R OMON bit is cleared, the application me[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 916 F reescale Semiconductor 23.5.3.4 ROM Contr ol in Emulation Expanded Mode In emulation expanded mode the e xternal bus will be connected to the emulator and to the application. If the R OMON bit is set, the internal FLASH provides the data. If the ER OMON bit is s[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 917 Figure 23-31. ROMON = 0 in Em ulation Expanded Mode 23.5.3.5 ROM Contr ol in Special T est Mode In special test mode the external b us is connected to the application. If the R OMON bit is set, the internal FLASH provides the data, otherwi[...]

Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev . 2.11 918 F reescale Semiconductor[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 919 Appendix A Electrical Characteristics A.1 General NO TE The electrical characteristics gi ven in this section should be used as a guide only . V alues cannot be guaranteed by Freescale and are subject to change without notice. This supplement cont[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 920 F reescale Semiconductor V SS1 and V SS2 are internally connected by metal. V DD A , V DDX , V DDR as well as V SSA , V SSX , V SSR are connected by anti-parallel diodes for ESD protection. NO TE In the follo wing context V DD35 is used for either V DDA ,V DDR , and V DDX[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 921 the injection current may flo w out of V DD35 and could result in external po wer supply going out of regulation. Ensure e xternal V DD35 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU [...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 922 F reescale Semiconductor A.1.6 ESD Protection and Latch-up Imm unity All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automoti ve grade integrated circuits. During the de vice qualification ESD stresses were performed for the Human Body M[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 923 A.1.7 Operating Conditions This section describes the operating conditions of the de vice. Unless otherwise noted those conditions apply to all the follo wing data. NO TE Please refer to the temperature rating of the de vice (C, V , M) with reg ar[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 924 F reescale Semiconductor A.1.8 P ower Dissipation and Thermal Characteristics Po wer dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The a verage chip-junction temperature ([...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 925 T able A-5. Thermal P ackage Characteristics 1 1 The values f or ther mal resistance are achiev ed by package sim ulations Num C Rating Symbol Min T yp Max Unit LQFP144 1 T Ther mal resistance LQFP144, single sided PCB 2 θ JA —— 4 1 ° C/W 2 [...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 926 F reescale Semiconductor A.1.9 I/O Characteristics This section describes the characteristics of all I/O pins except EXT AL, XT AL,XFC,TEST and supply pins. T able A-6. 3.3-V I/O Characteristics Conditions are 3.15 V < V DD35 < 3.6 V temperature from –40 ° C to +[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 927 T able A-7. 5-V I/O Characteristics Conditions are 4.5 V < V DD35 < 5.5 V temperature from –40 ° C to +140 ° C , unless otherwise noted I/O Characteristics for all I/O pins e xcept EXT AL, XT AL,XFC,TEST and supply pins . Num C Rating Sy[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 928 F reescale Semiconductor A.1.10 Supply Currents This section describes the current consumption characteristics of the de vice as well as the conditions for the measurements. A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted [...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 929 T able A-9. shows the configuration of the peripherals for run current measurement. T able A-9. P eripheral Configurations for Run Supply Current Measurements P eripheral Configuration MSCAN configured to loop-back mode using a bit rate of 1Mb[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 930 F reescale Semiconductor A.1.10.2 Additional Remarks In expanded modes the currents flo wing in the system are highly dependent on the load at the address, data, and control signals as well as on the duty cycle of those signals. No generally applicable numbers can gi ven[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 931 T able A-11. Pseudo Stop and Full Stop Current Conditions are shown in T able A-4 unless otherwise noted Num C Rating Symbol Min T yp Max Unit Pseudo stop current (API, RTI, and COP disab led) PLL off 10 C P C C P C P C P –40 ° C 27 ° C 70 ° [...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 932 F reescale Semiconductor A.2 A TD Characteristics This section describes the characteristics of the analog-to-digital con verter. A.2.1 A TD Operating Characteristics The T able A-12 and T able A-13 sho w conditions under which the A TD operates. The follo wing constraint[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 933 T able A-13. A TD Operating Characteristics 3.3V A.2.2 Factor s Influencing Accuracy Three factors — source resistance, source capacitance and current injection — ha ve an influence on the accuracy of the A TD. A.2.2.1 Source Resistance Due [...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 934 F reescale Semiconductor A.2.2.3 Current Injection There are two cases to consider . 1. A current is injected into the channel being con verted. The channel being stressed has con version v alues of $3FF ($FF in 8-bit mode) for analog inputs greater than V RH and $000 for[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 935 A.2.3 A TD Accuracy A.2.3.1 5-V Range T able A-15 specifies the A TD con version performance excluding an y errors due to current injection, input capacitance, and source resistance. A.2.3.2 3.3-V Range T able A-16 specifies the A TD con version[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 936 F reescale Semiconductor A.2.3.3 A TD Accuracy Definitions For the follo wing definitions see also Figure A-1 . Dif ferential non-linearity (DNL) is defined as the dif ference between two adjacent switching steps. The integral non-linearity (INL) is defined as the sum[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 937 Figure A-1. A TD Accuracy Definitions NO TE Figure A-1 sho ws only definitions, for specification v alues refer to T able A-15 . 1 5 Vin mV 10 15 20 25 30 35 40 50855090 5095 5100 51055110 5115 5120 50655070 5075 5080 5060 0 3 2 5 4 7 6 50 $3F7[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 938 F reescale Semiconductor A.3 NVM, Flash, and EEPROM NO TE Unless otherwise noted the abbre viation NVM (non volatile memory) is used for both Flash and EEPR OM. A.3.1 NVM Timing The time base for all NVM program or erase operations is deri ved from the oscillator . A mini[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 939 A.3.1.3 Sector Erase Erasing a 1024-byte Flash sector or a 4-byte EEPR OM sector takes: The setup time can be ignored for this operation. A.3.1.4 Mass Erase Erasing a NVM block takes: The setup time can be ignored for this operation. A.3.1.5 Blank[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 940 F reescale Semiconductor T able A-17. NVM Timing Characteristics Conditions are shown in T able A-4 unless otherwise noted Num C Rating Symbol Min T yp Max Unit 1 D Exter nal oscillator clock f NVMOSC 0.5 — 80 1 1 Restrictions for oscillator in crystal mode apply . MHz [...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 941 A.3.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life f ailures. The program/erase cycle count on the sector is incremented e very tim[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 942 F reescale Semiconductor Figure A-2. T ypical Endurance vs T emperature T ypical Endurance [10 3 Cycles] Operating T emperature T J [ ° C] 0 50 100 150 200 250 300 350 400 450 500 -40 -20 0 20 40 60 80 100 120 140 ------ Flash ------ EEPR OM[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 943 A.4 V oltage Regulator T able A-19. V oltage Regulator Electrical Characteristics Num C Characteristic Symbol Min T yp Max Unit 1 P Input voltages V VDDR,A 3.15 — 5.5 V 3 P Output voltage core Full perf or mance mode Reduced power mode Shutdown [...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 944 F reescale Semiconductor A.5 Reset, Oscillator , and PLL This section summarizes the electrical characteristics of the v arious startup scenarios for oscillator and phase-locked loop (PLL). A.5.1 Star tup T able A-20 summarizes sev eral startup characteristics explained i[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 945 If the MCU is woken-up by an interrupt and the f ast wake-up feature is enabled (FSTWKP = 1 and SCME = 1), the system will resume operation in self-clock mode after t fws . A.5.1.5 Pseudo Stop and W ait Recovery The recov ery from pseudo stop and [...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 946 F reescale Semiconductor T able A-21. Oscillator Characteristics Conditions are shown in T able A-4 unless otherwise noted Num C Rating Symbol Min T yp Max Unit 1a C Cr ystal oscillator range (loop controlled Pierce) f OSC 4.0 — 16 MHz 1b C Cr ystal oscillator range (fu[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 947 A.5.3 Phase Locked Loop The oscillator provides the reference clock for the PLL. The PLL´s v oltage controlled oscillator (VCO) is also the system clock source in self clock mode. A.5.3.1 XFC Component Selection This section describes the selecti[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 948 F reescale Semiconductor And finally the frequency relationship is defined as W ith the abov e values the resistance can be calculated. The e xample is shown for a loop bandwidth f C = 20 kHz: The capacitance C s can no w be calculated as: The capacitance C p should be [...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 949 The relati ve de viation of t nom is at its maximum for one clock period, and decreases tow ards zero for larger number of clock periods (N). Defining the jitter as: For N < 1000, the follo wing equation is a good fit for the maximum jitter: [...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 950 F reescale Semiconductor A.6 MSCAN A.7 SPI Timing This section provides electrical parametrics and ratings for the SPI. In T able A-24 the measurement conditions are listed. T able A-22. PLL Characteristics Conditions are shown in T able A-4 unless otherwise noted Num C R[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 951 A.7.1 Master Mode In Figure A-6 the timing diagram for master mode with transmission format CPHA = 0 is depicted. Figure A-6. SPI Master Timing (CPHA = 0) In Figure A-7 the timing diagram for master mode with transmission format CPHA=1 is depicted[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 952 F reescale Semiconductor In T able A-25 the timing characteristics for master mode are listed. A.7.2 Slave Mode In Figure A-8 the timing diagram for sla ve mode with transmission format CPHA = 0 is depicted. Figure A-8. SPI Slave Timing (CPHA = 0) T able A-25. SPI Master [...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 953 In Figure A-9 the timing diagram for sla ve mode with transmission format CPHA = 1 is depicted. Figure A-9. SPI Slave Timing (CPHA = 1) In T able A-26 the timing characteristics for sla ve mode are listed. T able A-26. SPI Slave Mode Timing Charac[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 954 F reescale Semiconductor A.8 External Bus Timing The follo wing conditions are assumed for all follo wing external b us timing values: • Crystal input within 45% to 55% duty • Equal loads of pins • Pad full dri ve (reduced dri ve must be of f) A.8.1 Normal Expanded [...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 955 T able A-27. Example 1a: Normal Expanded Mode Timing V DD35 = 5.0 V (EW AITE = 0) No. C Characteristic Symbol Min Max Unit — — F requency of inter nal bus f i D .C. 40.0 MHz — — Internal cycle time t cyc 25 ∞ ns — — F requency of ext[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 956 F reescale Semiconductor A.8.2 Normal Expanded Mode (External W ait Feature Enabled) Figure A-11. Example 1b: Normal Expanded Mode — Stretched Read Access CSx ADDRx RE DA T A x ADDR1 (Read) D A T A1 WE EW AIT UDS, LDS 3 6 7 1 8 2 ADDR2 12 13[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 957 Figure A-12. Example 1b: Normal Expanded Mode — Stretched Write Access CSx ADDRx RE D A T Ax (Write) D A T A1 WE EW AIT UDS, LDS 5 1 9 10 11 4 ADDR1 ADDR2 12 13[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 958 F reescale Semiconductor T able A-28. Example 1b: Normal Expanded Mode Timing V DD35 = 5.0 V (EW AITE = 1) No. C Characteristic Symbol 2 Stretch Cycles 3 Stretch Cycles Unit Min Max Min Max — — F requency of internal bus f i D .C. 40.0 D .C. 40.0 MHz — — Inter nal[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 959 A.8.3 Emulation Single-Chip Mode (Without W ait States) Figure A-13. Example 2a: Emulation Single-Chip Mode — Read Follo wed by Write ECLK R/W DA T A x ADDR1 IVD0 ADDR2 IVD1 (Read) D A T A1 (Write) D A T A2 ADDR3 LSTRB ECLK2X 1 1 2 3 4 5 6 7 8 9[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 960 F reescale Semiconductor T able A-29. Example 2a: Emulation Single-Chip Mode Timing V DD35 = 5.0 V (EW AITE = 0) No. C Characteristic 1 1 T ypical supply and silicon, room temperature only Symbol Min Max Unit — — Frequency of internal bus f i D .C. 40.0 MHz 1 — Cycl[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 961 A.8.4 Emulation Expanded Mode (With Optional Access Stretching) Figure A-14. Example 2b: Emulation Expanded Mode — Read with 1 Stretc h Cycle ECLK ADDR R/ W DA T A x LSTRB ECLK2X 1 2 3 4 5 6 8 9 12 12 ADDR [19:16]/ (Read) D A T A1 7 DA T A 0 ADD[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 962 F reescale Semiconductor Figure A-15. Example 2b: Emulation Expanded Mode Ò Write with 1 Stretc h Cycle ECLK R/ W D A T Ax (write) data1 LSTRB ECLK2X 11 10 1 2 3 4 5 6 7 12 12 ADDR1 ? ADDR1 x ADDR2 ADDR1 IQST A T0 ADDR1 ADDR2 ADDR1 ACC1 ADDR1 000 ADDR2 IQST A T1 ADDR ADD[...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 963 T able A-30. Example 2b: Emulation Expanded Mode Timing V DD35 = 5.0 V (EW AITE = 0) No. C Characteristic 1 1 T ypical supply and silicon, room temperature only Symbol 1 Stretch Cycle 2 Stretch Cycles 3 Stretch Cycles Unit Min Max Min Max Min Max [...]

Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev . 2.11 964 F reescale Semiconductor A.8.5 External T ag T rigger Timing Figure A-16. External T rigger Timing T able A-31. External T ag T rigger Timing V DD35 = 5.0 V No. C Characteristic 1 1 T ypical supply and silicon, room temperature only Symbol Min Max Unit 1 D F requency of i[...]

Appendix B Pac kage Information MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 965 Appendix B P ac kage Inf ormation B.1 General This section provides the ph ysical dimensions of the MC9S12XDP512 packages.[...]

Appendix B Pac kage Information MC9S12XDP512 Data Sheet, Rev . 2.11 966 F reescale Semiconductor B.2 144-Pin LQFP Figure B-1. 144-Pin LQFP Mechanical Dimensions (Case No. 918-03) N 0.20 T L-M 144 GA GE PLANE 73 109 37 SEA TING 108 1 36 72 PLANE 4X 4X 36 TIPS PIN 1 IDENT VIEW Y B B1 V1 A1 S1 V P G A S 0.1 C 2 θ VIEW AB J1 J1 140X 4X VIEW Y PLA TING[...]

Appendix B Pac kage Information MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 967 B.3 112-Pin LQFP P ackage Figure B-2. 112-Pin LQFP Mechanical Dimensions (Case No. 987) DIM A MIN MAX 20.000 BSC MILLIMETERS A1 10.000 BSC B 20.000 BSC B1 10.000 BSC C --- 1.600 C1 0.050 0.150 C2 1.350 1.450 D 0.270 0.370 E 0.450 0.750 F 0.270 0.330 G 0[...]

Appendix B Pac kage Information MC9S12XDP512 Data Sheet, Rev . 2.11 968 F reescale Semiconductor B.4 80-Pin QFP P ackage Figure B-3. 80-Pin QFP Mechanical Dimensions (Case No. 841B) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DA TUM PLANE -H- IS LOCA TED A T BOTT OM OF LEAD AND IS COINCIDEN[...]

Appendix C Recommended PCB Lay out MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 969 Appendix C Recommended PCB La yout The PCB must be carefully laid out to ensure proper operation of the v oltage regulator as well as of the MCU itself. The follo wing rules must be observed: • Every supply pair must be decoupled by a ceramic capac[...]

Appendix C Recommended PCB Lay out MC9S12XDP512 Data Sheet, Rev . 2.11 970 F reescale Semiconductor T able C-1. Recommended Decoupling Capacitor Choice Component Purpose T ype V alue C1 V DD1 filter capacitor Ceramic 220 nF C2 V DD2 filter capacitor (not av ailable on the 80-pin QFP packaging option) Ceramic X7R 220 nF C3 V DD A filter capacitor[...]

Appendix C Recommended PCB Lay out MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 971 Figure C-1. 144-Pin LQFP Recommended PCB Lay out C5 C4 C10 C9 R1 V DDR 1 V SSR1 V DDPLL V SSPLL C7 C8 Q1 C2 V DD2 V SS2 C1 V DD1 V SS1 C6 V DDX C12 V DDR2 C11 V DDX2 C3 V SSA V DD A V SSR2 V REGEN V SSX2[...]

Appendix C Recommended PCB Lay out MC9S12XDP512 Data Sheet, Rev . 2.11 972 F reescale Semiconductor Figure C-2. 112-Pin LQFP Recommended PCB Lay out C5 C4 C1 C6 C3 C2 C10 C9 R1 V DDX V SSX V DDR V SSR V DD1 V SS1 V DD2 V SS2 V DDPLL V SSPLL V DD A V SSA V REGEN C7 C8 Q1[...]

Appendix C Recommended PCB Lay out MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 973 Figure C-3. 80-Pin QFP Recommended PCB Lay out C5 C4 C3 C2 C10 C9 R1 C6 C1 V DD1 V SS1 V SS2 V DD2 V SSR V DDR VSSPLL V DDPLL V DD A V SSA V SSX V REGEN V DDX C7 C8 Q1 V SSPLL[...]

Appendix D Derivative Differences MC9S12XDP512 Data Sheet, Rev . 2.11 974 F reescale Semiconductor Appendix D Deriv ative Differences D .1 Memor y Sizes and P ac kage Options S12XD - F amily Device Package Flash RAM EEPROM ROM 9S12XDP512 144 LQFP 512K 32K 4K 112 LQFP 9S12XDT512 144 LQFP 20K 112 LQFP 80 QFP 9S12XDT384 144 LQFP 384K 20K 112 LQFP 80 Q[...]

Appendix D Derivative Differences MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 975 9S12XD128 1 112 LQFP 128K 8K 2K 80 QFP 9S12XD64 1 80 QFP 64K 4K 1K 1 P ar t includes module versions S12XDBGV3 and S12XMMCV3 which arenot co vered in this data sheet. Please ref er to the corresponding data sheets for detailed inf or mation. Device Pa[...]

Appendix D Derivative Differences MC9S12XDP512 Data Sheet, Rev . 2.11 976 F reescale Semiconductor D .2 Memor y Sizes and P ac kage Options S12XA - F amily Device Package Flash RAM EEPROM 9S12XA512 144 LQFP 512K 32K 4K 112 LQFP 80 QFP 9S12XA256 1 1 P ar t includes module versions S12XDBGV3 and S12XMMCV3 which are not cov ered in this data sheet. Pl[...]

Appendix D Derivative Differences MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 977 D .3 MC9S12XD-Famil y Flash Configuration 12345 1. XGA TE read access to Flash not possible on DG128/D128 and D64 2. Program P ages av ailable on DT384 are $E0 - $E7 and $F0 - $FF 3. Program P ages av ailable on DT256/DG256 are $E0 - $E7 and $F8 - $F[...]

Appendix D Derivative Differences MC9S12XDP512 Data Sheet, Rev . 2.11 978 F reescale Semiconductor D .4 P eripheral Sets S12XD - Famil y Device Package XGATE CAN SCI SPI IIC ECT PIT A/D I/O 9S12XDP512 144LQFP yes 5 6 3 2 8 4 2/24 119 112LQFP 5 4 3 1 8 4 2/16 91 9S12XDT512 144LQFP 3 6 3 1 8 4 2/24 119 112LQFP 3 4 3 1 8 4 2/16 91 80QFP 3 2 2 1 8 4 1/[...]

Appendix D Derivative Differences MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 979 D .5 P eripheral Sets S12XA - Famil y 2 ATD1 routed to PAD00-15 instead of PAD08-23. Device Package XGATE CAN SCI SPI IIC ECT PIT A/D I/O 9S12XA512 144LQFP yes no 6 3 1 8 4 2/24 119 112LQFP 4 3 1 8 4 2/16 91 80QFP 2 2 1 8 4 1/8 59 9S12XA256 144LQFP 4 [...]

Appendix D Derivative Differences MC9S12XDP512 Data Sheet, Rev . 2.11 980 F reescale Semiconductor D .6 Pinout explanations: • A/D is the number of modules/total number of A/D channels. • I/O is the sum of ports capable to act as digital input or output. – 144 Pin Packages: Port A = 8, B = 8, C=8, D=8, E = 6 + 2 input only, H = 8, J = 7, K = [...]

Appendix E Ordering Inf ormation MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 981 Appendix E Or dering Information The follo wing figure provides an ordering number e xample for the MC9S12XD-Family de vices Figure E-1. Order P ar t Number Example Customers who place orders using the generic MC partnumbers which are constructed usin[...]

Appendix E Ordering Inf ormation MC9S12XDP512 Data Sheet, Rev . 2.11 982 F reescale Semiconductor[...]

Appendix E Ordering Inf ormation MC9S12XDP512 Data Sheet, Rev . 2.11 F reescale Semiconductor 983 T able E-1. MC and SC P ar t Numbers MC P ART NUMBER (MASKSET -INDEPENDENT) FOR OUR RECOMMENDED MASKSET SC P ART NUMBER (MASKSET -SPECIFIC) FOR 0L15Y MASKSET ONL Y PKG MC9S12XDP512CPV SC104002CPV 112 MC9S12XDP512MPV SC104002MPV 112 MC9S12XDP512VPV SC10[...]

Appendix E Ordering Inf ormation MC9S12XDP512 Data Sheet, Rev . 2.11 984 F reescale Semiconductor MC9S12XDT512VFV SC104024VFV 144 MC9S12XDT384CFV SC104025CFV 144 MC9S12XDT384MFV SC104025MFV 144 MC9S12XDT384VFV SC104025VFV 144 MC9S12XD384CFV SC104026CFV 144 MC9S12XD384MFV SC104026MFV 144 MC9S12XD384VFV SC104026VFV 144 T able E-1. MC and SC P ar t Nu[...]

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