Hitachi H*/3694F-ZTAT manual

Hitachi Single-Chip Microcomputer H8/3694 Series H8/36 94 HD64336 94G, HD643 3694 H8/36 93 HD64336 93G, HD643 3693 H8/36 92 HD64336 92G, HD643 3692 H8/36 91 HD64336 91G, HD643 3691 H8/36 90 HD64336 90G, HD643 3690 H8/36 94F-ZTA T TM HD64F3 694G, H D64F3694 Hardware Manual ADE-602-252 Rev. 1.0 07/11/0 1 Hitachi, Ltd.[...]

Rev. 1.0, 0 7/01, page ii of xxi v[...]

Rev. 1.0, 0 7/01, Page iii of xxiv Cautions 1. Hitachi neither warrant s nor grant s licenses of any ri ghts of Hit achi’s or any t hird party’s patent, copyright , trademark, o r other inte llectual property rights for information c ontained in this document. Hitachi bears no responsibility for pr oblems that may arise with third party’s rig[...]

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Rev. 1.0, 0 7/01, Page v of xxiv Preface The H8/3694 Seri es is a singl e-chip microcomputer ma de up of the high-speed H8/3 00H CPU as its core, and the peripheral functions req uired to configure a system. T he H8/300H CPU has an instruction set th at is compatible with the H8/300 CPU. Target Users: This manual was written for us ers who will be [...]

Rev. 1.0, 0 7/01, page vi of xxiv 5. When the E10T is used, address breaks can be set as available to t he user, or for use by the E10T. If address breaks are set as bein g used by the E10T, the add ress break control registers must not be accessed. 6. When the E10T is us ed, NMI is an inp ut/output pin (open-drai n in out put mode), P85 and P87 ar[...]

Rev. 1.0, 0 7/01, Page vii of xxiv Contents Section 1 Overview........................................................................................................... ......... 1 1.1 Overview .................................................................................................................... ....... 1 1.2 Internal Block Diagram .[...]

Rev. 1.0, 0 7/01, page viii of xxiv 3.4.1 External Interrupts ............................................................................................... 50 3.4.2 Internal Interrupts ................................................................................................ 51 3.4.3 Interrupt Handling Sequence .............................[...]

Rev. 1.0, 0 7/01, Page ix of xxiv 6.4 Direct Transition ........................................................................................................... .... 78 6.4.1 Direct transition from the active mo de to the subactive mode ............................. 78 6.4.2 Direct transition from the s ubactive mode to the active mode .........[...]

Rev. 1.0, 0 7/01, page x of xxiv 9.1.4 Port Pull-Up Control Regis ter 1(PUCR1) ............................................................ 114 9.1.5 Pin Functions ....................................................................................................... 114 9.2 Port 2 ...................................................................[...]

Rev. 1.0, 0 7/01, Page xi of xxiv 11.3.5 Timer Control Register V1(TC RV1) ................................................................... 143 11.4 Operation.................................................................................................................. ......... 144 11.4.1 Timer V operation ...................................[...]

Rev. 1.0, 0 7/01, page xi i of xxiv Section 14 Serial Communication Interface3 (SCI3) ........................................ 181 14.1 Features ................................................................................................................... .......... 181 14.2 Input/Output Pins ...................................................[...]

Rev. 1.0, 0 7/01, Page xiii of xxiv 15.3.6 Slave Address Regis ter (SAR) ............................................................................. 232 15.3.7 I 2 C B us Transmit Data Register (IC DRT) ............................................................ 233 15.3.8 I 2 C B us Receive Data Register (ICDRR ) ...............................[...]

Rev. 1.0, 0 7/01, page xi v of xxiv Section 18 Power Supply Circuit ...................................................................... 273 18.1 W hen Using the Internal Power Supply St ep-Down Circuit ............................................. 273 18.2 When Not Us ing the Internal Power Supply Step-Down Circuit ..............................[...]

Rev. 1.0, 0 7/01, Page xv of xxiv Figures of Contents Section 1 Overview Figure 1- 1 Internal Block Diagram of H8/3694 Series of t he F-Z T AT TM and Mas k-ROM Versions ............................................................................................. 2 Figure 1- 2 Pin A rrangement of H8/3694 Series of the F- ZTAT TM and Mask-ROM Version[...]

Rev. 1.0, 0 7/01, page xvi of xxiv Figure 5-5 Ty pical Connection to Ceramic Oscillator .................................................................. 65 Figure 5-6 Ex ample of External Clock In put ................................................................................ 65 Figure 5-7 Block Diagram of the Subclock Generator ............[...]

Rev. 1.0, 0 7/01, Page xvii of xxiv Figure 11-8 C lear Timing by TMRIV Inpu t ............................................................................... 146 Figure 11-9 Puls e Output Example ............................................................................................. 147 Figure 11-10 Ex ample of Pulse Output Syn chronized to T[...]

Rev. 1.0, 0 7/01, page xviii of xxi v Figure 14- 3 Relation ship betw een Output Clock and Trans fer Data Phas e (A synchronous Mode)(Example with 8-Bit Data, Parity , T w o Stop Bits).............. 195 Figure 14-4 Sam ple SCI Initialization Flowchart ....................................................................... 196 Figure 14- 5 Exam ple [...]

Rev. 1.0, 0 7/01, Page xix of xxiv Figure 15-17 Sam ple Flowchart for Master Transmit Mode ...................................................... 246 Figure 15-18 Sam ple Flowchart for Master Receive Mode ........................................................ 247 Figure 15-19 Sam ple Flowchart for Slave Transmit Mode..............................[...]

Rev. 1.0, 0 7/01, page xx of xxi v Figure B.11 Port 7 Bl ock Diagram (P76) ................................................................................... 359 Figure B.12 Port 7 Bl ock Diagram (P75) ................................................................................... 360 Figure B.13 Port 7 Bl ock Diagram (P74) ...................[...]

Rev. 1.0, 0 7/01, Page xxi of xxiv Tables of Contents Section 1 Overview Table 1-1 Pin Functions ......................................................................................................... ....... 4 Section 2 CPU Table 2-1 Operation Notation...............................................................................................[...]

Rev. 1.0, 0 7/01, page xxii of xxiv Table 7-7 Command Sequ ence in Programmer Mode ................................................................ 96 Table 7-8 AC Characteristics in Transition to Memory Read Mode (Conditions : V CC = 5.0 V ±0.5 V, V SS = 0 V , T a = 25°C ± 5°C)................................. 98 Table 7-9 AC Characteristics i[...]

Rev. 1.0, 0 7/01, Page xxiii of xxiv Section 16 A/D Converter Table 16-1 Pin Configuration .................................................................................................. 25 5 Table 16-2 Analog Input Channels and Corresponding ADDR Re gisters .............................. 256 Table 16-3 A /D Conversion Time (Single Mode) .......[...]

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Rev. 1.0, 0 7/01, page 1 of 372 Section 1 Overview 1.1 Overview • High-speed H8/300H central processing u nit with an internal 16-bit architecture  Upward-compatible with H8/300 and H8 /300H CPUs on an object level  Sixteen 16-bit general regi sters  62 basic ins tructions • Various periphe ral functi ons  Timer A (can be used as a [...]

Rev. 1.0, 0 7/01, page 2 of 372 1.2 Internal Block Diagram P10/TMOW P11 P12 P14/ P15/ P16/ P17/ /TRGV P50/ P51/ P52/ P53/ P54/ P55/ / P56/SDA P57/SCL PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 V CC V SS V CL TEST AV CC P20/SCK3 P21/RXD P22/TXD P80/FTCI P81/FTIOA P82/FTIOB P83/FTIOC P84/FTIOD P85 P86 P87 P74/TMRIV P75/TMCIV P76/[...]

Rev. 1.0, 0 7/01, page 3 of 372 1.3 Pin Arran gement NC NC AV CC X2 X1 V CL TEST V SS OSC2 OSC1 V CC P50/ P51/ NC NC 1 2 3 4 5 6 7 8 9 1 01 11 2 1 31 41 5 1 6 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NC NC P22/TXD P21/RXD P20/SCK3 P87 P86 P85 P84/FTIOD P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI NC NC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 [...]

Rev. 1.0, 0 7/01, page 4 of 372 AVcc X2 X1 V CL TEST V SS OSC2 OSC1 Vcc P50/ P51/ 123 4 5 678 9 1 0 1 1 1 2 36 35 34 33 32 31 30 29 28 27 26 25 P22/TXD P21/RXD P20/SCK3 P87 P86 P85 P84/FTIOD P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 P14/ P15/ P16/ P17/ /TRGV PB4/AN4 PB5/AN5 PB6/AN[...]

Rev. 1.0, 0 7/01, page 5 of 372 1.4 Pin Functions Table 1-1 Pin Functions Pin No. Type Symbol FP-64E FP-64A FP-48F I/O Functions Power source V CC 12 10 Input Power suppl y pin. Conne ct this pin to the system pow er suppl y. pins V SS 9 7 Input Ground pin. C onnect t his pin to t he system power supply(0V) . AV CC 3 1 Input Analog power su pply pi[...]

Rev. 1.0, 0 7/01, page 6 of 372 Pin No. Type Symbol FP-64E FP-64A FP-48F I/O Functions Timer W FTCI 36 26 Input External event input pin. FTIOA to FTIOD 37 to 40 27 to 30 I/O Output compare output/ inpu t capture in put/ PWM output pin I 2 C bus inerface SDA 26 20 I/O IIC data I/O pin. Can dire ctly drive a bus by NMOS open-drai n output. (IIC) SCL[...]

Rev. 1.0, 0 7/01, page 7 of 372 Section 2 CPU This LSI has an H8 /3 00H CPU with an intern al 32-bit architecture that is up word-compatib le with the H8/300CPU, and su pports only normal mode, whic h has a 64-kbyte ad dress space. • Upward-compatible with H8 /300 CPUs  Can execute H8/30 0 CPUs object programs  Additional ei ght 16-bit e xt[...]

Rev. 1.0, 0 7/01, page 8 of 372 2.1 Address S pace and Memory Map The address space of this LSI is 64 kbytes, which inclu des the program area and the data area. Figures 2-1 show t he memory ma p. Interrupt vector On-chip ROM (32 kbytes) Not used Not used (1-kbyte work area for flash memory programming) Internal I/O register Internal I/O register H[...]

Rev. 1.0, 0 7/01, page 9 of 372 Interrupt vector On-chip ROM (16 kbytes) On-chip RAM (512 bytes) Internal I/O register H'0000 H'0033 H'0034 H'3FFF H'FF7F H'FF80 H'FFFF HD6433694G, HD6433694 (Mask ROM version) HD6433693G, HD6433693 (Mask ROM version) HD6433692G, HD6433692 (Mask ROM version) H'FD80 H'F730 [...]

Rev. 1.0, 0 7/01, page 10 of 372 2.2 Register Configuration The H8/300H CPU has the internal regis ters shown in fi gure 2-2. There are two types of re gisters; general registers and control registers. The control re gisters are a 24-bit program cou nter (PC), and an 8-b it con d ition code reg ister ( CCR). PC 23 0 15 0 7 0 7 0 E0 E1 E2 E3 E4 E5 E[...]

Rev. 1.0, 0 7/01, page 11 of 372 2.2.1 General Registers The H8/300H CPU has eight 32-bit general regist ers. These general re gisters are all funct ionally identical and can be used as both ad dress registers and data registers. When a general register is used as a data register, it can be accessed as a 32 -bit, 16-bit, or 8-bit register. Figure 2[...]

Rev. 1.0, 0 7/01, page 12 of 372 SP (ER7) F ree area Stack area Figure 2-4 Rela tionship b etween Stack Poin ter and Stack Area 2.2.2 Program Cou nter (PC) This 24-bit cou n ter indicates the address of the nex t instruction th e CPU will execute. The length of all CPU i nstructions is 2 bytes (one word), so the least s ignificant PC bi t is ignore[...]

Rev. 1.0, 0 7/01, page 13 of 372 Bit Bit Name Initial Value R/W Description 7 I 1 R/W Interrupt Mask Bit Masks int errupts ot her than NMI wh en set to 1. NMI is acce pted regar dless of t he I bit sett ing. The I bit is set to 1 at th e start of an except ion- handling sequence . 6 UI undefined R/W User Bit Can be wr itten and rea d by software us[...]

Rev. 1.0, 0 7/01, page 14 of 372 2.3 Data Formats The H8/300H CPU can proces s 1-bit, 4-bit (BCD), 8-bit (byte), 16-bi t (word), a nd 32-bit (longword) data. B it-manipulation instructions operate on 1-bit data by acces sing bit n (n = 0, 1, 2, …, 7) of byte operand data. Th e DAA and DAS decimal-adjust instructions treat byte data as two digits [...]

Rev. 1.0, 0 7/01, page 15 of 372 15 0 MSB LSB 15 0 MSB LSB 31 16 MSB 15 0 LSB ERn En Rn RnH RnL MSB LSB : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Data Type Data Format General Register Word data Word data Rn En Longword data Legend ERn F[...]

Rev. 1.0, 0 7/01, page 16 of 372 2.3.2 Mem ory Data Formats Figure 2-6 shows the data formats in memory. The H8/300H CPU can access word data and longword data i n memory, however wo rd or longword data must begi n at an even addres s. If an attempt is made to access word o r longword data at an odd ad dress, an address error does not occur, howeve[...]

Rev. 1.0, 0 7/01, page 17 of 372 2.4 Instruction Set 2.4.1 Tab le of Instru ctions Classifi ed by Function The H8/300H CPU has 62 instructions. Tables 2-2 to 2-9 summarize the instructions in each functional categ ory. The notat ion used in ta bles 2-2 to 2 -9 is defined bel ow. Table 2-1 Operation Notati on Symbol Description Rd General regi ster [...]

Rev. 1.0, 0 7/01, page 18 of 372 Table 2-2 Data Transfer Instructions Instruction Size * Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general reg isters or betw een a ge neral regist er and memory, or moves im mediate dat a to a genera l register. MOVFPE B (EAs) → Rd, Cannot be used in this LSI. MOVTPE B Rs → (EAs) Canno[...]

Rev. 1.0, 0 7/01, page 19 of 372 Table 2-3 Arithmetic Operations In structions (1) Instruction Size * Function ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addit ion or subtracti on on data i n two general r egisters, or on immediate data and dat a in a general regis ter (imm edi ate byte data cannot be s ubtracted from b yte data in a[...]

Rev. 1.0, 0 7/01, page 20 of 372 Table 2-3 Arithmetic Operations In structions (2) Instruction Size * Function DIVXS B/W Rd ÷ Rs → Rd Performs signed d ivision on data in two general regi sters: either 16 bits ÷ 8 bits → 8- bit quotient and 8-bit remai nder or 32 bit s ÷ 16 bits → 16-b it quotient and 16-bit remai nder. CMP B/W/L Rd – Rs[...]

Rev. 1.0, 0 7/01, page 21 of 372 Table 2-4 Logic Operations Instructions Instruction Size * Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a log ical AND op eration on a general regi ster and ano ther general re gister or imm ediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a log ical OR op eration on a general [...]

Rev. 1.0, 0 7/01, page 22 of 372 Table 2-6 Bit Manipula tion Inst ructions (1) Instruction Size * Function BSET B 1 → (<bit-No.> of <EAd> ) Sets a speci fied bit in a general re gister or memor y operand to 1. Th e bit number is spec ified by 3- bit immediate data or the l ower three bit s of a general re gister. BCLR B 0 → (<bit[...]

Rev. 1.0, 0 7/01, page 23 of 372 Table 2-6 Bit Manipula tion Inst ructions (2) Instruction Size * Function BXOR BIXOR B B C ⊕ (<bit-No.> of <EAd>) → C XORs the carry flag with a s pecified bit i n a general r egister or m emory operand and s tores the result in the carry flag. C ⊕ ¬ (<bit-No.> of <EA d>) → C XORs th[...]

Rev. 1.0, 0 7/01, page 24 of 372 Table 2-7 Branch Instructions Instruction Size Function Bcc * — Branches to a specified address if a specifi ed condition is true. The branching c onditions are listed b elow. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (f alse) Never BHI High C ∨ Z = 0 BLS Low or same C ∨ Z = 1 B[...]

Rev. 1.0, 0 7/01, page 25 of 372 Table 2-8 System Control Instructions Instruction Size * Function TRAPA — Starts trap-instr uction ex ception han dling. RTE — Returns from an except ion-handli ng routine. SLEEP — Causes a transiti on to a power-d own state. LDC B/W (EAs ) → CCR Moves the sour ce operand contents to the CCR. T he CCR size i[...]

Rev. 1.0, 0 7/01, page 26 of 372 Table 2-9 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+, R4L–1 → R4 L Until R 4L = 0 else ne xt; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5+ → @ER6+, R4–1 → R4 Until R 4 = 0 else ne xt; Transfers a da ta block. St arting from the a ddress se[...]

Rev. 1.0, 0 7/01, page 27 of 372 • Operation Field Indicates the fu nction of the ins truction, the a ddressing mo de, and the operatio n to be carried out on the ope rand. The operati on field always includes the fi rst four bits of the instruct ion. Some instructi ons have two operati on fields. • Register Field Specifies a general register. [...]

Rev. 1.0, 0 7/01, page 28 of 372 2.5 Addressing M odesand Effec tive Address C alculation The following des cribes the H8/3 00H CPU. In this LSI, t he upper eight bits are i gnored in the generated 24-bit address, s o the effective addres s is 16 bits . 2.5.1 Addressing Modes The H8/300H CPU s upports the eight ad dressing modes listed in t able 2-[...]

Rev. 1.0, 0 7/01, page 29 of 372 Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement c ontained in the instruction is added to an a ddress register (ERn) specified by the register field of the instructio n, and the lower 24 bits of the sum t he address of a memory operand. A 16-bit displacement is sign[...]

Rev. 1.0, 0 7/01, page 30 of 372 The instruction c ontains 8-bit (#x x:8), 16-bit (#x x:16), or 32-bit (#xx:32 ) immediate data as an operand. The ADDS, SUBS, INC, and DEC in structions contain immediate data imp licitly . So me bit manipulation ins tructions contain 3-bit i mmediate data i n the instructi on code, specifyi ng a bit number. The TRA[...]

Rev. 1.0, 0 7/01, page 31 of 372 Table 2-12 Effective Address Calculation (1) No 1 r op 31 0 23 2 3 Register indirect with displacement @(d:16,ERn) or @(d:24,ERn) 4 r op disp r op rm op rn 31 0 0 r op 23 0 31 0 disp 31 0 31 0 23 0 23 0 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Register direct(Rn) Ge[...]

Rev. 1.0, 0 7/01, page 32 of 372 Table 2-12 Ef fective Address Calculation ( 2) No 5 op 23 0 abs @aa:8 7 H'FFFF op 23 0 @aa:16 @aa:24 abs 15 16 23 0 op abs 6 op IMM #xx:8/#xx:16/#xx:32 8 Addressing Mode and Instruction Format Absolute address Immediate Effective Address Calculation Effective Address (EA) Sign extension Operand is immediate dat[...]

Rev. 1.0, 0 7/01, page 33 of 372 2.6 Basic Bus Cycle CPU operation i s synchronized b y a system clock ( ø) or a subclock ( ø SUB ). The period from a ris ing edge of ø or ø SUB to the next risi ng edge is call ed one state. A bus c ycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memo ry [...]

Rev. 1.0, 0 7/01, page 34 of 372 2.6.2 On-Chip Peripheral Modules On-chip peripheral mod ules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description o n the data bus widt h and number of accessing states of each register, refer to section 19, Inter nal I/O Registers. Registers [...]

Rev. 1.0, 0 7/01, page 35 of 372 2.7 CPU States There are four C PU states: the reset state, program execution state, program halt state, and exception-handling state. The pr ogram execution state includes active mode and subactive mode. For the program halt state there are a sleep m ode, standby mode, a nd sub-sleep mode. These states are shown in[...]

Rev. 1.0, 0 7/01, page 36 of 372 Reset state Program halt state Exception-handling state Program execution state Reset cleared SLEEP instruction executed Reset occurs Interrupt source Reset occurs Interrupt source Exception- handling complete Reset occurs Figure 2-12 S tate Transiti ons 2.8 Usage Notes 2.8.1 Notes on Data Access to Emp ty Areas The[...]

Rev. 1.0, 0 7/01, page 37 of 372 Example 1 : Bit manipulation for the timer load register and timer counter (Applicable for timer B and timer C, not for the series of this LSI.) Figure 2-13 shows an example of a timer in which two timer registers are assigned to the same address. When a bit mani pulation instruction access es the timer load registe[...]

Rev. 1.0, 0 7/01, page 38 of 372 • Prior to executing BSET in struction P57 P56 P55 P54 P53 P52 P51 P50 Input/outp ut Input Input Output Output Output O utput Output Output Pin state Low level High level Low level Low level Low level Low level Low level Low level P C R 5 001111 11 P D R 5 100000 00 • BSET instruction ex ecuted instruction BSET [...]

Rev. 1.0, 0 7/01, page 39 of 372 • Prior to executing BSET in struction MOV.B #80, R0L MOV.B R0L, @RAM0 MOV.B R0L, @PDR5 The PDR5 value (H'8 0) is written to a work area in memory (RAM0) as well as to PDR5. P57 P56 P55 P54 P53 P52 P51 P50 Input/outp ut Input Input Output Output Output O utput Output Output Pin state Low level High level Low [...]

Rev. 1.0, 0 7/01, page 40 of 372 • Prior to executing BCLR in struction P57 P56 P55 P54 P53 P52 P51 P50 Input/outp ut Input Input Output Output Output O utput Output Output Pin state Low level High level Low level Low level Low level Low level Low level Low level P C R 5 001111 11 P D R 5 100000 00 • BCLR instruction executed BCLR #0, @PCR5 The[...]

Rev. 1.0, 0 7/01, page 41 of 372 • Prior to executing BCLR in struction MOV.B #3F, R0L MOV.B R0L, @RAM0 MOV.B R0L, @PCR5 The PCR5 value (H'3 F) is written to a work area in memory (RAM0) as well as to PCR5. P57 P56 P55 P54 P53 P52 P51 P50 Input/outp ut Input Input Output Output Output O utput Output Output Pin state Low level High level Low [...]

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Rev. 1.0, 0 7/01, page 43 of 372 Section 3 Exception Handling Exception handl ing may be cause d by a reset, a tra p instruction (TRAPA), or inte rrupts. • Reset A reset has t he highest exception pri ority. Exception handl ing starts as soon as the reset is cleared by the RES pin. The chip i s also reset when t he watchdog timer overflows, and e[...]

Rev. 1.0, 0 7/01, page 44 of 372 Table 3-1 Exception Sources and Vector Address Vector Exception Source s Number Vector Address Priority Reset 0 H'0000 to H'0001 High Reserved f or system use 1 to 6 H'0002 to H' 000D NMI 7 H'000E to H'000F Trap instr uction (#0) 8 H'0010 to H'0011 (#1) 9 H'0012 to H&apos[...]

Rev. 1.0, 0 7/01, page 45 of 372 Vector Exception Source s Number Vector Address Pr iority IIC2 Transmit dat a empty Transmit end Receive data ful l NACK detect ion Arbitration lo st/Overrun err or Stop conditio ns detecte d 24 H'0030 to H'0031 High A/D conver sion end 25 H'0032 to H'0033 Low Note : * A low-vo ltage dete ction i[...]

Rev. 1.0, 0 7/01, page 46 of 372 Bit B it Name Initial V alue R/W Description 2 IEG2 0 R/W IRQ2 Edge Se lect 0: Falling ed ge of IRQ2 p in input is detected 1: Rising edge of IRQ2 pin input is d etected 1 IEG1 0 R/W IRQ1 Edge Se lect 0: Falling ed ge of IRQ1 p in input is detected 1: Rising edge of IRQ1 pin input is d etected 0 IEG0 0 R/W IRQ0 Edge[...]

Rev. 1.0, 0 7/01, page 47 of 372 3.2.3 In terrupt Enable Regi ster 1(IENR1) IENR1 enables direct tran sition interrupts, tim er A overflow interrupts, and external p in interrupts. Bit B it Name Initial V alue R/W Description 7 IENDT 0 R/W Direct Transfer I nterrupt Enable When this bit is set to 1, direct transit ion interrupt requests are enabled[...]

Rev. 1.0, 0 7/01, page 48 of 372 3.2.4 In terrupt Flag Register 1(I RR1) IRR1 is a status flag register for direct transit ion interrupt s, timer A overfl ow interrupts , and IRQ3 to IRQ0 interrupt reques ts. Bit B it Name Initial V alue R/W Description 7 IRRDT 0 R/W Direct Transfer Interrupt Request Flag [Setting cond ition] When a dir ect transfe[...]

Rev. 1.0, 0 7/01, page 49 of 372 3.2.5 Wak eup Interrupt Fl ag Register(IWPR) IWPR is a st atus flag register for WKP5 to WKP0 interru pt requests. Bit B it Name Initial V alue R/W Description 7 6 − − 1 1 − − Reserve d These bits ar e always read as 1, and cannot be modifie d. 5 IWPF5 0 R/W WKP5 Interrupt Reque st Flag [Setting cond ition] [...]

Rev. 1.0, 0 7/01, page 50 of 372 3.3 Reset When the RES pin goes lo w, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip pe ripheral modules are initialized by the reset. To ensure that this LS I is reset at power-up, hold the RES pin low until the cloc k pulse generator outp u t stab[...]

Rev. 1.0, 0 7/01, page 51 of 372 WKP5 to WKP0 Interrupts WKP5 to WKP0 interrupts are requested by input signa ls to pins WKP 5 to WKP 0. These six interrupts have the same vector addresses , and are detected indivi dually by eit her rising edge sensing or fal ling edge s ensing, depe nding on the set tings of bits WPEG5 to W PEG0 in IEGR2. When pin[...]

Rev. 1.0, 0 7/01, page 52 of 372 3.4.3 Interr upt Handling Seque nce Interrupt s are controll ed by an inter rupt control ler. Interrupt operat ion is desc ribed as follows . 1. If an interrupt occurs while th e NMI or in terrup t enable b it is set to 1 , an interrupt request signal is sent to th e interrupt contro ller. 2. When mu ltip le interru[...]

Rev. 1.0, 0 7/01, page 53 of 372 PC and CCR saved to stack SP (R7) SP – 1 SP – 2 SP – 3 SP – 4 Stack area SP + 4 SP + 3 SP + 2 SP + 1 SP (R7) Even address Prior to start of interrupt exception handling After completion of interrupt exception handling Legend: PC H : PC L : CCR: SP: Upper 8 bits of program counter (PC) Lower 8 bits of program[...]

Rev. 1.0, 0 7/01, page 54 of 372 Vector fetch ø Internal address bus Internal read signal Internal write signal (2) Internal data bus (16 bits) Interrupt request signal (9) (1) Internal processing Prefetch instruction of interrupt-handling routine (1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becom[...]

Rev. 1.0, 0 7/01, page 55 of 372 3.5 Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC an d CCR will not be sav ed correctly, leading to a program crash. To prevent th is, all in terrupt requests, including NMI, are disabled immediately after a reset. Since th[...]

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Rev. 1.0, 0 7/01, page 57 of 372 Section 4 Address Break The address brea k simplifies on-board program debugging. It requests an ad dress break inter rupt when th e set break co ndition is sa tisf ied. Th e interru p t request is n o t affec te d by the I b it of CCR. Break conditions that can be set include instruction execution at a specific add[...]

Rev. 1.0, 0 7/01, page 58 of 372 4.1.1 Address Break Control Register(ABRKCR) ABRKCR s ets address break co nditions. Bit B it Name Initial V alue R/W Description 7 RTINTE 1 R/W RTE Interrupt En able When this bit is 0, the i nterrupt immedi ately after executing R TE is maske d and then o ne instr uction must be executed . When this bit is 1, the [...]

Rev. 1.0, 0 7/01, page 59 of 372 Table 4-1 Access and Data Bus Used Word Access Byte Access Even Address Odd Address Even Address Odd Address ROM space Upper 8 bit s Lower 8 bits Upper 8 bits Upper 8 bits RAM space Upper 8 bits Lower 8 bits U pper 8 bits Upper 8 bit s I/O register wi th 8-bit data bus width Upper 8 bits Upper 8 bit s Upper 8 bits U[...]

Rev. 1.0, 0 7/01, page 60 of 372 4.1.4 Break Data Registers (BDRH, BDRL) BDR (BDRH, BDRL) i s a 16-bit read/write register that sets the d a ta fo r generating an address break interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is co mpared with the lower 8-bit data bus. When memory or regist ers are accessed by byte, the upper 8-bit d[...]

Rev. 1.0, 0 7/01, page 61 of 372 MOV instruc- tion 1 prefetch Register setting • ABRKCR = H'A0 • BAR = H'025A Program 0258 025A 025C 0260 0262 : * NOP NOP MOV.W @H'025A,R0 NOP NOP : 025C Address bus φ Interrupt request 025E 0260 025A 0262 0264 SP-2 MOV instruc- tion 2 prefetch NOP instruc- tion prefetch MOV instruc- tion executi[...]

Rev. 1.0, 0 7/01, page 62 of 372 RTE instruc- tion prefetch Register setting • ABRKCR = H'10 Program 0258 025A 025C 0260 0262 : NOP NOP MOV.W @H'025A,R0 NOP NOP : 039C Address bus φ Interrupt request 039E SP SP+2 025C 025E Interrupt request is disabled 0260 NOP instruc- tion prefetch MOV instruc- tion 1 prefetch MOV instruc- tion 2 pre[...]

Rev. 1.0, 0 7/01, page 63 of 372 Section 5 Clock Pulse Generators Clock oscillator circu itry (CPG: clock pu lse generator) is provided on -chip, including bo th a system clock pul se generator and a s ubclock puls e generator. The syst em clock pulse ge nerator consists of a system clock oscillator, a d uty correction circuit, and sy stem clo ck d[...]

Rev. 1.0, 0 7/01, page 64 of 372 LPM Note : LPM: Low-power mode (standby mode, subactive mode, or subsleep mode) 2 1 OSC OSC Figure 5-2 Block Diagram of the S ystem Clock Generator 5.1.1 Connecting a Crystal Oscilla to r Figure 5- 3 sh ows a typical metho d of connecting a crystal oscillator. An AT-cut parallel- resonance crys tal resonator sho uld[...]

Rev. 1.0, 0 7/01, page 65 of 372 5.1.2 Connecting a Ceramic Oscillato r Figure 5- 5 sh ows a typical metho d of connecting a ceramic oscillator. OSC 1 OSC 2 C 1 C 2 C 1 = 30 pF ±10% C 2 = 30 pF ±10% Figure 5-5 Ty pica l Connection to Ceramic Oscillato r 5.1.3 Extern al Clock Inpu t Method Connect an exter nal clock signal t o pin OSC 1 , and leav[...]

Rev. 1.0, 0 7/01, page 66 of 372 5.2.1 Connecting a 3 2.768-kH z Crystal Oscillator Clock pulse s can be supplied to the subclock di vider by co nnecting a 32.768 -kHz crystal oscillator, as shown in figure 5-8. Figure 5- 9 sh ows the equivalen t circuit of the 32.768- kHz crystal oscillator. X X C 1 C 2 1 2 C = C = 15 pF (typ.) 12 Figure 5-8 Typic[...]

Rev. 1.0, 0 7/01, page 67 of 372 5.3 Prescalers 5.3.1 Prescaler S Prescaler S i s a 13-bit counter using the s ystem clock (ø) as i ts input clock. The divided output is used for the internal cloc k of on-chip periphe ral modules. Prescaler S is initialized to H'0000 by a reset, and st arts counting on ex it from the rese t state. In standb y[...]

Rev. 1.0, 0 7/01, page 68 of 372 5.4.2 Notes on Board Design When using a crystal resonator (ceramic resonator ), place the resonator and its load capacitors as close as possible to the OSC 1 and OSC 2 pins . Other signal li nes should be ro uted away from the oscillator circuit to p r ev ent induction from in terfering with correct oscillation (se[...]

Rev. 1.0, 0 7/01, page 69 of 372 Section 6 Power-down Modes This LSI has s ix modes of operati on after a res et. These include a normal active mo de and four power-down modes , in which power di ssipation i s significantl y reduced. The mod ule standby mode reduces power dissipation by selectively haltin g on-chip module functio ns. • Active mod[...]

Rev. 1.0, 0 7/01, page 70 of 372 6.1.1 System Control Regi ster 1(SYSCR1) The SYSCR 1 register controls the power-down modes, as well as SYS CR2. Bit B it Name Initial V alue R/W Description 7 SSBY 0 R/W Software Standby This bit se lects the m ode to trans it after the e xecution o f the SLEEP instruct ion. 0: Enters the s leep mode or s ubsleep m[...]

Rev. 1.0, 0 7/01, page 71 of 372 Table 6-1 Operating Frequency and Waiting Time STS2 STS1 STS0 Waiting Time 16 MHz 10 MHz 8 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz 0 0 0 8,192 stat es 0.5 0.8 1.0 2.0 4.1 8.1 16.4 1 16,384 stat es 1.0 1.6 2.0 4.1 8.2 16.4 32.8 1 0 32,768 stat es 2.0 3.3 4.1 8.2 16.4 32.8 65.5 1 65,536 stat es 4.1 6.6 8.2 16.4 32.8 65.5 131.1 [...]

Rev. 1.0, 0 7/01, page 72 of 372 6.1.2 System Control Regi ster 2(SYSCR2) The SYSCR 2 register controls the power-down modes, as well as SYS CR1. Bit B it Name Initial V alue R/W Description 7 6 5 SMSEL LSON DTON 0 0 0 R/W R/W R/W Sleep Mode Se lection Low Speed on Flag Direct Tran sfer on Flag These bits select the m ode to enter aft er the execut[...]

Rev. 1.0, 0 7/01, page 73 of 372 Bit B it Name Initial V alue R/W Description 7 − 0 − Reserve d This bit is always read as 0 and cann ot be modif ied 6 MSTIIC 0 R/W IIC2 Modul e Standby IIC2 enters t he standb y mode when t his bit is set to 1 5 MSTS3 0 R/W SCI3 Module Stan dby SCI3 enters t he standby mode when th is bit is set to 1 4 MSTAD 0 [...]

Rev. 1.0, 0 7/01, page 74 of 372 Reset state Standby mode Active mode Sleep mode Subsleep mode Subactive mode Program halt state Program execution state Program halt state SLEEP instruction SLEEP instruction Interrupt Direct transition interrupt Direct transition interrupt Notes: 1. To make a transition to another mode by an interrupt, make sure in[...]

Rev. 1.0, 0 7/01, page 75 of 372 Table 6- 2 Tra nsition Mode af ter SLEEP Instr uction Ex ecutio n and Tran sition Mo de due to Interrupt DTON SSBY SMSEL LSON Transition Mode aft er SLEEP Instruction Execution Transition M ode due to Interrupt 0 0 0 0 Sleep mode Activ e mode 1 Subactive m ode 1 0 Subsleep mo de Active mode 1 Subactive m ode 1 X X S[...]

Rev. 1.0, 0 7/01, page 76 of 372 Table 6-3 Internal State in Each Operating Mode Function Active Mode Sleep Mode Subactive Mode Subsleep Mode Standby Mode System clock osci llat or Functioning Func tioning Halted Halted Halted Subclock oscill at or Functioning Func t i oning Functioning Functioning Functioning Instructi ons Functioning Halted Func [...]

Rev. 1.0, 0 7/01, page 77 of 372 When the RES pin goes low, the CPU goes into the reset state and the sleep m ode is cleared. 6.2. 2 Sta ndby Mode In the standby mo de, the clock p ulse generator st ops, so the CPU and o n-chip perip heral modules stop functioni ng. However, as long as the rate d voltage is s upplied, the c ontents of CPU regi ster[...]

Rev. 1.0, 0 7/01, page 78 of 372 6.2.4 Subactiv e Mo de The operating fre quency of t he subactive mode is selected from ø W /2, ø W /4, and ø W /8 by the SA1 and SA0 bits in SYSCR2. The operating frequency changes to the s et frequency after SLEEP instruction execution. When the SLEEP instruction is executed i n the subactive mode, a transition[...]

Rev. 1.0, 0 7/01, page 79 of 372 Legend tosc: OSC clock cycle time tw: Watch clock cy cle tim e tcyc: System clock (ø) cycle time tsubcyc: Subclock (ø SUB ) cycle time 6.4.2 Direct Transition from the Subactive Mode to the Activ e Mo de The time from the start of SLEEP inst ruction execution to the end of interrupt exception handling (the direct [...]

Rev. 1.0, 0 7/01, page 80 of 372[...]

Rev. 71, 07/01, page 81 of 3 72 Section 7 ROM The features of the 32-b it flash memory built into the flash memory (F-ZTAT) version are summarized below. • Programmin g/erase methods  The flash memo ry is programm ed 128 bytes at a time. Erase is perf ormed in singl e-block units. The flas h memory is confi gured as foll ows: 1 kbyte × 4 bl o[...]

Rev. 1.0, 0 7/01, page 82 of 372 H'007F H'0000 H'0001 H'0002 H'00FF H'0080 H'0081 H'0082 H'03FF H'0380 H'0381 H'0382 H'047F H'0400 H'0401 H'0402 H'04FF H'0480 H'0481 H'0481 H'07FF H'0780 H'0781 H'0782 H'087F H'0800 H&apo[...]

Rev. 71, 07/01, page 83 of 3 72 7.2.1 Flash Memory Control Regi ster 1 (FLMCR1) FLMCR1 is a regi ster that makes t he flash memory change t o program mode , program-verify mode, erase mode, or erase-verify m ode. For detail s on regist er setting, refer to section 7.4, F lash Memory Programmin g/Erasing. Bit Bit Name Initial Value R/W Description 7[...]

Rev. 1.0, 0 7/01, page 84 of 372 7.2.2 Flas h Memory Control Regi ster 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/e rasing. FLMCR2 is a read-only register, and shou ld not be written to . Bit Bit Name Initial Value R/W Description 7 FLER 0 R Flash Memory Error Indicates th at an error has occurr ed during a [...]

Rev. 71, 07/01, page 85 of 3 72 7.2.4 Flash Memory Power Control Register (FL PWCR) FLPWCR enables or disables a transition to the flash memory power-do wn mode when the LSI switches to subactive mode. The power s upply circ uit can be read i n the subactive mode, although it is part ly halted in the power-d own mode. Bit B it Name Initial Value R/[...]

Rev. 1.0, 0 7/01, page 86 of 372 7.3 On-Board Programming Modes There are two modes for programmi ng/erasing of the flash memory; boot mode, which enables on- board programmin g/erasing, an d programmer mode, i n which programming/e rasing is perfor med with a PROM programmer. On-board pro gramming/erasing can al so be performe d in user program mo[...]

Rev. 71, 07/01, page 87 of 3 72 4. After matchin g the bit rates, the chip transmits on e H'00 byte to the host to indicate the completion o f bit rate a djustment. The host shoul d confirm that this adjustment e nd indicati on (H'00) has been received n ormally, and transmit one H'55 byte to the chip. If reception could not be perfo[...]

Rev. 1.0, 0 7/01, page 88 of 372 Table 7-2 Boot Mode Operation Item Host Operation LSI Operation Branches to boot program at reset-start. Processing Contents Processing Contents Bit rate adjustment Continuously transmits data H'00 at specified bit rate. · Measures low-level period of receive data H'00. · Calculates bit rate and sets it [...]

Rev. 71, 07/01, page 89 of 3 72 7.3.2 Programm ing/Erasi ng in User Program Mode On-board program ming/erasing of an individ ual flash memory block can als o be performed in us er program mode by branching t o a user program/eras e control pr ogram. The user mus t set branchi ng conditions and provide on-board means of supplyin g programmi ng data.[...]

Rev. 1.0, 0 7/01, page 90 of 372 7.4 Flash Memory Programming/Erasing A software method using the CPU is employed to pr ogram and erase fl ash memory in the on- board programmin g modes. Dependi ng on the FLMCR 1 setting, the flas h memory operates in one of the followi ng four modes: Program mode, p rogram-verify m ode, erase mode, and erase-verif[...]

Rev. 71, 07/01, page 91 of 3 72 START End of programming Set SWE bit in FLMCR1 to 1 Write pulse application subroutine Wait 1 µ s Apply Write Pulse End Sub Set PSU bit in FLMCR1 to 1 WDT enable Disable WDT Wait 50 µ s Set P bit in FLMCR1 to 1 Wait (Wait time=programming time) Clear P bit in FLMCR1 to 0 Wait 5 µ s Clear PSU bit in FLMCR1 to 0 Wai[...]

Rev. 1.0, 0 7/01, page 92 of 372 Table 7-4 Reprogra m Data Comput ation Ta ble Program Data Verify Data Reprogram Data Comments 0 0 1 Programming complet ed 0 1 0 Reprogram bit 101 — 1 1 1 Remains in erased s tate Table 7-5 Additional- Progra m Da ta Computa tion Table Reprogram Data Verify Data Additional-Program Data Comments 0 0 0 Additional-p[...]

Rev. 71, 07/01, page 93 of 3 72 6. If the read data is not erased erased successfully, set erase mode a gain, and repeat the erase/erase-verify sequen ce as before. The maxim um numb er of repetitions o f th e erase/erase- verify seque nce is 100. 7.4.3 Interrupt Handli ng when Progra mming /Erasing Flash Memory All interrupts, inclu ding the NMI i[...]

Rev. 1.0, 0 7/01, page 94 of 372 Erase start Set EBR1 Enable WDT Wait 1 µ s Wait 100 µ s Set SWE bit in FLMCR1 to 1 n = 1 Set ESU bit in FLMCR1 to 1 Set E bit to 1 Wait 10 µ s Clear E bit to 0 Wait 10 µ s Clear ESU bit in FLMCR1 to 0 10 µ s Disable WDT Read verify data Increment address V erify data = all 1s ? Last address of block ? All erase[...]

Rev. 71, 07/01, page 95 of 3 72 7.5 Program/Erase Protection There are three kin ds of flash memor y program/erase protecti on; hardware prot ection, software protection, a nd error protect ion. 7.5.1 Hardware Protecti on Hardware protecti on refers to a st ate in which prog ramming/erasing of flash memory is forcibly disabled or aborted because o [...]

Rev. 1.0, 0 7/01, page 96 of 372 7.6 Programmer Mode In programmer mo de, a PROM programmer ca n be used to perform progra mming/erasing vi a a socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU device type with the on-chip Hitachi 64-kbyte flas h memory (F-ZTAT64V 5). A 10-MHz input clock is require d. For[...]

Rev. 71, 07/01, page 97 of 3 72 H8/3694F FP-64A/FP-64E Socket Adapter (Conversion to 32-pin arrangement) Pin No. Pin Name P54 P76 P20 P80 P81 P82 P83 P84 P85 P86 P87 P10 P14 P15 P16 P17 P50 P51 P52 P53 P21 P55 P56 P57 P74 P75 P22 TEST PB3 AV CC V CC X1 V SS V CL PB2 PB1 PB0 OSC1, OSC2 (OPEN) HN28F101 (32 Pins) Pin No. Pin Name 1 26 2 3 31 13 14 15 [...]

Rev. 1.0, 0 7/01, page 98 of 372 7.6.3 Mem ory Read Mode 1. After completio n of auto-program/auto-erase/status read operatio n s, a transition is made to the command wait state. When reading mem ory contents, a transition to memory read mode must first be made with a command write, after whic h the memory contents are read. Once memory read mode h[...]

Rev. 71, 07/01, page 99 of 3 72 Table 7-9 AC Characteristics i n Transition from Memory Read Mode to Another Mode (Conditions : V CC = 5.0 V ±0.5 V, V SS = 0 V, T a = 25°C ±5 °C) Item Symbol Min Max Unit Notes Comm and write cycle t nxtc 20 — µs Figure 7-7 CE hold time t ceh 0— n s CE setup time t ces 0— n s Data hold tim e t dh 50 — n[...]

Rev. 1.0, 0 7/01, page 1 00 of 372 A15–A0 I/O7–I/O0 t acc t acc t oh t oh Address stable Address stable Figure 7-8 CE and OE Enab le State Read Tim ing Waveforms A15–A0 I/O7–I/O0 t acc t ce t oe t oe t ce t acc t oh t df t df t oh Address stable Address stable Figure 7-9 CE and OE Clock Sys tem Read Timin g Waveforms 7.6.4 Au to-Program Mod[...]

Rev. 71, 07 /01, page 10 1 of 372 7. Perform one auto-program operation for a 128-byte block fo r each address. Two or more additional pr ogramming operatio ns cannot be per formed on a previ ously programmed a ddress block. 8. Confirm normal end of auto-pr ogramming by c hecking I/O6. Alternat ively, stat us read mode can also be used for this pur[...]

Rev. 1.0, 0 7/01, page 1 02 of 372 A15–A0 I/O7 I/O6 I/O5–I/O0 t wep t ds t dh t f t r t as t ah t wsts t write t spa t ces t ceh t nxtc t nxtc Address stable H'40 H'00 Data transfer 1 to 128 bytes Write operation end decision signal Write normal end decision signal Figure 7-10 Au to-Program Mode Timing Waveform s 7.6.5 Au to-Erase Mod[...]

Rev. 71, 07 /01, page 10 3 of 372 Table 7-12 AC Characteristics in Au to-Erase Mode (Conditions : V CC = 5.0 V ±0.5 V, V SS = 0 V, T a = 25 °C ±5°C) Item Symbol Min Max Unit Notes Comm and write cycle t nxtc 20 — µs Figure 7-1 1 CE hold time t ceh 0— n s CE setup time t ces 0— n s Data hold tim e t dh 50 — ns Data setup tim e t ds 50 ?[...]

Rev. 1.0, 0 7/01, page 1 04 of 372 7.6.6 Statu s Read Mode 1. Status read mode is pr ovided to ident ify the ki nd of abnormal e nd. Use this mode when an abnormal end occurs in auto-pr ogram mode or a uto-erase mode. 2. The return code is retained until a com m and write other than a status read mode comm and write is executed. 3. Table 7-13 shows[...]

Rev. 71, 07 /01, page 10 5 of 372 Table 7-14 St a tus Read Mode Return Code s Pin Name Initial Value Indications I/O7 0 1: Abnormal en d 0: Normal end I/O6 0 1: Command error 0: Otherwi se I/O5 0 1: Programm ing error 0: Otherwi se I/O4 0 1: Erasing error 0: Otherwi se I/O3 0 Undefined I/O2 0 Undefined I/O1 0 1: Over cou nting of writin g or erasin[...]

Rev. 1.0, 0 7/01, page 1 06 of 372 7.6.8 Programm er Mode Trans ition Time Commands cannot be accepted during the oscillation s tabilization period or the pro grammer mode setup period. After the pro grammer mode setu p time, a transiti on is made to mem ory read mode. Table 7-1 6 St ipulated Tran sition Times t o Command Wa it State Item Symbol Mi[...]

Rev. 71, 07 /01, page 10 7 of 372 7.7 Power-Down States for Flash Memory In user mode, the flash memory will operate in either of the followin g states: • Normal operatin g mode The flash memory can be read and written to at high speed. • Power-down operatin g mode The power supply ci rcuit of t he flash memory is partly halted an d can be read[...]

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Rev. 1.0, 0 7/01, page 1 09 of 372 Section 8 RAM This LSI has 2 kb yte, 1 kbyte o r 512 kbytes of on-chip hi gh-speed st atic RAM. The RAM i s connected to the CPU by a 1 6-bit data bus, enabling two-state access by the CPU to both byte data and word data. RAM0300A000 0_00002001 0700[...]

Rev. 1.0, 0 7/01, page 1 10 of 372[...]

Rev. 1.0, 0 7/01, page 1 11 of 372 Section 9 I/O Ports The series of t his LSI has twent y-nine general I/ O ports and eig ht input-only ports. Port 8 is a large current port, which ca n drive 20 mA (@V OL = 1. 5 V) when a low level si gnal is out put. Any of these ports can become an in put port immediately after a reset. They can also be used as [...]

Rev. 1.0, 0 7/01, page 1 12 of 372 9.1.1 Port M ode Register 1(PMR1) PMR1 s witches the functions of pins i n port 1 and port 2. Bit B it Name Initial V alue R/W Description 7 IRQ3 0 R/W P17/ IRQ3 /TRGV Pin Function Swit ch This bit se lects wh ether pin P17/ IRQ 3 /TR GV i s us ed as P17 or as IRQ3 /TRGV. 0: P17 I/O port 1: IRQ3 /TRGV input p in 6[...]

Rev. 1.0, 0 7/01, page 1 13 of 372 9.1.2 Port Control Register 1(PCR1) PCR1 select s inputs/output s in bit units for pins to be used as general I/O ports of port 1. Bit B it Name Initial V alue R/W Description 7 6 5 4 3 2 1 0 PCR17 PCR16 PCR15 PCR14 − PCR12 PCR11 PCR10 0 0 0 0 − 0 0 0 W W W W − W W W When the corre sponding p in is designa t[...]

Rev. 1.0, 0 7/01, page 1 14 of 372 9.1.4 Port Pull-Up Control Register 1(PUCR1) PUCR1 cont rols the pull- up MOS in bit units of the pins set as the input p orts. Bit B it Name Initial V alue R/W Description 7 6 5 4 3 2 1 0 PUCR17 PUCR16 PUCR15 PUCR14 − PUCR12 PUCR11 PUCR10 0 0 0 0 1 0 0 0 R/W R/W R/W R/W − R/W R/W R/W Only bits for which PCR1 [...]

Rev. 1.0, 0 7/01, page 1 15 of 372 P15/ IRQ1 pin Register PMR1 PCR1 Bit Name IRQ1 PCR15 Pin Function Setting value 0 0 P15 input pin 0 1 P15 output pin 1X IRQ1 input pin Legend X: Don't care. P14/ IRQ0 pin Register PMR1 PCR1 Bit Name IRQ0 PCR14 Pin Function Setting value 0 0 P14 input pin 0 1 P14 output pin 1X IRQ0 input pin Legend X: Don&apos[...]

Rev. 1.0, 0 7/01, page 1 16 of 372 P10/TMOW pin Register PMR1 PCR1 Bit Name TMOW PCR10 Pin Function Setting value 0 0 P10 input pin 0 1 P10 output pin 1 X TMOW output pin Legend X: Don't care. 9.2 Port 2 Port 2 is a general I/O port also functioning as a SCI3 I/O pin . Each pin of the p ort 2 is shown in figure 9-2. T he register s ettings of [...]

Rev. 1.0, 0 7/01, page 1 17 of 372 Bit B it Name Initial V alue R/W Description 7 6 5 4 3 − − − − − − − − − − − − − − − Reserve d 2 1 0 PCR22 PCR21 PCR20 0 0 0 W W W When each of the port 2 pi ns P22 to P20 f unctions as a n general I/O p ort, setting a PCR2 bit to 1 m akes the correspondin g pin an ou tput port, whil [...]

Rev. 1.0, 0 7/01, page 1 18 of 372 P21/RXD pin Register SCR3 PCR2 Bit Name RE PCR21 Pin Function Setting Value 0 0 P21 input pin 0 1 P21 output pin 1 X RXD input pin Legend X:Don't care. P20/SCK3 pin Register SCR3 SMR PCR2 Bit Name CKE1 CKE0 COM PCR20 Pin Function Setting Value 0 0 0 0 P20 input pin 0 0 0 1 P20 output pin 0 0 1 X SCK3 output p[...]

Rev. 1.0, 0 7/01, page 1 19 of 372 Port 5 has the following registers. For details on re gister addresses and register states during each process, refer to s ection 19, Internal I/O Regist er. • Port mode re gister 5(PMR5) • Port control register 5(PCR5) • Port data regi ster 5(PDR5) • Port pull-up control regis ter 5(PUC R5) 9.3.1 Port M o[...]

Rev. 1.0, 0 7/01, page 1 20 of 372 Bit B it Name Initial Value R/W Description 0 WKP0 0 R/W P50/ WKP0 Pin F unction Sw itch Selects wh ether pin P50/ WKP0 is used as P50 or as WKP0 . 0: P50 I/O port 1: WKP0 input pi n 9.3.2 Port Control Register 5(PCR5) PCR5 select s inputs/output s in bit units for pins to be used as general I/O ports of po rt 5. [...]

Rev. 1.0, 0 7/01, page 1 21 of 372 9.3.4 Port Pull-up Control Register 5(PUCR5) PUCR5 cont rols the pull- up MOS in bit units of the pins set as the input p orts. Bit Bit Name Initial Value R/W Description 7 6 − − 0 0 − − Reserve d These bits ar e always read as 0 and cannot be modifie d. 5 4 3 2 1 0 P55 P54 P53 P52 P51 P50 0 0 0 0 0 0 R/W [...]

Rev. 1.0, 0 7/01, page 1 22 of 372 P55/ WKP5 / ADTRG pin Register PMR5 PCR5 Bit Name WKP5 PCR55 Pin Function Setting Value 0 0 P55 input pin 0 1 P55 output pin 1X WKP5 / ADTRG input pin Legend X: Don't care. P54/ WKP4 pin Register PMR5 PCR5 Bit Name WKP4 PCR54 Pin Function Setting Value 0 0 P54 input pin 0 1 P54 output pin 1X WKP4 input pin Le[...]

Rev. 1.0, 0 7/01, page 1 23 of 372 P51/ WKP1 pin Register PMR5 PCR5 Bit Name WKP1 PCR51 Pin Function Setting Value 0 0 P51 input pin 0 1 P51 output pin 1X WKP1 input pin Legend X: Don't care. P50/ WKP0 pin Register PMR5 PCR5 Bit Name WKP0 PCR50 Pin Function Setting Value 0 0 P50 input pin 0 1 P50 output pin 1X WKP0 input pin Legend X: Don&apos[...]

Rev. 1.0, 0 7/01, page 1 24 of 372 9.4.1 Port Control Register 7(PCR7) PCR7 select s inputs/output s in bit units for pins to be used as general I/O ports of po rt 7. Bit Bit Name Initial Value R/W Description 7 −− − Reserve d 6 5 4 PCR76 PCR75 PCR74 0 0 0 W W W Setting a PCR7 bit to 1 ma kes the corre sponding pin an output port , while clea[...]

Rev. 1.0, 0 7/01, page 1 25 of 372 9.4.3 Pin Function s The corresponde nce between the regis ter specificati on and the port f unctions is s hown below. P76/TMOV p in Register TCSRV PCR7 Bit Name OS3 to OS0 PCR76 Pin Functi on Setting Value 0000 0 P76 input pin 1 P76 output pin Other than the above values X TMOV output pin Legend X:Don't care[...]

Rev. 1.0, 0 7/01, page 1 26 of 372 9.5 Port 8 Port 8 is a general I/O port also functioning as a Timer W I/ O pin. Each pin of t he port 8 is shown in figure 9-5 . The register s etting of the timer W has priorit y for functio ns of the pi ns P84/FTIOD, P83/FTIOC , P82/FTIOB, and P81/ FTIOA. P80/FTC I also functions as a t imer W input port that is[...]

Rev. 1.0, 0 7/01, page 1 27 of 372 9.5.2 Port Data Register 8(PDR8) PDR8 is a general I/O port data regi ster of port 8. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 P87 P86 P85 P84 P83 P82 P81 P80 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PDR8 stores o utput data for port 8 pins. PDR8 is read wh ile PCR8 bit s are set to 1, the[...]

Rev. 1.0, 0 7/01, page 1 28 of 372 P84/FTIOD pi n Register TIOR1 PCR8 Bit Name IOD2 IOD1 IOD0 PCR84 Pin Function Setting Value 0 0 0 0 P84 input/FTIOD inp ut pin 0 0 0 1 P84 output/FTIOD input p in 0 0 1 X FTIOD output pin 0 1 X X FTIOD output pin 1 X X 0 P84 input/FTIOD input p in 1 X X 1 P84 output/FTIOD input p in Legend X: Don't care. P83/[...]

Rev. 1.0, 0 7/01, page 1 29 of 372 P81/FTIOA pi n Register TIOR0 PCR8 Bit Name IOA2 IOA1 IOA0 PCR81 Pin Function Setting Value 0 0 0 0 P81 input/FTIOA inp ut pin 0 0 0 1 P81 output/FTIOA input p in 0 0 1 X FTIOA output pin 0 1 X X FTIOA output pin 1 X X 0 P81 input/FTIOA input p in 1 X X 1 P81 output/FTIOA input p in Legend X: Don't care. P80/[...]

Rev. 1.0, 0 7/01, page 1 30 of 372 9.6.1 Port Data Register B(PDRB) PDRB i s a general input-o nly port data register of port B. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 − − − − − − − − R R R R R R R R The input va lue of each pin is read by reading this register. However, if a port [...]

Rev. 1.0, 0 7/01, page 1 31 of 372 Section 10 Timer A Timer A is an 8-bit tim er with interv al timing and real-time clock tim e-b a se function s. Th e clo ck time-base function is available when a 32.768kHz crystal os cillator is connected. Figure 10-1 shows a block diag ram of timer A. 10.1 Features • Timer A can be used as an interval timer o[...]

Rev. 1.0, 0 7/01, page 1 32 of 372 ø W TMOW ø ø W /32 ø W /16 ø W /8 ø W /4 ø W /32 ø W /16 ø W /8 ø W /4 ø/8192, ø/4096, ø/2048, ø/512, ø/256, ø/128, ø/32, ø/8 ø W /128 ø W /4 1/4 PSW PSS TMA TCA IRRTA ÷ 8 * ÷ 64 * ÷ 128 * ÷ 256 * Legend TMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A overflow interrupt reque[...]

Rev. 1.0, 0 7/01, page 1 33 of 372 10.3.1 T imer Mode Register A(T MA) Bit Bit Name Initial Value R/W Description 7 6 5 TMA7 TMA6 TMA5 0 0 0 R/W R/W R/W Clock Output Select 7 to 5 These bits select the clock outp ut at the TMO W pin. 000: φ /32 001: φ /16 010: φ /8 011: φ /4 100: φ w /32 101: φ w /16 110: φ w /8 111: φ w /4 For detail s on [...]

Rev. 1.0, 0 7/01, page 1 34 of 372 10.3.2 Timer Counter A (TCA) TCA is an 8-bit readable up-co unter, which is incremented by internal clock input. The clock source for input t o this counter is selected by bi ts TMA3 to TMA0 in TMA. TCA values can be read by the CP U in active mode, but ca nnot be read i n subactive mode. W hen TCA overflows, t he[...]

Rev. 1.0, 0 7/01, page 1 35 of 372 10.5 Usage Note When the clock time base function is selected as the internal clock of TCA in active mode or sleep mode, the internal clock is not synchronous with the system cl ock, so it i s synchronized b y a synchronizin g circuit. This may result in a maxi mum error of 1/ø (s) in the c ount cycle.[...]

Rev. 1.0, 0 7/01, page 1 36 of 372[...]

Rev. 1.0, 0 7/01, page 1 37 of 372 Section 11 Timer V Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external e vents. Compare- match signals with two regist ers can also be used t o reset the count er, request an inter rupt, or output a pulse si gnal with an arbitrary duty c ycle. Counting can be initiated by a trigger input a[...]

Rev. 1.0, 0 7/01, page 1 38 of 372 TRGV TMCIV TMRIV TMO V ø T rigger control Clock select Clear control Output control PSS TCR V1 TCORB Comparator TCNTV Comparator TCORA TCR V0 Interrupt request control TCSR V CMIA CMIB OV I Internal data bus Legend : TCORA: Time constant register A TCORB: Time constant register B TCNTV : Timer counter V TCSR V : [...]

Rev. 1.0, 0 7/01, page 1 39 of 372 11.3 Register Descrip tion s Time V has the followi ng registers. F or details on register addres ses and register s tates during each process, refer to section 19, I nternal I/O Registers. • Timer counter V(TC NTV) • Timer constant register A(TCORA) • Timer constant register B(TC ORB) • Timer contr ol reg[...]

Rev. 1.0, 0 7/01, page 1 40 of 372 11.3.3 Timer Control Register V0(TCRV0) TCRV0 selects the input clock s ignals of TCNTV, specifies the clearing conditions of TCNTV, and controls each interr upt request. Bit Bit Name Initial Value R/W Description 7 CMIEB 0 R/W Compare Match Interrupt Enab le B When this bit is set to 1, interrupt reque st from th[...]

Rev. 1.0, 0 7/01, page 1 41 of 372 Table 11- 2 C lo ck signals to input to TCNTV a nd the counting co nditions TCRV0 TCRV1 Bit 2 Bit 1 Bit 0 Bit 0 CKS2 CKS1 CKS0 IC KS0 Description 000 − C lock input d isabled 1 0 Internal clock: co unts on φ /4, falling edge 1 Internal clock: counts on φ /8, fall ing edge 1 0 0 Internal clo ck: counts on φ /1[...]

Rev. 1.0, 0 7/01, page 1 42 of 372 11.3.4 Timer Control/Status Register V(TCSRV) TCSRV indicates the status fl ag and controls output s by using a c ompare match. Bit Bit Name Initial Value R/W Description 7 CMFB 0 R/W Compare Match Fla g B Setting condi tion: When the TCNT V value mat ches the TC ORB value Clearing c ondition: After reading C MFB=[...]

Rev. 1.0, 0 7/01, page 1 43 of 372 OS3 and OS2 sel ect the output level for compare match B. OS1 and OS0 sel ect the output l evel for compare matc h A. The two output levels can be cont rolled inde pendently. Aft er a reset, the timer outpu t is 0 until the first compare match. 11.3.5 Timer Control Register V1(TCRV1) TCRV1 is an 8-bit read/write r[...]

Rev. 1.0, 0 7/01, page 1 44 of 372 11.4 Operation 11.4.1 Timer V operation 1. According to ta ble 11-2, six i nternal/external cl ock signals output by pres caler S can be selected as the timer V operating clock signals. When the operating clock signal is selected, TCNTV starts counting-up. Figu re 11-2 shows t he count timin g with an inte rnal cl[...]

Rev. 1.0, 0 7/01, page 1 45 of 372 N – 1 N + 1 N ø TMCIV (External clock input pin) TCNTV input clock TCNTV Figure 11-3 Increment Timing with External Clock H'FF H'00 ø TCNTV Overflo w signal OV F Figure 11-4 OVF S et Timing N N N+1 ø TCNTV TCORA or TCORB Compare match signal CMF A or CMFB Figure 11-5 CMFA and CMFB Set Timing[...]

Rev. 1.0, 0 7/01, page 1 46 of 372 ø Compare match A signal Timer V output pin Figure 11-6 T MOV Output T iming N H'00 ø Compare match A signal TCNTV Figure 11-7 Clear Timing by Compare M atch N – 1 N H'00 ø Compare match A signal Timer V output pin TCNTV Figure 11-8 Clear Timing by TMRIV Input 11.5 Timer V application examples 11.5.[...]

Rev. 1.0, 0 7/01, page 1 47 of 372 4. With these sett in gs, a waveform is output with ou t furth er software intervention, with a period determined by TC ORA and a pulse widt h determined by TC ORB. Counter cleared TCNTV H'FF TCORA TCORB H'00 TMOV Figure 11-9 Pu lse Output E xample 11.5.2 Pulse Ou tput with Arbitrary Puls e Width and Del[...]

Rev. 1.0, 0 7/01, page 1 48 of 372 Counter cleared TCNTV H'FF TCORA TCORB H'00 TRGV TMOV Compare match A Compare match B clears TCNTV and halts count-up Compare match B clears TCNTV and halts count-up Compare match A Figure 11-10 Ex ample of Pulse Output Sy nchronized to TRGV In put 11.6 Usage Notes The following t ypes of contenti on or [...]

Rev. 1.0, 0 7/01, page 1 49 of 372 ø Address TCNTV address TCNTV write cycle by CPU Internal wr ite signal Counter clear signal TCNTV N H'00 T 1 T 2 T 3 Figure 11-11 Contention between TCNTV Write and Clear ø Address TCORA address Internal wr ite signal TCNTV TCORA N N N+1 M TCORA write data Inhibited T 1 T 2 T 3 TCORA write cycle by CPU Com[...]

Rev. 1.0, 0 7/01, page 1 50 of 372 Clock before switching Clock after switching Count clock TCNTV N N+1 N+2 Write to CKS1 and CKS0 Figure 11-13 I nternal Clock Sw itching and T CNTV Operation[...]

Rev. 1.0, 0 7/01, page 1 51 of 372 Section 12 Timer W Timer W has a 16-bit timer havin g output compare a nd input captu re functions. Ti mer W can count external events and out put pulses with an arbitrary duty c y cle by compare match between the timer counter an d four general registers. Thus, it can b e applied to various sy stem s. 12.1 Featur[...]

Rev. 1.0, 0 7/01, page 1 52 of 372 Table 12-1 Timer W Functions Input/Output Pins Item Counter FTIOA FTIOB FTIOC FTIOD Count clock Internal clo cks: φ , φ /2, φ /4, φ /8 External clo ck: FTCI General regi sters (output comp are/input capture re gisters) Period specified in GRA GRA GRB GRC (bu ffe r register for GRA in buffer mode) GRD (buffer r[...]

Rev. 1.0, 0 7/01, page 1 53 of 372 Internal clock: External clock: FTCI FTIOA FTIOB FTIOC FTIOD IRRTW Control logic Clock selector Comparator TCNT Internal data bus Bus interface Legend : TMRW: Timer mode register W (8 bits) TCRW: Timer control register W (8 bits) TIERW: Timer interrupt enable register W (8 bits) TSRW: Timer status register W (8 bi[...]

Rev. 1.0, 0 7/01, page 1 54 of 372 12.3 Register Descrip tion s Timer W has the fol lowing regist ers. For details on register addres ses and regi ster states during each process, refer to section 19, I nternal I/O Registers. • Timer mode regi ster W(TMRW ) • Timer c ontro l reg i ste r W(TCRW) • Timer interrupt enable regist er W(TIERW) • [...]

Rev. 1.0, 0 7/01, page 1 55 of 372 Bit Bit Name Initial Value R/W Description 7 CTS 0 R/W Counter Start The counter o peration is halted wh en this bit is 0; while it can be perform ed when t his bit is 1. 6 − 1 − Reserve d This bit is always read as 1 and cann ot be modif ied. 5 BUFEB 0 R/W Buffer Operation B Selects t he GRD functi on. 0: GRD[...]

Rev. 1.0, 0 7/01, page 1 56 of 372 12.3.2 Timer Control Register W(TCRW) TCRW selects the timer counter cloc k source, selects a clearing con dition, and specifies the timer initial outpu t levels. Bit Bit Name Initial Value R/W Description 7 CCLR 0 R/W Counter Clear The TCNT val ue is clear ed by com pare match A w hen this bit is 1. Whe n it is 0[...]

Rev. 1.0, 0 7/01, page 1 57 of 372 12.3.3 Timer In terrupt Enabl e Register W(TIERW ) TIERW controls the timer W in terru pt request. Bit Bit Name Initial Value R/W Description 7 OVIE 0 R/W Timer Overflow Int errupt Enable When this bit is set to 1, FOVI interrupt re quested by O VF flag in TSRW is enable d. 6 5 4 − − − 1 1 1 − − − Rese[...]

Rev. 1.0, 0 7/01, page 1 58 of 372 Bit Bit Name Initial Value R/W Description 3 IMFD 0 R/W Input Capture/Compare M atch Flag D [Setting cond itions] • TCNT=G RD when GRD functions a s an output compare regi ster • The TCNT value is tra nsferred to G RD by an inp ut capture signal when G RD functions as an inp ut capture register [Clearing cond [...]

Rev. 1.0, 0 7/01, page 1 59 of 372 12.3.5 Timer I/O Con trol Register 0(TIOR0) TIOR0 selects the functions of GRA and GRB , and specifies the functi ons of the FTIOA and FTIOB pins . Bit Bit Name Initial Value R/W Description 7 − 1 − Reserve d This bit is always read as 1 and cann ot be modif ied. 6 IOB2 0 R/W I/O Control B2 Selects the G RB fu[...]

Rev. 1.0, 0 7/01, page 1 60 of 372 12.3.6 Timer I/O Con trol Register 1(TIOR1) TIOR1 select s the functions of GR C and GRD, and specifies the functions of the FTIOC and FTIOD pins. Bit Bit Name Initial Value R/W Description 7 − 1 − Reserve d This bit is always read as 1 and canno t be modif ied. 6 IOD2 0 R/W I/O Control D2 Selects t he GRD fun[...]

Rev. 1.0, 0 7/01, page 1 61 of 372 12.3.7 Timer Counter (TCNT) TCNT is a 16-bit readable/writable up-counter. T he clock source is selected by bits CKS2 to CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA b y setting the CCLR of TCRW to 1. When TCNT overflows (changes from H'FFFF to H'0000), t he OVF flag [...]

Rev. 1.0, 0 7/01, page 1 62 of 372 12.4 Operation • Normal Operation • PWM Operation 12.4.1 Normal Operation TCNT performs free -running or periodic counti ng operati ons. After a reset , TCNT is set as a free- running count er. When the CS T bit in TMRW is set to 1, TCNT start s incrementing the count . When the count overflows from H'FFF[...]

Rev. 1.0, 0 7/01, page 1 63 of 372 TCNT value GRA H'0000 CST bit IMFA Time Flag cleared by software Figure 12-3 Periodic Counter Operation By setting a general register as an output compa re register, compare match A, B, C, or D can cause the outp ut at the FTIOA, FTIOB, F TIOC, or FTIOD pin to output 0, output 1, or t oggle. Figure 12-4 s how[...]

Rev. 1.0, 0 7/01, page 1 64 of 372 TCNT value H'FFFF H'0000 FTIOA FTIOB Time GRA GRB Toggle output Toggle output Figure 12-5 T oggle Output E xample (TOA = 0, T OB = 1) Figure 12-6 s hows another exa mple of toggle output when TCNT ope rates as a periodic count er, cleared by compare match A. Toggle output is se lected for bot h compare m[...]

Rev. 1.0, 0 7/01, page 1 65 of 372 TCNT value H'FFFF H'1000 H'0000 FTIOA GRA Time H'AA55 H'55AA H'F000 H'1000 H'F000 H'55AA GRB H'AA55 FTIOB Figure 12-7 Input Capt ure O pera ting Example Figure 12-8 s hows an example o f buffer operatio n when the GRA is set as an input -capture register and GRC is[...]

Rev. 1.0, 0 7/01, page 1 66 of 372 12.4.2 PWM Operation In PWM mode, PW M waveforms are generated by using GRA as the period regist er and GRB, GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB , FTIOC, and FTIOD pins. Up to t hree-phase PW M waveforms can be output . In PWM mode, a general regist er functions as an output com[...]

Rev. 1.0, 0 7/01, page 1 67 of 372 TCNT value GRA GRB GRC H'0000 FTIOB FTIOC FTIOD Time GRD Counter cleared by compare match A Figure 12-10 PWM Mode Example (2) Figure 12-11 s hows an example of buffer ope ration when the F TIOB pin is se t to PWM mode and GRD is set as the buffer register for GRB. TCNT is cleared by com pare match A, and FTIO[...]

Rev. 1.0, 0 7/01, page 1 68 of 372 TCNT value GRA H'0000 FTIOB Time GRB Duty 0% Write to GRB Write to GRB TCNT value GRA H'0000 FTIOB Time GRB Duty 100% Write to GRB Write to GRB Output does not change when cycle register and duty register compare matches occur simultaneously. TCNT value GRA H'0000 FTIOB Time GRB Duty 100% Write to G[...]

Rev. 1.0, 0 7/01, page 1 69 of 372 TCNT value GRA H'0000 FTIOB Time GRB Duty 100% Write to GRB TCNT value GRA H'0000 FTIOB Time GRB Duty 0% Write to GRB Write to GRB Output does not change when cycle register and duty register compare matches occur simultaneously. TCNT value GRA H'0000 FTIOB Time GRB Duty 0% Write to GRB Write to GRB[...]

Rev. 1.0, 0 7/01, page 1 70 of 372 12.5 Operation Timing 12.5.1 TCNT Co unt Timing Figure 12-14 s hows the TCNT count timing when the i n ternal clock source is selected. Figure 12- 15 shows the timing when the external cloc k source is selected. The pulse width of the external clock signal mus t be at least tw o system clock ( φ ) c ycles; shorte[...]

Rev. 1.0, 0 7/01, page 1 71 of 372 Figure 12- 16 shows the out put compare t iming. GRA to GRD TCNT TCNT input clock φ N N N+1 Compare match signal FTIOA to FTIOD Figure 12-16 O utput Compare Output Timing 12.5.3 Input Capture Timing Input capture on the rising edge, falling ed ge, or both edges can be se lected through settings in TIOR0 and TIOR1[...]

Rev. 1.0, 0 7/01, page 1 72 of 372 12.5.4 Timing of Co unter Clearing by Co mpare Match Figure 12-18 shows the timing when the counter is cleared by compare match A. When the GRA value is N, the counter counts from 0 to N, and its cycle is N + 1. TCNT Compare match signal φ GRA N N H'0000 Figure 12-18 Timing of Counter Clea ring by Compare Ma[...]

Rev. 1.0, 0 7/01, page 1 73 of 372 GRA, GRB TCNT Input capture signal φ GRC, GRD N M M N+1 N N N+1 Figure 12-20 Buf f er Operation Timing (Input Ca pture) 12.5.6 Timing of I MFA to IMFD Flag S etting at Compare Match If a general regis ter (GRA, GRB , GRC, or GRD) is us ed as an output compare register, the corresponding IMFA, IMFB, IMF C, or IMFD[...]

Rev. 1.0, 0 7/01, page 1 74 of 372 12.5.7 Timing of IMFA t o IMFD Setting at Input Capture If a general regis ter (GRA, GRB , GRC, or GRD) is us ed as an input capture regi ster, the corresponding IMFA, IMFB, IMFC, or IMF D flag is set to 1 when an input capture occurs. Figure 12-22 sh o ws the timing of th e IMFA to IMFD flag setting at inpu t cap[...]

Rev. 1.0, 0 7/01, page 1 75 of 372 12.6 Usage Notes The following t ypes of contenti on or operat ion can occur in t imer W operati on. 1. The pulse width o f the input cl ock signal and the input capture sig nal must be at least two system clock ( φ ) cycles; shor ter pu lses will not be de tected correctly. 2. Writing to registers is performed i[...]

Rev. 1.0, 0 7/01, page 1 76 of 372 TCNT Previous clock N N+1 N+2 N+3 New clock Count clock The change in signal level at clock switching is assumed to be a rising edge, and TCNT increments the count. Figure 12-25 I nternal Clock Sw itching and T CNT Operation[...]

Rev. 1.0, 0 7/01, page 1 77 of 372 Section 13 Watchdog Timer The watchdog timer(WDT) is an 8 - bit tim er th at can generate an internal reset signal for this LSI if a system crash prev ents the CPU fro m writing to the timer counter, thus allowing it to overflow. The block diagram of the WDT i s shown in figure 13 -1. ø Internal reset signal PSS [...]

Rev. 1.0, 0 7/01, page 1 78 of 372 13.2.1 Timer Control/Status Register WD(TCSRWD) TCSRWD is a register that indi cates TCSRWD and TCW D write control, wat chdog timer operation c ontrol, and t he operati on status. Bit Bit Name Initial Value R/W Description 7 B6WI 1 R Bit 6 Write Inhi bit The TCWE bit can be wri tten only whe n the write value of [...]

Rev. 1.0, 0 7/01, page 1 79 of 372 Bit Bit Name Initial Value R/W Description 0 WRST 0 R/W Watchdog Timer Reset [Setting cond ition] When TCWD ov erflows an d an interna l reset signal is generated [Clearing cond iti on] • Reset by RES pi n • When 0 is writte n to the WR ST bit while writ ing 0 to the B0WI bit when the TCSRWE bit=1 13.2.2 Timer[...]

Rev. 1.0, 0 7/01, page 1 80 of 372 13.3 Operation The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 to B2WI when TCS RWE in TCSRWD is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write accesses to TCSRWD is required.) When a clock pulse is input after the TCWD count value has rea[...]

Rev. 1.0, 0 7/01, page 1 81 of 372 Section 14 Serial Communication Interface3 (SC I3) Serial Communication Inter face (SCI) can handle both asynchronous a nd clocked synchronous serial communicat ion. In async hronous mode, s erial data c ommunication can be carried out us ing standard asynch ronous communicat ion chips s uch as a Universal Asynch [...]

Rev. 1.0, 0 7/01, page 1 82 of 372 Clock TXD RXD SCK 3 BRR SMR SCR3 SSR TDR RDR TSR RSR Transmit/receive control circuit Internal data bus Legend RSR: RDR: TSR: TDR: SMR: SCR3: SSR: BRR: BRC: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register 3 Serial status regis[...]

Rev. 1.0, 0 7/01, page 1 83 of 372 14.2 Input/Output Pins Table 14-1 s hows the SCI pi n configurati on. Table 14- 1 P in Co nfigurat io n Pin Name Abbrev. I/O Function SCI clock SCK3 I/O SCI clock input/output SCI receive data input RXD Input SCI receive dat a input SCI transmit dat a output TXD Output SCI transmit dat a output 14.3 Register Descr[...]

Rev. 1.0, 0 7/01, page 1 84 of 372 14.3.1 Receive Shift Register (RSR) RSR is a shift register that is us ed to receive serial data input from the RxD pin a nd convert it into parallel data. When one frame of data has been received, it is transferred to R DR automatically. RSR cannot be directly acces sed by the CPU. 14.3.2 Receive Data Register (R[...]

Rev. 1.0, 0 7/01, page 1 85 of 372 14.3.5 Serial Mode Regis ter (SMR) SMR is used to set the SCI’s serial transfer format and select the baud rate ge nerator clock source. Bit Bit Name Initial Value R/W Description 7 COM 0 R/W Communication Mod e 0: Asynchron ous mode 1: Clocke d synchronou s mode 6 CHR 0 R/W Character Le ngth (enabl ed only in a[...]

Rev. 1.0, 0 7/01, page 1 86 of 372 Bit Bit Name Initial Value R/W Description 1 0 CKS1 CKS0 0 0 R/W R/W Clock Sel ect 0 and 1 These bits select the clock so urce for the b aud rate generator. 00: ø clock (n = 0) 01: ø/4 cloc k (n = 1) 10: ø/16 clo ck (n = 2) 11: ø/64 clo ck (n = 3) For the relatio nship betwee n the bit rate reg ister setting a[...]

Rev. 1.0, 0 7/01, page 1 87 of 372 Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiproce ssor Interrupt E nable (enab led only when the M P bit in SMR i s 1 in asyn chronous mode) When thi s bit is set to 1, receive data in whic h the multiproce ssor bit is 0 is ski pped, and setti ng of the RDRF, FER, and OER st atus flags in SSR is d[...]

Rev. 1.0, 0 7/01, page 1 88 of 372 14.3.7 Serial Status Regi ster (SSR) SSR is a register containing status flags of the SCI and multiprocesso r b its for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PE R, and FER; they can only be cleared. Bit Bit Name Initial Value R/W Description 7 TDRE 1 R/W Transmit Data Register Empt y Indicates w [...]

Rev. 1.0, 0 7/01, page 1 89 of 372 Bit Bit Name Initial Value R/W Description 4 FER 0 R/W Framing Error [Setting cond ition] • When a fram ing error oc curs in rec eption [Clearing cond iti on] • When 0 i s written to FER after reading FER = 1 3 PER 0 R/W Parity Error [Setting cond ition] • When a parity error is detected dur ing reception [C[...]

Rev. 1.0, 0 7/01, page 1 90 of 372 14.3.8 Bit Rate Register (BRR) BRR is an 8- b it register th at adjusts the b it r ate. The initial va lu e of BRR is H'FF. T a b le 13-2 shows the r e latio nship b e tween the N setting in BRR an d the n setting in bits CKS1 an d CKS0 of SMR in asynchronous mode. Table 13-3 shows the maximum bit rate f or e[...]

Rev. 1.0, 0 7/01, page 1 91 of 372 Table 14- 2 Ex a mples of BRR Setting s for Va rious Bit Rate s ( Asynchronous Mode) (1 ) Operating Frequenc y ø (MHz) 2 2.097152 2.457 6 3 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.1[...]

Rev. 1.0, 0 7/01, page 1 92 of 372 Table 14- 2 Ex a mples of BRR Setting s for Va rious Bit Rate s ( Asynchronous Mode) (2 ) Operating Frequenc y ø (MHz) 6 6.144 7.3728 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 2 106 –0.44 2 108 0.08 2 130 –0.07 150 2 77 0.16 2 79 0.00 2 95 0.00 300 1 155 0.16 1 159 0.00 1 191 0.00 600 1 7[...]

Rev. 1.0, 0 7/01, page 1 93 of 372 Table 14- 2 Ex a mples of BRR Setting s for Va rious Bit Rate s ( Asynchronous Mode) (3 ) Operating Frequenc y ø (MHz) 12.288 14 14.7456 16 Bit Rate (bit/s) nN Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 217 0.08 2 248 –0.17 3 64 0.70 3 70 0.03 150 2 159 0.00 2 181 0.16 2 191 0.00 2 207 0.16 300 2[...]

Rev. 1.0, 0 7/01, page 1 94 of 372 Table 14- 4 BRR Set t ing s for Vario us Bit Rates (Clo cked Sy nchrono us Mode) Operating Frequenc y ø (MHz) 2 4 8 10 16 Bit Rate (bit/s) nN nN nN n N n N 1 1 0 3 7 0 — —— —— — 250 2 124 2 249 3 124 — — 3 249 500 1 249 2 124 2 249 — — 3 124 1k 1 124 1 249 2 124 — — 2 249 2.5k 0 199 1 99 1[...]

Rev. 1.0, 0 7/01, page 1 95 of 372 14.4 Operation in Asynchronous Mode Figure 14-2 s hows the general f ormat for async hronous seri al communication. One character (or frame) consists of a start b it (lo w level), followed by d ata (in LSB-first order), a parity bit (h igh or low level), and finally stop bits (high level). Inside the SCI, the tran[...]

Rev. 1.0, 0 7/01, page 1 96 of 372 14.4.2 SCI Initialization Before transmitting and receivin g data, you sh ould first clear th e TE and RE bits in SCR3 to 0 , then initialize the SCI as de scrib ed b elow. When the operating mode, or transfer format, is changed for e xample, the TE and R E bits must be cleared t o 0 before making the cha nge usin[...]

Rev. 1.0, 0 7/01, page 1 97 of 372 14.4.3 Data Trans mission Figure 14-5 s hows an example o f operation for tra n smission in asynchr onous mode. In transmiss ion, the SCI operates as described below. 1. The SCI monitors t he TDRE flag in SSR . If the flag is cleared t o 0, the S CI recognizes that data has been written to TDR, and transfers the d[...]

Rev. 1.0, 0 7/01, page 1 98 of 372 No Yes Start transmission Read TDRE flag in SSR [1] Write transmit data to TDR Yes No No Yes Read TEND flag in SSR [2] No Yes [3] Clear PDR to 0 and set PCR to 1 Clear TE bit in SCR3 to 0 TDRE = 1 All data transmitted? TEND = 1 Break output? [1] Read SSR and check that the TDRE flag is set to 1, then write transmi[...]

Rev. 1.0, 0 7/01, page 1 99 of 372 14.4.4 Serial Data Reception Figure 14-7 s hows an example o f operation for rece ption in as ynchronous mode. In serial reception, the SCI operates as described bel ow. 1. The SCI mon ito rs the communication line. If a start bit is d e tected , th e SCI performs internal synchronization, receives receive data in[...]

Rev. 1.0, 0 7/01, page 2 00 of 372 Table 14-5 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF * OER FER PER Receive Data Receive Error Type 1 1 0 0 Lost Overrun error 0 0 1 0 Transferred to RDR Framing error 0 0 0 1 Transferred to RDR Parity error 1 1 1 0 Lost Overrun error + framing error 1 1 0 1 Lost Overrun error + parity error 0[...]

Rev. 1.0, 0 7/01, page 2 01 of 372 Yes No Start reception [1] No Yes Read receive data in SSR [3] Clear RE bit in SCR3 to 0 Read OER, PER, and FER flags in SSR Error processing [4] Read receive data in RDR Yes No OER+PER+FER = 1 RDRF = 1 All data received? [1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs,[...]

Rev. 1.0, 0 7/01, page 2 02 of 372 (A) Start receive error processing Parity error processing Yes No Clear OER, PER, and FER flags in SSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing OER = 1 FER = 1 Break? PER = 1 Clear RE bit in SCR3 to 0 (Continued to previous page) [4] <End> Figure 14-8 Sample Serial Receptio[...]

Rev. 1.0, 0 7/01, page 2 03 of 372 14.5 Operation in Clocked Synchronous Mode Figure 14-9 s hows the general f ormat for clocke d synchron ous communication . In clocked synchronou s mode, data is tran smitted or received synchronous with clock pulses. A sing le character in the transmit data con sists of the 8-bit data starting from the LSB. In cl[...]

Rev. 1.0, 0 7/01, page 2 04 of 372 14.5.3 Serial Data Tran smission Figure 14- 10 shows an example of SCI ope ration for trans mission i n clocked sync hronous mode. In serial trans mission, the S CI operates as des cribed below. 1. T h e SC I m o n it o r s t h e T D RE f la g in SS R, a n d i f th e f l ag i s 0 , th e SC I recognizes th a t d a [...]

Rev. 1.0, 0 7/01, page 2 05 of 372 No Yes Start transmission Read TDRE flag in SSR [1] Write transmit data to TDR No Yes No Yes Read TEND flag in SSR [2] Clear TE bit in SCR3 to 0 TDRE = 1 All data transmitted? TEND = 1 [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. When data is [...]

Rev. 1.0, 0 7/01, page 2 06 of 372 14.5.4 Serial Data Reception (Clocked Synchronous Mode) Figure 14-12 s hows an example of SCI operati on for recepti on in clocked sy nchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs intern al in itialization synchro nous with a synchro nization clock inp ut or output, [...]

Rev. 1.0, 0 7/01, page 2 07 of 372 Yes No Start reception [1] [4] No Yes Read RDRF flag in SSR [2] [3] Clear RE bit in SCR3 to 0 Error processing (Continued below) Read receive data in RDR Yes No OER = 1 RDRF = 1 All data received? Read OER flag in SSR Start overrun error processing Overrun error processing Clear OER flag in SSR to 0 [4] [1] Read t[...]

Rev. 1.0, 0 7/01, page 2 08 of 372 14.5.5 Simultaneous Serial Data Transmission an d Reception Figure 14-14 shows a sample flowchart f or simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous s erial data transmit and receive operations. To switch from transmit mode t o simultaneous transmit an[...]

Rev. 1.0, 0 7/01, page 2 09 of 372 Yes No Start transmission/reception [3] Error processing [4] Read receive data in RDR Yes No OER = 1 All data received? [1] Read TDRE flag in SSR No Yes TDRE = 1 Write transmit data to TDR No Yes RDRF = 1 Read ORER flag in SSR Read RDRF flag in SSR Clear TE and RE bits in SCR to 0 [1] Read SSR and check that the T[...]

Rev. 1.0, 0 7/01, page 2 10 of 372 14.6 Multiprocessor Communication Function Use of the multip rocessor co mmunication function enables d ata tran sfer between a number of processors s haring communicati on lines by asy nchronous se rial communication us ing the multiprocesso r format, in which a multipro cessor bit is added to the transfer data. [...]

Rev. 1.0, 0 7/01, page 2 11 of 372 Transmitting station Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial transmission line Serial data ID transmission cycle = receiving station specification Data transmission cycle = Data transmission to receiving station specified by ID [...]

Rev. 1.0, 0 7/01, page 2 12 of 372 14.6.1 Multip rocessor Serial Data T ransmiss ion Figure 14-16 sho ws a sample flowchart for multiprocesso r serial d a ta tran sm ission. For an ID transmission cy cle, set the MPBT bit in SSR to 1 before transmissio n. For a data transmissio n cycle, clear the MPBT bit in SSR to 0 before transmission. All other [...]

Rev. 1.0, 0 7/01, page 2 13 of 372 14.6.2 Multiprocessor Serial Data Reception Figure 14-17 sho ws a sample flowchart for multiprocesso r serial d a ta reception . If the MPIE bit in SCR3 is set to 1 , d ata is skipped until data with a 1 multipro cessor bit is sent. On receiving data with a 1 multiprocessor b it, th e receive data is tran sferred [...]

Rev. 1.0, 0 7/01, page 2 14 of 372 Yes No Start reception No Yes [4] Clear RE bit in SCR3 to 0 Error processing [5] Yes No FER+OER = 1 RDRF = 1 All data received? Read MPIE bit in SCR3 [1] [2] Read OER and FER flags in SSR Read RDRF flag in SSR [3] Read receive data in RDR No Yes [A] This station’s ID? Read OER and FER flags in SSR Yes No Read RD[...]

Rev. 1.0, 0 7/01, page 2 15 of 372 Start receive error processing Yes No Clear OER, and FER flags in SSR to 0 No Yes No Yes Framing error processing Overrun error processing OER = 1 FER = 1 Break? [5] [A] End Figure 14-17 Sample Multiprocessor Serial Reception Flowchart (2)[...]

Rev. 1.0, 0 7/01, page 2 16 of 372 1 frame Start bit Start bit Receive data (ID1) Receive data (Data1) MPB MPB Stop bit Stop bit Mark state (idle state) 1 frame 0 1D 0 D 1 D 7 1 1 1 1 0D 0 D 1 D 7 ID1 0 Serial data MPIE RDRF RDR value RDR value LSI operation RXI interrupt request MPIE cleared to 0 User processing RDRF flag cleared to 0 RXI interrup[...]

Rev. 1.0, 0 7/01, page 2 17 of 372 14.7 Interrupts SCI creates the following six interrupt requests: transmission end, transmit data empty , receive data full, and receive errors ( overrun error , framing error, a nd parity error) . Table 14-6 shows the interrupt sources. Table 14- 6 SCI I nterrupt Reque st s Interrupt Requests Abbrev. Interrupt So[...]

Rev. 1.0, 0 7/01, page 2 18 of 372 14.8 Usage Notes 14.8.1 Break Detection and Processing When framing erro r detection is performed, a break can be detect ed by reading the RxD pi n value directly. In a break, the input from the R xD pin becomes all 0s , setting the F ER flag, and poss ibly the PER flag. Note that as the SCI continues the receive [...]

Rev. 1.0, 0 7/01, page 2 19 of 372 14.8.4 Receive Data Sampling Timing and Reception Margin in A synchronou s Mode In asynchron ous mode, the SC I operates on a bas ic clock with a fre quency of 16 t imes the transfe r rate. In recept ion, the SCI s amples the falli ng edge of the s tart bit usi ng the basic clock, an d performs internal synchroniz[...]

Rev. 1.0, 0 7/01, page 2 20 of 372[...]

Rev. 1.0, 0 7/01, page 2 21 of 372 Section 15 I 2 C Bus Interface 2 (IIC2) The I 2 C bus interface conform s to and provides a subset of th e Philips I 2 C bus (inter-IC bus ) interface functions. The register con figuration that controls the I 2 C bus differs pa rtly from the Philips con f iguration , ho wever. Figure 15-1 s hows a block diag ram [...]

Rev. 1.0, 0 7/01, page 2 22 of 372 SCL ICCR1 Transfer clock generation circuit Address comparator Interrupt generator Interrupt request Bus state decision circuit Arbitration decision circuit Noise canceler Noise canceler Output control Output control Transmission/ reception control circuit ICCR2 ICMR ICSR ICEIR ICDRR ICDRS ICDRT I 2 C bus control [...]

Rev. 1.0, 0 7/01, page 2 23 of 372 Vcc Vcc SCL in out SCL SDA in out SDA SCL (Master) (Slave 1) (Slave 2) SDA SCL in out SCL SDA in out SDA SCL in out SCL SDA in out SDA Figure 15-2 External Circuit Connections of I/O Pins 15.2 Input/Output Pins Table 15-1 s ummarizes the input /output pi ns used by t he I 2 C bus inter face. Table 15-1 I 2 C Bus I[...]

Rev. 1.0, 0 7/01, page 2 24 of 372 • I 2 C bus receive data register (ICDRR) • I 2 C bus s hift register (ICDR S) 15.3.1 I 2 C Bus Control Register 1 (ICCR1) ICCR1 is an 8-bit readable/writable register that enables or disables the I 2 C bus interface, controls transmission or reception, and selects master or slave mode, tra nsmission or recept[...]

Rev. 1.0, 0 7/01, page 2 25 of 372 Table 15-2 Transfer Rate Bit 3 Bit 2 Bit 1 Bit 0 Transfer Rate CKS3 CKS2 CKS1 CKS0 Clock φ =5 MH z φ =8 MHz φ =10 MHz φ =16 MHz 0 φ /28 179 kH z 286 kHz 357 kH z 571 kHz 0 1 φ /40 125 kHz 200 kHz 250 kH z 400 kHz 0 φ /48 104 kH z 167 kHz 208 kH z 333 kHz 0 1 1 φ /64 78.1 kHz 125 kHz 156 kHz 250 kHz 0 φ /8[...]

Rev. 1.0, 0 7/01, page 2 26 of 372 Bit Bit Name Initial Value R/W Description 6 SCP 1 W Start/Stop Issue C ondition Disabl e The SCP bit contro ls the is sue of start/ stop condit ions in master mode. To issue a start condition, write 1 in BBSY an d 0 in SCP. A retransmit st art conditi on is issu ed in the same way. To issue a stop c ondition, wri[...]

Rev. 1.0, 0 7/01, page 2 27 of 372 15.3.3 I 2 C Bus Mode Register (ICMR) ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred first, perfor ms master mode wait co ntrol, and s elects the trans fer bit count. Bit Bit Name Initial Value R/W Description 7 MLS 0 R/W MSB-First/LSB-First Sele ct 0: MSB-first 1: L[...]

Rev. 1.0, 0 7/01, page 2 28 of 372 Bit Bit Name Initial Value R/W Description 2 1 0 BC2 BC1 BC0 0 0 0 R/W R/W R/W Bit Counter 2 to 0 These bits specify th e number of bits to be tr ansferred ne xt. When read, the remaining number of tran sfer bits i s indicat ed. With the I 2 C bus format, the data is transferred with one addit i on acknowledge bi [...]

Rev. 1.0, 0 7/01, page 2 29 of 372 Bit Bit Name Initial Value R/W Description 5 RIE 0 R/W Receive Interru pt Enable This bit ena bles or di sables the r eceive dat a full interr upt request (RXI) and t he overrun err or interrupt reque st (ERI) with the cloc ked synchron ous format, wh en a receive d ata is transferred from ICDRS to ICDRR and the R[...]

Rev. 1.0, 0 7/01, page 2 30 of 372 Bit Bit Name Initial Value R/W Description 0 ACKBT 0 R/W Transmit Acknowledge In receive m ode, this b it specifies the bit to b e sent at the acknowle dge tim ing . 0: 0 is sent at the ack nowledge tim ing. 1: 1 is sent at the ack nowledge tim ing. 15.3.5 I 2 C Bus Status Register (ICSR) ICSR is an 8-bit readable[...]

Rev. 1.0, 0 7/01, page 2 31 of 372 Bit Bit Name Initial Value R/W Description 5 RDRF 0 R/W Receive Data Register Full [Setting cond ition] • When a re ceive data is tran sferred from ICDRS to ICDRR [Clearing cond iti ons ] • When 0 i s written in RDRF after rea ding RDRF = 1 • When ICDRR is read wit h an instructio n 4 NACKF 0 R/W No Acknowle[...]

Rev. 1.0, 0 7/01, page 2 32 of 372 Bit Bit Name Initial Value R/W Description 1 AAS 0 R/W Slave Address Recogni tion Flag In slave re ceive mod e, this flag is set to 1 if the first frame following a start conditi on matches bi ts SVA6 to SVA0 in SAR. [Setting cond itions] • When the slave addre ss is detect ed in slav e receive mode • When the[...]

Rev. 1.0, 0 7/01, page 2 33 of 372 15.3.7 I 2 C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. W hen ICDRT detects the space in the shift register (ICDRS), it tran sfers th e transmit data which is written in ICDRT to ICDRS and starts transferring d ata. If the next transfer data is wr[...]

Rev. 1.0, 0 7/01, page 2 34 of 372 15.4 Operation The I 2 C bus interface can co mmunicate either in I 2 C bus mode or cl ocked sync hronous seri al mode by sett ing FS in S AR. 15.4.1 I 2 C Bus Format Figure 15-3 s hows the I 2 C bus formats. Figure 15 -4 shows the I 2 C bus timing. The first fra me following a start condition always consist s of [...]

Rev. 1.0, 0 7/01, page 2 35 of 372 P: Stop conditio n. The master device drives SDA fro m low to high while SCL is hig h . 15.4.2 Master T ransmit Operati on In master transmit m ode, the master device ou tputs th e tran smit clock and transmit d ata, and the slave device returns an acknowledge signal. For master transmit mo de operation timing, re[...]

Rev. 1.0, 0 7/01, page 2 36 of 372 TDRE SCL (Master output) SDA (Master output) SDA (Slave output) TEND [5] Write data to ICDRT (third byte) ICDRT ICDRS [2] Instruction of start condition issuance [3] Write data to ICDRT (first byte) [4] Write data to ICDRT (second byte) User processing 1 Bit 7 Slave address Address + R/ Data 1 Data 1 Data 2 Addres[...]

Rev. 1.0, 0 7/01, page 2 37 of 372 15.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from t h e slave device, and returns an ack nowledge signal. For master receive mode operation timing, refer t o figures 15-7 and 1 5-8. The reception proced ure and operations in master receive mo de[...]

Rev. 1.0, 0 7/01, page 2 38 of 372 TDRE TEND ICDRS ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) [3] Read ICDRR 1 A 21 34 56 78 9 9 A TRS RDRF SCL (Master output) SDA (Master output) SDA (Slave output) Bit 7 Master transmit mode Master receive mode Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 User processing Data 1[...]

Rev. 1.0, 0 7/01, page 2 39 of 372 15.4.4 Slave Tr ansmit Op eration In slave transmit mode, the slave device outp uts the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. For slave transmit mode operation timing , refer to figures 1 5-9 and 15-10 . The transmiss ion procedure and operations in s l[...]

Rev. 1.0, 0 7/01, page 2 40 of 372 TDRE TEND ICDRS ICDRR 1 A 21 34 56 78 9 9 A TRS ICDRT SCL (Master output) Slave receive mode Slave transmit mode SDA (Master output) SDA (Slave output) SCL (Slave output) Bit 7 Bit 7 Data 1 Data 1 Data 2 Data 3 Data 2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 [2] Write data to ICDRT (data 1) [2] Write data to ICDR[...]

Rev. 1.0, 0 7/01, page 2 41 of 372 TDRE Data n TEND ICDRS ICDRR 1 9 23456789 TRS ICDRT A SCL (Master output) SDA (Master output) SDA (Slave output) SCL (Slave output) Bit 7 Slave transmit mode Slave receive mode Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 [3] Clear TEND [5] Clear TDRE [4] Read ICDRR (dummy read) after clearing TRS User processing Fig[...]

Rev. 1.0, 0 7/01, page 2 42 of 372 4. The last byte dat a is read by rea ding ICDR R. ICDRS ICDRR 12 1 34 56 78 9 9 A A RDRF Data 1 Data 2 Data 1 SCL (Master output) SDA (Master output) SDA (Slave output) SCL (Slave output) Bit 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 [2] Read ICDRR (dummy read) [2] Read ICDRR User processing Figure 15-11 [...]

Rev. 1.0, 0 7/01, page 2 43 of 372 15.4.6 Clocked Syn chronous Serial Format This module can be operated with t h e clocked synchronous s erial format, by setting the FS bit in SAR to 1. Wh en the M ST bit in ICCR1 is 1, the tr ansfer c lock ou tpu t from SCL is sele c ted. Whe n MST is 0, the external clock input is selected. Data Transfer Format [...]

Rev. 1.0, 0 7/01, page 2 44 of 372 12 78 1 7 8 1 SCL TRS Bit 0 Data 1 Data 1 Data 2 Data 3 Data 2 Data 3 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 1 SDA (Output) TDRE ICDRT ICDRS User processing [3] Write data to ICDRT [3] Write data to ICDRT [3] Write data to ICDRT [3] Write data to ICDRT [2] Set TRS Figure 15-14 T ransmit Mod e Operation Timi ng Re[...]

Rev. 1.0, 0 7/01, page 2 45 of 372 12 78 1 7 81 2 SCL MST TRS RDRF ICDRS ICDRR SDA (Input) Bit 0 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 1 User processing Data 1 Data 1 Data 2 Data 2 Data 3 [2] Set MST (when outputting the clock) [3] Read ICDRR [3] Read ICDRR Figure 15-15 Receive Mode Operation Timing 15.4.7 Noise Cancel er The logic levels at the [...]

Rev. 1.0, 0 7/01, page 2 46 of 372 15.4.8 Example of Us e Flowcharts in respective modes that use the I 2 C bus interface are shown in figures 15-17 t o 15-20. BBSY=0 ? No TEND=1 ? No Yes Start [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] Initialize Set MST and TRS in ICCR1 to 1. Write 1 to BBSY and 0 to SCP. Write transmit data in [...]

Rev. 1.0, 0 7/01, page 2 47 of 372 No Yes RDRF=1 ? No Yes RDRF=1 ? Last receive - 1? Mater receive mode Clear TEND in ICSR Clear TRS in ICCR1 to 0 Clear TDRE in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR Read RDRF in ICSR Read ICDRR Set ACKBT in ICIER to 1 Set RCVD in ICCR1 to 1 Read ICDRR Read RDRF in ICSR Write 0 to BBSY and SCP Read STOP in[...]

Rev. 1.0, 0 7/01, page 2 48 of 372 TDRE=1 ? Yes Yes No Slave transmit mode Clear AAS in ICSR Write transmit data in ICDRT Read TDRE in ICSR Last byte? Write transmit data in ICDRT Read TEND in ICSR Clear TEND in ICSR Clear TRS in ICCR1 to 0 Dummy read ICDRR Clear TDRE in ICSR End [1] Clear the AAS flag. [2] Set transmit data for ICDRT (except for t[...]

Rev. 1.0, 0 7/01, page 2 49 of 372 No Yes RDRF=1 ? No Yes RDRF=1 ? Last receive - 1? Slave receive mode Clear AAS in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR Read RDRF in ICSR Read ICDRR Set ACKBT in ICIER to 1 Read ICDRR Read RDRF in ICSR Read ICDRR End No Yes [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [1] Clear the AAS flag. [2] Set acknowle[...]

Rev. 1.0, 0 7/01, page 2 50 of 372 15.5 Interrupt Requ est There are six interrupt requests in this mod ule; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration los t/overrun. Table 15 -3 shows the contents of each interrupt request. Table 15-3 Interrupt Req uests Interrupt Request Abbreviation Inte[...]

Rev. 1.0, 0 7/01, page 2 51 of 372 15.6 Bit Synchronous Circuit In master mode,th is m o dule has a possib ility that high lev e l p eriod may be short in th e two states described below. • When SCL is driven to low by t he slave device • When the rising speed of SC L is lowered by the load of the SCL line (loa d capacitance or pull- up resista[...]

Rev. 1.0, 0 7/01, page 2 52 of 372[...]

Rev. 1.0, 0 7/01, page 2 53 of 372 Section 16 A/D Converter This LSI include s a su ccessive approx imation type 1 0-bit A/D converter that allows u p to eight analog input chan nels to be select ed. The block di agram of the A/D con verter is shown in figure 16-1. 16.1 Features • 10-bit reso lution • Eight input c hannels • Conversi on time:[...]

Rev. 1.0, 0 7/01, page 2 54 of 372 Module data bus Control circuit Internal data bus 10-bit D/A Comparator + Sample-and- hold circuit ADI interrupt Bus interface Successive approximations register Analog multiplexer A D C S R A D C R A D D R D A D D R C A D D R B A D D R A AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Legend ADCR : ADCSR : ADDRA : ADDRB : ADDRC [...]

Rev. 1.0, 0 7/01, page 2 55 of 372 16.2 Input/Output Pins Table 16-1 summari zes the input pi ns used by t he A/D converter. T he 18 analog input pins are divided into two groups ; analog inpu t pins 0 t o 3 (AN0 to AN3) c omprising gro up 0, analo g input pins 4 to 7 (AN4 t o AN7) comprisi ng group 1. T he AVcc pin is the power s upply pins f or t[...]

Rev. 1.0, 0 7/01, page 2 56 of 372 16.3 Register Description The A/D converter has the following re gisters. F or details on re gister addresse s and regist er states during each processing, refe r to section 19, Internal I/O Registers. • A/D data register A (ADDRA) • A/D data register B (ADDRB) • A/D data register C (ADDRC) • A/D data regi[...]

Rev. 1.0, 0 7/01, page 2 57 of 372 16.3.2 A/D Control/Status Register (ADCSR) ADCSR consi sts of the contr ol bits and convers ion end s tatus bits of t he A/D converter. Bit Bit Name Initial Value R/W Description 7 ADF 0 R/W A/D End Flag [Setting cond itions] • When A/D conversio n ends in sin gle mode • When A/D conversio n ends once o n all [...]

Rev. 1.0, 0 7/01, page 2 58 of 372 Bit Bit Name Initial Value R/W Description 2 1 0 CH2 CH1 CH0 0 0 0 R/W R/W R/W Channel Sel ect 2 to 0 Select analo g input cha nnels. When SCAN = 0 When SCAN = 1 000: AN0 000: AN0 001: AN1 001: AN0 and AN1 010: AN2 010: AN0 to AN2 011: AN3 011: AN0 to AN3 100: AN4 100: AN4 101: AN5 101: AN4 and AN5 110: AN6 110: A[...]

Rev. 1.0, 0 7/01, page 2 59 of 372 16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes ; single mode an d scan mode. When cha nging the o perating mode or anal og input channel, in order to preven t incorrect operation, first clear th e bit ADST in ADCSR to 0. The ADST bit can be [...]

Rev. 1.0, 0 7/01, page 2 60 of 372 16.4.3 Input Sampling and A/D Conv ersion Time The A/D converter has a b uilt-in sample-and-hold circuit. Th e A/D converter samples the analog input when t he A/D conversion s tart delay time (t D ) has passed after th e ADST bit is set to 1, then starts convers ion. Figure 16 -2 shows the A/D con version timin g[...]

Rev. 1.0, 0 7/01, page 2 61 of 372 Table 16- 3 A /D Co nversion Ti me ( Sing le Mode) CKS = 0 CKS = 1 Item Symbol Min Typ Max Min Typ Max A/D conver sion start de lay time t D 6— 9 4 — 5 Input sampling tim e t SPL — 3 1— — 1 5— A/D conver sion time t CO NV 131 — 134 69 — 70 Note: All values repre sent the num ber of state s. 16.4.4 [...]

Rev. 1.0, 0 7/01, page 2 62 of 372 16.5 A/D Conversion Accuracy Definitions This LSI's A/D conversion accurac y definitions are given below. • Resolution The number of A/ D converter digi tal output c odes • Quantization error The deviation i nherent in the A/D co nverter, given by 1/2 LSB (s ee figure 16-4) . • Offset error The deviatio[...]

Rev. 1.0, 0 7/01, page 2 63 of 372 FS Digital output Ideal A/D conversion characteristic Nonlinearity error Analog input voltage Offset error Actual A/D conversion characteristic Full-scale error Figure 16-5 A/D Conversion Accuracy Definitions (2) 16.6 Usage Notes 16.6.1 Permissible Signal Source Impe dance This LSI's anal og input is des igne[...]

Rev. 1.0, 0 7/01, page 2 64 of 372 20 pF 10 k C in = 15 pF Sensor output impedance up to 5 k This LSI Low-pass filter C to 0.1 F Sensor input A/D conv er ter equivalent circuit Figure 16-6 Analog Input Circuit Example[...]

Rev. 1.0, 0 7/01, page 2 65 of 372 Section 17 Power-on Reset and Low-Vo ltage Detection Circuits (Optional) This LSI incl udes a power-on res et circuit and l ow-voltage detecti on circuit. The low-voltage detection circui t has two funct ions: one is to generate an int errupt when the power-supply v oltage falls bel ow or rises above res pective s[...]

Rev. 1.0, 0 7/01, page 2 66 of 372 PSS : L VDCR : L VDSR : Prescaler S Low-v oltage-detection control register Low-v oltage-detection status register Legend CK R PSS R S Q OV F Vreset Vint L VDCR L VDSR Reference voltage Analog-noise cancellation circuit Analog-noise cancellation circuit Interrupt control circuit Internal reset signal Interrupt req[...]

Rev. 1.0, 0 7/01, page 2 67 of 372 Bit Bit Name Initial Value R/W Description 7 LVDE 0 R/W LVD Enable 0: The low-voltage dete cti on cir c uit is not used. (In standb y mode) 1: The low-voltage dete cti on cir c uit is used. 6 to 4 − 1 − Reserved These bits ar e always read as 1, and cannot be modifie d. 3 LVDSEL 0 R/W LVDI Detection Level Sele[...]

Rev. 1.0, 0 7/01, page 2 68 of 372 17.2.2 Low-Voltage-Detection S tatus Regis ter (LVDSR) LVDSR is an 8-bi t readable/wri table register whic h indicates whet her or not the power-supply voltage has bec ome lower or hi gher than the respective specified values. Bit Bit Name Initial Value R/W Description 7 to 2 − 1 − Reserved These bits ar e alw[...]

Rev. 1.0, 0 7/01, page 2 69 of 372 V CC V SS V SS OV F PSS-reset signal Internal reset signal PSS counter star ts Reset released 131,072 cycles t PWON Figure 17-2 Op erational Tim ing of the Power-on Res et Circuit 17.3.2 Low-Voltage Detection Ci rcuit Reset by Low Voltage Detect (LVDR): Figure 17-3 s hows the timing of the LVDR function. LVDR ente[...]

Rev. 1.0, 0 7/01, page 2 70 of 372 V CC Vreset V SS OV F PSS-reset signal Internal reset signal PSS counter star ts Reset released 131,072 cycles Figure 17-3 Op erational Tim ing of LVDR Interrupt by Low Voltage Detect (LVDI) : Figure 17-4 s hows the timing of LVDI functions . LVDI enters the modul e-standby st ate when power is first supplied . To[...]

Rev. 1.0, 0 7/01, page 2 71 of 372 V CC Vint(D) Vint(U) V SS L VDDF L VDUE L VDUF IRQ0 interrupt generated IRQ0 interr upt generated L VDDE Figure 17-4 Op erational T iming of LVDI Procedures for Operating and Releasing the Low-Voltage Detection Circuit : To operate or releas e the low-voltage detection circuit normall y, follow the procedure descr[...]

Rev. 1.0, 0 7/01, page 2 72 of 372 L VDRE L VDDE L VDUE t L VDON t L VDOFF L VDE Figure 17-5 Timing for Operation/Release of the L ow-Voltage Detection Circuit[...]

Rev. 1.0, 0 7/01, page 2 73 of 372 Section 18 Power Supply Circuit This LSI incorporates an internal power su pply step-down circuit. Use of this circuit enables the internal power su pply to be fix ed at a const ant level of appr oximately 3.0 V, regardless of the voltage of t he power supply con nected to the exte rnal V CC pin. As a res ult, the[...]

Rev. 1.0, 0 7/01, page 2 74 of 372 18.2 When Not Using the Internal Power Supply Step-Down Circuit When the internal p ower supply step-dow n circuit is not us ed, connect the ext ernal power suppl y to the V CL pin and V CC pin, as s hown in figure 18 -2. The external power supply is then input directly to the int ernal power s upply. The permi ss[...]

Rev. 1.0, 0 7/01, page 2 75 of 372 Section 19 Internal I/O Registers 19.1 Register Addresses Register Name Abbre- viation Bit No Address Module Name Data Bus Width Access State —— — H'F000 to H'F72F —— — Low-voltag e detection control reg ister LVDCR 8 H'F730 LVDC * 1 82 Low-voltag e detection status reg ister LVDSR 8 H&a[...]

Rev. 1.0, 0 7/01, page 2 76 of 372 Register Name Abbre- viation Bit No Address Module Name Data Bus Width Access State Flash memory p ower control re gister FLPWCR 8 H'FF92 ROM 8 2 Erase blo ck regi ster 1 E BR1 8 H'FF93 ROM 8 2 —— — H'FF94 to H'FF9A —— — Flash memory e nable regi ster FENR 8 H'FF9B ROM 8 2 —?[...]

Rev. 1.0, 0 7/01, page 2 77 of 372 Register Name Abbre- viation Bit No Address Module Name Data Bus Width Access State Timer mode re gister WD TMWD 8 H'FFC2 WDT * 3 82 —— — H'FFC3 —— — —— — H'FFC4 to H'FFC7 —— — Address break control reg ister ABRKCR 8 H'FFC8 Address break 8 2 Address break status re[...]

Rev. 1.0, 0 7/01, page 2 78 of 372 Register Name Abbre- viation Bit No Address Module Name Data Bus Width Access State —— — H'FFE6, H'FFE7 I/O port —— Port control reg ister 5 PCR5 8 H'FFE8 I/O port 8 2 —— — H'FFE9 I/O port —— Port control reg ister 7 PCR7 8 H'FFEA I/O port 8 2 Port control reg ister 8 P[...]

Rev. 1.0, 0 7/01, page 2 79 of 372 19.2 Register Bits Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Na me — ———————— — LVDCR LV DE — — — LVDS EL LVDRE LVDDE LV DUE LVDC LVDSR — — — — — — LVDDF LVDUF (opti onal) * 1 — ———————— — ICCR1 ICE RCVD MST TRS CK S3 CKS 2 CKS 1 [...]

Rev. 1.0, 0 7/01, page 2 80 of 372 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Na me TCRV0 CMI EB CMI EA O VIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Timer V TCSRV CMFB CFMA OVF — OS3 OS2 OS1 O S0 TCORA TCORA 7 TCORA6 TCORA5 TCORA4 T CORA3 TCORA2 TCORA1 TCORA 0 TCORB TCORB 7 TCORB6 TCORB5 TCORB4 T CORB3 TCORB2 TCORB1 TCORB 0 TCNTV TC[...]

Rev. 1.0, 0 7/01, page 2 81 of 372 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Na me — ———————— — PUCR1 P UCR17 PUCR16 PUCR15 PUCR14 — PUCR12 PUCR11 PUCR10 I/O port PUCR5 — — PUCR55 PUCR54 P UCR53 PUCR52 PUCR51 PUCR50 PDR1 P17 P 16 P15 P14 — P12 P11 P 10 P D R 2 —————P 2 2 P 2 1 P 2 0 P[...]

Rev. 1.0, 0 7/01, page 2 82 of 372 19.3 Registers States in Each Operating Mode Register Name Reset Active Sl eep Subacti ve Subsleep Standby Module LVDCR Initialize d −−−−− LVDC LVDSR Initial ized −−−−− (optional) * 1 ICCR1 Initial ized −−−−− IIC2 ICCR2 Initial ized −−−−− ICMR Initial ized −−−−− IC[...]

Rev. 1.0, 0 7/01, page 2 83 of 372 Register Name Reset Active Sl eep Subacti ve Subsleep Standby Module TMA I nitialized −−−−− Timer A TCA Initi alized −−−−− SMR Init ialized −− Initial ized Initial ized Initial ized SC I3 BRR I nitializ ed −− Initia lized In itialized In itialized SCR3 Initialize d −− Initial ized I[...]

Rev. 1.0, 0 7/01, page 2 84 of 372 Register Name Reset Active Sl eep Subacti ve Subsleep Standby Module PCR5 Initialize d −−−−− I/O port PCR7 Initialize d −−−−− PCR8 Initialize d −−−−− SYSCR 1 Initiali zed −−−−− Power-down SYSCR 2 Initiali zed −−−−− Power-down IEGR1 Initi alized −−−−− In t[...]

Rev. 1.0, 0 7/01, page 2 85 of 372 Section 20 Electrical Chara cteristics 20.1 Absolute Maximum Ratings Table 20- 1 A bso lute Maxim um Ratings Item Symbol Value Unit Note Power suppl y voltage V CC –0.3 to +7. 0 V * Analog power supply v oltage AV CC –0.3 t o +7.0 V * Input voltag e Ports other than ports B and X1 V IN –0.3 to V CC +0.3 V * [...]

Rev. 1.0, 0 7/01, page 2 86 of 372 Power Supply Volta g e and Operating Frequency Range 10.0 1.0 16.0 3.0 4.0 5.5 V CC (V) ø (MHz) 16.384 3.0 4.0 5.5 V CC (V) ø SUB (kHz) 8.192 4.096 1250 78.125 2000 3.0 4.0 5.5 V CC (V) ø (kHz) • A V CC = 3.3 to 5.5 V • Active mode • Sleep mode (When MA2 in SYSCR2 = 0 ) • A V CC = 3.3 to 5.5 V • Subac[...]

Rev. 1.0, 0 7/01, page 2 87 of 372 20.2.2 DC Characteristics Table 20-2 DC Characteristics (1) V CC = 3.0 to 5. 5 V, V SS = 0.0 V, T a = –2 0 to +75°C , unless otherwis e indicated. Values Item Symb ol Applicable Pins Test Condit ion Min Typ Max Unit Note s Input high voltage V IH RES , NMI , WKP0 to WKP 5 , IRQ0 to IRQ3 , ADTRG ,T MRIV, V CC = [...]

Rev. 1.0, 0 7/01, page 2 88 of 372 Values Item Symb ol Applicable Pins Test Condit ion Min Typ Max Unit Note s Output high voltage V OH P10 to P12, P14 to P17, P20 to P22, V CC = 4 .0 to 5 .5 V –I OH = 1 .5 mA V CC – 1.0 — — V P50 to P55, P74 to P76, P80 to P87, –I OH = 0 .1 mA V CC – 0.5 — — P56, P5 7 V CC = 4 .0 to 5 .5 V –I OH [...]

Rev. 1.0, 0 7/01, page 2 89 of 372 Values Item Symb ol Applicable Pins Test Condit ion Min Typ Max Unit Note s Input/ output leakage current | I IL |O S C 1 , NM I , WKP0 to WKP 5 , IRQ0 to IRQ3 , ADTRG , TRGV, TMRIV, TMCIV, FTCI, FT IOA to FTIOD, RXD , SCK3, SCL , SDA V IN = 0.5 V or higher (V CC – 0.5 V) —— 1 . 0 µ A P10 to P12, P14 to P17[...]

Rev. 1.0, 0 7/01, page 2 90 of 372 Values Item Symb ol Applicable Pins Test Condit ion Min Typ Max Unit Note s Sleep mode current I SLEEP1 V CC Sleep mode 1 V CC = 5.0 V, f OSC = 16 MHz —T B D T B D m A * consump- tion Sleep mode 1 V CC = 3.0 V, f OSC = 10 MH z —T B D — * Reference value I SLEEP2 V CC Sleep mode 2 V CC = 5.0 V, f OSC = 16 MHz[...]

Rev. 1.0, 0 7/01, page 2 91 of 372 Note: * Pin states dur ing curr ent consumpti on measureme nt are given below (e xcluding current in the pull- up MOS transist ors and output b uffers). Mode R ES Pin Internal St ate Other Pins Oscillat or Pins Acti ve mode 1 V CC Operates V CC System clo ck os cil lator: cerami c or cry s tal Active mode 2 Operat[...]

Rev. 1.0, 0 7/01, page 2 92 of 372 Table 20-2 DC Characteristics (2) V CC = 3.0 to 5. 5 V, V SS = 0.0 V, T a = –2 0 to +75°C , unless otherwis e indicated. Applicab le Values Item Symbol Pins Test Condit ion Min Typ Max Unit Allowabl e output low current (per pin) I OL Output pins except port 8, SCL and SDA V CC = 4.0 to 5.5 V — — 2 .0 mA Po[...]

Rev. 1.0, 0 7/01, page 2 93 of 372 20.2.3 AC Characteristics Table 20-3 AC Characteristics V CC = 3.0 to 5. 5 V, V SS = 0.0 V, T a = –2 0 to +75°C , unless otherwis e incicated. Applicab le Values Reference Item Symb ol Pins Test Cond ition Min Typ Max Unit Figure Syste m clo ck oscilla tion f OSC OSC 1 , OSC 2 V CC = 4.0 to 5.5 V 2. 0 — 16. 0[...]

Rev. 1.0, 0 7/01, page 2 94 of 372 Applicab le Values Reference Item Symb ol Pins Test Cond ition Min Typ Max Unit Figure RES pin l ow width t REL RES A t power-on and in modes other than those below t rc — — ms Figure 20-2 In active mode and sleep mode operation 1 0 ——t cyc Input pin high width t IH NMI , IRQ0 to IRQ3 , WKP0 to WKP5 , TMCI[...]

Rev. 1.0, 0 7/01, page 2 95 of 372 Table 20-4 I 2 C Bus Interface Timing V CC = 3.0 to 5. 5 V, V SS = 0.0 V, T a = –2 0 to +75°C , unless otherwis e indicated. Test Values Reference Item Symbol Condition Min Typ Max Unit Figure SCL i npu t cycl e time t SCL 12t cyc + 600 — — ns Figure 20-4 SCL input hi gh width t SCLH 3t cyc + 300 — — ns[...]

Rev. 1.0, 0 7/01, page 2 96 of 372 Table 20-5 Serial Communication Interface (SCI) Timing V CC = 3.0 to 5. 5 V, V SS = 0.0 V, T a = –2 0 to +75°C , unless otherwis e indicated. A pp licab le Values Reference Item Symbol Pins Test Cond ition Min Typ Max Unit Figure Input clock As ynchro- nous t Scyc SCK3 4 — — t cyc Fi gure 20-5 cycle Synchro[...]

Rev. 1.0, 0 7/01, page 2 97 of 372 20.2.4 A/D Converter Characteristic s Table 20-6 A/D Converter Characteristics V CC = 3.0 to 5. 5 V, V SS = 0.0 V, T a = –2 0 to +75°C , unless otherwis e indicated. Applicable Test Values Reference Item Symbol Pins Condition Min Typ Max Unit Figure Analog power supply voltage AV CC AV CC 3. 3 V CC 5.5 V * 1 An[...]

Rev. 1.0, 0 7/01, page 2 98 of 372 Applicable Test Values Reference Item Symbol Pins Condition Min Typ Max Unit Figure Conversion t ime (single mode) AV CC = 4 .0 to 5.5 V 134 — — t cyc Nonlinearit y error — — ±3.5 LS B Offset error — — ±3.5 LSB Full-scale error — — ±3.5 LSB Quantization error — — ± 0. 5 LSB Absolu te a ccur[...]

Rev. 1.0, 0 7/01, page 2 99 of 372 20.2.6 Flash Me mory Characteristics Table 20-8 Flash Memory Characteristi cs V CC = 3.0 to 5.5 V, V SS = 0.0 V, T a = –20 to +75°C, u nless otherwis e indicated. Test Values Item Sym bol Conditi on Min Typ Max Unit Programming time (per 128 bytes) * 1 * 2 * 4 t P —7 —m s Erase time (per block) * 1 * 3 * 6 [...]

Rev. 1.0, 0 7/01, page 3 00 of 372 Test Values Item Sym bol Conditi on Min Typ Max Unit Erasing Wait time after S WE bit se tting * 1 x 1 ——µ s Wait time af ter ESU bit se tting * 1 y 100 — — µs Wait time af ter E b it setting * 1 * 6 z 10 — 100 m s Wait time after E bit cl ear * 1 α 1 0 ——µ s Wait time after ES U bit cl ear * 1 ?[...]

Rev. 1.0, 0 7/01, page 3 01 of 372 20.2.7 Power-Supply- Voltage Det ect io n Circuit Characterist ics (Optional) Table 20-9 Po wer-Supply-Volt a ge Detection Circuit Cha racteristics V CC = 3.0 to 5.5 V, V SS = 0.0 V, T a = –20 to +75°C, u nless otherwi se specified. Test Values Item Symbol Condition Min Typ Max Unit Rising b y low-voltage detec[...]

Rev. 1.0, 0 7/01, page 3 02 of 372 20.3 Electrical Characteristics ( Mask ROM Version) 20.3.1 Power Supply Volta g e and Operating Ra nges Power Supply Volta g e and Oscillatio n Frequency Ra nge 10.0 2.0 16.0 2.7 4.0 5.5 V CC (V) ø OSC (MHz) 32.768 2.7 4.0 5.5 V CC (V) ø W (kHz) • A V CC = 3.0 to 5.5 V • Active mode • Sleep mode • A V CC[...]

Rev. 1.0, 0 7/01, page 3 03 of 372 Analog Power Supply Vo lt a ge and A/D Converter Accura cy Guarantee Range 10.0 2.0 16.0 3.0 4.0 5.5 A V CC (V) ø (MHz) • V CC = 2.7 to 5.5 V • Active mode • Sleep mode 20.3.2 DC Characteristics Table 20-10 DC Characteristics (1) V CC = 2.7 to 5. 5 V, V SS = 0.0 V, T a = –2 0 to +75°C , unless otherwis e[...]

Rev. 1.0, 0 7/01, page 3 04 of 372 Values Item Symb ol Applicable Pins Test Condit ion Min Typ Max Unit Note s Input low voltage V IL RES , NMI , WKP0 to WKP 5 , IRQ0 to IRQ3 , ADTRG ,T MRIV, V CC = 4.0 to 5.5 V –0. 3 — V CC × 0. 2 V TMCIV, FTCI, FTIOA to FTIO D, SCK3, TR GV –0.3 — V CC × 0. 1 RXD, S CL, SDA, P10 to P12, P14 to P17, P20 t[...]

Rev. 1.0, 0 7/01, page 3 05 of 372 Values Item Symb ol Applicable Pins Test Condit ion Min Typ Max Unit Note s Output low voltage V OL P10 to P12, P14 to P17, P20 to P22, V CC = 4 .0 to 5 .5 V I OL = 1 .6 mA —— 0 . 6 V P50 to P57, P74 to P76 I OL = 0.4 mA — — 0. 4 P80 to P87 V CC = 4.0 to 5.5 V I OL = 2 0.0 mA —— 1 . 5 V V CC = 4 .0 to [...]

Rev. 1.0, 0 7/01, page 3 06 of 372 Values Item Symb ol Applicable Pins Test Condit ion Min Typ Max Unit Not es Input capaci- tance C in All input pins except power supply pins f = 1 MH z, V IN = 0.0 V, T a = 25°C — — 15. 0 pF Acti ve mode current I OPE1 V CC Active mo de 1 V CC = 5.0 V, f OSC = 16 MHz —T B D T B D m A * consump- tion Acti ve[...]

Rev. 1.0, 0 7/01, page 3 07 of 372 Values Item Symb ol Applicable Pins Test Condit ion Min Typ Max Unit Notes RAM data retainin g voltage V RAM V CC 2.0 — — V Note: * Pin state s during curr ent consumption m easurement are given bel ow (excludi ng current in the pull- up MOS transist ors and output b uffers). Mode R ES Pin Internal St ate Othe[...]

Rev. 1.0, 0 7/01, page 3 08 of 372 Table 20-10 DC Characteristics (2) V CC = 2.7 to 5. 5 V, V SS = 0.0 V, T a = –2 0 to +75°C , unless otherwis e indicated. Applicab le Values Item Symbol Pins Test Cond ition Min Typ Max Unit Allowabl e output low current (per pin) I OL Output pins except port 8, SCL and SDA V CC = 4 .0 to 5.5 V — — 2.0 mA P[...]

Rev. 1.0, 0 7/01, page 3 09 of 372 20.3.3 AC Characteristics Table 20-11 AC Characteristics V CC = 2.7 to 5. 5 V, V SS = 0.0 V, T a = –2 0 to +75°C , unless otherwis e indicated. A pp licab le Values Reference Item Symb ol Pins Test Cond ition Min Typ Max Unit Figure Syste m clo ck oscilla tion f OSC OSC 1 , OSC 2 V CC = 4.0 to 5.5 V 2. 0 — 16[...]

Rev. 1.0, 0 7/01, page 3 10 of 372 Applicab le Values Reference Item Symb ol Pins Test Cond ition Min Typ Max Unit Figure RES pin l ow width t REL RES A t power-on and in modes other than those below t rc — — ms Figure 20-2 In active mode and sleep mode operation 1 0 ——t cyc Input pin high width t IH NMI , IRQ0 to IRQ3 , WKP0 to WKP5 , TMCI[...]

Rev. 1.0, 0 7/01, page 3 11 of 372 Table 20-12 I 2 C Bus Interface Timing V CC = 2.7 V to 5.5 V, V SS = 0. 0 V, T a = –20 t o +75°C, unles s otherwise speci fied. Test Values Reference Item Symbol Condition Min Typ Max Unit Figure SCL i npu t cycl e time t SCL 12t cyc + 600 — — ns Figure 20- 4 SCL input hi gh width t SCLH 3t cyc + 300 — ?[...]

Rev. 1.0, 0 7/01, page 3 12 of 372 Table 20-13 Serial Commu nication Interface (SCI) Timing A pp licab le Values Reference Item Symbol Pins Test Condition Min Typ Max U nit Figure Input clock As ynchro- nous t Scyc 4— — t cyc Figure 20-5 cycle Clo cked synchronous 6— — Input c lock pulse width t SCKW SCK3 0.4 — 0.6 t Scyc Figure 20-5 Tran[...]

Rev. 1.0, 0 7/01, page 3 13 of 372 20.3.4 A/D Converter Characteristic s Table 20-14 A/D Converter Characteristics V CC = 2.7 to 5. 5 V, V SS = 0.0 V, T a = –2 0 to +75°C , unless otherwis e indicated. Applicable Test Values Reference Item Symbol Pins Condition Min Typ Max Unit Figure Analog power supply voltage AV CC AV CC 3. 3 V CC 5.5 V * 1 A[...]

Rev. 1.0, 0 7/01, page 3 14 of 372 A pp licable Test Values Reference Item Symbol Pins Condition Min Typ Max Unit Figure Conversion t ime (single mode) AV CC = 4 .0 to 5.5 V 134 — — t cyc Nonlinearit y error — — ±3.5 LSB Offset error — — ± 3. 5 LS B Full-scale error — — ±3. 5 LS B Quantization error — — ±0. 5 LS B Absolu te [...]

Rev. 1.0, 0 7/01, page 3 15 of 372 20.3.6 Power-Supply- Voltage Det ect io n Circuit Characterist ics (Optional) Table 20-1 6 Power-Supply-Vo ltage Detectio n Circuit Characterist ics V CC = 2.7 to 5.5 V, V SS = 0.0 V, T a = –20 to +75°C, u nless otherwi se specified. Test Values Item Symbol Condition Min Typ Max Unit Rising b y low-voltage dete[...]

Rev. 1.0, 0 7/01, page 3 16 of 372 V IH V IL t IL to to TMCI FTIOA to FTIOD TMCIV, TMRIV TRGV t IH Figure 20-3 Input Timing SCL V IH V IL t ST AH t BUF P * S * t Sf t Of t Sr t SCL t SDAH t SCLH t SCLL SD A Sr * t ST AS t SP t STOS t SDAS P * Note: * S, P , and Sr represent the follo wing: S: Start condition P: Stop condition Sr: Retransmission sta[...]

Rev. 1.0, 0 7/01, page 3 17 of 372 t Scyc t TXD t RXS t RXH V OH V or V IH OH V or V IL OL * * * V OL * SCK3 TXD (transmit data) RXD (receive data) Note: * Output timing reference levels Output high: Output low: Load conditions are shown in figure 20-7. V = 2.0 V V = 0.8 V OH OL Figure 20-6 SCI Synchronous Mo de In put/Output Timing 20.5 Output Loa[...]

Rev. 1.0, 0 7/01, page 3 18 of 372[...]

Rev. 1.0, 0 7/01, page 3 19 of 372 Appendix A Instruction Set A.1 Instruction List Condition Code Symbol Description Rd General destinatio n regist er Rs General source register Rn General register ERd General destin ation regist er (address r egister or 32-bit r egister) ERs General source r egister (addres s register or 32-b it register) ERn Gene[...]

Rev. 1.0, 0 7/01, page 3 20 of 372 Condition Cod e Notation (cont) Symbol Description ↔ Changed a ccording to execution result * Undetermin ed (no guaranteed value) 0 Cleared to 0 1 Set to 1 — Not affected b y execution of the instruction ∆ Varies depend ing on con ditions, de scribed in notes[...]

Rev. 1.0, 0 7/01, page 3 21 of 372 Table A.1 Instruct io n Set 1. Data Transfer Inst ructions Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs)[...]

Rev. 1.0, 0 7/01, page 3 22 of 372 Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — MOV.W Rs, @–ERd MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, Rd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16, ERs), ERd MOV.L @(d:24, ERs), [...]

Rev. 1.0, 0 7/01, page 3 23 of 372 2. Arithmetic Instruction s Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDX.B #xx:8, Rd ADDX.B [...]

Rev. 1.0, 0 7/01, page 3 24 of 372 Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — DEC.L #1, ERd DEC.L #2, ERd DAS.Rd MULXU. B Rs, Rd MULXU. W Rs, ERd MULXS. B Rs, Rd MULXS. W Rs, ERd DIVXU. B Rs, Rd DIVXU. W Rs, ERd DIVXS. B R[...]

Rev. 1.0, 0 7/01, page 3 25 of 372 Mnemonic Operation Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — NEG.B Rd NEG.W Rd NEG.L ERd EXTU.W Rd EXTU.L ERd EXTS.W Rd EXTS.L ERd 0–Rd8 → Rd8 0–Rd16 → Rd16 0–ERd32 → ERd32 0 → (<[...]

Rev. 1.0, 0 7/01, page 3 26 of 372 3. Logic Inst ructions Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd OR.B #xx:8, Rd OR.B Rs, Rd OR[...]

Rev. 1.0, 0 7/01, page 3 27 of 372 4. Shift Instructions Mnemonic Operand Size No. of States * 1 Condition Code IH N Z V C SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR.B Rd SHLR.W Rd SHLR.L ERd ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR[...]

Rev. 1.0, 0 7/01, page 3 28 of 372 5. Bit-Mani pulation Ins tructions Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BCLR #xx:3, Rd BCL[...]

Rev. 1.0, 0 7/01, page 3 29 of 372 Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — BLD #xx:3, @ERd BLD #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8 BIST #xx:3, Rd[...]

Rev. 1.0, 0 7/01, page 3 30 of 372 6. Branching I nstructions — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — [...]

Rev. 1.0, 0 7/01, page 3 31 of 372 Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — JMP @ERn JMP @aa:24 JMP @@aa:8 BSR d:8 BSR d:16 JSR @ERn JSR @aa:24 JSR @@aa:8 RTS Operation PC ← ERn PC ← aa:24 PC ← @aa:8 PC → @–SP [...]

Rev. 1.0, 0 7/01, page 3 32 of 372 7. System C ontrol Inst ructions Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — TRAPA #x:2 RTE SLEEP LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(d:16, ERs), CCR LDC @(d:24, ERs), CCR LDC @[...]

Rev. 1.0, 0 7/01, page 3 33 of 372 8. Block Tra nsfer Instructi ons Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — EEPMOV. B EEPMOV. W Operation if R4L ≠ 0 then repeat @R5 → @R6 R5+1 → R5 R6+1 → R6 R4L–1 → R4L unti[...]

Rev. 1.0, 0 7/01, page 3 34 of 372 A.2 Operation Cod e Map Table A.2 O pera tion Code Map (1 ) AH AL 0123 4567 89A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F NOP BRA MULXU BSET BRN DIVXU BNOT STC BHI MULXU BCLR LDC BLS DIVXU BTST ORC OR.B BCC RTS OR XORC XOR.B BCS BSR XOR BOR BIOR BXOR BIXOR BAND BIAND ANDC AND.B BNE RTE AND LDC BEQ TRAPA BLD BILD B[...]

Rev. 1.0, 0 7/01, page 3 35 of 372 Table A.2 O pera tion Code Map (2 ) AH AL BH 0123 4567 89 A B C D E F 01 0A 0B 0F 10 11 12 13 17 1A 1B 1F 58 79 7A MOV INC ADDS DAA DEC SUBS DAS BRA MOV MOV BHI CMP CMP LDC/STC BCC OR OR BPL BGT Instruction code: BVS SLEEP BVC BGE Table A-2 (3) Table A-2 (3) Table A-2 (3) ADD MOV SUB CMP BNE AND AND INC EXTU DEC B[...]

Rev. 1.0, 0 7/01, page 3 36 of 372 Table A.2 O pera tion Code Map (3 ) AH ALBH BLCH CL 0123 4567 89A B C D E F 01406 01C05 01D05 01F06 7Cr06 7Cr07 7Dr06 7Dr07 7Eaa6 7Eaa7 7Faa6 7Faa7 MULXS BSET BSET BSET BSET DIVXS BNOT BNOT BNOT BNOT MULXS BCLR BCLR BCLR BCLR DIVXS BTST BTST BTST BTST OR XOR BOR BIOR BXOR BIXOR BAND BIAND AND BLD BILD BST BIST Ins[...]

Rev. 1.0, 0 7/01, page 3 37 of 372 A.3 Number of Execution States The status of execution fo r each instruction of the H8/300H CPU and the met hod of calculating the number of states required fo r instructio n execution are show n below. Table A.4 s hows the number of cycles of each t ype occurring in each instruction, such as instruction fetch and[...]

Rev. 1.0, 0 7/01, page 3 38 of 372 Table A.3 Number of Cycles in Each In struction Execution Status Access Location (Instruction Cycle) On-Chip M emory On-Chip Peripheral Module Instructi on fetch S I 2— Branch addr ess read S J Stack oper ation S K Byte data ac cess S L 2 or 3 * Word data acc ess S M — Internal operat ion S N 1 Note: * Depends[...]

Rev. 1.0, 0 7/01, page 3 39 of 372 Table A.4 Number of Cycles in Each Instruction Inst ructio n Mnemon ic Inst ruct ion Fetc h I Branch Addr. Read J Stack Operati on K Byte Data Access L Word Data Access M Internal Operati on N ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ER d ADD.L ERs, ERd 1 1 2 1 3 1 ADDS ADDS #1/[...]

Rev. 1.0, 0 7/01, page 3 40 of 372 Inst ructio n Mnemon ic Inst ruct ion Fetc h I Branch Addr. Read J Stack Operati on K Byte Data Access L Word Data Access M Internal Operati on N Bcc BLT d:8 BGT d: 8 BLE d:8 BRA d:16(BT d:16) BRN d:1 6(BF d:16) BHI d:16 BLS d:16 BCC d:16(BH S d: 16) BCS d :16( BLO d:16 ) BNE d:16 BEQ d: 16 BVC d:16 BVS d:16 BPL d[...]

Rev. 1.0, 0 7/01, page 3 41 of 372 Inst ructio n Mnemon ic Inst ruct ion Fetc h I Branch Addr. Read J Stack Operati on K Byte Data Access L Word Data Access M Internal Operati on N BIOR BIOR #x x:8, Rd BIOR #xx:8, @ERd BIOR #xx:8, @aa:8 1 2 2 1 1 BIST BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 1 2 2 2 2 BIXOR BIXOR #x x:3, Rd BIXOR #xx:3, @E[...]

Rev. 1.0, 0 7/01, page 3 42 of 372 Inst ructio n Mnemon ic Inst ruct ion Fetc h I Branch Addr. Read J Stack Operati on K Byte Data Access L Word Data Access M Internal Operati on N BTST BTST # xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa: 8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 1 2 2 1 2 2 1 1 1 1 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @a[...]

Rev. 1.0, 0 7/01, page 3 43 of 372 Inst ructio n Mnemon ic Inst ruct ion Fetc h I Branch Addr. Read J Stack Operati on K Byte Data Access L Word Data Access M Internal Operati on N INC INC.B Rd INC.W #1/2, Rd INC.L #1/ 2, ERd 1 1 1 JMP JMP @ER n JMP @aa: 24 JMP @@aa: 8 2 2 21 2 2 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 2 2 21 1 1 1 2 LDC LDC #xx:8, CCR [...]

Rev. 1.0, 0 7/01, page 3 44 of 372 Inst ructio n Mnemon ic Inst ruct ion Fetc h I Branch Addr. Read J Stack Operati on K Byte Data Access L Word Data Access M Internal Operati on N MOV MOV.B R s, @aa: 16 MOV.B R s, @aa: 24 MOV.W #xx: 16, Rd MOV.W R s, Rd MOV.W @ERs, Rd MOV.W @(d:16,ERs), Rd MOV.W @(d:24,ERs), Rd MOV.W @ERs+, Rd MOV .W @aa: 16, Rd M[...]

Rev. 1.0, 0 7/01, page 3 45 of 372 Inst ructio n Mnemon ic Inst ruct ion Fetc h I Branch Addr. Read J Stack Operati on K Byte Data Access L Word Data Access M Internal Operati on N MULXS MUL XS. B Rs, Rd MULXS.W Rs, ERd 2 2 12 20 MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd 1 1 12 20 NEG NEG.B Rd NEG.W Rd NEG.L ERd 1 1 1 NOP NOP 1 NOT NOT.B Rd NOT.W Rd NOT[...]

Rev. 1.0, 0 7/01, page 3 46 of 372 Inst ructio n Mnemon ic Inst ruct ion Fetc h I Branch Addr. Read J Stack Operati on K Byte Data Access L Word Data Access M Internal Operati on N ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd 1 1 1 RTE RTE 2 2 2 RTS RTS 2 1 2 SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd 1 1 1 SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd 1 1 1 SHLL SHLL.B[...]

Rev. 1.0, 0 7/01, page 3 47 of 372 Inst ructio n Mnemon ic Inst ruct ion Fetc h I Branch Addr. Read J Stack Operati on K Byte Data Access L Word Data Access M Internal Operati on N SUBX SUBX #xx:8, Rd SUBX. Rs, Rd 1 1 TRAPA TRAPA #xx:2 2 1 2 4 XOR XOR.B #x x:8, Rd XOR.B Rs, Rd XOR.W #xx:16, R d XOR.W Rs, Rd XOR.L #xx: 32, ER d XOR.L ERs, ERd 1 1 2 [...]

Rev. 1.0, 0 7/01, page 3 48 of 372 A.4 Combinations of Instructions an d Addressing Mode s Table A.5 Co mbinations o f Instructions a nd Addressing Mo des Addressing Mode MO V POP , PUSH MO VFPE, MO VTPE ADD , CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC D AA, D AS MULXU , MULXS, DIVXU , DIVXS NEG EXTU , EXTS AND , OR, XOR NO T BCC, BSR JMP , JSR RTS TRA[...]

Rev. 1.0, 0 7/01, page 3 49 of 372 Appendix B I/O Port Block Diagrams B.1 I/O Port Block RES goes low in a reset, and SBY goes low in a rese t and in standby m ode. PDR PUCR PMR PCR PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register TRGV Internal data bus Pull-up MOS Legend Figure B.1 Port[...]

Rev. 1.0, 0 7/01, page 3 50 of 372 PDR PUCR PMR PCR PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Internal data bus Pull-up MOS Legend Figure B.2 Port 1 Block Diagram (P16 to P14)[...]

Rev. 1.0, 0 7/01, page 3 51 of 372 PDR PUCR PCR PUCR: Port pull-up control register PDR: Port data register PCR: Port control register Internal data bus Pull-up MOS Legend Figure B.3 Port 1 Block Diagram (P12, P11)[...]

Rev. 1.0, 0 7/01, page 3 52 of 372 PDR PUCR PMR PCR PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Internal data bus TMOW Timer A Pull-up MOS Legend Figure B.4 Port 1 Block Diagram (P10)[...]

Rev. 1.0, 0 7/01, page 3 53 of 372 PDR PMR PCR PMR: Port mode register PDR: Port data register PCR: Port control register Internal data bus TxD SCI3 Legend Figure B.5 Port 2 Block Diagram (P22)[...]

Rev. 1.0, 0 7/01, page 3 54 of 372 PDR PCR PDR: Port data register PCR: Port control register RE Internal data bus RxD SCI3 Legend Figure B.6 Port 2 Block Diagram (P21)[...]

Rev. 1.0, 0 7/01, page 3 55 of 372 PDR PCR PDR: Port data register PCR: Port control register SCKIE Internal data bus SCKI SCI3 SCK OE SCK O Legend Figure B.7 Port 2 Block Diagram (P20)[...]

Rev. 1.0, 0 7/01, page 3 56 of 372 PDR PCR ICE SD AO/SCLO SD AI/SCLI IIC2 PDR: Port data register PCR: Port control register Internal data bus Legend Figure B.8 Port 5 Block Diagram (P57, P56)[...]

Rev. 1.0, 0 7/01, page 3 57 of 372 PDR PUCR PMR PCR PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Internal data bus Pull-up MOS Legend Figure B.9 Port 5 Block Diagram (P55)[...]

Rev. 1.0, 0 7/01, page 3 58 of 372 PDR PUCR PMR PCR PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Internal data bus Pull-up MOS Legend Figure B.10 Port 5 Block Diagram (P54 to P50)[...]

Rev. 1.0, 0 7/01, page 3 59 of 372 PDR PCR OS3 OS2 OS1 OS0 TMO V PDR: Port data register PCR: Port control register Internal data bus Timer V Legend Figure B.11 Port 7 Block Diagram (P76)[...]

Rev. 1.0, 0 7/01, page 3 60 of 372 PDR PCR TMCIV PDR: Port data register PCR: Port control register Internal data bus Timer V Legend Figure B.12 Port 7 Block Diagram (P75)[...]

Rev. 1.0, 0 7/01, page 3 61 of 372 PDR PCR TMRIV PDR: Port data register PCR: Port control register Internal data bus Timer V Legend Figure B.13 Port 7 Block Diagram (P74)[...]

Rev. 1.0, 0 7/01, page 3 62 of 372 PDR PCR PDR: Port data register PCR: Port control register Internal data bus Legend Figure B.14 Port 8 Block Diagram (P87 to P85)[...]

Rev. 1.0, 0 7/01, page 3 63 of 372 PDR PCR PDR: Port data register PCR: Port control register Internal data bus FTIOA FTIOB FTIOC FTIOD Timer W Output control signals A to D Legend Figure B.15 Port 8 Block Diagram (P84 to P81)[...]

Rev. 1.0, 0 7/01, page 3 64 of 372 PDR PCR FTCI PDR: Port data register PCR: Port control register Internal data bus Timer W Legend Figure B.16 Port 8 Block Diagram (P80)[...]

Rev. 1.0, 0 7/01, page 3 65 of 372 DEC V IN CH3 to CH0 A/D conv er ter Internal data bus Figure B.17 Port B Block Di agram (PB7 to PB0) B.2 Port States in Each Operating State Port Reset Sleep Subsleep Standby Subactive Active P17 to P14, P12 to P10 High impedance Retained Retained High impedance * Functioning Function ing P22 to P20 High impedance[...]

Rev. 1.0, 0 7/01, page 3 66 of 372 Appendix C Product Code Lineup Package (Hitachi Package Code) Product Type QFP-64 (FP-64A) LQFP-64 (FP-64E) LQFP-48 (FP-48F) Flash memory version Product with POR & LVDC HD64F3694GH HD64F3694GFP HD64F3694GFX Standard product HD64F3694H HD64F3694FP HD64F3694FX Mask Ro m version Product with POR & LVDC HD643[...]

Rev. 1.0, 0 7/01, page 3 67 of 372 Appendix D Package Dimensions The package dimensi ons that are s hows in the Hitachi S emiconductor P ackages Data Book has priority. Hitachi Code JEDEC EIAJ Mass (reference value) FP-64E Conforms 0.4 g Unit: mm *Dimension including the plating thickness Base material dimension M 12.0 ± 0.2 10 48 33 11 6 17 32 64[...]

Rev. 1.0, 0 7/01, page 3 68 of 372 Hitachi Code JEDEC EIAJ Mass (reference value) FP-64A Conforms 1.2 g Unit: mm *Dimension including the plating thickness Base material dimension 0.10 0.15 M 17.2 ± 0.3 48 33 49 64 1 16 32 17 17.2 ± 0.3 0.35 ± 0.06 0.8 3.05 Max 14 2.70 0 8 1.6 0.8 ± 0.3 *0.17 ± 0.05 0.10 +0.15 - 0.10 1.0 *0.37 ± 0.08 0.15 ± [...]

Rev. 1.0, 0 7/01, page 3 69 of 372 Index A/D Converter ........................................ 253 sample-and-hold circu it ...................... 260 Scan Mode .......................................... 259 Single Mode ........................................ 259 Absolute Maximum R atings ................... 285 Address Break ....................[...]

Rev. 1.0, 0 7/01, page 3 70 of 372 large curren t ports ....................................... 1 Memory Map .............................................. 8 Module Standby Function......................... 79 On-Board Programm in g Modes................ 86 Package ....................................................... 1 Package Dimensions .......[...]

Rev. 1.0, 0 7/01, page 3 71 of 372 TCORA ....................... 139, 276, 279, 281 TCORB ....................... 139, 276, 279, 2 81 TCRV0........................ 140, 275, 279, 281 TCRV1........................ 143, 276, 279, 281 TCRW ......................... 156, 275, 278, 281 TCSRV ....................... 142, 275, 279, 281 TCSRWD.............[...]

Rev. 1.0, 0 7/01, page 3 72 of 372[...]

H8/3694 Series Hardware Manual Publication Date: 1 st Edition, Ju ly 2001 Published by: Customer Service Divis ion Semiconductor & Integrated Ci rcuits Hitachi, Ltd. Edited by: Technical Documentation Grou p Hitachi Kodaira S emiconductor Co., Lt d. Copyright © Hi tachi, Ltd., 200 1. All rights reserved. Printe d in Japan.[...]