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Intel 41210 manual

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Table of contents for the manual

  • Page 1

    Order N umber: 27 8890-00 3US Intel ® 41210 Serial to Parallel PCI Bridge Developer’s Manual May 2005[...]

  • Page 2

    2 Intel ® 41210 Serial to Parallel PCI Bridg e Develo per’s Manua l INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CO NNECTION WITH INT EL ® PRODUCTS. EXCEPT AS PROVIDED IN INTEL ’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILI TY WHA TSOEVER, AND INTEL DISCLAIMS ANY EXP RESS OR IMPLIED WARRANTY RELA TING T O SALE AND[...]

  • Page 3

    Intel ® 41210 Se rial to Parallel P CI Bridge De veloper’s M anual 3 Contents Contents 1 Introduction ... ............. .................... ............. ................... ............. ................... ............. ................. 11 1.1 PCI Express * Interface Features .................... ............ ............. ..................[...]

  • Page 4

    4 Intel ® 41210 S erial to Par allel PCI Bridge De velope r’s Manual Contents 5.3.1 PCI Expre ss* Configu ration Acces s ........... ................... ............. .................... ....... 42 5.3.2 Type 0 Con figuration A ccess from PCI -X Interface .............. ............. ................... . 44 5.3.3 SMBus Configuratio n Access ..[...]

  • Page 5

    Intel ® 41210 Se rial to Parallel P CI Bridge De veloper’s M anual 5 Contents 12.2.6 Offset 0C h: CLS—Cac he-Line Si ze ... ............ ............. .................... ............. .......... 81 12.2.7 Offset 0D h: PMLT—Primary Master Laten cy Timer ................ .................... .......... 8 1 12.2.8 Offset 0Eh: HEADTYP— Heade[...]

  • Page 6

    6 Intel ® 41210 S erial to Par allel PCI Bridge De velope r’s Manual Contents 12.2.53 Offset 108h: ERRUNC_ MSK—PCI E xpress* Uncorrectab le Error Mask ........ ............. ................... ............. ................... ............ 106 12.2.54 Offset 10Ch: ERRUNC_S EV—PCI Ex press* Uncorrectabl e Error Severit y . ..................[...]

  • Page 7

    Intel ® 41210 Se rial to Parallel P CI Bridge De veloper’s M anual 7 Contents Tabl es 1 ODT Signal s ....... ............. ................... ............. ................... ............. ............. .......................... .... 14 2 PCI Expres s* Interface P ins .. ............. .................... ............ .................... ...[...]

  • Page 8

    8 Intel ® 41210 S erial to Par allel PCI Bridge De velope r’s Manual Contents 50 Offset 2C h: PMLU32— Prefetchabl e Memory Li mit Upper 32 Bi ts ..... .................... ............. ....... 87 51 Offset 30h: IOBLU1 6—I/ O Base and Lim it Upper 16 Bit s ..... ....... ...... ....... ...... ....... ...... ....... ...... . 87 52 Offset 34h: [...]

  • Page 9

    Intel ® 41210 Se rial to Parallel P CI Bridge De veloper’s M anual 9 Contents 100 Offset 178 h: PREF CTRL—Prefetch Control Regis ter .. ................... ............. .................... ........ 11 9 101 Offse t 300h: PW RBGT_HD R—Power B udgeting E nhanced Capabilit y Header .............. ........ 120 102 Offset 304 h: PWRBG T_DSEL—[...]

  • Page 10

    10 Intel ® 41210 S erial to Par allel PCI Bridge De velope r’s Manual Contents Revision History Date Revision Description May 2005 003 Revised T able 1 and T able 9 October 2004 002 Updated PCI Express operation information in Section 1.1 and T able 2 in Section 2 .2 . Removed L0s state information throughout manual. March 2004 001 Initial relea[...]

  • Page 11

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 11 Introduction Introduction 1 The Intel ® 41210 S erial to Parallel P CI Brid ge (also cal led the 4 1210 Bridge or th e 41210) integrates two PCI Exp ress*-to-PCI/PCI-X bridg es. Each bridge follows the PCI-to-PCI B ridge programming model. The PCI Express* port is compatible[...]

  • Page 12

    12 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Introduction • Up to two downstream delayed (memory read, I/O read/write and configuration read/write) transactions • T unable inbound read prefetch algorithm f o r PCI MRM/MRL commands • Device hidin g support f or secondary PCI devices • Secondary bu s private memory [...]

  • Page 13

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 13 Signal Description Signal Description 2 The “#” symbol at the en d of a signal name indicat es that the active (asserted) state occurs when the signal is at a low voltag e level. When “#” is not pres ent after the signal name , the sign al is asserted when at the high[...]

  • Page 14

    14 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Signal Descri ption T able 1. ODT Signals A_ACK64# B_AC K64# A_AD[63:32] B_AD[63:32] A_CBE#[7:4] B_CBE#[ 7:4] A_DEVSEL# B_DE VSEL# A_FRAME # B_FRAM E# A_GNT#[5:0] B_GNT#[5:0] A_IRDY# B_IRDY# A_P AR B_P AR A_P AR64 B_P AR64 A_PERR# B_PE RR# A_LOCK# B_LOCK# A_REQ#[5:0] B_REQ#[5:0[...]

  • Page 15

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 15 Signal Description 2.2 PCI Express* Interface T able 2. PCI Exp ress* Int erface P ins Signal I/O Description REFCLKp/ REFCLKn I PCI Express* R efe renc e Cl ock s: 100 MHz differential clock pair PET p[7 :0]/ PETn[7:0] O PCI Express* Serial Data T ransmit: PCI Express* diffe[...]

  • Page 16

    16 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Signal Descri ption 2.3 PC I Bus Interface (T wo Inst ances) Each interface is marked by either the letter “A ” or “B” to signify the interf ace. For example, A_AD refers to th e AD bus on PCI bus A, and B_AD refers to the AD bus on PCI bus B. For p in names described i[...]

  • Page 17

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 17 Signal Description A_PERR# B_PERR# I/O Parity Error: PERR# is driven by an external PCI device when it receives data that has a p arity error . PERR# is drive n by the 41210 in the following cases: • when the 41210, as an initiator , detects a parity error during a read tra[...]

  • Page 18

    18 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Signal Descri ption 2.4 PC I Bus Interface 64-Bit Ext ension (T wo Interfaces) 2.5 PC I Bus Interface Clocks and , Reset and Power Managemen t (T wo In terfaces) T able 4. PCI I nterface Pins: 64-Bit Exte nsions Signal I/O Description A_AD[63:32] B_AD[63:32] I/O PCI Address/Dat[...]

  • Page 19

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 19 Signal Description 2.6 Interrupt Interface (T wo Interfaces) This section lists the interrupt interface signals. There are two sets of interrupt signals for the standa rd INT A–IN TD PCI signals. T able 6. Interrup t Interfac e Pins Signal I/O Descriptio n A_INT A# A_IN TB#[...]

  • Page 20

    20 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Signal Descri ption 2.7 Reset Strap s The following sign als are used fo r static configura tion. Th ese signals are all sampled on the rising edge of PERST# . T able 7. R eset S trap Pins Signal I/O Description A_133EN B_133EN I PCI-X 133 MHz Enable: The 133EN pin, when high, [...]

  • Page 21

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 21 Signal Description 2.8 SMBus Interface T able 8. SMBus Interface Pins Signal I/O Descriptio n SMBCLK I/OD SMBus Clock: This signal must be p ulled to 3.3 V through an 8.2 K Ω resistor . SMBDA T I/OD SMBu s Dat a: This signal must be pulled to 3.3 V through an 8.2 K Ω resi[...]

  • Page 22

    22 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Signal Descri ption 2.9 Mi scellane ous Pins T able 9 . Miscellaneous Pins Signal I/O Description CFG RST # O Configur a tion Res e t : This signal is asserted low when ever t he bridge goes through a fundemen tal reset (PERST# , RS TIN#, or P CI Express Res et). This signal sh[...]

  • Page 23

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 23 Signal Description 2.10 V o lt age Pins § § T abl e 10. Miscellaneous Pins Signal Number Description RCOMP 1 Analog Compensati on Pin: RCOMP is the analog compensation pin for PCI. Pull down to ground through a 100 Ω ±1% resistor . VCC 36 1.5 V Core V oltage: 1.5 V ± 5%[...]

  • Page 24

    24 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Signal Descri ption THIS P A GE INTEN TI ONALL Y LEFT B LANK[...]

  • Page 25

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 25 PCI-X In te rface PCI-X Int er face 3 This section deals with the specifics of the ope r at ion and transaction flow details of the PCI interfaces. 3.1 Initializatio n The Intel ® 41210 S erial to Parallel PCI Brid ge (also called the 4 1210 Bri dge or th e 41210) is the sou[...]

  • Page 26

    26 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual PCI-X Int erface In summary: • A_RST# and B_RST# are output s from the 41210 . • PCI clocks are actively d riven out from the 41210. • The 41210 d rives X_AD[31 :0], X_BE[ 3:0], and X_P AR low du ring PCI bus reset. • The 41210 d rives X_REQ64# l ow during reset . 3.2 T[...]

  • Page 27

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 27 PCI-X In te rface 3.2.2 PCI- X Mode Ta b l e 1 4 lists the transactions that t he 41 210 supports when th e PCI interface is in the PCI-X mode. As a master , the 41210 supp orts the memory write block comma nd for writes that are multip les o f cache-line. 3.2.3 Read T ransac[...]

  • Page 28

    28 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual PCI-X Int erface 3.2.3 .2 D elayed All memory read transactions are delayed read transactions. When the 412 10 accepts a delayed read request, it samples the add ress, command, and address parity . This information is entered into the delayed transaction queue. When the 41210 i[...]

  • Page 29

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 29 PCI-X In te rface 3.2.5 LOCK Cycl es A lock is established when all the following conditions are true: • A PCI Express* device initiates a Memory Read Lock (MRdLk) request to read from a tar get PCI device. • LOCK# is asserted on the PC I bus. • The tar get PCI devi ce [...]

  • Page 30

    30 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual PCI-X Int erface 3.2.6 Decodi ng In the PCI mode, the 4 1210 s uppo rt s only the linear i ncrement address mode for bu rst i ng memory transfers (indicated w hen the lowest two address bits are equa l to 0). When either of these address bits is non-zero, the 4121 0 disconnects[...]

  • Page 31

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 31 PCI-X In te rface of reordering allowed. Retry is not considered an error co ndition, so ther e is no error logging or report ing don e on a retry . • The 41210 terminates a tran saction with retry to an initiator when o ne of the following conditions is met: — The 41210 [...]

  • Page 32

    32 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual PCI-X Int erface 3.2.7.2 PCI-X Mode T ransaction T e rmination • Initiator Disconnect or Satisfactio n of Byte Count As a PCI-X mast er , the 41210 us es normal terminatio n (initiat or dis connect or satisfaction of byte count) if DEVSE L# is returned by th e target within s[...]

  • Page 33

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 33 PCI-X In te rface • T ar get T erminations Initiated by the 41210 The 41210 r esponds with a retry t o PCI-X when one of the followi ng condi tions i s met: — A memory r ead transaction occurs and th e 4121 0 delayed transaction queue is full. — A LOCK transaction is es[...]

  • Page 34

    34 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual PCI-X Int erface 3.3 PC I-X Protocol Specifics 3.3.1 Attri bu tes Ta b l e 1 6 describ es h ow the 41210 fills in attribute fields where the PCI -to-PCI Bridg e Specification , Revision 1 .1 a l l ow s some implementation flex ibility . 3.3.2 4 GB and 4 K Page Crossover The PCI[...]

  • Page 35

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 35 PCI-X In te rface 3.3.4 S plit T ran sactions • Completer attributes are given in Ta b l e 1 7 . • Unexpected Split Comp letio ns The 41210 assert s DEVSE L# and discard s the data when th e Requester ID match es the bridge but the ta g does no t match that o f any outsta[...]

  • Page 36

    36 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual PCI-X Int erface For controlling the priority level , there is one bit for each of the PCI REQ# inputs and one bi t for the internal request input . Bit[7] in the control register is for the bridge, bit[5] is for REQ[5]#, bit[4] is for REQ[4]#, and so on. A value of 1 in a bit [...]

  • Page 37

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 37 Power Man a gement Power Management 4 4.1 Hardware-Controlled Active St ate Power Management PCI Expr ess* defines a hardware- i nitiated power manag ement of the PC I Express* Link called active state power management. Under hardware cont rol, the link can be put in to a low[...]

  • Page 38

    38 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Power Man a gement 4.4 Intel ® 41210 Se rial to Parallel PCI Bridge Devic e Powe r Manage men t Each bridge segment supp orts PCI-PM 1.1 device power m anagement states D0, D 3hot, and D3cold. Each function , when programmed to the D3hot state, behaves as follows: • The func[...]

  • Page 39

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 39 Power Man a gement T o support the PCI Express* p ower-managemen t event-signaling p rotocol, the 412 10 suppo rts the follow ing m e ssages: • PME_T urn_Of f • PME_TO_ACK PME_T urn_Of f is used t o turn of f PME generation from all PCI Express * devices before th e syste[...]

  • Page 40

    40 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Power Man a gement THIS P A GE INTEN TI ONALL Y LEFT B LANK[...]

  • Page 41

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 41 Addressing Addressing 5 5.1 Addressable Sp aces within the Int el ® 41210 Serial to Parallel PCI Bridge Befo re di s cus sing all the addr essi n g/c onfi gu rat ion as pect s of t he In t el ® 41210 Seri al to Par allel PCI Bridge (also called the 41210 Bridge or th e 4121[...]

  • Page 42

    42 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Addressing 5.2 Sec ondary PCI Devices Devices on the secondary PCI bus can b e co nfigu red as pr ivate d evices a nd h idden fr om BIOS and host software. Devices ar e hidden by inhi biting the assertion of the IDSEL input of the device during configurati on cycle s. This feat[...]

  • Page 43

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 43 Addressing The extended add ress bits used to acces s the config uration r egion above 25 6 B are all 0s when the access mechanism com p atible with the PCI-to-PCI Bridge Specification , Revisi on 1.1 is used, or when accessing devices on PCI. Note that 4121 0, wh en it trans[...]

  • Page 44

    44 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Addressing • T ype 1-to- T yp e 1 Forw a rdi ng : The 41210 pa sses a T ype 1 PCI Express * configuration cycl e as a T ype 1 configur ation cycle on PCI when it is intended for a device at tached to a b us below the bridg e and beyond th e bus directly attached to the s econ[...]

  • Page 45

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 45 Addressing Instead of hav ing a s econ dary IDSEL# p in, the 4 1210 reserves a device number of 0 for itself. The 41210 claims a T ype 0 con figuration trans act ion fr om PCI-X when the Upstream C o nfiguration Enable bit is set in the Bridge Initializatio n R egister ( “O[...]

  • Page 46

    46 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Addressing The base register consists of an 8 -bit field at configur ati on address 1Ch, and a 1 6-bit field at address 30 h. The top four bits (bits[7:4 ] of address 1Ch) of the 8- bit field define b its[15:12 ] of the I/O base add ress. The bo tt om four bits ( bits[3:0]) rea[...]

  • Page 47

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 47 Addressing 5.5 Memory Sp ace Access Mechan ism The 41210 s upports 6 4 bits of memory ad dressing on both inter faces. T wo memory windows can be setup for forwarding memo ry transa ct ions from PCI Express*-t o- PCI. These windows ar e defined as par t of the standard PCI-to[...]

  • Page 48

    48 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Addressing 5.5.1 Memory-M apped I/O Window Softwa re us es the mem ory-m app e d I/O wind ow to map all non-p refet ch able (in other words, reads that have side ef fects, such as reads to FIFOs, or “read -to-clear” status registers) me mory space into PCI memor y space. Th[...]

  • Page 49

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 49 Addressing 5.5.2 Pr efetc h able Memory Wi ndow The prefetchable memo ry base and address reg ist ers, alon g with th eir upper 3 2-bit coun terparts, define an additional ad dress rang e that the 41210 uses to forward accesses. Software map s the prefetchable PCI memory spac[...]

  • Page 50

    50 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Addressing When this bit is cleared, the 41210 forwards transactions ad dressing the VGA frame b uffer memory and VGA I/O registers from PCI Express* to PCI when the defined memory and I/O address ranges enable forwarding. When cleared, accesses to the VGA frame buf fer memory [...]

  • Page 51

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 51 Transac tion Ordering T ransaction Ordering 6 The Intel ® 41210 S erial to Parallel PCI Brid ge (called her eafter the 41210 Bridg e or 41210) follows t he producer -consumer model of a standard PCI Expres s*-to-PCI bri dge. Base d on th is model, the 4 1210 implements a s e[...]

  • Page 52

    52 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Transaction Or d erin g 6.2 Downst ream T ransactio n Ordering Ta b l e 2 2 lists th e combined set of ordering rules in the downstream path of the 41210. 6.3 Relaxed Ordering/N o-Snoop Suppo rt The 41210 fo rwards the PCI Ex press*/PCI-X rel axed ord ering and n o-snoop attrib[...]

  • Page 53

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 53 Interrupt Suppor t Interrupt Support 7 The Intel ® 41210 S erial to Parallel PCI Brid ge (called her eafter the 41210 Bridg e or 41210) can generate an i n- band i nterru pt request on PCI Expres s * fo r bo ot devi ces and for sy st ems that do not support Mes sage Signaled[...]

  • Page 54

    54 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Interrupt Suppo rt 7.2 I nterru pt Rout ing for Devices behin d a Bridge Given t he legacy i nterrup t shari ng sch eme shown in Ta b l e 2 3 , to get the best legacy interrupt performance (by reducing interru pt sharing), adap t er boar ds must select the appr opriate INT A#?[...]

  • Page 55

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 55 System Management Bus Interface System Management Bus Interface 8 The SMBus interface allows the Intel ® 41210 Serial to Parallel PCI Bridge (called her eafter the 41210 Br i dge or 41 210) to serve as a s lave device res iding on the SMBus for sys tem managemen t functions [...]

  • Page 56

    56 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual System Management Bus Interface 8.1 SMB us Commands The 41210 s upports six SMBus co mmands: Sequencing these commands in i tia tes accesses to the internal config uration and memory registers. For high reliability , the 41210 also supports the optional packet-error-checking fe[...]

  • Page 57

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 57 System Management Bus Interface 8.2 Initialization Seq uence All configuration read and writes are accomp li shed through SMBus write(s ) followed by an SMBus read (for a r ead co mmand ). For con figur at ion acces s, the SMBu s write sequence is used to initialize the follo[...]

  • Page 58

    58 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual System Management Bus Interface Figure 6. DWor d Configuration Read Protocol (SMBus Block Write /Block Read, PEC Enabled) Figure 7. DWord Configur ation Read Protocol (SMBus W ord Write/Word Re ad, PEC Enabled) B3187-01 W Cmd = 11010010 S 11X0_XXX W A Cmd = 11010010 A Byte Coun[...]

  • Page 59

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 59 System Management Bus Interface Figure 8. DWord C onfiguration Read Protoc ol (SMBus Block Write/Block Read, PEC Disabled) Figure 9. DWord Con figuration Read Pr oto col (SM B us Wor d Wr i te /Wo rd R ea d, PE C Di sa b led ) B3189-01 W Cmd = 11000010 S 11X0_XXX W A Cmd = 11[...]

  • Page 60

    60 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual System Management Bus Interface 8.2.2 Configuration Writes Configuration writes are acc omplished throu gh a seri es of SMBus writes. As with reads, a write sequence is used first to initialize the bus number , device, function, and register number for the configuration access.[...]

  • Page 61

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 61 System Management Bus Interface 8.3 Error Handling The SMBus slave interface handles two types of errors: internal an d PEC. Internal errors can occur when the target function is busy servicing a request from the PCI Express* interface. The SMBus un it may time-ou t these tra[...]

  • Page 62

    62 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual System Management Bus Interface 8.4 SMB us Interface Reset The master has two ways to reset the slave in terface state machin e in the 41210: • The master holds SCL K low fo r 25 ms cum ulative. “Cumula tive” in this case means that all the “low time” for SCLK is coun[...]

  • Page 63

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 63 Local Initialization Local Initialization 9 The Intel ® 41210 S erial to Parallel PCI Brid ge (called her eafter the 41210 Bridg e or 412 10) includes device-specific regis ters that allow for co ntr ol of the b ridges’ s behavior , both int ernally and externally . Exampl[...]

  • Page 64

    64 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Local Initialization THIS P A GE INTEN TI ONALL Y LEFT B LANK[...]

  • Page 65

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 65 Clock and Reset Clock and Reset 10 10.1 Clocking The Intel ® 41210 S erial to Parallel PCI Bridge ( cal led hereafter the 412 10 Bridge or the 41210) always uses the PCI Expr es s* REFCLK as its primary clock input and drives the PCI clock outputs . The clock d omains are sh[...]

  • Page 66

    66 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Clock and Reset 10.2.1 PERST# R eset Mechanism All the voltage sources in the sy stem are tracked by a s ystem co mponent that as serts the PERST# signal only after all the voltages have been st ab le for some predetermin ed time. The 41210 receives the PERST# signal as a n asy[...]

  • Page 67

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 67 Clock and Reset 10.2.4 Softw are PCI Reset (SBR—Sec ondary Bus Reset) Commonly referred to as the Secondary Bus Reset (SBR), the software PCI reset is initiated by a write to the bridge control register and resets only the particular PCI segment. This reset can be used for [...]

  • Page 68

    68 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Clock and Reset THIS P A GE INTEN TI ONALL Y LEFT B LANK[...]

  • Page 69

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 69 Error Hand ling Error Handling 11 For each interface, the I ntel ® 41210 Serial to Parallel PCI Bridge (called hereafter the 41210 Bridge or 41210) implements the specifi ed error-l ogg ing and escalation actions a s per the interface rules. For example, errors encountered o[...]

  • Page 70

    70 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Error Hand ling 11 . 2 . 1 E r r o r Ty p e s PCI errors are class ified into two categories: fatal and non- fatal: • Fatal errors are those that have the potential to cause data corruption. Software must be careful to contain and escalate these error s (when needed). • Non[...]

  • Page 71

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 71 Error Hand ling 1 1.2.2.2 Sp lit T ermination on PCI- X Interf ace A split-terminatio n error translation o ccurs when a completion-requ ired transaction rec eives a “split termination” resp o nse when originally mastered on the PCI-X bus, and a “split completion” err[...]

  • Page 72

    72 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Error Hand ling 1 1.2.2 .3 Split T ermination on PCI Express* Interf ace Ta b l e 3 1 shows the split-comp letion errors rece i ved on the PCI Express* interf ace and how they translate to PCI-X. § § T able 31. Completion-Status T ransl ation for PCI Exp ress* Split-Compl eti[...]

  • Page 73

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 73 Register Descriptio n Register Description 12 This chapter describes the registers of the Intel ® 41210 Ser ial to Paral le l PCI Bri dge . 12.1 Register Nome nclature and Acce ss Attribut es Ta b l e 3 2 describes the nomenclature used for de s cribi ng b it attribut es thr[...]

  • Page 74

    74 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2 Con figuration Reg isters The bridge conf i guration space fo llows the standard PCI E xpress*-to-PCI Bridge configur ation space format. Refer to t he PCI Expr ess*-to-PCI Bridge Specification , Rev ision 1.0a for de tail s on the format. Each 4121[...]

  • Page 75

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 75 Register Descriptio n Figure 12. Intel ® 41210 Ser ial to Parallel PCI Bridge Capabilities 0xFFF E x t e n d e d C o n f i g u r a t i o n S p a c e Power B udgeting Capab i lity 0x300 B3174-02 PCI Express Advance d Error Reporting Capab i lity PCI-X Capability PCI-PM 1.1 Ca[...]

  • Page 76

    76 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption T able 33. Legacy Configur ation Sp ace Byte Offset Byte Offset DID VID 00h Reserved 80h PSTS PCICMD 04h 84h Class Code (CC) REVID 08h 88h Reserved HEAD TYP PML T CL S 0Ch 8Ch Reserved 10h 90h 14h 94h SML T BNUM 18h 98h SSTS IOBL 1Ch 9Ch MBL 20h A0h PMBL[...]

  • Page 77

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 77 Register Descriptio n T abl e 34. PCI Express* Extended Conf igu ration Sp ace Register Byte Offset EXP AERR_C APID 100 ERRUNC_STS 104 ERRUNC_MSK 108 ERRUNC_SEV 10C ERRCOR_STS 1 10 ERRCOR_MSK 1 14 ADVERR _CTL 1 18 HDR_LOG 11 C 120 124 128 Reserved PCIXERRUNC_STS 12C PCIXERRUN[...]

  • Page 78

    78 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.1 Off s et 00h: ID —I de ntif ie r s Contains the vendor and device identifiers for software. 12.2.2 Offset 04h: PCICMD—Command Register This register controls ho w the device beha ves on the primary inter face (PCI Express* ). As this component[...]

  • Page 79

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 79 Register Descriptio n 12.2.3 Offset 06h: PSTS—Primary Device St atus For the writable bits in this register, writing a 1 clears the bit. W riting a 0 to the bit has no effect. 2R W 0 b Bus Master En able (BME): This bit controls the ability of the 41210 to issue memory and [...]

  • Page 80

    80 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.4 Offset 08h: REVID—Revision ID This register is the Revi sion ID Regis ter . 11 R W C 0 b Signal ed T arget A bort (ST A): This bit is set when a completion packet with Completer Abort (CA) s tatus is gen erated on PCI Express*. 0 = No error. 1 =[...]

  • Page 81

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 81 Register Descriptio n 12.2.5 Offset 09h: CC—Class Code This register co ntains the class code, s ub-cl ass c ode, and programming inter face for the device. 12.2.6 Offset 0Ch: CLS—Cache-Line Size This register indicates the cache- l ine size of the system. 12.2.7 Offset 0[...]

  • Page 82

    82 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.9 Offset 18h: BNUM—Bus Num bers This register contains the primary , secondary , and maximum subordinate bu s number regi sters. 12.2.10 Offset 1Bh: SML T—Secondary Master Latency T imer This timer controls the amount of time that the 41210 cont[...]

  • Page 83

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 83 Register Descriptio n 12.2.1 1 Offset 1Ch: IOBL—I/O Base and Limit This register defines the base and limit, alig ned to a 4 KB boundary , o f the I/O area of the bridge. Accesses from PCI Expr es s* that are within the rang es specified in t his register are sent to P CI w[...]

  • Page 84

    84 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.12 Offset 1Eh: SS TS—Secondary S t atus For the writable bits in this register, w riting 1 to the bit clears the bit. W riting 0 to the bit has no effect . T able 46. Offset 1E h: S S TS—Secondary St atus Bits T ype Reset Description 15 RWC 0b D[...]

  • Page 85

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 85 Register Descriptio n 12.2.13 Offset 20h: MBL—Memory Base and Limit Defines the base and limit, alig ned to a 1 MB bound ary , of the non- prefetchable memory area of the bridge. Accesses fr om PCI Express* that are with in the r anges specified in this reg ister are sent t[...]

  • Page 86

    86 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.14 Offset 24h: PMBL—Prefetchable Memory Base and Limit This regist er def ines the bas e and limit, aligned to a 1 MB bou ndary , of the prefetchab l e memory area of the bridg e. Accesses from PCI Express* that are within the ranges speci fied in[...]

  • Page 87

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 87 Register Descriptio n 12.2.16 Offset 2Ch: PMLU32—Prefetchable Memory Limit Upper 32 Bit s This regist er defines the upper 32 bits of the prefetchable ad dress base reg i ster . 12.2.17 Offset 30h: IOBLU16—I/O Base and Limit Upper 16 Bit s Since I/O is limited to 64 KB, t[...]

  • Page 88

    88 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.20 Offset 3Eh: BCTRL—Bridge Control This regis ter provid es extensions t o the Com mand Reg i ster ( “Offset 04 h: PCICMD—Command Register” on page 78 ) that are specific to a bridge. The Bridge C ontrol Register p rovides many of the same [...]

  • Page 89

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 89 Register Descriptio n 5R W 0 b Master A bort Mode ( MAM): This bit controls the bridge’s behavior when a ma ster-abort (or unsupported request) oc curs on either interface. This bit does not affect the behavior when the bridge forwards a UR completion from PCI Express* to m[...]

  • Page 90

    90 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.21 Offset 40h: BCNF—Bridge Configur ation Register The bridge co ntrol bits speci fic to the Intel ® 41210 Serial to Parallel PCI Bridge are listed in Ta b l e 5 5 . T able 55. Offset 40h: BCNF—B ridge Configuration Re gister Bits T ype Reset D[...]

  • Page 91

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 91 Register Descriptio n 12.2.22 Offset 42h: MTT—Mult i-T ransaction T imer This register controls the amou nt of time that the 41210 arbiter allows for a PCI initiator to perform multiple back-to-back transactions on the PCI bus. The number of clocks programmed in the MTT rep[...]

  • Page 92

    92 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.26 Offset 46h: EXP_CAP—PCI Express * Cap ability This register s tor es the v ersion n umb er o f th e capability item an d o t her bas e inf ormation co ntained in the capability structu re. 12.2.27 Offset 48h : EXP_DCAP—PCI Express* Device Cap[...]

  • Page 93

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 93 Register Descriptio n 12.2.28 Offset 4Ch: EXP_DCTL—PCI Express* Device Control Register This regist er stores co mmand bits that cont rol the 41210 behavio r on PCI Exp ress*. T able 62. Of fset 4Ch: E XP_DCTL— PCI Expr ess* Device Co ntrol Regi ster (Sheet 1 of 2 ) Bits [...]

  • Page 94

    94 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.29 Offset 4Eh: EXP_DSTS—PCI Express* Devi ce S t atus Register This register s t ores information on the PCI Expr es s* device status. 12.2.30 Offset 50h: EXP_LCAP—PCI Express* Link Cap abilities Regi ster 2R W 0 b Report Fatal Errors: When this[...]

  • Page 95

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 95 Register Descriptio n 12.2.31 Offset 54h: EXP_LCTL—PCI Express* Link Control Register 14:12 RO 1 10b L0s Exit Laten cy: The value in t hese bits is determined by t he setting of the Common Clock Configuration bit (bit[6]) in the Link Cont rol Register ( Offset 54h: EXP_LCTL[...]

  • Page 96

    96 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.32 Offset 56h: EXP_LSTS—PCI Express* Link St atus Register 12.2.33 Offset 5Ch: MSI_CAPID—PCI Express* MSI Cap ability Identifier Note: MSI genera tion is us ed for internal de bugging purposes and does not occur in n ormal oper ation. 12.2.34 Of[...]

  • Page 97

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 97 Register Descriptio n 12.2.35 Offset 5Eh: MSI_MC—PCI Expre ss* MSI Message Control 12.2.36 Offset 60h: MSI_MA—PCI Expres s* MSI Message Address 12.2.37 Offset 68h: MSI_MD—PCI Expres s* MSI Message Dat a 12.2.38 Offset 6Ch: PM_CAPID—Power Management Cap abilities Ident[...]

  • Page 98

    98 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.39 Offset 6Dh: PM_NXTP—Power Management Next It em Pointer 12.2.40 Offset 6Eh: PM_P MC—Power Management Cap abilities T able 73. Offset 6Dh: PM_NXTP—Power Management Next Item Pointer Bits T ype Reset Description 7:0 RO D8h Next Pointer: This [...]

  • Page 99

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 99 Register Descriptio n 12.2.41 Offset 70h: PM_PMCSR—Power Management Control/St atus Register 12.2.42 Offset 72h: PM_BSE—Power Management Bri dge Support Extensions 12.2.43 Offset 73h: PM_DA T A—Power Management Dat a Field T able 75. Of fset 70h : PM_PMC SR—Pow er Man[...]

  • Page 100

    100 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.44 Offset D8h: PX_CAPID—PCI-X Cap abilities Identifi er This register identifies this item in the capabilities list as a PC I-X register set. 12.2.45 Offset D9h: PX_NXTP—PCI- X Next Item Pointer This register indicates where the next item in th[...]

  • Page 101

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 101 Register Descriptio n 12.2.46 Offset DAh: PX_SSTS— PCI-X Secondary St atus This is the PCI-X status register for t he bridge s econdary side. T able 80. Of fset DAh: P X_SSTS —PCI-X Seconda ry St at us Bits T ype Reset Description 15:9 RO 00h Res erved 8:6 RO See T able [...]

  • Page 102

    102 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.47 Offset DCh: PX_BSTS—PCI-X Bridge St atus This register iden tifies PCI-X status register for the bridge primary side. 12.2.48 Offset E0h: PX _USTC —PCI-X Up stream S plit T ransaction Contro l This register controls the behavior of the 41210[...]

  • Page 103

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 103 Register Descriptio n 12.2.49 Offset E4h: PX_DSTC—PCI-X Downst ream S p lit T ransaction Control This register controls the behavior of the 41210 buf fers for forwarding split transactions from PCI Express* to the secondary bus. T able 83. Of fset E4h : PX_DST C—PCI-X Do[...]

  • Page 104

    104 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.50 Offset FCh: BINIT—Bridge Initialization Register T able 84. Offset FCh: BINIT—Br idge Initialization Register Bits T ype Reset Description 31:5 RO 000 0000h Reserved 4R W S 0 b Opa que Memor y Win dow En able: When this bit is set, t he Inte[...]

  • Page 105

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 105 Register Descriptio n 12.2.51 Offset 100h: EXP AERR_CA PID—PCI Expres s* Advanced Error Cap ability Identifier This register stores the PCI Express* extended capability ID value. 12.2.52 Offset 104h: ERRUNC_ST S—PCI Express* Uncorrect able Error St atus Register This reg[...]

  • Page 106

    106 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.53 Offset 108h: ERRUNC_MSK—PCI Ex p ress* Uncorrect able Error Mask This regi ster con trols the re porting of indiv i dual uncor r ectable errors by device to the host bridge via a PCI Express * error message. This r egister also controls the lo[...]

  • Page 107

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 107 Register Descriptio n 12.2.54 Offset 10Ch: ERRUNC_SEV— PCI Express* Uncorrect able Error S everity This register co ntrols whether an individual uncorr ectable error is repo rted as a fatal erro r. An uncorrectable error is reported as fatal when the corresponding error bi[...]

  • Page 108

    108 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.55 Offset 1 10h: ERRCOR_STS—PCI E xp ress* Corr ec table Error St atus This regis ter reports the er ror st atus of individual co rrectable error so urces on a PCI Exp ress* device. An indi vidual error status bit set to 1 indi cates that a parti[...]

  • Page 109

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 109 Register Descriptio n 12.2.56 Offset 1 14h: ERRCOR_MSK— PCI Express* Correct able Error Mask This register co ntrols the reporting o f indivi dual correctab le errors via ERR_CO R message. A masked error (respective bit set in mask re gister) i s not r eported t o the hos [...]

  • Page 110

    110 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.58 Offset 1 1C–12Bh: HDR_LOG—PCI Express* T r ansaction Header Log This register is t he transaction header log for PCI Ex press* errors. T able 92. Offset 1 1C–12Bh : HDR_LO G—PCI Ex press* T ran saction He ader Log Bits T ype Reset Descri[...]

  • Page 111

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 111 Register Descriptio n 12.2.59 Offset 12Ch: PCIXERRUNC_STS—Uncorrect able PCI-X S t atus Regist er T able 93. Offset 12Ch: PCIX ERRUNC_STS— Uncorr ectable PCI-X St atus Regis ter (Sheet 1 of 2) Bits T ype Reset Description 15:14 RsvdZ 00b Reserved Zero: Software must writ[...]

  • Page 112

    112 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 2R W C S 0 b PCI-X Detected T arget Abort (optional in specificati on): The 41210 sets this bit when i t is the mast er of a reques t transaction on the PCI bus and it receives a target abor t. The 41210 logs t he header for that transac tion. This bit [...]

  • Page 113

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 113 Register Descriptio n 12.2.60 Offset 130h: PCIXERRUNC_MSK—Uncorrect able PCI-X Error Mask Regist er This regist er mask s the repo rting of PCI-X un correctable erro rs. There is one mask bit per error . Note that the s tatus bits ar e set in th e status reg ister regardle[...]

  • Page 114

    114 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 2R W C S 0 b P CI -X Detected T arget Abort Mask: (optional in specifi c a t ion) 0 = Not masked 1 = Masked 1R W C S 0 b P CI -X Detected Split Completion Master Ab ort Mask : 0 = Not masked 1 = Masked 0R W C S 0 b P CI -X Detected Split Completion T ar[...]

  • Page 115

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 115 Register Descriptio n 12.2.61 Offset 134h: PCIXERRUNC_SEV—Uncorrect able PCI-X Error Seve rity Register This regi ster con trols th e severity of the rep o rting of PC I-X unco rrectable errors. There is one mask bit per error . When a bit is set to 1, the corresponding er[...]

  • Page 116

    116 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.62 Offset 13 8h: PCIXERRUNC_PTR—Un c orrectable PCI- X Erro r Pointe r This register points t o the first error t hat occurred. This register is re -armed when the erro r status register corresponding to the error indicated by this reg ister is c[...]

  • Page 117

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 117 Register Descriptio n 12.2.63 Offset 13C–14Bh: PCIXHDR_LOG—Uncorrect able PCI-X Error T ransaction Header Log This register is the transaction h ead er log for PC I errors. The log in this regis ter correspond s to one of the status bits s et in the PCI-X un corr ectable[...]

  • Page 118

    118 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.65 Offset 170h: SS R—Strap S tatus Register This register ind i cates the status of various reset strap s in the 41210. T able 99. Offset 170h: SSR—Strap St atu s Register Bits T ype Reset Description 15 RO S t rap Configur ation Retry St rap: [...]

  • Page 119

    Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 119 Register Descriptio n 12.2.66 Offset 178h: PREFCTRL—Prefetch Control Register The followi ng regist er contains pref etch parameters for PCI operation. T able 100. Offset 17 8h: PREF CTRL—Prefet ch Control Register Bits T ype Reset Description 63:60 Rs vdP 0000b P reserv[...]

  • Page 120

    120 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.67 Offset 300h: PWRBG T_CAPID—Po wer Bud geting Enhanced Capability Header This register defines the capability identifier . 12.2.68 Offset 30 4h: PWRBG T_DSEL— P ower Budgeting Dat a Select Register 12.2.69 Offset 30 8h: PWRBG T_DA T A—Power[...]