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Intel 80L188EA manual

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Table of contents for the manual

  • Page 1

    * Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products.[...]

  • Page 2

    80C186EA/80C188EA, 80L186EA/80L188EA 80C186EA/80C188EA AND 80L186EA/80L188EA 16-Bit High Integration Embedded Processor CONTENTS PAGE INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 80C186EA CORE ARCHITECTURE ÀÀÀÀÀÀÀ 4 Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 Clock Generator ÀÀÀÀÀÀ[...]

  • Page 3

    80C186EA/80C188EA, 80L186EA/80L188EA NOTE: Pin names in parentheses apply to the 80C186EA/80L188EA Figure 1. 80C186EA/80C188EA Block Diagram 272432 – 2 3 3[...]

  • Page 4

    80C186EA/80C188EA, 80L186EA/80L188EA INTRODUCTION Unless specifically noted, all references to the 80C186EA apply to the 80C188EA, 80L186EA, and 80L188EA. References to pins that differ between the 80C186EA/80L186EA and the 80C188EA/ 80L188EA are given in parentheses. The ‘‘L’’ in the part number denotes low voltage operation. Physi- cally [...]

  • Page 5

    80C186EA/80C188EA, 80L186EA/80L188EA 272432 – 3 (A) Crystal Connection NOTE: The L 1 C 1 network is only required when using a third-overtone crystal. 272432 – 4 (B) Clock Connection Figure 2. Clock Configurations 80C186EA PERIPHERAL ARCHITECTURE The 80C186EA has integrated several common sys- tem peripherals with a CPU core to create a com- pa[...]

  • Page 6

    80C186EA/80C188EA, 80L186EA/80L188EA PCB Function Offset 00H Reserved 02H Reserved 04H Reserved 06H Reserved 08H Reserved 0AH Reserved 0CH Reserved 0EH Reserved 10H Reserved 12H Reserved 14H Reserved 16H Reserved 18H Reserved 1AH Reserved 1CH Reserved 1EH Reserved 20H Reserved 22H End of Interrupt 24H Poll 26H Poll Status 28H Interrupt Mask 2AH Pri[...]

  • Page 7

    80C186EA/80C188EA, 80L186EA/80L188EA PCB Function Offset 20H Interrupt Vector 22H Specific EOI 24H Reserved 26H Reserved 28H Interrupt Mask 2AH Priority Mask 2C In-Service 2E Interrupt Request 30 Interrupt Status 32 TMR0 Interrupt Control 34 DMA0 Interrupt Control 36 DMA1 Interrupt Control 38 TMR1 Interrupt Control 3A TMR2 Interrupt Control 3C Rese[...]

  • Page 8

    80C186EA/80C188EA, 80L186EA/80L188EA 80C187 Interface (80C186EA Only) The 80C187 Numerics Coprocessor may be used to extend the 80C186EA instruction set to include floating point and advanced integer instructions. Connecting the 80C186EA RESOUT and TEST / BUSY pins to the 80C187 enables Numerics Mode operation. In Numerics Mode, three of the four M[...]

  • Page 9

    80C186EA/80C188EA, 80L186EA/80L188EA PACKAGE INFORMATION This section describes the pins, pinouts, and thermal characteristics for the 80C186EA in the Plastic Leaded Chip Carrier (PLCC) package, Shrink Quad Flat Pack (SQFP), and Quad Flat Pack (QFP) pack- age. For complete package specifications and infor- mation, see the Intel Packaging Outlines a[...]

  • Page 10

    80C186EA/80C188EA, 80L186EA/80L188EA Table 2. Pin Description Nomenclature Symbol Description P Power Pin (Apply a V CC Voltage) G Ground (Connect to V SS ) I Input Only Pin O Output Only Pin I/O Input/Output Pin S(E) Synchronous, Edge Sensitive S(L) Synchronous, Level Sensitive A(E) Asynchronous, Edge Sensitive A(L) Asynchronous, Level Sensitive H[...]

  • Page 11

    80C186EA/80C188EA, 80L186EA/80L188EA Table 3. Pin Descriptions Pin Pin Input Output Description Name Type Type States V CC P POWER connections consist of six pins which must be shorted externally to a V CC board plane. V SS G GROUND connections consist of five pins which must be shorted externally to a V SS board plane. CLKIN I A(E) CLocK INput is [...]

  • Page 12

    80C186EA/80C188EA, 80L186EA/80L188EA Table 3. Pin Descriptions (Continued) Pin Pin Input Output Description Name Type Type States A18:16 O H(Z) These pins provide multiplexed Address during the address phase of the bus cycle. Address bits 16 through 19 are A19/S6 – A16 R(Z) presented on these pins and can be latched using ALE. (A19 – A8) P(X) A[...]

  • Page 13

    80C186EA/80C188EA, 80L186EA/80L188EA Table 3. Pin Descriptions (Continued) Pin Pin Input Output Description Name Type Type States WR/QS1 O H(Z) WRite output signals that data available on the data bus are to be written into the accessed memory or I/O device. In Queue Status R(Z) Mode, QS1 provides queue status information along with QS0. P(1) ARDY [...]

  • Page 14

    80C186EA/80C188EA, 80L186EA/80L188EA Table 3. Pin Descriptions (Continued) Pin Pin Input Output Description Name Type Type States MCS0/PEREQ I/O A(L) H(1) These pins provide a multiplexed function. If enabled, these pins normally comprise a block of Mid-Range Chip MCS1 /ERROR R(1) Select outputs which will go active whenever the address MCS2 P(1) o[...]

  • Page 15

    80C186EA/80C188EA, 80L186EA/80L188EA 80C186EA PINOUT Tables 4 and 5 list the 80C186EA pin names with package location for the 68-pin Plastic Leaded Chip Carrier (PLCC) component. Figure 9 depicts the complete 80C186EA/80L186EA pinout (PLCC pack- age) as viewed from the top side of the component (i.e., contacts facing down). Tables 6 and 7 list the [...]

  • Page 16

    80C186EA/80C188EA, 80L186EA/80L188EA Table 5. PLCC Package Location with Pin Names Location Name 1 AD15 (A15) 2 AD7 3 AD14 (A14) 4 AD6 5 AD13 (A13) 6 AD5 7 AD12 (A12) 8 AD4 9V CC 10 AD11 (A11) 11 AD3 12 AD10 (A10) 13 AD2 14 AD9 (A9) 15 AD1 16 AD8 (A8) 17 AD0 Location Name 18 DRQ0 19 DRQ1 20 T0IN 21 T1IN 22 T0OUT 23 T1OUT 24 RESIN 25 PCS0 26 V SS 27[...]

  • Page 17

    80C186EA/80C188EA, 80L186EA/80L188EA Table 6. QFP (EIAJ) Pin Names with Package Location Address/Data Bus Bus Control Processor Control I/O Name Location Name Location Name Location Name Location AD0 64 ALE/QS0 10 RESIN 55 UCS 45 AD1 66 BHE (RFSH) 7 RESOUT 18 LCS 46 AD2 68 S0 23 CLKIN 16 MCS0/PEREQ 40 AD3 70 S1 22 OSCOUT 17 MCS1/ERROR 41 AD4 74 S2 [...]

  • Page 18

    80C186EA/80C188EA, 80L186EA/80L188EA Table 7. QFP (EIAJ) Package Location with Pin Names Location Name Location Name Location Name Location Name 1 AD15 (A15) 21 S2 41 MCS1/ERROR 61 DRQ0 2V CC 22 S1 42 MCS2 62 V SS 3 A16 23 S0 43 MCS3/NCS 63 N.C. 4 A17 24 V SS 44 V CC 64 AD0 5 A18 25 HLDA 45 UCS 65 AD8 (A8) 6 A19/S6 26 HOLD 46 LCS 66 AD1 7 BHE (RFSH[...]

  • Page 19

    80C186EA/80C188EA, 80L186EA/80L188EA Table 8. SQFP Pin Functions with Package Location AD Bus AD0 1 AD1 3 AD2 6 AD3 8 AD4 12 AD5 14 AD6 16 AD7 18 AD8 (A8) 2 AD9 (A9) 5 AD10 (A10) 7 AD11 (A11) 9 AD12 (A12) 13 AD13 (A13) 15 AD14 (A14) 17 AD15 (A15) 19 A16/S3 21 A17/S4 22 A18/S5 23 A19/S6 24 Bus Control ALE/QS0 29 BHE /(RFSH )2 6 S0 40 S1 39 S2 38 RD [...]

  • Page 20

    80C186EA/80C188EA, 80L186EA/80L188EA 272432 – 7 Figure 7. Shrink Quad Flat Pack (SQFP) Pinout Diagram NOTES: 1. XXXXXXXXD indicates the Intel FPO number. 2. Pin names in parentheses apply to the 80C188EA. PACKAGE THERMAL SPECIFICATIONS The 80C186EA/80L186EA is specified for operation when T C (the case temperature) is within the range of 0 § Ct [...]

  • Page 21

    80C186EA/80C188EA, 80L186EA/80L188EA ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings * Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65 § Ct o a 150 § C Case Temperature under Bias ÀÀÀ b 65 § Ct o a 150 § C Supply Voltage with Respect to V SS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 0.5V to a 6.5V Voltage on Other Pins with Respect t[...]

  • Page 22

    80C186EA/80C188EA, 80L186EA/80L188EA DC SPECIFICATIONS (80C186EA/80C188EA) Symbol Parameter Min Max Units Conditions V CC Supply Voltage 4.5 5.5 V V IL Input Low Voltage for All Pins b 0.5 0.3 V CC V V IH Input High Voltage for All Pins 0.7 V CC V CC a 0.5 V V OL Output Low Voltage 0.45 V I OL e 3 mA (min) V OH Output High Voltage V CC b 0.5 V I OH[...]

  • Page 23

    80C186EA/80C188EA, 80L186EA/80L188EA DC SPECIFICATIONS (80L186EA/80L188EA) Symbol Parameter Min Max Units Conditions V CC Supply Voltage 2.7 5.5 V V IL Input Low Voltage for All Pins b 0.5 0.3 V CC V V IH Input High Voltage for All Pins 0.7 V CC V CC a 0.5 V V OL Output Low Voltage 0.45 V I OL e 1.6 mA (min) V OH Output High Voltage V CC b 0.5 V I [...]

  • Page 24

    80C186EA/80C188EA, 80L186EA/80L188EA I CC VERSUS FREQUENCY AND VOLTAGE The current (I CC ) consumption of the processor is essentially composed of two components; I PD and I CCS . I PD is the quiescent current that represents internal device leakage, and is measured with all inputs or floating outputs at GND or V CC (no clock applied to the device)[...]

  • Page 25

    80C186EA/80C188EA, 80L186EA/80L188EA AC SPECIFICATIONS AC CharacteristicsÐ80C186EA25/80C186EA20/80C186EA13 Symbol Parameter Min Max Min Max Min Max Units Notes INPUT CLOCK 25 MHz (12) 20 MHz 13 MHz T F CLKIN Frequency 0 50 0 40 0 26 MHz 1 T C CLKIN Period 20 % 25 % 38.5 % ns 1 T CH CLKIN High Time 10 % 10 % 12 % ns 1, 2 T CL CLKIN Low Time 10 % 10[...]

  • Page 26

    80C186EA/80C188EA, 80L186EA/80L188EA AC SPECIFICATIONS (Continued) AC CharacteristicsÐ80C186EA25/80C186EA20/80C186EA13 Symbol Parameter Min Max Min Max Min Max Units Notes SYNCHRONOUS INPUTS 25 MHz (12) 20 MHz 13 MHz T CHIS TEST, NMI, INT3:0, 8 10 10 ns 1, 9 T1:0IN, ARDY T CHIH TEST, NMI, INT3:0, 3 3 3 ns 1, 9 T1:0IN, ARDY T CLIS AD15:0 (AD7:0), A[...]

  • Page 27

    80C186EA/80C188EA, 80L186EA/80L188EA AC SPECIFICATIONS AC CharacteristicsÐ80L186EA13/80L186EA8 Symbol Parameter Min Max Min Max Units Notes INPUT CLOCK 13 MHz 8 MHz T F CLKIN Frequency 0 26 0 16 MHz 1 T C CLKIN Period 38.5 % 62.5 % ns 1 T CH CLKIN High Time 12 % 12 % ns 1, 2 T CL CLKIN Low Time 12 % 12 % ns 1, 2 T CR CLKIN Rise Time 1 8 1 8 ns 1, [...]

  • Page 28

    80C186EA/80C188EA, 80L186EA/80L188EA AC SPECIFICATIONS AC CharacteristicsÐ80L186EA13/80L186EA8 Symbol Parameter Min Max Min Max Units Notes SYNCHRONOUS INPUTS 13 MHz 8 MHz T CHIS TEST, NMI, INT3:0, T1:0IN, ARDY 22 22 ns 1, 9 T CHIH TEST, NMI, INT3:0, T1:0IN, ARDY 3 3 ns 1, 9 T CLIS AD15:0 (AD7:0), ARDY, SRDY, DRQ1:0 22 22 ns 1, 10 T CLIH AD15:0 (A[...]

  • Page 29

    80C186EA/80C188EA, 80L186EA/80L188EA AC SPECIFICATIONS (Continued) Relative Timings (80C186EA25/20/13, 80L186EA13/8) Symbol Parameter Min Max Unit Notes RELATIVE TIMINGS T LHLL ALE Rising to ALE Falling T b 15 ns T AVLL Address Valid to ALE Falling (/2 T b 10 ns T PLLL Chip Selects Valid to ALE Falling (/2 T b 10 ns 1 T LLAX Address Hold from ALE F[...]

  • Page 30

    80C186EA/80C188EA, 80L186EA/80L188EA AC TEST CONDITIONS The AC specifications are tested with the 50 pF load shown in Figure 8. See the Derating Curves section to see how timings vary with load capacitance. Specifications are measured at the V CC /2 crossing point, unless otherwise specified. See AC Timing Waveforms, for AC specification definition[...]

  • Page 31

    80C186EA/80C188EA, 80L186EA/80L188EA 272432 – 10 NOTE: 20% V CC k Float k 80% V CC Figure 10. Output Delay and Float Waveform 272432 – 11 NOTE: RESIN measured to CLKIN, not CLKOUT Figure 11. Input Setup and Hold 31 31[...]

  • Page 32

    80C186EA/80C188EA, 80L186EA/80L188EA 272432 – 12 NOTES: 1. T DXDL for write cycle followed by read cycle. 2. Pin names in parentheses apply to tthe 80C188EA. Figure 12. Relative Signal Waveform 32 32[...]

  • Page 33

    80C186EA/80C188EA, 80L186EA/80L188EA DERATING CURVES 272432 – 13 Figure 13. Typical Output Delay Variations Versus Load Capacitance 272432 – 14 Figure 14. Typical Rise and Fall Variations Versus Load Capacitance RESET The processor performs a reset operation any time the RESIN pin is active. The RESIN pin is actually synchronized before it is p[...]

  • Page 34

    80C186EA/80C188EA, 80L186EA/80L188EA Figure 15. Powerup Reset Waveforms 272432 – 15 NOTES: 1. CLKOUT synchronization occurs approximately 1 (/2 CLKIN periods after RESIN is sampled low. 2. Pin names in parentheses apply to the 80C188EA. 34 34[...]

  • Page 35

    80C186EA/80C188EA, 80L186EA/80L188EA Figure 16. Warm Reset Waveforms 272432 – 16 NOTES: 1. CLKOUT resynchronization occurs approximately 1 (/2 CLKIN periods after RESIN is sampled low. If RESIN is sampled low while CLKOUT is transitioning high, then CLKOUT will remain high for two CLKIN periods. If RESIN is sampled low while CLKOUT is transitioni[...]

  • Page 36

    80C186EA/80C188EA, 80L186EA/80L188EA BUS CYCLE WAVEFORMS Figures 17 through 23 present the various bus cycles that are generated by the processor. What is shown in the figure is the relationship of the various bus signals to CLKOUT. These figures along with the information present in AC Specifications allow the user to determine all the critical ti[...]

  • Page 37

    80C186EA/80C188EA, 80L186EA/80L188EA 272432-18 NOTES: 1. During the data phase of the bus cycle, A19/S6 is driven high for a DMA cycle. 2. Pin names in parentheses apply to the 80C188EA. Figure 18. Write Cycle Waveform 37 37[...]

  • Page 38

    80C186EA/80C188EA, 80L186EA/80L188EA 272432 – 19 NOTES: 1. The processor drives these pins to 0 during Idle and Powerdown Modes. 2. Pin names in parentheses apply to the 80C188EA. Figure 19. Halt Cycle Waveform 38 38[...]

  • Page 39

    80C186EA/80C188EA, 80L186EA/80L188EA NOTES: 272432 – 20 1. INTA occurs one clock later in Slave Mode. 2. Pin names in parentheses apply to the 80C188EA. Figure 20. INTA Cycle Waveform 39 39[...]

  • Page 40

    80C186EA/80C188EA, 80L186EA/80L188EA 272432 – 21 NOTE: 1. Pin names in parentheses apply to the 80C188EA. Figure 21. HOLD/HLDA Waveform 40 40[...]

  • Page 41

    80C186EA/80C188EA, 80L186EA/80L188EA 272432 – 22 NOTE: 1. Pin names in parentheses apply to the 80C188EA. Figure 22. DRAM Refresh Cycle During Hold Acknowledge 41 41[...]

  • Page 42

    80C186EA/80C188EA, 80L186EA/80L188EA 272432 – 23 NOTES: 1. Generalized diagram for READ or WRITE. 2. ARDY low by either edge causes a wait state. Only rising ARDY is fully synchronized. 3. SRDY low causes a wait state. SRDY must meet setup and hold times to ensure correct device operation. 4. Either ARDY or SRDY active high will terminate a bus c[...]

  • Page 43

    80C186EA/80C188EA, 80L186EA/80L188EA 80C186EA/80C188EA EXECUTION TIMINGS A determination of program exeuction timing must consider the bus cycles necessary to prefetch in- structions as well as the number of execution unit cycles necessary to execute instructions. The fol- lowing instruction timings represent the minimum execution time in clock cyc[...]

  • Page 44

    80C186EA/80C188EA, 80L186EA/80L188EA INSTRUCTION SET SUMMARY Function Format 80C186EA 80C188EA Comments Clock Clock Cycles Cycles DATA TRANSFER MOV e Move: Register to Register/Memory 1000100w m o dr e g r / m 2/12 2/12 * Register/memory to register 1000101w m o dr e g r / m 2 / 9 2 / 9 Immediate to register/memory 1100011w m o d0 0 0 r / m data da[...]

  • Page 45

    80C186EA/80C188EA, 80L186EA/80L188EA INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EA 80C188EA Comments Clock Clock Cycles Cycles DATA TRANSFER (Continued) SEGMENT e Segment Override: CS 00101110 2 2 SS 00110110 2 2 DS 00111110 2 2 ES 00100110 2 2 ARITHMETIC ADD e Add: Reg/memory with register to either 000000dw m o dr e g r / m 3/10 3/[...]

  • Page 46

    80C186EA/80C188EA, 80L186EA/80L188EA INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EA 80C188EA Comments Clock Clock Cycles Cycles ARITHMETIC (Continued) IMUL e Integer multiply (signed): 1111011w m o d101 r / m Register-Byte 2 5–2 8 2 5–2 8 Register-Word 3 4–3 7 3 4–3 7 Memory-Byte 3 1–3 4 3 2–3 4 Memory-Word 4 0–4 3 4 0?[...]

  • Page 47

    80C186EA/80C188EA, 80L186EA/80L188EA INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EA 80C188EA Comments Clock Clock Cycles Cycles LOGIC (Continued) XOR e Exclusive or: Reg/memory and register to either 001100dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 1000000w m o d110 r / m data data if w e 1 4/16 4/16 * Immediate to a[...]

  • Page 48

    80C186EA/80C188EA, 80L186EA/80L188EA INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EA 80C188EA Comments Clock Clock Cycles Cycles CONTROL TRANSFER (Continued) RET e Return from CALL: Within segment 11000011 1 6 2 0 Within seg adding immed to SP 11000010 data-low data-high 18 22 Intersegment 11001011 2 2 3 0 Intersegment adding immediate[...]

  • Page 49

    80C186EA/80C188EA, 80L186EA/80L188EA INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EA 80C188EA Comments Clock Clock Cycles Cycles PROCESSOR CONTROL CLC e Clear carry 11111000 2 2 CMC e Complement carry 11110101 2 2 STC e Set carry 11111001 2 2 CLD e Clear direction 11111100 2 2 STD e Set direction 11111101 2 2 CLI e Clear interrupt 1111[...]

  • Page 50

    80C186EA/80C188EA, 80L186EA/80L188EA REVISION HISTORY Intel 80C186EA/80L186EA devices are marked with a 9-character alphanumeric Intel FPO number un- derneath the product number. This data sheet up- date is valid for devices with an ‘‘A’’, ‘‘B’’, ‘‘C’’, ‘‘D’’, or ‘‘E’’ as the ninth character in the FPO number[...]