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Intel 82540EP manual

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Table of contents for the manual

  • Page 1

    82540EP Gigabit Et hernet Contr oller Netw orking Silico n Dat ashe et Revision 1.2 Apr il 20 03[...]

  • Page 2

    ii D atashee t INFORMA TION IN THIS DOCUMENT IS PRO VIDED IN CONNECTION WI TH INTEL PRODUCTS . NO LICENSE, EXPRESS OR IMPLIED , B Y ESTOPP EL O R OTHERW ISE , T O AN Y INT EL LECT UAL PROP ERTY RI GHT S IS GR ANTED BY THI S D OC UMENT . EX CEP T AS P ROVIDED IN INTEL'S TERMS AND CON DITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUME S NO LIABILIT[...]

  • Page 3

    Datasheet ii i Netw orking Si licon — 82540E P Revision History Date Re vision Notes Ap r 200 2 0.25 In iti al R e leas e No v 2002 1.0 Ch an ged docu ment stat us to Inte l Con fiden tia l. J an 2003 1.1 Se ctio n 1 .0. R e plac ed B loc k D iag ram Se ction 2 .6. Ad ded T a bl e f ootn ot e Sec ti on 4. 1, 4.2 , 4.3 . Re pl ac ed t able s Sec t[...]

  • Page 4

    82540EP — Networking Silico n iv D atasheet Note : Thi s page is int e ntion ally left bla nk.[...]

  • Page 5

    Datasheet v Netw orking Si licon — 82540E P Content s 1.0 Int roducti on... ..... ... .... ..... .. ..... ..... ..... .... ... .... ..... ... .... ..... ..... .... ... ..... .... ..... ..... .. ..... ..... .. ..... .... .. 1 1.1 Docu men t Sco p e ..... ..... .. ..... .. ..... .. ..... ... .... ... .... ... .... ... ..... .. ..... .. ..... .. ...[...]

  • Page 6

    82540EP — Networking Silico n vi D atasheet 4. 5.3 EEPRO M In terfa ce ...... ..... .. ..... ..... .. ..... ..... .... ..... ... .... ..... ..... .... ... ..... .... ... . 26 5. 0 P a cka g e and Pi n out Info rma ti on .. ..... .. ..... .. ..... .. ..... .. ..... .. ..... .. ..... ... .... ... .... ... .... ... ..... .. ..... . 27 5. 1 Devic e I[...]

  • Page 7

    Netw orking Si licon — 82540E P Datasheet 1 1.0 Introduction The Inte l ® 82540 EP Gigabi t Ether net Contr oll er is a s ingle , compa ct compone nt wi th an inte g rated Gigabi t E the rnet Media Acc ess Contro l (MAC) and phys i c al la yer (PHY) functio ns. For des ktop , works tatio n and mobil e PC Network des i gns with cr itical spac e c[...]

  • Page 8

    82540EP — Networking Silico n 2 D atasheet Figu re 1. Giga b it Eth ern e t Co nt roller B l ock Di agram Tx Arb PCI i/f PC I I/F RX MAC TX M AC TX de scriptor engi n e Dat a Al ignmen t FI F Os PC I Core DM A MAC C or e 8254 0EP Ar ch it ec tu re Packe t Buffer Tar get Cont rol Cont rol, Stat us & Inte rru p t Regist ers Ta rget Lo gic Filte[...]

  • Page 9

    Netw orking Si licon — 82540E P Datash eet 3 1.1 Doc ument Scope This docu m ent co ntains dat ashe et speci f ications for the 82540EP Giga bit Ethe rnet Cont roller, incl uding signal descr iptions, DC and A C parameters, packaging da ta , and pi nout inform at ion . 1.2 Re fer ence Docu ments This appl icat ion assumes th at the desi gne r is [...]

  • Page 10

    82540EP — Networking Silico n 4 Dat asheet Note : This page is int e nt ion ally left bla nk.[...]

  • Page 11

    Netw orking Si licon — 82540E P Datash eet 5 2.0 Features of the 82540EP Gigab it Ethern et Controller 2.1 PCI Feat ur es 2.2 MA C S peci fic Fe atur es Fe atu res B enef it s PC I Revi sion 2.3 su pp or t f or 32-b it wid e inter f ac e at 33 M Hz an d 6 6 MH z • Ap plicat ion fl e xi bilit y f or LAN on Moth erbo ard (L OM) or em bedd ed s ol[...]

  • Page 12

    82540EP — Networking Silico n 6 Dat asheet 2.3 PHY Spe cif ic Fe atu res Featu res Be ne fits I nte grat ed PHY for 10/ 100 /10 0 0 Mb ps fu ll an d ha lf dup lex op er a t io n • S ma ll er foo tpr in t an d low er p ower dis sip ati on com pa red to mul ti-c hip M A C an d PHY so lu tions IEEE 8 0 2.3ab Auto -Negotia tio n supp or t • A uto[...]

  • Page 13

    Netw orking Si licon — 82540E P Datash eet 7 2. 5 Man ag eabili ty Fe at ures Fe atu res B enef it s Mana ge abil ity fea tur es : S MB por t, ASF 1 .0, ACPI , W ak e on LA N, and PXE • Ne twork m a nagem ent fle xibi lit y On-board SMB por t • En abl es IP M I and ASF im plem e nta ti on s • Al lo ws pa c ket s r out in g to an d fr om eit[...]

  • Page 14

    82540EP — Networking Silico n 8 Dat asheet 2.6 Addi tio nal D evi ce Fe atu res 2.7 T ech no logy Fe at ures Featu res Be ne fits Fo ur act i vit y and lin k indi ca tion ou tputs that di re ctl y driv e LED s • L in k an d ac tiv it y indi ca tio ns (1 0, 10 0, and 10 00 Mbp s) on each p or t Pr ogr a mma ble LE D f u nc t io na li ty • Sof [...]

  • Page 15

    Netw orking Si licon — 82540E P Datash eet 9 3.0 Signal D escriptions Note: T he ta r geted sign al names are subject to ch a nge with out notic e. V erify wit h your loc al Intel sales of f ice tha t you hav e the late st informa tio n b efor e f inali z ing a desig n. 3 .1 S ig nal T y pe D efi ni ti ons The signa ls of the 82540EP controll er [...]

  • Page 16

    82540EP — Networking Silico n 10 Dat asheet CBE[3 :0]# TS Bu s Co mm an d and By t e Enab les . Bus com mand an d by te ena ble si gnals ar e m ul tiple xe d on the sam e PCI pins. Duri ng the ad dr e ss p hase o f a tra nsacti on, CB E [3:0] # def ine the bus com m and. In t h e da ta phas e, C BE [ 3: 0]# are use d a s byt e enable s. Th e byt [...]

  • Page 17

    Netw orking Si licon — 82540E P Datash eet 11 3.2. 2 Arbitr ation Signa ls 3.2. 3 Inter rupt S igna l 3.2. 4 Syst em Signals 3.2. 5 Err or Rep o rting Si gnal s Symb ol T y pe Na me an d Fun ctio n REQ# TS Request Bu s. The Req ue st B us si gn al is u s ed t o r equ es t c ont ro l of the bu s f r om t he ar bit er. Thi s sig n al is p oint -t o[...]

  • Page 18

    82540EP — Networking Silico n 12 Dat asheet 3. 2.6 P owe r Ma nagem ent Si gnals 3. 2.7 I mpedan ce Comp ensatio n Signals 3. 2.8 SMB S ignals 3. 3 EEPR O M an d Seri al FL ASH Inte rf ac e Sign als Symbo l T yp e N ame an d Func tion LAN _ PWR_ GOOD I P o we r Good (Power-on Reset). T he Pow er Goo d sign al i s used t o in di cat e t hat s ta b[...]

  • Page 19

    Netw orking Si licon — 82540E P Datash eet 13 3.4 Mi sce ll an eo us Si g nals 3.4. 1 LED S ignals 3.4. 2 Other Sign als FL_C E# O FLASH Chip E nable Ou tput. Us ed t o e n able FL AS H devic e. FL_S CK O FLASH Seria l Clock Output . T he clo ck r ate of th e s e ri al FLA SH i nt erfa ce i s app r oximat el y 1 MHz . FL_S I O FL ASH Serial Data [...]

  • Page 20

    82540EP — Networking Silico n 14 Dat asheet 3.5 3. 5.1 Cr y stal Signa ls 3. 5.2 An alog S ign als Symbo l T yp e N ame an d Func tion XT AL 1 I Crystal One . Th e Crys tal One p in is a 25 M H z + /- 5 0 ppm in pu t sig na l. It ca n be conn ec te d to eit her an os ci ll ato r o r c r yst al. If a c r y s tal is u se d, Cr y st al T w o (XT AL2[...]

  • Page 21

    Netw orking Si licon — 82540E P Datash eet 15 3.6 T est In terf ace Si g nals 3. 7 P ow er S upp ly Con nect io ns 3.7. 1 Digital S upp lies 3.7. 2 Analog Supplies Symb ol T y pe Na me an d Fun ctio n JT AG_TC K I JT A G Cl ock. JT AG_TD I I JT AG TD I. JT AG_TD O O JT A G T D O . JT AG_T MS I JT AG T MS . JT AG_ TRST # I J T A G Rese t. Thi s i [...]

  • Page 22

    82540EP — Networking Silico n 16 Dat asheet 3. 7.3 G ro und and No Connec ts 3. 7.4 Co ntr ol S ignals Symbo l T yp e N ame an d Func tion GND P G round. NC P No Co nnect. Do not co nn ect any c irc ui tr y to th ese pi ns. Pu ll-u p or pu ll- down re si st ors shou ld n ot be con ne ct ed t o t hes e pi ns. Symbo l T yp e N ame an d Func tion CT[...]

  • Page 23

    Netw orking Si licon — 82540E P Datash eet 17 4.0 V oltage, T emperatu re , and Timing Specifications Note: T he specif i cati on v alues li sted in this s ecti on are sub ject to chan ge wit hout notic e. V erify with your loca l Intel s ales of fic e th a t you ha ve the lates t in formation before fi naliz ing a design. 4.1 Abs olut e Max im u[...]

  • Page 24

    82540EP — Networking Silico n 18 Dat asheet 4.3 DC S peci fic ati on s V AH An alog Hig h VDD Ra nge 3. 3V ± 10% 33 . 3 3 . 6 V V D Core Digital V ol tag e Range 1.5V ± 5% 1. 425 1. 5 1. 575 V V AL Anal og Low VDD Ra nge 2.5V ± 5% 2. 37 5 2.5 2 .62 5 V a. Sustai ned opera tion of the device at condi tions e xceedi ng th ese values , ev en if t[...]

  • Page 25

    Netw orking Si licon — 82540E P Datash eet 19 T able 5. Po wer Spe cificati ons - D3cold D3cold - wake-up e nabled D3cold - wake disabl ed - max powe r savin gs mode di sabled D3 cold - w ake disa bled - max pow er sav i ng s mod e enabl ed a unp lug ge d/ n o li nk @1 0 Mb ps @100 Mbps Ty p I c c (m A) Ma x Icc (mA) T y p I c c (mA) Max Ic c (mA[...]

  • Page 26

    82540EP — Networking Silico n 20 Dat asheet 2.5 V 20 20 4 0 40 80 80 2 40 245 0.1 0.1 1.5 V 10 10 3 0 35 55 60 4 00 425 1 1 Subsy stem 3. 3V cur ren t 7 0 mA 135 m A 200 mA 800 m A 10 m A T able 7 . P owe r Sp ecificati ons - Complete S u bsystem T able 8 . I/ O Char acterist ics Sym bol Pa ra mete r Condi tion Min T yp Max Uni t V IL V olt age i[...]

  • Page 27

    Netw orking Si licon — 82540E P Datash eet 21 4.4 A C Characteris tics T able 9. A C Ch aract erist i cs: 3.3 V Interfac ing Sym bol Param ete r Min Ty p M ax Unit PCIC L K C lock f req ue ncy in PCI m ode 66 MHz T able 10. 25 MHz Clock Input Require ments Sym bol Paramete r a Min T y p Max U nit fi_ TX_ CLK TX _C LK_ IN f req ue nc y 25 - 50 p p[...]

  • Page 28

    82540EP — Networking Silico n 22 Dat asheet 4.5 Tim ing Spe cific ati ons Note : Ti m ing s pec if icatio ns are s ubj e ct to cha nge . V erify with you r local Int el sales of fi c e that you ha ve the latest info rm ati on before f inalizi ng a de sign. 4.5.1 PC I Bu s I nter face 4.5.1 .1 PCI B u s I n ter fa ce Clock Figure 1. A C T est Load[...]

  • Page 29

    Netw orking Si licon — 82540E P Datash eet 23 4. 5. 1.2 PCI Bu s I nt erfa ce Ti ming NOTES: 1. Out pu t ti m in g me as ure m ent s ar e a s sh own . 2. REQ # an d GN T# s ign a ls ar e p oi nt- t o-p oi nt and have di fferen t o ut pu t va lid del ay a nd inpu t s e tup ti mes th an bu ssed si gn als . GNT# h as a setu p of 10 ns; REQ# ha s a s[...]

  • Page 30

    82540EP — Networking Silico n 24 Dat asheet Figure 4. PCI Bus Interf ace I nput Timing Meas ureme nt Conditi on s V TH V TL V T EST PCI _CLK T SU V T EST I nput V MAX V T EST V TL V TH I nput V alid T H T able 16. P CI Bus Int erf ace Ti mi ng Measuremen t Cond iti ons Symb ol Param eter PCI 66 M Hz 3. 3 v Uni t VT H In put me as ur emen t t es t[...]

  • Page 31

    Netw orking Si licon — 82540E P Datash eet 25 Figu re 6 . TV AL (m ax ) F all ing E dge T est Loa d 10 pF 25 Ω Pin T est P oint 1/2 inch max. V CC Figu re 7 . TV AL (m in) T est Load 1k Ω Pin T est P oint 1/2 inch max. V CC 10 pF 1k Ω Figure 8. TV AL T est Lo ad (PCI 5 V Signal in g En vironment) 50 pF Pin T est P oint 1/2 inch max.[...]

  • Page 32

    82540EP — Networking Silico n 26 Dat asheet 4. 5.2 Link Interface Timing 4. 5.3 EE PROM Interface a. The EEPRO M clock is der ived fr om a 125 MHz inter na l clock. T able 1 7. Rise an d Fall T imes Symbo l Parame te r Cond itio n Min M ax Un it TR C l ock ris e t im e 0.8 V to 2.0 V 0 .7 ns TF Cl oc k f all ti me 2.0 V to 0. 8 V 0 . 7 ns T R D a[...]

  • Page 33

    Netw orking Si licon — 82540EP Datasheet 27 5.0 P ac kage an d Pinout Inf ormati on This se ct ion describes the 82540EP devi c e, manuf actured in a 19 6-le a d ball grid arr ay measur ing 15mm X 15mm. Ext ernal product identif icati on is sho wn i n Figure 1 0 . The nomina l ball pi tch is 1mm. The pin num ber -to-si gna l mapping is in dic a t[...]

  • Page 34

    82540EP — Net worki ng Sili co n 28 D atasheet 5.2 P ackage I nfor mat ion The 82540E P de vic e is a 196- lead ba ll grid arra y (TFBGA) measur ing 15 mm 2 . T he pack a ge dim ensi ons are deta iled in Figure 11 . The nomi nal ba ll pitc h is 1 mm. Figure 11. 82540E P Mechan ical Speci fications[...]

  • Page 35

    Netw orking Si licon — 82540EP Datasheet 29 5.3 Th ermal Spec ifi cat ions The 8254 0EP de v ic e is specif ied for operat ion when the ambi ent temperat ure (T A) is within the range of 0 ° C to 70 ° C. TC ( c ase t emperat ure) i s cal culated using t he eq ua tion: TC = T A + P ( θ J A - q JC) TJ (junct ion temper atu re) is ca lc ulated us[...]

  • Page 36

    82540EP — Net worki ng Sili co n 30 D atasheet 5.4 Pi nou t Informa tion T a bl e 19 . PCI Addre ss, Da t a, and C o ntrol S ig nal s Signa l P in Signal Pin Sign al Pi n PC I_AD[0] N7 PCI_AD[ 16 ] K1 CBE0 # M4 PC I_AD[1] M7 P CI_AD[ 17 ] E3 CBE1 # L3 PC I_AD[2] P6 PCI _AD[ 18] D1 CBE2 # F3 PC I_AD[3] P5 PCI _AD[ 19] D2 CBE3 # C4 PC I_AD [4] N5 P[...]

  • Page 37

    Netw orking Si licon — 82540EP Datasheet 31 T able 24. P ower Manag emen t Sign als Signa l Pin Si gnal P in LAN_PWR_ GOOD A9 A UX_ PWR J12 PME# A6 CLKRUN# C8 T able 25. I mped ance Co mpen sation Signals Signa l Pin Si gnal P in ZN_COM P H4 ZP_COMP G4 T able 26. SMB Signal s Signa l Pin Si gnal P in Signa l P in SMBCLK A1 0 S MBD A T A C 9 SMB A[...]

  • Page 38

    82540EP — Net worki ng Sili co n 32 D atasheet T abl e 31. PHY Signa ls Signa l P in Signal Pin Sign al Pi n XT AL 1 K14 M DI0 + C13 M DI2 + F 13 XT AL 2 J1 4 M DI1- E14 MD I3- H14 RE F B14 M DI1 + E 13 MD I3+ H 13 MDI0- C14 MDI 2- F14 T able 3 2. T est Interface S ignals Signa l P in Signal Pin Sign al Pi n JT AG _TC K L14 JT A G_TDO M 14 JT AG [...]

  • Page 39

    Netw orking Si licon — 82540EP Datasheet 33 T able 35. Grou nds and No Connec t Signals S ignal Pin S ign al Pin S ign al Pin Sign al Pin GND B3 GND E7 GND G9 NC A1 GND B7 GND E8 GND G10 NC A14 GND C10 GND E9 GND G11 NC C5 GND C12 GND E10 GND G14 NC D10 GND D4 GND F4 GND H9 NC D12 GND D5 GND F5 GND H10 NC D14 GND D6 GND F6 GND K2 NC F12 GND D7 GN[...]

  • Page 40

    82540EP — Net worki ng Sili co n 34 D atasheet PC I_AD [26] B 5 PC I_AD [27] B 6 GND B7 PC I_AD [31] B 8 RST# B 9 SMBA LRT# B10 LED 2 / LINK 10 0# B 11 LED 3 / LINK 10 00# B 12 CTRL_25 B13 REF B1 4 PC I_AD [21] C1 M66E N C2 REQ# C3 CBE3# C4 NC C5 PC I_AD [28] C6 PC I_AD [29] C7 CLKRUN# C8 SMBDA T A C9 GND C10 LED1 / ACT# C11 GND C12 MDI 0+ C13 MD[...]

  • Page 41

    Netw orking Si licon — 82540EP Datasheet 35 VDDO (3 .3V) E1 GND E2 PCI_AD [17] E3 GND E4 GND E5 GND E6 GND E7 GND E8 GND E9 GND E10 D V DD (1.5V ) E11 D V DD (1.5V ) E12 MDI 1+ E13 MDI 1- E14 IRD Y# F1 FRAME# F2 CBE2# F3 GND F4 GND F5 GND F6 GND F7 GND F8 GND F9 GND F10 GND F11 NC F12 MDI 2+ F 13 MDI 2- F 14 CLK G1 VIO G2 TRD Y# G3 ZP_CO MP G4 D [...]

  • Page 42

    82540EP — Net worki ng Sili co n 36 D atasheet GND G11 A VD DL (2 .5 V) G1 2 D VDD (1.5V) G13 GND G14 STOP# H1 INT A # H2 DE VSEL# H3 ZN_ COMP H 4 D VDD (1.5V) H5 D VDD (1.5V) H6 D VDD (1.5V) H7 D VDD (1.5V) H8 GND H9 GND H10 D VDD (1.5V) H1 1 NC H12 MDI 3+ H13 MDI 3- H14 PA R J 1 PERR# J2 GNT# J3 NC J4 D VDD (1.5V) J5 D VDD (1.5V) J6 D VDD (1.5V[...]

  • Page 43

    Netw orking Si licon — 82540EP Datasheet 37 D V DD (1.5V ) K7 D V DD (1.5V ) K8 D V DD (1.5V ) K9 D V DD (1.5V ) K10 D V DD (1.5V ) K11 GND K12 VDDO (3 .3V) K13 XT AL1 K14 PCI_AD [14] L1 PCI_AD [15] L2 CBE1# L3 D V DD (1.5V ) L4 D V DD (1.5V ) L5 GND L6 NC L7 A V DDL (2.5 V) L8 D V DD (1.5V ) L9 D V DD (1.5V ) L10 GND L11 JT AG_T MS L 12 JT AG_RS[...]

  • Page 44

    82540EP — Net worki ng Sili co n 38 D atasheet PC I_AD [9] N3 PC I_AD [7] N4 PC I_AD [4] N5 VD DO (3.3V) N6 PC I_AD [0] N7 VD DO (3.3V) N8 FL_SCK N9 EE_DO N1 0 NC N11 GND N12 SD P6 N13 SD P0 N14 NC P1 VD DO (3.3V) P 2 PC I_AD [8] P3 PC I_AD [6] P4 PC I_AD [3] P5 PC I_AD [2] P6 EE_CS P 7 GND P8 FL _SO P9 EE_DI P1 0 CTRL_15 P11 VD DO (3.3V) P12 SD [...]

  • Page 45

    Netw orking Si licon — 82540EP Datasheet 39 5.5 Vis ual Pin Re f er ence Fi gu re 12 . Bal l Grid Ar r ay / P i n Ref ere nce f or 19 6 -TFB G A (t hru- the - to p vie w) • AB CDE F GH J K LM N P 14 NC PHY REF MDI- [0] NC MDI- [1] MDI- [2] VSS MDI- [3] XTAL2 XTAL1 JTCK JTDO SDP[0] NC 14 13 TEST CTRL 25 MDI+ [0] VSS MDI+ [1] MDI+ [2] 1.5V MDI+ [[...]