Intel 87C196CB manual

87C196CB Supplement to 8XC196NT User’ s Manual[...]

87C196CB Supplement to 8XC196NT User ’ s Manual August 2004 O rder Num ber : 2 72787 -00 3 CB_title.fm5 Page 1 Tuesday, September 1 5, 1998 9:54 AM[...]

Information in thi s document is provided in connec tion with Intel pr oducts. No l icense, express or implied, by e stoppel or othe rwise, to any intellectual p roperty rights is gr anted by this doc ument. Except as provided in I ntel’s T erms and Conditions of Sale for such pr oducts, Intel assumes no liability whatsoev er , and Intel disc lai[...]

iii CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTS .......... ................. ................. ................. ................ ................. ..... 1-1 1.2 RELATED DOCUMENTS ........... ................. ................ ................. ................. ........... ..... 1-2 CHAPTER 2 ARCHITECTURAL OVERVIEW 2.1 DEVICE FEATU[...]

87C196CB SUPPLEMENT iv 7.4.4 Progra mming a Me ssage Acc eptance Filter .......... ................. ........... ................. .... 7-17 7.5 CONFIGURING MESSAGE OBJECTS ............ ................. ................. ................. ........ 7-20 7.5.1 Specify ing a Message Obje ct’s Confi guratio n .............. ................. .......[...]

v CONTENTS FIGURES Figure Pa ge 2-1 87C196CB Bl ock Diagra m............. ................. ................. ................. ................. ...........2-2 2-2 Clock Ci rcuitry ............... ................ ................. ................. ................. ................. ...........2-3 2-3 Internal Clock Phas es ........ ............[...]

8XC196CB SUPPLEMENT vi FIGURES Figur e Page A -2 87C196CB 100- pin QFP Package ...... .. ..... .. ..... .. ..... . ..... ...... . ..... ..... ....... ..... ..... ..... ...... A-3[...]

vii CONTENTS TABLES Table Pa ge 1-1 Relate d Documents ............ ................. ................. ................. ................ ................. ...... 1-2 2-1 Featu res of the 8XC196NT and 87C196CB .............. ................. ................. .................2-1 2-2 State Times at Various Freque nc ies ......... ..... ...... ...[...]

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1 Guide to This Manual[...]

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1-1 CHAPTER 1 GUIDE TO THIS MANUAL Thi s document is a supplement to the 8XC196NT Microcontroller User’s Manual . It describ es the differen ces between the 87C196CB and the 8XC196NT. For information not found in this supplement, please consult the 8XC196NT Microcontroller User’s Manu al (o rder number 272317) or the 87C196 CB datasheet ( 87C19[...]

87C196CB SUPPLEMENT 1-2 Chapte r 9 — Interfacing with External Memory — discu sses differenc es in th e bus timing mode s supp orted by the 8 X C196NT a nd the 8 7C196CB. Chapte r 10 — Pr ogramming the Nonvola tile Memory — descri bes the me mory ma ps a nd rec - ommen ded circuit s to support progr a mming of the 87C196CB’ s 56 Kbyte s o[...]

2 Architectural Overview[...]

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2-1 CHAPTER 2 ARCHITECTU RAL OVERVIEW This ch apter describes architectu ral differences between the 87C196 CB and the 8XC196NT. Both the 8XC196NT and the 87C19 6CB are designed for high-speed calculations and fast I/O. With the ad dition of the CAN (controller area network ) peripheral, the 8 7C196CB reduces point- to-poin t wiring requiremen ts, [...]

87C196CB SUPPLEMENT 2-2 2.2 BLOCK DIAGRAM Figure 2- 1 shows the major blocks within the device. The 8XC196NT and 87C196CB hav e the same peripheral set with the exceptio n of the CAN (controller area network) peripheral, which i s uniqu e to the 87C196CB. The CAN periph eral manages commun ications between multiple net- work nodes. Th is integrated[...]

2-3 ARCHITECTURAL OVERVIEW Figure 2- 2. Clock Circuitry The rising edg es of PH1 and PH2 generate the in ternal CLKOUT signal (Figure 2-3). Th e clock circuitry routes separ ate internal clock signals to the CPU an d the peripher als to provide flexibil- ity in power man agement. It also outputs the CLKOUT signal o n the CLKOUT pin. Because of the [...]

87C196CB SUPPLEMENT 2-4 Figure 2-3 . Internal Cloc k Phases The comb ined period o f phase 1 and pha se 2 of the internal CLKOUT sig nal defines the ba sic time unit known as a state t ime or state . Table 2-2 lists state time duratio ns at various frequen ci es. The follo wing formulas calculate th e frequency of PH1 and PH2 , the duration of a st[...]

2-5 ARCHITECTURAL OVERVIEW Figure 2-4. Effect of Clock Mode on CLKOUT Frequency Table 2-3. Relation ships Between In put Freque ncy, Clock Multi plier, and State Times F XTAL 1 (Frequ ency on XTAL1 ) PLLEN Mul tipl ier f (Input F requency to the Divid e-by -tw o Circui t) t (Clock Period) State Ti me 4 MHz 0 1 4 MHz 250 ns 500 ns 5 MHz 0 1 5 MHz 20[...]

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Memory Partitions 3[...]

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3-1 CHAPTER 3 MEMORY PART ITIONS This chapter describ es the differences in the add ress space of the 87C196CB from that of the 8XC196NT. Th e 87C19 6CB has 56 Kby tes of one-time-pr ogrammable r ead-only mem ory (OT- PROM), while the 8XC196NT is available with 32 Kbytes. The 87C196CB also has an additional 512 bytes of register RAM. The 87 C196CB [...]

87C196CB SUPPLEMENT 3-2 Table 3-2. 87C19 6CB Memory Map Hex Address Description Addressing Mode s FFF FFF FF2080 Program memory ( After a device reset, the first instruct ion fetch is from FF2080H) † Indirect, index ed, extended FF207F FF2000 Special purp ose m emory † Indirect, index ed, extended FF1FF F FF0600 Exte rnal device (memory or I/O)[...]

3-3 MEMORY PARTITIONS Table 3 -3. 87C196CB Pe ripheral SFRs Ports 0, 1, 2, and 6 SFRs Timer 1, Timer 2, and EPA SFRs Address Hi gh (Odd ) Byte L ow (Even) Byte Addres s High (O dd) Byte Low (Even) Byt e 1FDEH Reserved Reserved † 1F9EH TIMER2 (H) TIMER2 (L) 1FDCH Reserved Reserved 1F9CH Res erved T2CONTROL 1FDAH Reserved P0_PIN † 1F9AH TIMER1 (H[...]

87C196CB SUPPLEMENT 3-4 Table 3 -4. CAN Peripheral SF Rs Mes sag e 15 Mess ag e 11 Addr High ( Odd) Byte Low (Even ) Byte Addr High (Odd) By te Low (Even ) Byte 1EFEH Reserved CAN_MSG15DAT A7 1EBEH Re served CAN_MSG11DATA7 1EFCH CAN_MSG1 5DATA6 CAN_MSG1 5DATA5 1EBCH CAN_M SG11DATA6 CAN_MSG1 1DATA5 1EFAH C AN_MSG15DAT A4 CAN_MSG15DAT A3 1EBAH CAN_MS[...]

3-5 MEMORY PARTITIONS Message 7 Message 3 and Bit Timing 0 Addr High (Odd ) Byte Low (Even) Byte Addr Hig h (Odd) Byte Low (Even) Byte 1E7EH Reser ved CAN_MSG7 DATA7 1E3EH CAN_BTIM E0 † CAN_MSG3 DATA7 1E7CH C AN_MSG7DATA6 C AN_MSG7DATA5 1E3CH CAN_MSG3D ATA6 CAN_MSG3D ATA5 1E7AH CAN_MSG7 DATA4 CAN_MSG7 DATA3 1E3AH CAN_MSG3D ATA4 CAN_MSG3D ATA3 1E7[...]

87C196CB SUPPLEMENT 3-6 Table 3-5. Selectin g a Window of Periphera l SFRs Periph eral WSR V alue f or 32-byte Windo w (00E0–00FFH ) WSR V alue for 64-byte Windo w (00C0–00FFH) WSR Value f or 128-byte Wi ndow (0080–00FFH) Ports 0, 1, 2, 6 7EH 3FH 1FH A/D convert er, EPA inter rupts 7DH 3EH EPA compare 0–1, capture/c ompar e 8–9 , timers 7[...]

3-7 MEMORY PARTITIONS Table 3 -6. Selecting a Window of the Upper Regist er File Register RAM Locations WSR Value for 32-byte Win dow (00E0–00FFH) WSR Value for 64-byte Wi n dow (00C0–00FFH ) WSR Val ue for 128-b yte Window (0080–00FFH) 03E0–03FFH 5FH 2FH 17H 03C0–03DFH 5EH 03A0–03BFH 5DH 2EH 0380–039FH 5CH 0360–037FH 5BH 2DH 16H 03[...]

87C196CB SUPPLEMENT 3-8[...]

3-9 MEMORY PARTITIONS Table 3 -7. Selecting a Window of Uppe r Register RAM Register RAM Locations WSR Value for 32-byte Win dow (00E0–00FFH) WSR Value for 64-byte Wi n dow (00C0–00FFH ) WSR Val ue for 128-b yte Window (0080–00FFH) 0DE0–0DFFH 6FH 37H 1BH 0DC0–0DDFH 6EH 0DA0–0DBFH 6DH 36H 0D80–0D9FH 6CH 0D60–0D7FH 6BH 35H 1AH 0D40–[...]

87C196CB SUPPLEMENT 3-10 Table 3-8. Windows Base Address WSR V alue for 32-byt e Windo w (00E0–00FFH) WSR Valu e for 64-byte W indo w (00C0–00FFH) WSR Value f or 128-byte Wi ndow (0080–00FFH) Peripheral S FRs 1FE0H 7F H † 3FH † 1FH † 1FC0H 7EH 1FA0H 7DH 3EH 1F80H 7CH 1F60H 7BH 3DH 1EH 1F40H 7AH 1F20H 79H 3CH 1F00H 78H CAN Peripheral SFR[...]

3-11 MEMORY PARTITIONS Upper Reg ister File 03E0H 5F H 2FH 17H 03C0H 5EH 03A0H 5DH 2EH 0380H 5CH 0360H 5BH 2DH 16H 0340H 5AH 0320H 59H 2CH 0300H 58H 02E0H 57H 2BH 15H 02C0H 56H 02A0H 55H 2AH 0280H 54H 0260H 53H 29H 14H 0240H 52H 0220H 51H 28H 0200H 50H 01E0H 4F H 27H 13H 01C0H 4EH 01A0H 4DH 26H 0180H 4CH 0160H 4BH 25H 12H 0140H 4AH 0120H 49H 24H 01[...]

87C196CB SUPPLEMENT 3-12 Table 3-9 . WSR Settings and Direct Addresses for Windowab le SFRs Registe r Mnem on ic Memo ry Locatio n 32-byte Wi ndows (00E0–00FFH ) 64-byte Windows (00C0–00FFH) 1 28-byte Wi ndows (0080–00FFH) WSR Direct Address WSR Direct Addres s WSR Direct Address AD_COMMAND 1FACH 7DH 00ECH 3EH 00ECH 1F H 00ACH AD_RESULT 1FAAH[...]

3-13 MEMORY PARTITIONS CAN_MSG7C ON0 1E70H 73H 00F 0H 39H 00F0H 1 CH 00F 0H CAN_MSG8CON0 1E80H 74H 00E0H 3AH 00C0H 1D H 0080H CAN_MSG9CON0 1E90H 74H 00F0H 3AH 00D0H 1 DH 0090H CAN_MSG10C ON0 1EA0H 75H 00E 0H 3AH 00E0H 1D H 00A 0H CAN_MSG11C ON0 1EB0H 75H 00F 0H 3AH 00F0 H 1D H 00B 0H CAN_MSG12CON 0 1EC0H 76H 00E0H 3BH 00C0H 1DH 00C0 H CAN_MSG13C ON[...]

87C196CB SUPPLEMENT 3-14 CAN_MSG9DATA0 1E97H 74H 00F 7H 3AH 00D7H 1D H 0097H CAN_MSG10D ATA0 1EA7H 75H 00E7H 3AH 00E7H 1D H 00A7 H CAN_MSG11D ATA0 1EB7H 75H 00F7H 3AH 00F7H 1DH 00B7H CAN_MSG12DATA0 1EC7H 76H 00E 7H 3BH 00C7H 1 DH 00C7H CAN_MSG13DATA0 1ED7H 76H 00F 7H 3BH 00D7H 1 DH 00D7 H CAN_MSG14D ATA0 1EE7H 77H 00E7H 3BH 00E7H 1D H 00E7 H CAN_MS[...]

3-15 MEMORY PARTITIONS CAN_MSG11D ATA2 1EB9H 75H 00F9H 3AH 00F9H 1DH 00B9H CAN_MSG12DATA2 1EC9H 76H 00E 9H 3BH 00C9H 1 DH 00C9H CAN_MSG13DATA2 1ED9H 76H 00F 9H 3BH 00D9H 1 DH 00D9 H CAN_MSG14D ATA2 1EE9H 77H 00E9H 3BH 00E9H 1D H 00E9 H CAN_MSG15D ATA2 1EF9H 77H 00F9H 3BH 00F9H 1DH 00F9H CAN_MSG1D ATA3 1E1AH 70H 00FA H 38H 00DAH 1CH 009AH CAN_MSG2D [...]

87C196CB SUPPLEMENT 3-16 CAN_MSG13D ATA4 1EDBH 76H 00F BH 3BH 00DBH 1 DH 00DBH CAN_MSG14D ATA4 1EEBH 77H 00EB H 3BH 00EBH 1 DH 00EBH CAN_MSG15D ATA4 1EFBH 77H 00F BH 3BH 00FB H 1DH 00F BH CAN_MSG1DATA5 1E1CH 70H 00FCH 38H 00DCH 1CH 009C H CAN_MSG2DATA5 1E2CH 71H 00ECH 38H 00EC H 1CH 00ACH CAN_MSG3D ATA5 1E3CH 71H 00FCH 38H 00FC H 1 CH 00BCH CAN_MSG[...]

3-17 MEMORY PARTITIONS CAN_MSG15D ATA6 1EFDH 77H 00FDH 3BH 00FDH 1 DH 00FDH CAN_MSG1D ATA7 1E1EH 70H 00FE H 38H 00DEH 1 CH 009EH CAN_MSG2D ATA7 1E2EH 71H 00EEH 38H 00EEH 1C H 0 0AEH CAN_MSG3D ATA7 1E3EH 71H 00FEH 38H 00FEH 1 CH 00BEH CAN_MSG4D ATA7 1E4EH 72H 00EEH 39H 00CEH 1 CH 00CEH CAN_MSG5DATA7 1E5EH 72H 00F EH 39H 00DE H 1CH 00DEH CAN_MSG6D AT[...]

87C196CB SUPPLEMENT 3-18 CAN_MSG2ID1 1E23H 71H 00E3H 38H 00E3H 1CH 00A3H CAN_MSG3I D1 1E33H 71H 00F3H 38H 00F3H 1 CH 00B 3H CAN_MSG4ID1 1E43H 72H 00E 3H 39H 00C3H 1 CH 00C3H CAN_MSG5ID1 1E53H 72H 00F3H 39H 00D3H 1 CH 00D3H CAN_MSG6ID1 1E63H 73H 00E3H 39H 00E3H 1CH 00E3H CAN_MSG7I D1 1E73H 73H 00F3 H 39H 00F3H 1 CH 00F 3H CAN_MSG8ID1 1E83H 74H 00E 3[...]

3-19 MEMORY PARTITIONS CAN_MSG4ID3 1E45H 72H 00E 5H 39H 00C5H 1 CH 00C5H CAN_MSG5ID3 1E55H 72H 00F5H 39H 00D5H 1 CH 00D5H CAN_MSG6ID3 1E65H 73H 00E5H 39H 00E5H 1CH 00E5H CAN_MSG7I D3 1E75H 73H 00F5 H 39H 00F5H 1 CH 00F 5H CAN_MSG8ID3 1E85H 74H 00E 5H 3AH 00C5H 1 DH 0085H CAN_MSG9ID3 1E95H 74H 00F5H 3AH 00D5H 1 DH 0095H CAN_MSG10I D3 1EA5H 75H 00E 5[...]

EPA2_TI ME † 1F6AH 7B H 00EA H 3DH 00EAH 1EH 00EAH EPA3_TI ME † 1F6EH 7B H 00EE H 3DH 00EEH 1EH 00EEH EPA8_TI ME † 1F82H 7CH 00E2H 3EH 00C2H 1FH 0082H EPA9_TI ME † 1F86H 7CH 00E6H 3EH 00C6H 1FH 0086H EPAIPV 1FA8H 7DH 00E8H 3EH 00E8H 1F H 00A8H P1_DIR 1FD2H 7EH 00F2H 3FH 00D2H 1FH 00D2H P2_DIR 1FCBH 7EH 00EBH 3FH 00CBH 1FH 00CBH P6_DIR 1FD3H[...]

4 Standard and PTS Interrupts[...]

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4-1 CHAPTER 4 STANDARD A ND PTS INTERRUPTS 4.1 INTERRUPT SOURCES, VECTORS, AND PRIORITIE S The interr upt structure of the 87C19 6CB is the same as that of the 8XC196 NT. The only differ- ence is that INT13 , which was re served on the 8XC196NT, suppo rts the CAN peripheral. Table 4-1 lists the 87C196CB’s interrupts sources, def ault priorities ([...]

87C196CB SUPPLEMENT 4-2 INT_MASK 1 Address: Reset St ate : 0013H 00H The interrupt mask 1 (INT_MA SK1) register enables or disables (mask s) individual interrupt reques ts. (The EI and DI instruc tions enable and disable servicing of all m askable interrupts .) INT_MASK1 can be read from or written to as a byte register. PU SHA saves this regist er[...]

5 I/O Ports[...]

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5-1 CHAPTER 5 I/O POR TS 5.1 PORT 0 AND EPORT The I/O por t s of the 87C19 6CB are functionally identically to those of th e 8XC196NT. However, the 87C1 96CB implements all eight pins of p ort 0, and the 100 -pin 87C196CB also implements all eight pins of the EPORT. The associated registers have been modified to include bits cor re- spondin g to th[...]

5-2 87C196CB SUPPLEMENT EP_DIR Address: Reset Stat e: 1FE3H FFH In I/O mod e, each bit of the extended port I/O direct ion (EP_DI R) register contr ols the direct ion of the corresponding pin. Clearing a bit conf igures a pin as a complementary outpu t; setting a bit configures a pin as either an input or an open-drain output. (Open-drain output s [...]

5-3 I/O PORTS EP_PIN Address: Reset Stat e: 1FE7H XXH Each bit of the exten ded port input ( EP_PIN) r egister reflects t he current s tate of the corresponding pin, regardless of the pin configuration. 7 0 PIN7 PIN6 P IN5 PIN4 PI N3 PI N2 P IN1 PIN0 Bit Numbe r Bit Mnemonic Fu nction 7:0 PIN7:0 Extended Address Port Pin x Input This bit contains t[...]

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6 Analog-to-digital ( A/D) Converter[...]

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6-1 CHAPTER 6 ANALOG- TO-DIGIT AL ( A/D) CO NVERTER 6.1 ADDITIONAL A/D INPUT CHAN NELS The 87C196CB’s A/D converter is functio nally identical to that of the 8XC196NT, but it has eight analog input channels instead of four. Table 6 -1 lists the A/D signals. Figure 6-1 describ es the comma nd register and Figure 6-2 describes the result r egister.[...]

87C196CB SUPPLEMENT 6-2 AD_COMMAND Address: Reset Stat e: 1F ACH C0H The A/D command ( A D_CO M MAN D) register selects the A/D channel number t o be converted, controls whether the A/D convert er start s imm ed iately or w ith an EPA command, and se lects the conversion mode. 7 0 — — M1 M0 GO ACH2 ACH1 ACH0 Bit Numbe r Bit Mnemonic Fu nction 7[...]

6-3 ANALOG-TO-DIGITAL ( A/D) CONVERTER AD_RESULT ( Read) Address: Reset Stat e: 1FA AH 7F80H The A/D resu lt ( AD_RESU LT) register consis ts of two bytes. The high byte cont ains the e ight most- significant bits from the A/ D convert er. The low byte conta ins the two least-significant bits from a ten- bit A/D conv ersion, indicates t he A/D chan[...]

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7 CAN Serial Communications Controller[...]

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7-1 CHAPTER 7 CAN SERIAL COMMUN ICAT IONS CON TRO LL ER The 87C196CB has a peripheral n ot found in the 8XC196NT — the CAN (co ntroller area net- work) p eripheral. The CAN serial communications con troller manages co mmunications between multiple network no des. This integrated peripheral is s imilar to Intel’s standalone 82 527 CAN serial com[...]

87C196CB SUPPLEMENT 7-2 This bus co nfiguration reduces point-to-p oint wiring requ irements, making the CAN controller well suited to auto motive and f actory autom ation ap plications. In ad dition, it relieves the C PU of much o f the communications b urden while providin g a high level of d ata integrity throug h error management logic. The CAN[...]

7-3 CAN SERIAL COMMUNICATIONS CONTROLLER 7.2 CAN CONTROLLER SIGNALS AND REGISTERS Table 7-1 describes the CAN con troller’s pins, and Table 7-2 describes the contro l and status reg- isters. Table 7 -1. CAN Controller Sign als Signal Type Description RXCAN I Receive This signal carries messages from other nodes on the CAN bus to the CAN controlle[...]

87C196CB SUPPLEMENT 7-4 7.3 CAN CONTROLLER OPERATION This sectio n describes the address map , message obje cts, message frames (which contain mes- sage objects), er ror detection and managemen t logic, and bit timing for CAN transmissions and receptions. CAN_MSG x CON1 1E y 1H Messag e Object x Control 1 Program t his register to indicat e that a [...]

7-5 CAN SERIAL COMMUNICATIONS CONTROLLER 7.3.1 Addres s Map The CAN controller ha s 256 bytes of RAM, contain i ng 15 message objects and control and s tatus registers at fixed addresses. Each message o bject occupies 15 con secutive bytes beginning at a base address that is a multiple of 16 bytes. The b yte above each message object is reserved ( [...]

87C196CB SUPPLEMENT 7-6 7.3.2 .1 Receive a nd Transmit Prio rities The lowest-numbered message object always has the high est priority, re gardless of the message identifier. When multip le messages are ready to transmit, the CAN controller transmits the mes- sage from the lowest-numbered message object first. When multiple message objects are capa[...]

7-7 CAN SERIAL COMMUNICATIONS CONTROLLER 7.3.3 Mes sage Frame s A message object is co ntained within a message frame that add s control a nd error-d etection bits to the content of the message object. The f rame for an extended message differs slightly from that for a standard messag e, but they contain similar information. A data frame contains a[...]

87C196CB SUPPLEMENT 7-8 Table 7-6 . Standard Mess age Frame Field Description Bit Count SOF Start-of-fr ame. A dominant (0) bit marks the beginning of a message fram e. 1 Arbitrati on 11-bit message identifier. 12 RTR. Remote transm ission request. Dominant (0) for data frames; recessive (1) for remot e frames. Control IDE. Ident ifier extensio n b[...]

7-9 CAN SERIAL COMMUNICATIONS CONTROLLER 7.3.4 Error D etection and Management Logic The CAN contro ller has several error d etection mechanisms, includ ing cyclical redundancy checking (CRC) and bit cod ing rules (stuf fing and destuff ing). Th e CAN controller g enerates a CRC code f or transmitted messages and ch ecks the CRC code of inco ming m[...]

87C196CB SUPPLEMENT 7-10 7.3.5 Bit Timing A message object consists of a series of bits transmitted in consecutive bit times. The CAN pro- tocol specifies a bit time com posed of four separate, no noverlapping time segments: a synchro- nization de lay se gment, a pro pagatio n de lay se gment, and two pha se d elay segmen ts ( Figure 7-4 and Table [...]

7-11 CAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-5. A Bit Time as Impleme nted in the CAN Con troller Table 7-9 . CAN Controller Bit Time Segments Symb ol Defin itio n t SYNC _ SEG This tim e segment is equivalent to SYNC_SEG in the CAN protocol. Its length is one time quantum . t TSEG 1 This time segment is equivalent to the sum of PROP_SE G and[...]

87C196CB SUPPLEMENT 7-12 7.3.5 .1 Bit Timing Equations The bit timing eq uations of the integrated CAN contr oller are equivalent to tho se for the 82527 CAN peripheral with the DSC bit in the CPU interface register set (system clock divided by two). The following equations show the timing calculations for the in tegrated CAN controller and the 825[...]

7-13 CAN SERIAL COMMUNICATIONS CONTROLLER 7.4 CONFIGURING THE CAN CON TROLLER This section explain s how to configur e the CAN controller. Several registers combine to control the configu ration: the CAN control register, the two bit timing registers, and the three mask reg- isters. 7.4.1 Programming the C AN Control (CAN_CON) Register The CAN cont[...]

87C196CB SUPPLEMENT 7-14 1 IE Interr upt Enable This bit globally enables and di sables interrupt s (error, status -change, and message object transmit and receive interrupts) . 0 = disable interrupts 1 = enable interrupts When the IE bit is set, an interrupt is generated only if the corresponding interrupt source’s enable bit (EIE or SIE in CAN_[...]

7-15 CAN SERIAL COMMUNICATIONS CONTROLLER 7.4.2 Pro gramming the Bit Timing 0 (CAN_BTIME 0) Register Bit timing register 0 ( Figure 7-7) defines the length of one time quan tum and the maxim um amount by which the samp le point can be moved (t TS EG 1 or t TS EG 2 can be sho rtened and the other lengthened ) to compensate for resynch ron izatio n. [...]

87C196CB SUPPLEMENT 7-16 7.4.3 Pro gramming the Bit Timing 1 (CAN_BTIME 1) Register Bit timing register 1 (Figure 7-8 ) controls the time at which the bus is sampled and the number of samples taken. In s ingle-sample mode, the bu s is sampled once and the value of that sample is considered valid. In three-samp le mode, the bus is sampled three time[...]

7-17 CAN SERIAL COMMUNICATIONS CONTROLLER 7.4.4 Pro gramming a Message Acceptance Filter The mask registers prov ide a method f or developing an acceptance filtering strategy . Without a filtering strategy, a messa ge ob ject could accept an incomin g message only if their identifier s were identica l. T he mask register s allow a message object to[...]

87C196CB SUPPLEMENT 7-18 CAN_SG MSK (87C196CB) Address: Reset State: 1E07H, 1E06 H Unchanged Program the CAN standard global mask (CAN_S G MSK) regist er to mask (“don’t care”) specific message identifier bits for standard mes sage objects. 15 8 87C196CB MSK20 M SK19 MSK18 — — — — — 7 0 MSK28 MSK27 MSK26 MSK25 MS K24 MSK23 MSK22 MS [...]

7-19 CAN SERIAL COMMUNICATIONS CONTROLLER CAN_EG MSK (87C196CB) Address: Reset State: 1E0BH, 1E 0AH, 1E09H, 1E08H Unchanged Program the CAN extended global mask (CAN_E GMSK ) register to mask (“don’t care”) specific message identifier bits for extended mess age objec ts. 31 24 87C196CB MSK4 MSK3 MSK2 MS K1 MSK0 — — — 23 16 MSK12 MSK11 M[...]

87C196CB SUPPLEMENT 7-20 7.5 CONFIGURING MESSAGE OBJE CTS Each message object consists of a con figuration register, a message iden tifier, con trol registers, and data registers (fr om zero to eight bytes of data). This section explains how to conf igure mes- sage objects and determine their status. CAN_MSK15 † (87C196CB) Address: Reset State: 1[...]

7-21 CAN SERIAL COMMUNICATIONS CONTROLLER 7.5.1 Spec ifying a Message Obje ct’s Configuration Each message object conf iguration register (Figure 7-1 2) specifies a message identifier type (standard or extended ), transfer dir ection (transmit or receive), and d ata length (in b ytes). Set the XTD bit for a message object with an extended iden ti[...]

87C196CB SUPPLEMENT 7-22 7.5.2 Pro gramming the Message Obje ct Identifier Each message identifier register (Figure 7-13) specifies the message’s identifier. For messages with extend ed identifiers, write the identifier to bits ID28:0. For m essages with standard identi- fiers, write the id entifier to bits ID28:1 8. Software can chang e the iden[...]

7-23 CAN SERIAL COMMUNICATIONS CONTROLLER 7.5.3 Pro gramming the Message Obje ct Control Registers Each message object contro l register consists of four bit pairs — one bit of each pair is in true form and one is in com plement form . This format allo ws software to set or clear any bit with a single write oper ation, witho ut affecting the rema[...]

87C196CB SUPPLEMENT 7-24 CAN_MSG x CON0 x = 1–15 (87C196CB) Address: Reset State: 1E x 0H ( x = 1–F) Unchanged Program t he CAN message object x control 0 (CAN_MSG x CON0) register to indicate whether the message object is ready to transmit and to contro l whether a success ful tran smiss ion or reception generates an interrupt. The least-signi[...]

7-25 CAN SERIAL COMMUNICATIONS CONTROLLER 3:2 RXIE Rece ive Interrupt Enable Transmit mes sage ob jects do not use this bit-pair. For a receive message object, set this bit-pair to enable this message object to initiate a receive (RX) interrupt aft er a successful recept ion. You must also set the interr upt enable bit (CAN_CON.1) t o enable the in[...]

87C196CB SUPPLEMENT 7-26 CAN_MSG x CON1 x = 1–15 (87C196CB) Address: Reset Stat e: 1E x 1H ( x = 1–F ) Unchanged The CAN message object x control 1 (C AN_MSG x CON1) regist er indicates whet her a messa ge object has been updated, whether a message has been overwritt en, whether the CPU is updating the message, and whether a transmission or rec[...]

7-27 CAN SERIAL COMMUNICATIONS CONTROLLER 3:2 MSGLST or CPUUPD Message Lost (Receive) For a receive message object, the CAN controller sets this bit-pair to indicate that it stored a new message while the NEWDAT bit-pair was still set, overwriting the previous message. bit 3 bit 2 0 1 no overwrite occurr ed 1 0 a message was lost (overwritt en) CPU[...]

87C196CB SUPPLEMENT 7-28 CAN_MSG x DATA0–7 x = 1–15 (87C196CB) Address: Reset Stat e: 1E x EH, 1E x DH, 1E x CH, 1E x BH, 1E x AH, 1E x 9H, 1E x 8H, 1E x 7H ( x = 1–F) Unchanged The CAN message object data (CAN_MSG x DATA0–7) regist ers contain data to be transmitted or data received. Any unused data bytes have random va lues that change du[...]

7-29 CAN SERIAL COMMUNICATIONS CONTROLLER 7.6 ENABLING THE CAN INTE RRUPTS The CAN con troller has a single interrupt in put (INT13) to the interru pt controller. (Gen erally, PTS interrupt service is no t useful for the CAN con troller because the PTS canno t readily deter- mine the sour ce of the CAN con troller’s multip lexed interr upts.) To [...]

87C196CB SUPPLEMENT 7-30 1 IE Interr upt Enable This bit globally enables and di sables interrupt s (error, status -change, and message object transmit and receive interrupts) . 0 = disable interrupts 1 = enable interrupts When the IE bit is set, an interrupt is generated only if the corresponding interrupt source’s enable bit (EIE or SIE in CAN_[...]

7-31 CAN SERIAL COMMUNICATIONS CONTROLLER When the SIE bit in the CAN control r egister is set, the CAN controller g enerates a successful reception (RXOK) interrupt req uest each time it receives a valid message, even if no message ob- ject accepts it. If you set both the SIE bit (Figure 7-1 7) and an individual message object’s RXIE bit (Figure[...]

87C196CB SUPPLEMENT 7-32 7.7 DETERMINING THE CAN CONTROLLER’S I NTERRUPT STATUS A successful reception or transmission or a change in the s tatu s regi ster can cause the CAN con- troller to g enerate an interr upt request. The INT_PEND1 r egister (see Table 7 -2 on p age 7 -3) in- dicates whether a CAN interr upt req uest is pending . The CAN in[...]

7-33 CAN SERIAL COMMUNICATIONS CONTROLLER If an individual message object caused the interr upt request (CAN_INT = 02–10H), software can read the associated message object control 0 register (Figu re 7-21). The INT_PND bit-pair will be set, indicating that a receive or transmit interru pt request is pendin g CAN_ST AT (87C196CB) Address: Reset St[...]

87C196CB SUPPLEMENT 7-34 . CAN_MSG x CON0 ( n = 1–15) Address: 1 E x 0H ( x =1–F) Reset State: Unchanged Program t he CAN mess age object x control 0 register (CAN_MS GxCO N0) to indicat e whet her the message object is ready to transmit and to control whether a success ful trans miss ion or reception generates an interrupt. The most -significa[...]

7-35 CAN SERIAL COMMUNICATIONS CONTROLLER 7.8 FLOW DIAGRAMS The flow diagrams in this section describe the s teps that your software (shown as CPU) and the CAN controller e xecute to receiv e and transmit messages. Table 7-13 lists the reg ister bits shown in the d iagrams along with their a ssociated registers and a cross-reference to the figure t[...]

87C196CB SUPPLEMENT 7-36 Figure 7-22. Recei ving a Messag e for Messag e Objects 1–1 4 — CPU Flow (All bits undefined) NEWDAT := 0 Process message contents. NEWDAT = 1? Request update? TX_REQ := 1 Power Up Initialization Process Yes No No Yes Restart Process A2594-01 MSGVAL INT_PND TXIE RXIE := 1 := 0 := (Application specific)[...]

7-37 CAN SERIAL COMMUNICATIONS CONTROLLER Figure 7 -23. Receivi ng a Message for Message Objec t 15 — CPU Flow (All bits undefined) NEWDAT := 0 and RMTPND := 0 Process message contents. NEWDAT = 1? Power Up Initialization Process No Yes Restart Process A2597-02 MSGVAL INT_PND RXIE  := 1 := 0 := (Application specific) NEWDAT R[...]

87C196CB SUPPLEMENT 7-38 Figure 7-24. Recei ving a Messag e — CAN Controller Flow NEWDAT := 0 Load identifer and control into buffer Send remote frame Transmission successful? TXIE = 1? INT_PND := 1 TX_REQ := 0 RMTPND:= 0 TX_ REQ= 1 ? MSGLST =0? Bus idle? Received frame with same identifer as this message object? RXIE = 1? IN[...]

7-39 CAN SERIAL COMMUNICATIONS CONTROLLER Figure 7 -25. Transmi tting a Message — CPU Flow (All bits undefined) CPUUPD := 1 NEWDAT := 1 Want to send? TX_REQ := 1 Power Up Initialization Update Yes No Yes Update message? CPUUPD := 0 Write/calculate message contents. A2596-01 MSGVAL INT_PND TXIE RXIE  := 1 := 0 := (Applicati[...]

87C196CB SUPPLEMENT 7-40 Figure 7-26. Transm itting a Messag e — CAN Controller Flow NEWDAT := 0 Load message into buffer Send message Transmission successful? NEWDAT = 1 ? TXIE = 1? INT_PND := 1 TX_REQ := 0 RMTPND := 0 TX_REQ= 1? CPUUPD= 0? Bus free? Received remote frame with same identifer as this message object? TX_REQ :=[...]

7-41 CAN SERIAL COMMUNICATIONS CONTROLLER 7.9 DESIGN CONSIDE RATIONS This section outlines design considerations for the CAN controller . 7.9 .1 Hardwa re Reset A hardware reset clear s the error man agement coun ters and the bus-off state and leaves the reg- isters with the values listed in Table 7-14. 7.9 .2 Software Initialization The software i[...]

87C196CB SUPPLEMENT 7-42 The CAN contr oller synchronizes itself to the CAN b us by waiting for 12 8 bus idle states (128 occurrences of 1 1 consecutive recessive bits) before participating in bus activities. During this sequence, th e CAN controller writes a bit 0 error co de to the LEC2:0 bits of the status reg ister each time it receiv es a rece[...]

8 Special Operating Modes[...]

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8-1 CHAPTER 8 SPECIAL O PERATING MODES 8.1 CLOCK CIRCUITRY The 87C196CB’s idle, powerd own, and ONCE modes are the same as those o f the 8XC196NT. The only differen ce is in the way that the power saving modes disable the clock circuitry (Figure 8-1). Figure 8- 1. Clock Circuitry A3168-01 Clock Generators CPU Clocks (PH1, PH2) Divide-by-two ?[...]

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9 Interfacing with External Memory[...]

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9-1 CHAPTER 9 INTERFACIN G WITH EXTERNAL MEMO RY The 87C1 96CB’s external memory interface is similar to that of the 8XC196NT. However, the 87C196CB su pports only two of the bus timing mo des, modes 3 and 0. In addition, the 100-pin 87C196CB has four ad ditional address pins ( A23:20). 9 .1 ADDRE SS PINS The 100-p in 87C1 96CB has 24 available a[...]

87C196CB SUPPLEMENT 9-2 Figure 9-1 . Modes 0 and 3 Timings A0809-01 t CLKOUT ALE AD15:0 RD# ALE RD# MODE 3 MODE 0 T RLDV = 1t T AVDV = 3t T RLDV = 3t T AVDV = 5t T RHDZ = 1t Data Data Address Address Data Data Data Address Address Address T RHDZ = 1t AD15:0 Data Data[...]

9-3 INTERFACING WITH EXTERNAL MEMORY CCR1 no direct access † The chip configuration 1 (CCR1) register enables the wat chdog tim er and selects the bus timing mode. Tw o of its bits combine with three bits o f CCR0 to contr ol wait states and bus width. Another bit contro ls whether CCR2 is loaded. 7 0 MSEL1 M SEL0 0 1 WDE BW1 IRC2 LDCCB2 Bit Numb[...]

87C196CB SUPPLEMENT 9-4 1 IRC 2 Ready Control This bit, along with IRC0 (CCR0.4) and IRC1 (CCR0.5), limits the number of wait states that can be inserted while the READY pin is held low. Wait states are insert ed into the bus cyc le either until the RE ADY pin is pulled high or until this internal number is reached. IRC2 IRC1 IRC0 0 0 0 zero wait s[...]

10 Programming the Nonvolatile Memory[...]

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10-1 CHAPTER 10 PROGRAMMIN G THE NONVO LATILE MEMO RY The 87C196CB ha s 56 Kbytes of OTPROM (FF2000–FFFFFFH), while the 8XC196NT has only 32 Kbytes (FF2000–FF9FFFH). The 87C19 6CB’s programming signals, registers, and proce- dures are the same as those o f the 8 XC196NT. T his chapter describes the d if feren ces in memo ry mapping and progra[...]

10-2 87C196CB SUPPLEMENT 10.3 MEMORY MAP AND CIRCUIT FOR AUTO PROGRAMM ING Because the 87C196CB has an a dditional 24 Kbytes of OTPROM, its auto programming memo ry map (Table 10-3) and circuit (Figure 10-1) differ from those of the 8XC196NT. Table 1 0-2. Slave Programming Mode Memory Map Description Address Com ments OTPROM FF2000–FFFFFFH OTPR O[...]

10-3 PROGRAMM ING THE NONVOLATILE MEMORY Figure 10-1. Auto Progra mming Circuit 10.4 MEMORY MAP FOR SERIAL PORT P ROGRAMMING The 87C196CB’s memory map (Table 10-4) for ser ial port pro gramm ing differs from that of the 8XC196NT. Th e remaining information o n serial port programmin g is correct fo r the 87C196CB. 270k Ω +5.0V XTAL1 20 pF 20 pF[...]

10-4 87C196CB SUPPLEMENT The lower 24 Kbytes of OTPROM (FF2000–FF7FFFH) are remappe d to A00 0–FFFFH, and the upper 32 Kbytes (FF8000–FFFFFFH) are mapped to 8000–FFFFH. A b ank switc hing m echa- nism differ entiates between the two address ranges. Th e most-significant bit of an o therwise re- served by te register (location 1FF9H) selects[...]

A Signal Descriptions[...]

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A-1 APPENDIX A SIGNAL DESCR IPTIONS A.1 FUNCTIONAL GROUPINGS OF SIGNALS Table A-1 lists the signals for the 87C196CB, grouped by functio n. A diagram of each package that is cu rrently available shows the pin locatio n of each signal. NOTE As new packages are supp orted, they will be added to th e datasheets first. If your package typ e is not sh o[...]

87C196CB Supplement A- 2 Figure A-1. 8 7C196CB 84-pin PLCC Package PLLEN P6.3 / T1DIR P6.2 / T1CLK P6.1 / EPA9 / COMP1 P6.0 / EPA8 / COMP0 P1.0 / EPA0 / T2CLK P1.1 / EPA1 P1.2 / EPA2 / T2DIR P1.3 / EPA3 P1.4 / EPA4 P1.5 / EPA5 P1.6 / EPA6 P1.7 / EPA7 V SS1 V CC V REF ANGND P0.7 / ACH7 / PMODE3 P0.6 / ACH6 / PMODE2 P0.5 / ACH5 / PMODE1 P0.4 / ACH4 /[...]

A-3 SIGNAL DESCRIPTIONS Figure A-2. 87C196CB 100-pin QFP Package A.2 SIGNAL DESCR IPTIONS T able A-2 defines the columns used in T ab le A-3, which descri bes the signals. P5.7 / BUSWIDTH P5.2 / WR# / WRL# / SLPWR# P5.5 / BHE# / WRH# P5.3 / RD# / SLPRD# A20 / EPORT.4 A21 / EPORT.5 A22 / EPORT.6 V PP A23 / EPORT.7 P5.0 / ADV# / ALE / SLPALE P5.1 / I[...]

87C196C B Supplement A-4 Table A-2. Description of Columns of Table A-3 Column Headi ng Descripti on Name Lists the signals, arranged alphabet ically. Many pins have t wo functions, so there are more entries in this column than there are pins. Ever y signal is listed in this column. Type Identifies the pin function listed in the Name column as an i[...]

A-5 SIGNAL DESCRIPTIONS ADV# O Addre ss Valid This active-low output signal is asserted only during externa l memory accesses. ADV # indicates that valid address informat ion is available on the system address/ data bus. The signal remains low while a valid bus cycle is in progress and is returned high as soon as the bus cycle completes. An externa[...]

87C196C B Supplement A-6 BREQ# O Bus Request This active-low output signal is asserted during a hold cycle when the bus controller has a pending exter nal memory cycle. The device can assert BREQ # at the same time as or after it asserts HLDA# . Once it is asserted, BREQ# rem ains assert ed until HOLD# is remov ed. You must enable the bus-hold prot[...]

A-7 SIGNAL DESCRIPTIONS EA# I External Acc ess This input determines whether mem ory acc esses to special-purpose and program memory partit ions (FF2000–F F 9FF FH) are directed to internal or external memory. These acces ses are direct ed to internal memor y if EA# is held high and to external memor y if EA# is held low. For an access to any oth[...]

87C196C B Supplement A-8 HLDA# O Bus Hold Acknowledge This active-low output indicates that the CPU has released the bus a s the result of an external device asserting HOLD# . HLDA# is multiplexed with P2.6 and CPVER. HOLD# I Bus Hold Request An external device uses this act ive-low inpu t signal to request control of the bus. This pin functions as[...]

A-9 SIGNAL DESCRIPTIONS P0.7:0 I Port 0 This is a high-impedanc e, input-only por t. Port 0 pins should no t be left floating. These pins may individually be used as analog inputs ( ACH x ) or digital inputs (P0. x ). While it is possible for the pins t o function simultaneously as analog and digital inputs, this is not recomm ended because reading[...]

87C196C B Supplement A-10 P6.7:0 I/O Port 6 This is a s tandard 8-bit bidirec tional port. Port 6 is multiplexed as follows: P6.0/EPA 8/CO M P0, P6.1/EP A9/ CO MP 1, P6.2/T1CLK , P6.3/T1DI R, P6. 4/SC0, P6.5/ SD0, P6.6/SC 1, and P6.7/ SD1. PACT# O Programming Activ e During auto programming or ROM-dum p, a low signal indicates that programming or d[...]

A-11 SIGNAL DESCRIPTIONS PROG# I Programm ing Start During programming, a falling edge latches data on the PBUS and begins programming, while a rising edge ends programming. The current location is programmed with the same data as lon g as PROG# rem a ins asserted, so the data on the PBUS must remain stab le while PROG # is active. During a word du[...]

87C196C B Supplement A-12 SD1:0 I/O Data Pins for SSIO 0 and 1 SD0 is multiplexed with P6.5, and SD1 is multiplexed with P6.7. SLP7:0 I/O Slave Port Address/Data bus Slave port address/data bus in multiplexed mode and slave port dat a bus in demultiplexed mode. In multiplexed mode, SLP1 is the source of the internal control signal, SLP_A DDR. SLP7:[...]

A-13 SIGNAL DESCRIPTIONS T2DIR I Timer 2 External Directi on External direction (up/ down) for timer 2. Timer 2 increments when T2DIR is high and decrements when it is low. A lso used in conjunct ion with T2CLK for quadrature counting mode. T2DIR is multiplexed with P1.2 and EPA2 . TXCAN O T ransm it This signal carries mess ages from the integrate[...]

87C196C B Supplement A-14 A.3 DEFAULT CONDITIONS Table A-5 lists the default fun ctions of the I/O and co ntrol pins of the micro controller with their values during various oper ating conditions. Tab le A-4 defines the symbols used to represent the pin status. Refer to the DC Characteristics table in the d atasheet for actual specifications fo r V[...]

A-15 SIGNAL DESCRIPTIONS P2.2 EXTINT WK1 (Note 3) (Note 3) P2.3 BREQ# W K1 (Note 3) (Note 3) P2.4 INTOUT# WK1 (Note 3) (Not e 3) P2.5 HOLD# W K1 (Note 3) (Note 3) P2.6 HLDA# WK1 (Note 3) (Not e 3) P2.7 C LKOUT CLK OUT act ive, LoZ0/1 (Not e 3) (Not e 4) P3.7:0 A D7:0 WK1 (Note 6) (Not e 6) P4.7:0 A D15: 8 WK1 (Note 6) (Not e 6) EPORT.3: 0 AD19:1 7 [...]

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Glossary[...]

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Glossary -1 GLOSS ARY This glossary def in es acron yms, ab brev iations, and te rms that hav e special meanin g in thi s man- ual. (Chapter 1 d iscusses notational conventions and general termino logy.) absolute error The m aximum differen ce between corr espond ing actual and ideal code transitions . Ab solute error accounts fo r all deviations o[...]

Glossary -2 87C196CB SUPPLEMENT CAN Controller ar ea network. The 87C196CB’s integrated networkin g periph eral, similar to Intel’s standalone 82527 CAN serial communications con troller, that supports CAN spec ification 2.0. CCBs Chip configuration by tes. The chip configuration registers ( CCRs ) are loaded with the contents of the CCBs after[...]

Glossary -3 GLOSSARY code width Th e voltage chan ge correspon ding to th e difference between two ad jacent code transitions . Code width deviations cause differential nonlinearity and nonlin- earity errors. crossta lk See off-isolation. DC input leakage Leakage cu rrent fro m an analog input pin to ground. deassert The act of making a signal inac[...]

Glossary -4 87C196CB SUPPLEMENT FET Field-effect transistor. frequency genera tor The 8XC196MD periph eral that generates o utputs with a fix ed 50% duty cycle an d a progr ammable frequ ency. The frequency generator can be u sed for infrared transmission. full-scale error Th e difference between th e ideal and actual input voltage corr esponding t[...]

Glossary -5 GLOSSARY ISR See interrupt service routine. linearity errors See differential nonlinea rity and nonlinearity . LONG-INTEGER A 32-bit, s igned variab le with values fro m –2 31 throug h +2 31 –1. LSB 1) Least-significant bit of a byte or least-s ignificant byte of a word. 2) In an A/D converter, the r eference voltag e divided by 2 n[...]

Glossary -6 87C196CB SUPPLEMENT nonlinearity The maximum deviation of code tran sitions of the terminal-based characteristic from th e corre- sponding code transitions of the idea l characteristic . nonmaskable interrupts Interrupts that can not be masked (disabled) and cannot be as signed to the PTS for processing. The nonm askable interrupts are [...]

Glossary -7 GLOSSARY prioritized interrupt Any maskable in terrupt o r nonmaskab le NMI. Two of the n onmaskable interrupts (unim plemented opcode and software trap) are not prioritized; th ey vector directly to the interrupt service routine wh en executed. program memory A partition of memory where instructions can be stored for fetching and execu[...]

Glossary -8 87C196CB SUPPLEMENT PTS transfer The mo vement of a single b yte or word from the source memo ry location to the d estination memo ry location. PTS vector A location in special-purp ose memory that holds the starting address of a PTS control block . PWM Pulse-width modulated (outputs). The 8XC196M x devices have several options for prod[...]

Glossary -9 GLOSSARY sample delay The time period between th e time that A/D converter receives th e “start con version” signal an d the time that the sample capacitor is connected to the selected channel. sample delay un certainty The variation in the sample dela y . sample time The period of time that the sample win dow is open. ( That is, th[...]

Glossary -10 87C196CB SUPPLEMENT source current Current flowing out of a device from V CC . Always a negative va lue. SP Stack pointer. special interrupt Any of the three no nmaskable interrupts (un imple- mented o pcode, software trap, o r NMI). special-purpose mem ory A partition of memor y used for storing the in terrupt vectors , PTS vectors , [...]

Glossary-1 1 GLOSSARY transfer function errors Errors inh erent in an analog -to-digital conv ersion process: qua ntizing error , zero-offset error , full-scale error , differential nonlinearity , and n onlinearity . Error s that are hard ware-dep endent, rather th an being inherent in the process it self, include feedthroug h , repeatability , cha[...]

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Index[...]

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Index -1 A A/D converter, signals, 6-1 AD_COMM AND register, 6-2 AD_RESUL T register, 6-3 Auto programming mode circuit, 10-3 memory map, 10-2 B Block diag r am CAN perip heral, 7-2 clock circu itry, 2-2 core an d peripherals, 2-2 Bus-timin g modes, 9-1 –9-2 comparison , 9-1 , 9-2 C CAN serial com munications cont roller, 7-1– 7-42 address map,[...]

87C196CB SUPPLEMENT Inde x-2 P P0_PIN register, 5-1 Period (t), 2-4 Pin diag ra ms, A-1 Pins, reset status, A-14–A-15 Port 0, 5-1 Powerd own mode, pin status, A-14 R Registers AD_COMM AND, 6-2 AD_RESUL T, 6-3 CAN_BTIM E0, 7-3, 7-15 CAN_BTIM E1, 7-3, 7-16 CAN_CON, 7-3 , 7-13, 7-29 CAN_EGMS K, 7-3, 7-19 CAN_INT, 7-3, 7-32 CAN_MSG x CF G, 7-3, 7 -21[...]