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Intel CM8064601466200 manual

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  • Page 1

    Reference Numbe r: 328899-007 Desktop 4th Generation Intel ® Core™ Processor Family, Desktop Intel ® Pentium ® Processor Family, and Desktop Intel ® Celeron ® Processor Family Specification Update December 2013 Revision 007[...]

  • Page 2

    2 Specification Update INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WI TH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER WISE, TO ANY INTELLECTUAL PROPERTY RI GHTS IS GRANTED BY THIS DOCUMENT . EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FO R SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHA TSOEVER [...]

  • Page 3

     Contents Specification Update 3 Contents Revision History ................ ............ ................. ............. ............ ................. ............ ............ 5 Preface .................. ............. ................ ............. ............. ................ ............. ................ ........ 6 Summary Tables of Chan[...]

  • Page 4

    Contents 4 Specification Update[...]

  • Page 5

     Specification Update 5 Revision History Revision Description Date 001 • Initial Release. June 2013 002 • No Updates. R evision number added to Revision History to maintain consistency with NDA Specificat ion Update numbering. N/A 003 •E r r a t a — Added HSD59-99 • Updated Identification Info rmation August 2013 004 • No Updates. R [...]

  • Page 6

    6 Specification Update Preface This document is an update to the specifications contained in the Affected Documents table below . This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications , operating system s, [...]

  • Page 7

     Specification Update 7 Nomenclature Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and softw are designed to b e used with any giv en stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code use[...]

  • Page 8

    8 Specification Update Summary Tables of Changes The following tables indicate the errata , specification changes, specification clarifications, or documentation changes which apply to the processor . Intel may fix some of the errata in a fu ture stepping of the component, and account fo r the other outstanding issues through documentation or speci[...]

  • Page 9

     Specification Update 9 Errata (Sheet 1 of 5) Number Steppings Status ERRATA C-0 HSD1 XN o F i x LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in 64-bit Mode HSD2 XN o F i x EFLAGS Discrepancy on Page Faults and on EPT -Induced VM Exits after a T ranslation Change HSD3 XN o F i x MCi_S tatus Overflow Bit May Be I n[...]

  • Page 10

    10 Specification Update HSD26 XN o F i x S p ecific Graphic s Blitter Instruc t ions May Result in Unpredictable Graphics Controller Behavior HSD27 XN o F i x Processor May Enter Shutdown Unexpectedly on a Second Uncorrectable Error HSD28 XN o F i x Modified Compliance Patterns for 2.5 GT/s and 5 GT/s Transfer Rates Do Not Follow PCIe* Specificatio[...]

  • Page 11

     Specification Update 11 HSD55 XN o F i x Internal Parity Errors May Incorrectly Report Overflow in The IA32_MCi_ST A TUS MSR HSD56 XN o F i x Performance Monitor Events OTHER_ASSISTS.A VX_TO_SSE And OTHER_ASSISTS.SSE_TO_A VX May Over Count HSD57 XN o F i x Processor May Run at Incorrect P-St ate HSD58 XN o F i x Performance Monitor Event DSB2MI[...]

  • Page 12

    12 Specification Update HSD82 XN o F i x PCIe* Host Bridge DID May Be Incorrect HSD83 XN o F i x T ransactional Abort M ay Produce an Incorrect Branch Record HSD84 XN o F i x SMRAM S tate-Save Area Abov e the 4GB Bou ndary May Cause Unpredictable System Behavior HSD85 XN o F i x DMA Remapping Faults for the Graphics VT -d Un it May Not Properly Rep[...]

  • Page 13

     Specification Update 13 HSD110 XN o F i x A PEBS Record May Contain Processor S tate for an Unexpected Instruction HSD111 XN o F i x MSR_PP1_ENERGY_ST A TUS Reports Incorrect Energy Data HSD112 XN o F i x x87 FPU DP May be Incorrect After Instructions That Save FP S tate to Memory HSD113 XN o F i x Processor May Hang During Package C7 Exit HSD1[...]

  • Page 14

    14 Specification Update Identification Information Component Identification us ing Programmin g Interface The processor stepping can be identified by the following register contents. Notes: 1. The Extended F amily , Bits [27:20] are used in conjunc tion with the F amily Code, specified in Bits[11:8], to indicate whether the processor belong s to th[...]

  • Page 15

     Specification Update 15 Component Marking Information The processor stepping can be identified by the following component markings. Figure 1. Desktop 4th Generation Intel ® Core™ Processor Fami ly Top-Side Markings Table 2. Desktop Processor Identification (Sheet 1 of 2) S-Spec Number Processor Number Stepping Cache Size (MB) Func- tional Co[...]

  • Page 16

    16 Specification Update SR18K I7-4770R C-0 6 4 3 3.9 1600 3.2 65 SR18M I5-4670R C-0 4 4 3 3.7 1600 3 65 SR18Q I5-4570R C -0 4 4 3 3.2 1600 2.7 65 SR1BW I7-4771 C-0 8 4 2 3.9 1600 3.5 95 SR1CA I5-45 70T C -0 4 2 2 3.6 1600 2.9 35 SR1CE G3430 C-0 3 2 1 3.3 1600 3.3 65 SR1CG G3220 C-0 3 2 1 3 1333 3 65 SR1CL G3220T C -0 3 2 1 2.6 1333 2.6 35 SR1NB G34[...]

  • Page 17

     Specification Update 17 Errata HSD1. LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in 64-bit Mode Problem: An exception/interrupt ev ent should be transparent to the LBR (Last Branch R ecord), B TS (Bran ch T race Store) and B TM (Branch T race Message) mechanisms. However , during a specific boundary condition wh[...]

  • Page 18

    18 Specification Update HSD4. LER MSRs May Be Unreliable Problem: Due to certain internal processor events, updates to the LER (Last Exception R ecord) MSRs, MSR_LER_FROM_LIP (1DDH) and MSR_L ER_TO_LIP (1DEH), may happen when no update was expected. Implication: The values of the LER MSRs may be unreliable. W orkaround: None identifi ed. Status: Fo[...]

  • Page 19

     Specification Update 19 HSD8. FREEZE_WHILE_SMM Does No t Prevent Event From Pending PEBS During SMM Problem: In general, a PEBS record should be gene ra ted on the first count of the event after the counter has overflow ed. However , IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM (MSR 1D9H, bit [14]) prevents performance counters from counting during SMM ([...]

  • Page 20

    20 Specification Update HSD11. Performance Monitor Precise In struction Retired Event May Present Wrong Indications Problem: When the PDIR (Precise Distribution for Instructions Retired) mechanism is activated (INST_RETIRED.ALL (event C0H, umask valu e 00H) on Counter 1 progr ammed in PEBS mode), the processor may return wrong PEBS/PMI interrupts a[...]

  • Page 21

     Specification Update 21 HSD14. Execution of VAESIMC or VAESKE YGENASSIST With An Illegal Value for VEX.vvvv May Produce a #NM Exception Problem: The VA ESIMC and V AESKEYGENASSIST in stru ctions should produce a #UD (Invalid- Opcode) exception if the value of the vvvv field in the VEX prefix is not 1111b. Due to this erratum, if CR0.TS is “1?[...]

  • Page 22

    22 Specification Update HSD17. PCIe* Root-port Initiated Comp liance State Transmitter Equalization Settings May be Incorrect Problem: If the processor is directed to enter PCIe Polling.Compliance at 5.0 GT/s or 8.0 GT/s transfer r ate s, it should use the Link Control 2 Compliance Preset/De-emphasis field (bits [15:12]) to determine the correct de[...]

  • Page 23

     Specification Update 23 HSD21. PCIe Root Port May Not Initiate Link Speed Change Problem: The PCIe Base specification requires the upstream component to maintain the PCIe link at the target link speed or the highest speed supported by both components on the l ink, whichever is lower . PCIe root port will not initi ate the link speed change with[...]

  • Page 24

    24 Specification Update HSD24. VEX.L is Not Ignored with VCVT*2SI Instructions Problem: The VEX.L bit should be ignored for the VCVTSS2SI, VCVTSD2SI, VCVTTS S2SI, and VCVT TSD2SI instructions, however due to this erratum the VEX.L bi t is not ignored and will cause a #UD. Implication: Unexpected #UDs will be seen when the VEX.L bit is set to 1 with[...]

  • Page 25

     Specification Update 25 HSD28. Modified Compliance Patterns for 2.5 GT/s and 5 GT/s Transfer Rates Do Not Follow PCIe* Specification Problem: The PCIe controller does not produce the PCIe specification defined seque nce for the Modified Compliance Pattern at 2.5 GT/s and 5 GT/s tr ansfer rates. This err atum is not seen at 8 GT/s transfer rates[...]

  • Page 26

    26 Specification Update HSD31. MSR_PERF_STATUS May Repo rt an Incorrect Core Voltage Problem: The core operating voltage can be determined by dividing MSR_PERF_ST A TUS MSR (198H) bits [47:32] by 2^13. However , due to this erratum, this calculation may report half the actual core voltage. Implication: The core operating v oltage may be reported in[...]

  • Page 27

     Specification Update 27 HSD35. PLATFORM_POWER _LIMIT MSR Not Visible Problem: The PLA TFORM_POWER_LIMIT M SR (615H) is used to control the PL3 (power limit 3) mechanism of the processor . Due to this erratum, this MSR is n ot visible to software. Implication: Software is unable to read or write th e PLA TFORM_POWER_LIMIT MSR. If software attemp[...]

  • Page 28

    28 Specification Update HSD40. Spurious VT-d Interrupts Ma y Occur When the PFO Bit is Set Problem: When the PFO (Primary F ault Overflow) field (bit [0] in the VT -d FSTS [Fault Status] register) is set to 1, further faults sho u ld not gener ate an interrupt. Due to this erratum, further interrupts may still occur . Implication: Unexpected Invali[...]

  • Page 29

     Specification Update 29 HSD44. Display May Flicker When Package C-States Are Enabled Problem: When package C-States are enabled, the di splay ma y not be refreshed at the correct rat e. Implication: When this err atum occurs, the user may observe flickering on the display . W orkaround: It is possible for the BIOS to contain a workaround for th[...]

  • Page 30

    30 Specification Update HSD49. AVX Gather Instruction That Should Result in #DF May Cause Unexpected System Behavior Problem: Due to this erratum, an execution of a 128-bit A VX gather instruction may fail to generate a #DF (double fault) when expected . Instructions impacted by this erratum are: VGA THERDPS, VGA TH ERDPD, VGA THERQPS, VGA THERQPD,[...]

  • Page 31

     Specification Update 31 HSD53. The From-IP for Branch Tra cing May be Incorrect Problem: BT M (Branch T race Message) an d B TS (Branc h T race Store) report the “From-IP” indicating the source address of the br anch instruction. Due to this erratum, B TM and B TS may repeat the “From-IP” v alue previo usly reported. The “T o-IP” v [...]

  • Page 32

    32 Specification Update HSD58. Performance Monitor Ev en t DSB2MITE_SWITCHES.COUNT May Over Count Problem: The P erformance Monitor Ev ent DSB2MITE _SWIT CHES.C OUNT (Event A BH; Umask 01H) should count the number of DSB (Decode Stream Buffer) to MITE (Macro Instruction T ranslation Engine) switches. Due to th is erratum, the DSB2MITE_SWITCHES.COUN[...]

  • Page 33

     Specification Update 33 HSD62. Some Performance Monitor Event Counts May be In accurate During SMT Mode Problem: The performance monitor event OFFCORE_RE QUESTS_OUTST ANDING (Event 60H, any Umask V alue) should count the number of occurrences that loads or stores stay in the super queue each cycle. The performance monitor event CYCLE_ACTI VITY [...]

  • Page 34

    34 Specification Update HSD66. A PCIe* LTR Update Message May Cause The Processor to Hang Problem: If a PCIe device sends an L TR (Latency T olerance R eport) update message while the processor is in a package C6 or deeper , the processor may hang. Implication: Due to this Err atum the processor may hang if a PCIe L TR update message is received wh[...]

  • Page 35

     Specification Update 35 HSD70. IA32_VMX_VMCS_ENU M MSR (48AH) Does N ot Properly Report The Highest Index Value Used For VMCS Encoding Problem: IA32_VMX_VMCS_ENUM MSR (48AH) bits 9:1 rep ort the highest index value used for any VMCS encoding. Due to this erratum, the v alue 21 i s returned in bits 9:1 although there is a VMCS field whose encodi[...]

  • Page 36

    36 Specification Update Status: For the steppings affected, see the Summary Table of Changes . HSD74. Performance Monitoring Events Ma y Report Incorrect Number of Load Hits or Misses to LLC Problem: The following performance monitor events should count the numbers of loads hitting or missing LLC. Howev er due to this erratum, The L3_hit related ev[...]

  • Page 37

     Specification Update 37 HSD78. Certain Performance Monitoring Events May Over Count Software Demand Loads Problem: The following performance monitor events should count the number of software demand loads. However due to this err atum, they may also include requests from the Next P age Prefetcher and over count. OFFCORE_REQUESTS_OUTST AND ING.D[...]

  • Page 38

    38 Specification Update HSD82. PCIe* H ost Bridge DID May Be Incorrect Problem: The PCIe Host Bridge DID register (Bus 0; Device 0; Function 0; Offset 2H) contents may be incorrect. Implication: Software that depends on the Host Bridge DID value may not beha ve as expected. W orkaround: It is possible for the BIOS to contain a workaround for this e[...]

  • Page 39

     Specification Update 39 HSD87. Intel ® TSX Inst ructions May Cause Unpredictable System behavior Problem: Under certain system conditions, Intel TSX (T ransactional Synchronization Extensions) instructions may result in unpred ictable system behavior. Implication: Due to this erratum, use of Intel TSX may result in unpredictable be havior. W o[...]

  • Page 40

    40 Specification Update HSD92. Execution of FXSAVE or FXRSTO R With the VEX Prefix May Produce a #NM Exception Problem: Attempt to use FXSA VE or FXRSTOR with a VEX prefix should produce a #UD (Invalid- Opcode) exception. If either the TS or EM flag bits in CR0 are set, a #NM (device-not - available) exception will be r aised instead of #UD excepti[...]

  • Page 41

     Specification Update 41 HSD97. Video/Audio Distortion May Occur Problem: Due to this erratum, internal processo r operations can o ccasionally delay the completion of memory read requests enough to cause video or au dio streaming underru n. Implication: Visible artifacts such as flickering on a video device or glitches on audio ma y occur . W o[...]

  • Page 42

    42 Specification Update HSD101. Incorrect LBR Source Addres s May be Reported For a Transactional Abort Problem: If the fetch of an instruction in a transactio nal region causes a fault, a transactional abort occurs. If LBRs are enabled, the source address recorded for such a transactiona l abort is the address of the instruction being fetched. If [...]

  • Page 43

     Specification Update 43 HSD105. Warm Reset Does Not Stop GT Power Draw Problem: Due to this erratum, if GT is enabled prior to a wa rm reset, it will remain powered after the warm reset. The processor will make incorrect po wer management decis ions because it assumes the GT is not drawing p ower after a warm reset. Implication: The processor m[...]

  • Page 44

    44 Specification Update HSD109. Processor Energy Policy Sele ction May Not Work as Expected Problem: When the IA32_ENERGY_PERF_BIAS MSR (1B0H) is set to a v alue of 4 or more, the processor will try to increase the energy efficiency of T urbo mode. Howev er , this functionality is effectively disabled if the software requested P-state exceeds the m[...]

  • Page 45

     Specification Update 45 HSD113. Processor May Ha ng During Package C7 Exit Problem: Under certain internal timing conditions, th e processor might not properly exit package C7 leading to a hang. Implication: Due to this erratum, the package C7 state may not be reliable. Intel has not observed this erratum with any commercially av ailable system[...]

  • Page 46

    46 Specification Update The page fault (in #4) may report an incorrect error code and faulting linear address; these would describe the read-modify-write instruction’ s me mory access instead of that of the faulting instruction. (The address of the faulting instruction is reported correctly .) Implication: The erratum makes it appear that th e pa[...]

  • Page 47

     Specification Update 47 Specification Changes The Specification Changes listed in this section apply to the following documents: •I n t e l ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture •I n t e l ® 64 and IA-32 Arch itectures Softwa re Develope r’s Manual, Volume 2A: Instruction Set Reference [...]

  • Page 48

    48 Specification Update Specification Clarifications The Specification Clarifications listed in this section may apply to the following documents: •I n t e l ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture •I n t e l ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set[...]

  • Page 49

     Specification Update 49 Documentation Changes The Documentation Changes listed in this section apply to the following documents: •I n t e l ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture •I n t e l ® 64 and IA-32 Arch itectures Softwa re Develope r’s Manual, Volume 2A: Instruction Set Reference [...]

  • Page 50

    50 Specification Update § § Display Family Display Model Display Family Display Model Display Family Display Model Display Family Display Model 0F_xx 06_1C 06_1A 06_1E 06_1F 06_25 06_26 06_27 06_2C 06_2E 06_2F 06_35 06_36[...]