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Intel Xeon 7041 manual

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Table of contents for the manual

  • Page 1

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet Revision 2.1 September 2006 Document Number: 309626-0 02[...]

  • Page 2

    2 Dual-Core In tel ® Xeon ® Processor 7000 Series Datasheet INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER WISE, T O ANY INTELLECTUAL PROPERTY RI GH TS IS GRANTED BY THIS DOCUMENT . EXCEPT AS PROVID ED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCT[...]

  • Page 3

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 3 Contents 1 Introduction... ................ ................ ................ ................. ................ ................ .............. ..... 11 1.1 Terminology..... ................ ................ ................. ................... ................ ................ 12 1.2 R[...]

  • Page 4

    4 Dual-Core Intel ® Xeon ® Processor 7000 Seri es Datasheet 6.2.2 On-Demand Mode . ................ ................. ................... ................ ............. 71 6.2.3 PROCHOT# Signal Pin .......................... ................ ................... ............. 71 6.2.4 FORCEPR# Signal Pin ............. ................ ............[...]

  • Page 5

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 5 Figures 2-1 On-Die Front Side Bus Te rmination .......... ................ ................ ................ .......... 15 2-2 Phase Lock Loop (PLL) F ilt er Requirements ............................ .................... ...... 17 2-3 Dual-Core In tel ® Xeon ® Processor 700 0 SeriesLoad[...]

  • Page 6

    6 Dual-Core Intel ® Xeon ® Processor 7000 Seri es Datasheet 2-16 GTL + Asynchronous and AGTL+ Asynchr onous Signal Group DC Specifications ......... ................ ................ ................... ................. ................ ... 31 2-17 SMBus Signal Group DC Specifications ... ................... .................... ................[...]

  • Page 7

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 7 Revision History § Document Number Revision Number Description Date 309626 -001 • Initial release of this document November 2005 309626 -002 • Changed product name to Dual-Core Intel® Xeon® Proce ssor 7000 Series • Updated Section 1.2 Reference Documents September 2006[...]

  • Page 8

    8 Dual-Core Intel ® Xeon ® Processor 7000 Seri es Datasheet[...]

  • Page 9

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 9 Features  A vailable at 2.66 or 3.0 GHz  90 nm process technology  Binary compatible with app lication running on previous members of Inte l's IA-32 microprocessor line  Intel NetBurst ® microarchitecture  Hyper-Threading T echnology  Hardware support for multithre[...]

  • Page 10

    10 Dual-Core Intel ® Xeon ® Processor 7000 Seri es Datasheet[...]

  • Page 11

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 11 1 Introduction The Dual-Core Intel ® Xeon ® processor 7000 series is Intel’ s first dual core product for multi-processor servers, utiliz ing two physical Intel N etBurst ® microarchitecture cores in one package. It maintains the tradition of compatibi lity with IA-32 software and i[...]

  • Page 12

    Introduction 12 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet which are accessed through an SMBus interface and co ntain information releva nt to the particular processor and system in which it is installed. Thermal managemen t and furth er thermal re dundancy can be achieved with the use of the Thermal Monitor feature. The Dual-Core I[...]

  • Page 13

    Introduction Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 13 transactions as well as interrupt messages pa ss between the processor and chipset over the FSB. • Functional O peration — Refers to th e normal operating conditions in which al l processor specifications, including DC, AC, system bus, si gnal quality , mechanical, and t[...]

  • Page 14

    Introduction 14 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 1.2 Reference Document s Material and concepts available in the following documen ts may be beneficial when reading this document: NOTES: 1. Contact your Intel representative for the latest revision of documents. 2. This collateral is available pu blicly at http://de veloper[...]

  • Page 15

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 15 2 Electrical Specifications 2.1 Front Side Bus and G TLREF Most Dual-Core Intel Xeon processor 7000 series FSB signals use Assisted Gunning T ransceiver Logic (AG TL+) signalin g technology . The termination voltage level for the Dual-Core Intel Xeon processor 7000 series AG TL+ signals [...]

  • Page 16

    Electrical Specifications 16 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet The BCLK[1:0] inputs directly control the opera ting speed for the FSB interface. The processor core frequency is configured during reset by using values stored internally durin g manufacturing. The stored value sets the highest bus fraction at wh ich the partic[...]

  • Page 17

    Electrical Specifications Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 17 2.1.3 Phase Lock Loop (PLL) Power and Filter V CCA , V CCIOPLL are power sources required by the P LL clock generators on the Dual-Co re Intel Xeon processor 7000 series. These are anal og PLLs and they requ ire low noise power supplies for minimum jit ter . The[...]

  • Page 18

    Electrical Specifications 18 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet processor . A minimum V CC voltage is provided in Ta b l e 2 - 7 and changes with frequency . This allows processors running at a higher frequency to have a relaxed mi nimum V CC voltage specification. The specifications ha ve been set such that one voltage regu[...]

  • Page 19

    Electrical Specifications Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 19 T able 2-3. V olt age Identification (VID) Definition VID5 VID4 VID3 VID2 VID1 VID0 VID (V) VID5 VID4 VID3 VID2 VID1 VID0 VID (V) 001010 0 . 8 3 7 5 0 1 1 0 1 0 1.2125 101001 0 . 8 5 0 0 1 1 1 0 0 1 1.2250 001001 0 . 8 6 2 5 0 1 1 0 0 1 1.2375 101000 0 . 8 7 5 0[...]

  • Page 20

    Electrical Specifications 20 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 2.3 Reserved, Unused, and TESTHI Pins All RESER VED pins must be left unconnected. Connection of these pins to V CC , V SS , or to any other signal (including each othe r) can result in comp onent malfunction or in compatibility with future processors. See Secti[...]

  • Page 21

    Electrical Specifications Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 21 2.5 Front Side Bus Signal Group s The FSB signals are grouped by buffer type as listed in Ta b l e 2 - 4 . The buffer type indicates which AC and DC specifications apply to the signals. AG TL+ input signals have differential input buffers that use G TLREF as a r[...]

  • Page 22

    Electrical Specifications 22 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet The ODTEN signals enables or disables R TT . Those signals affected by ODTEN still p resent R TT termination to the signal’ s pin when the processor is placed in tri-state mode. Furthermore, the following signals are not affected when the proces sor is placed [...]

  • Page 23

    Electrical Specifications Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 23 2.7 T est Access Port (T AP) Connection Due to the voltage levels supported by other compo nents in the T AP logic, Intel recommends that the Dual-Core Intel Xeon processor 7000 series be first in the T AP chain, followed by any other components within the syste[...]

  • Page 24

    Electrical Specifications 24 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 2.9 Processor DC S pecifications The following notes apply: • The processor DC specifications in this section are defined at the processor core silicon and not at the package pins unless noted otherwise. • The notes associated with each parameter are part of[...]

  • Page 25

    Electrical Specifications Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 25 I CC_TDC I CC for Dual-Core Intel Xeon processor 7000 series Thermal Design Current 2.8 - FMB GHz 130 A 7, 20, 13 NOTES: 1. Unless otherwise noted, all specificati ons in this table apply to all processors. These sp ecifications are based on silicon characteriza[...]

  • Page 26

    Electrical Specifications 26 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet NOTES: 1. Processor or voltage regulator thermal protection circ uitry should not trip for load currents greater than I CC_TDC . 2. Not 100% tested. S pecified by design characterization. Figure 2-3. Dual-Core Intel ® Xeon ® Processor 7000 SeriesLoad Current v[...]

  • Page 27

    Electrical Specifications Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 27 NOTES: 1. The V CC_MIN and V CC_MAX loadlines represent static and transient limits. 2. This table is intended to aid in reading discrete points on Figure 2-4 . 3. The loadlines specify volt age limits at the die measured at the VCCSENSE and VSSSENCE pins. V olt[...]

  • Page 28

    Electrical Specifications 28 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet NOTES: 1. The V CC_MIN and V CC_MAX loadlines represent static and transient limits. 2. The V CC_MIN and V CC_MAX loadlines are plots of the discrete point found in T able 2-9 . 3. Refer to T able 2-8 for processor VID information. 4. The loadlines specify volta[...]

  • Page 29

    Electrical Specifications Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 29 NOTES: 1. V OS is measured overshoot voltage. 2. T OS is measured time duration above VID. Figure 2- 5. V CC Overshoot Examp le W aveform Example Overs hoot Wa veform 0 5 10 15 20 25 Time [us] Voltage [V] VID - 0.000 VID + 0. 050 V OS T OS T OS : Overshoot time [...]

  • Page 30

    Electrical Specifications 30 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet NOTES: 1. V IL is defined as the voltage range at a receiving agent that will be interpre ted as a logical low value. 2. V IH is defined as the voltage range at a receiving agent that will be interpreted as a logica l high value. 3. The V TT represented in these[...]

  • Page 31

    Electrical Specifications Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 31 NOTES: 1. All outputs are open drain. 2. The V TT represented in these specificat ions refers to instantaneous V TT . 3. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load. 4. V HYS re[...]

  • Page 32

    Electrical Specifications 32 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet[...]

  • Page 33

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 33 3 Mechanical Specifications The Dual-Core Intel Xeon processo r 7000 series is packaged in a FC-mPGA4 package that interfaces with the motherboard via a mPGA604 sock et. The pac kage consists of a processor core mounted on a substrate pin-carrier . An IHS is attach ed to the package subs[...]

  • Page 34

    Mechanical Specifications 34 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet Figure 3-2. Processor Package Drawing (Shee t 1 of 2)[...]

  • Page 35

    Mechanical Specifications Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 35 Figure 3-3. Processor Packag e Drawing (Sheet 2 of 2)[...]

  • Page 36

    Mechanical Specifications 36 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 3.2 Processor Component Keepout Zones The processor may contain compone nts on the substrate that define component keepout zone requirements. A thermal and mechanical solu tion design must not intrude into the required keepout zones. Decoupling capacitors are ty[...]

  • Page 37

    Mechanical Specifications Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 37 3.4 Package Handling Guidelines Ta b l e 3 - 2 inclu des a list of guidelines on package handling in term s of recommended maximum loading on the processor IHS relative to a fixed substrate. These packag e handling loads may be experienced during heatsink remova[...]

  • Page 38

    Mechanical Specifications 38 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 3.8 Processor Markings Figure 3-4 shows the topside markings and Fig ure 3-5 shows the bottom-side markings on the processor . These diagrams are to aid in the identification o f th e Dual-Core Intel Xeon processor 7000 series. Please note that the figures in th[...]

  • Page 39

    Mechanical Specifications Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 39 3.9 Processor Pin-Out Coordinates Figure 3-6 shows the top view of the processo r pin co ordinates. The coordinates are referred to throughout the docume nt to identify p rocessor pins. Figure 3-6. Processor Pin-Out Coordinates, T op View Vcc/Vs s ADDRESS DATA V[...]

  • Page 40

    Mechanical Specifications 40 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet § Figure 3-7. Processor Pin-Out Co ordinates, Bottom V iew Vcc/Vss ADDRESS DATA Vcc/ Vss CLOCKS COMMON CLOCK COMMON CLOCK Asyn c / JTAG Processor Bott om V iew = Signal = Power = Ground = Reserved/No Connect A C E G J L N R U W AA AC AE B D F H K M P T V Y AB A[...]

  • Page 41

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 41 4 Pin Listing 4.1 Dual-Core Intel Xeon Processor 7000 Series Pin Assignment s Section 2.5 contains the front side bus signal groups for the Dual-Core Intel Xeon processor 7000 series (see Ta b l e 2 - 4 ). This section provides a sorted pin li st in Ta b l e 4 - 1 and Ta b l e 4 - 2 . Ta[...]

  • Page 42

    42 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet Pin Listing BPM3# F5 Common Clk Input/Output BPM4# E8 Common Clk Input/Output BPM5# E4 Common Clk Input/Output BPRI# D23 Common Clk Input BR0# D20 Common Clk Input/Output BR1# F12 Common Clk Input/Output BR2# E1 1 Common Clk Input/Output BR3# D10 Common Clk Input/Output BSEL0 AA3 Power/O[...]

  • Page 43

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 43 Pin Listing DBI1# AD22 Source Sync Input/Ou tput DBI2# AE12 Source Sync Inp ut/Output DBI3# AB9 Source Sync Input/Ou tput DBSY# F18 Common Clk Input/Output DEFER# C23 Common Clk Input Don’t Care A2 Don’t Care A26 Don’t Care A28 Don’t Care A30 Don’t Care A31 Don’t Care B4 Don?[...]

  • Page 44

    44 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet Pin Listing DSTBP3# Y1 1 Source Sync Input/Output FERR#/PBE# E27 Async G TL+ Output FORCEPR# A15 Async G TL+ Input G TLREF0 W23 Power/Other Input G TLREF1 W9 Power/Oth er Input G TLREF2 F23 Power/Other Input G TLREF3 F9 Power/Other Input HIT# E22 Common Clk Input/Output HITM# A23 Common [...]

  • Page 45

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 45 Pin Listing V CC D18 Power/Other V CC D24 Power/Other V CC D31 Power/Other V CC E6 Power/Other V CC E20 Power/Other V CC E26 Power/Other V CC E28 Power/Other V CC E30 Power/Other V CC F1 Power/Other V CC F4 Power/Other V CC F29 Power/Other V CC F31 Power/Other V CC G2 Power/Other V CC G4[...]

  • Page 46

    46 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet Pin Listing V CC T30 Power/Oth er V CC U23 Power/Other V CC U25 Power/Other V CC U27 Power/Other V CC U29 Power/Other V CC U31 Power/Other V CC V2 Power/Other V CC V4 Power/Other V CC V6 Power/Other V CC V8 Power/Other V CC V24 Power/Other V CC V26 Power/Other V CC V28 Power/Other V CC V[...]

  • Page 47

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 47 Pin Listing V SS E9 Power/Other V SS E15 Power/Other V SS E17 Power/Other V SS E23 Power/Other V SS E29 Power/Other V SS E31 Power/Other V SS F2 Power/Other V SS F7 Power/Other V SS F13 Power/Other V SS F19 Power/Other V SS F25 Power/Other V SS F28 Power/Other V SS F30 Power/Other V SS G[...]

  • Page 48

    48 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet Pin Listing V SS P7 Power/Other V SS P9 Power/Other V SS P23 Power/Other V SS P25 Power/Other V SS P27 Power/Other V SS P29 Power/Other V SS P31 Power/Other V SS R2 Power/Other V SS R4 Power/Other V SS R6 Power/Other V SS R8 Power/Other V SS R24 Power/Other V SS R26 Power/Other V SS R28 [...]

  • Page 49

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 49 Pin Listing V SS AD17 Power/Other V SS AD23 Power/Other Vss AE6 Power/Other V SS AE1 1 P ower/Other V SS AE21 Power/Other V SS AE27 Power/Other V SSA AA5 Power/Other Input V SSSENSE D26 Power/Other Output V TT A4 Power/Other V TT B12 Power/Other T able 4-1. Pin Listing by Pin Name (Cont?[...]

  • Page 50

    50 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet Pin Listing 4.1.2 Pin Listing by Pin Number T able 4-2. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Ty p e Direction A1 VID5 Power/Other Output A2 D on’t Care A3 SKTOCC# Power/Other Output A4 V TT Power/Other A5 V SS Power/Other A6 A32# Source Sync Input/Output A7 A33# Sou[...]

  • Page 51

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 51 Pin Listing C17 A8# Source Sync Input/Output C18 A6# Source Sync Input/Output C19 V SS Power/Other C20 REQ3# Common Clk Input/Output C21 REQ2# Common Clk Input/Output C22 V CC Power/Other C23 DEFER# Common C lk Input C24 TDI T AP Input C25 V SS Power/Other Input C26 IGNNE# Async G TL+ In[...]

  • Page 52

    52 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet Pin Listing F6 BPM0# C ommon Clk Input/Output F7 V SS Power/Other F8 BPM1# C ommon Clk Input/Output F9 G TLREF3 Power/Other Input F10 V TT Power/Other F1 1 BINIT# Common Clk Input/Output F12 BR1# Common Clk Input/Output F13 V SS Power/Other F14 ADSTB1# Source Sync Input/Output F15 A19# S[...]

  • Page 53

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 53 Pin Listing K3 Don’t Care K4 V SS Power/Other K5 Don’t Care K6 V SS Power/Other K7 Don’t Care K8 V SS Power/Other K9 Don’t Care K23 V CC Power/Other K24 V SS Power/Other K25 V CC Power/Other K26 V SS Power/Other K27 V CC Power/Other K28 V SS Power/Other K29 V CC Power/Other K30 V[...]

  • Page 54

    54 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet Pin Listing P26 V CC Power/Other P27 V SS Power/Other P28 V CC Power/Other P29 V SS Power/Other P30 V CC Power/Other P31 V SS Power/Other R1 Don’t Care R2 V SS Power/Other R3 Don’t Care R4 V SS Power/Other R5 Don’t Care R6 V SS Power/Other R7 Don’t Care R8 V SS Power/Other R9 Don[...]

  • Page 55

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 55 Pin Listing W5 BCLK1 FSB Clk Input W6 TESTHI0 Power/Other Input W7 TESTHI1 Power/Other Input W8 TESTHI2 Power/Other Input W9 G T LREF1 Power/Other Input W23 G TLREF0 Power/Other Input W24 V SS Power/Other W25 V CC Power/Other W26 V SS Power/Other W27 V CC Power/Other W28 V SS Power/Other[...]

  • Page 56

    56 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet Pin Listing AB7 PWRGOOD Async G TL+ Input AB8 V CC Power/Other AB9 DBI3# Source Sync Input/Output AB10 D55# Source Sync Input/Output AB1 1 V SS Power/Other AB12 D51# Source Sync Input/Output AB13 D52# Source Sync Input/Output AB14 V CC Power/Other AB15 D37# Source Sync Input/Output AB16 [...]

  • Page 57

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 57 Pin Listing § AD27 D4# Source Sync Input/Output AD28 SM_ALERT# SMBus Output AD29 SM_WP SMBus Input AD30 Don’t Care AD31 Don’t Care AE2 Don’t Care AE3 Don’t Care AE4 V TT Power/Other AE5 TESTHI6 Power/Other Input AE6 V SS Power/Other Input AE7 D58# Source Sync Input/Output AE8 Do[...]

  • Page 58

    58 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet Pin Listing[...]

  • Page 59

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 59 5 Signal Definitions 5.1 Signal Definitions T able 5-1. Signal Definit ions (Sheet 1 of 7) Name T ype Description A[39:3]# I/O A[39:3]# (Address) define a 2 40 -byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction . In [...]

  • Page 60

    Signal Definitions 60 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet BNR# I/O BNR # (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the curr ent bus owner cann ot issue any new transactions. Since multiple agents might need to request a bus stal l at t[...]

  • Page 61

    Signal Definitions Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 61 D[63:0]# I /O D[63:0]# (Data) are the data signals. These si gnals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer . D[63:0]# are quad[...]

  • Page 62

    Signal Definitions 62 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet HIT# HITM# I/O I/O HIT# (Snoop Hit) and HITM# (Hit Mo dified) convey transaction snoop operation results. Any FSB agent may assert both HIT# and HIT M# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM # tog ether [...]

  • Page 63

    Signal Definitions Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 63 ODTEN I ODTE N (On-die termination enable) should be connected to V TT through a resistor to enable on-die termination for end bus agents. For middle bus agents, pull this signal do wn via a resistor to ground to disable on-die termination. W henever ODTEN is high, on-[...]

  • Page 64

    Signal Definitions 64 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet SM_EP_A[2:0] I The SM_EP_A (EEPROM Select Address) pins are decoded on the SMBus in conjunction with the upper address bits in order to maintain unique addresses on the SMBus in a system w ith multiple processors. T o set an SM_EP_A line high, a pull-up resistor should[...]

  • Page 65

    Signal Definitions Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 65 § V CCA IV CCA provides isolated power for the analog portion of t he internal PLL ’s. Use a discrete RLC filter to provide clean power . Refer to the appropriate plat form design guide for complete implementation details. V CCIOPLL IV CCIOPLL provides isolated powe[...]

  • Page 66

    Signal Definitions 66 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet[...]

  • Page 67

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 67 6 Thermal Specifications 6.1 Package Thermal S pecifications The Dual-Core Intel Xeon proce ssor 7000 series requires a thermal solut ion to maintain temperatures within operati ng limits. Any attemp t to operate the processor outside these operating limits may result in permanent damage[...]

  • Page 68

    Thermal Specifications 68 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet The upper point of the thermal profile consists of the Thermal Design Power (TDP) defined in Ta b l e 6 - 1 and the associated T CASE value. The lower point of the thermal profile consists of x = P CONTROL_BASE and y = T CASE_MAX @ P CONTROL_BASE . Pcontrol is defi[...]

  • Page 69

    Thermal Specifications Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 69 NOTE: Refer to the Dual-Core Intel ® Xeon ® Processor 7000 Sequence Thermal/Mechanical Design Guidelines for system and environmental implementation details. Figure 6- 1. Dual-Core Intel ® Xeon ® Processor 700 0 Series Thermal Profile A 0.184 T able 6-2. Dual-C[...]

  • Page 70

    Thermal Specifications 70 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 6.1.2 Thermal Metrology The maximum and minimum case temperatures (T CASE ) specified in Ta b l e 6 - 1 are measured at the geometric top center of the processor IHS. Figure 6-2 illustrates the location where T CASE temperature measurements should be made. For deta[...]

  • Page 71

    Thermal Specifications Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 71 operating temperature. Once the temperatur e has dropped below the maximum operating temperature and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases. W ith a therm al solution designed to meet th e thermal profile, it is anticip [...]

  • Page 72

    Thermal Specifications 72 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 6.2.4 FORCEPR# Signal Pin The FORCEPR# (force power reduction) input can be used by the platform to force the Dual-Core Intel Xeon processor 7000 series processor to activate the TCC . If the Thermal Monitor is enabled, the TCC will be act ivated upon the assertio [...]

  • Page 73

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 73 7 Features 7.1 Power-On Configuration Options Several configuration options can be set by ha rdware. The Dual-Core Intel Xeon processor 700 0 series samples its hardware configuration at reset, on the active-to-inacti ve transition of RESET#. For specifications on these options, refer to[...]

  • Page 74

    Features 74 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 7.2.2 HAL T Power Down St ate HAL T is a low power state entered when the processor executes the HAL T instruction. The processor transitions to the Normal state u pon th e occurrence of SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt deliver ed over the FSB. RESET# [...]

  • Page 75

    Features Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 75 BINIT# is not serviced while the processor is in S top-Grant state. The event is latched and can be serviced by software upon exit from t he Stop-Grant state. RESET# causes the processor to immediately in itial ize itself, but the processor will stay in Stop-Grant state. A tran [...]

  • Page 76

    Features 76 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 7.3 Enhanced Intel SpeedS tep ® T echnology Enhanced Intel SpeedStep T echnology enables the processor to switch between multip le frequency and voltage poin ts, which may result in platfo rm power saving s. In order to support this technology , the system must support dynam ic[...]

  • Page 77

    Features Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 77 The processor SMBus implementation uses the clock and data signals of the System Management Bus (SMBus) Specification . It does not implement the SMBSUS# si gnal. Layout and routing guidelines are available in the appropri ate platform design guide document. For platforms which [...]

  • Page 78

    Features 78 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet T able 7-2. Proce ssor Information ROM Format (Sheet 1 of 3) Offset/Section # of Bit s Function Notes Header: 00h 8 Data Format Revision Two 4-bit hex digit s 01 - 02h 16 EEPROM Size Size in bytes (MSB firs t) 03h 8 Processor Data Address Byte pointer, 00h if not present 04h 8 P[...]

  • Page 79

    Features Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 79 Cache Data: 25 - 26h 16 Reserved Reserved for future use 27 - 28h 16 L2 Cache Size per core 16-bit hexadecimal number (in KB) 29 - 2Ah 16 L3 Cache Size 16-bi t hexadecimal number (in KB). 2B - 2Ch 16 Processor Cache VID 16-bit hexadecimal Vcache value requested by CVID output (i[...]

  • Page 80

    Features 80 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 7.4.2 Scratch EEPROM Also available in the memory component on th e processor SMBus is an EEPROM which may be used for other data at the system or proc essor vendor ’ s discretion. The dat a in this EEPROM, once programmed, can be write-protected by asserting the acti ve-high [...]

  • Page 81

    Features Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 81 7.4.4 SMBus Thermal Sensor The processor ’ s SMBus thermal sen sor provides a means of acquiring th ermal data from the processor . The thermal sensor is composed of control logic, SMBus in terface logic, precision analog-to-digita l converters, and precision curr ent sources.[...]

  • Page 82

    Features 82 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet NOTES: 1. This is an 8-bit field. The device wh ich sent the alert will respond to the ARA Packet with its address in the seven most significant bits. The l east significant bit is undefined and may return as a ‘1’ or ‘0’. See Section 7.4.8 for details on the Thermal Sen[...]

  • Page 83

    Features Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 83 NOTES: 1. Bit 3 of Configuration register 1 must be set to 0 (default value is 0) 2. Writing to RESER VED bits may cause unexpected re sults. RESER VED bits that must be correctly programmed are identified in the register definitions in the following section. Reading from RESERV[...]

  • Page 84

    Features 84 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet Note: Writing to a read-command regist er or reading from a write-comma nd register will produce inv alid results. The default command after reset is to a reserved value (00h). After reset, Receive Byte SMBus packets will return invalid data until anoth er command is sent to the[...]

  • Page 85

    Features Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 85 alarm condition persists). If the SM_ALER T# signal is enabled via the Thermal Sensor Configuration Register and a thermal diode threshol d is exceeded, an alert will be sent to the platform via the SM_ALER T# signal. 7.4.6.4 Configuration Register The Configuration Register con[...]

  • Page 86

    Features 86 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 7.4.6.5 Conversion Rate Register The contents of the Conversion Rate Registers determine the nomin al rate at which analog-to-digital conversions happen when the SM Bus thermal sensor is in auto-convert m ode. There are two Conversion Rate Registers: addres s 04h for reading the[...]

  • Page 87

    Features Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 87 7.4.7 SMBus Thermal Sensor Alert Interrupt The SMBus thermal sensor located on the proces sor includes the ability to interrupt the SMBus when a fault condition exists. The fault conditions consist of: 1. A processor thermal diode value measuremen t that exceeds a user-defined h[...]

  • Page 88

    Features 88 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 7.4.8 SMBus Device Addressing Of the addresses broadcast across the SMBus, th e memory component claims those of the form “1010XXXZb”. The “XXX” bits are defined by pull-up and pull-down resistors on the system baseboard. These address pins are pulled down weakly (10 k ?[...]

  • Page 89

    Features Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 89 NOTE: 1. This addressing scheme will support up to 8 processors on a single SMBus. 7.4.9 Managing Dat a in the PIROM The PIROM consists of the following section s: • Header • Processor Data • Processor Core Data • Cache Data • Package Data • Part Number Data • Ther[...]

  • Page 90

    Features 90 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet The Header also includes the data format revision at offset 0h and the EEPROM size (formatted in hex bytes) at offset 01-02h. The data format revi si on is used whenever fiel ds within the PIROM are redefined. Normally the revision would begin at a va lue of 1. If a field, or bi[...]

  • Page 91

    Features Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 91 7.4.9.3.2 Front Side Bus Frequency Offset 1A - 1Bh provides FSB frequency information. Systems may need to read this offset to decide if all installed proces sors support the same FSB speed. Because the Intel NetBurst ® microarchitecture bus is described as a 4x data bus, the f[...]

  • Page 92

    Features 92 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 7.4.9.4 Cache Data This section contains cache-related data. 7.4.9.4.1 L2 Cach e Size Offset 27 - 28h is the L2 cache size field. The fi eld reflects the size of the level two cache for each core in kilobytes. Example: The Dual-Core Intel Xeon processor 7000 series may have a 2 [...]

  • Page 93

    Features Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 93 7.4.9.6.1 Processor Part Number Offse t 38 - 3Eh contains seven ASCII characters re flectin g the Intel part number for the processor . This informatio n is typically marked on the outside of the processor . If the part number is less than 7 characters, a leading space is ins er[...]

  • Page 94

    Features 94 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet Example: The Dual-Core Intel Xeon processor 7000 series has two cores an d two threads per co re. Therefore, this register will have a value of 0Ah 7.4.9.7.4 Additional Processor Feature Flags Offset 7Ah provides additional feature in formatio n for the processor . This field is[...]

  • Page 95

    Features Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 95 Checksums are automatically calculated and programm ed by Intel. The first step in calculating the checksum is to add each byte from the field to the ne xt subsequent byte. This result is then negated to provide the checksum. Example: For a byte string of AA445Ch, the resultin g[...]

  • Page 96

    Features 96 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet[...]

  • Page 97

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 97 8 Boxed Processor Specifications 8.1 Introduction The Dual-Core Intel Xeon processor 7000 series will be offered as an Intel boxed processor . Intel boxed processors are intended for system integrators who buil d systems from components available through distribution channels. The boxed [...]

  • Page 98

    Boxed Processor Specifications 98 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet NOTE: 1. The heatsink in this image is for reference only . 2. This drawing shows the retenti on scheme for the boxed processor . 8.2 Mechanical S pecifications This section documents the mech anical specifications of the box ed processor passive heatsink. [...]

  • Page 99

    Boxed Processor Specifications Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 99 Figure 8-2. T op Side Board Keepout Zones (Part 1)[...]

  • Page 100

    Boxed Processor Specifications 100 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet Figure 8-3. T op Side Board Keepout Zones (Part 2)[...]

  • Page 101

    Boxed Processor Specifications Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 101 Figure 8-4. Bottom Side Board Keepout Zones[...]

  • Page 102

    Boxed Processor Specifications 102 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet Figure 8-5. Board Mounting-Hole Keepo ut Zones[...]

  • Page 103

    Boxed Processor Specifications Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 103 Figure 8-6. Thermal Solution V olumetric[...]

  • Page 104

    Boxed Processor Specifications 104 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 8.2.2 Boxed Processor Heat sink Weight The boxed processor heat sink wei ght is approx imately 530 grams. See Section 3 of this document for details on the processor weight. 8.2.3 Boxed Processor Retenti on Mechanism and Heat sink Support s Baseboards and [...]

  • Page 105

    Boxed Processor Specifications Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 105 solution limitatio ns by using a load path attached to the chassis pan. Th e hat spring on the under side of the baseboard provides the necessary comp ressive load for the thermal interface material. The baseboard is intended to be isolated such that the d[...]

  • Page 106

    Boxed Processor Specifications 106 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet[...]

  • Page 107

    Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet 107 9 Debug T ools Specifications Please refer to the ITP700 Debug Port Design Gui de, eXtended Debug Port : Debug Port D esign Guide for T win Castle Chipset Platforms , eXtended Debug Port: Debug Port Design Guid e for MP Platforms , and th e appropriate platform design guide for more d e[...]

  • Page 108

    Debug T ools Specifications 108 Dual-Core Intel ® Xeon ® Processor 7000 Series Datasheet[...]