LSI 53C875A manual

® S14047 LSI53C875A PCI to U ltra SCSI Controller TECHNICAL MANU AL Decem ber 200 0 Ve r s i o n 2 . 0[...]

ii This doc ument co ntains prop rietary information o f LSI Logic C orporation. The inf ormation c ontain ed herein is not to b e used b y or di sclose d to third par ties withou t the e xpre ss written pe rmission of an of ficer of L SI Logic Corporatio n. LSI Log ic produc ts are not in tended f or use in li fe-su pport appliances , dev ices , o[...]

Pref ace iii Preface This book is th e pri mar y reference and tec hnical manual for the LSI53C875 A PCI to Ultra SCSI Co ntrolle r . It contai ns a com plete functiona l descr ip tion for the produc t and also in clude s complet e physical and electr ical sp ecifi cations. A udie nce This manual provides reference inform ation o n the LSI53 C875A [...]

iv Preface • Chapte r 6, Electr ical Spe cifications cont ains t he elec tri cal character is tics and AC timing diagrams. • Appendix A, Register Summ ary i s a regi ster summa r y . • Appendix B , External Memory Interfa ce Diagra m Examples cont ains sev eral example i nterface dra wings for connect ing the LSI53C 875A to externa l ROMs. Re[...]

Pref ace v PCI Specia l Interest Group 2575 N.E. K ather ine Hillsbo ro , OR 97214 (800) 433-51 77; (503) 69 3-623 2 (Inter nationa l); F AX (5 03) 693-834 4 Con ventions Used in This Manual The word asser t m eans to d ri v e a sig nal tr ue or ac tive . The wo rd deasser t means to dr ive a signa l f alse or inac tive . Hexadecimal numbe rs are i[...]

vi Preface[...]

Contents vii Contents Chapter 1 General Description 1.1 New F e atures in the LSI53 C875A 1-3 1.2 Benefits of Ultra SCS I 1-3 1.3 T olerANT ® Te c h n o l o g y 1 - 4 1.4 LSI53C 875A Bene fits Summ ar y 1-4 1.4.1 SCSI P erforman ce 1-5 1.4.2 PCI P erforma nce 1-6 1.4.3 Inte gration 1-6 1.4. 4 Eas e of Use 1-6 1.4.5 Flexibility 1-7 1.4.6 Rel iabili[...]

viii Cont ents 2.2.11 P ar ity Optio ns 2-24 2.2.12 DMA FIFO 2-27 2.2.13 SCSI B us Int erf ace 2-32 2.2.14 Select/R esele ct Dur ing S election /Reselec tion 2-33 2.2.15 Synchron ous Operatio n 2-34 2.2.16 Interru pt Handl ing 2-37 2.2.17 Chained B lock Mov es 2-44 2.3 P arall el ROM Interface 2-48 2.4 Ser ial EEP ROM Interface 2-50 2.4.1 Default D[...]

Contents ix Chapter 4 Registers 4.1 PCI Conf igura tion Regis ters 4-1 4.2 SCSI R egister s 4-18 4.3 64-Bit SCRIP TS Selec tors 4-99 4.4 Phase Mi smatch Jump Regi ster s 4-10 3 Chapter 5 SCSI SCRIPTS Instruction Set 5.1 Low Lev el Reg ister In terface Mode 5-1 5.2 High Level SCSI SCRIPT S Mode 5-2 5.2.1 Sample Ope ration 5-3 5. 3 B l ock M ove I n [...]

xC o n t e n t s 6.3 A C Character istic s 6-9 6.4 PCI and Exter nal Mem or y Interface Timing Diagrams 6 -11 6.4.1 T arget Timing 6-13 6.4. 2 In itiato r Timing 6- 19 6.4.3 Exter na l Memor y Tim ing 6-35 6.5 SCSI Timi ng Diagrams 6-52 6.6 P ackage Diagrams 6-58 Appendix A Register Summary Appendix B External Me mory Interface Diagram Examples Ind[...]

Contents xi 6.9 P CI Config uratio n Regis ter Read 6- 13 6.10 PCI Con figuration Re gister Wri te 6-14 6.11 32-Bit Op erating Regi ster/SCR IPTS RAM Rea d 6-15 6.12 64-Bit A ddress Operatin g Regis ter/SCRIP TS R AM Read 6-16 6.13 32-Bit Op erating Regi ster/SCR IPTS RAM Wr ite 6-17 6.14 64-Bit A ddress Operatin g Re gister/S CRIPTS R AM Wr ite 6-[...]

xii Co ntent s B.3 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 M byte Interface with 150 ns Memor y B-3 B.4 512 Kbyte Interface with 15 0 ns Memo r y B-4 Ta b l e s 2.1 PCI Bu s Comm ands and Encoding T ypes f or the LSI53C875 A 2-4 2.2 PCI Cac he Mode A lignm ent 2-12 2.3 Bits Us ed f or Parity Contr ol and Generation 2-25 2.4 SCSI Parity Co ntrol 2-[...]

Contents xiii 5.2 S CSI Inf or mat ion T r ansf er Phase 5- 12 5.3 Read/W rite Ins truc tions 5-24 5.4 T ransfer Control In stru ctions 5-26 5.5 S CSI Phase Co mparisons 5-29 6.1 A bsolute M axim um Stress Rati ngs 6- 2 6.2 Operat ing Condit ions 6-2 6.3 Input Ca pacit ance 6-2 6.4 Bidire ctional Signals —MAD[7: 0], MAS/[1: 0], MCE/ , MOE/, MWE/ [...]

xiv Co ntent s 6.30 Exter n al Memor y Wr ite 6-38 6.31 Nor mal/F as t Memor y ( ≥ 128 K bytes) Sing le Byte Access Rea d Cycle 6-42 6.32 Nor mal/F as t Memor y ( ≥ 128 K bytes) Sing le Byte Access Wri te Cycle 6-43 6.33 Slow Memor y ( ≤ 128 Kbytes) Read Cy cle 6-48 6.34 Slow Memor y ( ≤ 128 K bytes) Wr ite Cyc le 6-49 6.35 ≤ = 64 Kby tes[...]

LSI53C8 75A PCI to Ultra SCSI Controll er 1-1 Chapter 1 General D escript ion Chapter 1 is divi ded in to the following sections : • Section 1.1, “ New F eat ures in the LSI 53C875A” • Section 1.2, “B enefits o f Ultra S CSI” • Section 1 .3, “T oler ANT ® T ec hnolo g y ” • Section 1.4, “L SI53C8 75A Benefits Su mmar y” The[...]

1-2 Gener al Description Figure 1.1 T ypical LSI53C875A System Application Figure 1 .2 T ypical LSI53C875A Board A pplicatio n PCI Bus Interf ace Controller LSI53C875A P C It oW i d eU l t r a SCSI Controller PCI Graphic Accelerator PCI F ast Ether net Memory Controller Memo r y Fixed Disk, Opt ical Disk Printer, T ape, and Ot her P er ipherals Cen[...]

Ne w F eatures in the LSI 53C875A 1-3 1.1 Ne w Features in the LSI53 C875A The LSI53C87 5A is a drop-in replaceme nt f or the LSI53C875 PCI to Ultra SCSI C ontrolle r , with these addi tional be nefits: • Suppor ts 32- bit PCI Int erf ace w ith 64-bit a ddressi ng. • Hand les SCSI p hase mis matches in SCRI PTS with out interrupt ing the CPU . [...]

1-4 Gener al Description synchron ous ne gotiation s f or Ultra SCSI rates and to enable the clock quadr upler . Chapte r 2, “F unctiona l De scri ption,” contain s more informati on on Ul tra SCSI design. 1.3 T olerANT ® T echn olo gy The LSI5 3C875A f e ature s T olerA NT techno logy , whi ch in cludes active negation o n the S CSI dr ivers [...]

LSI53C8 75A Benefits Sum m ary 1-5 • Ease of Use • Fle xibility • Relia bility • T estabili ty 1.4. 1 SCSI P erforma nce T o improve SCSI perfor mance, the LSI53C8 75A: • Has integrated SE transc eivers. • Bursts up to 512 bytes across th e PCI bus throug h its 944 byte FIFO. • P erforms wi de, Ultra SCSI s ynchronou s transfers as fa[...]

1-6 Gener al Description • Suppo r ts addi tional arithme tic ca pability with the Exp anded Reg ister Mo ve in struction. 1.4.2 PCI P erf ormance T o improve PCI performanc e, the LSI53C875 A: • Complies with PC I 2.2 spec ificati on. • Suppor ts 32-bi t 33 MHz PCI inter face with 64-bit addressin g. • Suppor ts dual addres s cycles which [...]

LSI53C8 75A Benefits Sum m ary 1-7 • Up to one me gabyte of add -in memo r y suppor t for BIOS and SCRIPT S storag e. • Redu ced SCSI de v elop ment e ff or t. • Compil er-co mpatible w ith existin g LSI53 C7XX a nd LSI5 3C8X X f a mily SC RIPTS. • Direct con necti on to PC I and SCSI S E. • Dev elop ment too ls and samp le SCSI S CRIPTS [...]

1-8 Gener al Description • SCSI clock quadr upler b its enable Ultra SCSI transfer r ates with a 20 or 40 MHz SCSI clock input. • Select able IRQ pin disable bit. • Ability t o route sy stem cl ock to SCSI clock. • Compatible with 3.3 V and 5 V PCI. 1.4.6 R eliability Enhan ced reli ability features of the LS I53C875A i nclude: • 2 kV ES [...]

LSI53C8 75A PCI to Ultra SCSI Controll er 2-1 Chapter 2 Functio nal Description Chapter 2 is divi ded in to the following sections : • Section 2.1, “P CI Func tional Descri ption ” • Section 2.2, “SCSI F unctiona l Descr ip tion” • Sect ion 2.3, “P aralle l ROM Int erf ace” • Section 2.4, “S eri al EEPROM In terface” • Sec[...]

2-2 Functi ona l Des cr ipti on Figure 2.1 LSI53C875A Bl ock Diagram 2.1 PCI Functional Descriptio n The LS I53C 875A i mplem ents a PCI-to -Wide Ult ra SCSI co ntrolle r . 2.1.1 PCI A ddressing There a re three physical PCI- define d addres s space s: • PCI Con figuration spa ce. • I/O space for operating registe rs. • Memor y s pace for ope[...]

PCI Functio nal Description 2-3 2.1.1.1 Configuration Space The host proces sor uses the PCI config uration spac e to initialize the LSI53C875 A through a defined s et of configuratio n space registe rs. The Config uration regis ters ar e acces sible only by system BIOS duri ng PCI configura tion c ycles. The configura tion spac e is a c ontigu ous[...]

2-4 Functi ona l Des cr ipti on 2.1.2.1 Interrupt Ack nowledge Command The LSI5 3C875A doe s not re spond t o this co mmand a s a slav e and it nev er generate s this command as a master. 2.1.2.2 Spec ial Cycle Command The LSI5 3C875A doe s not re spond t o this co mmand a s a slav e and it nev er generate s this command as a master. T able 2.1 PCI[...]

PCI Functio nal Description 2-5 2.1.2.3 I/O Read Command The I/O Read comm and reads data from an agen t mappe d in I/O address s pace. All 32 address bi ts are dec oded. 2.1.2.4 I/O Write Command The I/O Wr ite comm and wri tes data to an ag ent mappe d in I/O addr ess space. A ll 32 a ddress bits are decod ed. 2.1.2.5 Reserve d Command The LSI5 3[...]

2-6 Functi ona l Des cr ipti on 2.1.2.10 Memory Re ad Multip le Command This comm and is ide ntica l to the Me mor y Re ad comman d except that it additiona lly indic ates that the master may intend to f e tch more than one cach e line b efore disconne cting . The LSI5 3C875A suppo r ts PCI M emor y Read Mul tiple fun ction ality and is sues Me mor[...]

PCI Functio nal Description 2-7 line. This c omman d is int ended for use wi th bulk seque ntial data transfers where the me mor y sys tem and th e request ing master might gain s ome performa nce advantage by read ing to a cache li ne boun dar y rather than a single memo r y cycle. The Read Line functi on in the LSI53C 875A takes advantage of the [...]

2-8 Functi ona l Des cr ipti on 2.1.2.13 Me mory W rite and Inv al idate Command The Memo r y Wr ite and I nv al idate com mand i s identic al to the M emor y Write co m mand , exc ept that it add itionall y guaran tees a minim um transfer of one c omplete cac he line; that is to say , the master inte nds to writ e all bytes with in the a ddresse d[...]

PCI Functio nal Description 2-9 After each data transfer , the chip re-ev alu ates the burst size based on the amount of rema ining data to transfer and again selec ts the highest possible multiple of the cache line si ze , and n o larger tha n the DM A Mode (DMODE ) burst size. The mo st likely sce nari o of thi s scheme i s that the chip selects [...]

2-10 Functio nal Description software e nabled or d isabled to allow the us er full flexibility in usin g these comm ands. 2.1.3.1 Enabling Cache Mod e In order to enable the cache l ogic to i ssue PCI cache comm ands (Memor y Read Li ne, Memor y Read Mu ltiple, and Me mor y Wr it e and Inv alid ate) on any g iven PCI master ope ration the followin[...]

PCI Functio nal Description 2-11 • T o issue Memor y R ead Multi ple com mands, the Re ad Mul tiple enable bit in th e DMA M ode (DMODE) register must b e set. • T o issue Memo r y Wr ite and Invalidate comm ands, both the Wr ite and Inv alid ate enables in t he C hip T est Three (CTEST3) register and the PCI configuration c ommand regis ter mu[...]

2-12 Functio nal Description • Multiple Me mor y Wr ite and Inv a lidate s. • A single da ta res idual Me mor y W rit e to co mplete the t ransfer . Ta b l e 2 . 2 descri bes PCI c ache mode align ment. T able 2.2 PCI Cache Mode Alignment Host Memor y A0 0 h B0 4 h 08h C0 C h D1 0 h 14h 18h 1Ch E2 0 h 24h 28h 2Ch F3 0 h 34h 38h 3Ch G4 0 h 44h 4[...]

PCI Functio nal Description 2-13 2.1. 3.5 Exa mples: MR = Memo r y Rea d, MRL = Me mor y R ead Line, MRM = Memor y Read Multiple, MW = Mem or y Wr ite, MWI = Memor y W rite and Inv al idate. Read E xample 1 – B u r s t=4D w o r d s ,C a c h e L i n eS i z e= 4D w o r d s : Read E xample 2 – B u r s t=8D w o r d s ,C a c h e L i n eS i z e= 4D w[...]

2-14 Functio nal Description Read E xample 3 – Burst = 16 Dwords, Cache Line Size = 8 Dw or ds: Write E xample 1 – B u r s t=4D w o r d s ,C a c h e L i n eS i z e= 4D w o r d s : Ct oE : MRM (21 byte s) Dt oF : MRM ( 31 bytes ) MR (1 byte ) At oH : MRM (31 bytes ) MRM (32 bytes ) MRM (18 bytes ) At oG : MRM (31 bytes ) MRM (32 bytes ) MR (3 by[...]

PCI Functio nal Description 2-15 Write E xample 2 – B u r s t=8D w o r d s ,C a c h e L i n eS i z e= 4D w o r d s : Dt oF : MW (1 5 bytes ) MWI (16 byt es) MW (1 byte) At oH : MW (1 5 bytes ) MWI (16 byt es) MWI (16 byt es) MWI (16 byt es) MWI (16 byt es) MW (2 bytes) At oG : MW (1 5 bytes) MWI (16 byt es) MWI (16 byt es) MWI (16 byt es) MW (3 b[...]

2-16 Functio nal Description Write E xample 3 – Burst = 16 Dwords, Cache Line Size = 8 Dw or ds: 2.1.3.6 Memor y-to-Mem ory Moves Memor y- to-Memor y Moves also suppor t PCI c ache co mmands, as descr ibed a bov e, wit h one limi tation . Memor y Wr ite and Invalidate on Memor y- to-Memor y Move writes are only suppor ted if t he sou rce and dest[...]

SCSI Functio nal Description 2-17 access ed as a regi ster-or iented d evice. Error recov e r y and/o r diagnos tic procedu res use the ability to sam ple and/or asser t any signal on the SCSI bus. In supp or t o f SCSI lo opback diagn ostics, the SCS I core ma y perform a self-sel ection an d operate as both an initiator an d a tar get. The LS I53[...]

2-18 Functio nal Description The Pha se Mism atch Jump l ogic powers up disabled and mus t be enabled by setting the Pha se Mismat ch Jump Enable bit (ENP MJ , bit 7 in the Chip Control 0 (CCNTL0) register). Utilizing t he inform ation su pplie d in the P h a s eM i s m a t c hJ u m pA d d r e s s 1( P M J A D 1 ) and P hase Mismatc h Jump Addre ss[...]

SCSI Functio nal Description 2-19 2.2.3 64-Bi t Address ing i n SCRIPT S The LSI5 3C875A has a 32-bi t PCI in terface which provide s 64-bit address capabi lity in th e init iator mod e. D ACs can be generated for all SCRIPT S operation s. There are si x sele ctor regis ters whic h hold the upper Dword of a 64-bit addr ess. All but one of th ese is[...]

2-20 Functio nal Description 2.2.5 Des igning an Ultra SCSI Sy stem Since U ltra SCSI is ba sed on existing SCSI stan dards, it can use existing dri v er pro grams as long as the s oftware is able to negot iate for Ultra SCSI s ynchr onous transfer rates. Additio nal software m odifica tions ar e needed to ta ke advantage of the new features in th [...]

SCSI Functio nal Description 2-21 S t e p3 . H a l tt h eS C S Ic l o c k b ys e t t i n gt h eH a l tS C S IC l o c k b i t ( SCSI T est Three ( STEST3) ,b i t5 ) . Step 4. Set the clock con version factor using the SCF and CCF fields in the SCSI Contr ol Three (S CNTL3) register . Step 5. Set the SCLK Quad r upler Se lect bit ( SC SI T es t One ([...]

2-22 Functio nal Description • On ev er y Store instr ucti on. The S tore ins truc tion may also be used to place modifi ed code di rectly in to memo r y . T o av oid inad ver tently flushin g the prefetch unit conten ts use the No Flus h option for all Store operations th at do not modify code within the next 8 Dwords . • On ev er y write to t[...]

SCSI Functio nal Description 2-23 Load and S tore ins truc tions, refer to Chapter 5, “SCSI SCRIP TS Instr uction Set. ” 2.2.9 JT A G Boundary Scan T esting The LSI5 3C875A include s suppor t for JT A G bounda r y sc an testin g in accord ance wi th the IEEE 1149 .1 spec ificatio n with on e exception, whic h is ex plaine d in this section . Th[...]

2-24 Functio nal Description 2.2.11 P arity Options The LSI5 3C875A im pleme nts a flexible pari ty sche me that a llows control of the pari ty sense, allows parity che c king to be tur ned on or o ff , an d has the ability to del iberately send a b yte with bad p arit y ov er the SCSI bus to test par ity er ror re covery p roce dures. Ta b l e 2 .[...]

SCSI Functio nal Description 2-25 T able 2.3 Bit s Used for Parity Control and Gene ration Bit Name L ocation Desc ription Asser t SA TN/ on P ar ity Errors SCSI Control Zer o (SCNTL0) ,B i t1 C ause s th e LSI 53C 875A to au tom atica lly as ser t SA TN/ when it detects a SCSI parity error while ope rating as an initia tor . Enab le Pa r ity Check[...]

2-26 Functio nal Description T able 2.4 SCSI P arity Control EPC 1 1. EPC = E nable Pari ty C heckin g (bi t 3 SCSI Control Zero (SCNTL0) ). ASEP 2 2. ASEP = Assert SCSI Even P arity (bit 2 SCSI Co ntr ol O ne (S CNTL1 ) ). Descrip tion 0 0 Does n ot chec k f or parity errors . P arity is gener ated when sending SCSI data . Asserts odd parity when [...]

SCSI Functio nal Description 2-27 Figure 2.2 P arity Chec king/Generation 2.2. 12 DMA FI FO The DMA FIFO is 8 bytes wid e by 118 transfers deep. The DMA FIFO is illu strated in Fi gure 2.3 . Th e default DMA FIF O size is 11 2 bytes to assure compa tibil ity wit h olde r products in the LSI53 C8XX family . The DMA FIFO size ma y be set to 944 byt e[...]

2-28 Functio nal Description Figure 2.3 DMA F I FO Sec tions The LSI53C87 5A automa tical ly suppor ts misa ligned DMA transfers. A 944-byte FIFO all ows the LSI53C87 5A to sup por t 2 , 4, 8, 16, 32, 6 4, or 128 Dword bursts across the PC I bus interface. 2.2.12.1 Data Paths The data pa th through the L SI53C8 75A is depende nt on whethe r data is[...]

SCSI Functio nal Description 2-29 Figure 2.4 LSI53C87 5A Host Interface SCS I Data P ath s The following steps deter mi ne if any bytes remain i n the data p ath when the chip halts an operation : Asynchr onous SCSI Send – Step 1. If the DM A FIFO si ze is set to 112 bytes (bit 5 of the Chip T est Fiv e (CTEST5) regi ster c leared), lo ok at the [...]

2-30 Functio nal Description bits of the DBC r egister fr om the 10-bi t v alue of the D MA FIFO Byte Offset Cou nter , which con sists of bits [1 :0] in the CTEST5 registe r and bi ts [7:0] of th e DMA FI FO reg ister . A ND the r esult with 0x3F F for a byte count between zer o and 94 4. Ste p 2. Read b it 5 i n the SCSI S tatus Zero (S ST A T0) [...]

SCSI Functio nal Description 2-31 then the least s ignificant byte or the most si gnifican t byte i n the SODR re gister is full, res pectively . Asynchr onous SCSI Receive – Step 1. If the DM A FIFO si ze is set to 112 bytes (bit 5 of the Chip T est Fiv e (CTEST5) regi ster c leared), lo ok at the DM A FIFO (DFIFO) and DMA Byte Co unter ( DBC) r[...]

2-32 Functio nal Description AND the r esult with 0x 3FF f or a byte count be tween zero and 944. Ste p 2. Read t he SCSI Status One (SST A T1) regist er and examine bits [7:4], the bi nar y rep rese ntation of th e number of v alid bytes in the SCSI FIFO , to deter m ine if any b yte s are left in the SCSI FIFO . Step 3. If any wid e tr ansf ers h[...]

SCSI Functio nal Description 2-33 Figure 2 .5 Regulated T ermination for Ultra SCSI 2.2. 14 Select /Resele ct During Sel ection/Reselec tion In multithr eaded SCSI I/O environm ents, it is no t uncommo n to be sele cted or resele cted while tr y ing to perfor m selecti on/resel ectio n. This TERM L1 TERM L2 TERM L3 TERM L4 TERM L5 TERM L6 TERM L7 T[...]

2-34 Functio nal Description situatio n may occur whe n a SCS I controlle r (operati ng in the i nitia tor mode ) tries to se lect a target an d is res elected b y another . The Sele ct SCRIPTS instr uction ha s an alter nate ad dress to which t he SCR IPTS wi ll jump w hen this s ituation occur s. The anal ogous si tuatio n for target devices is b[...]

SCSI Functio nal Description 2-35 Figure 2.6 Determining the Synchr onous T ransfer Rate SCLK Clock Quadrupler QCLK SCF Div id er CCF Divider Synchronous Divider Asynchronous SCSI Logic Divide by 4 SCF2 SCF1 SCF0 SCF Divisor 00 1 1 01 0 1 . 5 01 1 2 10 0 3 00 0 3 10 1 4 11 0 6 11 1 8 TP2 TP1 TP0 X FERP Divisor 00 0 4 00 1 5 01 0 6 01 1 7 10 0 8 10 [...]

2-36 Functio nal Description 2.2.15.2 SCSI Control Three (SCNTL3) Register , Bit s [6:4] (S CF[2:0]) The SCF[2: 0] bits s elect the factor by which the frequenc y of SCLK is divided before being pre sented to t he sync hronous SCSI contr ol logi c. The outpu t from this div ider co ntrol s the rate a t which data c an be received; thi s rate must n[...]

SCSI Functio nal Description 2-37 • Ultra SCSI Enab le bit, SC SI Control Three ( SCNTL3) r egister bi t 7. Setting th is bit enables Ultra SCSI synchr onous transfers in systems that u se the internal SCSI cl ock qua drupler . • T olerANT Enable bit, SCSI T est Thre e (STEST 3) re gister bit 7. A ctive negation must be e nabled for the LSI53C8[...]

2-38 Functio nal Description polled wh en polled inter rupts are us ed. It is also the first regis ter that should b e read after the I RQ/ pi n is asser ted i n assoc iation with a hardware inter rupt. The INTF (In terr upt-on-the- Fly) bi t should b e the firs t interr upt ser viced. It mus t be wri tten to one t o be clear ed. This inte rru pt m[...]

SCSI Functio nal Description 2-39 conditi ons caus ed the DMA -type in terr upt, and c lears that DM A inte rru pt conditi on. Bit 7 i n DST A T , DF E, is pur ely a status bit; it will n ot gene rate an interr upt und er any circum stances a nd will not be cleared when r ead. DMA interr upt s flush neithe r the DM A nor SCSI FI FOs before generati[...]

2-40 Functio nal Description Pur po se Timer E xpired ( GEN), an d Handsha ke-to-Handsh ake Timer Expired ( HTH) interr up ts are nonfatal. When opera ting in the T arget mode, CMP , S EL, RS L, T arge t mode: SA TN/ act ive (M /A), GEN, and HT H are nonfatal. Refer t o the descri ption f or the Disa ble H alt on a P arity Err or or SA TN/ acti ve [...]

SCSI Functio nal Description 2-41 Interru pts can b e disabled by setting SYNC_IR QD bit 0 i n the Inte rrupt Status One (IST A T1 ) regist er . If an i nterr upt is a lready as ser ted and SYNC_IR QD is then set, the inter rupt wi ll remain as ser ted until ser v iced. At this p oint, th e IRQ/ pin is block e d for future inter rupt s until th is [...]

2-42 Functio nal Description generates a n interr upt, th e bit cor respond ing to the ear lier m asked nonfatal interr upt is st ill set. A related s ituation t o interr upt s tacking is when two i nterr upts oc cur simultaneo usly . Sinc e stacking does not oc cur unti l the SIP o r DIP bits are set, there is a sma ll tim ing win dow in whic h mu[...]

SCSI Functio nal Description 2-43 • If the ins truc tion is a JUMP/ CALL WH EN/IF <p hase>, th e DMA SCRIPT S P o inter (D SP) is upd ated to t he transfer address before halting. • All other ins truc tions may halt bef o re complet ion. 2.2.16.7 Sample I nterrupt Ser vice Rout ine The following is a s ample of an inte rru pt ser v ice ro[...]

2-44 Functio nal Description 2.2. 17 Chained B lock Mo ves Since th e LSI53C 875A h as the capabil ity to trans f e r 16-bit w ide SCS I data, a unique si tuatio n occur s when deal ing wi th odd bytes. The Chained Move (CHMO V ) SCRIPTS instr uction al ong with the Wide SCSI Send (W SS) and Wide SCSI Recei ve (WSR) bits in the SCSI Contr ol T wo ([...]

SCSI Functio nal Description 2-45 Figure 2.7 Block Move and Chained Block Mo ve Instruc tions 2.2.17.1 Wide S CSI Send Bi t The WSS b it is set whenev er th e SCSI controller is sen ding data (Data-Out f or initia tor or Data- In f or target) and the contr oller detec ts a par t ial transf er at the end of a chained Block Mov e SCRIPTS instr uct io[...]

2-46 Functio nal Description two bytes are sent ou t acros s the bus, regard less of t he type o f Block Mov e instr uct ion (nor m al or ch ained) . The fl ag is auto matic ally cl eared when the “ma rri ed” word is se nt. The f lag is alte r nately cl eared thr ough SCRIPTS or by the m icroproc essor . Also, the micr oproces sor or SCRIPTS ca[...]

SCSI Functio nal Description 2-47 2.2.17.5 Chained Block Mov e SCRIPTS Instruction A chai ned Block Move SCRIPTS instr uction is pr imar ily u sed t o transfer consec utive data send or data receive b locks. Using the chained Bl ock Mov e instr uc tion facilitat es par tial rec eive transfers and all ows correct par t ial send beh avior without add[...]

2-48 Functio nal Description send com mand, th e first byte of th e data s end co mmand is ass umed t o be the high-o rder byte and is “marr ied” with th e low-order byte stored in the lower byte of the SC SI Output D ata La tch (SODL ) regi ster bef ore the two bytes are sent a cross th e SCSI bus. For “N” consec utive wide data send Block[...]

P arallel R OM Interfa ce 2-49 The LSI5 3C875A su ppor ts a variety of sizes and sp eeds of expansion ROM, using pul l-down resis tors on the MAD [3:0] pi ns. The enco ding o f pins MAD[3:1 ] allows the user to define how much externa l memor y is av aila ble to the LSI53C8 75A. Ta b l e 2 . 6 shows the memor y s pace associate d with the possible [...]

2-50 Functio nal Description 2.4 Serial EEPR OM Interface The LS I53C875 A imp lements a n inter fa ce that allo ws attac hment of a ser ial E EPROM device to th e GPIO 0 and GPI O1 pi ns. There a re two modes of o peratio n rela ting to the se rial EEP ROM and the S ubsyst em ID and Subsys tem V endor ID registers. These modes are pr ogrammable th[...]

P ow er Man agement 2-51 2.4.2 No Do wnload Mode When MAD 7 is pu lled up th rough an extern al resisto r , the a utomati c download is d isabled and no data is au tomati cally load ed into chip registe rs at power-up. The Subsystem ID and S ubsystem V endor ID registe rs are read onl y , pe r the PCI spe cific ation, w ith a default v a lue of 0x1[...]

2-52 Functio nal Description The LS I53C875 A po wer stat es show n in Ta b l e 2 . 8 are indepen dently control led through two power state bits that are loc ated in the PCI Po w e r Mana gement C ontr ol /Stat us (PMCS R) r egister 0x44 . Although the PCI Bus P ower Manag ement Inter f a ce Spec ificatio n does not allow power state transitio ns [...]

P ow er Man agement 2-53 2.5. 3 P ow er State D2 P ower state D2 is a lower power state than D1 . In this state the LSI53C 875A core i s pla ced in t he coma m ode. The following PCI Config uration Space co mmand regis ter enable bits are suppres sed: • I/O Space E nable • Memor y S pace Ena ble • Bus M asteri ng Ena ble • SERR/Enable • E[...]

2-54 Functio nal Description[...]

LSI53C8 75A PCI to Ultra SCSI Controll er 3-1 Chapter 3 Signal Des criptions This chap ter pres ents the LSI53C8 75A pi n configu ration and s ignal definit ions usin g tables and illustra tions. This chapt er contai ns the f o llowin g sectio ns: • Section 3.1, “L SI53C875A Functi onal S ignal Gro uping” • Sec tion 3. 2, “Signa l Descrip[...]

3-2 Signa l Descripti ons 3.1 LSI53C875A Functional Signal Grouping Figure 3.1 present s the L SI53C87 5A si gnals by func tional group . Figure 3.1 LSI53C875A Functional Signal Gr ouping LSI53C875A CLK RST/ AD[31:0] C_BE[3:0]/ PA R FRAM E/ TRD Y/ IRD Y/ ST OP/ DEVS EL/ IDSE L REQ/ GNT/ PERR/ SERR/ IRQ/ GPIO0_F ETCH/ GPIO1 _MASTER/ GPIO2 GPIO3 GPIO[...]

Signal D escriptions 3-3 3.2 Signal Descriptions The Sig nal Descr ipti ons are d ivided i nto P CI Bus Inte rface Signals , SCS I Bus Inte rface Signals , GPIO S ignal s, ROM Flash an d Memor y Inter f a ce Signals , T est In terface Signals ,a n d Po wer a nd Groun d Sig nals . The PCI B us Inter f a ce Si gnals ar e subdiv ided into Sys tem Sign[...]

3-4 Signa l Descripti ons 3.3 PCI Bus Interface Signals The PCI Bus Int erface Signals s ection co ntains ta bles descr ibing the signals for the f o llowing sig nal groups : System Si gnals , Addres s and Data Signals , Interface Contr ol Signal s , Arbitrati on Signals , Error Repor ting Sig nals , and Interr upt S ignal . 3.3. 1 System Sig nals [...]

PCI Bus Interf ace Signals 3-5 3.3.2 Address and Data Signals Ta b l e 3 . 3 descri bes Addres s and Data sign als. T able 3.3 Address and Data Signals Name PQFP BGA T ype Strength Desc ription AD[31:0] 150, 151, 153, 154, 156, 157, 1 5 9 ,1 6 0 ,3 , 5, 6, 7, 9, 11–13, 28– 30, 32, 34– 36, 38, 40, 41, 43, 44, 46, 47, 49, 50 B5, C5, A4, B4, A3,[...]

3-6 Signa l Descripti ons 3.3.3 Interface Control Signals Ta b l e 3 . 4 descri bes th e Inter f a ce Cont rol sig nals. T able 3.4 Interface Contr ol Signals Name PQFP BGA T ype Streng th Description FRAME/ 16 F2 S/T/S 8 m A PCI Cy cle Frame is driv en by the c urrent maste r to indicate the be gin ning and d urat ion of an a cces s. FRAME / is as[...]

PCI Bus Interf ace Signals 3-7 3.3.4 Arbitration Signals Ta b l e 3 . 5 desc ribes Arbit ration si gnals . 3.3.5 E rror Reporting Signals Ta b l e 3 . 6 descri bes the E rror Re por t ing signa ls. T able 3.5 Arbitr ation Signals Name PQFP BGA T ype Strength Description REQ/ 148 E6 O 8 mA PCI Request i ndicates to th e system arbiter t hat this age[...]

3-8 Signa l Descripti ons 3.3.6 Interrupt Signal Ta b l e 3 . 7 descri bes th e Interr upt signal. 3.4 SCSI Bus Interface Si gn als The SCSI Bu s Interface signal s section c ontains tables descr ibing th e signals for the following signal grou ps: SC SI Bus In terface Sign als , SCSI Signals ,a n d SCSI Contro l Sig nals . 3.4.1 SCSI Bus Interface[...]

SCSI Bus Interf ace Signals 3-9 3.4.2 S CSI Signals Ta b l e 3 . 9 descri bes the S CSI signa ls. 3.4.3 SCSI Contr ol Signals Ta b l e 3 . 1 0 des cr ibes the SCSI C ontrol si gnals. T ab le 3.9 SCSI Signal s Name PQFP BGA T ype Strength Descripti on SD[15:0] 113, 115–17, 85 –87, 89, 102, 103, 10 5–108, 110, 111 D13, E10, C13, D11, J9, L13, K[...]

3-10 Signal D escriptions 3.5 GPIO Signals Ta b l e 3 . 1 1 des cr ibes th e SCSI GPIO sig nals. T able 3.11 GPIO Signals Name PQFP BGA T ype Strength Description GPIO0_FETCH/ 53 N5 I/O 8 mA SCSI General Purpose I/O pin. Opt ionally , when d riven LOW , in dica tes tha t the next bus requ est wi ll b e for an opc ode fetc h. Thi s pin is progr amma[...]

ROM Flas h an d Mem or y Inte rface S igna ls 3-11 3.6 ROM Flash and Memor y Interface Signals Ta b l e 3 . 1 2 des cr ibes t he ROM Flash and Me mor y In terface signals. T ab le 3.12 R OM F l as h and Mem ory Int erface Sig nal s Name PQFP BGA T ype Strength Description MWE/ 139 C 7 O 4 mA Memo ry Wr ite E nable . T h i sp i ni su s e da saw r i [...]

3-12 Signal D escriptions 3.7 T e st Int erfac e Sig nals Ta b l e 3 . 1 3 des cr ibes T e st Inte rface signals. MAD[7:0 ] 59–62, 64–67 L7 , M7, N7, K7, M8, N8, L8, K8 I/O 4 mA Memory Address/Data Bus. This b us is us ed in conjun ction with the m emory address str obe pins and e xternal address latche s to assemb le up to a 20-bit ad dress f [...]

P ow er and Ground Signals 3-13 3.8 P ower and Ground Signals Ta b l e 3 . 1 4 des cr ibes the Po wer and Gr ound sig nals. T able 3.14 P ower and Ground S ignals Name PQFP BGA T ype Strength Description VSS_I/O 4, 10, 14, 18, 23, 27, 31, 37, 42, 48, 69, 79, 88, 93, 99 , 104, 109 , 114, 123, 133 , 152, 158 A 9 ,B 1 1 ,D 1 2 , E13, F 12, G11, J13, K[...]

3-14 Signal D escriptions 3.9 MAD Bus P r ogramming The MAD[7 :0] pins, in ad dition to s er vin g as the addr ess/d ata bus f o r the loca l memor y interface, also are used t o program power-up opti ons for the chip. A par ti cular opti on is programmed allowing the int er nal pull-down cur rent sin k to pull the pin LOW at reset or by connecti n[...]

MAD Bus Progr amming 3-15 • The MAD[ 0] pin i s the slow ROM pin. When pulled u p , i t enables two ex tra cycles o f data ac cess ti me to all ow use of slower mem or y devices . • All MAD pins h av e i nter nal pull-down r esistor s.[...]

3-16 Signal D escriptions[...]

LSI53C8 75A PCI to Ultra SCSI Controll er 4-1 Chapter 4 Regist ers This chap ter descr ibes all LS I53C875 A regis ters and is divi ded into the f o llowin g sectio ns: • Section 4.1 “P CI Configuration Reg isters ” • Section 4.2 “SCS I Registers ” • Sectio n 4.3 “64-Bi t SCRIPTS S electo rs” • Section 4.4 “P hase Misma tch Ju[...]

4-2 Re giste rs bits that are curr ently s uppor ted by the LSI5 3C875A are descr ibe d in th is chapt er . Reser ved bits sho uld not be accessed . Regist er s: 0x00–0 x01 V endor ID Read Only VID V endor ID [15:0] This 16 -bi t reg ist er ident ifies the man uf acturer of the device. The V endor ID is 0x1 000. T able 4.1 PCI Configuration Regis[...]

PCI Con fi gura tio n Reg ist ers 4-3 Regist er s: 0x02–0 x03 Device ID Read Only DID Device ID [ 15:0] This 16- bit reg ister ident ifies the particular de vice . The LSI53C875 A Device ID is 0x00 13. Regist er s: 0x04–0 x05 Command Read/Write The Command regist er provide s coar se control over a device’ s abil ity to generate and respond t[...]

4-4 Re giste rs R Reser ved 5 WIE Write and I n valida te Enable 4 This bit a llows the LSI5 3C875A to generate w rite and inv alidat e command s on th e PCI bus. The WIE bi t in the DMA Control (DC NTL) regi ster must a lso be se t for the device to generate Wr ite a nd Inv alidate c omman ds. R Reser ved 3 EBM Enable Bus Mastering 2 This bi t con[...]

PCI Con fi gura tio n Reg ist ers 4-5 Regist er s: 0x06–0 x07 Status Read/Write Reads to this r egister b ehave nor mally . Wr ites are sli ghtly different in that bits can be clear ed, but not set. A bit is cleared wh enev er the reg ister is writ ten, and the data in the corr espondi ng bit loc ation is a on e. F o r instan ce, to clear bi t 15[...]

4-6 Re giste rs These b its are read onl y and sho uld indi cate th e slowest time that a device asser ts DEVS EL/ for any b us command except Configu ration Read a nd Confi guration Wri te. The LSI53 C875A sup por ts a value of 0b01. DPR Data P arity Error Reported 8 This bit is s et when all o f the following conditions are met: • The bus agent[...]

PCI Con fi gura tio n Reg ist ers 4-7 Regist er s: 0x09–0 x0B Class Code Read Only CC Class Code [23:0] This 24-bi t registe r is used to identi fy the gener ic func tion of the d e vi ce. The upper byte of this reg ister is a base class cod e, the middle byte is a subcl ass code, and th e lower byte identifies a sp ecific regi ster lev el pr ogr[...]

4-8 Re giste rs Register: 0 x0D Latenc y Timer Read/Write L T Latency Tim er [7:0 ] The Late ncy Timer reg ister s pecifie s, in unit s of PCI bus clocks, the value of the La tency T imer for this PCI bus master . T he LSI53 C875A s uppor ts this timer . A ll eight bits are wr itable, allowing l atency values of 0 –255 PCI clocks. Use the f o llo[...]

PCI Con fi gura tio n Reg ist ers 4-9 Regist er s: 0x10–0 x13 Base Address Register Zero (I/O) Read/Write B A R0 Base Address Register Zero - I/O [31:0] This ba se addres s registe r is use d to map the operating reg ist er set i nto I/O spac e. The LSI 53C875A r equi res 256 bytes of I/O space f or this base address regis ter . It has bit zero h[...]

4-10 Re gist ers Regist er s: 0x18–0 x1B Base Address Register T wo (SCRIPTS RAM) Read/Write B A R2 Base Address Register T wo [31:0] This b ase regist er is used to ma p the SC RIPTS RAM int o memor y s pace. The de f ault v alue of this r egister is 0x000000 00. The LSI53 C875A points to 4096 bytes of address s pace with t his register. This re[...]

PCI Con fi gura tio n Reg ist ers 4- 11 control ler instal led on them (and there f ore the same V endor ID and Device ID). If the exter nal s eria l EEPROM in terf ace is enabled (MAD[7] LOW), this reg ister i s autom atica lly loa ded at power-up from the e x ter nal serial EEPROM and wi ll conta in the value download ed fro m the ser ia l EEPROM[...]

4-12 Re gist ers v alue that shou ld be s tored in the exter nal ser ial EEPROM i s vendor spe cifi c. Pl ease see the Sect ion 2.4 “Ser ial EE PROM Inter face” in Chapter 2 f or ad ditio nal informati on on downlo ading a value for this registe r . Regist er s: 0x30–0 x33 Expansion ROM Base Address Read/Write ERBA Expansion ROM Bas e Address[...]

PCI Con fi gura tio n Reg ist ers 4- 13 Register: 0 x34 Capabilities P ointer Read Only CP Capabilities Point e r [7:0] This reg ister i ndicates that the first extend ed capabi lity registe r is located at off set 0x40 in the PCI Confi guration . Regist er s: 0x35–0 x3B Rese rved Register: 0 x3C Interrupt Line Read/Write IL Interrupt Line [7:0] [...]

4-14 Re gist ers Register: 0 x3D Interrupt Pin Read Only IP Interrupt Pin [7:0] This regis ter indica tes which inter rupt pin t he de vice uses. Its v a lue is set to 0x01 f o r the INT A / signal. Register: 0 x3E Min_Gnt Read Only MG MIN_GNT [ 7:0] This re gister is used to sp ecify th e desired se ttings f or latency timer values. Mi n_Gn t is u[...]

PCI Con fi gura tio n Reg ist ers 4- 15 Register: 0 x40 Capability ID Read Only CID Cap_ID [7:0] This regi ster indi cates the typ e of data str uctur e currentl y being used. It is set to 0x01, in dicating the P ower Managemen t Data S truc ture. Register: 0 x41 Next Item P o inter Read Only NIP Nex t_I tem_Ptr [7:0] Bits [7:0] c ontain the offs e[...]

4-16 Re gist ers D2S D2_Support 10 The LSI5 3C875A s ets thi s bit to in dicate supp or t for power managemen t state D2. D1S D1_Support 9 The LSI5 3C875A s ets thi s bit to in dicate supp or t for power managemen t state D1. R Reser ved [8:6] DSI Device Specific Init ialization 5 This bit i s cleared to indic ate that t he LSI53C87 5A requires n o[...]

PCI Con fi gura tio n Reg ist ers 4- 17 DSCL Data_ Scale [14:13] The LSI5 3C875A doe s not sup por t the data registe r . Therefore, these two bits ar e always cleared. DSL T Data_Sel ect [12:9] The LSI5 3C875A doe s not sup por t the data registe r . Therefore, these four bits are always cleared. PEN PM E_E nabl e 8 The LSI5 3C875A al wa ys retur [...]

4-18 Re gist ers Register: 0 x47 Data Read Only D A T A Data [7:0] This regis ter provides an opti onal mec hanism for the function to repor t state -depende nt operating data. The LSI53C875 A does not use this r egister and always returns 0x00. 4.2 SCSI Register s The control re gisters for the SCSI core are directly acces sible from the PCI bus u[...]

SCSI Registers 4-19 T able 4.2 SCSI Register A ddress Map 31 16 15 0 SCNTL3 SCNTL2 SCNTL1 SCNTL0 0x00 GPREG0 SDID SXFER SCID 0x 04 SBCL SSI D SOC L SFBR 0x 08 SST A T 2 SST A T1 SS T A T0 DST A T 0x0C DSA 0x10 MBO X1 MBO X0 IST A T1 IST A T0 0x14 CTEST3 CTEST2 C TEST1 C TEST0 0x18 TEMP 0x1C CTEST6 CTES T5 CTEST 4 DFIFO 0 x20 DCMD DBC 0x24 DNAD 0x28[...]

4-20 Re gist ers Register: 0 x00 SCSI Contr ol Zero (SCNTL0) Read/Write ARB[1:0] Arbitration Mode Bits 1 and 0 [7:6] Simpl e Ar bitr ation 1. The LS I53C875A waits for a bus free con dition to occur . 2. It as ser ts SBSY/ an d its SCSI ID (contain ed in the SCSI Chi p ID (SCID) register ) onto the SCSI bus. If the S SEL/ si gnal is a sser ted by a[...]

SCSI Registers 4-21 Full Arbi tration, S election/R eselectio n 1. The LS I53C875A waits for a bus free con dition. 2. It as ser ts SBSY/ and i ts SCSI ID (the hig hest pr ior ity ID stored i n the SCSI Chip ID (SCID) r egister ) onto the SCSI b us . 3. If the S SEL/ signa l is asser ted by another SC SI device or if th e LSI53 C875A dete cts a hig[...]

4-22 Re gist ers W A TN Select with SA TN/ on a Start Sequence 4 When this bi t is set and the LSI53C 875A is i n the initiato r mode, the SA TN/ sign al is asse r ted d urin g selecti on of a SCS I targ et de vic e. This is t o inf orm th e ta rget t hat th e LSI5 3C875A has a messa ge to se nd. If a selecti on time-ou t occurs while a ttempti ng [...]

SCSI Registers 4-23 ( SET TAR GET or CLEAR TA RGET ). When this bit is set, the chip is a tar get device by def aul t. When this bi t is cleared , the LS I53C8 75A is a n initiato r device by default. Caution : Wri ting this b it while not connecte d may cause the lo ss of a selec tion or rese lecti on due to the changi ng of targ et or initiato r [...]

4-24 Re gist ers may trans f e r up to three ad ditional bytes before haltin g to synchron ize bet ween inter n al core cells. Du ring synchron ous operatio n, the LSI53C 875A transfers data until there are no out standi ng synchron ous offsets. If the LSI53C875 A is rec eiving dat a, any data r esidin g in the DMA FIFO is sent to m emor y before h[...]

SCSI Registers 4-25 SCSI Co ntrol Zero ( SCNTL0) r egister are set f or f ull arbitration a nd selec tion b ef o re setti ng this bi t. Arb itrat ion is retried un til won . At that p oint, th e LSI53C 875A holds SB SY and S SEL ass er te d, and waits f o r a select or rese lect seq uence. The Immedia te Arbitration bi t is cleared auto maticall y [...]

4-26 Re gist ers Caution : Wri ting to thi s regis ter wh ile not co nnecte d may cause th e loss of a sele ction/r eselecti on by clear ing the Connec ted bit. Register: 0 x02 SCSI Contr ol T wo (SCNTL2) Read/Write SDU S CSI Disconnect Unexpected 7 This bit is valid i n the initia tor mode on ly . W hen this bi t is set, the SCS I core is not e xp[...]

SCSI Registers 4-27 combine d with t he firs t byte from the su bsequent tr ansfer so that a wide transfer is complet ed. SLPMD SLP A R Mode 5 If this bit is clear ed, the SCSI Longitudi nal Parity (SLP AR ) registe r functions as a byte-wide long itudinal par ity registe r . If this bit is set, t he SLP AR func tions as a word-wide longitudi nal p[...]

4-28 Re gist ers group codes. If this bit is set , the de v ice does not rel oad the Block Move b y te count, r egardl ess of th e group code. WSR Wide SC SI Receive 0 When re ad, this bit retu rn s the value of th e Wide SCS I Receive (WSR) flag. Set ting this bi t clears the WS R flag. This cle arin g functio n is s elf-clear ing. The WSR fl ag i[...]

SCSI Registers 4-29 SCF[2:0] Synchr onous Cloc k Con version F actor [6:4] These b its sel ect a factor by which t he frequen cy of SCLK is divided before being p resented to the synchron ous S CSI co ntrol log ic. Wr ite the se to th e same v alue as the Clock Conv ersio n F actor bi ts below unless f a st SCS I operation is desire d. See the SCSI[...]

4-30 Re gist ers Register: 0 x04 SCSI Chip ID (SCID) Read/Write R Reser ved 7 RRE Enable Response to Reselection 6 When t his bi t is set , the LSI53C 875A is enabled to respond to bus-initiated resele ction at the chi p ID in th e Respo nse ID Zero (R ESPID 0) and Respon se ID One (RES PID1) r egisters. No te that th e chip do es not automa ticall[...]

SCSI Registers 4-31 Register: 0 x05 SCSI T ransfer (SX FER) Read/Write Note: When using T able Indir ect I/O co mmands, bi ts [7:0] o f this registe r are loade d from the I/O da ta str ucture. TP[2:0] SCSI Synchr onous T ransfer P eriod [7:5] These b its deter mi ne the S CSI syn chronous transfer peri od used by the LSI53C 875A when send ing sync[...]

4-32 Re gist ers (This SCSI sy nchrono us core clock is deter m ined in SCNTL3 b its [6:4], Ext CC = 1 i f SCNTL1 bit 7 is as ser ted and the LS I53C875A is sen ding da ta. ExtCC = 0 if th e LSI53C875 A is rec eiving data.) SXFER P = 10 0 ÷ 25 = 4 Where: Ta b l e 4 . 3 shows e xa mples of sync hronous transfer periods an d rates f or SCSI- 1. SXFE[...]

SCSI Registers 4-33 Ta b l e 4 . 4 shows example transfer peri ods and rates for f as t SCS I-2 and Ultra SCSI. MO[4:0] Max SCSI Synchr onous Offset [4:0] These bi ts descri be the maxim um SCSI synchro nous offset us ed by the LSI53C 875A when transferri ng synchron ous SCSI data in eit her the initi ator or target mode. Ta b l e 4 . 5 d escri bes[...]

4-34 Re gist ers T able 4.5 Maxim um Synchr onous Offset MO4 MO3 MO2 MO1 MO0 Synchrono us Offset 00000 0 - A s y n c h r o n o u s 00001 1 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01000 8 01001 9 01010 1 0 01011 1 1 01100 1 2 01101 1 3 01110 1 4 01111 1 5 10000 1 6 10001 1 7 10010 1 8 10011 1 9 10100 2 0 10101 2 1 10110 2 2 10111 2 3 11000 2[...]

SCSI Registers 4-35 Register: 0 x06 SCSI Destinat ion ID (SDID) Read/Write R Reser ved [7:4] ENC Enc oded Destin ation SCS I ID [3:0] Wri ting th ese bits se t the SCS I ID of the in tended ini tiator or targe t dur ing SC SI resel ection o r selec tion ph ases, respectively . When ex ecuti ng SCRI PTS, the SCRIPTS processo r wri tes the desti nati[...]

4-36 Re gist ers is als o possible to program t hese si gnals as live inpu ts and sense them th rough a SCRIPT S register to regi ster Mo ve Ins tructio n. GPIO4 ma y be used t o enab le or disable V PP , the 12 V ol t power supply to th e external flash memor y . This bit powers up with the pow e r to e x ter nal memor y di sabled. GPIO[3 :0] defa[...]

SCSI Registers 4-37 ab y t es t o r e di ns y s t e mm e m o r y ,t h eb y t em u s tf i r s tb e mov ed to an inter mediate LS I53C87 5A register (such as a SCRA TCH r egister ), and then to the S FBR. This regi ster also co ntains t he state of the lower eigh t bits of the SCS I data bus dur ing t he Selec tion ph ase if the COM bit in the DM A C[...]

4-38 Re gist ers Register: 0 x0A SCSI Sel ector ID (SSI D) Read Only V AL SC SI V alid 7 If V AL is a sser te d, then the two SCSI IDs are detec ted on the bus durin g a bus-initiated sele ction or reselecti on, and the encoded des tination SCS I ID bits below are valid. If V AL is d easser ted, on ly one ID i s present a nd the conte nts of the en[...]

SCSI Registers 4-39 REQ SREQ/ Status 7 AC K S AC K / S t a t u s 6 BSY SBSY/ Status 5 SEL SSEL/ Stat us 4 AT N S A T N / S t a t u s 3 MSG SMSG/ Stat us 2 C_D S C_D/ Status 1 I_O SI_O/ Status 0 Register: 0 x0C DMA Status (DST A T) Read Only Readin g this regis ter cle ars any bits tha t are set at t he time the register is read, but does not neces [...]

4-40 Re gist ers MDPE Master Dat a P arity Error 6 This b it is set whe n the LSI53C 875A as a mas ter det ects a data par ity error, or a target device signals a pa rity er ror duri ng a data phase. This bit is compl etely disa bled b y the M aster P arity Err or Enab le bit ( bit 3 of Ch ip T est F our (CTEST4) ). BF Bus Fault 5 This b it is set [...]

SCSI Registers 4-41 • Duri ng a T ransfer Control ins truc tion, the Co mpare Data (bit 18 ) and Compa re Pha se (bit 17 ) bits ar e set in the DMA Byte Coun ter (DBC) regis ter whil e the LSI53C875 A is i n target mode. • Duri ng a T ransfer Control ins truc tion, the Ca rr y T e st bit (bit 2 1) is set and either the Comp are Data ( bit 18) o[...]

4-42 Re gist ers Register: 0 x0D SCSI Status Ze ro (SST A T0) Read Only ILF SIDL Least Signif icant Byte Fu ll 7 This bit is set when t he least sign ificant byte in the SCSI Inpu t Data Latch (S IDL) registe r cont ains dat a. Data is transferred from the SCSI bus to the SCSI Inp ut Data Latch registe r before being s ent to th e DMA FIF O and the[...]

SCSI Registers 4-43 AIP Arbitr ation in Pr ogress 4 Arbitration in Progress (AI P = 1) indica tes that the LSI53C875 A has detec ted a Bus F r ee cond ition, asse r ted SBSY , and asse r t ed its SCSI ID onto the SCSI bus. LO A Lost Arbitration 3 When set, LOA indicat es that the LSI53C 875A has dete cted a bu s free cond ition, ar bitr ated f or t[...]

4-44 Re gist ers synchron ous da ta transfers, or up to 31 word s f or wide. V alue s ov er 31 will not occ ur . T able 4.6 SCSI Synchr onous Data FIFO W ord Count FF4 (SST A T2 bit 4) FF3 FF 2 FF1 FF0 Bytes or W ords in the SCSI FIFO 0 0000 0 0 0001 1 0 0010 2 0 0011 3 0 0100 4 0 0101 5 0 0110 6 0 0111 7 0 1000 8 0 1001 9 0 1 010 1 0 0 1 011 1 1 0[...]

SCSI Registers 4-45 SDP0 L Latc hed SCSI P arity 3 This bit ref lects the SCSI p arity s ignal (SDP 0/), corre sponding to th e data latched i n the SCSI Inpu t Data Latch (SI DL) . It cha nges when a n e w byte is latched into the least signi ficant byte of the SIDL registe r . This bit is active HIGH, in other word s, it is set w hen t he par ity[...]

4-46 Re gist ers Register: 0 x0F SCSI Status T w o (SST A T2) Read Only ILF1 SIDL Most Significant Byte Full 7 This bit i s set when t he mos t significa nt byte in the SCSI Inpu t Data Lat ch (SI DL) cont ains d ata. Data is transferred from the SCSI bus to the SCSI Inpu t Data Latc h register before being sent to the DMA FIFO and then to the hos [...]

SCSI Registers 4-47 fi eld, s ee the defini tion f or SCSI Stat us One (SST A T1) bits [7:4]. SPL1 Latched SCSI P arity for SD[15:8] 3 This acti v e HIGH bi t reflects the SCS I odd par ity s ignal corre sponding to the da ta latched into th e most s i g n i f i c a n tb y t ei nt h e SC SI Input Data Latch (SIDL) registe r . R Reser ved 2 LDSC Las[...]

4-48 Re gist ers Register: 0 x14 Interrup t Status Zero (IS T A T0) Read/Write This reg ister i s acces sible by the host CPU while a L SI53C8 75A is ex ecuting SCRIPT S (without inte rf er ing in the ope ration of the function ). It is use d to poll for interr upts if hard ware interr upts a re disabled. Read this regis ter after ser vic ing an in[...]

SCSI Registers 4-49 clear t he ID Mod e bit or a ny of the PCI co nfiguration registe rs. This bit is no t self-c lear ing; i t must be cl eared to clear the reset conditi on (a hardware reset also cl ears this bit). SIGP Signa l Proce ss 5 SIGP i s a R/W b it that is wr itable at any tim e, and pol led and res et using C h i p Te s t Tw o ( C T E [...]

4-50 Re gist ers the SCRIPTS proc essor is still ex ecut ing a SCRIPTS program. If this bit is set when th e Interrup t Sta tus Zero (IST A T0) or Interr upt Stat us One ( IST A T1) regi sters ar e read they are not auto matic ally cle ared. T o c lear this b it, writ e it to a one. The rese t operatio n is sel f-clear ing. Note: If the INTF bit is[...]

SCSI Registers 4-51 • A bus fault is detecte d • An abor t cond ition is detect ed • A SCRIPTS instr uction i s ex ecuted in singl e step mode • A SCRIPTS interr upt i nstr uction i s ex ecu ted • An illegal in str uction is de tected T o deter mi ne exactly which c ondit ion(s) c aused the interr upt, r ead the DMA Status (DST A T) regis[...]

4-52 Re gist ers addition , this bit ma y be read and wri tten while SCR IPTS are ex ecut ing. Register: 0 x16 Mailbox Zero (MBO X0) Read/Write MBO X 0 Mailbo x Zer o [7:0 ] These are general pur pose bits that may be read or writ ten whil e SCRIPT S are r unnin g. They also may be read or writt en by the SCRIPTS pr ocessor . Note: The h ost and th[...]

SCSI Registers 4-53 Register: 0 x18 Chip T est Zero (CTEST0) Read/Write FMT Byte E mpty in DMA FIFO [7:0] These bits iden tify the bottom bytes in the DM A FIFO that are empty . Eac h bit cor respond s to a byte lane in the DMA FIFO . For e xample, if byte lane three is empty , then FMT3 will be set. Sinc e the FMT flags ind icate the status of b y[...]

4-54 Re gist ers Register: 0 x1A Chip T est T wo (CTEST2) Read Only (bit 3 w r ite) DDIR Data T ransfer Di rection 7 This stat us bit indicate s whic h direc tion data i s being transferred. When th is bit is s et, the data is transferred from the S CSI bus to the host bus. When th is bit is clear , the d ata is tr ansf erred from th e hos t bu s t[...]

SCSI Registers 4-55 Base Addres s Regi ster One (ME MOR Y) .T h i si st h e memor y m apped o perating re gister bas e addres s. Bits [9:0] will be 0. The SCRA TCHB r egister contains bits [31:13] of the RAM B ase Addr ess value from the P CI Base Add ress Reg ister T wo (SCRIP TS RAM) .T h i si st h e base addr ess for the inter nal 4 Kbytes RAM. [...]

4-56 Re gist ers Register: 0 x1B Chip T est Th ree (CTE ST3) Read/Write V C h i pR e v i s i o nL e v e l [ 7 : 4 ] These b its iden tify the c hip revision lev e l for software pur poses. I t should hav e the sa me value as t he lower nibble of the PCI Re vision ID (Re v ID ) registe r , at a ddress 0x08 in t he configu ration spa ce. FLF Flush DM[...]

SCSI Registers 4-57 WRIE Write and Inv alida te Enable 0 This bit, w hen se t, causes the iss uing of Wri te and Inv alid ate comma nds on the PCI b u s whenev er legal . The Wr ite an d Inv a lidate E nable bit in the PCI Config uration Comm and regis ter must al so be set in order for the chip to gene rate Wr ite and Invalidate comm ands. Regist [...]

4-58 Re gist ers while data is being transferred between t he two cor es. Once the chip has stop ped transferring data, thes e bits ar e st abl e. The DMA FIF O (DFIF O) regist er counts th e number of bytes transf erred between the DMA cor e and the S CSI core. The DMA Byte C ounter (DBC) regis ter coun ts the num ber of by tes tra nsf erred acro [...]

SCSI Registers 4-59 Register: 0 x21 Chip T est Four (CTEST4) Read/Write BDIS Burst Disable 7 When set , this bit causes the LSI5 3C875A to p erform bac k-to-b ac k cyc les f or all t ransf ers . When thi s bit is cleare d, back-to-back transfers for opcode f e tches and burst transf e rs f or data moves are perf or med. FBL3 FIFO Byte Contr ol 6 Th[...]

4-60 Re gist ers LSI53C875 A is inf or med of the error by the PERR/ pin being as ser ted by the target. When t his bi t is clea red, the LSI53C 875A does not in terr upt if a master parit y error occurs. Thi s bit is clea red at power-up. FBL[2:0] FIFO Byte Control [2:0] These bits stee r the cont ents of the Chip T est S ix (CTEST6) register to t[...]

SCSI Registers 4-61 the curr ent DBC value. This bit automatic ally cle ars itse lf after incr ementing t he DNAD r egister. BBCK Clock Byte Counter 6 Settin g this bi t decrem ents th e byte count co ntained in the 24-bi t DBC regi ster . It is d ecremen ted based o n the DMA Byte Counter (DB C) cont ents and the c urrent DMA Next Address (DNAD ) [...]

4-62 Re gist ers BO[9:8] DM A FIFO Byte Offset Counter , Bits [9:8] [1:0] These a re the upp er two bits of the DFBOC. The DFBO C consis ts of thes e bits, and the DMA FIFO (DFIFO) registe r , bit s [7:0]. Register: 0 x23 Chip T est Six (CTEST6 ) Read/Write DF DMA FIF O [ 7:0] Wri ting to this reg ister wr ites data to the ap propr iate byte lane o[...]

SCSI Registers 4-63 LSI53C 875A. Th e DBC c ounter is decrem ented ea ch time da ta is transferred on the PCI bus. It is decrem ented by an amount equ al to the numb er of bytes tha t are transferred. The maximum numbe r of b ytes that ca n be transferred in any one Blo ck Mov e c ommand i s 16,777,2 15 bytes. The maximum value th at can b e loaded[...]

4-64 Re gist ers Regist er s: 0x28–0 x2B DMA Next Address (DNA D) Read/Write DNAD DMA Next Address [31:0] This 32-bi t register c ontains the general p ur pose a ddress pointer . At the star t of s ome SCRIP TS operations, its v alue is copied fr om the DMA SCRIPTS Pointer Sav e (DSP S) regi ster . Its v alue ma y not be v alid e xcept i n cer ta[...]

SCSI Registers 4-65 Regist er s: 0x30–0 x33 DMA SC RIPT S Pointer Save (D SPS) Read/Write DSPS DMA SCRIPTS P o inter Save [31:0] This register conta ins the second Dword of a SCRIPTS instr uct ion. It i s ov erwr itten each tim e a SCR IPTS instr uct ion is f etched. When a SCRIP TS interr upt instr uct ion is ex ecute d, this regi ster holds the[...]

4-66 Re gist ers Register: 0 x38 DMA Mode (DMODE) Read/Write BL[1:0] Burst Le ngth [7:6 ] These b its cont rol the ma ximum numb er of D words transferred per b us ownership, r e gardles s of whether the transfers are back-to-b ack, b urst, o r a comb inatio n of both. The L SI53C8 75A asse r ts t he Bus R equest ( REQ/) output whe n the DMA FIFO c[...]

SCSI Registers 4-67 SIOM Source I/O Me mory E nable 5 This bit is defined as an I/O Memor y E nable bit f or the source addr ess of a Memo r y Move or Block Mov e Command. If th is bit is s et, then the source ad dress is in I/O space; and if clear ed, then the source addre ss is in memor y spac e. This functi on is usefu l f or reg ister- to-memor[...]

4-68 Re gist ers ERMP Enable Read Multiple 2 If this bi t is set a nd cache mode is e nabled, a Rea d Multiple comm and is us ed on a ll read cy cles whe n it is legal. BOF Burst Opcode Fetc h Enable 1 Settin g this bit causes the LSI53C 875A to fetch inst r uctions in b urst mode . Specifica lly , the chip b ursts in t h ef i r s tt w oD w o r d s[...]

SCSI Registers 4-69 Register: 0 x39 DMA Interrupt Enable (DIEN) Read/Write R Reser ved 7 MDPE Master Dat a P arity Error 6 BF Bus Fault 5 ABRT Aborted 4 SSI Single Step Interrupt 3 SIR SCRIPT S Int errupt I nstru ction Rec eived 2 R Reser ved 1 IID Ille gal Instruction Detected 0 This reg ister contain s the interr upt mask bi ts corre sponding to [...]

4-70 Re gist ers F or m ore informat ion on interr upts, see Chapter 2, “Functiona l Descript ion” . Register: 0 x3A Scratch Byte Regis ter (SBR) Read/Write SBR Sc ratch Byte Re gister [7:0] This is a general pur pos e regis ter . A par t from C PU access, only regi ster Read/Wr ite and Memor y Moves into this regis ter alte r its co ntents. Th[...]

SCSI Registers 4-71 the LSI53C 875A to make more efficient use of the syste m PC I bus , thus imp rovin g o v eral l syste m performa nce. The unit will flush when ev er the PF F bit is set, as well as on all transfer control instr uctio ns when the transfer conditions are met, o n ev er y writ e to the DMA SCRIPTS P ointer (DSP) , on ev er y reg u[...]

4-72 Re gist ers STD Start DMA Operation 2 The LSI5 3C875A fetches a SCS I SCRIPT S inst ru ction from the a ddress co ntained i n the DMA SCRIP TS P ointer (DSP) regist er when this bi t is set. This bit is req uired if the LSI 53C8 75A is in o ne of the f o llowing m odes: • M a n u a ls t a r tm o d e–B i t0i nt h e DMA Mode (DMODE) registe [...]

SCSI Registers 4-73 Regist ers: 0x3C–0x3F Adder Sum Output (ADDER) Read Only ADDER Adder Sum Output [31:0] This reg ister c ontains th e outpu t of t he inter n al adder , and is used pri mari ly f or test pur pose s. The power-up v alue for this register is ind eter mina te. It is used t o deter mi ne if the correct me mor y addr ess was calcula[...]

4-74 Re gist ers CMP Function Complete 6 Indicate s full arbi tration and sel ectio n sequence i s complet ed. SEL S elected 5 Indicate s the LSI53C 875A is sel ected by a SCSI i nitiator device. Set the Enable Respon se to S electio n bit i n the SCSI Chip ID (SCID) reg ister f or this to occur . RSL Reselec ted 4 Indicate s the LSI53C 875A is r e[...]

SCSI Registers 4-75 RST SCSI Reset Condition 1 Indicate s asser tion of the S RST/ si gnal by the LSI53C 875A or any other SCS I device. This conditio n is edge-tr igger ed, so mult iple inter ru pts canno t occur because of a singl e SRST / pulse. PA R S C S I P a r i t y E r r o r 0 Indicate s detecti on by the LSI53C 875A of a par ity err or whi[...]

4-76 Re gist ers HTH Handshake-to-Handsha ke Timer Expired 0 The han dshake-to-hand shake tim er is expired. T he tim e measur ed is the S CSI Req uest-to-Req uest (targe t) or Acknowledge-to-A cknowledge (initia tor) per iod. See t he descr iption of the SCSI Timer Zero (S TIME0) register, bits [7:4] , for more informatio n on the handshake- to-ha[...]

SCSI Registers 4-77 target. In target mode, this bi t is set wh en the S A TN/ signal is as ser ted by the initiator . CMP Function Complete 6 This bit i s set whe n an arbit ration only or full arbitration seque nce is c omple ted. SEL S elected 5 This bit is set when the LSI53C875 A is sel ected b y anothe r SCSI device. The Enable Respo nse to S[...]

4-78 Re gist ers • Residual da ta in the synchr onous da ta FIFO – a transfer other tha n synch ronou s data re ceive is star ted wit h data left i n the sy nchronou s data FIFO . UDC Unexpected Disconnect 2 This bit is set when the LSI53C875 A is operating in the initiato r mode and the target device unexpectedly discon nects from th e SCSI bu[...]

SCSI Registers 4-79 (SIEN1) register or not. Eac h bit that is set ind icate s an occur rence of the correspo nding con ditio n. Readin g the SI ST1 clear s the int err upt con ditio n. R Reser ved [7:3] STO Select ion or Rese lection Time -out 2 The SCSI device which the LSI53 C875A is attempting to sele ct or re select d oes no t respond within t[...]

4-80 Re gist ers check byte are rec eived from the S CSI bus (all si gnals are shown active HIG H): A one in any bit posi tion of the fi nal SLP AR value would i n d i c a t eat r a n s m i s s i o ne r r o r . The SLP AR regis ter is also use d to generate the check bytes f or SCSI send o peration s. If the SLP A R regist er contains al l zeros pr[...]

SCSI Registers 4-81 W h i c hb y t ei sa c c e s s e di sc o n t r o l l e db yt h eS L P H B E Nb i t in the SCSI Control T wo (SCNTL2) register . Register: 0 x45 SCSI Wide Residue (SW IDE) Read/Write SWIDE SCSI Wide R esidue [7:0] After a wi de SCSI da ta recei ve operation, this r egister conta ins a residual da ta byte if the last byte received[...]

4-82 Re gist ers DW R D a t a W r i t e 3 This bi t is used to defi ne if a data write is c onsidered t o be a lo cal m emor y acce ss. DRD Data Read 2 This bit is used to define if a data read is consider ed to be a lo cal m emor y acce ss. PSCPT P ointer SCRIPTS 1 This bit i s used to define if a po inter to a SCRIPT S indirec t or table indirect[...]

SCSI Registers 4-83 LEDC LED_CNTL 5 The inte rn al connec ted sign al (bit 3 of the Inter r upt S tatu s Zero (IST A T0) regi ster) wil l be pres ente d on GPIO0 i f this bit is set a nd bit 6 of GP CNTL0 is c leared an d the c hip is not in progress of perfor ming a n EEPROM autodownlo ad regar dless of the sta te of bit 0 (GPI O0). This provid es[...]

4-84 Re gist ers SEL[3: 0] Select ion Time-O ut [3:0] These b its select t he SCSI s elect ion/resel ection tim e-out period. Wh en this timi ng (plus the 200 µ s selec tion a bor t time) is exceede d, the STO bit in the SC SI Inter rup t Status One (SIS T1) registe r is set. For a mo re det ailed ex planati on of inter rup ts, ref er to Cha pter [...]

SCSI Registers 4-85 Register: 0 x49 SCSI Timer One (STIME1) Read/Write R Reser ved 7 HTHB A Handshake-to- Handshake Timer Bus Activity Enable 6 Setting thi s bit caus es this time r to begin tes ting for SCSI REQ/, ACK/ activit y as soon as SBSY/ is as ser ted, regard less of the agents par ticipat ing in the transfer . GENSF General Purpo se Timer[...]

4-86 Re gist ers Register: 0 x4A Resp onse ID Zer o (RES PID0 ) Read/Write RESPIO0 Res ponse ID Zero [7:0] RESPID0 and Respon se ID One (RESPID1) contain t he selecti on or re selecti on IDs. In other words, these two 8-bit regi sters c ontain the I D that the c hip respo nds to o n the SCSI bus. Each bi t represent s one pos sible ID with the most[...]

SCSI Registers 4-87 c h i p c a na r b i t r a t e w i t ho n l yo n eI Dv a l u ei nt h eS C I D registe r . Register: 0 x4C SCSI T est Zero ( STEST0) Read Only SSAID SCSI Sele cted As ID [ 7:4] These bits c ontain the e ncoded value of t he SCSI ID th at the LSI53C 875A is selected dur ing a SCSI sel ection phase. Th ese bits wo rk i n conju ncti[...]

4-88 Re gist ers SOM S C SI Synchr onous Offset Maxim um 0 This bi t indicate s that the cu rrent synch ronou s SREQ /, SA CK/ of fset is the ma ximum spec ified by bits [3:0 ] in the SCSI T ran sfer (SXFER ) reg ister . This b it is no t latch ed and may change at any time. It is us ed in low lev el synchron ous SCSI ope rations. When this bit is [...]

SCSI Registers 4-89 QSEL SCLK Qua drupler Se lect 2 This bit , when set , sel ects the ou tput of the interna l clock quadr upler for use a s the inte rn al SCS I clock. Whe n cleare d, this bit sel ects the clo ck presented on S CLK for use as th e inter nal S CSI clock. R Reser ved [1:0] Register: 0 x4E S C S I Te s t Tw o ( S T E S T 2 ) Read/Wr[...]

4-90 Re gist ers SZM SC SI Hi gh Imped ance Mo de 3 Settin g this bi t places all the op en drain 48 mA SCSI dri v ers into a hi gh impedan ce state. This is to allow inter na l loopback mod e operation withou t affecting the SCSI bus. A W S A l w a y sW i d eS C S I 2 When t his bit i s set, al l SCSI inform ation t ransf e rs are done in 16-b it [...]

SCSI Registers 4-91 Register: 0 x4F SCSI T est Three (STE S T3) Read/Write TE T olerANT E nable 7 Settin g this bi t enables the ac tive negation po r tion of LSI Logic T oler ANT tec hnology . Act ive negation c auses the SCSI Re quest, Acknowledge, Data, and P a rity signals to be a ct ively deasse r ted, inste ad of r elying o n ex ter nal pull [...]

4-92 Re gist ers f o r test pur pos es or to lower I DD during a po wer -down mode. DSI D isa ble S ing le I ni tia tor R es pons e 4 If this bit is se t, the LSI53 C875A ign ores all bus-initia ted selecti on attempts th at employ the single in itiator opti on from SCS I-1. In orde r to selec t the LS I53C8 75A while this bit is set, t he LSI53C87[...]

SCSI Registers 4-93 STW SCSI FIF O T est Write 0 Settin g this bit places th e SCSI c ore in to a test mo de in which the FIFO is easi ly read or writ ten. While this bit is set, wri tes to the le ast signifi cant byte of the SCSI Outp ut Data Latch (SO DL) register cause t he entir e word containe d in the SODL to be loaded into the FIFO . These f[...]

4-94 Re gist ers Register: 0 x52 SCSI T est Four (STEST4) Read Only R Reser ved [7:6] LOCK Frequenc y Lock 5 This bit i s used w hen en abling the SCSI clock quadr upler , whic h all ows the LSI 53C875A to tr ansf er data at Ul tra SC SI rates. P oll t his bit for a 1 to deter mine tha t the cl ock quadr upler h as locked. F or m ore infor mation o[...]

SCSI Registers 4-95 Register: 0 x56 Chip Control 0 (CCNTL0) Read/Write ENPMJ Enable Phase Mism atch Jump 7 Upon setti ng this bi t, any phase m isma tches do not interr upt but force a jump to an al ter nate loc ation to handle the phase mism atch. Pr ior to actuall y takin g the jump, the appropr ia te remain ing byte co unts and address es will b[...]

4-96 Re gist ers ENNDJ Enable Jump on Nondata Phase Mismat ches 5 This b it contro ls wheth er or not a j ump is tak en during a nond ata phase mis match (i.e . messa ge in, mes sage out, status, or c omman d). When t his bit i s clear, jumps will only be t aken on Data-In o r Data-Out phase s and a phase mism atch interr up t will be generated f o[...]

SCSI Registers 4-97 Register: 0 x57 Chip Control 1 (CCNTL1) Read/Write ZMOD E High Im pedance Mo de 7 Settin g this b it ca uses the LSI53C875A to plac e all ou tput and bidir ectiona l pins except M AC/_TEST O UT , into a high imped ance state. Also, setting this bit causes all I/O pins to becom e inputs, and all pul l-ups and pull-downs to be dis[...]

4-98 Re gist ers Index Mode 1 (64TIMOD set) table entr y f or m at: EN64TIBMV Enable 64-Bit T able Indirect BMO V 1 Settin g this bi t enables 64-b it addr essin g for T able Indirect B MO Vs us ing th e upper byte (bit [24:31]) o f the first Dword of the table entr y . W hen this b it is cleared table indirec t BMOVs will use the S tatic Block Mov[...]

64-Bit SCRIPTS Selec tors 4-99 Regist er: 0x5A–0x5B Rese rved Regist ers: 0x5C–0x5F Scratch Regis ter B (SCRA TCH B) Read/Write SCRA TCHB Scratch Register B [31:0] This is a general pur pos e use r definable s cratch pad registe r . Apa r t from CPU ac cess, on ly registe r Read/Wr ite and Memor y Moves directed at the SCRA TCH regi ster will a[...]

4-100 Reg i sters operation is performed , one of the six s elector r egister s below will be used to ge nerate a 6 4-bit add ress. If the sel ector for a par ticular device operation is zero , then a s tandard 32-bit a ddress cy cle w ill be gen erated. If the selec tor value is non zero , then a DA C wil l be iss ued and the 64-bi t addres s will[...]

64-Bit SCRIPTS Selec tors 4-101 Register s: 0xA4–0x A 7 Memor y Move Write Selector ( MMWS) Read/Write MMWS Memor y Move Write Se lector [31:0] Supplie s the upper Dword of a 64-bit addres s duri ng data writ e operations dur ing Me mor y-to-M emor y Moves and absolute add ress STORE operations. A special mo de of this register can be e nabled by[...]

4-102 Reg i sters Write s to th e SFS regi st er are una ffe cted. Cl earing t h e PCI Confi guratio n Into Ena ble bit causes the S FS reg ister to retur n to nor mal o peratio n. Regist ers: 0xA C–0xAF DSA Relative S elector (DRS) Read/Write DRS DSA Relative Sele ctor [31:0] Supplie s the u pper Dword of a 64-bit addre ss dur ing table indirect[...]

Phase M isma tch Jump Reg ist ers 4 -1 03 Register s: 0xB4–0x B 7 Dynamic Block Move Sel ector (DBMS) Read/Write DBMS Dynamic Block Move Select or [ 31:0] Supplie s the u pper Dword of a 64-bit addre ss dur ing bloc k move operations, reads or wr ites. This reg ister is used only du ring 64 -bit dire ct BMO V instr ucti ons and will be reloaded w[...]

4-104 Reg i sters Register s: 0xC0–0x C 3 P h a s eM i s m a t c hJ u m pA d d r e s s1( P M J A D 1 ) Read/Write PMJAD1 Phase Mismatch Jump Address 1 [ 31:0] This reg ister c ontain s the 3 2-bit add ress that will be jumped to up on a phas e mismatc h. Depend ing upon t he state o f the PM JCTL bi t in regi ster Chip Control 0 (CCNTL0) this add[...]

Phase M isma tch Jump Reg ist ers 4 -1 05 Register s: 0xC8–0x C B Remaining Byte Count (RBC) Read/Write RBC Remaining Byte Count (RBC) [31:0] This regi ster co ntains the byte coun t that re mains for the BMO V that was ex ecuting when the pha se mism atch occurr ed. In the cas e of dir ect or in direct BMO V instr uct ions, the up per byte of th[...]

4-106 Reg i sters In the cas e of a S CSI dat a receive, if ther e is a byte in the SCSI Wi de Residue (SWI DE) register th en this address wi ll point to the locat ion where tha t byte must be stored. The SWID E byte must be manual ly wr itten to memor y an d this addres s must be in crem ented pr ior to updating a ny scatter/ gather en tr y . In [...]

Phase M isma tch Jump Reg ist ers 4 -1 07 Register s: 0xD4–0x D 7 Instructio n Address (IA) Read/Write IA Instru ction Address [31:0] This reg ister al wa ys conta ins th e addres s of the BMO V instr uct ion tha t was ex ecuti ng when the phase m isma tch occurre d. Thi s value will always match th e value in the Entr y Storage Ad dress ( ESA) e[...]

4-108 Reg i sters canno t be counte d f or th is BMO V as it was actually p ar t of the byte coun t for the pre v ious B MO V . Register: 0 xDB Rese rved Registers: 0x DC–0xDF Cumulat ive SCSI Byte Count (CSBC) Read/Write CSBC Cumulati ve SCSI Byte Count [31:0] This loadable regi ster conta ins a cumulat ive count of the actual numb er of bytes t[...]

LSI53C8 75A PCI to Ultra SCSI Controll er 5-1 Chapter 5 SCSI SCRIPTS Instruction Set The LSI5 3C875A c ontains a SC SI SCRI PTS proc essor that per mi ts both DMA and S CSI com mands to b e fetched from host memo r y or int er nal SCRIPT S RAM . Algor ith ms wr itten i n SCSI S CRIPTS c ontro l the acti ons of the SCSI and DMA cores. The S CRIPTS p[...]

5-2 SCSI SCRIPTS Instruction Set require cer tain unique tim ings or bus sequence s to operate properl y . Another feature allowed at t he low le v el is loop back testing. In l oopback m o d e ,t h eS C S Ic o r ec a nb ed i r e c t e dt ot a l kt ot h eD M Ac o r et ot e s t inter nal da ta paths all the way out to the c hip’ s pi ns. 5.2 High [...]

High Le v el SCSI SCRIPTS Mode 5-3 Each in str uctio n cons ists of two or three 32 -bit wor ds. The first 32-bi t wo rd is alw a ys loaded in to the DMA Command (DCM D) and DMA Byte Counter (DBC) regi sters, th e second in to th e DMA SCRIPTS P o inter Save (DSPS) r egister . The third word, used o nly by Memory Move instr ucti ons, is loaded in t[...]

5-4 SCSI SCRIPTS Instruction Set • The LSI5 3C875A typ ically fetches two Dword s (64 bit s) and de codes the high or der byte of the fir st longword as a SCRIPTS instr ucti on. If the instr ucti on is a B lock Mov e, t he lower three bytes of t he fir st longword are s tored an d inter preted as the number o f bytes to be mov ed. The s econd l o[...]

High Le v el SCSI SCRIPTS Mode 5-5 Figure 5.1 SCRIPTS O verview System Processor System Memory SCSI Initi ator Write Exam ple × Select A TN 0, alt_addr × Move from identi fy_msg_buf, when MSG_ OUT × Move from data_buf when DA T A _OUT × Move from stat_i n_buf, when ST A TUS × Move SCNTL2 & 7F to SCNTL2 × Clear ACK × Wail disconnect a lt2[...]

5-6 SCSI SCRIPTS Instruction Set 5.3 Bloc k M o ve Instructi o n P erformi ng a Block Move instr uction, bit 5, S ource I/ O - Memor y Enable (SIOM) and bit 4, Destin ation I/O - Me mor y Ena ble (DIOM) in the DMA Mode (DMODE ) registe r deter min es whether th e source/de stinatio n address reside s in memo r y or I/O space. When d ata is bei ng m[...]

Bloc k M o ve Inst r uction 5-7 Direct Addressi ng The b yte count a nd absolut e addr ess ar e: Indirect Addressing Use the f etched byte count, b ut f etch the data addr ess from the address in the instr ucti on. Once the data po inter add ress i s loaded, it is ex ecuted as when th e chip operates in the dire ct mode. Thi s indi rect f eatu re a[...]

5-8 SCSI SCRIPTS Instruction Set the data str ucture. Sign extended v alues of all ones f or negative values are allowed, but bits [31:24] ar e ignored . Note: Do no t use ind irec t and ta ble indirect addre ssin g simultaneo usly; us e only one addr essing m ethod at a tim e. P r i o rt ot h es t a r to fa nI / O ,t h e Da ta Str ucture A ddress [...]

Bloc k M o ve Inst r uction 5-9 OPC OpCode 27 This 1-b it OpCode field d efines th e type of Block Mov e (MO VE ) Instru ction to be p ref or med in T a rget and Initi ator mode. T arget Mode In T arget m ode, the Op Code bit def ines t he following operations: These ins truc tions pe rf or m the following steps : 1. The LSI5 3C875A verifies that i[...]

5-10 SCSI SCRIPTS Instruction Set registe r contai ns 0x000 000, an illegal instr uction interr upt is ge nerated. 4. The LSI5 3C875A transfers the number of bytes sp ecified in the DBC registe r star ting at the addr ess sp ecified in the DMA Next Address (DNAD) r egister. If the OpCode bit i s set and a data transfer ends on an odd byte bounda r [...]

Bloc k M ov e Instruction 5-11 registe r . Thes e phase l ines ar e latched when SRE Q/ is asser ted . 4 . I ft h eS C S Ip h a s eb i t sm a t c ht h ev a l u es t o r e di nt h eS C S I SCSI S tatus One ( SST A T 1) reg ister , th e LSI53 C875A transfers the number of bytes spec ifie d in the DMA By te Counter (DBC) registe r star ting at t he ad[...]

5-12 SCSI SCRIPTS Instruction Set TC[23:0] T ra nsfer Counter [23:0] This 24 -bit field spe cifies th e number of data bytes to be mov ed between the LSI53C8 75A and system mem or y . The fie ld is stor ed in the DMA Byte Cou nter (DBC) registe r . When th e LSI53 C875A t ransf e rs data t o/from memor y , the DB C registe r is dec remente d by the[...]

I/O Ins tr uc tion 5-13 5.3.2 Second Dwor d Star t Address [31:0] This 32-b it field s pecifie s the sta r tin g address of the data to mov e to/from mem or y . T his field is copi ed to the DMA Ne xt Address ( DNAD) regi ster . When th e LSI53C 875A transfers data to or f rom memo r y , t he DN AD regis ter is increm ented by the num ber of bytes [...]

5-14 SCSI SCRIPTS Instruction Set 5.4.1 Fi rst Dw ord IT[1:0] Instruction T ype - I/O Instruc tion [31:30] The IT bit co nfiguration (01) de fines an I/O Ins truc tion Ty p e . OPC[2:0] OpCo de [29:27] The OpC ode bit co nfiguration s define the I/O operation performe d but the OpCode bit mea nings change in T arg et mode com pared to In itiato r m[...]

I/O Ins tr uc tion 5-15 This w ay th e SC RIPT S can mo ve on to th e ne xt instr uct ion before the r eselect ion co mplete s. It continues ex ecuting S CRIPTS u ntil a SCRIPT th at requir es a response f rom th e Initiator i s encoun tered. If the LSI53 C875A is selecte d or resel ected before winning a rbitratio n, it fetches the next instr ucti[...]

5-16 SCSI SCRIPTS Instruction Set When t he SACK/ or SA TN/ b its are cleared , the corre sponding bits a re clea red in the SCSI Ou tput C ontrol La tch ( SOCL) reg ister . Do not set SA CK/ or SA TN/ e xcept f or testi ng purposes . When the target bi t is cle ared, the c orrespon ding b it in the SCSI Control Ze ro (SCNTL0) registe r is cl eared[...]

I/O Ins tr uc tion 5-17 the LSI53C87 5A to Initi ator mode if it is res elected , or to T arget mod e if it is selected . If the Sele ct with SA TN/ fiel d is set, the SA TN/ s ignal is asser ted dur i ng the sel ectio n phas e. W ait Disconnect Instruction The LSI53 C875A waits for the T arg et to perform a “leg al” discon nect from the SCS I [...]

5-18 SCSI SCRIPTS Instruction Set RA Relative Addressing Mode 26 When this bit is set, the 24-bi t signed value in the DMA Ne xt Address ( DNAD) regi ster is us ed as a relative displac ement from th e current DMA SCRI PTS P ointe r (DSP) address. Us e this bi t only in conju nction wi th the Select , Resele ct, Wait Select , and Wait Reselec t ins[...]

I/O Ins tr uc tion 5-19 Use this b it only in con junc tion with the S elect , Rese lect, W ai t Selec t, and Wait Reselect in str uct ions. Use bits 25 and 26 individ ually or in = comb inatio n to produce the f o llowin g conditi ons: Direct Uses the dev ice ID a nd physical addre ss in the instr u ction . T able Indirect Uses the phy sical ju mp[...]

5-20 SCSI SCRIPTS Instruction Set T able Relat ive T reats the alter nate ju mp addres s as a rel ative jump and f e tches the device ID , s ynchron ous offse t, and synchron ous p erio d indi rectly . The value in bits [ 23:0] of the firs t four b ytes of th e SCRIPTS i nstr uction i s added to the data s tru cture bas e addres s to form the fetch[...]

I/O Ins tr uc tion 5-21 R Reser ved [8:7] A CK Se t/Clear SA CK / 6 R Reser ved [5:4] A T N Set/ Clear SA TN/ 3 These two bits are u sed in c onjun ction wi th a Set o r Clea r instr uct ion to asser t or d easse r t th e corr espondin g SC SI control s ignal. Bi t 6 contr ols the SCS I SA CK/ si gnal. Bit 3 control s the SCSI SA TN/ signal. T h eS[...]

5-22 SCSI SCRIPTS Instruction Set If rela tive or table relat ive address ing is used, th is value is a 24- bit sign ed offset r elative to the cur rent DMA SCRIPT S P o inter (D SP) regis ter value. 5.5 Read/Write Instru ctions The Read/ Wr ite instr uctio n supp or ts ad dition , subtracti on, and compar ison of two sepa rate values within th e c[...]

Read /Wr ite In str uct io ns 5-23 A[6:0] Regis ter Address - A[6:0] [22:16] It is possible to c hange re gister values from SCRIP TS in read-modi fy-wr ite cycl es or move to/from SFB R cycle s. A[6:0] se lects an 8-bit so urce /destinati on registe r within the LSI53C8 75A. ImmD Immediate Data [15:8] This 8-b it value is used a s a seco nd operan[...]

5-24 SCSI SCRIPTS Instruction Set 5.5.4 Mov e T o/From S F BR Cycles All operatio ns are r ead-modi fy-wr ites. Howe ver , two register s are inv o lved, one o f whic h is al wa ys the S FBR . Ta b l e 5 . 3 sho ws the possi bl e read-m odify-wr ite o perations. Th e possible fun ctions o f this in stru ction are: • Wri te one byte (v alue con ta[...]

T ransf er Control Instructio ns 5-25 Misce llaneous Notes: • Substi tute the desired reg ister nam e or address f or “RegA” in the syntax e xamples . • data 8 in dic ates e igh t bit s of dat a. • Use SFBR instead o f data8 to add tw o register v alues. 5.6 T ransfer C ontr ol Instructions This sec tion desc ri bes the T ransfer Control [...]

5-26 SCSI SCRIPTS Instruction Set 5.6.1 Fi rst Dw ord IT[1:0] Instructi on T ype - T ransfer Contr ol Instruc tion [31: 30] The IT bit config uration (10) de fines the T ransfer Control Instruct ion T ype. OPC[2:0] OpCo de [29:27] This 3 -bit fiel d speci fies th e type of T ransfer Contr ol Instr uction t o ex ecute. All T ransfer Control Instr uc[...]

T ransf er Control Instructio ns 5-27 DMA SCRIPTS P ointe r Sav e (DSPS) regis ter . The DSP registe r now contains th e address of the ne x t instr uct ion. If the compar iso ns are false , the LS I53C875A fetches the next instru ction f rom the a ddress poi nted to by the DMA SCRIPT S P o inter (D SP) regist er , leaving the instr ucti on pointer[...]

5-28 SCSI SCRIPTS Instruction Set If the compar iso ns are false , the LS I53C875A fetches the next instr uctio n from the addre ss pointed to by the DSP registe r and the instr uction p ointer is not m odified. Interrupt Inst ruction The LSI5 3C875A can do a tr ue/false compa r ison of th e ALU car r y bit , or comp are the ph ase an d/or data a s[...]

T ransf er Control Instructio ns 5-29 RA Relative Addressing Mode 23 When this bit is set, the 24-bi t signed value in the DMA SCRIPT S P o inter Sav e (DSP S) regist er is used as a relative offset fr om the cu rrent DMA S CRIPTS Pointer (DSP) ad dress (whic h is pointi ng to the next instruc tion, not the o ne current ly ex ecuti ng). The relativ[...]

5-30 SCSI SCRIPTS Instruction Set signed (2’s compleme nt), the jump can be f orward or backward. A relative transfer can be to any add ress wi thin a 16 Mbyte segment. The program counte r is combined with the 24-bit sig ned offset (usi ng addition or subtracti on) to f o r m the new ex ecutio n address. SCRIPTS programs may contain a mixtur e o[...]

T ransf er Control Instructio ns 5-31 CD Compare Data 18 When t his bit i s set, the fir st byte received from the SCSI data bus (contained in the SCSI First Byte Rece ived (SFBR) register) is compar ed with the Data to be Compared Field in th e T ransfer Control instruc tion. The W ai t for V alid Phase bit co ntrol s when this com pare occurs. Th[...]

5-32 SCSI SCRIPTS Instruction Set DCV Data Compare V alue [7:0] This 8-bit fi eld is the data comp ared aga inst the regi ster . These bits are use d in conjunction with the Data Compare M ask Fiel d to test for a par ticular da ta value. 5.6.2 Second Dwor d Jump Address [31: 0] This 32-b it field con tains the add ress of the next instr uct ion to[...]

Memor y Move Instr uc tions 5-33 • Indirec t addres ses are not allowed. A burst of data i s fetched from the source address, put into th e DMA FIFO and then wr itte n out to the desti nation add ress. The m ov e continues until t he byte count decreme nts to zero , t hen another SCRIPTS is fetched from s ystem memor y . The DMA SCRI PTS P oi nte[...]

5-34 SCSI SCRIPTS Instruction Set 5.7.2 Rea d/Writ e Sy stem Me mor y from SCR IPTS By usin g the Me mor y M ov e instr uction, singl e or multip le regis ter values are transferred to or f rom syste m memor y . Beca use the LSI53 C875A res ponds to a ddresse s as define d in the Base Addres s Register Z ero (I/O ) or Base Add ress Regist er One (M[...]

Load and Store Instructio ns 5-35 5.7.4 Thir d Dwor d TEMP Reg ister [31:0] These b its cont ain the des tination a ddress for the Memor y M ov e. 5.8 Load a nd Store Instructions The Load and Stor e instr uctions pr ovide a more efficien t wa y to mov e data from/t o memor y to/ from an int er nal regi ster in the chip wi thout usin g the nor ma l[...]

5-36 SCSI SCRIPTS Instruction Set The SIOM and DIOM bits in the DM A Mode (DM ODE) regi ster deter mi ne whether the de stination o r source addr ess of the ins tru ction is in Me mor y space or I/O s pace, as il lustra ted in the following table. The Load a nd Store util izes the PCI comman ds f or I/O read and I/O wr ite to acces s the I/O space.[...]

Load and Store Instructio ns 5-37 Note: This bit h as no eff ect unles s the Pref etch En able bi t in the DMA Control (DC NTL) re giste r is set . LS Load and Store 24 When t his bit i s set, the instr ucti on is a L oad. Wh en cleare d, it is a Store. R Reser ved 23 RA[6:0] Reg ister Address [2 2:16] A[6:0] selects the regi ster to Lo ad and S to[...]

5-38 SCSI SCRIPTS Instruction Set[...]

LSI53C8 75A PCI to Ultra SCSI Controll er 6-1 Chapter 6 Electrical Specificat ions This sec tion s pecifie s the LS I53C875A electr ic al and mec hanical character is tics. It is di vided i nto the following se ctions: • Secti on 6. 1, “D C Cha ract er isti cs” • Section 6.2, “T olerA NT T ec hnology Electr ical Ch aracter ist ics” • [...]

6-2 Electr ica l Spe cifi cati ons T able 6.1 Ab solute M aximum Stress Rat ings 1 1. Stress es be yond thos e listed abo ve ma y cause permanent damag e to the devi ce. These are st ress rat ings only; funct ional oper ation of the de vice at these or a ny other condi tions bey ond those i n d i c a t e di nt h e Operating Cond itions section of t[...]

DC Characteristics 6-3 T able 6.4 Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/, MOE/, MW E/ Symbol P arameter Min Max Unit T est Conditions V IH Input hig h voltage 2.0 5.25 V – V IL Input lo w voltage V SS − 0.5 0. 8 V – V OH Output high vol tage 2.4 V DD V − 4m A V OL Output low v oltage V SS 0.4 V 4 mA I OZ 3-state le akage − 10 1[...]

6-4 Electr ica l Spe cifi cati ons T able 6.6 Bidirectional S ignals—AD[31:0], C_BE[3:0]/, FRAME/, IRD Y/, TRD Y /, D E V S E L / ,S T O P / ,P E R R / ,P A R Symb ol Para meter Min Max Unit T est Condit ions V IH Input high v oltage 0.5 V DD 5.25 V – V IL Inpu t low voltag e V SS 0.3 V DD V– V OH O utput high voltage 0.9 V DD V DD V − 16 m[...]

T olerANT T echnolo gy Electrical Char acteristic s 6-5 6.2 T olerANT T echnolog y Electri cal C haracteristi cs The LSI5 3C875A features T o lerANT technolo gy , whic h include s ac tive negation o n the S CSI dr ivers and input sig nal fi lter ing on the SCS I receivers. Active nega tion acti vely drives the S CSI Requ est, Acknowledge, Data, and[...]

6-6 Electr ica l Spe cifi cati ons T able 6.11 T oler ANT T echnology Electr ical Chara cteri stics for SE SC SI Signal s Symbol P arameter Min 1 1. These v alues are gu aranteed b y periodic char acterization; the y are not 100% tested on e very device. Max Unit T e st Con di tion s V OH 2 2. Activ e negation out puts only: Data, P ar ity , SREQ/,[...]

T olerANT T echnolo gy Electrical Char acteristic s 6-7 Figure 6.1 Rise and Fall Time T est Condition Figure 6.2 SCSI Input Filtering Figure 6 .3 Hysteres is o f SCSI R eceivers + − 2.5 V 47 Ω 20 pF REQ/ or SACK/ Input t 1 V TH Note: t 1 is the input filtering period. 1 0 Received Logic Le vel Input V oltage (V olts) 1.1 1.3 1.5 1.7[...]

6-8 Electr ica l Spe cifi cati ons Figure 6.4 Input C urrent as a Function of Input V oltage Figure 6.5 Output Current as a Function of Output V oltage +40 +20 0 − 20 − 40 − 4 0 4 8 12 16 − 0.7 V 8.2 V HIGH-Z OUTPUT AC T I V E Input V oltage (V olts) Input Current (milliAmperes) 14.4 V Output Sink Current (milliAmperes) 0 − 200 − 400 ?[...]

A C Char acter istics 6-9 6.3 A C Characterist ics The AC characteri stics d escri bed in this secti on appl y ov e r the e ntire range of ope rating cond itions ( refer to the DC Character istics se ction ). Chip timin gs are ba sed on simula tio n at worst case voltage, te mperature, and process ing. Timing was dev eloped with a load c apacitanc [...]

6-10 Electrical Sp ecificat ions Ta b l e 6 . 1 3 and Figu re 6.7 provide Reset I nput tim ing da ta. Figure 6.7 Reset Input Ta b l e 6 . 1 4 and Figu re 6.8 provide Interru pt Out put timing data. T able 6.13 Reset Input Symb ol P arameter Min Max Unit t 1 Reset pul se width 10 – t CLK t 2 Reset d easser ted setup t o CLK HIGH 0 – ns t 3 MAD s[...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-11 Figure 6.8 Interrupt Output 6.4 PCI an d External Memor y Interface Timing D iagrams Figure 6.9 through F igure 6.32 represent signal a ctivity when t he LSI53C875 A ac cesse s the P CI bus. This s ection i ncludes timin g diagrams for access to three groups of memor y conf igurations. The [...]

6-12 Electrical Sp ecificat ions – Burst Read, 32-Bit Addr ess an d Data – Burst Read, 64-Bit Addr ess an d Data – Burst Write , 32-Bi t Addr ess and Data – Burst Write , 64-Bit A ddr ess and 3 2-Bit Da ta • Ext er nal Memo r y Timin g – Exter nal Mem or y Read – Exter nal Mem or y Wri te – Nor mal/Fast Memor y ( ≥ 1 28 K bytes) S[...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-13 6.4. 1 T arget Timing The tables an d figures in th is sect ion des cr ibe targe t timin gs. Figure 6.9 PCI Configuration Register Read T able 6.15 PCI Configuration Register Re ad Symb ol P arameter Min Max Unit t 1 Shared sig nal input setu p time 7 – ns t 2 Shared signal inp ut hold ti[...]

6-14 Electrical Sp ecificat ions Figure 6.10 PCI Configuration Register W rite T able 6.16 PCI Configuration Register W rite Symb ol P arameter Min Max Unit t 1 Shared sig nal input setu p time 7 – ns t 2 Shared signal inp ut hold time 0 – ns t 3 CLK to shared signa l output val id – 11 ns CLK (Driven by System) FRAME/ (Dr iven by Master) AD [...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-15 Figure 6.11 32-Bit Operating Register/SCRIPTS RA M Read T able 6.17 32-Bit Operating Regis ter/SCRIPTS RA M Read Symb ol P arame ter Min Max Unit t 1 Shared sig nal input setu p time 7 – ns t 2 Shared signal inp ut hold time 0 – ns t 3 CLK to shared signa l output val id – 11 ns CLK ([...]

6-16 Electrical Sp ecificat ions Figure 6.12 64-Bit Address Operating Register/SCRI PTS RAM Read T able 6.18 64-Bit Address Operatin g Regist er/SCRIPT S RAM Read Symb ol P arame ter Min Max Unit t 1 Shared sig nal input setu p time 7 – ns t 2 Shared signal inp ut hold time 0 – ns t 3 CLK to shared signa l output val id – 11 ns CLK (Driv en b[...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-17 Figure 6.13 32-Bit O perating Register/SCRIPTS RAM Write T able 6.19 32-Bit Operating Regis ter/SCRIPTS RA M Write Symb ol P arameter Min Max Unit t 1 Shared sig nal input setu p time 7 – ns t 2 Shared signal inp ut hold time 0 – ns t 3 CLK to shared signa l output val id – 11 ns CLK [...]

6-18 Electrical Sp ecificat ions Figure 6.14 64-Bit Address Operating Register /SCRIPTS RAM Write T able 6.20 64-Bit Address Operatin g Reg ister/SCRI PTS RAM Wr ite Symb ol P arame ter Min Max Unit t 1 Shared sig nal input setu p time 7 – ns t 2 Shared signal inp ut hold time 0 – ns t 3 CLK to shared signa l output val id – 11 ns Bus Addr Lo[...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-19 6.4.2 Initiator Timing The tables an d figures in th is sect ion des cr ibe LSI53C 875A i nitiat or timing s. T able 6.21 Nonbur st Opcode Fetch, 32-Bit Address and Data Symb ol P arame ter Min Max Unit t 1 Shared sig nal input setu p time 7 – ns t 2 Shared signal inp ut hold time 0 – n[...]

6-20 Electrical Sp ecificat ions Figure 6.15 Nonbur st Opcode Fetch, 32-Bit Address and Data CLK (Driven by System) FRAME/ (Driven by LSI53C875A) AD (Driven by LSI53C875A- C_BE/ (Driven by LSI53C875A) PA R (Driven by LSI53C875A- IRD Y/ (Driven by LSI53C875A) TRD Y/ (Driv en by T arg et) ST OP/ (Driven by T arget ) DEVS EL/ (Driv en by T arg et) Add[...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-21 T able 6.22 Burst Opcode F etch, 32-Bi t Address and Data Symb ol P arame ter Min Max Un it t 1 Shar ed sign al in put set up ti me 7 – ns t 2 Shared signal inp ut hold time 0 – ns t 3 CLK to shared signa l output val id 2 11 ns t 4 Side signal inpu t setup time 10 – ns t 5 Side sign [...]

6-22 Electrical Sp ecificat ions Figure 6.16 Burst Opcode Fetch, 32-Bit Add ress and Data CLK (Driven by System) FRAME/ (Driven by LSI53C875A) AD (Driven by LSI53C875A- C_BE/ (Driven by LSI53C875A) PA R (Driven by LSI53C875A- IRD Y/ (Driven by LSI53C875A) TRD Y/ (Driv en by T arg et) ST OP/ (Driven by T arget ) DEVS EL/ (Driv en by T arg et) Addr/ [...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-23 T able 6.23 Back-to-Back Read, 32-Bit Address and Data Symbol P arameter Min Max Unit t 1 Shar ed si gnal i nput se tup t ime 7 – ns t 2 Shar ed s ignal i nput ho ld ti me 0 – ns t 3 CLK to shared signa l output va lid 2 11 ns t 4 Side signal inp ut setup time 10 – ns t 5 Side si gna [...]

6-24 Electrical Sp ecificat ions Figure 6.17 B ack-to-Back Read, 32-Bit Address and Data CLK (Dr iven by System) FRAM E/ (Dr iven by LSI53C8 75A) AD (Dr iven by LSI53C8 75A- C_BE/ (Dr iven by LSI53C8 75A) PA R (Dr iven by LSI53C8 75A- IRD Y/ (Dr iven by LSI53C8 75A) TRD Y/ (Driven by T arget ) ST OP/ (Driven by T arget ) DEVS EL/ (Driven by T arget[...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-25 T ab le 6.24 Back -to-B ac k Wri te, 32-Bi t Add re ss and Dat a Symb ol P arame ter Min Max Uni t t 1 Shar ed sign al in put set up ti me 7 – ns t 2 Shared signal inp ut hold time 0 – ns t 3 CLK to s har ed s ignal o utpu t valid 2 11 ns t 4 Side signal inpu t setup time 10 – ns t 5 [...]

6-26 Electrical Sp ecificat ions Fig ure 6. 18 Bac k-to- Bac k W rite, 32-Bi t Addr ess and Data CLK (Driven by System) FRAME/ (Driven by LSI53C875A) AD (Driven by LSI53C875A- C_BE/ (Driven by LSI53C875A) PA R (Driven by LSI53C875A- IRD Y/ (Driven by LSI53C875A) TRD Y/ (Driv en by T arg et) ST OP/ (Driven by T arget ) DEVS EL/ (Driv en by T arg et)[...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-27 T able 6.25 Burst Read, 32 -Bit Addres s and Da ta Symb ol P arameter Min Max Unit t 1 Shared sig nal input setu p time 7 – ns t 2 Shared signal inp ut hold time 0 – ns t 3 CLK to shared signa l output val id 2 11 ns[...]

6-28 Electrical Sp ecificat ions Figure 6.19 Burst Read, 32-Bit Address and Data t 1 t 2 CLK GPIO0_FETCH/ (Driven by LSI53C875A) GPIO1_MAS TER/ (Driven by LSI53C875A) REQ/ (Driven by LSI53C875A) PA R (Driven by LSI53C875A- IRD Y/ (Driven by LSI53C875A) TRD Y/ (Driven by T arget) ST OP/ (Driven by T arget) DEVSEL/ (Driven by T arget) AD (Driven by L[...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-29 T able 6.26 Burst Read, 64 -Bit Addres s and Da ta Symb ol P arame ter Min Max Uni t t 1 Shar ed sign al in put set up ti me 7 – ns t 2 Shared signal inp ut hold time 0 – ns t 3 CLK to s har ed s ignal o utpu t valid 2 11 ns t 10 CLK HIGH to GPIO1_MASTER/HIGH – 20 ns[...]

6-30 Electrical Sp ecificat ions Figure 6.20 Burst Read, 64-Bit Address and Data t 1 t 2 CLK GPIO0_FETCH/ (Driven by LSI53C875A) GPIO1_MAS TER/ (Driven by LSI53C875A) REQ/ (Driven by LSI53C875A) PA R (Addr dr vn by LSI53C875A; IRD Y/ (Driven by LSI53C875A) TRD Y / (Driven by T arget) ST OP/ (Driven by T arget) DEVSEL/ (Driven by T arget) AD[31:0] ([...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-31 T able 6.27 Burst Write, 32-Bit Address a nd Data Symb ol P arame ter Min Max Unit t 1 Shared sig nal input setu p time 7 – ns t 2 Shared signal inp ut hold time 0 – ns t 3 CLK to shared signa l output val id 2 11 ns t 10 CLK HIGH to GPIO1_MASTER/ HIGH – 20 ns[...]

6-32 Electrical Sp ecificat ions Figure 6.21 Burst Write, 32-Bit Ad dress and Data t 1 CLK (Dr iven by System) GPIO0_FETCH/ (Driven by LSI53C875A) GPIO1 _MASTER/ (Driven by LSI53C875A) REQ/ (Driven by LSI53C875A) PA R (Driven by LSI53C875A) IRD Y/ (Driven by LSI53C875A) TRD Y/ (Driven by T arget ) ST OP/ (Driven by T arget ) DEVS EL/ (Driven by T a[...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-33 T ab le 6.28 Burs t Writ e, 64-B it Addr ess and 32 -Bit D ata Symb ol P arame ter Min Max Uni t t 1 Shar ed sign al in put set up ti me 7 – ns t 2 Shared signal inp ut hold time 0 – ns t 3 CLK to s har ed s ignal o utpu t valid 2 11 ns t 10 CLK HIGH to GPIO1_MASTER/ HIGH – 20 ns[...]

6-34 Electrical Sp ecificat ions Figure 6.22 Burst Write, 64-Bit Ad dress and 32-Bit Data t 1 CLK (Dri ve n by Syst em) GPIO0_FET CH/ (Driven by LSI53C875A) GPIO1_M ASTER/ (Driven by LSI53C875A) REQ/ (Driven by LSI53C875A) PA R (Driven by LSI53C875A) IRD Y/ (Driven by LSI53C875A) TRD Y/ (Dri v en by T arget) STOP/ (Dri v en by T arget) DEVS EL/ (Dr[...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-35 6.4.3 External Mem ory Timing The tables an d figures in this sect ion des cr ibe LSI53C 875A exter na l timin gs. The Ext er nal Me mor y Wr it e timin gs st ar t o n page 6 -40 . T ab le 6.29 Ext ernal Mem ory Re ad Symbol P arameter Min Max Unit t 1 Shared sign al input setup time 7 – [...]

6-36 Electrical Sp ecificat ions Figure 6.23 External Me mory Read 12 3 4 5 6 7 8 9 CLK (Driven by System) PA R (Driven by Master-Addr ; IRD Y/ (Driven by Master) TRD Y/ (Driven by LSI53C875A) ST OP/ (Driven by LSI53C875A) DEVS EL/ (Driven by LSI53C875A) AD (Driven by Master-Addr ; C_B E[3 :0]/ (Driven by Master) FRAM E/ (Driven by Master) LSI53C87[...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-37 Figure 6.23 External Memory Read (Cont.) MAD (Addr dr iven by LSI53C875A; Data driven by Memory ) 11 12 13 14 15 16 17 18 19 20 21 10 CLK (Dr iven by System) PA R (Driven by Master-Addr ; IRD Y/ (Dri ve n by Mast er) TRD Y/ (Driven by LSI53C875A) ST OP/ (Driven by LSI53C875A) DEVS EL/ (Driv[...]

6-38 Electrical Sp ecificat ions T ab le 6.30 Ext erna l Mem ory Wri te Symb ol P arameter Min Max Unit t 1 Shared sig nal input setu p time 7 – ns t 2 Shared signal inp ut hold time 0 – ns t 3 CLK to shared signa l output val id – 11 ns t 11 Address s etup to MAS/ HIG H 25 – ns t 12 Address hold from MAS/ HIGH 15 – n s t 13 MAS/ pulse wi[...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-39 The Exter na l Memor y Wr ite timings star t on pa ge 6-40 .[...]

6-40 Electrical Sp ecificat ions Figure 6.24 External Memory Write 12 3 4 5 6 78 9 CLK (Driven by System) PA R (Driven by Master-Addr ; IRD Y/ (Driven by Master) TRD Y/ (Driven by LSI53C875A) ST OP/ (Driven by LSI53C875A) DEVS EL/ (Driven by LSI53C875A) AD (Driven by Master-Addr ; C_B E[3 :0]/ (Driven by Master) FRAM E/ (Driven by Master) LSI53C875[...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-41 Figure 6.24 External Me mory Write (Cont.) MAD (Addr dr iven by LSI53C875A; Data driven by Memory ) 11 12 13 14 15 16 17 18 19 20 21 10 CLK (Dr iven by System) PA R (Driven by Master-Addr ; IRD Y/ (Dri ve n by Mast er) TRD Y/ (Driven by LSI53C875A) ST OP/ (Driven by LSI53C875A) DEVS EL/ (Dr[...]

6-42 Electrical Sp ecificat ions Figure 6.25 Normal/Fast Memory ( ≥ = 128 Kbytes) S ingle By te Access Read Cycle T able 6.31 Normal/Fast Memory ( ≥ = 1 28 Kbytes) Sing le Byte Acc ess Read C ycle Symb ol P arameter Min Max Unit t 11 Address s etup to MAS/ HIG H 25 – ns t 12 Address hold from MAS/ HIGH 15 – n s t 13 MAS/ pulse width 25 – [...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-43 Figure 6.26 Normal/Fast Memory ( ≥ = 128 K bytes) Single By te Access Writ e Cycle T able 6.32 Normal/Fast Memory ( ≥ = 1 28 Kbytes) Sing le Byte A ccess Wr ite Cycle Symb ol P arame ter Min Max Unit t 11 Address s etup to MAS/ HIG H 25 – ns t 12 Address hold from MAS/ HIGH 15 – ns [...]

6-44 Electrical Sp ecificat ions Figure 6.27 Normal/Fast Memory ( ≥ = 128 Kbytes) M ultiple Byte Access R ead Cycle MAD (Addr Dr iven by LS I53C87 5A; MAS1/ (Driven by LSI53C875A) MAS0/ (Driven by LSI53C875A) MCE/ (Driven by LSI53C875A) MOE/ (Driven by LSI53C875A) MWE/ (Driven by LSI53C875A) 02 4 6 8 1 01 2 1 4 1 6 1 7 Data dr iv en by Memor y) C[...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-45 Figure 6.27 Normal/Fast Memory ( ≥ = 128 Kbytes) M ultiple Byte Access R ead Cycle (Cont.) MAD (Addr Dr iven by LS I53C87 5A ; MAS1/ (Driven by LSI53C875A) MAS0/ (Driven by LSI53C875A) MCE/ (Driven by LSI53C875A) MOE/ (Driven by LSI53C875A) MWE/ (Driven by LSI53C875A) 15 18 20 22 24 26 2 [...]

6-46 Electrical Sp ecificat ions Figure 6.28 Normal/Fast Memory ( ≥ = 128 Kbytes) M ultiple Byte Access W rite Cycle MAD (Driven by LSI53C875A) MAS1/ (Driven by LSI53C875A) MAS0/ (Driven by LSI53C875A) MCE/ (Driven by LSI53C875A) MOE/ (Driven by LSI53C875A) MWE/ (Driven by LSI53C875A) 02 4 6 8 1 0 1 2 1 4 CLK (Driven by System) PA R (Driven by Ma[...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-47 Figure 6.28 Normal/Fast Memory ( ≥ = 128 Kbytes) M ultiple Byte Access W rite Cycle (Cont.) MAD (Driven by LSI53C875A; MAS1/ (Driven by LSI53C875A) MAS0/ (Driven by LSI53C875A) MCE/ (Driven by LSI53C875A) MOE/ (Driven by LSI53C875A) MWE/ (Driven by LSI53C875A) 15 18 20 22 24 26 28 30 CLK [...]

6-48 Electrical Sp ecificat ions Figure 6.29 Slow Me mory ( ≤ = 128 Kbytes) Read Cycle T able 6.33 Slow Me mory ( ≤ = 128 Kbytes) Read C ycle Symb ol P arame ter Min Max Un it t 11 Address s etup to MAS/ HIG H 25 – ns t 12 Address hold from MAS/ HIGH 15 – ns t 13 MAS/ pulse width 25 – ns t 14 MCE/ LO W to data cloc ked in 150 – ns t 15 [...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-49 Figure 6.30 Slow Me mory ( ≤ = 128 Kb ytes ) Write C ycle T able 6.34 Slow Me mory ( ≤ 128 Kb ytes) Wri te Cyc le Symb ol P arame ter Min Max Un it t 11 Address s etup to MAS/ HIG H 25 – ns t 12 Address hold from MAS/ HIGH 15 – ns t 13 MAS/ pulse width 25 – ns t 20 Data setup t o [...]

6-50 Electrical Sp ecificat ions Figure 6.31 ≤ 64 Kbytes ROM Read Cycle Ta b l e 6 . 3 5 ≤ = 64 Kbytes ROM Read Cycle Symb ol P arameter Min M a x Unit t 11 Address s etup to MAS/ HIG H 25 – ns t 12 Address hold from MAS/ HIGH 15 – ns t 13 MAS/ pulse width 25 – ns t 14 MCE/ LO W to data cloc ked in 150 – ns t 15 Address v alid to data c[...]

PCI and Ex ternal Memory Interf ace Timing D iagr ams 6-51 Figure 6.32 ≤ 64 Kbyte ROM Write Cy cle Ta b l e 6 . 3 6 ≤ = 64 Kbyte ROM Write Cycle Symb ol P arameter Min Max Unit t 11 Address s etup to MAS/ HIG H 25 – ns t 12 Address hold from MAS/ HIGH 15 – n s t 13 MAS/ pulse width 25 – ns t 20 Data setup t o MWE/ LO W 30 – ns t 21 Data[...]

6-52 Electrical Sp ecificat ions 6.5 S CSI Tim ing D iagrams The tables and diagrams in this secti on descr ibe the LSI53C 875A SCS I timing s. Figure 6.33 Initiator Asynchronous Send T able 6.37 Initiator Asynchr onous Send Symb ol P arameter Min Max Unit t 1 SA CK/ ass er ted from SREQ / asser ted 5 – ns t 2 SA CK/ deas serted from SREQ/ deass [...]

SCSI Timing Diagr ams 6-53 Figure 6.34 Initiator As ynchr onous Receive T able 6.38 Initiator Asynchronous Receive Symb ol P arame ter Min Max Un it t 1 SA CK/ ass er ted from SREQ / asser ted 5 – ns t 2 SA CK/ deas serted from SREQ/ deass er ted 5 – ns t 3 Data setup t o SREQ/ asserted 0 – ns t 4 Data hold from SAC K/ asser ted 0 – ns SREQ[...]

6-54 Electrical Sp ecificat ions Figure 6.35 T arget Asynchr onous Send T able 6.39 T arget Async hronous Send Symb ol P arameter Min Max Unit t 1 SREQ/ deass er ted from SA CK/ asser ted 5 – ns t 2 SREQ/ asse r ted from SA CK/ deasserted 5 – ns t 3 Data se tup to SREQ/ asserted 55 – ns t 4 Data hold from SAC K/ asser ted 0 – ns SREQ/ SA CK[...]

SCSI Timing Diagr ams 6-55 Figure 6.36 T arget Asynchronous Receive T able 6.40 T arget Asynchr onous Receive Symb ol P arame ter Min Max Un it t 1 SREQ/ deass er ted from SA CK/ asser ted 5 – ns t 2 SREQ/ asserted from SA CK/ deasserted 5 – ns t 3 Dat a setup to S ACK/ asser ted 0 – ns t 4 Data hold from SREQ/ deas ser ted 0 – ns T able 6.[...]

6-56 Electrical Sp ecificat ions T able 6.42 SCSI-2 Fast T ran sfers 10.0 Mbytes (8-Bi t T ransfers) or 20.0 Mbytes (16-Bit T ransfers) 40 MHz Cloc k Symb ol P arameter Min M a x Unit t 1 Send SREQ/ or SACK/ assertion pulse width 30 – ns t 2 Send SREQ/ or SA CK/ deassertion pulse width 30 – ns t 1 Receive SREQ/ or SA CK/ a sser tion puls e widt[...]

SCSI Timing Diagr ams 6-57 Figure 6.37 Initiator a nd T arget S ynchr onous T r ansfer SREQ/ or SACK/ Send Data SD[15:0]/, SDP[1:0]/ Receive Data SD[15:0]/, SDP[1:0]/ t 3 t 4 t 1 t 2 t 5 t 6 nn + 1 V alid n V alid n + 1 V alid n V alid n + 1[...]

6-58 Electrical Sp ecificat ions 6.6 Pac kage Diag rams This sec tion o f the manual has a packag e drawing and pino ut for both the PQFP and BGA . Figure 6 .38 LSI5 3C875A 160-Pin PQFP Mechanical Dra wing Important: This drawing may not be the latest version. For b oard lay out and m anufacturing, obtain the most recent engineering d rawings from [...]

P ackage D iagra ms 6-59 Figure 6.38 160 -pin PQFP (P 3) Mechanical Dr awing (Sheet 2 of 2) Important: This drawing may not be the latest version. For b oard lay out and m anufacturing, obtain the most recent engineering d rawings from yo u r LSI Logic marketi ng representative by requesting the outline drawing for package code P3.[...]

6-60 Electrical Sp ecificat ions T able 6.44 160 PQFP Pin Lis t by Location NC 121 NC 122 VSSIO 123 NC 124 NC 125 TES T_H SC / 126 TES T_R ST/ 1 27 VDDIO 128 VDD A 129 TCK 130 TRST/ 131 VSSA 132 VSSIO 133 NC 134 NC 135 MASN[1]/ 136 MASN[0]/ 137 VDDIO 138 MEW/ 13 9 MOE/ 14 0 MCE/ 14 1 TDI 142 SERR/ 143 RST/ 144 CLK 145 VSSCORE 146 GNT/ 14 7 REQ/ 148[...]

P ackage D iagra ms 6-61 Figure 6.39 169-Pin BGA Mechanical Dra wing Important: This drawing may not be the latest version. For b oard lay out and m anufacturing, obtain the most recent engineering d rawings from yo u r LSI Logic marketi ng representative by requesting the outline drawing for package code GV .[...]

6-62 Electrical Sp ecificat ions T able 6.45 169 BGA Pin List by Location VSSIO K12 SIO K13 PCI_AD[9] L1 PCI_AD[8] L2 PCI_AD[4] L3 PCI_AD[2] L4 VDDCORE L5 VSSCORE L6 MAD[ 7] L7 MAD[ 1] L8 GPIO[4] L9 MA C_TEST OUT/ L10 VDDIO L11 VDDCORE L12 SD[10] L13 PCI_AD[7] M1 NC M2 PCI_AD[5] M3 NC M4 IRQ/ M5 SCLK M6 MAD[ 6] M7 MAD[ 3] M8 GPIO[3] M9 VDDIO M10 NC[...]

LSI53C8 75A PCI to Ultra SCSI Controller A-1 Appendix A Regist er Summ ar y T able A.1 LSI5 3C875A PCI Re gister Map Register Nam e Address Read/Write P age Base Addres s Register O ne (MEMOR Y) 0x1 4–0x17 Read/Write 4- 9 Base Address Register T wo (SCRIPTS RAM) 0x18–0 x1B Read/Write 4-10 Base Addres s Register Zero (I/O ) 0x1 0–0x13 Read/Wri[...]

A-2 Register Summary P ow er Manage ment Capabi lities (PMC) 0x4 2–0x43 Read Only 4-15 P ow er Manage ment Control/Stat us (PMCSR) 0x44–0 x45 Read/Write 4-16 Reser ved 0x28– 0x2B – 4- 10 Reser ved 0x35– 0x3B – 4- 13 Revision I D (Rev ID) 0x08 Rea d Onl y 4-6 Status 0x06–0 x07 Read/Write 4- 5 Subsyste m ID 0x2E–0x 2F Read Only 4-11 S[...]

Register Su mmar y A-3 DMA C ommand ( DCM D) 0x 27 Rea d/Wr ite 4 -63 DMA Control (DCNTL) 0x3B Read/Write 4-70 DMA FIFO (DFIFO) 0x20 Read/Write 4-57 DMA Interrupt Enab le (DIEN) 0x39 Read/Write 4-69 DMA Mode (D MODE) 0x38 Read/Write 4-66 DMA Ne xt Address (DNAD) 0x28–0 x2B Read/Write 4-64 DMA Ne xt Address 64 (DNAD64) 0xB8–0xBB Read/Write 4-103[...]

A-4 Register Summary Remainin g Byte Count (RBC) 0xC8–0x CB Read/Write 4-105 Reser ved 0x53 – 4-94 Reser ved 0x5A –0x5 B – 4-99 Reser ved 0xBC –0x BF – 4-103 Reser ved 0xDB – 4-108 Reser ved 0xE0–0x FF – 4-108 Response ID One (RESPID1) 0x4B Read/Write 4-86 Response ID Zero (RESPID0) 0x4A Read/Write 4-86 Scra tch Byte Registe r (SB[...]

Register Su mmar y A-5 SCSI I nte rr upt En able Zer o (SI EN0) 0x 40 Rea d/Wr it e 4 -73 SCSI Interrupt Stat us One (SIST1) 0x43 Read Only 4-78 SCSI Interrupt Stat us Zero (SIST0) 0x42 Read Only 4-76 SCSI Longi tudinal P arity (SLP AR) 0x44 Read/Write 4-79 SCSI Output Con trol Latch (SOCL) 0x09 Read/Write 4-37 SCSI Output D ata Latch (SODL) 0x5 4?[...]

A-6 Register Summary[...]

LSI53C8 75A PCI to Ultra SCSI Controller B-1 Appendix B External Memory Interface D iagram Examples Appen dix B has example e x ter nal mem or y interface diagrams. Figure B.1 16 Kb yte Interface wi th 200 ns Memory LSI53C875A 27C128 MOE/ OE MCE/ CE D0 8 MAD[7:0] Bus CK Q0 8 A[7:0] QE 6 A[13:8] V DD MAS0/ MAS1/ Note: MAD[3:1] pulled LOW internally [...]

B-2 External Memor y Interf ace Diagram Exam ples Figure B.2 64 Kb yte Interface wi th 150 ns Memory LSI53C875A 27C512-15/ MOE/ OE MCE/ CE D0 8 MAD[7:0] Bus CK Q0 8 A[7:0] QE 6 A[15:8] V DD MAS0/ MAS1/ Note: MAD 3, 1, 0 pulled LOW internally . MAD bus sense logic enabled f or 64 Kbyte of fast memory (150 ns devices @ 33 MHz). HCT374 GPIO4 MWE/ VPP [...]

External Memory Interfa c e Diagr am Example s B-3 Figure B.3 128 Kbytes, 256 Kb y tes, 512 Kbytes, or 1 Mb yt e Interface wit h 150 ns Memor y LSI53C875A 27C020-15/ MOE/ OE MCE/ CE 8 MAD[7:0] Bus 8 A[7:0] 6 A[15:8] V DD MAS0/ MAS1/ Note: MAD[2:0] pulled LOW internally . MAD bus sense logic enabled f or 128, 256 , 512 Kbytes, or 1 Mb yte of fast me[...]

B-4 External Memor y Interf ace Diagram Exam ples Figure B.4 512 Kb yte Interface wit h 150 ns Memory OE WE D[7:0] A0 A16 . . . LSI53C875A MOE/ 8 MAD[7:0] Bus A[7:0] D0 CK Q0 QE 8 A[15:8] V DD MAS0/ MAS1/ Note: MAD2 pulled LOW internally . MAD bus sense logic enabled f or 512 Kbytes of slow memory (150 ns devices, additional time required for HCT13[...]

LSI53C8 75A PCI to Ultra SCSI Controller IX-1 Inde x Sym bol s (64TIMO D) 4-97 (A7) 5-23 (AAP) 4-2 2 (ABRT) 4-40 , 4-48 (ACK) 4-37 , 4- 39 (ADB) 4-23 (ADCK) 4-60 (ADDER) 4-73 (AESP) 4-24 (AIP) 4-43 (APS) 4-1 6 (ARB[1:0]) 4-2 0 (ART) 4- 87 (ATN) 4- 37 , 4- 39 (AWS) 4-90 (BAR0) 4-9 (BAR1) 4-9 (BAR2) 4-10 (BBCK) 4-6 1 (BDIS) 4-5 9 (BF) 4- 40 , 4-69 (B[...]

IX-2 Inde x (ERBA) 4-1 2 (ERL) 4-67 (ERMP) 4- 68 (ESA) 4-1 06 (EWS) 4-29 (EXC) 4-2 3 (EXT) 4-90 (FBL3) 4- 59 (FE) 4- 82 (FF[3:0] ) 4-43 (FF4) 4-46 (FFL) 4-53 (FLF) 4-56 (FLSH) 4-51 (FM) 4-56 (FMT) 4-53 (GEN) 4-75 , 4-79 (GEN[3:0 ]) 4-85 (GENSF) 4- 85 (GPCNTL0) 4-8 2 (GPIO) 4-35 (GPIO[1: 0]) 4-83 (GPIO[4: 2]) 4-83 (GPREG0) 4-35 (HSC) 4-9 1 (HT) 4-8 [...]

Inde x IX-3 (SGE) 4-7 4 , 4-77 (SI) 4-51 (SID) 4-11 (SIEN0) 4- 73 (SIEN1) 4- 75 (SIGP) 4- 49 , 4-54 (SIOM) 4-67 (SIP) 4-50 (SIR) 4-40 (SIST0) 4-76 (SIST1) 4-78 (SLB) 4-8 9 (SLPAR) 4-79 (SLPHBEN) 4-27 (SLPM D) 4-27 (SLT) 4-87 (SOCL) 4-37 (SODL) 4-94 (SOM) 4-88 (SOZ) 4-87 (SPL1) 4-47 (SRE) 4-30 (SRST) 4- 48 (SRTM) 4-5 9 (SRUN) 4-51 (SSAID) 4-87 (SSE)[...]

IX-4 Inde x burst (C ont.) length ( BL[1:0]) 4-66 length b it 2 (BL2) 4-61 opcode fet ch enab le (BO F) 4-6 8 size selection 2-6 bus command and byte en ables 3- 5 fault (BF ) 4-40 , 4-69 byte count 5-37 empty in DMA FIFO (F MT) 4-53 full in DMA F IFO (FFL) 4-53 offset co unter (BO) 4-57 C cache line size 2-7 , 2-9 (CLS) 4-7 enable (CLS E) 4-70 reg[...]

Inde x IX-5 DMA interrupt ( Cont.) pendin g (DIP ) 4-50 mode ( DMODE ) 4-66 SCRIPTS pointer ( DSP) 4-64 pointer save (DSPS) 4- 65 status ( DSTAT) 4- 39 DMA next address (DNAD) 4-64 addres s 64 (DNAD 64) 4-103 DMODE 2-6 registe r 2-22 DSA relative 5-3 6 relative select or (DRS) 4-102 DSPS register 5-34 DSTAT 2-38 , 2-42 , 2-43 dual addre ss cycles c[...]

IX-6 Inde x IDSEL 2-3 , 3-6 signal 2- 5 illegal instruction detec ted (IID) 4-40 , 4-6 9 immedia te arbitra tion (IARB) 4-2 4 data 5-23 indirect add ressi ng 5-6 initialization de vice select 3-6 initiator mode 5-16 phase mis match 4-7 6 ready 3-6 input 3- 3 capacitance 6-2 instruction addres s (IA) 4- 107 block mo ve 5-6 prefetch u nit flu shing 2[...]

Inde x IX-7 memory ( Cont .) read lin e comm and 2- 6 read multiple 2-10 , 2-11 read multiple command 2-6 space 2-2 , 2-3 to memo ry 2- 16 to memo ry moves 2-1 6 write 2-10 , 2-11 write and invalidate 2- 10 write and invalidate co mmand 2-8 write caching 2-11 write command 2-5 write enable 3-11 Min_Gn t (MG) 4-1 4 MOE/ 3-11 move to/fr om SFBR cycle[...]

IX-8 Inde x reset 3-4 input 6- 10 SCSI offset (ROF) 4-89 response ID one (RESPID1) 4-86 response ID zero (RESPID0) 4-86 return inst ruction 5-27 revision ID (RID) 4-6 ROM flash and memory interface signals 3-11 pin 2-49 RST/ 3-4 S SACK 2-42 SACK/ status (ACK) 4-39 SACs 2-19 SATN/ status (ATN) 4-39 SBSY/ status (BSY) 4- 39 SC_D/ status (C_D) 4- 39 S[...]

Inde x IX-9 SEL 2-39 select 2-17 instruction 5-16 with ATN/ 5-20 with SAT N/ on a sta rt sequ ence (W ATN) 4- 22 selected (SEL) 4-7 4 , 4-77 selection or reselectio n time-o ut (STO ) 4-75 , 4-79 selection response lo gic test (S LT) 4-87 selection time-out (SEL[3:0 ]) 4-84 sema phore (SEM) 4- 49 serial EEP ROM interface 2-50 SERR/ 3-7 SERR/ enable[...]

IX-10 Inde x Ultra SCSI (Cont.) single-e nded tr ansfers 20.0 Mbyte s (16-b it transf ers) quadrupl ed 40 M Hz clock 6-56 20.0 Mb ytes (8-b it trans fers ) 40 MHz clo ck 6-56 synchro nous da ta tran sfers 2- 36 unexpected disconn ect (UDC) 4-74 , 4-78 updated a ddress (UA) 4-105 upper re gister ad dress line (A7) 5- 23 use data8/ SFBR 5- 22 V VDD 3[...]

Customer Fee dbac k W e would appreci ate your f e edback on this document. P lease copy the f o llowing pa ge, add your comm ents, and fax it to us at the number shown. If approp riat e, please als o fax copies of any m arked-up pa ges from this document . Impor tant: Pleas e include your name, phone number, f a x number , and compa ny address so [...]

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Sales Off ices and Design Resource Center s (Co ntinu e d) Ko re a Seoul LSI Logic C orporat ion of Ko re a L t d 10th Fl., Haesung 1 B ldg. 942, Daechi- dong, Kangnam-k u, Seoul, 135-283 T el: 82.2.52 8.3400 F ax: 82.2.528.2 250 The Ne t her lands Eindhoven LSI Logic Eur ope Ltd Wo rld T rade Center Eindho ven Building ‘Rijder’ Bogert 26 5612 [...]

International Distr ibut ors Au st r a l i a New South W a les Rept echni c Pty Ltd 3/36 Bydo wn Street Neutr al Bay , NSW 2089 ♦ T el: 612.99 53.984 4 F a x: 612.995 3.968 3 Belgium Acal nv/sa Lozenber g 4 1932 Za ventem T el: 32.2. 720598 3 F a x: 32.2.72 51014 China Beijing LSI Logi c Inte rnational Service s Inc. Beijing Represe ntative Offic[...]