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M-Systems Flash Disk Pioneers Flash Memory manual

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Table of contents for the manual

  • Page 1

    White Paper Implementing MLC NAND Flash for Cost-Effective, High-Capacity Memory Written by: Raz Dan and Rochelle Singer JANUARY 2003 91-SR-014-02-8L, REV 1. 0[...]

  • Page 2

    Implementing MLC NAND Flash for Cost -Effective, High-Capacity Memory 91-SR-014-0 2-8L 2 Introduction Multi-Level Cell (MLC) technology greatly reduces flash die size to achieve a breakthrough cost structure. It does this by st oring 2 bits of data per physical cell in stead of the traditi onal 1 bit per cell, using Binary flash technology. But the[...]

  • Page 3

    Implementing MLC NAND Flash for Cost -Effective, High-Capacity Memory 91-SR-014-0 2-8L 3 of NOR flash and achieving barely adequate reliability, but it has serious limita tions: its performance is far slower than standard NOR flash. NAND flash appeared to be the ideal media for data sto rage, due to its high-speed erase and write, high density (thu[...]

  • Page 4

    Implementing MLC NAND Flash for Cost -Effective, High-Capacity Memory 91-SR-014-0 2-8L 4 e - Oxide Floating Gate Select Gate Source Dr ain Substrate Progr am (Inject electrons) Erase (Remov e electrons) Figure 1: A Basic Flash Cell Binary and MLC Technologies In flash devices that implement Binary flas h technology, there are two possible ranges fo[...]

  • Page 5

    Implementing MLC NAND Flash for Cost -Effective, High-Capacity Memory 91-SR-014-0 2-8L 5 MLC Benefits and Limitations MLC high-density design innovations reduce the s ilicon die size, which is the major element contributing to overall device cost. For MLC NAND, th is reduction in size and cost is greatest in capacities of 256Mbit (32MByte ) and hig[...]

  • Page 6

    Implementing MLC NAND Flash for Cost -Effective, High-Capacity Memory 91-SR-014-0 2-8L 6 Read Disturb Errors The read disturb effect causes a page read operati on to induce a permanent, bit value change in one of the read bits. In Binary flash technology based on a 0.16 µ manufacturing process, the typical read disturb error rate is on the order o[...]

  • Page 7

    Implementing MLC NAND Flash for Cost -Effective, High-Capacity Memory 91-SR-014-0 2-8L 7 Sustained Read When comparing sustained read performance values in real-world scenarios for Binary Flash with MLC, the gap lessens considerably : MLC performance is 98 percent of Binary flash performance. Operations that both Binary flas h and MLC require to su[...]

  • Page 8

    Implementing MLC NAND Flash for Cost -Effective, High-Capacity Memory 91-SR-014-0 2-8L 8 Overcoming MLC Limitations Because MLC technology can potentially bring the industry breakth rough cost and size benefits for local data and code storage, M-Systems chose to take on the challenge of perfecting it by providing solutions to overcome MLC reliabili[...]

  • Page 9

    Implementing MLC NAND Flash for Cost -Effective, High-Capacity Memory 91-SR-014-0 2-8L 9 Table 1 maps the various features of x2 technology agai nst the three major ar eas of MLC limitations that they overcome. The rem ainder of this se ction explains how each feature ach ieves these enhancements in Mobile DiskOnChip G3. Table 1: Overcoming MLC Lim[...]

  • Page 10

    Implementing MLC NAND Flash for Cost -Effective, High-Capacity Memory 91-SR-014-0 2-8L 10 Enhanced EDC and ECC The Error Detection Code (EDC) and Error Corr ection Code (ECC) devel oped for x2 technology is based on M-Systems’ highly effective combinati on used in previous generation DiskOnChip products. This system contains hardware-embedded EDC[...]

  • Page 11

    Implementing MLC NAND Flash for Cost -Effective, High-Capacity Memory 91-SR-014-0 2-8L 11 Efficient Bad Block Handling x2 technology handles bad blocks, which can be randomly present in flash m edia, by enabling unaligned block access to two planes. Bad blocks are mapped individually on each plane, as shown in Figure 4. Good units can therefore be [...]

  • Page 12

    Implementing MLC NAND Flash for Cost -Effective, High-Capacity Memory 91-SR-014-0 2-8L 12 MultiBurst To improve MLC read performance rates, x2 te chnology incorporates a f eature called MultiBurst. MultiBurst enables parallel read acces s from two 16-bit planes to the flash contro ller, thereby achieving the desired output data rate for the host. T[...]

  • Page 13

    Implementing MLC NAND Flash for Cost -Effective, High-Capacity Memory 91-SR-014-0 2-8L 13 Parallel Multiplane Access As discussed earlier, the MLC flash media is built of two planes that can operate in parallel. This architecture is one of the most powerful, x2 technology innovations, doubli ng read, write and erase performance. Two pages on differ[...]

  • Page 14

    Implementing MLC NAND Flash for Cost -Effective, High-Capacity Memory 91-SR-014-0 2-8L 14 How to Contact Us Website: http://www.m-sys.com General Information: info@m-sys.com Technical Information: techsupport@m-sys.com USA M-Systems Inc. 8371 Central Ave, Suite A Newark CA 94560 Phone: +1-510-494-2090 Fax: +1-510-494-5545 Taiwan M-Systems Asia Ltd.[...]