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NXP Semiconductors UM10310 manual

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Table of contents for the manual

  • Page 1

    UM10310 P89LPC9321 User manual Rev . 01 — 1 December 2008 User manual Documen t informat ion Info Content Keywords P89LPC9321 Abstract T echnical information for the P89LPC9321 device[...]

  • Page 2

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 2 of 139 Cont act information For more in formation, ple ase visit: http://www .n xp.com For sales of fice addresses, please send an email to : salesaddresses@nxp.com NXP Semiconductors UM10310 P89LPC9321 User manual Revision hi story Rev Date Description 01 2[...]

  • Page 3

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 3 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 1. Introduction The P89LPC9321 is a single- chip microcontroller designed for appli cations demanding high-integration, low cost so lutions over a wid e range of p erformance require ments. The P89LPC9[...]

  • Page 4

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 4 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual Fig 2. PL CC2 8 pin configurati on Fig 3. DIP28 pin co nfiguration P89LPC9321F A 002aae105 5 6 7 8 9 10 11 25 24 23 22 21 20 19 12 13 14 15 16 17 18 4 3 2 1 28 27 26 P1.6/OCB P1.5/RST V SS P3.1/XTAL1 P[...]

  • Page 5

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 5 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 1.2 Pin description T able 1. Pin description Symbol Pin Ty p e Description P0.0 to P0.7 I/O Port 0: Port 0 is an 8-bit I/O port w ith a user-configurable output type. During reset Port 0 latches are c[...]

  • Page 6

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 6 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual P1.0/TXD 18 I/O P1.0 — Port 1 bit 0. O TXD — T ransmitter output for serial port. P1.1/RXD 17 I/O P1.1 — Port 1 bit 1. I RXD — Receiver input for serial port. P1.2/T0/SCL 12 I/O P1.2 — Port 1[...]

  • Page 7

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 7 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual [1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5. P2.5/SPICLK 16 I/O P2.5 — Port 2 bit 5. I/O SPICLK — SPI clock. When configured as ma ster , this pin is output; when configured as sl[...]

  • Page 8

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 8 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 1.3 Functional diagram Fig 4. Functional diagram V DD V SS PORT 0 PORT 3 TXD RXD T0 INT0 INT1 RST SCL SD A 002aae103 CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF CMP1 T1 XT AL2 XT AL1 KBI0 KBI1 KBI2 KBI3 KBI4 K[...]

  • Page 9

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 9 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 1.4 Block diagram Fig 5. Blo ck diagram ACCELERA TED 2-CLOCK 80C51 CPU 8 kB CODE FLASH 256-BYTE D A T A RAM PORT 2 CONFIGURABLE I/Os PORT 1 CONFIGURABLE I/Os PORT 0 CONFIGURABLE I/Os KEYP AD INTERR UPT[...]

  • Page 10

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 10 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 1.5 Special function registers Remark: SFR accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defin ed. • Accesses to any define d SFR locations[...]

  • Page 11

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    xxxxxxxxxxxxxx xxxxxxx xxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxx x x x x xxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxxx xxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxx xxxxxxxxxxxxx xxx xxxxxxxxxxxxxxxx x xxxxx xxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxx xxxxxxx xxxxxxxxx xxxxxxxxxxxxxxxxxx xxx xxxxx xxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx[...]

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    xxxxxxxxxxxxxx xxxxxxx xxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxx x x x x xxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxxx xxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxx xxxxxxxxxxxxx xxx xxxxxxxxxxxxxxxx x xxxxx xxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxx xxxxxxx xxxxxxxxx xxxxxxxxxxxxxxxxxx xxx xxxxx xxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx[...]

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    xxxxxxxxxxxxxx xxxxxxx xxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxx x x x x xxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxxx xxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxx xxxxxxxxxxxxx xxx xxxxxxxxxxxxxxxx x xxxxx xxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxx xxxxxxx xxxxxxxxx xxxxxxxxxxxxxxxxxx xxx xxxxx xxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx[...]

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    xxxxxxxxxxxxxx xxxxxxx xxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxx x x x x xxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxxx xxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxx xxxxxxxxxxxxx xxx xxxxxxxxxxxxxxxx x xxxxx xxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxx xxxxxxx xxxxxxxxx xxxxxxxxxxxxxxxxxx xxx xxxxx xxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx[...]

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    xxxxxxxxxxxxxx xxxxxxx xxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxx x x x x xxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxxx xxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxx xxxxxxxxxxxxx xxx xxxxxxxxxxxxxxxx x xxxxx xxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxx xxxxxxx xxxxxxxxx xxxxxxxxxxxxxxxxxx xxx xxxxx xxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx[...]

  • Page 20

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 20 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 1.6 Memory organization The various P89LPC9321 memory sp aces are as follows: DA T A — 128 bytes of internal data memo ry space (00h:7Fh ) accesse d via direct or indirect addressing, using instru c[...]

  • Page 21

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 21 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 2. Clocks 2.1 Enhanced CPU The P89LPC9321 uses an enha nced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle co nsists of two CPU clock cycles, and most instructi[...]

  • Page 22

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 22 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 2.3.2 Medium speed oscillator option This option support s an external cryst al in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configur ation. 2.3.3 High speed oscilla[...]

  • Page 23

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 23 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 2.6 W atchdog oscillator option The watchdog has a separate oscillator which has a frequency of 400 kHz, c alibrated to ± 5 % at room temperature. This oscillator can be used to sa ve power when a hi[...]

  • Page 24

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 24 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 2.8 Clock sources switch on the fly P89LPC9321 can implement clock source switch in any sources of watchdog oscillator , 7/14MHz IRC oscillator , external crystal oscilla tor and external clock input [...]

  • Page 25

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 25 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 2.9 Oscillator Clock (O SCCLK) wake-up delay The P89LPC9321 has an internal wake-up timer that dela ys the clock until it stabilizes depending on the clock source used. If the clock source is any of t[...]

  • Page 26

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 26 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual Each interrupt source can be individually enable d or disabled by setting or clearing a bit in the interrupt enable reg isters IEN0 or IEN1. The IEN0 register also cont ains a global enable bit, EA, w[...]

  • Page 27

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 27 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual If the external interrupt is level-tr iggered, the external source must hold the re quest active until the requested interrupt is generated. If the external inte rrupt is still asserted when the inter[...]

  • Page 28

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 28 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 4. I/O ports The P89LPC9321 has four I/O po rt s: Port 0, Po rt 1, Port 2, and Port 3. Ports 0, 1,and 2 are 8-bit ports, and Por t 3 is a 2-bit port. Th e exact number of I/O pins available de pen ds [...]

  • Page 29

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 29 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 4.1 Port configurations All but three I/O port pins on the P89LPC932 1 may be configured by sof tware to one of four types on a pin-by -pin basis, as shown in T able 13 . These are: quasi-bidirectiona[...]

  • Page 30

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 30 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual (Please refer to the P89LPC9321 dat a sheet, Dynamic characteristics for glitch filter specifications). 4.3 Open drain output configuration The open drain output configurat ion turns off all pull-up s[...]

  • Page 31

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 31 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 4.4 Input-only configuration The input port configuration is shown in Figure 12 . It is a Schmitt-trig gered input that also has a glitch suppression circuit. (Please refer to the P89LPC9321 dat a she[...]

  • Page 32

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 32 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual Digital output s are disabled by putting the port pins into the input-only mode as described in the Port Configurations section (see Figure 12 ). Digital in puts on Port 0 may be disabled through the [...]

  • Page 33

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 33 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 5. Power monitoring functions The P89LPC9321 incorpor ates power monitori ng function s designed to prevent incorre ct operation during initial power -o n and power loss or reduction during op eration[...]

  • Page 34

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 34 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual For correct activation of Brownout Detect, cert ain V DD rise and fall times must be observed. Please see the data sheet for specifications. 5.2 Power-on detection The Power-On Detect has a fu nction [...]

  • Page 35

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 35 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual T able 17. Po wer reduction modes PMOD1 (PCON.1) PMOD0 (PCON.0) Description 0 0 Normal mode (default) - no power reduction. 0 1 Idle mode. The Idle mode lea ves peripherals r unning in o rder to allow[...]

  • Page 36

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 36 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual T able 18 . Power Control register (PC ON - addres s 87h ) bit allocation Bit 76543210 Symbol SMOD1 SMOD0 - BOI GF1 GF0 PMOD1 PMOD0 R e s e t 00- 00000 T able 19 . Power Control register (PC ON - addr[...]

  • Page 37

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 37 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 6. Reset The P1.5/RST pin can function as either an active low reset input or as a digital input, P1.5. The RPE (Reset Pin Enable ) bit in UCFG1, when set to 1, enables the external reset input functi[...]

  • Page 38

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 38 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual [1] The value shown is for a power- on reset. Other reset sources will set their corresponding bits. 6.1 Reset vector Following reset, the P89LPC9321 will fetch instructions from ei ther address 0000h[...]

  • Page 39

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 39 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual break reset occ ur s or the no n- vo lat ile Boot S tatus bit (BOO TS T A T .0) = 1, or the device has been forced into ISP mode. Otherwise, instruct ions will be fetched from address 0000H. 7. Timers[...]

  • Page 40

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 40 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 7.1 Mode 0 Putting either T imer into Mode 0 makes it look like an 8048 T imer , which is an 8-bit Counter with a divide-by-32 prescaler . Figure 15 shows Mode 0 opera tion. In this mode, the T imer r[...]

  • Page 41

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 41 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 7.3 Mode 2 Mode 2 configures the T imer register as an 8-bit Cou nter (TLn) with automatic reload, as shown in Figure 17 . Overflow from TLn not only set s TFn, but also reloads TLn with the contents [...]

  • Page 42

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 42 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 3 IE1 Interrupt 1 Edge flag. Set by hardware when exter nal interrupt 1 edge is det ected. Cleared by hardware when the interrupt is processed, or by software. 4 TR0 T imer 0 Run contro l bit. Set/cle[...]

  • Page 43

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 43 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 7.6 Timer overflow toggle output T imers 0 and 1 can be configured to automatica lly toggle a port output whenever a timer overflow occurs. The same device pins that ar e used for the T0 and T1 cou nt[...]

  • Page 44

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 44 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual The Real-time Clock is a 23-bit down counter . The clock source for this counter can be either the CPU clock (CCLK) or the XT AL1-2 os cillator . There are five SFRs used for the RTC : RTCCON — Real[...]

  • Page 45

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 45 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 8.2 Changing RTCS1/RTCS0 RTCS1/R TCS0 cannot be changed if the RT C is currently enabled (RTCCON.0 = 1). Setting RTCEN and upda tin g RTCS1/R TCS0 may be done in a single write to RTCCON. However , if[...]

  • Page 46

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 46 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 010 0 00 Low frequ ency crystal Low frequency crystal /DIVM 01 10 1 1 Low frequency crystal /DIV 1 00 Low frequency crystal Internal RC oscillator 01 10 1 1 Internal RC oscillator 01 1 0 00 High freq [...]

  • Page 47

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 47 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 9. Capture/Compare Unit (CCU) This unit fe atures: • A 16-bit timer with 16-bit reload on ove rflow • Selectable clock (CCUCLK), with a prescaler to divide the cloc k sour ce by any integer betwee[...]

  • Page 48

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 48 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 9.3 Basic timer operation The T imer is a free-runnin g up /d o wn co un te r co un tin g at the pace deter min ed by th e prescaler . The timer is started by settin g the CCU Mode Select bits TMOD21 [...]

  • Page 49

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 49 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual depends on whether the timer is runnin g in PWM mode or in basic timer mode. In basic timer mode, writing a one to TCOU2 will caus e the values to be latched immediately and the value of TCOU2 will al[...]

  • Page 50

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 50 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 9.4 Output comp are The four output comp are chann els A, B, C a nd D ar e controlled th rough four 1 6-bit SFRs, OCRAH:OCRAL, OCRBH:OCRBL, OCR CH:OC RCL, OCRDH: OCRDL. Each output compare channe l ne[...]

  • Page 51

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 51 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual In order for a Comp are Output Action to occur , the compare va lues must be within the counting range of the CCU timer . When the comp ar e channel is enabled, the I/O pin (which must be configured a[...]

  • Page 52

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 52 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual Input Captur e Edge Select - ICESx bit (x be ing A or B) in th e CCCRx register. The user will have to configure the associated I/O pin as an input in order for an external event to trigger a capture.[...]

  • Page 53

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 53 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual The user will have to configur e the output compare pins as output s in order to enable the PWM output. As with basic timer operation, when the PWM (compar e) pins are co nnected to the compare logi c[...]

  • Page 54

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 54 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual [1] x = A, B, C, D [2] ‘ON’ means in the CCUCLK cycle after the event takes place. 9.8 Synchronized PWM register up date When the OCRx registers are written, a bu ilt in mechanism ensures that the[...]

  • Page 55

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 55 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual still operate as normal even if it has this added functiona lity enabled. When the PWM unit is halted, the timer will still run as normal. Th e HL TRN bit in TCR20 will be set to indicate that a halt [...]

  • Page 56

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 56 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual • The user is discouraged from writing or reading the tim er in asynchronous mode. The results may be unpredict able • Interrupts and flags are asynchronous. There will be delay as the event may n[...]

  • Page 57

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 57 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual Fig 25. Capture/comp are unit interrupt s. 002aaa896 interrupt to CPU T OIE2 (TICR2.7) T OIF2 (TIFR2.7) TICIE2A (TICR2.0) TICF2A (TIFR2.0) TICIE2B (TICR2.1) TICF2B (TIFR2.1) T OCIE2A (TICR2.3) T OCF2A[...]

  • Page 58

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 58 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual T able 47 . CCU interrupt flag regist er (TIFR 2 - address E9h) bit allocation Bit 76543210 Symbol TOIF2 TOCF2D TOCF2C TOCF2B TOCF2A - TICF2B TICF2A R e s e t 00000x 00 T able 48 . CCU interrupt fla g[...]

  • Page 59

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 59 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 10. UART The P89LPC9 321 has an enhanced UART that is compatible with the conventional 80C5 1 UART except that T i m e r 2 ove r flow can no t be used as a ba ud rat e so ur ce . The P89LPC9321 does i[...]

  • Page 60

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 60 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 10.4 Mode 3 1 1 bits are transm itted (through TXD) or recei ved (through RXD): a star t bit (logic 0), 8 data bit s (LSB first), a programmable 9th data bit, and a stop bit (logic 1). Mode 3 is the s[...]

  • Page 61

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 61 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 10.8 Framing error A Framing error occurs wh en the stop bit is sensed as a logic 0. A Framing error is reported in the st atus register (SST A T). In addition, if SMOD0 (P CON.6) is 1, framing errors[...]

  • Page 62

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 62 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual T able 55. Serial Port Control register (SCON - addr e ss 98h) bit allocation B i t 76543210 Symbol SM0/FE SM1 SM2 REN TB8 RB8 TI RI R e s e t xxxxxx0 0 T able 56. Serial Port Control register (SCON -[...]

  • Page 63

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 63 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 10.10 More abou t UART Mode 0 In Mode 0, a write to SBUF will initiate a tran smission. At the end of the transmission, TI (SCON.1) is set, which must be clear ed in so f twa re. Double buffering mu s[...]

  • Page 64

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 64 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 10.1 1 Mo re abou t UART Mode 1 Reception is initiated by detecting a 1-to-0 transition on RxD. RxD is sampl ed at a rate 16 times the programmed bau d rate. When a tran si tion is detected, the divid[...]

  • Page 65

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 65 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 10.12 More about UART Modes 2 and 3 Reception is the sa me as in Mode 1. The signal to load SBUF and RB8, and to set RI, will be gene rated if, and only if, the following conditions are met at the tim[...]

  • Page 66

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 66 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 10.14 Break detect A break is detected when 1 1 consecutive bits are sensed low and is reported in the st atus register (SST A T). For Mode 1, this co nsists of the st art bit, 8 data bits, and two st[...]

  • Page 67

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 67 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual – If DBISEL is logic 1 and INTLO is logic 0, a Tx interrupt will occ u r at the beginning of the STOP bit of the data currently in the shifter (which is also the last data). – If DBISEL is logic 1[...]

  • Page 68

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 68 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual If double buf fering is enabled, TB8 MUST be upd ated before SBUF is written, as TB8 will be double-buf fered together with SBUF data. The o per ation described in the Section 10.17 “ T ransmit inte[...]

  • Page 69

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 69 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 10.20 Automatic address recognition Automatic address recognition is a feature which allows the UAR T to recognize certain addresses in the serial bit stream by usi ng hard ware to make the comp ariso[...]

  • Page 70

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 70 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual reset SADDR and SADEN are load ed with 0s. This produces a given address of all ‘d on ’t cares’ as well as a Broadcast address of all ‘don’t cares’. This effectively disables the Automatic[...]

  • Page 71

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 71 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual The P89LPC9321 CPU interfaces with the I 2 C-bus through six S p ecial Function Registers (SFRs): I2CON (I 2 C Control Register), I2DA T (I 2 C Data Register), I2 ST A T (I 2 C S tatus Register), I2AD[...]

  • Page 72

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 72 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 11 . 3 I 2 C control register The CPU can read an d write this register . There are two bit s are af fected by hardwa re: the SI bit and the STO bit. The SI bit is set by hardware and the STO bit is c[...]

  • Page 73

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 73 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 11 . 4 I 2 C St atus register This is a read- only register . It contains the st at us code of the I 2 C interface. The least three bits are always 0. Ther e are 26 possible status codes. When the cod[...]

  • Page 74

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 74 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual The values for I2SCLL and I2SCLH do not have to be the same; the user ca n give diff erent duty cycles for SCL by setting thes e two registers. However , the value of the register must ensure that the[...]

  • Page 75

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 75 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual The first byte transmitted cont ains the slave address of the receiving device (7 bit s) and the data direction bit. In this case, the data direction bit (R/W) will be logic 0 indicating a write. Data[...]

  • Page 76

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 76 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual After a repeated ST ART condition, I 2 C-bus may switch to the Master T ransmitter Mode. 1 1.6.3 Slave Receiver mode In the Slave Receiver Mode, data bytes ar e received from a master transmitter . T [...]

  • Page 77

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 77 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 1 1.6.4 Slave T ransmitter mode The first byte is received an d hand le d as in th e Slav e Rec eiver Mode. Howeve r , in this mode, the direction bit will indicate that the tran sfer direction is rev[...]

  • Page 78

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 78 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual Fig 37. I 2 C serial interface block diag ram. INTERNAL BUS 002aaa899 ADDRESS REGISTER COMP ARA T OR SHIFT REGISTER 8 I2ADR ACK BIT COUNTER / ARBITRA TION & SYNC LOGIC 8 I2D A T TIMING AND CONTROL[...]

  • Page 79

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 79 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual T able 73 . Maste r T ransmitter mode St atus co de (I2ST A T) Status of the I 2 C hardware Applicat ion sof tware response Next action t aken by I 2 C hardware to/from I2DA T to I2CON ST A STO SI AA [...]

  • Page 80

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 80 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 30h Dat a byte in I2DA T has bee n transmitted, NOT ACK has been received L o a d d a t a b y t e o r 000x D a t a b y t e w i l l b e t r a n s m i t t e d ; ACK bit will be received no I2DA T action[...]

  • Page 81

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 81 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 50h Data byte has been received; ACK has been returned Read data byte 0 0 0 0 Data byte will be received; N OT ACK bit will be returned read data byte 0 0 0 1 Data byte will be recei ved; ACK bit will[...]

  • Page 82

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 82 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 88H Previously addressed with own SLA address; Data has been received; NACK has been returned R e a d d a t a b y t e o r 0000S w i t c h e d t o n o t a d d r e s s e d S L A mode; no recogniti on of[...]

  • Page 83

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 83 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual A0H A ST OP condition or repeated ST ART condition has been received while still addressed as SLA/REC or SLA/TRX N o I 2 D A T a c t i o n 0000S w i t c h e d t o n o t a d d r e s s e d S L A mode; n[...]

  • Page 84

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 84 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 12. Serial Peripheral Interface (SPI) The P89LPC9321 provides an other high-speed serial communication interface, the SPI interface. SPI is a full-duplex, high-spe ed, synch ronous communication bu s [...]

  • Page 85

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 85 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual The SPI interface has four pins: SPICLK, MOSI, MISO and SS : • SPICLK, MOSI and MISO are typically ti ed together between two or more SPI devices. Data flows from master to slave on the MOSI (Master[...]

  • Page 86

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 86 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual T able 78. SPI Control register (SPCTL - a ddress E2h) bit descri ption Bit Symbol Descrip tion 0 SPR0 SPI Clock Rate Select SPR1, SPR0: 00 — CCLK ⁄ 4 01 — CCLK ⁄ 16 10 — CCLK ⁄ 64 11 — [...]

  • Page 87

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 87 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual In Figure 39 , SSIG (SPCTL.7) for the slave is logic 0, and SS is used to select the s lave. The SPI master can use any po rt pin (including P2.4/SS ) to dr ive th e SS pin. Figure 40 shows a case whe[...]

  • Page 88

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 88 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual In Figure 41 , SSIG (SPCTL.7) bits for the slaves ar e logic 0, and the slaves are selected by the corr esponding SS s ignals. The SPI master ca n use any po rt pin (includ ing P2.4/SS ) to drive the [...]

  • Page 89

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 89 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual [1] Selected as a port function [2] The MSTR bit changes to logic 0 automatically when SS be comes low in input mode and SSIG is logic 0. 12.2 Additional consider ations for a slave When CPHA equals z[...]

  • Page 90

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 90 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual slave and sta rt sending dat a to it. T o avoid bu s contention, the SPI becomes a slave. As a result of the SPI becoming a sl ave, the MOSI and SPICLK pins are forced to be an input and MISO becomes [...]

  • Page 91

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 91 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual (1) Not defined Fig 42. SPI slave transfer format with CPHA = 0. 12345678 MSB LSB DORD = 0 DORD = 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB MSB LSB DORD = 0 DORD = 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB (1) 002aaa[...]

  • Page 92

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 92 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual (1) Not defined Fig 43. SPI slave transfer format with CPHA = 1. 12345678 MSB LSB DORD = 0 DORD = 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB MSB LSB DORD = 0 DORD = 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB 002aaa935 [...]

  • Page 93

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 93 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual (1) Not defined Fig 44. SPI master transfer for mat with CPHA = 0. 12345678 MSB LSB 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB MSB LSB DORD = 0 DORD = 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB 002aaa936 Clock cycle SPIC[...]

  • Page 94

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 94 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 12.7 SPI clock prescaler select The SPI clock pr escaler selection uses the SPR1 -SPR0 bits in the SPCTL re gister (see Ta b l e 7 8 ). 13. Analog comp arators T wo analog comp arators are provided on[...]

  • Page 95

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 95 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual The overall connections to both comp arators are shown in Figure 46 . There are eight possible con figurations for each comparator , as deter mined by the control bits in th e correspond ing CMPn regi[...]

  • Page 96

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 96 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 13.2 Internal reference volt age An internal referen ce voltag e, V ref(b g) , may supply a default reference when a single comparator input pin is used. Plea se refer to the P89LPC9321 dat a sheet fo[...]

  • Page 97

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 97 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 13.5 Comp arators and power reduction modes Either or both co mparators may remain enabled when Powe r-down mode or I dle mode is activated, but both comp arators are disabled automatically in T otal [...]

  • Page 98

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 98 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual ;Positive inpu t on CIN1A. ;Negative inpu t from CMPREF pin. ;Output to CMP1 pin enabled. CALL delay10us ;The comparator nee ds at least 10 mic roseconds before use. ANL CMP1,#0FEh ;Clear comparator 1[...]

  • Page 99

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 99 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual If PGA is enabled, it will consume pow er . Po wer can be reduced by disabling the PGA. PGA can be disabled via clearing ENPGAx bit. In Power-down mode or T otal Power-do wn mode, PGA does not func ti[...]

  • Page 100

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 100 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 14. Keyp ad interrupt (KBI) The Keypad Interrupt function is intended primarily to allo w a single interrupt to be generated wh en Port 0 is equal to or not equal to a certain p attern. This function[...]

  • Page 101

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 101 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual [1] The Keypad Interrupt must be enabled in order for the settings o f the KBMASK register to be effective. 15. W atchdog timer (WDT) The watchdog timer subsystem pr otects the system from incorrect [...]

  • Page 102

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 102 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual external crystal oscillator or the watchdog oscillator select ed by the WDCLK bit in the WDCON register and XT AL WD bit in the CL KC ON register . (Note that switching of the clock sources will not [...]

  • Page 103

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 103 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual T o feed the watchdog, two write instructions must be sequentially exe cuted successfully . Between the two write instructions, SFR reads ar e allo wed, but writes are not allowed. The instructions s[...]

  • Page 104

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 104 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual (3) Ta b l e 9 9 shows sample P89LPC9321 timeout values. tclks 2 57 + () () 255 1 + () 1 104 8577 = + = T able 97. Watchdog Timer Control register (WDCON - address A7h) bi t allocation Bit 76543210 S[...]

  • Page 105

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 105 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 15.3 W atchdog clock source The watchdog timer system has an on-chip 400 KHz oscillator . The watchdog timer can be clocked from the watchdog oscillator , PCLK or external crys tal oscillator (refer [...]

  • Page 106

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 106 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 15.4 W atchdog Timer in T imer mode Figure 51 shows the W atchdog T imer in T imer Mode. In this mode, any changes to WDCON are written to the shadow register af ter one watchdog clock cycle. A watch[...]

  • Page 107

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 107 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 15.5 Power-down operation The WDT oscillator and external crystal osc illator will continue to run in power-down, consuming ap pr o xim ate ly 50 μ A, as long as the WDT oscilla tor is selected as t[...]

  • Page 108

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 108 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 16.1 Sof tware reset The SRST bit in AU XR1 gives software the opportunity to reset the pro cessor complete ly , as if an external reset or watch dog reset ha d o ccu rred. If a va lue is writte n to[...]

  • Page 109

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 109 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual Bit 2 of AUXR1 is permanently wired as a logic 0. This is so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register , without the possibility of i[...]

  • Page 110

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 1 10 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual Row Fill: In this mode the addressed row (64 bytes, with addres s DEEADR[5:0] ignored) is filled with the DEEDA T pattern. T o erase the entire row to 00h or prog ram the entire row to FFh, write 00[...]

  • Page 111

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 1 1 1 o f 139 NXP Semiconductors UM10310 P89LPC9321 User manual 5. If both the EIEE (IEN1.7) bit and the EA (IEN0.7) bit are log ic 1s, wait for the Data EEPROM interrupt then read/poll the EEIF (DEECON.7) bit until it is set to logic 1. If EIEE or EA is logic[...]

  • Page 112

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 1 12 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 5. If both the EIEE (IEN1.7) bit and the EA (IEN0.7) bit are log ic 1s, wait for the Data EEPROM interrupt then read/poll the EEIF (DEECON.7) bit until it is set to logic 1. If EIEE or EA is logic 0[...]

  • Page 113

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 1 13 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual • Internal fixed boot ROM, containi ng lo w -level In-Application Programming (IAP) routines that can be called from the en d application (in ad dition to IAP- Lite). • Default seria l loader pr[...]

  • Page 114

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 1 14 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual • FMDA T A (Flash Data Register). Accept s data to be loaded into the page reg ister . The page register consist s of 64 bytes and an update flag for ea ch byte. When a LOAD command is issued to F[...]

  • Page 115

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 1 15 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual • Write the data for the next byte to be programmed to FMDA T A. • Repeat writing of FMADRL and/or FMDA T A until all desired bytes ha ve been loaded into the p age register . • Write the page[...]

  • Page 116

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 1 16 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual ;* C = clear on no err or, set on error * ;*************** ****************** ***************** LOAD EQU 00H EP EQU 68H PGM_USER: MOV FMCON,# LOAD ;load command, clears page r egister MOV FMADRH, R4[...]

  • Page 117

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 1 17 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual { FMDATA = dbytes[ i]; } FMCON = EP; //erase & prog page command Fm_stat = FMCON; //read the res ult status if ((Fm_stat & 0x0 F)!=0) prog_fail=1 ; else prog_fail=0; return(prog_fail); } 18.[...]

  • Page 118

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 1 18 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual The factory default settings for this device is shown in T able 107 , below . The factory pre-programme d bo ot loader can be erased by the user . Users who wish to use this load er should take caut[...]

  • Page 119

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 1 19 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual expense in component s and cir cuit board ar ea. The ISP function uses five pin s (V DD , V SS , TXD0, RXD0, and RST ). Only a small connector needs to be available to interface your application to [...]

  • Page 120

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 120 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual T able 108 . In-system Progra mming (ISP) hex record formats Record type Command/data function 00 Program User Code Memory Page : nnaaaa00dd..ddcc Where: nn = number of bytes to program; aaaa = page [...]

  • Page 121

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 121 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 03 Miscellaneous Read Functions : 01xxxx03sscc Where xxxx = req uired field but value is a ‘don’t care’; ss= subfunction code; cc = checksum Subfunction codes: 00= UCFG1 01= UCFG2 02= Boot V ec[...]

  • Page 122

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 122 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 18.12 In-application programming (IAP) Several In-App lication Programm ing (IAP) calls ar e available for u se by an applic ation program to perm it se lect ive era sin g an d pr og ra m m ing of Fl[...]

  • Page 123

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 123 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual is a logic 0, an internal W rite Enable (WE) flag is forced set and writes to the flash memory and configuration bytes are enabled. If the Active W rite Enable (A WE) bit is a logic 1, then the state[...]

  • Page 124

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 124 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual T able 10 9. IAP error status Bit Fl ag Descr iption 0 OI Operation Interrupted. Indicates that an operatio n was aborted due to an interrupt occu rring during a program or erase cycle. 1 SV Security[...]

  • Page 125

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 125 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual T able 1 10. IAP function calls IAP function IAP call parameters Program User Code Page (requires ‘key’) Input pa rameters: ACC = 00h R3= number of bytes to program R4= page address (MSB) R5= pag[...]

  • Page 126

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 126 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual Misc. Read Input parameters: ACC = 03h R7= register address 00= UCFG1 01= UCFG2 02= Boot V ector 03= S tatus Byte 04 to 07 = reserved 08= Security Byte 0 09= Security Byte 1 0A= Security Byte 2 0B= S[...]

  • Page 127

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 127 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 18.17 User configuration bytes A number of user-con figurable features of the P89LPC9321 must be d efined at power- up and therefore cannot be set by the program af ter start of execution. Thes e fea[...]

  • Page 128

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 128 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 18.18 User security bytes This device has three sec urity bits associated w ith each of its eigh t sectors, as s hown in T a ble 1 16 4 WDSE Watchdog Safety En able bit. Refer to T able 96 “ Watchd[...]

  • Page 129

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 129 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 18.19 Boot V ector register 18.20 Boot st atu s register T abl e 1 17. Sector Security Bytes (SECx) bit des cri ption Bit Symbol Des cription 0 MOVCDISx MOVC Disable. Disables the MOVC co mmand for s[...]

  • Page 130

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 130 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual T abl e 122. Bo ot Status (BOOTST A T) bit descri ption Bit Symbol Des cription 0 BSB Boot S tatus Bit. If programmed to logic 1, t he P89LPC9321 will always start execution at an address comprised o[...]

  • Page 131

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 131 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 19. Instruction set T able 12 3. Instruction set summar y Mnemonic Description Bytes Cycles Hex code ARITHMETIC ADD A,Rn Add register to A 1 1 28 to 2F ADD A,dir Add direct byte to A 2 1 2 5 ADD A,@R[...]

  • Page 132

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 132 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual XRL A,Rn Exclusive-OR register to A 1 1 68 to 6F XRL A,dir Exclusive-OR direct byte to A 2 1 65 XRL A, @Ri Exclusive-OR indirect memory to A 1 1 66 to 67 XRL A,#data Exclusive-OR immediate to A 2 1 6[...]

  • Page 133

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 133 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual XCHD A,@Ri Exchange A and indirect memory nibb le 1 1 D6 to D7 BOOLEAN Mnemonic Description Bytes Cycl es Hex code CLR C Clear carry 1 1 C3 CLR bit Clear direct bit 2 1 C2 SETB C Set carry 1 1 D3 SET[...]

  • Page 134

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 134 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 20. Legal information 20.1 Definitions Draft — The document is a draf t versi on only . The content is still under internal review and subject to formal approval, which may result in modifications [...]

  • Page 135

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 135 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 21. T ables T able 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 5 T able 2. S pecial function registers . . . . . . . . . . . . . . . . . 1 1 T able 3. Extended special func[...]

  • Page 136

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 136 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual T able 68. I 2 C S tatus register (I2ST A T - add ress D9h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 T able 69. I 2 C S tatus register (I2ST A T - add ress D9h) bit[...]

  • Page 137

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 137 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 22. Figures Fig 1. TSSOP28 pin configuration . . . . . . . . . . . . . . . . . . 3 Fig 2. PLCC28 pin configuration . . . . . . . . . . . . . . . . . . . 4 Fig 3. DIP28 pin configuration . . . . . . .[...]

  • Page 138

    UM10310_1 © NXP B.V. 2008. All rights reserved. User manual Rev . 01 — 1 December 2008 138 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 23. Content s 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Pin description . . . . . . . . . . [...]

  • Page 139

    NXP Semiconductors UM10310 P89LPC9321 User manual © NXP B.V . 20 08. All rig ht s reserved. For more information, please visit: http://www.nxp.com For sales office addresses, plea se se nd an email t o: salesaddresses@ nxp.com Date of releas e: 1 December 2008 Document identi fier: UM10310 _1 Please be awa re that import ant notices con cerning th[...]