Omega Engineering PCI-DIO96 manual

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Table of contents for the manual

  • Page 1

    PCI-DIO96 DIGITAL INPUT/OUTPUT User’s Manual Revision 2 November, 2000[...]

  • Page 2

    TABLE OF CONTENTS 22 7.3 VOLTAGE DIVIDERS ..................................... 21 7.2 TTL TO SOLID STATE RELAYS .......................... 20 7.1 PULL UP & PULL DOWN RESISTORS ................... 20 7 ELECTRONICS AND INTERFACING ....................... 18 6 SPECIFICATIONS ............................................ 17 5.4.7 Counter Interrupt [...]

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    This page is blank.[...]

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    1 INTRODUCTION The PCI-DIO96 is a 96-bit lin e digital I/O board. The board provides the 96 bits in four 24- bit groups. Each group provi des an 8-bi t port A and port B, as w ell as an 8-bit p or t C that can b e sp lit into ind epe ndent 4-b it po rt C-HI and a 4 -bit po rt C-LO. See Figure 1-1 below. On power up and reset, all I/O bits are set t[...]

  • Page 5

    2 INSTALLATION The PCI-DIO96 boards are completely plug-an d-play . There are no switches or jum p ers on the board. All board addresses are set by your com puter’s plu g-and-play software. Insta Cal is the installation, calibration and test softw are supp lied with y o ur data acquisition / IO hardware. Refer to the Exte nded Softwar e Installat[...]

  • Page 6

    3.2 CONNECTOR DIAGRAM The PCI-DIO96 I/O conn ector is a 100-pin ty pe connector access ible from the rear of the PC at the expansion backplate See Figure 3-1 below for the board pin out. Figure 3-1. PCI-DIO96 100-Pin Connector Pin Out 3 Port A7 B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 3[...]

  • Page 7

    Figure 3-2. Cable C100FF-xx Configuration 4 SIGNAL CONDI TIONING OR 50-PI N SCREW TERMINAL BOARD SIGNAL COND ITIONI NG o r 50 -PIN SCREW TERMIN AL BOARD . C100FF-xx CABLE BOARD’ S 100 -PIN I/O CONNECTOR I/O PI NS 1 TO 50 I/O PINS 5 1 TO 100[...]

  • Page 8

    Figure 3-3. Pin Translation - Pins 51 to 100 DI/O Signals 5 1 Port A7 D Port A6 D 2 3 Port A5 D Port A4 D 4 5 Port A3 D Port A2 D 6 7 Port A1 D Port A0 D 8 9 Port B7 D Port B6 D 10 1 1 Port B5 D Port B4 D 12 13 Port B3 D Port B2 D 14 15 Port B1 D Port B0 D 16 17 Port C7 D Port C6 D 18 19 Port C5 D Port C4 D 20 21 Port C3 D Port C2 D 22 23 Port C1 D[...]

  • Page 9

    3.3 SIGNAL CONNECTION CONSIDERATIONS All t he digi tal input s on th e PCI-DIO96 are 8255 CMOS TTL. The PCI-DIO96 output signals are 8255 CMOS. OMEGA Engineering Inc. o ff e rs a w i d e v a riet y o f d i g ital si gn a l c o n d iti o n i n g products that provide an ideal interface betw een hig h voltage and/or h igh current signals and the P CI[...]

  • Page 10

    3.4 CIO-ERB24 & SSR-RACK24 CONNECTIONS PCI-DIO96 boards provide digital I/O in two m ajor groups of 48 bits each (96 total, but each si de of th e C100FF-x x cable provides 48 bits). How ever, man y popular relay and SSR boards prov ide only 24-bit s of I/O. The CIO- ERB24 and SSR-RA CK24 each im plements a con nector scheme w here all 96 bits [...]

  • Page 11

    4 SOFTWARE We highly recomm end that users take adv antage of ou r Univ ersal Library package's easy- to-use program min g interfaces. However, if y ou are an ex perienced program mer, and w ish to read an d w rite directly to the board, w e have provi ded a detailed register map in the next chapter. 4.1 UNIVERSAL LIBRARY The Universal Library[...]

  • Page 12

    5 REGISTER MAPS The PCI Controll er, a PLX-9052, h as four con fig uration, con trol, and statu s registers (Table 5-1). They are described in the following section. Table 5-1. I/O Region Register Operations 8-bit byte Digital I/O registers BADR3 N/A N/A BADR2 32-bit double word PCI I/O-mapped config. registers BADR1 32-bit double word PCI memory-m[...]

  • Page 13

    INTE Interrupt enable (local): 0 = disabled, 1 = enabled (default) INTPOL Interrupt polarity: 0 = active low (default), 1 = active high INT Interrupt status: 0 = interrupt not active, 1 = interrupt active PCINT PCI interrupt enable: 0 = disabled (default), 1 = enabled LEVEL/EDGE Interrupt trigger control: 0 = level triggered mode (default), 1 = edg[...]

  • Page 14

    5.4 BADR3 BADR3 is an 8-bit data bus for reading, writing and control of the individual 82C55 chips and the 82C54. Refer to Table 5-2 for register offsets. Table 5-2. BADR3 Registers Interrupt Control 2 Interrupt Control 2 BADR3 + 15h Interrupt Control 1 Interrupt Control 1 BADR3 + 14h Counter Configure Counter Configuration BADR3 + 13h N/A N/A BAD[...]

  • Page 15

    GROUP 0, PORT B DATA BADR3 + 1 READ/WRITE D0 D1 D2 D3 D4 D5 D6 D7 0 1 2 3 4 5 6 7 GROUP 0, PORT C DATA BADR3 + 2 READ/WRITE CL1 CL2 CL3 CL4 CH1 CH2 CH3 CH4 C1 C2 C3 C4 C5 C6 C7 C8 0 1 2 3 4 5 6 7 GROUP 0 CONFIGURE BADR3 + 3 READ/WRITE CL B M1 CH A M2 M3 MS 0 1 2 3 4 5 6 7 This register is used to configure the Group 0 ports as either input or o utp[...]

  • Page 16

    Table 5-3. DIO Port Configurations/Per Group IN IN IN IN 155 9B 1 1 1 1 OUT IN IN IN 154 9A 0 1 1 1 IN IN OUT IN 153 99 1 0 1 1 OUT IN OUT IN 152 98 0 0 1 1 IN OUT IN IN 147 93 1 1 0 1 OUT OUT IN IN 146 92 0 1 0 1 IN OUT OUT IN 145 91 1 0 0 1 OUT OUT OUT IN 144 90 0 0 0 1 IN IN IN OUT 139 8B 1 1 1 0 OUT IN IN OUT 138 8A 0 1 1 0 IN IN OUT OUT 137 89[...]

  • Page 17

    GROUP 1 CONFIGURE BADR3 + 7 READ/WRITE CL B M1 CH A M2 M3 MS 0 1 2 3 4 5 6 7 5.4.3 Group 2 8255 Configuration & Data GROUP 2, PORT A DATA BADR3 + 8 READ/WRITE D0 D1 D2 D3 D4 D5 D6 D7 0 1 2 3 4 5 6 7 GROUP 2, PORT B DATA BADR3 + 9 READ/WRITE D0 D1 D2 D3 D4 D5 D6 D7 0 1 2 3 4 5 6 7 GROUP 2, PORT C DATA BADR3 + A hex READ/WRITE CL1 CL2 CL3 CL4 CH1[...]

  • Page 18

    GROUP 3, PORT B DATA BADR3 + D hex READ/WRITE D0 D1 D2 D3 D4 D5 D6 D7 0 1 2 3 4 5 6 7 GROUP 3, PORT C DATA BADR3 + E hex READ/WRITE CL1 CL2 CL3 CL4 CH1 CH2 CH3 CH4 C1 C2 C3 C4 C5 C6 C7 C8 0 1 2 3 4 5 6 7 GROUP 3 CONFIGURE BADR3 + F hex READ/WRITE CL B M1 CH A M2 M3 MS 0 1 2 3 4 5 6 7 5.4.5 8254 Configuration & Data COUNTER 1 DATA BADR3 + 10 hex[...]

  • Page 19

    COUNTER CONFIGURATION BADR3 + 13 hex READ/WRITE D0 D1 D2 D3 D4 D5 D6 D7 0 1 2 3 4 5 6 7 This register is used to set the operating modes of each of the 82C54’s counters. Configure the counters by writing mode information to the Configure register, followed by the count information written to the specific counter (data) registers. Refer to the Cel[...]

  • Page 20

    5.4.7 Counter Interrupt Source Configure BADR3 + 15 hex READ/WRITE CTR1 CTRIR INTEN X X X X X 0 1 2 3 4 5 6 7 INTEN Enables or disabled interrupts. 1 = enabled, 0 = disabled CTRIR Enables or disables the counters as an interrupt source. 1 = counters may generate interrupts. 0 = counters cannot generate interrupts. CTR1 Controls whether counter 2 is[...]

  • Page 21

    6 SPECIFICATIONS Power Consumption 150 mA max +5V Digital Input / Output User installed. Dual footprint allows pull-up or pull-down configuration Pull-Up/Pull-Down Resistors Input mode (high impedance) Power-up / reset state 0.8 volts max, − 0.5 volts absolute min Input Low 2.0 volts min, 5.5 volts absolute max Input High 0.4 volts max @ 2.5mA Ou[...]

  • Page 22

    Interrupts The interrupt control registers function with the four 82C55 devices and the 82C54 counter timer to provide interrupt sources. 1. 82C55 in Mode 1 or Mode 2 Interrupt configuration: • First Port C0 • First Port C3 • Second Port C0 • Second Port C3 • Third Port C0 • Third Port C3 • Fourth Port C0 • Fourth Port C3 Note: Any [...]

  • Page 23

    7 ELECTRONICS AND INTERFACING This brief introduction to the electronics most often needed by digital I/O board users covers a few key concepts. IMPORTANT NOTE WHENEVER AN 82C55 IS POWERED-ON OR RESET , A LL PINS ARE SET TO HIGH-IMPEDANCE INPUT . FOLL OWING STA NDA RD TTL FUNC TIONA LITY , THES E INPU TS WI LL TYPI CA LLY FLOAT HIGH, A ND MAY HA VE[...]

  • Page 24

    If the bo ard is in output mod e, the board has enough po w er to overri de the pull-up/down resistor's high signal and drive the line to 0 volts. If the output circuit asserts a high signal, the pull-up resistor guaranties that the line goes to +5 V. Of course, a pull-dow n resistor accomplishes the same task ex cept that the line is pulled l[...]

  • Page 25

    The most conv enient w ay to u se solid state relays and a PCI-DIO96 board is to use a Solid State Relay Rack. An SSR Rack is a circuit board with input buff er amplifiers that are powerful enough to switch the SSRs. T he buffer am plifier s and SSRs are socketed. The standard b uf fer amplifiers are inverting types, m eaning that a low input from [...]

  • Page 26

    For a given attenuation, pick a hand y resistor and call it R2, then u se this formula to calculate R1. R1=(A-1)*R2 with a f ull scale range of 0 to 5 volts, the Attenuation is 2:1, or just 2. Digital inputs can readily use voltage dividers. For example, if you w ish to measure a digital signal that is at 0 volts when off and 24 volts when on, y o [...]

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    For Your Notes 24[...]

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    For Your Notes 25[...]

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    For Your Notes 26[...]

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    EC Declaration of Conformity Description Part Number Digital I/O board PCI-DIO96 to which this d eclaration relates, m eets the essential requirements, is in conform ity with , and CE markin g has been applied according to th e relevant EC Directives listed belo w using the r elevant section o f the following EC standa rds and ot her normative docu[...]

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    OMEGA Engineering Inc. One OMEGA Drive Stamford , CT 0 6801 ( 800 ) 872 - 9436 Fax: ( 203 ) 359 - 7700 E-mail: info@ omega .com www. omega .com[...]