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Philips LPC2138 manual

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Table of contents for the manual

  • Page 1

    _ V1.7 User’s Guide Philips/NXP LPC2138 Target Board  iSYSTEM, March 2007 1/13 Ordering code ITLPC2138 Dimensions 100 x 96 mm Figure 1: ITLPC2138FE Target Board[...]

  • Page 2

    Contents Contents .............................................................................................................................. 2 Introduction ......................................................................................................................... 3 Description ......................................................[...]

  • Page 3

    Introduction NXP LPC2138 Ta rget Board is an evaluati on and a devel opment syst em for NXP ARM7TDMI-S based LPC2138 m icrocontroller. Th e ITLPC2138 package c onsists of a USB ca ble and a target boar d populated wi th NXP LPC2138 CPU, minim um peripherals, JTAG deb ug connector, ETM trace connector and a n on-board integrated iSYSTEM debugger. Th[...]

  • Page 4

    Block Diagram Figure 3: ITLPC2 138 Block diagram Notes 1. The board provides 16-pin co nn ector for the optional LCD display (type CMC216x04 or EW162B0GL Y, checkout ba cklight LE D p ol ari t y), which is not included in the pack age.  iSYSTEM, March 2007 4/13[...]

  • Page 5

    Components List Name Description P1 Expansion connector GPIO pins P0.0 – P0.7 P2 Expansion connector GPIO pins P0.8 – P0.15 P3 Expansion connector GPIO pins P0.16 – P0.23 P4 Expansion connector GPIO pins P0.25 – P0.31 P5 Expansion connector GPIO pins P1.16 – P1.23 P6 Expansion connector GPIO pins P1.24 a nd P1.25 P11 RTC power supply inpu[...]

  • Page 6

    Jumper & Connector Descriptions  J1, J2: LCD LED Backlight Polarity: If J1 and J2 is set in posi tion 1-2, then LC D pin15 is connect ed to +5V and pin16 is connected to GND. If J1 and J2 is set in position 2-3 then pin15 is connected to GND and pin16 is connected to +5V. Defau lt set in position 1-2.  J7: Trace Port En able : J7 is set t[...]

  • Page 7

    Connectors DB9 male connector UART1 (P35) Pin No. Symbol 2 RxD 3 TxD 5 GND 7 RTS 8 CTS The serial port is configured a s a standard RS232 interface with RTS/CTS co ntrol. Cross female to fem ale cable is needed for conn ection with PC computer COM port. 16-pin LCD connector (P21) Top View Pin Assignment for Crystal Clear technol ogy CMC2 16x04 or E[...]

  • Page 8

    20-pin JTAG Debug Connector (P33) Not used 1 2 T3V3 CPU_TRST 3 4 GND CPU_TDI 5 6 GND CPU_TMS 7 8 GND CTCK 9 10 GND Not used 11 12 GND CPU_TDO 13 14 GND CPU_RESET 15 16 GND Not used 17 18 GND Not used 19 20 GND An external J TAG deb ug tool can be c onnected t o a 20-pi n P33 debug c onnector. Jum per J9 must be set to 2- 3 position when using an ex[...]

  • Page 9

    CPU expansion connectors Figure 4: Expansion con nectors All CPU signals are available on the ex pansion connectors, which are standa rd connectors with a 2.54 mm raster.  iSYSTEM, March 2007 9/13[...]

  • Page 10

    Schematic Note: On-board integrated debugger is not part of the schematic.  iSYSTEM, Ma rch 2 00 7 10/13[...]

  • Page 11

    Use of the on-board integrated debugger Follow below instructions, in order to get a sample app lication running with “out of the box” experience . All jumpers are set in the default pos ition during the final tests in the manufacturing. If winIDEA 2006 CD is not part of th e package, please obtain winIDEA 2006 setup fro m your local iSYSTEM of[...]

  • Page 12

    Use of an external debugger An external debugger can be:  a JTAG debugger, which connect s to a 20 -pin P33 con nector  a development too l sup porting JTAG debuggin g and ETM (on-ch ip trace), which co nnects to a 38-pin Mictor P32 connector Setting up a debug enviro nment for the first time  Verify jumpers J15-J20 (see Ju mpers descripti[...]

  • Page 13

    Troubleshooting The flash boot loader code is exec uted every time the CPU is powered or re set. The loader ca n execute the ISP command ha ndler or the user applicat ion code. P 0.14 is sens ed on a rising edge on t he RST (CPU reset) pin. If a low level is detected, ISP command h andler starts and takes over control of th e CPU after reset. If th[...]