English dropdown-ico

Renesas 16-bit single-chip microcomputer manual

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334

Go to page of

Similar user manuals

A good user manual

The rules should oblige the seller to give the purchaser an operating instrucion of Renesas 16-bit single-chip microcomputer, along with an item. The lack of an instruction or false information given to customer shall constitute grounds to apply for a complaint because of nonconformity of goods with the contract. In accordance with the law, a customer can receive an instruction in non-paper form; lately graphic and electronic forms of the manuals, as well as instructional videos have been majorly used. A necessary precondition for this is the unmistakable, legible character of an instruction.

What is an instruction?

The term originates from the Latin word „instructio”, which means organizing. Therefore, in an instruction of Renesas 16-bit single-chip microcomputer one could find a process description. An instruction's purpose is to teach, to ease the start-up and an item's use or performance of certain activities. An instruction is a compilation of information about an item/a service, it is a clue.

Unfortunately, only a few customers devote their time to read an instruction of Renesas 16-bit single-chip microcomputer. A good user manual introduces us to a number of additional functionalities of the purchased item, and also helps us to avoid the formation of most of the defects.

What should a perfect user manual contain?

First and foremost, an user manual of Renesas 16-bit single-chip microcomputer should contain:
- informations concerning technical data of Renesas 16-bit single-chip microcomputer
- name of the manufacturer and a year of construction of the Renesas 16-bit single-chip microcomputer item
- rules of operation, control and maintenance of the Renesas 16-bit single-chip microcomputer item
- safety signs and mark certificates which confirm compatibility with appropriate standards

Why don't we read the manuals?

Usually it results from the lack of time and certainty about functionalities of purchased items. Unfortunately, networking and start-up of Renesas 16-bit single-chip microcomputer alone are not enough. An instruction contains a number of clues concerning respective functionalities, safety rules, maintenance methods (what means should be used), eventual defects of Renesas 16-bit single-chip microcomputer, and methods of problem resolution. Eventually, when one still can't find the answer to his problems, he will be directed to the Renesas service. Lately animated manuals and instructional videos are quite popular among customers. These kinds of user manuals are effective; they assure that a customer will familiarize himself with the whole material, and won't skip complicated, technical information of Renesas 16-bit single-chip microcomputer.

Why one should read the manuals?

It is mostly in the manuals where we will find the details concerning construction and possibility of the Renesas 16-bit single-chip microcomputer item, and its use of respective accessory, as well as information concerning all the functions and facilities.

After a successful purchase of an item one should find a moment and get to know with every part of an instruction. Currently the manuals are carefully prearranged and translated, so they could be fully understood by its users. The manuals will serve as an informational aid.

Table of contents for the manual

  • Page 1

    RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C F AMIL Y / M16C/60 SERIES 16 Rev. 1.02 Revision date: Jul. 01, 2005 Hardware Manual www.renesas.com Before using this material, please visit our website to verify that this is the most updated document available. REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN)[...]

  • Page 2

    Keep safety first in your circuit designs! Notes regarding these materials • Renesas T echnology Corporation puts the maximum effort into making semiconductor prod- ucts better and more reliable, but there is always the possibility that trouble may occur with them. T rouble with semiconductors may lead to personal injury , fire or property damage[...]

  • Page 3

    How to Use This Manual 1. Introduction This hardware manual provides detailed information on the M16C/6N Group (M16C/6NL, M16C/6NN) of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, used for bit function in each register are sho[...]

  • Page 4

    3. M16C Family Documents The following documents were prepared for the M16C family (1) . Document Contents Short Sheet Hardware overview Data Sheet Hardware overview and electrical characteristics Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, timing charts) Software Man[...]

  • Page 5

    A-1 T able of Contents SFR Page Reference ............................................................................................................ B -1 1. Overview ............................................................................................................................... 1 1.1 Applications ...................................[...]

  • Page 6

    A-2 7.2 CPU Clock and Peripheral Function Clock .................................................................................... ............ 43 7.2.1 CPU Clock and BCLK ....................................................................................................... ................. 43 7.2.2 Peripheral Function Clock ...................[...]

  • Page 7

    A-3 1 1. DMAC ....................................................................................................................... ......... 78 1 1.1 Transfer Cycle ............................................................................................................ .............................. 83 1 1.1.1 Effect of Source and Destinatio[...]

  • Page 8

    A-4 18. CAN Module ................................................................................................................. ... 198 18.1 CAN Module-Related Registers .............................................................................................. ............... 199 18.1.1 CAN Message Box .....................................[...]

  • Page 9

    A-5 20.4 Standard Serial I/O Mode .................................................................................................. .................... 256 20.4.1 ID Code Check Function .................................................................................................. .............. 256 20.4.2 Example of Circuit Application in Sta[...]

  • Page 10

    A-6 22.18 Flash Memory V ersion ..................................................................................................... .................... 308 22.18.1 Functions to Prevent Flash Memory from Rewriting .................................................................... 308 22.18.2 Stop Mode ...........................................[...]

  • Page 11

    B-1 SFR Page Reference PM0 PM1 CM0 CM1 AIER PRCR CM2 WDTS WDC RMAD0 RMAD1 PLC0 PM2 SAR0 DAR0 TCR0 DM0CON SAR1 DAR1 TCR1 DM1CON Address Register Symbol Page The blank areas are reserved. 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 001 1h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 0[...]

  • Page 12

    B-2 Address Register Symbol Page CAN0 Message Box 2: Identifier / DLC CAN0 Message Box 2: Data Field CAN0 Message Box 2: Time Stamp CAN0 Message Box 3: Identifier / DLC CAN0 Message Box 3: Data Field CAN0 Message Box 3: Time Stamp CAN0 Message Box 4: Identifier / DLC CAN0 Message Box 4: Data Field CAN0 Message Box 4: Time Stamp CAN0 Message Box 5: [...]

  • Page 13

    B-3 Address Register Symbol Page The blank areas are reserved. 200 201 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 01 10h 0 111 h 01 12h 01 13h 01 14h 01 15h 01 16h 01 17h 01 18h 01 19h 01 1Ah 01 1Bh 01 1Ch 01 1Dh 01 1Eh 01 1Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012B[...]

  • Page 14

    B-4 FMR1 FMR0 RMAD2 AIER2 RMAD3 The blank areas are reserved. Address Register Symbol Page 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 0[...]

  • Page 15

    B-5 C0MCTL0 C0MCTL1 C0MCTL2 C0MCTL3 C0MCTL4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 C0MCTL9 C0MCTL10 C0MCTL1 1 C0MCTL12 C0MCTL13 C0MCTL14 C0MCTL15 C0CTLR C0STR C0SSTR C0ICR C0IDR C0CONR C0RECR C0TECR C0TSR C1CTLR Address Register Symbol Page The blank areas are reserved. 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 02[...]

  • Page 16

    B-6 T ABSR CPSRF ONSF TRGSR UDF TA 0 TA 1 TA 2 TA 3 TA 4 TB0 TB1 TB2 T A0MR T A1MR T A2MR T A3MR T A4MR TB0MR TB1MR TB2MR TB2SC U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON DM0SL DM1SL CRCD CRCIN Address Register Symbol Page The blank areas are reserved. 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 0[...]

  • Page 17

    Rev.1.02 Jul 01, 2005 page 1 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev .1.02 Jul 01, 2005 Under development This document is under development and its contents are subject to change 1. Overview The M16C/6N Group (M16C/6NL, M16C/6NN) of single-chip microcomputers are built using the high-perf[...]

  • Page 18

    Rev.1.02 Jul 01, 2005 page 2 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview Under development This document is under development and its contents are subject to change. 1.2 Performance Outline Tables 1.1 and 1.2 list a performance outline of M16C/6N Group (M16C/6NL, M16C/6NN). Table 1.1 Performance Outline of M16C/6N Group (1[...]

  • Page 19

    Rev.1.02 Jul 01, 2005 page 3 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview Under development This document is under development and its contents are subject to change. Table 1.2 Performance Outline of M16C/6N Group (128-pin Version: M16C/6NN) Item Performance C P U Number of B asic I nstructions 9 1 instructions Minimum Inst[...]

  • Page 20

    Rev.1.02 Jul 01, 2005 page 4 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview Under development This document is under development and its contents are subject to change. 1.3 Block Diagram Figure 1.1 shows a block diagram of M16C/6N Group (M16C/6NL, M16C/6NN). Figure 1.1 Block Diagram NOTES: 1: ROM size depends on microcomputer[...]

  • Page 21

    Rev.1.02 Jul 01, 2005 page 5 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview Under development This document is under development and its contents are subject to change. 1.4 Product List Table 1.3 lists the M16C/6N Group (M16C/6NL, M16C/6NN) products and Figure 1.2 shows the type numbers, memory sizes and packages. Table 1.3 P[...]

  • Page 22

    Rev.1.02 Jul 01, 2005 page 6 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview Under development This document is under development and its contents are subject to change. PIN CONFIGURATION (top view) Figure 1.3 Pin Configuration (Top View) (1) 1.5 Pin Configuration Figures 1.3 and 1.4 show the pin configuration (top view). 1 2 [...]

  • Page 23

    Rev.1.02 Jul 01, 2005 page 7 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview Under development This document is under development and its contents are subject to change. PIN CONFIGURATION (top view) Figure 1.4 Pin Configuration (Top View) (2) 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 [...]

  • Page 24

    Rev.1.02 Jul 01, 2005 page 8 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview Under development This document is under development and its contents are subject to change. 1.6 Pin Description Tables 1.4 and 1.5 list the pin descriptions. Table 1.4 Pin Description (100-pin and 128-pin Versions) (1) I I I I I I O I O O I I I I/O I[...]

  • Page 25

    Rev.1.02 Jul 01, 2005 page 9 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview Under development This document is under development and its contents are subject to change. Table 1.5 Pin Description (100-pin and 128-pin Versions) (2) Applies the reference voltage for the A/D converter and D/A converter. Analog input pins for the [...]

  • Page 26

    Rev.1.02 Jul 01, 2005 page 10 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 2. Central Processing Unit (CPU) Under development This document is under development and its contents are subject to change. Figure 2.1 CPU Registers 2.1 Data Registers (R0, R1, R2, and R3) The R0 register consists of 16 bits, and is used mainly for transfers a[...]

  • Page 27

    Rev.1.02 Jul 01, 2005 page 11 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 2. Central Processing Unit (CPU) Under development This document is under development and its contents are subject to change. 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) [...]

  • Page 28

    Rev.1.02 Jul 01, 2005 page 12 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 3. Memory Under development This document is under development and its contents are subject to change. 3. Memory Figure 3.1 shows a memory map of the M16C/6N Group (M16C/6NL, M16C/6NN). The address space extends the 1 Mbyte from address 00000h to FFFFFh. The int[...]

  • Page 29

    Rev.1.02 Jul 01, 2005 page 13 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. 4. Special Function Register (SFR) SFR (Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.12[...]

  • Page 30

    Rev.1.02 Jul 01, 2005 page 14 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.2 SFR Information (2) CAN0 Wake-up Interrupt Control Register CAN0 Successful Reception Interrupt Control Register CAN0 Succes[...]

  • Page 31

    Rev.1.02 Jul 01, 2005 page 15 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.3 SFR Information (3) X: Undefined 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 0[...]

  • Page 32

    Rev.1.02 Jul 01, 2005 page 16 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.4 SFR Information (4) X: Undefined 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 0[...]

  • Page 33

    Rev.1.02 Jul 01, 2005 page 17 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.5 SFR Information (5) X: Undefined 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 0[...]

  • Page 34

    Rev.1.02 Jul 01, 2005 page 18 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.6 SFR Information (6) X: Undefined NOTE: 1. The blank areas are reserved and cannot be accessed by users. 0140h 0141h 0142h 01[...]

  • Page 35

    Rev.1.02 Jul 01, 2005 page 19 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.7 SFR Information (7) X: Undefined NOTES: 1. These registers are included in the flash memory version. Cannot be accessed by u[...]

  • Page 36

    Rev.1.02 Jul 01, 2005 page 20 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.8 SFR Information (8) T imer B3, B4, B5 Count Start Flag T imer A1-1 Register T imer A2-1 Register T imer A4-1 Register Three-[...]

  • Page 37

    Rev.1.02 Jul 01, 2005 page 21 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. X: Undefined NOTE: 1. The blank areas are reserved and cannot be accessed by users. 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 02[...]

  • Page 38

    Rev.1.02 Jul 01, 2005 page 22 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. X: Undefined NOTE: 1. The blank areas are reserved and cannot be accessed by users. XXh XXh 00h 00h CAN0 Acceptance Filter Support Reg[...]

  • Page 39

    Rev.1.02 Jul 01, 2005 page 23 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. X: Undefined NOTES: 1. The TA2P to TA4P bits in the UDF register are set to "0" after reset. However, the contents in these [...]

  • Page 40

    Rev.1.02 Jul 01, 2005 page 24 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. X: Undefined NOTES: 1. These registers exist only in the128-pin version. 2. The blank areas are reserved and cannot be accessed by use[...]

  • Page 41

    Rev.1.02 Jul 01, 2005 page 25 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 5. Reset Under development This document is under development and its contents are subject to change. 5. Reset Hardware reset, software reset, watchdog timer reset and oscillation stop detection reset are available to reset the microcomputer. 5.1 Hardware Reset [...]

  • Page 42

    Rev.1.02 Jul 01, 2005 page 26 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 5. Reset Under development This document is under development and its contents are subject to change. Figure 5.2 Reset Sequence Figure 5.1 Example Reset Circuit RESET VCC R E S E T VCC 0 V 0 V Supply a clock with td(P-R) +20 or more cycles to the XIN pin 0.2VCC [...]

  • Page 43

    Rev.1.02 Jul 01, 2005 page 27 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 5. Reset Under development This document is under development and its contents are subject to change. P0, P1, P2, P3, P4, P5, P6, P7, Input port P8_0 to P8_4, P8_6, P8_7, P9, P10, P11, P12, P13, P14_0, P14_1 (2) ____________ Table 5.1 Pin Status When RESET Pin L[...]

  • Page 44

    Rev.1.02 Jul 01, 2005 page 28 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 6. Processor Mode Under development This document is under development and its contents are subject to change. 6. Processor Mode Three processor mode is available single-chip mode only. Figures 6.1 and 6.2 show the processor mode related registers. Figure 6.3 sh[...]

  • Page 45

    Rev.1.02 Jul 01, 2005 page 29 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 6. Processor Mode Under development This document is under development and its contents are subject to change. Figure 6.2 PM1 Register Symbol Address After Reset PM1 0005h 00001000b PM17 PM13 PM12 PM10 - (b1) - (b6-b4) Data Block Enable Bit (2) Reserved Bit Watc[...]

  • Page 46

    Rev.1.02 Jul 01, 2005 page 30 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 6. Processor Mode Under development This document is under development and its contents are subject to change. Figure 6.3 Memory Map Single-chip mode SFR Internal RAM Can not use Internal ROM Capacity 16 Kbytes 20 Kbytes 31 Kbytes Address XXXXXh 03FFFh 03FFFh 03[...]

  • Page 47

    Rev.1.02 Jul 01, 2005 page 31 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 7. Clock Generating Circuit 7.1 Types of Clock Generating Circuit Four circuits are incorporated to generate the system clock signal: • Mai[...]

  • Page 48

    Rev.1.02 Jul 01, 2005 page 32 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 7.1 Clock Generating Circuit 1/16 CLKOUT CM01-CM00=00b PM01-PM00=00b, CM01-CM00=01b PM01-PM00=00b, CM01-CM00=10b PM01-PM00=00b, CM01-C[...]

  • Page 49

    Rev.1.02 Jul 01, 2005 page 33 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 7.2 CM0 Register System Clock Control Register 0 (1) NOTES: 1. Write to this register after setting the PRC0 bit in the PRCR register [...]

  • Page 50

    Rev.1.02 Jul 01, 2005 page 34 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 7.3 CM1 Register RW RW RW RW RW RW RW Bit Name Function Bit Symbol CM10 CM15 CM16 CM17 CM11 - (b4-b2) All Clock Stop Control Bit (2) ([...]

  • Page 51

    Rev.1.02 Jul 01, 2005 page 35 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 7.4 CM2 Register Oscillation Stop Detection Register (1) Symbol Address After Reset CM2 000Ch 0X000000b (2) Function b7 b6 b5 b4 b3 b2[...]

  • Page 52

    Rev.1.02 Jul 01, 2005 page 36 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 7.5 PCLKR Register NOTES: 1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable). 2[...]

  • Page 53

    Rev.1.02 Jul 01, 2005 page 37 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Symbol Address After Reset PM2 001Eh XXX00000b Processor Mode Register 2 (1) b7 b6 b5 b4 b3 b2 b1 b0 00 0 Specifying Wait when Accessing SFR [...]

  • Page 54

    Rev.1.02 Jul 01, 2005 page 38 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 7.8 PLC0 Register PLC07 Function PLL Control Register 0 (1) Operation Enable Bit (3) 0 : PLL Off 1 : PLL On Bit Name Bit Symbol Symbol[...]

  • Page 55

    Rev.1.02 Jul 01, 2005 page 39 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. NOTE: 1 . Place a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setti[...]

  • Page 56

    Rev.1.02 Jul 01, 2005 page 40 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 7.10 Examples of Sub Clock Connection Circuit 7.1.2 Sub Clock The sub clock is generated by the sub clock oscillation circuit. This cl[...]

  • Page 57

    Rev.1.02 Jul 01, 2005 page 41 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 7.1.3 On-chip Oscillator Clock This clock, approximately 1 MHz, is supplied by a on-chip oscillator. This clock is used as the clock source f[...]

  • Page 58

    Rev.1.02 Jul 01, 2005 page 42 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 7.11 Procedure to Use PLL Clock as CPU Clock Source Set the PLC02 to PLC00 bits (multiplying factor). (When PLL clock > 16 MHz) Set[...]

  • Page 59

    Rev.1.02 Jul 01, 2005 page 43 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 7.2 CPU Clock and Peripheral Function Clock Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the perip[...]

  • Page 60

    Rev.1.02 Jul 01, 2005 page 44 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 7.4 Power Control Normal operation mode, wait mode and stop mode are provided as the power consumption control. All mode states, except wait [...]

  • Page 61

    Rev.1.02 Jul 01, 2005 page 45 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 7.4.1.6 On-chip Oscillator Mode The on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on-chip osci[...]

  • Page 62

    Rev.1.02 Jul 01, 2005 page 46 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 7.4.2 Wait Mode In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the watchdog timer. However[...]

  • Page 63

    Rev.1.02 Jul 01, 2005 page 47 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Interrupt CM02 Bit = 0 CM02 Bit = 1 _______ NMI Interrupt Can be used Can be used Serial I/O Interrupt Can be used when operating with Can be[...]

  • Page 64

    Rev.1.02 Jul 01, 2005 page 48 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 7.4.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the[...]

  • Page 65

    Rev.1.02 Jul 01, 2005 page 49 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 7.4.3.3 Exiting Stop Mode _______ Stop mode is exited by a hardware reset, NMI interrupt or peripheral function interrupt. _______ When the h[...]

  • Page 66

    Rev.1.02 Jul 01, 2005 page 50 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 7.12 State Transition to Stop Mode and Wait Mode Stop Mode Reset Normal Mode PLL Operation Mode High-Speed Mode, Medium-Speed Mode Med[...]

  • Page 67

    Rev.1.02 Jul 01, 2005 page 51 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 7.13 State Transition in Normal Operation Mode CPU clock : f(PLL) CM07 = 0 CM06 = 0 CM17 = 0 CM16 = 0 PLL operation mode PLL operation[...]

  • Page 68

    Rev.1.02 Jul 01, 2005 page 52 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Table 7.7 Allowed Transition and Setting State after transition High-Speed Mode, Low-Speed Low Power PLL Operation On-chip Oscillator On-chip[...]

  • Page 69

    Rev.1.02 Jul 01, 2005 page 53 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 7.5 Oscillation Stop and Re-oscillation Detection Function The oscillation stop and re-oscillation detection function is such that main clock[...]

  • Page 70

    Rev.1.02 Jul 01, 2005 page 54 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 7.5.3 How to Use Oscillation Stop and Re-oscillation Detection Function • The oscillation stop, re-oscillation detection interrupt shares t[...]

  • Page 71

    Rev.1.02 Jul 01, 2005 page 55 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 8. Protection Under development This document is under development and its contents are subject to change. 8. Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Fi[...]

  • Page 72

    Rev.1.02 Jul 01, 2005 page 56 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. Figure 9.1 Interrupts • Maskable Interrupt: A n interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priorit[...]

  • Page 73

    Rev.1.02 Jul 01, 2005 page 57 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. 9.2 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. 9.2.1 Undefined In[...]

  • Page 74

    Rev.1.02 Jul 01, 2005 page 58 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. 9.3 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts. 9.3.1 Special Interrupt[...]

  • Page 75

    Rev.1.02 Jul 01, 2005 page 59 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. Figure 9.2 Interrupt Vector 9.4.1 Fixed Vector Tables The fixed vector tables are allocated to the addresses from FFFDCh to FFFFFh. Table 9.1 lists the fixe[...]

  • Page 76

    Rev.1.02 Jul 01, 2005 page 60 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. Table 9.2 Relocatable Vector Tables 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 to 63 BRK Instruction (2) CAN0 [...]

  • Page 77

    Rev.1.02 Jul 01, 2005 page 61 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. 9.5 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. W[...]

  • Page 78

    Rev.1.02 Jul 01, 2005 page 62 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. Figure 9.4 Interrupt Control Registers (2) 0044h 0048h 0049h 005Dh to 005Fh 0057h 0058h 005Bh Interrupt Control Register (1) INT3IC S4IC/INT5IC (6) S3IC/INT[...]

  • Page 79

    Rev.1.02 Jul 01, 2005 page 63 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. 9.5.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “ 1 ” (enabled) enables the maskable interrupt. Setting the I [...]

  • Page 80

    Rev.1.02 Jul 01, 2005 page 64 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. 9.5.4 Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt r[...]

  • Page 81

    Rev.1.02 Jul 01, 2005 page 65 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. Figure 9.6 Interrupt response time 9.5.6 Variation of IPL when Interrupt Request is Accepted When a maskable interrupt request is accepted, the interrupt pr[...]

  • Page 82

    Rev.1.02 Jul 01, 2005 page 66 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. 9.5.7 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 hi[...]

  • Page 83

    Rev.1.02 Jul 01, 2005 page 67 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. 9.5.8 Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are res[...]

  • Page 84

    Rev.1.02 Jul 01, 2005 page 68 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. Figure 9.10 Interrupts Priority Select Circuit Timer B2 Timer B0, SI/O6 (2) Timer A3, INT6 (2) Timer A1 Timer B1, INT8 (2) Timer A4 DMA1 DMA0 SI/O3, INT4 IN[...]

  • Page 85

    Rev.1.02 Jul 01, 2005 page 69 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. ______ 9.6 INT Interrupt _______ INTi interrupt (i = 0 to 8) (1) is triggered by the edges of external inputs. The edge polarity is selected using the IFSR1[...]

  • Page 86

    Rev.1.02 Jul 01, 2005 page 70 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. Figure 9.11 IFSR0 Register NOTES: 1. When the PCLK6 bit in the PCLKR register = 0, A/D conversion and key input share the vector and interrupt control regis[...]

  • Page 87

    Rev.1.02 Jul 01, 2005 page 71 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. Figure 9.12 IFSR1 Register Interrupt Request Cause Select Register 1 RW Symbol Address After Reset IFSR1 01DFh 00h RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2[...]

  • Page 88

    Rev.1.02 Jul 01, 2005 page 72 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. Figure 9.13 IFSR2 Register Interrupt Request Cause Select Register 2 RW Symbol Address After Reset IFSR2 01CFh X0000000b RW RW RW RW RW RW RW - b7 b6 b5 b4 [...]

  • Page 89

    Rev.1.02 Jul 01, 2005 page 73 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. ______ 9.7 NMI Interrupt _______ _______ ______ An NMI interrupt request is generated when input on the NMI pin changes state from high to low. The NMI inte[...]

  • Page 90

    Rev.1.02 Jul 01, 2005 page 74 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. 9.10 Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the ad- dress indicated by the [...]

  • Page 91

    Rev.1.02 Jul 01, 2005 page 75 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. Figure 9.16 AIER Register, AIER2 Register and RMAD0 to RMAD3 Registers RW - Address Match Interrupt Enable Register Address Match Interrupt 0 Enable Bit Add[...]

  • Page 92

    Rev.1.02 Jul 01, 2005 page 76 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 10. W atchdog T imer Under development This document is under development and its contents are subject to change. 10. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog ti[...]

  • Page 93

    Rev.1.02 Jul 01, 2005 page 77 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 10. W atchdog T imer Under development This document is under development and its contents are subject to change. Figure 10.2 WDC Register and WDTS Register 10.1 Count Source Protective Mode In this mode, a on-chip oscillator clock is used for the watchdog timer[...]

  • Page 94

    Rev.1.02 Jul 01, 2005 page 78 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change. 11. DMAC The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA[...]

  • Page 95

    Rev.1.02 Jul 01, 2005 page 79 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change. Item Specification No. of Channels 2 (cycle steal method) Transfer Memory Space • From any address in the 1-Mbyte space to a fixed address • From a fixed a[...]

  • Page 96

    Rev.1.02 Jul 01, 2005 page 80 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change. Figure 11.2 DM0SL Register DMA0 Request Cause Select Register Symbol Address After Reset DM0SL 03B8h 00h DSEL0 DSEL1 DSEL2 DSEL3 DSR DMS - (b5-b4) Function Bit[...]

  • Page 97

    Rev.1.02 Jul 01, 2005 page 81 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change. Figure 11.3 DM1SL Register, DM0CON and DM1CON Registers DMA1 Request Cause Select Register Symbol Address After Reset DM1SL 03BAh 00h DSEL0 DSEL1 DSEL2 DSEL3 D[...]

  • Page 98

    Rev.1.02 Jul 01, 2005 page 82 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change. Figure 11.4 SAR0 and SAR1 Registers, DAR0 and DAR1 Registers, TCR0 and TCR1 Registers Symbol After Reset SAR0 SAR1 Indeterminate Indeterminate Setting Range RW[...]

  • Page 99

    Rev.1.02 Jul 01, 2005 page 83 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change. 11.1 Transfer Cycle The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read a[...]

  • Page 100

    Rev.1.02 Jul 01, 2005 page 84 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change. Figure 11.5 Transfer Cycles for Source Read NOTE: 1. The same timing changes occur with the respective conditions at the destination as at the source. (1) When[...]

  • Page 101

    Rev.1.02 Jul 01, 2005 page 85 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change. 11.2 DMA Transfer Cycles Any combination of even or odd transfer read and write addresses is possible. Table 11.2 shows the number of DMA transfer cycles. Tabl[...]

  • Page 102

    Rev.1.02 Jul 01, 2005 page 86 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change. 11.3 DMA Enable When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0, 1) to “ 1 ” (enabled), the DMAC operates as follows: [...]

  • Page 103

    Rev.1.02 Jul 01, 2005 page 87 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change. 11.5 Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected active in the [...]

  • Page 104

    Rev.1.02 Jul 01, 2005 page 88 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. 12. Timers Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer A (five) and timer B (s[...]

  • Page 105

    Rev.1.02 Jul 01, 2005 page 89 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Figure 12.2 Timer B Configuration f1 or f2 f8 f32 fC32 1 0 00 01 10 11 TCK1 TMOD1 to TMOD0 00: Timer mode 10: Pulse width / period measuring mode 01: Event c[...]

  • Page 106

    Rev.1.02 Jul 01, 2005 page 90 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. 12.1 Timer A Figure 12.3 shows a block diagram of the timer A. Figures 12.4 to 12.6 show the timer A-related registers. The timer A supports the following fo[...]

  • Page 107

    Rev.1.02 Jul 01, 2005 page 91 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Figure 12.4 TA0MR to TA4MR Registers and TA0 to TA4 Registers Timer Ai Mode Register (i = 0 to 4) TA0MR to TA4MR Bit Name Function Bit Symbol RW b7 b6 b5 b4 [...]

  • Page 108

    Rev.1.02 Jul 01, 2005 page 92 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Figure 12.5 TABSR Register and UDF Register Timer A4 Up/Down Flag Timer A3 Up/Down Flag Timer A2 Up/Down Flag Timer A1 Up/Down Flag Timer A0 Up/Down Flag Tim[...]

  • Page 109

    Rev.1.02 Jul 01, 2005 page 93 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Figure 12.6 ONSF Register, TRGSR Register and CPSRF Register One-Shot Start Flag Symbol Address ONSF 0382h Timer A0 One-Shot Start Flag Timer A1 One-Shot Sta[...]

  • Page 110

    Rev.1.02 Jul 01, 2005 page 94 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Item Specification Count Source f1, f2, f8, f32, fC32 Count Operation • Down-count • When the timer underflows, it reloads the reload register contents a[...]

  • Page 111

    Rev.1.02 Jul 01, 2005 page 95 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Item Specification Count Source • External signals input to TAiIN pin (effective edge can be selected in program) • Timer B2 overflows or underflows, Tim[...]

  • Page 112

    Rev.1.02 Jul 01, 2005 page 96 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Figure 12.8 TA0MR to TA4MR Registers in Event Counter Mode (when not using two-phase pulse signal processing) Symbol Address After Reset TA0MR to TA4MR 0396h[...]

  • Page 113

    Rev.1.02 Jul 01, 2005 page 97 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Item Specification Count Source • Two-phase pulse signals input to TAiIN or TAiOUT pins Count Operation • Up-count or down-count can be selected by two-p[...]

  • Page 114

    Rev.1.02 Jul 01, 2005 page 98 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Figure 12.9 TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase pulse signal processing with timer A2, A3 or A4) Timer Ai Mode Register (i =[...]

  • Page 115

    Rev.1.02 Jul 01, 2005 page 99 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. 12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value to “ 0 ” by Z-phase (counter initial[...]

  • Page 116

    Rev.1.02 Jul 01, 2005 page 100 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Item Specification Count Source f1, f2, f8, f32, fC32 Count Operation • Down-count • When the counter reaches 0000h , it stops counting after reloading [...]

  • Page 117

    Rev.1.02 Jul 01, 2005 page 101 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Bit Name Symbol TA0MR to TA4MR Function Bit Symbol b7 b6 b5 b4 b3 b2 b1 b0 Operation Mode Select Bit 1 0 : One-shot timer mode b1 b0 TMOD1 TMOD0 MR0 Pulse O[...]

  • Page 118

    Rev.1.02 Jul 01, 2005 page 102 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. 12.1.4 Pulse Width Modulation (PWM) Mode In pulse width modulation mode, the timer outputs pulses of a given width in succession. The counter functions as e[...]

  • Page 119

    Rev.1.02 Jul 01, 2005 page 103 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Figure 12.12 TA0MR to TA4MR Registers in Pulse Width Modulation Mode Bit Name Timer Ai Mode Register (i = 0 to 4) Function Bit Symbol b7 b6 b5 b4 b3 b2 b1 b[...]

  • Page 120

    Rev.1.02 Jul 01, 2005 page 104 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Figure 12.13 Example of 16-bit Pulse Width Modulator Operation 1 / fi ✕ (2 — 1) 16 Count source Input signal to TAiIN pin PWM pulse output from TAiOUT p[...]

  • Page 121

    Rev.1.02 Jul 01, 2005 page 105 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. 12.2 Timer B Figure 12.15 shows a block diagram of the timer B. Figures 12.16 and 12.17 show the timer B-related registers. Timer B supports the following t[...]

  • Page 122

    Rev.1.02 Jul 01, 2005 page 106 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Figure 12.16 TB0MR to TB5MR Registers and TB0 to TB5 Registers Timer Bi Mode Register (i = 0 to 5) Bit Name Function Bit Symbol RW b7 b6 b5 b4 b3 b2 b1 b0 0[...]

  • Page 123

    Rev.1.02 Jul 01, 2005 page 107 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Figure 12.17 TABSR Register, TBSR Register and CPSRF Register Symbol Address After Reset TABSR 0380h 00h Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Bit Name B[...]

  • Page 124

    Rev.1.02 Jul 01, 2005 page 108 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Item Specification Count Source f1, f2, f8, f32, fC32 Count Operation • Down-count • W hen the timer underflows, it reloads the reload register contents[...]

  • Page 125

    Rev.1.02 Jul 01, 2005 page 109 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Item Specification Count Source • E xternal signals input to TBiIN pin (effective edge can be selected in program) • Timer Bj overflow or underflow Coun[...]

  • Page 126

    Rev.1.02 Jul 01, 2005 page 110 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Item Specification Count Source f1, f2, f8, f32, fC32 Count Operation • Up-count • Counter value is transferred to reload register at an effective edge [...]

  • Page 127

    Rev.1.02 Jul 01, 2005 page 111 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Figure 12.20 TB0MR to TB5MR Registers in Pulse Period and Pulse Width Measurement Mode Timer Bi Mode Register (i = 0 to 5) Bit Name Bit Symbol RW b7 b6 b5 b[...]

  • Page 128

    Rev.1.02 Jul 01, 2005 page 112 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Figure 12.22 Operation Timing When Measuring Pulse Width Figure 12.21 Operation Timing When Measuring Pulse Period Count source Measurement pulse TBiS bit I[...]

  • Page 129

    Rev.1.02 Jul 01, 2005 page 113 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. 13. Three-Phase Motor Control Timer Function Timers A1, A2, A4 and B2 can be used to output three-phase motor drive wavefo[...]

  • Page 130

    Rev.1.02 Jul 01, 2005 page 114 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 13.1 Three-Phase Motor Control Timer Function Block Diagram DUB1 bit Timer B2 (Timer Mode) Timer B2 Underflow ICTB2[...]

  • Page 131

    Rev.1.02 Jul 01, 2005 page 115 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 13.2 INVC0 Register NOTES: 1. Set the INVC0 register after the PRC1 bit in the PRCR register is set to "1"[...]

  • Page 132

    Rev.1.02 Jul 01, 2005 page 116 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 13.3 INVC1 Register INV10 INV1 1 INV12 INV13 INV15 T A1 1, T A21 and T A41 Registers INV00 and INV01 Bit Not used U[...]

  • Page 133

    Rev.1.02 Jul 01, 2005 page 117 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 13.4 IDB0 and IDB1 Registers and DTT Register Three-Phase Output Buffer Register i (i = 0, 1) (1) Symbol Address Af[...]

  • Page 134

    Rev.1.02 Jul 01, 2005 page 118 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 13.5 TA1, TA2, TA4, TA11, TA21 and TA41 Registers, and TB2 Register T imer Ai, Ai-1 Register (i = 1, 2, 4) (1) (2) [...]

  • Page 135

    Rev.1.02 Jul 01, 2005 page 119 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 13.6 ICTB2 Register and TB2SC Register T imer B2 Interrupt Occurrence Frequency Set Counter (1) (2) (3) Symbol Addr[...]

  • Page 136

    Rev.1.02 Jul 01, 2005 page 120 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 13.7 TRGSR Register and TRBSR Register T rigger Select Register Symbol Address After Reset TRGSR 0383h 00h b7 b6 b5[...]

  • Page 137

    Rev.1.02 Jul 01, 2005 page 121 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 13.8 TA1MR, TA2MR and TA4MR Registers, and TB2MR Register T imer Ai Mode Register (i = 1, 2, 4) Symbol Address Afte[...]

  • Page 138

    Rev.1.02 Jul 01, 2005 page 122 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 13.9 Triangular Wave Modulation Operation The three-phase motor control timer function is enabled by setting the IN[...]

  • Page 139

    Rev.1.02 Jul 01, 2005 page 123 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 13.10 Sawtooth Wave Modulation Operation Timer B2 U-Phase Sawtooth Wave Signal Wave U-Phase Output Signal (1) U-Pha[...]

  • Page 140

    Rev.1.02 Jul 01, 2005 page 124 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14. Serial I/O Serial I/O is configured with 7 channels: UART0 to UART2 and SI/O3 to SI/O6 (1) . NOTE: 1. 100-pin version supports 5 channels; UART0 to U[...]

  • Page 141

    Rev.1.02 Jul 01, 2005 page 125 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.1 UART0 Block Diagram RXD0 1 / (n0+1) 1/16 1/16 1/2 U0BRG register Clock synchronous type (when internal clock is selected) Clock synchronous t[...]

  • Page 142

    Rev.1.02 Jul 01, 2005 page 126 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.3 UART2 Block Diagram RXD2 1 / (n2+1) 1/16 1/16 1/2 U2BRG register Clock synchronous type (when internal clock is selected) Clock synchronous t[...]

  • Page 143

    Rev.1.02 Jul 01, 2005 page 127 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.4 UARTi Transmit/Receive Unit SP SP PAR 2SP 1SP UART TXDi D8 D7 D6 D5 D4 D3 D2 D1 D0 2SP 1SP UART RXDi D7 D6 D5 D4 D3 D2 D1 D0 D8 0 00000 0 SP [...]

  • Page 144

    Rev.1.02 Jul 01, 2005 page 128 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.5 U0TB to U2TB Registers, U0RB to U2RB Registers, and U0 BRG to U2BRG Registers Nothing is assigned When write, set to "0". When read[...]

  • Page 145

    Rev.1.02 Jul 01, 2005 page 129 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.6 U0MR to U2MR Registers and U0C0 to U2C0 Registers Function UARTi Transmit/Receive Control Register 0 (i = 0 to 2) Bit Name Bit Symbol Symbol [...]

  • Page 146

    Rev.1.02 Jul 01, 2005 page 130 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.7 U0C1, U1C1 Registers and U2C1 Register b7 b6 b5 b4 b3 b2 b1 b0 Function UARTj Transmit/Receive Control Register 1 (j = 0, 1) Bit Name Bit Sym[...]

  • Page 147

    Rev.1.02 Jul 01, 2005 page 131 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.8 UCON Register and U0SMR to U2SMR Registers b7 b6 b5 b4 b3 b2 b1 b0 Function UART Transmit/Receive Control Register 2 Bit Name Bit Symbol Symb[...]

  • Page 148

    Rev.1.02 Jul 01, 2005 page 132 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.9 U0SMR2 to U2SMR2 Registers and U0SMR3 to U2SMR3 Registers b7 b6 b5 b4 b3 b2 b1 b0 Function UARTi Special Mode Register 2 (i = 0 to 2) Bit Nam[...]

  • Page 149

    Rev.1.02 Jul 01, 2005 page 133 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.10 U0SMR4 to U2SMR4 Registers b7 b6 b5 b4 b3 b2 b1 b0 Function UARTi Special Mode Register 4 (i = 0 to 2) Bit Name Bit Symbol Symbol Address Af[...]

  • Page 150

    Rev.1.02 Jul 01, 2005 page 134 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.1 Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 14.1 lists the s[...]

  • Page 151

    Rev.1.02 Jul 01, 2005 page 135 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Table 14.2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode Register Bit Function UiTB (1) 0 to 7 Set transmission data UiRB (1) 0 [...]

  • Page 152

    Rev.1.02 Jul 01, 2005 page 136 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Table 14.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 14.3 shows pin functions for the case where the m[...]

  • Page 153

    Rev.1.02 Jul 01, 2005 page 137 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.11 Transmit and Receive Operation (1) Example of Transmit Timing (when internal clock is selected) (2) Example of Receive Timing (when external[...]

  • Page 154

    Rev.1.02 Jul 01, 2005 page 138 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.1.1 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in clock synchronous serial I/O m[...]

  • Page 155

    Rev.1.02 Jul 01, 2005 page 139 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.1.3 LSB First/MSB First Select Function Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format. Figure 14.13 shows the tr[...]

  • Page 156

    Rev.1.02 Jul 01, 2005 page 140 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.1.5 Serial Data Logic Switching Function When the UiLCH bit in the UiC1 register (i = 0 to 2) = 1 (reverse), the data written to the UiTB register h[...]

  • Page 157

    Rev.1.02 Jul 01, 2005 page 141 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. _______ _______ 14.1.1.7 CTS/RTS Function _______ ________ ________ When the CTS function is used transmit and receive operation start when “ L ” is [...]

  • Page 158

    Rev.1.02 Jul 01, 2005 page 142 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Item Specification Transfer Data Format • Character bit (transfer data): Selectable from 7, 8 or 9 bits • Start bit: 1 bit • Parity bit: Selectable[...]

  • Page 159

    Rev.1.02 Jul 01, 2005 page 143 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Table 14.6 Registers to Be Used and Settings in UART Mode Register Bit Function UiTB 0 to 8 Set transmission data (1) UiRB 0 to 8 Reception data can be r[...]

  • Page 160

    Rev.1.02 Jul 01, 2005 page 144 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Table 14.7 lists the functions of the input/output pins during UART mode. Table 14.8 lists the P6_4 pin functions during UART mode. Note that for a perio[...]

  • Page 161

    Rev.1.02 Jul 01, 2005 page 145 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. (1) Example of Transmit Timing when Transfer Data is 8-bit Long (parity enabled, one stop bit) (2) Example of Transmit Timing when Transfer Data is 9-bit[...]

  • Page 162

    Rev.1.02 Jul 01, 2005 page 146 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. • Example of Receive Timing when Transfer Data is 8-bit Long (parity disabled, one stop bit) The above timing diagram applies to the case where the reg[...]

  • Page 163

    Rev.1.02 Jul 01, 2005 page 147 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.2.2 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in UART mode, follow the procedur[...]

  • Page 164

    Rev.1.02 Jul 01, 2005 page 148 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.21 TXD and RXD I/O Polarity Inverse 14.1.2.4 Serial Data Logic Switching Function The data written to the UiTB register has its logic reversed [...]

  • Page 165

    Rev.1.02 Jul 01, 2005 page 149 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. _______ _______ 14.1.2.6 CTS/RTS Function _______ ________ ________ When the CTS function is used transmit operation start when “ L ” is applied to t[...]

  • Page 166

    Rev.1.02 Jul 01, 2005 page 150 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.3 Special Mode 1 (I 2 C Mode) I 2 C mode is provided for use as a simplified I 2 C interface compatible mode. Table 14.10 lists the specifications o[...]

  • Page 167

    Rev.1.02 Jul 01, 2005 page 151 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.23 I 2 C Mode Block Diagram CLK control Falling edge detection External clock Internal clock Start/stop condition detection interrupt request S[...]

  • Page 168

    Rev.1.02 Jul 01, 2005 page 152 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Table 14.11 Registers to Be Used and Settings in I 2 C Mode Register Bit Function Master Slave UiTB (1) 0 to 7 Set transmission data UiRB (1) 0 to 7 Rece[...]

  • Page 169

    Rev.1.02 Jul 01, 2005 page 153 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. No acknowledgment detection (NACK) Rising edge of SCLi 9th bit Acknowledgment detection (ACK) Rising edge of SCLi 9th bit Rising edge of SCLi 9th bit L A[...]

  • Page 170

    Rev.1.02 Jul 01, 2005 page 154 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.24 Transfer to UiRB Register and Interrupt Timing i = 0 to 2 This diagram applies to the case where the following condition is met. The CKDIR b[...]

  • Page 171

    Rev.1.02 Jul 01, 2005 page 155 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.3.1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt [...]

  • Page 172

    Rev.1.02 Jul 01, 2005 page 156 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Table 14.13 STSPSEL Bit Functions Figure 14.26 STSPSEL Bit Functions 14.1.3.3 Arbitration Unmatching of the transmit data and SDAi pin input data is chec[...]

  • Page 173

    Rev.1.02 Jul 01, 2005 page 157 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.3.4 Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 14.24. The CSC bit in the UiSMR2 register is use[...]

  • Page 174

    Rev.1.02 Jul 01, 2005 page 158 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.3.7 ACK and NACK If the STSPSEL bit in the UiSMR4 register is set to “ 0 ” (start and stop conditions not generated) and the ACKC bit in the UiS[...]

  • Page 175

    Rev.1.02 Jul 01, 2005 page 159 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.4 Special Mode 2 Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 14.14 lists t[...]

  • Page 176

    Rev.1.02 Jul 01, 2005 page 160 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.27 Serial Bus Communication Control Example (UART2) Microcomputer (Master) Microcomputer (Slave) Microcomputer (Slave) P1_3 P1_2 P7_2(CLK2) P7_[...]

  • Page 177

    Rev.1.02 Jul 01, 2005 page 161 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Table 14.15 Registers to Be Used and Settings in Special Mode 2 Register Bit Function UiTB (1) 0 to 7 Set transmission data UiRB (1) 0 to 7 Reception dat[...]

  • Page 178

    Rev.1.02 Jul 01, 2005 page 162 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.4.1 Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the UiSMR3 r[...]

  • Page 179

    Rev.1.02 Jul 01, 2005 page 163 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.29 Transmission and Reception Timing (CKPH = 0) in Slave Mode (External Clock) Figure 14.30 Transmission and Reception Timing (CKPH = 1) in Sla[...]

  • Page 180

    Rev.1.02 Jul 01, 2005 page 164 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.5 Special Mode 3 (IE Mode) In this mode, one bit of IEBus is approximated with one byte of UART mode waveform. Table 14.16 lists the registers used [...]

  • Page 181

    Rev.1.02 Jul 01, 2005 page 165 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.31 Bus Collision Detect Function-Related Bits (3) SSS Bit in UiSMR Register (transmit start condition select) Transmission enable condition is [...]

  • Page 182

    Rev.1.02 Jul 01, 2005 page 166 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Item Specification Transfer data format • Direct format • Inverse format Transfer clock • The CKDIR bit in the U2MR register = 0 (internal clock) :[...]

  • Page 183

    Rev.1.02 Jul 01, 2005 page 167 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Table 14.18 Registers to Be Used and Settings in SIM Mode Register Bit Function U2TB (1) 0 to 7 Set transmission data U2RB (1) 0 to 7 Reception data can [...]

  • Page 184

    Rev.1.02 Jul 01, 2005 page 168 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.32 Transmit and Receive Timing in SIM Mode The above timing diagram applies to the case where data is received in the direct format. STPS bit i[...]

  • Page 185

    Rev.1.02 Jul 01, 2005 page 169 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.33 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up. Figure 14.33 SIM Interface Connection 14.1.6.1 P[...]

  • Page 186

    Rev.1.02 Jul 01, 2005 page 170 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.6.2 Format When direct format, set the PRY bit in the U2MR register to “ 1 ” , the UFORM bit in the U2C0 register to “ 0 ” and the U2LCH bit[...]

  • Page 187

    Rev.1.02 Jul 01, 2005 page 171 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.2 SI/Oi (i = 3 to 6) (1) SI/Oi is exclusive clock-synchronous serial I/Os. Figure 14.36 shows the block diagram of SI/Oi, and Figures 14.37 and 14.38 [...]

  • Page 188

    Rev.1.02 Jul 01, 2005 page 172 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.37 S3C to S6C Registers, S3BRG to S6BRG Registers, and S3TRR to S6TRR Registers 0 0 : Selecting f1SIO or f2SIO 0 1 : Selecting f8SIO 1 0 : Sele[...]

  • Page 189

    Rev.1.02 Jul 01, 2005 page 173 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.38 S3456TRR Register 0 : During transmission/reception 1 : Transmission/reception completed S3TRF S4TRF S5TRF Symbol S3456TRR Address 01DAh Aft[...]

  • Page 190

    Rev.1.02 Jul 01, 2005 page 174 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Item Specification Transfer Data Format Transfer data length: 8 bits Transfer clock • SMi6 bit in SiC register = 1 (internal clock) : fj/ 2(n+1) fj = f[...]

  • Page 191

    Rev.1.02 Jul 01, 2005 page 175 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.2.1 SI/Oi Operation Timing Figure 14.39 shows the SI/Oi operation timing. Figure 14.39 SI/Oi Operation Timing 14.2.2 CLK Polarity Selection The SMi4 b[...]

  • Page 192

    Rev.1.02 Jul 01, 2005 page 176 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.2.3 Functions for Setting an SOUTi Initial Value If the SMi6 bit in the SiC register = 0 (external clock), the SOUTi pin output can be fixed high or l[...]

  • Page 193

    Rev.1.02 Jul 01, 2005 page 177 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. Item Performance Method of A/D C onversion Successive approximation (capacitive coupling amplifier) Analog Input Voltage (1) 0V to AVCC (VCC) Operatin[...]

  • Page 194

    Rev.1.02 Jul 01, 2005 page 178 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. Figure 15.1 A/D Converter Block Diagram ANEX0 ANEX1 OPA0=1 OPA1=1 ADGSEL1 to ADGSEL0=00b OPA1 to OPA0=11b =000b =001b =010b =011b =100b =101b =110b =1[...]

  • Page 195

    Rev.1.02 Jul 01, 2005 page 179 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. Figure 15.2 ADCON0 Register and ADCON1 Register CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 RW RW RW RW RW RW RW RW SCAN0 SCAN1 MD2 BITS VCUT OPA0 OPA1 CKS1 Fun[...]

  • Page 196

    Rev.1.02 Jul 01, 2005 page 180 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. Figure 15.3 ADCON2 Register, and AD0 to AD7 Registers NOTES: 1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will [...]

  • Page 197

    Rev.1.02 Jul 01, 2005 page 181 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. Item Specification Function T he CH2 to CH0 bits in the ADCON0 register, the ADGSEL1 to ADGSEL0 bits in the ADCON2 register and the OPA1 to OPA0 bits [...]

  • Page 198

    Rev.1.02 Jul 01, 2005 page 182 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. Figure 15.4 ADCON0 Register and ADCON1 Register in One-shot Mode CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 0 0 : One-shot mode (3) 0 : Software trigger 1 : AD[...]

  • Page 199

    Rev.1.02 Jul 01, 2005 page 183 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. 15.1.2 Repeat Mode In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 15.3 lists the specificat[...]

  • Page 200

    Rev.1.02 Jul 01, 2005 page 184 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. Figure 15.5 ADCON0 Register and ADCON1 Register in Repeat Mode CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 RW RW RW RW RW RW RW RW SCAN0 SCAN1 MD2 BITS VCUT OPA[...]

  • Page 201

    Rev.1.02 Jul 01, 2005 page 185 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. 15.1.3 Single Sweep Mode In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital code. Table 15.4 l[...]

  • Page 202

    Rev.1.02 Jul 01, 2005 page 186 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. Figure 15.6 ADCON0 Register and ADCON1 Register in Single Sweep Mode CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 1 0 : Single sweep mode 0 : Software trigger 1 [...]

  • Page 203

    Rev.1.02 Jul 01, 2005 page 187 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. 15.1.4 Repeat Sweep Mode 0 In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital code. Table 15.5 lists[...]

  • Page 204

    Rev.1.02 Jul 01, 2005 page 188 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. Figure 15.7 ADCON0 Register and ADCON1 Register in Repeat Sweep Mode 0 CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 1 1 : Repeat sweep mode 0 or Repeat sweep mod[...]

  • Page 205

    Rev.1.02 Jul 01, 2005 page 189 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. Item Specification Function The input voltages on all pins selected by the ADGSEL1 to ADGSEL0 bits in the ADCON2 register are A/D converted repeatedly[...]

  • Page 206

    Rev.1.02 Jul 01, 2005 page 190 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. Figure 15.8 ADCON0 Register and ADCON1 Register in Repeat Sweep Mode 1 CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 1 1 : Repeat sweep mode 0 or Repeat sweep mod[...]

  • Page 207

    Rev.1.02 Jul 01, 2005 page 191 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. 15.2 Function 15.2.1 Resolution Select Function The desired resolution can be selected using the BITS bit in the ADCON1 register. If the BITS bit is s[...]

  • Page 208

    Rev.1.02 Jul 01, 2005 page 192 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. 15.2.5 Current Consumption Reducing Function When not using the A/D converter, its resistor ladder and reference voltage input pin (VREF) can be separ[...]

  • Page 209

    Rev.1.02 Jul 01, 2005 page 193 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. R0 R (7.8 k Ω ) C (1.5 pF) VIN Microcomputer Sensor equivalent circuit VC Sampling time Sample and hold function enabled: Sample and hold function d[...]

  • Page 210

    Rev.1.02 Jul 01, 2005 page 194 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 16. D/A Converter Under development This document is under development and its contents are subject to change. 16. D/A Converter This is an 8-bit, R-2R type D/A converter. These are two independent D/A converters. D/A conversion is performed by writing to the D[...]

  • Page 211

    Rev.1.02 Jul 01, 2005 page 195 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 16. D/A Converter Under development This document is under development and its contents are subject to change. Figure 16.2 DACON Register, DA0 and DA1 Registers Figure 16.3 D/A Converter Equivalent Circuit D/A Control Register (1) Symbol Address After Reset Sym[...]

  • Page 212

    Rev.1.02 Jul 01, 2005 page 196 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 17. CRC Calculation Under development This document is under development and its contents are subject to change. 17. CRC Calculation The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses a generator polynomial of CR[...]

  • Page 213

    Rev.1.02 Jul 01, 2005 page 197 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 17. CRC Calculation Under development This document is under development and its contents are subject to change. Figure 17.3 CRC Calculation b15 b7 b15 1189h b7 b15 0A41h b0 b0 b0 b0 b0 CRCD register CRCIN register Two cycles later, the CRC code for "80h,&[...]

  • Page 214

    Rev.1.02 Jul 01, 2005 page 198 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18. CAN Module The CAN (Controller Area Network) module for the M16C/6N Group (M16C/6NL, M16C/6NN) of microcomputers is a communication controller implem[...]

  • Page 215

    Rev.1.02 Jul 01, 2005 page 199 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.1 CAN Module-Related Registers The CAN0 module has the following registers. 18.1.1 CAN Message Box A CAN module is equipped with 16 slots (16 bytes or[...]

  • Page 216

    Rev.1.02 Jul 01, 2005 page 200 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.2 CAN0 Message Box Table 18.1 shows the memory mapping of the CAN0 message box. It is possible to access to the message box in byte or word. Mapping o[...]

  • Page 217

    Rev.1.02 Jul 01, 2005 page 201 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. Figures 18.2 and 18.3 show the bit mapping in each slot in byte access and word access. The content of each slot remains unchanged unless transmission or[...]

  • Page 218

    Rev.1.02 Jul 01, 2005 page 202 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. Figure 18.4 Bit Mapping of Mask Registers in Byte Access 18.3 Acceptance Mask Registers Figures 18.4 and 18.5 show the C0GMR register, the C0LMAR registe[...]

  • Page 219

    Rev.1.02 Jul 01, 2005 page 203 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.4 CAN SFR Registers Figures 18.6 to 18.12 show the CAN SFR registers. Figure 18.6 C0MCTLj Register b7 b6 b5 b4 b3 b2 b1 b0 Bit Sy mbo l Bi t Name Func[...]

  • Page 220

    Rev.1.02 Jul 01, 2005 page 204 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. Figure 18.7 C0CTLR Register Function Bit Sy mbol Reset CAN Module Reset Bit (1) Loop Bac k Mode LoopBack Select Bit (2) Message Ord er MsgOrder BasicCAN [...]

  • Page 221

    Rev.1.02 Jul 01, 2005 page 205 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. - (b4-b0) - (b5) - (b6) - (b7) CAN1 Control Reg ister (1) C1CTLR X0000001b 0230h b7 b6 b5 b4 b3 b2 b1 b0 NOTE: 1. Make sure "0020h" is set to t[...]

  • Page 222

    Rev.1.02 Jul 01, 2005 page 206 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. Figure 18.9 C0STR Register (b15) (b8) b7 b6 b5 b4 b3 b2 b1 b0 Reset State Flag Loop Back State Flag Message Order State Flag Basic CAN Mode State Flag Bu[...]

  • Page 223

    Rev.1.02 Jul 01, 2005 page 207 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. Figure 18.10 C0SSTR Register, C0ICR Register and C0IDR Register (b15) (b8) b7 b0 b7 b0 Func tion Slot status bits Each bit corresponds to the slot with t[...]

  • Page 224

    Rev.1.02 Jul 01, 2005 page 208 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. Figure 18.11 C0CONR Register b7 b6 b5 b4 b3 b2 b1 b0 0 : O ne time sampling 1 : Three times sampling 0 0 0 0 : Divide-by-1 of fCAN 0 0 0 1 : Divide-by-2 [...]

  • Page 225

    Rev.1.02 Jul 01, 2005 page 209 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. Figure 18.12 C0RECR Register, C0TECR Register, C0TSR Register and C0AFS Register Reception error counting function The value is incremented or decremente[...]

  • Page 226

    Rev.1.02 Jul 01, 2005 page 210 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.5 Operational Modes The CAN module has the following four operational modes. • CAN Reset/Initialization Mode • CAN Operation Mode • CAN Sleep Mo[...]

  • Page 227

    Rev.1.02 Jul 01, 2005 page 211 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.5.2 CAN Operation Mode The CAN operation mode is activated by setting the Reset bit in the C0CTLR register to “ 0 ” . If the Reset bit is set to ?[...]

  • Page 228

    Rev.1.02 Jul 01, 2005 page 212 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.5.5 Bus Off State The bus off state is entered according to the fault confinement rules of the CAN specification. When returning to the CAN operation [...]

  • Page 229

    Rev.1.02 Jul 01, 2005 page 213 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.6 Configuration CAN Module System Clock The M16C/6N Group (M16C/6NL, M16C/6NN) has a CAN module system clock select circuit. Configuration of the CAN [...]

  • Page 230

    Rev.1.02 Jul 01, 2005 page 214 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.8 Bit-rate Bit-rate depends on f1, the division value of the CAN module system clock, the division value of the baud rate prescaler, and the number of[...]

  • Page 231

    Rev.1.02 Jul 01, 2005 page 215 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. Figure 18.17 Correspondence of Mask Registers to Slots Figure 18.18 Acceptance Function When using the acceptance function, note the following points. (1[...]

  • Page 232

    Rev.1.02 Jul 01, 2005 page 216 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.10 Acceptance Filter Support Unit (ASU) The acceptance filter support unit has a function to judge valid/invalid of a received ID through table search[...]

  • Page 233

    Rev.1.02 Jul 01, 2005 page 217 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.11 Basic CAN Mode When the BasicCAN bit in the C0CTLR register is set to “ 1 ” (Basic CAN mode enabled), slots 14 and 15 correspond to Basic CAN m[...]

  • Page 234

    Rev.1.02 Jul 01, 2005 page 218 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.12 Return from Bus Off Function When the protocol controller enters bus off state, it is possible to make it forced return from bus off state by setti[...]

  • Page 235

    Rev.1.02 Jul 01, 2005 page 219 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.15 Reception and Transmission Table 18.3 shows configuration of CAN reception and transmission mode. Table 18.3 Configuration of CAN Reception and Tra[...]

  • Page 236

    Rev.1.02 Jul 01, 2005 page 220 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.15.1 Reception Figure 18.21 shows the behavior of the module when receiving two consecutive CAN messages, that fit into the slot of the shown C0MCTLj [...]

  • Page 237

    Rev.1.02 Jul 01, 2005 page 221 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.15.2 Transmission Figure 18.22 shows the timing of the transmit sequence. CTX TrmRe q bit TrmAc ti ve bit CAN0 Successful Transmission Interrupt TrmSt[...]

  • Page 238

    Rev.1.02 Jul 01, 2005 page 222 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.16 CAN Interrupt The CAN module provides the following CAN interrupts. • CAN0 Successful Reception Interrupt • CAN0 Successful Transmission Interr[...]

  • Page 239

    Rev.1.02 Jul 01, 2005 page 223 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change. 19. Programmable I/O Ports The programmable input/output ports (hereafter referred to simply as I/O ports) consist of 87 lines P0 to P10 in t[...]

  • Page 240

    Rev.1.02 Jul 01, 2005 page 224 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change. 19.1 PDi Register (100-pin Version: i = 0 to 10, 128-pin Version: i = 0 to 13) Figure19.7 shows the PDi register. This register selects wheth[...]

  • Page 241

    Rev.1.02 Jul 01, 2005 page 225 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure19.1 I/O Ports (1) NOTES: 1. Symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed VCC. 2. P11 to P14 [...]

  • Page 242

    Rev.1.02 Jul 01, 2005 page 226 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure19.2 I/O Ports (2) "1" Output Data bus Direction register Port latch Pull-up selection (NOTE 1) Input to respective periphera[...]

  • Page 243

    Rev.1.02 Jul 01, 2005 page 227 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure19.3 I/O Ports (3) Data bus Pull-up selection Direction register Port latch Input to respective peripheral functions Switching between [...]

  • Page 244

    Rev.1.02 Jul 01, 2005 page 228 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Data bus Direction register Pull-up selection Port latch Analog input Input to respective peripheral functions (NOTE 1) D/A output enabled An[...]

  • Page 245

    Rev.1.02 Jul 01, 2005 page 229 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure19.5 I/O Ports (5) Figure19.6 I/O Pins fC Rf Rd Data bus Direction register Pull-up selection Port latch "1" Output Direction[...]

  • Page 246

    Rev.1.02 Jul 01, 2005 page 230 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure19.7 PD0 to PD13 Registers Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Port Pi Dire[...]

  • Page 247

    Rev.1.02 Jul 01, 2005 page 231 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure19.8 P0 to P13 Registers and PC14 Register Port P8 Register Bit name Bit symbol RW b7 b6 b5 b4 b3 b2 b1 b0 P8 03F0h Indeterminate Symbo[...]

  • Page 248

    Rev.1.02 Jul 01, 2005 page 232 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Pull-up Control Register 0 Bit Name Bit Symbol RW b7 b6 b5 b4 b3 b2 b1 b0 PUR0 03FCh 00h Symbol Address After Reset NOTE: 1. The pin for whic[...]

  • Page 249

    Rev.1.02 Jul 01, 2005 page 233 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure19.10 PUR3 Register Pull-up Control Register 3 (128-pin version) Bit Name Bit Symbol RW b7 b6 b5 b4 b3 b2 b1 b0 PUR3 03DFh 00h Symbol A[...]

  • Page 250

    Rev.1.02 Jul 01, 2005 page 234 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Table 19.2 Unassigned Pin Handling Pin Name Connection Ports P0 to P7, P8_0 to P8_4, P8_6, P8_7, P9 to P14 (5) XOUT (4) _______ NMI(P8_5) AVC[...]

  • Page 251

    Rev.1.02 Jul 01, 2005 page 235 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20. Flash Memory Version Aside from the built-in flash memory, the flash memory version microcomputer has the same functions as the masked ROM[...]

  • Page 252

    Rev.1.02 Jul 01, 2005 page 236 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.1 Memory Map The flash memory contains the user ROM area and a boot ROM area. The user ROM area has space to store the microcomputer operat[...]

  • Page 253

    Rev.1.02 Jul 01, 2005 page 237 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.1.1 Boot Mode The microcomputer enters boot mode when a hardware reset occurs while an “ H ” signal is applied to the CNVSS and P5_0 pi[...]

  • Page 254

    Rev.1.02 Jul 01, 2005 page 238 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 20.2 ROMCP Register Figure 20.3 Address for ID Code Stored ROM Code Protect Control Address Symbol Address Value when Shipped ROMCP 0FF[...]

  • Page 255

    Rev.1.02 Jul 01, 2005 page 239 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Item EW0 Mode EW1 Mode Operation Mode • Single chip mode Single chip mode • Boot mode Space where Rewrite • User ROM area User ROM area [...]

  • Page 256

    Rev.1.02 Jul 01, 2005 page 240 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.3.1 EW0 Mode The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “ 1 ” (CPU rewrite mode enabled[...]

  • Page 257

    Rev.1.02 Jul 01, 2005 page 241 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 20.4 FMR0 Register and FMR1 Register Flash Memory Control Register 0 Symbol Address After Reset FMR0 01B7h 00000001b b7 b6 b5 b4 b3 b2 [...]

  • Page 258

    Rev.1.02 Jul 01, 2005 page 242 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.3.3.1 FMR00 Bit This bit indicates the flash memory operating status. It is set to “ 0 ” while the program, block erase, erase all unlo[...]

  • Page 259

    Rev.1.02 Jul 01, 2005 page 243 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 20.6 Setting and Resetting of EW1 Mode Figure 20.5 Setting and Resetting of EW0 Mode Procedure to enter EW0 mode Set CM0, CM1, and PM1 [...]

  • Page 260

    Rev.1.02 Jul 01, 2005 page 244 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 20.7 Processing Before and After Low Power Dissipation Mode Transfer a low power dissipation mode program to a space other the flash me[...]

  • Page 261

    Rev.1.02 Jul 01, 2005 page 245 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.3.4 Precautions on CPU Rewrite Mode 20.3.4.1 Operating Speed Set the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 regi[...]

  • Page 262

    Rev.1.02 Jul 01, 2005 page 246 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.3.4.9 Writing Command and Data Write commands and data to even addresses in the user ROM area. 20.3.4.10 Wait Mode When entering wait mode,[...]

  • Page 263

    Rev.1.02 Jul 01, 2005 page 247 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.3.5 Software Commands Software commands are described below. The command code and data must be read and written in 16-bit unit, to and from[...]

  • Page 264

    Rev.1.02 Jul 01, 2005 page 248 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 20.8 Program Command 20.3.5.4 Program Command (40h) The program command writes 2-byte data to the flash memory. By writing “ xx40h ?[...]

  • Page 265

    Rev.1.02 Jul 01, 2005 page 249 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 20.9 Block Erase Command 20.3.5.5 Block Erase Command The block erase command erases each block. By writing “ xx20h ” in the first [...]

  • Page 266

    Rev.1.02 Jul 01, 2005 page 250 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.3.5.6 Erase All Unlocked Block The erase all unlocked block command erases all blocks except the block A. By writing “ xxA7h ” in the f[...]

  • Page 267

    Rev.1.02 Jul 01, 2005 page 251 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.3.5.8 Read Lock Bit Status Command (71h) The read lock bit status command reads the lock bit state of a specified block. By writing “ xx7[...]

  • Page 268

    Rev.1.02 Jul 01, 2005 page 252 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.3.6 Data Protect Function Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02 bit in th[...]

  • Page 269

    Rev.1.02 Jul 01, 2005 page 253 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Table 20.5 Status Register SR7 (D7) SR6 (D6) SR5 (D5) SR4 (D4) SR3 (D3) SR2 (D2) SR1 (D1) SR0 (D0) Sequencer status Reserved Erase status Prog[...]

  • Page 270

    Rev.1.02 Jul 01, 2005 page 254 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. FRM00 Register (Status Register) Status Error Error Occurrence Conditions FMR07 bit FMR06 bit (SR5) (SR4) 1 1 Command • Command is written i[...]

  • Page 271

    Rev.1.02 Jul 01, 2005 page 255 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 20.12 Full Status Check and Handling Procedure for Each Error Full status check FMR06 =1 and FMR07=1? NO YES FMR07=0? YES NO FMR06=0? Y[...]

  • Page 272

    Rev.1.02 Jul 01, 2005 page 256 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.4 Standard Serial I/O Mode In standard serial I/O mode, the serial programmer supporting the M16C/6N Group (M16C/6NL, M16C/ 6NN) can be use[...]

  • Page 273

    Rev.1.02 Jul 01, 2005 page 257 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Table 20.7 Pin Functions for Standard Serial I/O Mode NOTES: 1. ___________ When using standard serial I/O mode 1, the TXD pin must be held hi[...]

  • Page 274

    Rev.1.02 Jul 01, 2005 page 258 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 20.13 Pin Connections for Standard Serial I/O Mode (1) CNVSS RESET VSS VCC1 VCC2 TXD SCLK EPM CE RXD BUSY M16C/6N Group (M16C/6NL) (Fla[...]

  • Page 275

    Rev.1.02 Jul 01, 2005 page 259 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 20.14 Pin Connections for Standard Serial I/O Mode (2) 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 2 2 32 42 52 62 72 82 93[...]

  • Page 276

    Rev.1.02 Jul 01, 2005 page 260 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.4.2 Example of Circuit Application in Standard Serial I/O Mode Figures 20.15 and 20.16 show example of circuit application in standard seri[...]

  • Page 277

    Rev.1.02 Jul 01, 2005 page 261 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.5 Parallel I/O Mode In parallel I/O mode, the user ROM area and the boot ROM area can be rewritten by a parallel programmer supporting the [...]

  • Page 278

    Rev.1.02 Jul 01, 2005 page 262 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.6 CAN I/O Mode In CAN I/O mode, the CAN programmer supporting the M16C/6N Group (M16C/6NL, M16C/6NN) can be used to rewrite the flash memor[...]

  • Page 279

    Rev.1.02 Jul 01, 2005 page 263 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 20.17 Pin Connections for CAN I/O Mode (1) CNVSS RESET CTX CRX VSS VCC1 VCC2 SCLK EPM CE M16C/6N Group (M16C/6NL) (Flash memory version[...]

  • Page 280

    Rev.1.02 Jul 01, 2005 page 264 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 20.18 Pin Connections for CAN I/O Mode (2) 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 2 2 32 42 52 62 72 82 93 0 73 74 75 76 77 78 79 [...]

  • Page 281

    Rev.1.02 Jul 01, 2005 page 265 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.6.2 Example of Circuit Application in CAN I/O Mode Figure 20.19 shows example of circuit application in CAN I/O mode. Refer to the user ’[...]

  • Page 282

    Rev.1.02 Jul 01, 2005 page 266 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change. 21. Electrical Characteristics Table 21.1 Absolute Maximum Ratings NOTE: 1. Ports P11 to P14 are only in the 128-pin version. V CC AV CC V [...]

  • Page 283

    Rev.1.02 Jul 01, 2005 page 267 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change. Table 21.2 Recommended Operating Conditions (1) (1) Supply Voltage (VCC1 = VCC2) Analog Supply Voltage Supply Voltage Analog Supply Voltage[...]

  • Page 284

    Rev.1.02 Jul 01, 2005 page 268 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change. Table 21.3 Recommended Operating Conditions (2) (1) Main Clock Input Oscillation No W a i t Mask ROM Version VCC = 3.0 to 5.5V Frequency (2[...]

  • Page 285

    Rev.1.02 Jul 01, 2005 page 269 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change. Table 21.4 Electrical Characteristics (1) (1) V CC -2.0 V CC -0.3 3.0 3.0 0.2 0.2 0.2 30 2.0 2.5 1.6 0 0 50 1.5 15 HIGH Output Voltage HIGH[...]

  • Page 286

    Rev.1.02 Jul 01, 2005 page 270 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change. Table 21.5 Electrical Characteristics (2) (1) Mask ROM f(BCLK) = 24MHz, PLL operation, No division On-chip oscillation, No division Flash M[...]

  • Page 287

    Rev.1.02 Jul 01, 2005 page 271 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change. Resolution Integral 10 bits Nonlinearity Error 8 bits Absolute 10 bits Accuracy 8 bits Differential Nonl inearity Error Offset Error Gain E[...]

  • Page 288

    Rev.1.02 Jul 01, 2005 page 272 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change. 2 150 150 ms µs µs Time for Internal Power Supply Stabilization During Powering-On STOP Release Time Low Power Dissipation Mode Wait Mode[...]

  • Page 289

    Rev.1.02 Jul 01, 2005 page 273 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change. 15 15 ns ns ns ns ns External Clock Input Cycle Time External Clock Input HIGH Pulse Width External Clock Input LOW Pulse Width External Cl[...]

  • Page 290

    Rev.1.02 Jul 01, 2005 page 274 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change. ns ns ns ns ns ns TBiIN Input Cycle Time (counted on one edge) TBiIN Input HIGH Pulse Width (counted on one edge) TBiIN Input LOW Pulse Wid[...]

  • Page 291

    Rev.1.02 Jul 01, 2005 page 275 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change. Figure 21.3 Timing Diagram t su(D — C) CLKi TXDi RXDi t c(CK) t w(CKH) t w(CKL) t w(INL) t w(INH) t d(C — Q) t h(C — D) t h(C — Q) [...]

  • Page 292

    Rev.1.02 Jul 01, 2005 page 276 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22. Usage Precaution 22.1 SFR There is the SFR which can not be read (containg bits that will result in unknown data when read). Please set these r[...]

  • Page 293

    Rev.1.02 Jul 01, 2005 page 277 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.2 External Clock Do not stop the external clock when it is connected to the XIN pin and the main clock is selected as the CPU clock.[...]

  • Page 294

    Rev.1.02 Jul 01, 2005 page 278 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.3 PLL Frequency Synthesizer Stabilize supply voltage so that the standard of the power supply ripple is met. (Refer to 21. Electrical characteri[...]

  • Page 295

    Rev.1.02 Jul 01, 2005 page 279 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.4 Power Control ____________ When exiting stop mode by hardware reset, set RESET pin to “ L ” until a main clock oscillation is stabilized. [...]

  • Page 296

    Rev.1.02 Jul 01, 2005 page 280 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. Suggestions to reduce power consumption. Ports The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A c[...]

  • Page 297

    Rev.1.02 Jul 01, 2005 page 281 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.5 Oscillation Stop, Re-oscillation Detection Function If the following conditions are all met, the following restriction occur in operation of o[...]

  • Page 298

    Rev.1.02 Jul 01, 2005 page 282 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.6 Protection Set the PRC2 bit to “ 1 ” (write enabled) and then write to any address, and the PRC2 bit will be set to “ 0 ” (write prote[...]

  • Page 299

    Rev.1.02 Jul 01, 2005 page 283 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.7 Interrupt 22.7.1 Reading Address 00000h Do not read the address 00000h in a program. When a maskable interrupt request is accepted, the CP U r[...]

  • Page 300

    Rev.1.02 Jul 01, 2005 page 284 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.7.4 Changing Interrupt Generate Factor If the interrupt generate factor is changed, the IR bit of the interrupt control register for the changed[...]

  • Page 301

    Rev.1.02 Jul 01, 2005 page 285 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.7.6 Rewrite Interrupt Control Register (a ) The interrupt control register for any interrupt should be modified in places where no interrupt req[...]

  • Page 302

    Rev.1.02 Jul 01, 2005 page 286 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.8 DMAC 22.8.1 Write to DMAE Bit in DMiCON Register (i = 0, 1) When both of the conditions below are met, follow the steps below. Conditions • [...]

  • Page 303

    Rev.1.02 Jul 01, 2005 page 287 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.9 Timers 22.9.1 Timer A 22.9.1.1 Timer A (Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using [...]

  • Page 304

    Rev.1.02 Jul 01, 2005 page 288 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.9.1.2 Timer A (Event Counter Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to[...]

  • Page 305

    Rev.1.02 Jul 01, 2005 page 289 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.9.1.3 Timer A (One-shot Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 t[...]

  • Page 306

    Rev.1.02 Jul 01, 2005 page 290 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.9.1.4 Timer A (Pulse Width Modulation Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR [...]

  • Page 307

    Rev.1.02 Jul 01, 2005 page 291 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.9.2 Timer B 22.9.2.1 Timer B (Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i[...]

  • Page 308

    Rev.1.02 Jul 01, 2005 page 292 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.9.2.3 Timer B (Pulse Period/pulse Width Measurement Mode) The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR ([...]

  • Page 309

    Rev.1.02 Jul 01, 2005 page 293 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.10 Thee-Phase Motor Control Timer Function If there is a possibility that you may write data to TAi-1 register (i = 1, 2, 4) near Timer B2 overf[...]

  • Page 310

    Rev.1.02 Jul 01, 2005 page 294 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.11 Serial I/O 22.11.1 Clock Synchronous Serial I/O Mode 22.11.1.1 Transmission/reception _______ ________ With an external clock selected, and c[...]

  • Page 311

    Rev.1.02 Jul 01, 2005 page 295 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.11.2 Special Modes 22.11.2.1 Special Mode 1 (I 2 C Mode) When generating start, stop and restart conditions, set the STSPSEL bit in the UiSMR4 r[...]

  • Page 312

    Rev.1.02 Jul 01, 2005 page 296 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.11.3 SI/Oi (i = 3 to 6) (1) The SOUTi default value which is set to the SOUTi pin by the SMi7 in the SiC register bit approximately 10ns may be [...]

  • Page 313

    Rev.1.02 Jul 01, 2005 page 297 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.12 A/D Converter Set the ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before a trigger occurs). When the V[...]

  • Page 314

    Rev.1.02 Jul 01, 2005 page 298 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. If the CPU reads the ADi register at the same time the conversion result is stored in the ADi register after completion of A/D conversion, an incor[...]

  • Page 315

    Rev.1.02 Jul 01, 2005 page 299 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.13 CAN Module 22.13.1 Reading C0STR Register The CAN module on the M16C/6N Group (M16C/6NL, M16C/6NN) updates the status of the C0STR register i[...]

  • Page 316

    Rev.1.02 Jul 01, 2005 page 300 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. Figure 22.5 When Updating Period of CAN Module Matches Access Period from CPU fCAN ✕ : When the CAN module ’ s State_Reset bit updating period [...]

  • Page 317

    Rev.1.02 Jul 01, 2005 page 301 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.13.2 Performing CAN Configuration If the Reset bit in the C0CTLR register is changed from “ 0 ” (operation mode) to “ 1 ” (reset/initial[...]

  • Page 318

    Rev.1.02 Jul 01, 2005 page 302 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.13.3 Suggestions to Reduce Power Consumption When not performing CAN communication, the operation mode of CAN transceiver should be set to “ s[...]

  • Page 319

    Rev.1.02 Jul 01, 2005 page 303 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.13.4 CAN Transceiver in Boot Mode When programming the flash memory in boot mode via CAN bus, the operation mode of CAN transceiver should be se[...]

  • Page 320

    Rev.1.02 Jul 01, 2005 page 304 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.14 Programmable I/O Ports _______ If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase ___[...]

  • Page 321

    Rev.1.02 Jul 01, 2005 page 305 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.15 Dedicated Input Pin When dedicated input pin voltage is larger than VCC pin voltage, latch up occurs. When different power supplied to the sy[...]

  • Page 322

    Rev.1.02 Jul 01, 2005 page 306 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.16 Electric al Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers Flash memory version and mask ROM version may[...]

  • Page 323

    Rev.1.02 Jul 01, 2005 page 307 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.17 Mask ROM Version When using the masked ROM version, write nothing to internal ROM area.[...]

  • Page 324

    Rev.1.02 Jul 01, 2005 page 308 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.18 Flash Memory Version 22.18.1 Functions to Prevent Flash Memory from Rewriting ID codes are stored in addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FF[...]

  • Page 325

    Rev.1.02 Jul 01, 2005 page 309 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.18.8 Operation Speed Set the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to clock frequency of 10 MHz or less bef[...]

  • Page 326

    Rev.1.02 Jul 01, 2005 page 310 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.19 Flash Memory Programming Using Boot Program When programming the internal flash memory using boot program, be careful about the pins state an[...]

  • Page 327

    Rev.1.02 Jul 01, 2005 page 311 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.20 Noise Connect a bypass capacitor (approximately 0.1 µF) across the VCC1 and VSS pins, and VCC2 and VSS pins using the shortest and thicker p[...]

  • Page 328

    Rev.1.02 Jul 01, 2005 page 312 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) Appendix 1. Package Dimensions Under development This document is under development and its contents are subject to change. Appendix 1. Package Dimensions Terminal cross section b 1 c 1 b p c 2. 1. DIMENSIONS " * 1" AND " * 2" DO NOT INCLUDE[...]

  • Page 329

    Rev.1.02 Jul 01, 2005 page 313 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) Register Index Under development This document is under development and its contents are subject to change. Register Index A AD0 to AD7 ................................... 180 ADCON0 .... 179,182,184,186,188,190 ADCON1 .... 179,182,184,186,188,190 ADCON2 ......[...]

  • Page 330

    Rev.1.02 Jul 01, 2005 page 314 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) Register Index Under development This document is under development and its contents are subject to change. U0C1 to U2C1 ............................... 130 U0MR to U2MR ............................. 129 U0RB to U2RB .............................. 128 U0SMR to [...]

  • Page 331

    REVISION HISTORY M16C/6N Group ( M16C/6NL, M16C/6NN) Hardware Manual Rev . Date Description Page Summary C-1 1.00 Sep. 30, 2004 1.01 Nov. 01, 2004 1.02 Jul. 01, 2005 – First edition issued – Revised edition issued * Revised parts and revised contents are as follows (except for expressional change). 267 Table 21.2 Recommended Operating Condition[...]

  • Page 332

    REVISION HISTORY M16C/6N Group ( M16C/6NL, M16C/6NN) Hardware Manual Rev . Date Description Page Summary C-2 229 Figure 19.6 I/O Pins: NOTE 1 is deleted. 269 Table 21.4 Electrical Characteristics (1) • Measuring Condition of V OL is revised from “L OL = –200µA ” to “L OL = 200µA ”. 270 Table 21.5 Electrical Characteristics (2): Mask R[...]

  • Page 333

    M16C/6N Group (M16C/6NL, M16C/6NN) Hardware Manual Publication Data : Rev.1.00 Sep 30, 2004 Rev.1.02 Jul 01, 2005 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.[...]

  • Page 334

    M16C/6N Group (M16C/6NL, M16C/6NN) Hardware Manual 2- 6 -2, Ote-machi, Chiyoda-ku, Tokyo, 1 00-0004, Japan[...]