Renesas M32R-FPU manual

RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R-FPU 32 Rev. 1.01 Revision date: Oct 31, 2003 Software Manual www.renesas.com Before using this material, please visit our website to confirm that this is the most current document available. REJ09B0112-0101Z[...]

Keep safety first in your circuit designs! Notes regarding these materials • Renesas T echnology Corporation puts the maximum ef fort into making semiconductor prod- ucts better and more reliable, but there is always the possibility that trouble may occur with them. T rouble with semiconductors may lead to personal injury , fire or property damag[...]

REVISION HISTORY Rev . Date Description Page Summary M32R-FPU Software Manual 1.00 Jan 08, 2003 First edition issued – 1.01 Oct 31, 2003 Hexadecimal Instruction Code Table corrected (BTST instruction) APPENDICES-3 Appendix Figure 3.1.1 corrected Incorrect) *The E1 stage of the FDIV instruction requires 13 cycles. Correct) *The E1 stage of the FDI[...]

M32R-FPU Software Manual (Rev.1.01) (1) T able of contents CHAPTER 1 CPU PROGRAMMING MODEL 1.1 CPU register .......................................................................................................... 1-2 1.2 General-purpose registers ...................................................................................... 1-2 1.3 Contro[...]

M32R-FPU Software Manual (Rev.1.01) CHAPTER 3 INSTRUCTIONS 3.1 Conventions for instruction description ................................................................... 3-2 3.2 Instruction description ............................................................................................. 3-5 APPENDIX Appendix 1 Hexadecimal Instraction Code [...]

M32R-FPU Software Manual (Rev.1.01) This page left blank intentionally.[...]

CHAPTER 1 CPU PROGRAMMIING MODEL 1.1 CPU Register 1.2 General-purpose Registers 1.3 Control Registers 1.4 Accumulator 1.5 Program Counter 1.6 Data Format 1.7 Addressing Mode[...]

1 1-2 M32R-FPU Software Manual (Rev.1.01) b0 b0 CPU PROGRAMMING MODEL 1.1 CPU Register 1.1 CPU Register The M32R family CPU, with a built-in FPU (herein referred to as M32R-FPU) has 16 general-purpose registers, 6 control registers, an accumulator and a program counter. The accumulator is of 56-bit configuration, and all other registers are a 32- b[...]

1 1-3 M32R-FPU Software Manual (Rev.1.01) CRn b31 b0 CPU PROGRAMMING MODEL 1.3 Control Registers 1.3 Control Registers There are 6 control registers which are the Processor Status Word Register (PSW), the Condition Bit Register (CBR), the Interrupt Stack Pointer (SPI), the User Stack Pointer (SPU), the Backup PC (BPC) and the Floating-point Status [...]

1 1-4 M32R-FPU Software Manual (Rev.1.01) CPU PROGRAMMING MODEL 1.3 Control Registers The Processor Status Word Register (PSW) indicates the M32R-FPU status. It consists of the current PSW field which is regularly used, and the BPSW field where a copy of the PSW field is saved when EIT occurs. The PSW field consists of the Stack Mode (SM) bit, the [...]

1 1-5 M32R-FPU Software Manual (Rev.1.01) b0 CPU PROGRAMMING MODEL 1.3 Control Registers 1.3.2 Condition Bit Register: CBR (CR1) The Condition Bit Register (CBR) is derived from the PSW register by extracting its Condition (C) bit. The value written to the PSW register's C bit is reflected in this register. The register can only be read. (Writ[...]

1 1-6 M32R-FPU Software Manual (Rev.1.01) CPU PROGRAMMING MODEL 1.3 Control Registers <At reset release: H0000 0100> b Bit Name Function R W 0 FS Reflects the logical sum of FU, FZ, FO and FV. R – Floating-point Exception Summary Bit 1 FX Set to "1" when an inexact exception occurs R W Inexact Exception Flag (if EIT processing is [...]

1 1-7 M32R-FPU Software Manual (Rev.1.01) CPU PROGRAMMING MODEL 1.3 Control Registers 21 EV 0: Mask EIT processing to be executed when an R W Invalid Operation Exception invalid operation exception occurs Enable Bit 1: Execute EIT processing when an invalid operation exception occurs 22 No function assigned. Fix to "0". 0 0 23 DN 0: Handl[...]

1 1-8 M32R-FPU Software Manual (Rev.1.01) CPU PROGRAMMING MODEL 1.3 Control Registers 1.3.6 Floating-point Exceptions (FPE) Floating-point Exception (FPE) occurs when Unimplemented Exception (UIPL) or one of the five exceptions specified in the IEEE754 standard (OVF/UDF/IXCT/ DIV0/IVLD) is detected. Each exception processing is outlined below. (1) [...]

1 1-9 M32R-FPU Software Manual (Rev.1.01) CPU PROGRAMMING MODEL 1.3 Control Registers (3) Inexact Exception (IXCT) The exception occurs when the operation result differs from a result led out with an infinite range of precision. The following table shows the operation results and the respective conditions in which each IXCT occurs. Operation Result[...]

1 1-10 M32R-FPU Software Manual (Rev.1.01) CPU PROGRAMMING MODEL 1.3 Control Registers (5) Invalid Operation Exception (IVLD) The exception occurs when an invalid operation is executed. The following table shows the operation results and the respective conditions in which each IVLD occurs. Occurrence Condition Operation Result (Content of the Desti[...]

1 1-11 M32R-FPU Software Manual (Rev.1.01) CPU PROGRAMMING MODEL 1.4 Accumulator 1.4 Accumulator The Accumulator (ACC) is a 56-bit register used for DSP function instructions. The accumulator is handled as a 64-bit register when accessed for read or write. When reading data from the accumulator, the value of bit 8 is sign-extended. When writing dat[...]

1 1-12 M32R-FPU Software Manual (Rev.1.01) 1.6 Data Format 1.6.1 Data Type The data types that can be handled by the M32R-FPU instruction set are signed or unsigned 8, 16, and 32-bit integers and single-precision floating-point numbers. The signed integers are represented by 2's complements. CPU PROGRAMMING MODEL 1.6 Data Format b7 b0 signed b[...]

1 1-13 M32R-FPU Software Manual (Rev.1.01) 1.6.2 Data Format (1) Data format in a register The data sizes in the M32R-FPU registers are always words (32 bits). When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign-extended ( LDB , LDH instructions) or zero-extended ( LDUB , LDUH instructions) to a word (3[...]

1 1-14 M32R-FPU Software Manual (Rev.1.01) (2) Data format in memory The data sizes in memory can be byte (8 bits), halfword (16 bits) or word (32 bits). Although byte data can be located at any address, halfword and word data must be located at the addresses aligned with a halfword boundary (least significant address bit = "0") or a word[...]

1 1-15 M32R-FPU Software Manual (Rev.1.01) 1.7 Addressing Mode M32R-FPU supports the following addressing modes. (1) Register direct [R or CR] The general-purpose register or the control register to be processed is specified. (2) Register indirect [@R] The contents of the register specify the address of the memory. This mode can be used by all load[...]

1 1-16 M32R-FPU Software Manual (Rev.1.01) CPU PROGRAMMING MODEL 1.7 Addressing Mode This page left blank intentionally.[...]

CHAPTER 2 INSTRUCTION SET 2.1 Instruction set overview 2.2 Instruction format[...]

2 2-2 M32R-FPU Software Manual (Rev.1.01) 2.1 Instruction set overview The M32R-FPU has a total of 100 instructions. The M32R-FPU has a RISC architecture. Memory is accessed by using the load/store instructions and other operations are executed by using register-to-register operation instructions. M32R CPU supports compound instructions such as &qu[...]

2 2-3 M32R-FPU Software Manual (Rev.1.01) INSTRUCTION SET 2.1 Instruction set overview Three types of addressing modes can be specified for load/store instructions. (1) Register indirect The contents of the register specify the address. This mode can be used by all load/ store instructions. (2) Register relative indirect (The contents of the regist[...]

2 2-4 M32R-FPU Software Manual (Rev.1.01) 2.1.2 Transfer instructions The transfer instructions carry out data transfers between registers or a register and an immediate value. LD24 Load 24-bit immediate LDI Load immediate MV Move register MVFC Move from control register MVTC Move to control register SETH Set high-order 16-bit 2.1.3 Operation instr[...]

2 2-5 M32R-FPU Software Manual (Rev.1.01) • logic operation instructions AND AND AND3 AND 3-operand NOT Logical NOT OR OR OR3 OR 3-operand XOR Exclusive OR XOR3 Exclusive OR 3-operand • multiply/divide instructions DIV Divide DIVU Divide unsigned MUL Multiply REM Remainder REMU Remainder unsigned • shift instructions SLL Shift left logical SL[...]

2 2-6 M32R-FPU Software Manual (Rev.1.01) 2.1.4 Branch instructions The branch instructions are used to change the program flow. BC Branch on C-bit BEQ Branch on equal to BEQZ Branch on equal to zero BGEZ Branch on greater than or equal to zero BGTZ Branch on greater than zero BL Branch and link BLEZ Branch on less than or equal to zero BLTZ Branch[...]

2 2-7 M32R-FPU Software Manual (Rev.1.01) The addressing mode of the BRA , BL , BC and BNC instructions can specify an 8-bit or 24-bit immediate value. The addressing mode of the BEQ , BNE , BEQZ , BNEZ , BLTZ , BGEZ , BLEZ , and BGTZ instructions can specify a 16-bit immediate value. In the JMP and JL instructions, the register value becomes the b[...]

2 2-8 M32R-FPU Software Manual (Rev.1.01) 2.1.5 EIT-related instructions The EIT-related instructions carry out the EIT events (Exception, Interrupt and Trap). Trap initiation and return from EIT are EIT-related instructions. TRAP Trap RTE Return from EIT 2.1.6 DSP function instructions The DSP function instructions carry out multiplication of 32 b[...]

2 2-9 M32R-FPU Software Manual (Rev.1.01) Fig. 2.1.2 DSP function instruction operation 1 (multiply, multiply and accumulate) Rsrc1 01 5 1 6 3 1 H ACC 06 3 L 01 5 1 6 3 1 H L x x MULLO instruction MULHI instruction Rsrc2 Rsrc1 03 1 ACC 06 3 01 5 1 6 3 1 HL x x MUL WLO instruction MUL WHI instruction Rsrc2 32 bits Rsrc1 01 5 1 6 3 1 H L 01 5 1 6 3 1[...]

2 2-10 M32R-FPU Software Manual (Rev.1.01) ACC 06 3 sign 0 RAC instruction ACC 06 3 sign 0 RACH instruction < word size round off > < halfword size round off > data data 06 3 06 3 Note: The actual operation is processed in two steps. Refer to Chapter 3 for details . Fig. 2.1.4 DSP function instruction operation 3 (transfer between accum[...]

2 2-11 M32R-FPU Software Manual (Rev.1.01) INSTRUCTION SET 2.1 Instruction set overview 2.1.7 Floating-point Instructions The following instructions execute floating-point operations. FADD Floating-point add FSUB Floating-point subtract FMUL Floating-point multiply FDIV Floating-point divede FMADD Floating-point multiply and add FMSUB Floating-poin[...]

2 2-12 M32R-FPU Software Manual (Rev.1.01) 2.2 Instruction format There are two major instruction formats: two 16-bit instructions packed together within a word boundary, and a single 32-bit instruction (see Figure 2.2.1 ). Figure 2.2.2 shows the instruction format of M32R CPU. Fig. 2.2.2 Instruction format of M32R CPU Fig. 2.2.1 16-bit instruction[...]

2 2-13 M32R-FPU Software Manual (Rev.1.01) The MSB (Most Significant Bit) of a 32-bit instruction is always "1". The MSB of a 16-bit instruction in the high-order halfword is always "0" (instruction A in Figure 2.2.3), however the processing of the following 16-bit instruction depends on the MSB of the instruction. In Figure 2.2[...]

2 2-14 M32R-FPU Software Manual (Rev.1.01) This page left blank intentionally. INSTRUCTION SET 2.2 Instruction format[...]

CHAPTER 3 INSTRUCTIONS 3.1 Conventions for instruction description 3.2 Instruction description[...]

3 3-2 M32R-FPU Software Manual (Rev.1.01) 3.1 Conventions for instruction description Conventions for instruction description are summarized below. [Mnemonic] Shows the mnemonic and possible operands (operation target) using assembly language notation. Table 3.1.1 Operand list symbol(see note) addressing mode operation target R register direct gene[...]

3 3-3 M32R-FPU Software Manual (Rev.1.01) Table 3.1.3 Operation expression (operator) (cont.) operator meaning - sign invert (monomial operator) = substitute right side into left side (substitute operator) += adds right and left variables and substitute into left side (substitute operator) - = subtract right variable from left variable and substitu[...]

3 3-4 M32R-FPU Software Manual (Rev.1.01) [Description] Describes the operation performed by the instruction and any condition bit change. [EIT occurrence] Shows possible EIT events (Exception, Interrupt, Trap) which may occur as the result of the instruction's execution. Only address exception (AE), floating-point exception (FPE) and trap (TR[...]

3 3-5 M32R-FPU Software Manual (Rev.1.01) 3.2 Instruction description This section lists M32R-FPU instructions in alphabetical order. Each page is laid out as shown below. 3 ADD arithmetic oper Add [Mnemonic] [Function] [Description] [EIT occurrence] [Instruction format] Add Rdest,Rsrc Add Rdest = Rdest + Rsrc; None Add Rde 0000 dest 1010 src instr[...]

3 3-6 M32R-FPU Software Manual (Rev.1.01) ADD dest 0000 ADD Rdest,Rsrc ADD 1010 arithmetic/logic operation Add src [Mnemonic] ADD Rdest,Rsrc [Function] Add Rdest = Rdest + Rsrc; [Description] ADD adds Rsrc to Rdest and puts the result in Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] INSTRUCTIONS 3.2 Instruction descrip[...]

3 3-7 M32R-FPU Software Manual (Rev.1.01) ADD3 [Mnemonic] ADD3 Rdest,Rsrc,#imm16 [Function] Add Rdest = Rsrc + ( signed short ) imm16; [Description] ADD3 adds the 16-bit immediate value to Rsrc and puts the result in Rdest. The immediate value is sign-extended to 32 bits before the operation. The condition bit (C) is unchanged. [EIT occurrence] Non[...]

3 3-8 M32R-FPU Software Manual (Rev.1.01) ADDI [Mnemonic] ADDI Rdest,#imm8 [Function] Add Rdest = Rdest + ( signed char ) imm8; [Description] ADDI adds the 8-bit immediate value to Rdest and puts the result in Rdest. The immediate value is sign-extended to 32 bits before the operation. The condition bit (C) is unchanged. [EIT occurrence] None [Enco[...]

3 3-9 M32R-FPU Software Manual (Rev.1.01) ADDV [Mnemonic] ADDV Rdest,Rsrc [Function] Add Rdest = ( signed ) Rdest + ( signed ) Rsrc; C = overflow ? 1 : 0; [Description] ADDV adds Rsrc to Rdest and puts the result in Rdest. The condition bit (C) is set when the addition results in overflow; otherwise it is cleared. [EIT occurrence] None [Encoding] A[...]

3 3-10 M32R-FPU Software Manual (Rev.1.01) ADDV3 [Mnemonic] ADDV3 Rdest,Rsrc,#imm16 [Function] Add Rdest = ( signed ) Rsrc + ( signed ) ( ( signed short ) imm16 ); C = overflow ? 1 : 0; [Description] ADDV3 adds the 16-bit immediate value to Rsrc and puts the result in Rdest. The immediate value is sign-extended to 32 bits before it is added to Rsrc[...]

3 3-11 M32R-FPU Software Manual (Rev.1.01) ADDX [Mnemonic] ADDX Rdest,Rsrc [Function] Add Rdest = ( unsigned ) Rdest + ( unsigned ) Rsrc + C; C = carry_out ? 1 : 0; [Description] ADDX adds Rsrc and C to Rdest, and puts the result in Rdest. The condition bit (C) is set when the addition result cannot be represented by a 32-bit unsigned integer; othe[...]

3 3-12 M32R-FPU Software Manual (Rev.1.01) AND AND 1100 0000 AND Rdest,Rsrc logic operation instruction AND src dest [Mnemonic] AND Rdest,Rsrc [Function] Logical AND Rdest = Rdest & Rsrc; [Description] AND computes the logical AND of the corresponding bits of Rdest and Rsrc and puts the result in Rdest. The condition bit (C) is unchanged. [EIT [...]

3 3-13 M32R-FPU Software Manual (Rev.1.01) AND3 [Mnemonic] AND3 Rdest,Rsrc,#imm16 [Function] Logical AND Rdest = Rsrc & ( unsigned short ) imm16; [Description] AND3 computes the logical AND of the corresponding bits of Rsrc and the 16-bit immediate value, which is zero-extended to 32 bits, and puts the result in Rdest. The condition bit (C) is [...]

3 3-14 M32R-FPU Software Manual (Rev.1.01) BC BC [Mnemonic] (1) BC pcdisp8 (2) BC pcdisp24 [Function] Branch (1) if ( C==1 ) PC = ( PC & 0xfffffffc ) + ( ( ( signed char ) pcdisp8 ) << 2 ); (2) if ( C==1 ) PC = ( PC & 0xfffffffc ) + ( sign_extend ( pcdisp24 ) << 2 ); where #define sign_extend(x) ( ( ( signed ) ( (x)<< 8 ) [...]

3 3-15 M32R-FPU Software Manual (Rev.1.01) bit operation Bit clear [M32R-FPU Extended Instruction] INSTRUCTIONS 3.2 Instruction description BCLR BCLR [Mnemonic] BCLR #bitpos,@(disp16,Rsrc) [Function] Bit operation for memory contents Set 0 to specified bit. * ( signed char* ) ( Rsrc + ( signed short ) disp16 ) & = ~ ( 1<< ( 7-bitpos ) ) ;[...]

3 3-16 M32R-FPU Software Manual (Rev.1.01) BEQ BEQ branch instruction Branch on equal to [Mnemonic] BEQ Rsrc1,Rsrc2,pcdisp16 [Function] Branch if ( Rsrc1 == Rsrc2 ) PC = ( PC & 0xfffffffc ) + ( ( ( signed short ) pcdisp16 ) << 2); [Description] BEQ causes a branch to the specified label when Rsrc1 is equal to Rsrc2. The condition bit (C) [...]

3 3-17 M32R-FPU Software Manual (Rev.1.01) BEQZ BEQZ branch instruction Branch on equal to zero [Mnemonic] BEQZ Rsrc,pcdisp16 [Function] Branch if ( Rsrc == 0 ) PC = ( PC & 0xfffffffc ) + ( ( ( signed short ) pcdisp16 ) << 2); [Description] BEQZ causes a branch to the specified label when Rsrc is equal to zero. The condition bit (C) is un[...]

3 3-18 M32R-FPU Software Manual (Rev.1.01) BGEZ BGEZ branch instruction Branch on greater than or equal to zero [Mnemonic] BGEZ Rsrc,pcdisp16 [Function] Branch if ( (signed) Rsrc >= 0 ) PC = ( PC & 0xfffffffc ) + ( ( ( signed short ) pcdisp16 ) << 2); [Description] BGEZ causes a branch to the specified label when Rsrc treated as a sign[...]

3 3-19 M32R-FPU Software Manual (Rev.1.01) BGTZ BGTZ branch instruction Branch on greater than zero [Mnemonic] BGTZ Rsrc,pcdisp16 [Function] Branch if ((signed) Rsrc > 0) PC = (PC & 0xfffffffc) + ( ( (signed short) pcdisp16 ) << 2); [Description] BGTZ causes a branch to the specified label when Rsrc treated as a signed 32-bit value is [...]

3 3-20 M32R-FPU Software Manual (Rev.1.01) BL BL branch instruction Branch and link [Mnemonic] (1) BL pcdisp8 (2) BL pcdisp24 [Function] Subroutine call (PC relative) (1) R14 = ( PC & 0xfffffffc ) + 4; PC = ( PC & 0xfffffffc ) + ( ( ( signed char ) pcdisp8 ) << 2 ); (2) R14 = ( PC & 0xfffffffc ) + 4; PC = ( PC & 0xfffffffc ) +[...]

3 3-21 M32R-FPU Software Manual (Rev.1.01) BLEZ BLEZ branch instruction Branch on less than or equal to zero [Mnemonic] BLEZ Rsrc,pcdisp16 [Function] Branch if ((signed) Rsrc <= 0) PC = (PC & 0xfffffffc) + (((signed short) pcdisp16) << 2); [Description] BLEZ causes a branch to the specified label when the contents of Rsrc treated as a [...]

3 3-22 M32R-FPU Software Manual (Rev.1.01) BLTZ BLTZ branch instruction Branch on less than zero [Mnemonic] BLTZ Rsrc,pcdisp16 [Function] Branch if ((signed) Rsrc < 0) PC = (PC & 0xfffffffc) + (((signed short) pcdisp16) << 2); [Description] BLTZ causes a branch to the specified label when Rsrc treated as a signed 32-bit value is less t[...]

3 3-23 M32R-FPU Software Manual (Rev.1.01) BNC BNC branch instruction Branch on not C-bit [Mnemonic] (1) BNC pcdisp8 (2) BNC pcdisp24 [Function] Branch (1) if (C==0) PC = ( PC & 0xfffffffc ) + ( ( ( signed char ) pcdisp8 ) << 2 ); (2) if (C==0) PC = ( PC & 0xfffffffc ) + ( sign_extend ( pcdisp24 ) << 2 ); where #define sign_exte[...]

3 3-24 M32R-FPU Software Manual (Rev.1.01) BNE BNE branch instruction Branch on not equal to [Mnemonic] BNE Rsrc1,Rsrc2,pcdisp16 [Function] Branch if ( Rsrc1 != Rsrc2 ) PC = ( PC & 0xfffffffc ) + ((( signed short ) pcdisp16) << 2); [Description] BNE causes a branch to the specified label when Rsrc1 is not equal to Rsrc2. The condition bit[...]

3 3-25 M32R-FPU Software Manual (Rev.1.01) BNEZ BNEZ branch instruction Branch on not equal to zero [Mnemonic] BNEZ Rsrc,pcdisp16 [Function] Branch if ( Rsrc != 0 ) PC = ( PC & 0xfffffffc ) + ( ( ( signed short ) pcdisp16 ) << 2); [Description] BNEZ causes a branch to the specified label when Rsrc is not equal to zero. The condition bit ([...]

3 3-26 M32R-FPU Software Manual (Rev.1.01) BRA BRA branch instruction Branch [Mnemonic] (1) BRA pcdisp8 (2) BRA pcdisp24 [Function] Branch (1) PC = ( PC & 0xfffffffc ) + ( ( ( signed char ) pcdisp8 ) << 2 ); (2) PC = ( PC & 0xfffffffc ) + ( sign_extend ( pcdisp24 ) << 2 ); where #define sign_extend(x) ( ( ( signed ) ( (x)<<[...]

3 3-27 M32R-FPU Software Manual (Rev.1.01) BSET BSET INSTRUCTIONS 3.2 Instruction description bit operation Instructions Bit set [M32R-FPU Extended Instruction] [Mnemonic] BSET #bitpos,@(disp16,Rsrc) [Function] Bit operation for memory contents Set 0 to specified bit. * ( signed char* ) ( Rsrc + ( signed short ) disp16 ) : = ( 1<< ( 7-bitpos [...]

3 3-28 M32R-FPU Software Manual (Rev.1.01) BTST BTST INSTRUCTIONS 3.2 Instruction description bit operation Instructions Bit test [M32R-FPU Extended Instruction] [Mnemonic] BTST #bitpos,Rsrc [Function] Remove the bit specified by the register. C = Rsrc >> ( 7-bitpos ) ) &1; [Description] Take out the bit specified as bitpos within the Rsr[...]

3 3-29 M32R-FPU Software Manual (Rev.1.01) CLRPSW CLRPSW INSTRUCTIONS 3.2 Instruction description bit operation Instructions Clear PSW [M32R-FPU Extended Instruction] [Mnemonic] CLRPSW #imm8 [Function] Set the undefined SM, IE, and C bits of PSW to 0. PSW& = ~imm8 : 0xffffff00 [Description] Set the AND result s of the reverse value of b0 (MSB),[...]

3 3-30 M32R-FPU Software Manual (Rev.1.01) CMP [Mnemonic] CMP Rsrc1,Rsrc2 [Function] Compare C = ( ( signed ) Rsrc1 < ( signed ) Rsrc2 ) ? 1:0; [Description] The condition bit (C) is set to 1 when Rsrc1 is less than Rsrc2. The operands are treated as signed 32-bit values. [EIT occurrence] None [Encoding] src1 0000 CMP Rsrc1,Rsrc2 CMP 0100 compar[...]

3 3-31 M32R-FPU Software Manual (Rev.1.01) CMPI [Mnemonic] CMPI Rsrc,#imm16 [Function] Compare C = ( ( signed ) Rsrc < ( signed short ) imm16 ) ? 1:0; [Description] The condition bit (C) is set when Rsrc is less than 16-bit immediate value. The operands are treated as signed 32-bit values. The immediate value is sign-extended to 32-bit before th[...]

3 3-32 M32R-FPU Software Manual (Rev.1.01) CMPU [Mnemonic] CMPU Rsrc1,Rsrc2 [Function] Compare C = ( ( unsigned ) Rsrc1 < ( unsigned ) Rsrc2 ) ? 1:0; [Description] The condition bit (C) is set when Rsrc1 is less than Rsrc2. The operands are treated as un- signed 32-bit values. [EIT occurrence] None [Encoding] src1 0000 CMPU Rsrc1,Rsrc2 CMPU 0101[...]

3 3-33 M32R-FPU Software Manual (Rev.1.01) CMPUI [Mnemonic] CMPUI Rsrc,#imm16 [Function] Compare C = ( ( unsigned ) Rsrc < ( unsigned ) ( ( signed short ) imm16 ) ) ? 1:0; [Description] The condition bit (C) is set when Rsrc is less than the 16-bit immediate value. The operands are treated as unsigned 32-bit values. The immediate value is sign-e[...]

3 3-34 M32R-FPU Software Manual (Rev.1.01) dest 1001 src 0000 0000 0000 0000 0000 DIV Rdest,Rsrc DIV [Mnemonic] DIV Rdest,Rsrc [Function] Signed division Rdest = ( signed ) Rdest / ( signed ) Rsrc; [Description] DIV divides Rdest by Rsrc and puts the quotient in Rdest. The operands are treated as signed 32-bit values and the result is rounded towar[...]

3 3-35 M32R-FPU Software Manual (Rev.1.01) DIVU [Mnemonic] DIVU Rdest,Rsrc [Function] Unsigned division Rdest = ( unsigned ) Rdest / ( unsigned ) Rsrc; [Description] DIVU divides Rdest by Rsrc and puts the quotient in Rdest. The operands are treated as unsigned 32-bit values and the result is rounded toward zero. The condition bit (C) is unchanged.[...]

3 3-36 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FADD FADD [Mnemonic] FADD Rdest,Rsrc1,Rsrc2 [Function] Floating-point add Rdest = Rsrc1 + Rsrc2 ; [Description] Add the floating-point single precision values stored in Rsrc1 and Rsrc2 and store the result in Rdest. The result is rounded according to the RM field of[...]

3 3-37 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description [Supplemental Operation Description] The following shows the values of Rsrc1 and Rsrc2 and the operation results when DN = 0 and DN = 1. DN = 0 Rsrc2 add UIPL QNaN QNaN SNaN QNaN SNaN +0 +0 +0 (Note) (Note) +Infinity +Infinity IVLD IVLD IVLD -Infinity -Infinity -Inf[...]

3 3-38 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FCMP FCMP src1 1101 src2 0000 dest 0000 0000 1100 FCMP Rdest,Rsrc1,Rsrc2 [Mnemonic] FCMP Rdest,Rsrc1,Rsrc2 [Function] Floating-point compare Rdest = (comparison results of Rsrc1 and Rsrc2); When at least one value, either Rsrc1 or Rsrc2, is SNaN, a floating-point ex[...]

3 3-39 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description [Supplemental Operation Description] The following shows the values of Rsrc1 and Rsrc2 and the operation results when DN = 0 and DN = 1. DN = 0 DN = 1 IVLD: Invalid Operation Exception UIPL: Unimplemented Exception NaN: Not a Number SNaN: Signaling NaN QNaN: Quiet N[...]

3 3-40 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FCMPE FCMPE src1 1101 src2 0000 dest 0000 0000 1101 FCMPE Rdest,Rsrc1,Rsrc2 [Mnemonic] FCMPE Rdest,Rsrc1,Rsrc2 [Function] Floating-point compare Rdest = (comparison results of Rsrc1 and Rsrc2); When at least one value, either Rsrc1 or Rsrc2, is QNaN or SNaN, a float[...]

3 3-41 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description [Supplemental Operation Description] The following shows the values of Rsrc1 and Rsrc2 and the operation results when DN = 0 and DN = 1. DN = 0 DN = 1 IVLD: Invalid Operation Exception UIPL: Unimplemented Exception NaN: Not a Number SNaN: Signaling NaN QNaN: Quiet N[...]

3 3-42 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FDIV FDIV [Mnemonic] FDIV Rdest,Rsrc1,Rsrc2 [Function] Floating-point divide Rdest = Rsrc1 / Rsrc2 ; [Description] Divide the floating-point single precision value stored in Rsrc1 by the floating-point single pre- cision value stored in Rsrc1 and store the result in[...]

3 3-43 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description [Supplemental Operation Description] The following shows the values of Rsrc1 and Rsrc2 and the operation results when DN = 0 and DN = 1. DN = 0 DN = 1 IVLD: Invalid Operation Exception UIPL: Unimplemented Exception DIV0: Zero Divide Exception NaN: Not a Number SNaN:[...]

3 3-44 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FMADD FMADD [Mnemonic] FMADD Rdest,Rsrc1,Rsrc2 [Function] Floating-point multiply and add Rdest = Rdest + Rsrc1 * Rsrc2 ; [Description] This instruction is executed in the following 2 steps. ● Step 1 Multiply the floating-point single precision value stored in Rsr[...]

3 3-45 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description [Supplemental Operation Description] The following shows the values of Rsrc1, Rsrc2 and Rdest and the operation results when DN = 0 and DN = 1. DN=0 Value after Multiplication Operation Value after Addition Operation IVLD: Invalid Operation Exception UIPL: Unimpleme[...]

3 3-46 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description DN=1 Value after Multiplication Operation Value after Addition Operation IVLD: Invalid Operation Exception UIPL: Unimplemented Exception NaN: Not a Number SNaN: Signaling NaN QNaN: Quiet NaN Note: The rounding mode is “-0” when rounding toward “-Infinity”, a[...]

3 3-47 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FMSUB FMSUB [Mnemonic] FMSUB Rdest,Rsrc1,Rsrc2 [Function] Floating-point multiply and subtract Rdest = Rdest - Rsrc1 * Rsrc2 ; [Description] This instruction is executed in the following 2 steps. ● Step 1 Multiply the floating-point single precision value stored i[...]

3 3-48 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description [Supplemental Operation Description] The following shows the values of Rsrc1, Rsrc2 and Rdest and the operation results when DN = 0 and DN = 1. DN=0 Value after Multiplication Operation Value after Subtraction Operation IVLD: Invalid Operation Exception UIPL: Unimpl[...]

3 3-49 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description DN=1 Value after Multiplication Operation Value after Subtraction Operation IVLD: Invalid Operation Exception UIPL: Unimplemented Exception NaN: Not a Number SNaN: Signaling NaN QNaN: Quiet NaN Note: The rounding mode is “-0” when rounding toward “-Infinity”[...]

3 3-50 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FMUL FMUL [Mnemonic] FMUL Rdest,Rsrc1,Rsrc2 [Function] Floating-point multiply Rdest = Rsrc1 * Rsrc2 ; [Description] Multiply the floating-point single precision value stored in Rsrc1 by the floating-point single precision value stored in Rsrc2 and store the results[...]

3 3-51 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description [Supplemental Operation Description] The following shows the values of Rsrc1 and Rsrc2 and the operation results when DN = 0 and DN = 1. DN=0 DN=1 IVLD: Invalid Operation Exception UIPL: Unimplemented Exception NaN: Not a Number SNaN: Signaling NaN QNaN: Quiet NaN R[...]

3 3-52 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FSUB FSUB [Mnemonic] FSUB Rdest,Rsrc1,Rsrc2 [Function] Floating-point subtract Rdest = Rsrc1 - Rsrc2 ; [Description] Subtract the floating-point single precision value stored in Rsrc2 from the floating-point single precision value stored in Rsrc1 and store the resul[...]

3 3-53 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description Rsrc2 Subtraction UIPL QNaN QNaN SNaN QNaN SNaN +0 +0 +0 (Note) (Note) +Infinity +Infinity IVLD IVLD IVLD -Infinity -Infinity -Infinity +Infinity -0 -0 +Infinity -Infinity Denormalized Number Denormalized Number Normalized Number Normalized Number -0 Rsrc1 Rsrc2 QNa[...]

3 3-54 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FTOI FTOI [Mnemonic] FTOI Rdest,Rsrc [Function] Convert the floating-point single precision value to 32-bit integer. Rdest = (signed int) Rsrc ; [Description] Convert the floating-point single precision value stored in Rsrc to a 32-bit integer and store the result i[...]

3 3-55 M32R-FPU Software Manual (Rev.1.01) [Supplemental Operation Description] The results of the FTOI instruction executed based on the Rsrc value, both when DN = 0 and DN = 1, are shown in below. DN = 0 Rsrc Value (exponent with no bias) Rdest Exception Rsrc ≥ 0 +Infinity When EIT occurs: no change Invalid Operation Exception 127 ≥ exp ≥ 3[...]

3 3-56 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FTOS FTOS [Mnemonic] FTOS Rdest,Rsrc [Function] Convert the floating-point single precision value to 16-bit integer. Rdest = (signed int) Rsrc ; [Description] Convert the floating-point single precision value stored in Rsrc to a 16-bit integer and store the result i[...]

3 3-57 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description [Supplemental Operation Description] The results of the FTOS instruction executed based on the Rsrc value, both when DN = 0 and DN = 1, are shown in below. DN = 0 Rsrc Value (exponent with no bias) Rdest Exception Rsrc ≥ 0 +Infinity When EIT occurs: no change Inva[...]

3 3-58 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description ITOF ITOF [Mnemonic] ITOF Rdest,Rsrc [Function] Convert the integer to a floating-point single precision value. Rdes = (float) Rsrc ; [Description] Converts the 32-bit integer stored in Rsrc to a floating-point single precision value and stores the result in Rdest. [...]

3 3-59 M32R-FPU Software Manual (Rev.1.01) JL JL branch instruction Jump and link [Mnemonic] JL Rsrc [Function] Subroutine call (register direct) R14 = ( PC & 0xfffffffc ) + 4; PC = Rsrc & 0xfffffffc; [Description] JL causes an unconditional jump to the address specified by Rsrc and puts the return address in R14. The condition bit (C) is u[...]

3 3-60 M32R-FPU Software Manual (Rev.1.01) JMP JMP branch instruction Jump [Mnemonic] JMP Rsrc [Function] Jump PC = Rsrc & 0xfffffffc; [Description] JMP causes an unconditional jump to the address specified by Rsrc. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] JMP Rsrc 1111 0001 1100 src INSTRUCTIONS 3.2 Instruction desc[...]

3 3-61 M32R-FPU Software Manual (Rev.1.01) LD LD load/store instruction Load [Mnemonic] (1) LD Rdest,@Rsrc (2) LD Rdest,@Rsrc+ (3) LD Rdest,@(disp16,Rsrc) [Function] Load to register from the contents of the memory. (1) Rdest = *( int *) Rsrc; (2) Rdest = *( int *) Rsrc, Rsrc += 4; (3) Rdest = *( int *) ( Rsrc + ( signed short ) disp16 ); [Descript[...]

3 3-62 M32R-FPU Software Manual (Rev.1.01) LD24 LD24 load/store instruction Load 24-bit immediate [Mnemonic] LD24 Rdest,#imm24 [Function] Load the 24-bit immediate value into register. Rdest = imm24 & 0x00ffffff; [Description] LD24 loads the 24-bit immediate value into Rdest. The immediate value is zero-extended to 32 bits. The condition bit (C[...]

3 3-63 M32R-FPU Software Manual (Rev.1.01) LDB LDB load/store instruction Load byte [Mnemonic] (1) LDB Rdest,@Rsrc (2) LDB Rdest,@(disp16,Rsrc) [Function] Load to register from the contents of the memory. (1) Rdest = *( signed char *) Rsrc; (2) Rdest = *( signed char *) ( Rsrc + ( signed short ) disp16 ); [Description] (1) LDB sign-extends the byte[...]

3 3-64 M32R-FPU Software Manual (Rev.1.01) LDH LDH load/store instruction Load halfword [Mnemonic] (1) LDH Rdest,@Rsrc (2) LDH Rdest,@(disp16,Rsrc) [Function] Load to register from the contents of the memory. (1) Rdest = *( signed short *) Rsrc; (2) Rdest = *( signed short *) ( Rsrc + ( signed short ) disp16 ); [Description] (1) LDH sign-extends th[...]

3 3-65 M32R-FPU Software Manual (Rev.1.01) LDI LDI transfer instruction Load immediate [Mnemonic] (1) LDI Rdest,#imm8 (2) LDI Rdest,#imm16 [Function] Load the immediate value into register. (1) Rdest = ( signed char ) imm8; (2) Rdest = ( signed short ) imm16; [Description] (1) LDI loads the 8-bit immediate value into Rdest. The immediate value is s[...]

3 3-66 M32R-FPU Software Manual (Rev.1.01) LDUB LDUB load/store instruction Load unsigned byte [Mnemonic] (1) LDUB Rdest,@Rsrc (2) LDUB Rdest,@(disp16,Rsrc) [Function] Load to register from the contents of the memory. (1) Rdest = *( unsigned char *) Rsrc; (2) Rdest = *( unsigned char *) ( Rsrc + ( signed short ) disp16 ); [Description] (1) LDUB zer[...]

3 3-67 M32R-FPU Software Manual (Rev.1.01) LDUH LDUH load/store instruction Load unsigned halfword [Mnemonic] (1) LDUH Rdest,@Rsrc (2) LDUH Rdest,@(disp16,Rsrc) [Function] Load to register from the contents of the memory. (1) Rdest = *( unsigned short *) Rsrc; (2) Rdest = *( unsigned short *) ( Rsrc + ( signed short ) disp16 ); [Description] (1) LD[...]

3 3-68 M32R-FPU Software Manual (Rev.1.01) LOCK LOCK load/store instruction Load locked [Mnemonic] LOCK Rdest,@Rsrc [Function] Load locked LOCK = 1, Rdest = *( int *) Rsrc; [Description] The contents of the word at the memory location specified by Rsrc are loaded into Rdest. The condition bit (C) is unchanged. This instruction sets the LOCK bit in [...]

3 3-69 M32R-FPU Software Manual (Rev.1.01) MACHI MACHI DSP function instruction Multiply-accumulate high-order halfwords [Mnemonic] MACHI Rsrc1,Rsrc2 [Function] Multiply and add accumulator += (( signed) (Rsrc1 & 0xffff0000) * (signed short) (Rsrc2 >> 16)); [Description] MACHI multiplies the high-order 16 bits of Rsrc1 and the high-order [...]

3 3-70 M32R-FPU Software Manual (Rev.1.01) MACLO MACLO DSP function instruction Multiply-accumulate low-order halfwords [Mnemonic] MACLO Rsrc1,Rsrc2 [Function] Multiply and add accumulator += ( ( signed ) ( Rsrc1 << 16 ) * ( signed short ) Rsrc2 ) ; [Description] MACLO multiplies the low-order 16 bits of Rsrc1 and the low-order 16 bits of Rsr[...]

3 3-71 M32R-FPU Software Manual (Rev.1.01) MACWHI MACWHI DSP function instruction Multiply-accumulate word and high-order halfword [Mnemonic] MACWHI Rsrc1,Rsrc2 [Function] Multiply and add accumulator += ( ( signed ) Rsrc1 * ( signed short ) ( Rsrc2 >> 16 ) ); [Description] MACWHI multiplies the 32 bits of Rsrc1 and the high-order 16 bits of [...]

3 3-72 M32R-FPU Software Manual (Rev.1.01) MACWLO MACWLO DSP function instruction Multiply-accumulate word and low-order halfword [Mnemonic] MACWLO Rsrc1,Rsrc2 [Function] Multiply and add accumulator += ( ( signed ) Rsrc1 * ( signed short ) Rsrc2 ) ; [Description] MACWLO multiplies the 32 bits of Rsrc1 and the low-order 16 bits of Rsrc2, then adds [...]

3 3-73 M32R-FPU Software Manual (Rev.1.01) MUL MUL multiply and divide instruction Multiply [Mnemonic] MUL Rdest,Rsrc [Function] Multiply { signed64bit tmp; tmp = ( signed64bit ) Rdest * ( signed64bit ) Rsrc; Rdest = ( int ) tmp;} [Description] MUL multiplies Rdest by Rsrc and puts the result in Rdest. The operands are treated as signed values. The[...]

3 3-74 M32R-FPU Software Manual (Rev.1.01) MULHI MULHI DSP function instruction Multiply high-order halfwords [Mnemonic] MULHI Rsrc1,Rsrc2 [Function] Multiply accumulator = (( signed) (Rsrc1 & 0xffff000 ) * (signed short) (Rsrc2 >> 16)); [Description] MULHI multiplies the high-order 16 bits of Rsrc1 and the high-order 16 bits of Rsrc2, an[...]

3 3-75 M32R-FPU Software Manual (Rev.1.01) MULLO MULLO DSP function instruction Multiply low-order halfwords [Mnemonic] MULLO Rsrc1,Rsrc2 [Function] Multiply accumulator = ( ( signed ) ( Rsrc1 << 16 ) * ( signed short ) Rsrc2 ); [Description] MULLO multiplies the low-order 16 bits of Rsrc1 and the low-order 16 bits of Rsrc2, and stores the re[...]

3 3-76 M32R-FPU Software Manual (Rev.1.01) MULWHI MULWHI DSP function instruction Multiply word and high-order halfword [Mnemonic] MULWHI Rsrc1,Rsrc2 [Function] Multiply accumulator = ( ( signed ) Rsrc1 * ( signed short ) ( Rsrc2 >> 16 ) ); [Description] MULWHI multiplies the 32 bits of Rsrc1 and the high-order 16 bits of Rsrc2, and stores th[...]

3 3-77 M32R-FPU Software Manual (Rev.1.01) MULWLO MULWLO DSP fucntion instruction Multiply word and low-order halfword [Mnemonic] MULWLO Rsrc1,Rsrc2 [Function] Multiply accumulator = ( ( signed ) Rsrc1 * ( signed short ) Rsrc2 ); [Description] MULWLO multiplies the 32 bits of Rsrc1 and the low-order 16 bits of Rsrc2, and stores the result in the ac[...]

3 3-78 M32R-FPU Software Manual (Rev.1.01) MV MV transfer instruction Move register [Mnemonic] MV Rdest,Rsrc [Function] Transfer Rdest = Rsrc; [Description] MV moves Rsrc to Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] dest 0001 M V Rdest,Rsrc src 1000 INSTRUCTIONS 3.2 Instruction description[...]

3 3-79 M32R-FPU Software Manual (Rev.1.01) MVFACHI MVFACHI DSP function instruction Move high-order word from accumulator [Mnemonic] MVFACHI Rdest [Function] Transfer from accumulator to register Rdest = ( int ) ( accumulator >> 32 ) ; [Description] MVFACHI moves the high-order 32 bits of the accumulator to Rdest. The condition bit (C) is unc[...]

3 3-80 M32R-FPU Software Manual (Rev.1.01) MVFACLO MVFACLO DSP function instruction Move low-order word from accumulator [Mnemonic] MVFACLO Rdest [Function] Transfer from accumulator to register Rdest = ( int ) accumulator [Description] MVFACLO moves the low-order 32 bits of the accumulator to Rdest. The condition bit (C) is unchanged. [EIT occurre[...]

3 3-81 M32R-FPU Software Manual (Rev.1.01) MVFACMI MVFACMI DSP function instruction Move middle-order word from accumulator [Mnemonic] MVFACMI Rdest [Function] Transfer from accumulator to register Rdest = ( int ) ( accumulator >> 16 ) ; [Description] MVFACMI moves bits16 through 47 of the accumulator to Rdest. The condition bit (C) is unchan[...]

3 3-82 M32R-FPU Software Manual (Rev.1.01) MVFC MVFC transfer instruction Move from control register [Mnemonic] MVFC Rdest,CRsrc [Function] Transfer from control register to register Rdest = CRsrc ; [Description] MVFC moves CRsrc to Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] dest 0001 MVFC Rdest,CRsrc src 1001 INSTR[...]

3 3-83 M32R-FPU Software Manual (Rev.1.01) MVTACHI MVTACHI DSP function instruction Move high-order word to accumulator [Mnemonic] MVTACHI Rsrc [Function] Transfer from register to accumulator accumulator [ 0 : 31 ] = Rsrc ; [Description] MVTACHI moves Rsrc to the high-order 32 bits of the accumulator. The condition bit (C) is unchanged. [EIT occur[...]

3 3-84 M32R-FPU Software Manual (Rev.1.01) MVTACLO MVTACLO DSP function instruction Move low-order word to accumulator [Mnemonic] MVTACLO Rsrc [Function] Transfer from register to accumulator accumulator [ 32 : 63 ] = Rsrc ; [Description] MVTACLO moves Rsrc to the low-order 32 bits of the accumulator. The condition bit (C) is unchanged. [EIT occurr[...]

3 3-85 M32R-FPU Software Manual (Rev.1.01) MVTC MVTC transfer instruction Move to control register [Mnemonic] MVTC Rsrc,CRdest [Function] Transfer from register to control register CRdest = Rsrc ; [Description] MVTC moves Rsrc to CRdest. If PSW(CR0) is specified as CRdest, the condition bit (C) is changed; otherwise it is un- changed. [EIT occurren[...]

3 3-86 M32R-FPU Software Manual (Rev.1.01) NEG NEG arithmetic operation instruction Negate [Mnemonic] NEG Rdest,Rsrc [Function] Negate Rdest = 0 – Rsrc ; [Description] NEG negates (changes the sign of) Rsrc treated as a signed 32-bit value, and puts the result in Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] dest 000[...]

3 3-87 M32R-FPU Software Manual (Rev.1.01) NOP NOP branch instruction No operation [Mnemonic] NOP [Function] No operation /* */ [Description] NOP performs no operation. The subsequent instruction then processed. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] NOP 0000 0111 0000 0000 INSTRUCTIONS 3.2 Instruction description[...]

3 3-88 M32R-FPU Software Manual (Rev.1.01) NOT NOT logic operation instruction Logical NOT [Mnemonic] NOT Rdest,Rsrc [Function] Logical NOT Rdest = ~ Rsrc ; [Description] NOT inverts each of the bits of Rsrc and puts the result in Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] dest 0000 NOT Rdest,Rsrc src 1011 INSTRUCTI[...]

3 3-89 M32R-FPU Software Manual (Rev.1.01) OR OR logic operation instruction OR [Mnemonic] OR Rdest,Rsrc [Function] Logical OR Rdest = Rdest | Rsrc ; [Description] OR computes the logical OR of the corresponding bits of Rdest and Rsrc, and puts the result in Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] dest 0000 O R R[...]

3 3-90 M32R-FPU Software Manual (Rev.1.01) OR3 OR3 logic operation instruction OR 3-operand [Mnemonic] OR3 Rdest,Rsrc,#imm16 [Function] Logical OR Rdest = Rsrc | ( unsigned short ) imm16 ; [Description] OR3 computes the logical OR of the corresponding bits of Rsrc and the 16-bit immediate value, which is zero-extended to 32 bits, and puts the resul[...]

3 3-91 M32R-FPU Software Manual (Rev.1.01) RAC RAC DSP function instruction Round accumulator [Mnemonic] RAC [Function] Saturation Process { signed64bit tmp; tmp = ( signed64bit ) accumulator << 1; tmp = tmp + 0x0000 0000 0000 8000; if( 0x0000 7fff ffff 0000 < tmp ) accumulator = 0x0000 7fff ffff 0000; else if( tmp < 0xffff 8000 0000 00[...]

3 3-92 M32R-FPU Software Manual (Rev.1.01) [Supplement] This instruction is executed in two steps as shown below: <step 1> <step 2> The value in the accumulator is altered depending on the supposed bit 80 through 7 after left-shift operation and bit 8 through bit 63 after shift operation. if bit 48 is 0 , there is no carry . if bit 48 i[...]

3 3-93 M32R-FPU Software Manual (Rev.1.01) RACH RACH DSP function instruction Round accumulator halfword [Mnemonic] RACH [Function] Saturation Process { signed64bit tmp; tmp = ( signed64bit ) accumulator << 1; tmp = tmp + 0x0000 0000 8000 0000; if( 0x0000 7fff 0000 0000 < tmp ) accumulator = 0x0000 7fff 0000 0000; else if( tmp < 0xffff [...]

3 3-94 M32R-FPU Software Manual (Rev.1.01) [Supplement] This instruction is executed in two steps, as shown below. <proccess 1> <proccess 2> The value in the accumulator is altered depending on the supposed bit 80 through 7 after left-shift operation and bit 8 through bit 63 after shift operation. if bit 32 is 0 , there is no carry . if[...]

3 3-95 M32R-FPU Software Manual (Rev.1.01) REM REM multiply and divide instruction Remainder [Mnemonic] REM Rdest,Rsrc [Function] Signed remainder Rdest = ( signed ) Rdest % ( signed ) Rsrc ; [Description] REM divides Rdest by Rsrc and puts the quotient in Rdest. The operands are treated as signed 32-bit values. The quotient is rounded toward zero [...]

3 3-96 M32R-FPU Software Manual (Rev.1.01) REMU REMU multiply and divide instruction Remainder unsigned [Mnemonic] REMU Rdest,Rsrc [Function] Unsigned remainder Rdest = ( unsigned ) Rdest % ( unsigned ) Rsrc ; [Description] REMU divides Rdest by Rsrc and puts the quotient in Rdest. The operands are treated as unsigned 32-bit values. The condition b[...]

3 3-97 M32R-FPU Software Manual (Rev.1.01) RTE RTE EIT-related instruction Return from EIT [Mnemonic] RTE [Function] Return from EIT SM = BSM ; IE = BIE ; C = BC ; PC = BPC & 0xfffffffc ; [Description] RTE restores the SM, IE and C bits of the PSW from the BSM, BIE and BC bits, and jumps to the address specified by BPC. At this time, because th[...]

3 3-98 M32R-FPU Software Manual (Rev.1.01) SETH SETH Transfer instructions Set high-order 16-bit [Mnemonic] SETH Rdest,#imm16 [Function] Transfer instructions Rdest = ( signed short ) imm16 << 16 ; [Description] SETH load the immediate value into the 16 most significant bits of Rdest. The 16 least significant bits become zero. The condition b[...]

3 3-99 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description SETPSW SETPSW Bit Operation Instructions Set PSW [M32R-FPU Extended Instruction] [Mnemonic] SETPSW #imm8 [Function] Set the undefined SM, IE, anc C bits of PSW to 1. PSW : = imm8&0x000000ff [Description] Set the AND result of the value of b0 (MSB), b1, and b7 (L[...]

3 3-100 M32R-FPU Software Manual (Rev.1.01) SLL SLL shift instruction Shift left logical [Mnemonic] SLL Rdest,Rsrc [Function] Logical left shift Rdest = Rdest << ( Rsrc & 31 ) ; [Description] SLL left logical-shifts the contents of Rdest by the number specified by Rsrc, shifting zeroes into the least significant bits. Only the five least [...]

3 3-101 M32R-FPU Software Manual (Rev.1.01) SLL3 SLL3 shift instruction Shift left logical 3-operand [Mnemonic] SLL3 Rdest,Rsrc,#imm16 [Function] Logical left shift Rdest = Rsrc << ( imm16 & 31 ) ; [Description] SLL3 left logical-shifts the contents of Rsrc into Rdest by the number specified by the 16-bit immediate value, shifting zeroes [...]

3 3-102 M32R-FPU Software Manual (Rev.1.01) SLLI SLLI shift instruction Shift left logical immediate [Mnemonic] SLLI Rdest,#imm5 [Function] Logical left shift Rdest = Rdest << imm5 ; [Description] SLLI left logical-shifts the contents of Rdest by the number specified by the 5-bit immediate value, shifting zeroes into the least significant bit[...]

3 3-103 M32R-FPU Software Manual (Rev.1.01) SRA SRA shift instruction Shift right arithmetic [Mnemonic] SRA Rdest,Rsrc [Function] Arithmetic right shift Rdest = ( signed ) Rdest >> ( Rsrc & 31 ) ; [Description] SRA right arithmetic-shifts the contents of Rdest by the number specified by Rsrc, replicates the sign bit in the MSB of Rdest an[...]

3 3-104 M32R-FPU Software Manual (Rev.1.01) SRA3 SRA3 shift instruction Shift right arithmetic 3-operand [Mnemonic] SRA3 Rdest,Rsrc,#imm16 [Function] Arithmetic right shift Rdest = ( signed ) Rsrc >> ( imm16 & 31 ) ; [Description] SRA3 right arithmetic-shifts the contents of Rsrc into Rdest by the number specified by the 16- bit immediate[...]

3 3-105 M32R-FPU Software Manual (Rev.1.01) SRAI SRAI shift instruction Shift right arithmetic immediate [Mnemonic] SRAI Rdest,#imm5 [Function] Arithmetic right shift Rdest = ( signed ) Rdest >> imm5 ; [Description] SRAI right arithmetic-shifts the contents of Rdest by the number specified by the 5-bit immedi- ate value, replicates the sign b[...]

3 3-106 M32R-FPU Software Manual (Rev.1.01) SRL SRL shift instruction Shift right logical [Mnemonic] SRL Rdest,Rsrc [Function] Logical right shift Rdest = ( unsigned ) Rdest >> ( Rsrc & 31 ) ; [Description] SRL right logical-shifts the contents of Rdest by the number specified by Rsrc, shifts zeroes into the most significant bits and puts[...]

3 3-107 M32R-FPU Software Manual (Rev.1.01) SRL3 SRL3 shift instruction Shift right logical 3-operand [Mnemonic] SRL3 Rdest,Rsrc,#imm16 [Function] Logical right shift Rdest = ( unsigned ) Rsrc >> ( imm16 & 31 ) ; [Description] SRL3 right logical-shifts the contents of Rsrc into Rdest by the number specified by the 16-bit immediate value, [...]

3 3-108 M32R-FPU Software Manual (Rev.1.01) SRLI SRLI shift instruction Shift right logical immediate [Mnemonic] SRLI Rdest,#imm5 [Function] Logical right shift Rdest = ( unsigned ) Rdest >> ( imm5 & 31 ) ; [Description] SRLI right arithmetic-shifts Rdest by the number specified by the 5-bit immediate value, shift- ing zeroes into the mos[...]

3 3-109 M32R-FPU Software Manual (Rev.1.01) ST ST load/store instruction Store [Mnemonic] (1) ST Rsrc1,@Rsrc2 (2) ST Rsrc1,@+Rsrc2 (3) ST Rsrc1,@-Rsrc2 (4) ST Rsrc1,@(disp16,Rsrc2) [Function] Store (1) * ( int *) Rsrc2 = Rsrc1; (2) Rsrc2 += 4, * ( int *) Rsrc2 = Rsrc1; (3) Rsrc2 -= 4, * ( int *) Rsrc2 = Rsrc1; (4) * ( int *) ( Rsrc2 + ( signed shor[...]

3 3-110 M32R-FPU Software Manual (Rev.1.01) [Encoding] src1 1010 src1 0010 0111 src2 0100 src2 disp16 src1 0010 0110 src2 src1 0010 0100 src2 ST Rsrc1,@Rsrc2 ST Rsrc1,@+Rsrc2 ST Rsrc1,@-Rsrc2 ST Rsrc1,@(disp16,Rsrc2) INSTRUCTIONS 3.2 Instruction description ST ST load/store instruction Store[...]

3 3-111 M32R-FPU Software Manual (Rev.1.01) STB STB load/store instruction Store byte [Mnemonic] (1) STB Rsrc1,@Rsrc2 (2) STB Rsrc1,@(disp16,Rsrc2) [Function] Store (1) * ( char *) Rsrc2 = Rsrc1; (2) * ( char *) ( Rsrc2 + ( signed short ) disp16 ) = Rsrc1; [Description] (1) STB stores the least significant byte of Rsrc1 in the memory at the address[...]

3 3-112 M32R-FPU Software Manual (Rev.1.01) STH STH load/store instruction Store halfword [M32R-FPU Extended Mnemonic] [Mnemonic] (1) STH Rsrc1,@Rsrc2 (2) STH Rsrc1,@Rsrc2+ [M32R-FPU Extended Mnemonic] (3) STH Rsrc1,@(disp16,Rsrc2) [Function] Store (1) * ( signed short *) Rsrc2 = Rsrc1; (2) * ( signed short *) Rsrc2 = Rsrc1, Rsrc2 + = 2 ; (3) * ( s[...]

3 3-113 M32R-FPU Software Manual (Rev.1.01) SUB SUB arithmetic operation instruction Subtract [Mnemonic] SUB Rdest,Rsrc [Function] Subtract Rdest = Rdest - Rsrc; [Description] SUB subtracts Rsrc from Rdest and puts the result in Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] dest 0000 0010 src SUB Rdest,Rsrc INSTRUCTION[...]

3 3-114 M32R-FPU Software Manual (Rev.1.01) SUBV SUBV arithmetic operation instruction Subtract with overflow checking [Mnemonic] SUBV Rdest,Rsrc [Function] Subtract Rdest = Rdest - Rsrc; C = overflow ? 1 : 0; [Description] SUBV subtracts Rsrc from Rdest and puts the result in Rdest. The condition bit (C) is set when the subtraction results in over[...]

3 3-115 M32R-FPU Software Manual (Rev.1.01) SUBX SUBX arithmetic operation instruction Subtract with borrow [Mnemonic] SUBX Rdest,Rsrc [Function] Subtract Rdest = ( unsigned ) Rdest - ( unsigned ) Rsrc - C; C = borrow ? 1 : 0; [Description] SUBX subtracts Rsrc and C from Rdest and puts the result in Rdest. The condition bit (C) is set when the subt[...]

3 3-116 M32R-FPU Software Manual (Rev.1.01) TRAP TRAP EIT-related instruction Trap [Mnemonic] TRAP #imm4 [Function] Trap occurrence BPC = PC + 4; BSM = SM; BIE = IE; BC = C ; IE = 0; C = 0; call_trap_handler( imm4 ); [Description] TRAP generates a trap with the trap number specified by the 4-bit immediate value. IE and C bits are cleared to "0[...]

3 3-117 M32R-FPU Software Manual (Rev.1.01) UNLOCK UNLOCK load/store instruction Store unlocked [Mnemonic] UNLOCK Rsrc1,@Rsrc2 [Function] Store unlocked if ( LOCK == 1 ) { * ( int *) Rsrc2 = Rsrc1; } LOCK = 0; [Description] When the LOCK bit is 1, the contents of Rsrc1 are stored at the memory location specified by Rsrc2. When the LOCK bit is 0, st[...]

3 3-118 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description UTOF UTOF Floating Point Instructions Unsigned integer to float [M32R-FPU Extended Instruction] [Mnemonic] UTOF Rdest,Rsrc [Function] Convert from unsigned integer to floating-point single precision value. Rdest = ( float ) ( unsigned int ) Rsrc ; [Description] UTO[...]

3 3-119 M32R-FPU Software Manual (Rev.1.01) XOR XOR logic operation instruction Exclusive OR [Mnemonic] XOR Rdest,Rsrc [Function] Exclusive OR Rdest = ( unsigned ) Rdest ^ ( unsigned ) Rsrc; [Description] XOR computes the logical XOR of the corresponding bits of Rdest and Rsrc, and puts the result in Rdest. The condition bit (C) is unchanged. [EIT [...]

3 3-120 M32R-FPU Software Manual (Rev.1.01) XOR3 XOR3 logic operation instruction Exclusive OR 3-operand [Mnemonic] XOR3 Rdest,Rsrc,#imm16 [Function] Exclusive OR Rdest = ( unsigned ) Rsrc ^ ( unsigned short ) imm16; [Description] XOR3 computes the logical XOR of the corresponding bits of Rsrc and the 16-bit immediate value, which is zero-extended [...]

APPENDICES APPENDIX 1 Hexadecimal Instraction Code APPENDIX 2 Instruction List APPENDIX 3 Pipeline Processing APPENDIX 4 Instruction Execution Time APPENDIX 5 IEEE754 Specification Overview APPENDIX 6 M32R-FPU Specification Supplemental Explanation[...]

APPENDICES APPENDICES-2 M32R-FPU Software Manual (Rev.1.01) Appendix1 Hexadecimal Instraction Code The bit pattern of each instruction and correspondence of mnemonic are shown below. The instructions enclosed in the bold lines are M32R-FPU extended instructions. Appendix Table 1.1.1 Instruction Code Table b0 3 4 7 8 1 1 12 b15 16-bit instruction b [...]

APPENDICES APPENDICES-3 M32R-FPU Software Manual (Rev.1.01) 1000 1001 1010 101 1 1100 11 0 1 111 0 1111 89 BC DE F A b 8 -b 11 b 0 -b 3 hexadecimal numeral 16-bit instruction 32-bit instruction ADDV Rdest,Rsrc ADDX Rdest,Rsrc ADD Rdest,Rsrc NOT Rdest,Rsrc AND Rdest,Rsrc XOR Rdest,Rsrc OR Rdest,Rsrc MV Rdest,Rsrc MVFC Rdest,CRsrc MVTC Rsrc,CRdest RT[...]

APPENDICES APPENDICES-4 M32R-FPU Software Manual (Rev.1.01) mnemonic function condition bit (C) ADD Rdest,Rsrc Rdest = Rdest + Rsrc – ADD3 Rdest,Rsrc,#imm16 Rdest = Rsrc + (sh)imm16 – ADDI Rdest,#imm8 Rdest = Rdest + (sb)imm8 – ADDV Rdest,Rsrc Rdest = Rdest + Rsrc change ADDV3 Rdest,Rsrc,#imm16 Rdest = Rsrc + (sh)imm16 change ADDX Rdest,Rsrc [...]

APPENDICES APPENDICES-5 M32R-FPU Software Manual (Rev.1.01) mnemonic function condition bit (C) FMADD Rdest,Rsrc1,Rsrc2 Rdest = Rdest + Rsrc1 * Rsrc2 – FMSUB Rdest,Rsrc1,Rsrc2 Rdest = Rdest - Rsrc1 * Rsrc2 – FMUL Rdest,Rsrc1,Rsrc2 Rdest = Rdest * Rsrc2 – FSUB Rdest,Rsrc1,Rsrc2 Rdest = Rsrc1 - Rsrc2 – FTOI Rdest,Rsrc Rdest = (s)Rsrc2 – FTO[...]

APPENDICES APPENDICES-6 M32R-FPU Software Manual (Rev.1.01) mnemonic function condition bit (C) NEG Rdest,Rsrc Rdest = 0 - Rsrc – NOP /*no-operation*/ – NOT Rdest,Rsrc Rdest = ~ Rsrc – OR Rdest,Rsrc Rdest = Rdest | Rsrc – OR3 Rdest,Rsrc,#imm16 Rdest = Rsrc | (uh)imm16 – RAC Round the 32-bit value in the accumulator – RACH Round the 16-b[...]

APPENDICES APPENDICES-7 M32R-FPU Software Manual (Rev.1.01) where: typedef singed int s; /* 32 bit signed integer (word)*/ typedef unsigned int u; /* 32 bit unsigned integer (word)*/ typedef signed short sh; /* 16 bit signed integer (halfword)*/ typedef unsigned short uh; /* 16 bit unsigned integer (halfword)*/ typedef signed char sb; /* 8 bit sign[...]

APPENDICES APPENDICES-8 M32R-FPU Software Manual (Rev.1.01) Appendix 3 Pipeline Processing Appendix 3.1 Instructions and Pipeline Processing Appendix Figure 3.1.1 shows each instruction type and the pipeline process. APPENDIX 3 Appendix 3 Pipeline Processing IF D E MEM2 MEM1 WB Pipeline Stage Pipeline Stage Pipeline Stage ■ Load/Store instruction[...]

APPENDICES APPENDICES-9 M32R-FPU Software Manual (Rev.1.01) The overview of each pipeline stage is shown below. ● IF stage (instruction fetch stage) The instruction fetch (IF) is processed in this stage. There is an instruction queue and instructions are fetched until the queue is full regardless of the completion of decoding in the D stage. If t[...]

APPENDICES APPENDICES-10 M32R-FPU Software Manual (Rev.1.01) Appendix Figure 3.2.1 Pipeline Flow with no Stall (1) Appendix 3.2 Pipeline Basic Operation (1) Pipeline Flow with no Stall The following diagram shows an ideal pipeline flow that has no stall and executes each instruction in 1 clock cycle. (Since this is just an ideal case, all instructi[...]

APPENDICES APPENDICES-11 M32R-FPU Software Manual (Rev.1.01) Appendix Figure 3.2.2 Pipeline Flow with no Stall (2) <Case 4> Three FPU instructions continue consecutively with no register dependency IF D E1 WB FADD R0,R5,R6 FSUB R1,R6,R7 IF D E2 E1 WB E2 E1 WB E2 E1 WB E2 IF D FMUL R2,R7,R8 FCMP R0,R0,R3 IF D IF D EA WB FMADD R0,R5,R6 FMADD R1[...]

APPENDICES APPENDICES-12 M32R-FPU Software Manual (Rev.1.01) (2) Pipeline Flow with Stalls A pipeline stage may stall due to execution of a process or branch instruction. The following diagrams show typical stall cases. <Case 1> An instruction which requires several cycles is executed in E IF D E WB DIV R1,R2 E E IF D stall WB ADD R3,R4 E sta[...]

APPENDICES APPENDICES-13 M32R-FPU Software Manual (Rev.1.01) Appendix Figure 3.2.4 Pipeline Flow with Stalls (2) <Case 3> A branch instruction is executed (except for the case in which no branch occurs at a conditional branch instruction) IF D E WB Branch Instruction IF D WB E IF D WB E stall stall stall IF D WB E stall IF D Bypass process br[...]

APPENDICES APPENDICES-14 M32R-FPU Software Manual (Rev.1.01) Appendix Figure 3.2.5 Pipeline Flow with Stalls (3) <Case 6> FPSR is accessed by an MVFC instruction after the FPU instruction is executed <Case 7> The operation result of the FPU instruction is used by the subsequent instruction IF D E1 WB FADD R0,R1,R2 IF D WB E E2 MVFC R3, [...]

APPENDICES APPENDICES-15 M32R-FPU Software Manual (Rev.1.01) Appendix Figure 3.2.6 Pipeline Flow with Stalls (4) <Case 8> The FPU and integer instructions run consecutively (with no register dependency) IF D E WB IF D WB E2 DW B E stall IF D E2 WB E1 E1 stall IF <Case 9> The FPU and integer instructions run consecutively (with register [...]

APPENDICES APPENDICES-16 M32R-FPU Software Manual (Rev.1.01) Appendix Figure 3.2.7 Pipeline Flow with Stalls (5) <Case 12> The FPU and FMADD/FMSUB instructions run consecutively (with no register dependency) IF D E1 E2 WB IF D WB E2 DW B E2 E1 stall IF D E2 WB EA EM EA EM stall IF <Case 13> The FPU and FMADD/FMSUB instructions run conse[...]

APPENDICES APPENDICES-17 M32R-FPU Software Manual (Rev.1.01) Appendix 4 Instruction Execution Time Normally, the E stage is considered as representing as the instruction execution time, however, because of the pipeline processing the execution time for other stages may effect the total instruction execution time. In particular, the IF, D, and E sta[...]

APPENDICES APPENDICES-18 M32R-FPU Software Manual (Rev.1.01) Appendix 5 IEEE754 Specification Overview The following is a basic overview of the IEEE754 specification. M32R-FPU fulfills the IEEE754 requirements through a combination of software and hardware features. Appendix 5.1 Floating Point Formats The following describes the floating-point form[...]

APPENDICES APPENDICES-19 M32R-FPU Software Manual (Rev.1.01) APPENDIX 5 Appendix 5 IEEE754 Specification Overview Appendix Table 5.1.1 Single Precision Floating-Point Bit Values Exponent Expressed value Before adding bias After adding bias ( =0111 1111) 0111 1111 (+127) 1111 1110 Normalized number • • • • • • (The absolute value can be [...]

APPENDICES APPENDICES-20 M32R-FPU Software Manual (Rev.1.01) APPENDIX 5 Appendix 5 IEEE754 Specification Overview Appendix 5.2 Rounding The following 4 rounding modes are specified by IEEE754. Appendix Table 5.2.1 Four Rounding Modes Rounding Mode Operation Round to Nearest (default) Assuming an infinite range of precision, round to the best approx[...]

APPENDICES APPENDICES-21 M32R-FPU Software Manual (Rev.1.01) (2) Underflow Exception (UDF) The exception occurs when the absolute value of the operation result is less then the largest describable precision in the floating-point format. Appendix Table 5.3.2 shows the operation results when a UDF occurs. Appendix Table 5.3.2 Operation Results due to[...]

APPENDICES APPENDICES-22 M32R-FPU Software Manual (Rev.1.01) APPENDIX 5 Appendix 5 IEEE754 Specification Overview (5) Invalid Operation Exception (IVLD) The exception occurs when an invalid operation is executed. Appendix Table 5.3.5 shows operation results and the respective conditions in which each IVLD occurs. Appendix Table 5.3.5 Operation Resu[...]

APPENDICES APPENDICES-23 M32R-FPU Software Manual (Rev.1.01) Appendix 6 M32R-FPU Specification Supplemental Explanation Appendix 6.1 Operation Comparision: Using 1 instruction (FMADD or FMSBU) vs. two instructions (FMUL and FADD) The following is an explanation of the differences between an operation using just one instruction (FMADD or FMSUB) and [...]

APPENDICES APPENDICES-24 M32R-FPU Software Manual (Rev.1.01) (1) Overflow occurs in Step 1 <When EO = 0, EX = 0: OVF and IXCT occur> Type of R0 Condition FMUL + FADD Operation FMADD Operation Normalized – R0 = OVF immediate R0 = OVF immediate number, 0 value (Note 1) + R0 value (Note 2) Infinity when OVF immediate value EV=0 IVLD occurs sam[...]

APPENDICES APPENDICES-25 M32R-FPU Software Manual (Rev.1.01) (2) When underflow occurs in Step 1 <When EU = 0, DN = 1: UDF occurs> Type of R0 Condition FMUL + FADD Operation FMADD Operation Normalized – R0 = R0 + 0 Same as left number, 0, Infinity Denormalized – R0 = 0 Same as left number QNaN – R0 = maintained (QNaN) Same as left SNaN [...]

APPENDICES APPENDICES-26 M32R-FPU Software Manual (Rev.1.01) APPENDIX 6 Appendix 6 M32R-FPU Specification Supplemental Explanation (3) When Invalid Operation Exception occurs in Step 1 ■ If at least one of [R1, R2] is an SNaN <When EV = 0: IVLD occurs> Type of R0 Condition FMUL + FADD Operation FMADD Operation Normalized – R0 = R3 Same as[...]

APPENDICES APPENDICES-27 M32R-FPU Software Manual (Rev.1.01) (4) When Inexact Operation Exception occurs in Step 1 ■ If an Inexact Operation occurs due to rounding: <When EX = 0: IXCT occurs> Type of R0 Condition FMUL + FADD Operation FMADD Operation Normalized – R0 = rounded value of Same as left number, 0, R1*R2 + R0 Infinity Denormaliz[...]

APPENDICES APPENDICES-28 M32R-FPU Software Manual (Rev.1.01) APPENDIX 6 Appendix 6 M32R-FPU Specification Supplemental Explanation Appendix 6.2 Rules concerning Generation of QNaN in M32R-FPU The following are rules concerning generating a QNaN as an operation result. Instructions that generate NaNs as operation results are FADD, FSUB, FMUL, FDIV, [...]

APPENDICES APPENDICES-29 M32R-FPU Software Manual (Rev.1.01) Appendix 7 Precautions Appendix 7.1 Precautions to be taken when aligning data When aligning or allocating the data area following the code area in a program, the alignment must be done from an address that has an adjusted word alignment. If the data area is aligned or allocated without a[...]

APPENDICES APPENDICES-30 M32R-FPU Software Manual (Rev.1.01) This page left blank intentionally. APPENDIX 7 Appendix 7 Precautions[...]

INDEX[...]

INDEX INDEX-2 M32R-FPU Software Manual (Rev.1.01) Symbol #imm 1-15, 3-2 @(disp,R) 1-15, 3-2 @+R 1-15, 3-2 @-R 1-15, 3-2 @R 1-15, 3-2 @R+ 1-15, 3-2 A Accumulator(ACC) 1-11 Addressing Mode 1-15, 3-2 Arithmetic operation instructions 2-4 ADD 3-6 ADD3 3-7 ADDI 3-8 ADDV 3-9 ADDV3 3-10 ADDX 3-11 NEG 3-86 SUB 3-113 SUBV 3-114 SUBX 3-115 B Backup PC(BPC) 1[...]

INDEX INDEX-3 M32R-FPU Software Manual (Rev.1.01) L Load/store instructions 2-2 LD 3-61 LDB 3-63 LDH 3-64 LDUB 3-66 LDUH 3-67 LOCK 3-68 ST 3-109 STB 3-111 STH 3-112 UNLOCK 3-117 Logic operation instructions 2-5 AND 3-12 AND3 3-13 NOT 3-88 OR 3-89 OR3 3-90 XOR 3-119 XOR3 3-120 M Multiply/divide instructions 2-5 DIV 3-34 DIVU 3-35 MUL 3-73 REM 3-95 R[...]

INDEX INDEX-4 M32R-FPU Software Manual (Rev.1.01) R R 1-15, 3-2 Register direct(R or CR) 1-15, 3-2 Register indirect(@R) 1-15, 3-2 Register indirect and register update 1-15, 3-2 Register relative indirect(@(disp, R)) 1-15, 3-2 S Shift instructions 2-5 SLL 3-100 SLL3 3-101 SLLI 3-102 SRA 3-103 SRA3 3-104 SRAI 3-105 SRL 3-106 SRL3 3-107 SRLI 3-108 S[...]

RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER SOFTWARE MANUAL M32R-FPU Publication Data : Rev.1.00 Jan 08, 2003 Rev.1.01 Oct 31, 2003 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2003. Renesas Technology Corp., All rights reserved. Printed in Japan.[...]

M32R Family Software Manual 2- 6 -2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan[...]