Renesas SH7641 manual

Revision Date: Se p . 14 , 2005 32 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series SH7641 HD6417641 Rev.4.00 REJ09B0023-0400 SH7641 The revision list can be viewed directly by  clicking the title page.  The revision list summarizes the locations of  revisions and additions. Details should a[...]

Rev. 4.00 Sep. 14, 2005 Page ii of l[...]

Rev. 4.00 Sep. 14, 2005 Page iii of l 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a t[...]

Rev. 4.00 Sep. 14, 2005 Page iv of l General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not con nect anythin g to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pi ns or to red uce noise. If s omething is c onnected to the NC pi ns, the operation of the[...]

Rev. 4.00 Sep. 14, 2005 Page v of l Important Notice on the Quality Assurance for this LSI Although th e wafer process and assembly process of th is LSI are entrusted to the external silico n foundries, the quality of this LS I is guaranteed for the custo mers under the quality assurance system of our company. However, if it is clear that our compa[...]

Rev. 4.00 Sep. 14, 2005 Page vi of l Configuration of This Manual This manual comprises th e follo wing items: 1. General Precautions on Handling of Product 2. Config uration of This Man ual 3. Preface 4. Conte nts 5. Overvi ew 6. Description of Functi onal Modules • CPU and System-C ontrol M odules • On-Chip Peripheral M odules The configurat [...]

Rev. 4.00 Sep. 14, 2005 Page vii of l[...]

Rev. 4.00 Sep. 14, 2005 Page viii of l Preface The SH7641 RISC (Reduced Inst ruction Set C om put er ) mi croc omputer incl udes a Renesas Technology ori ginal RISC CPU as its core, and the pe ripheral funct ions requi red to confi gure a system. Target Users: This manual was written for users who will be u s ing th is LSI in th e design of applica[...]

Rev. 4.00 Sep. 14, 2005 Page ix of l Rules: Register name: The following notat i o n is used for cases when the same or a similar function, e.g. serial communication, is implemented on mor e th an one cha nnel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB (most significant bit) is on the left and the LSB (least si[...]

Rev. 4.00 Sep. 14, 2005 Page x of l Abbreviations ADC Analog to digital converter ALU Arithmetic logic unit bpp bits per pixel bps bits per sec ond BSC Bus state controller CODEC Code r-decode r CPG Clock pulse generator CPU Central proces sing unit CRC Cyclic redundancy check DMAC Direct memory access control ler DSP Digital signal processor ESD E[...]

Rev. 4.00 Sep. 14, 2005 Page xi of l USB Universal serial bus WDT Watch dog timer[...]

Rev. 4.00 Sep. 14, 2005 Page xii of l[...]

Rev. 4.00 Sep. 14, 2005 Page xiii of l Contents Section 1 Overview ................................................................................................1 1.1 Features ....................................................................................................................... ........... 1 1.2 Block Diagram ....................[...]

Rev. 4.00 Sep. 14, 2005 Page xiv of l 3.1.5 Shift Opera tions .................................................................................................... 109 3.1.6 Most Significa nt Bit De tection Oper ation ............................................................ 112 3.1.7 Rounding Ope ration...........................................[...]

Rev. 4.00 Sep. 14, 2005 Page xv of l 6.2 Register Desc riptions ......................................................................................................... 1 66 6.2.1 Standby C ontrol Regi ster (ST BCR)...................................................................... 166 6.2.2 Standby C ontrol Regist er 2 (ST BCR2) ..............[...]

Rev. 4.00 Sep. 14, 2005 Page xvi of l 9.1.1 TRAP A Exception Regi ster (TRA) ...................................................................... 198 9.1.2 Exce ption Event Regi ster (EXPE VT) ................................................................... 199 9.1.3 Inter rupt Event Regist er 2 (INTEVT2) ......................................[...]

Rev. 4.00 Sep. 14, 2005 Page xvii of l 10.6.2 Timing to Clear an Interrupt So urce ..................................................................... 240 Section 11 User Break Controller (UBC) ..........................................................241 11.1 Features ..............................................................................[...]

Rev. 4.00 Sep. 14, 2005 Page xviii of l 12.4.4 SDRAM Control Regi ster (SD CR)....................................................................... 314 12.4.5 Refresh Timer Control/Statu s Register (R TC SR) ................................................. 317 12.4.6 Refresh Timer Coun ter (RTC NT)................................................[...]

Rev. 4.00 Sep. 14, 2005 Page xix of l Section 14 U Memory ........................................................................................451 14.1 Features ....................................................................................................................... ....... 451 14.2 U Memory Ac cess from CPU .......................[...]

Rev. 4.00 Sep. 14, 2005 Page xx of l 16.3.9 I 2 C Bus Shift Regist er (ICDRS) ............................................................................ 487 16.3.10 NF2CYC Regi ster (NF2CYC) .............................................................................. 487 16.4 Operation ...........................................................[...]

Rev. 4.00 Sep. 14, 2005 Page xxi of l 18.3.7 Timer General Regi ster (T GR) ............................................................................. 553 18.3.8 Timer Start Regist er (TSTR) ................................................................................ 554 18.3.9 Timer Synchro Regi ster (TSY R) ................................[...]

Rev. 4.00 Sep. 14, 2005 Page xxii of l 18.7.13 Buffer Operation Se tting in Complement ary PWM Mode ................................... 636 18.7.14 Reset Sync PWM Mode Buffer Opera tion and Compare Match Flag .................. 637 18.7.15 Overflow Flags in Rese t Sync PWM Mode .......................................................... 638 18.7.16 [...]

Rev. 4.00 Sep. 14, 2005 Page xxiii of l 19.3.12 Line Status Regist er (SCLSR ) .............................................................................. 720 19.4 Operation ...................................................................................................................... ..... 721 19.4.1 Overview.............................[...]

Rev. 4.00 Sep. 14, 2005 Page xxiv of l 20.4.4 EP1 Bulk-OUT Transfer (Dual FIFOs) ................................................................ 774 20.4.5 EP2 Bulk-IN Transfer (Dual FIFOs) .................................................................... 776 20.4.6 EP3 Interrupt-IN Transfer......................................................[...]

Rev. 4.00 Sep. 14, 2005 Page xxv of l 21.3.6 Input Sampling and A/D C onversion Time .......................................................... 810 21.4 Interrupt an d DMAC Tr a nsfer Request.............................................................................. 812 21.5 Definitions of A/D Co nversion Accuracy ...............................[...]

Rev. 4.00 Sep. 14, 2005 Page xxvi of l 23.4.2 Port D Data Regi ster (PDDR ) ............................................................................... 850 23.5 Port E ......................................................................................................................... ........ 851 23.5.1 Register Desc ription ..............[...]

Rev. 4.00 Sep. 14, 2005 Page xxvii of l 25.3.12 H-UDI Related Pi n Timing ................................................................................... 960 25.3.13 USB Module Signa l Timi ng ................................................................................. 962 25.3.14 USB Transceive r Timing ...................................[...]

Rev. 4.00 Sep. 14, 2005 Page xxviii of l[...]

Rev. 4.00 Sep. 14, 2005 Page xxix of l Figures Section 1 Overview Figure 1.1 Block Di agram .............................................................................................................. 7 Figure 1.2 Pin A ssignments (BG A-256)......................................................................................... 8 Section 2 CPU F[...]

Rev. 4.00 Sep. 14, 2005 Page xxx of l Figure 3.14 Data Tran sfer Operatio n Flow ................................................................................. 119 Figure 3.15 Single Data-Trans fer Operation Flow (Word)......................................................... 120 Figure 3.16 Single Data-Transfe r Operation Flow (Longword) ......[...]

Rev. 4.00 Sep. 14, 2005 Page xxxi of l Section 11 User Break Controller (UBC ) Figure 11.1 Block Diagram of User Break Contr oller ................................................................ 242 Section 12 Bus State Controller (BSC) Figure 12.1 BSC Func tional Block Di agram .....................................................................[...]

Rev. 4.00 Sep. 14, 2005 Page xxxii of l Figure 12.28 Single Writ e Timi ng (Bank Active, Differe nt Row Addr esses in the Sam e Bank) ................................ 364 Figure 12.29 Auto-Refresh Tim ing ............................................................................................ 3 66 Figure 12.30 Se lf-Refres h Timing ............[...]

Rev. 4.00 Sep. 14, 2005 Page xxxiii of l Figure 13.8 Exam ple of DMA T ransf er Tim ing in Single Address M ode.................................. 436 Figure 13.9 DMA Transfer Exam pl e in the Cycle-Steal Norm al Mode (Dual Address, DREQ Low L evel De tection) ......................................................... 437 Figure 13.10 Example of DMA [...]

Rev. 4.00 Sep. 14, 2005 Page xxxiv of l Figure 16.9 Slave Tra nsmit Mode Operation Tim ing (1) ........................................................... 494 Figure 16.10 Slave Transm it Mode Operation Timing (2) ......................................................... 495 Figure 16.11 Slave Receive Mode Operation Timing (1)......................[...]

Rev. 4.00 Sep. 14, 2005 Page xxxv of l Figure 18.20 Exam ple of PW M Mode Setting Pr ocedure .......................................................... 578 Figure 18.21 Exam ple of PWM Mode Opera tion (1) ................................................................. 578 Figure 18.22 Exam ple of PWM Mode Opera tion (2) ..........................[...]

Rev. 4.00 Sep. 14, 2005 Page xxxvi of l Figure 18. 53 Exampl e of Output P hase Swit ching by Mea ns of UF, VF, WF Bit Setti ngs (2) ............................................................................................... 615 Figure 18.54 Count Tim ing in Internal Clock Ope ration............................................................ 6[...]

Rev. 4.00 Sep. 14, 2005 Page xxxvii of l Figure 18.90 Error Occurre nce in Norm al Mode, Reco very in Reset -Synchrono us PWM Mode........................................................................................................... 649 Figure 18.91 Error Occ urrence in PWM Mode 1, Recovery in Normal Mode........................... 650 Figure [...]

Rev. 4.00 Sep. 14, 2005 Page xxxviii of l Figure 18.117 Output-Level Detection Op eration ...................................................................... 682 Section 19 Serial Communicati on Interface w ith FIFO (SCIF) Figure 19.1 Bloc k Diagram of SCIF..........................................................................................[...]

Rev. 4.00 Sep. 14, 2005 Page xxxix of l Figure 20.16 EP 2 PKTE O peration ............................................................................................ 78 5 Figure 20.17 Example of USB Functio n Module Ext ernal Circui try (For On-Chip Transceiver).................................................................................... 78[...]

Rev. 4.00 Sep. 14, 2005 Page xl of l Section 25 Electrical Characteristics Figure 25.1 Powe r-On Sequence ................................................................................................ 908 Figure 25.2 EXTAL Clock Input Timing ................................................................................... 917 Figure 25.3 CKIO C[...]

Rev. 4.00 Sep. 14, 2005 Page xli of l Figure 25.27 Synchronous DRA M Single Write Bus Cycle (Auto Precharge, TR WL = 1 Cy cle) ..................................................................... 939 Figure 25.28 Synchronous DRA M Single Write Bus Cycle (Auto Precharge, WTRCD = 2 Cycles, TR WL = 1 Cycle) ...........................................[...]

Rev. 4.00 Sep. 14, 2005 Page xlii of l Figure 25.48 MTU Cl ock Input Tim ing ..................................................................................... 956 Figure 25.49 POE In put/Output Tim ing ..................................................................................... 957 Figure 25.50 I 2 C Bus Interface Input/O utput Timing [...]

Rev. 4.00 Sep. 14, 2005 Page xliii of l Tables Section 1 Overview Table 1.1 Features ..................................................................................................................... 1 Table 1.2 Pin functions ............................................................................................................. 9 Table 1.3[...]

Rev. 4.00 Sep. 14, 2005 Page xliv of l Table 2.31 DSP O peration Instructions .................................................................................... 90 Table 2.32 DC Bit Update Definitions ..................................................................................... 96 Table 2.33 Exam ples of NOPX a nd NOPY Instruction Codes .[...]

Rev. 4.00 Sep. 14, 2005 Page xlv of l Table 7.8 LRU and Way Replacement (when W2LO CK = 1 and W3LOCK = 1) ............... 186 Section 8 X/Y Memory Table 8.1 X/Y Mem ory Speci fications ................................................................................. 193 Section 9 Exception Handling Table 9.1 Exception E vent Vectors................[...]

Rev. 4.00 Sep. 14, 2005 Page xlvi of l Table 12.10 Re lationshi p between B SZ1, 0, A2/ 3ROW1, 0, and Address Multiplex Output (3 ) ........................................................................... 344 Table 12.11 Re lationshi p between B SZ1, 0, A2/ 3ROW1, 0, and Address Multiplex Ou tput (4)- 1...........................................[...]

Rev. 4.00 Sep. 14, 2005 Page xlvii of l Section 14 U Memory Table 14.1 U Mem ory Speci fications ..................................................................................... 451 Section 15 User Debugging Inter face (H-UDI) Table 15.1 Pin Configurat ion ........................................................................................[...]

Rev. 4.00 Sep. 14, 2005 Page xlviii of l Table 18.27 Out put Level Sel ect Function ........................................................................... 558 Table 18.28 Out put level Sel ect Function............................................................................. 560 Table 18.29 Register Com binations in Buffer Operation .......[...]

Rev. 4.00 Sep. 14, 2005 Page xlix of l Table 21.4 A/D Conve rsion Time (Multi Mode and Scan Mode) .......................................... 811 Table 21.5 Interrupt a nd DMAC Tr ansfer Request ................................................................ 812 Section 22 Pin Function Controller (PFC) Table 22.1 List of Multiple xed Pins..........[...]

Rev. 4.00 Sep. 14, 2005 Page l of l Appendix Table A.1 Pin States in Reset State, Power Do wn Mode, and B us-Released States When Other Functio n is Sele cted.......................................................................... 967 Table A.2 Pin States in Reset State, Power Do wn Mode, and B us-Released States When I/O Port is Select ed ......[...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 1 of 982 REJ09B0023-0400 Section 1 Overview This LSI is a single-chip RISC microprocessor that in tegra t es a Renesas Tech nol ogy original 32 - bit SuperH RISC engine architect ure CPU with a digital s ignal processi ng (DSP) ext ension a s its core, with 16-k byt e o f cache memo r y, 1 6- k byt e [...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 2 of 828 REJ09B0023-0400 Items Specification DSP • Mixture of 16-bit and 32-bit instructions • 32-/40-bit internal data paths • Multiplier, ALU, barrel shifter and DSP registe r • Large DSP data registers  Six 32-bit data registers  Two 40-bit data registers • Extended Harvard Architec[...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 3 of 982 REJ09B0023-0400 Items Specification Cache memory • 16-kbyte cache, mixed instruction/data • 256 entries, 4-way set associative, 16-byte block le ngth • Write-back, write-through, LRU replac ement algorithm • 1-stage write-back buffer • Maximum 2 ways of the cache can be locked X/Y m[...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 4 of 828 REJ09B0023-0400 Items Specification Bus state controller (BSC) • Physical address space div ided into eight areas, four areas (area 0, areas 2 to 4), each a maximum of 64 Mbytes and other four areas (areas 5A, 5B, areas 6A, 6B), each a maximum of 32 Mbytes • The following features settabl[...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 5 of 982 REJ09B0023-0400 Items Specification Advanced user debugger (AUD) • Six output pins • Trace of branch source/destination address • Window data trace function • Full trace function  All trace data can be output by stalling the C PU even when the trace data is not output in time • R[...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 6 of 828 REJ09B0023-0400 Items Specification Compare match timer (CMT) • 16-bit counter × 2 channels • Selection of four clocks • Interrupt request or DMA transfer request can be gener ated by compare-match Serial communication interface with FIFO (SCIF) • 3 channels • Asynchronous mode or [...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 7 of 982 REJ09B0023-0400 1.2 Block Diagram The block diagram of thi s LSI is sh own in fi gure1. 1. X/Y Memory SH3 CPU MTU CMT SCIF IIC2 H-UDI USB DSP UBC AUD ADC BSC DMAC U Memory CACHE INTC CPG/ WDT External Bus Interface Y-BUS I-BUS X-BUS L-BUS Peripheral-BUS I/O port [Legend] ADC: AUD: BSC: CACHE:[...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 8 of 828 REJ09B0023-0400 1.3 Pin Assignments The pin assignments of this LSI is shown in figure 1.2 . 1 A B C D E F G H J K L M N P V W Y R T U A B C D E F G H J K L M N P V W Y R T U 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 0 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 9 20 SH7641 BGA-256 ([...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 9 of 982 REJ09B0023-0400 1.4 Pin functions Table 1.2 sum marizes the pi n functions. Table 1.2 Pin functions No. (BGA256) Pin Name Description B2 D7 Data bus C2 D6 Data bus D2 D5 Data bus B1 D4 Data bus E2 D3 Data bus E3 D2 Data bus C1 VssQ Ground for I/O circuits (0V) D3 D1 Data bus D1 VccQ Power sup[...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 10 of 828 REJ09B0023-0400 No. (BGA256) Pin Name Description J1 DPLS/PTB[8] USB D+ input from Receiver/Port B K3 Vss Ground (0V) K2 A18 Address bus K4 Vcc Power supply (1.8V) K1 A19/PTA[8] Address bus/Port A L1 A20/PTA[9] Address bus/Port A L4 A21/PTA[10] Address bus/Port A M1 A22/PTA[11] Address bus/P[...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 11 of 982 REJ09B0023-0400 No. (BGA256) Pin Name Description W1 VccQ Power supply for I/O circuits (3.3V) V3 IRQ3 /PTJ[3] External interrupt request/Port J T2 IRQ4 /PTJ[4] External interrupt request/Port J T3 IRQ5 /PTJ[5] External interrupt request/Port J U3 IRQ6 /PTJ[6] External interrupt request/Port[...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 12 of 828 REJ09B0023-0400 No. (BGA256) Pin Name Description W9 TIOC3C/PTE[5] Timer input output 3C/Port E U9 TIOC3A/PTE[7] Timer input output 3A/Port E Y9 TIOC2B/PTE[8] Timer input output 2B/Port E V10 Vss Ground (0V) W10 TIOC2A/PTE[9] Timer input output 2A/Port E U10 Vcc Power supply (1.8V) Y10 TIOC1[...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 13 of 982 REJ09B0023-0400 No. (BGA256) Pin Name Description Y18 VssQ Ground for I/O circuits (0V) W17 PTF[7] Port F Y19 VccQ Power supply for I/O circuits (3.3V) V18 PTG[8] Port G W16 SCL/PTG[9] Serial clock/Port G * 2 V16 SDA/PTG[10] Serial data/Port G * 2 V17 PTG[11] Port G W18 PTG[12] Port G Y20 PT[...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 14 of 828 REJ09B0023-0400 No. (BGA256) Pin Name Description N20 RESETP Power − on Reset request M18 VccQ Power supply for I/O circuits (3.3V) M19 VssQ Ground for I/O circuits (0V) M17 XTAL Clock oscillator pin M20 EXTAL External clock/Crystal oscillator pin L18 Vss Ground (0V) L19 RESETM Manual Rese[...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 15 of 982 REJ09B0023-0400 No. (BGA256) Pin Name Description F19 DACK0 /PTC[11] DMA request acknowled ge/Port C D17 Vss Ground (0V) C20 VssQ Ground for I/O circuits (0V) D19 DACK1 /PTC[12] DMA request acknowledge/Port C B20 VccQ Power supply for I/O circuits (3.3V) C18 D31/PTD[15] Data bus/Port D E19 D[...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 16 of 828 REJ09B0023-0400 No. (BGA256) Pin Name Description A14 WE0 /DQMLL D7 to D0 Select signal/DQM (SDRAM) D13 VssQ Ground for I/O circuits (0V) A13 WE1 /DQMLU D15 to D8 Select signal/DQM (SDRAM) C12 CASU /PTA[5] CAS for Upper-32M-byte address/Port A B12 WE3 /DQMUU/AH D31 to D24 Select signal/DQM ([...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 17 of 982 REJ09B0023-0400 No. (BGA256) Pin Name Description C6 A1 Address bus A4 A0/PTA[0] Address bus/Port A D5 Vcc Power supply (1.8V) B6 D15 Data bus D4 Vss Ground (0V) A3 VssQ Ground for I/O circuits (0V) B4 D14 Data bus A2 VccQ Power supply for I/O circuits (3.3V) C3 D13 Data bus B5 D12 Data bus [...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 18 of 828 REJ09B0023-0400 Table 1.3 lists the pin fu nct i ons. Table 1.3 Pin Functions Classification Symbol I/O Name Function Vcc I Power supply Power supply for the internal LSI. Connect all Vcc pins to the system. There will be no operation if any pins are open. Vss I Ground Ground p in. Connect a[...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 19 of 982 REJ09B0023-0400 Classification Symbol I/O Name Function CKIO O System clock Supplies the system clock to external devices. Clock CKIO2 O System clock Supplies the sy stem clock to external devices. Operating mode control MD3, MD2, MD0 I Mode set Sets the operating mode. Do n ot change values[...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 20 of 828 REJ09B0023-0400 Classification Symbol I/O Name Function Bus control RD/ WR O Read/write Read/write signal BS O Bus start Bus-cycle start WE3 /DQMUU/ AH O Byte specification Indicates that bits 31 to 24 of the data in the external memory or device are being written. Selects D31 to D24 when SD[...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 21 of 982 REJ09B0023-0400 Classification Symbol I/O Name Function DREQ0 , DREQ1 I DMA-transfer request Input pin for external requests for DMA transfer. DACK0 , DACK1 O DMA-transfer request receive Output pin for request receive, in response to external requests for DMA transfer. Direct memory access [...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 22 of 828 REJ09B0023-0400 Classification Symbol I/O Name Function TCLKA TCLKB TCLKC TCLKD I Clock input External clock input pins TIOC0A TIOC0B TIOC0C TIOC0D I/O Input capture/ output compare match The TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins. TIOC1A TIOC1B I/O Input [...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 23 of 982 REJ09B0023-0400 Classification Symbol I/O Name Function XVDATA I Data input Input pin for receive data from USB differential receiver USB function module DPLS I D+ input Input pin for D+ signal from USB receiver DMNS I D- input Input pin for D- signal from USB receiver TXDPLS O D+ output D+ [...]

Section 1 Overview Rev. 4.00 Sep. 14, 2005 Page 24 of 828 REJ09B0023-0400 Classification Symbol I/O Name Function PTA14 to PTA0 I/O General purpose port 15 bits general purpose inp ut/output pins PTB8 to PTB0 I/O General purpose port 9 bits general purpose input/output pins PTC15 to PTC0 I/O General purpose port 16 bits general purpose inp ut/outpu[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 25 of 982 REJ09B0023-0400 Section 2 CPU 2.1 Registers This LSI has the same registers as the SH-3 . In addition, this LSI also suppor ts the same DSP- related registers as in the SH-D SP. The basic software-acc essible registers are divided in to four distinct groups: • General registers • Control regi[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 26 of 982 REJ09B0023-0400 The system registers are accessed by the LDS/STS instructions (the PC is software -accessible, but is included he re because its c ontents are saved in, a nd restored from, SPC i n exception handling). The system registers are: • MACH : Multiply and accumulate high register • [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 27 of 982 REJ09B0023-0400 31 R0_BANK1 * 1 , * 2 R1_BANK1 * 2 R2_BANK1 * 2 R3_BANK1 * 2 R4_BANK1 * 2 R5_BANK1 * 2 R6_BANK1 * 2 R7_BANK1 * 2 R0_BANK0 * 1 , * 3 R1_BANK0 * 3 R2_BANK0 * 3 R3_BANK0 * 3 R4_BANK0 * 3 R5_BANK0 * 3 R6_BANK0 * 3 R7_BANK0 * 3 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL VBR PR [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 28 of 982 REJ09B0023-0400 39 A0G A1G 32 31 A0 A1 M0 M1 X0 X1 Y0 Y1 DSR MS ME MOD 0 (c) DSP mode register configuration (DSP = 1) Figure 2.2 Register Confi gura ti on in Each Pr ocessin g Mode (2) Register values after a reset are shown in table 2 .1. Table 2.1 Initial Reg ister Values Type Registers Initia[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 29 of 982 REJ09B0023-0400 2.1.1 General Registers There are sixte en 32-bi t general regi sters (Rn ), designated R 0 to R15. The general re gisters a re used for dat a processing and address calcula tion. With SuperH microcomputer typ e instructions, R0 is used as an index register. With a number of instr[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 30 of 982 REJ09B0023-0400 On the other hand, regi st ers R 2 to R9 are also use d for DSP data addres s cal cul at i on wh en DSP extension is en abled (see fig ure 2.4). Ot her symbol s that represe nt the pur pose of the registers in DSP type instructions is show n in [ ]. 31 R0 R1 R2 [As] R3 [As] R4 [As[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 31 of 982 REJ09B0023-0400 Ay1: .REG (R7) Iy: .REG (R9) As0: .REG (R4) ; This is optional, if another alias is required for single data transfer. As1: .REG (R5) ; This is optional, if another alias is required for single data transfer. As2: .REG (R2) As3: .REG (R3) Is: .REG (R8) ; This is optional, if anoth[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 32 of 982 REJ09B0023-0400 and end addres ses of a loop (t he conte nts of the RS and RE registers are sl ightly di fferent from t he actual loop start and end addresses). The modulo register, MOD, is provided to im plement modulo addressing for circular data buffering. MOD hol ds the modul o start ad dress[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 33 of 982 REJ09B0023-0400 31 0 1 RC 0-0 DSP DM Y DM X M Q I3 I2 I1 I0 RF1 RF0 ST RB BL 28 27 16 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SR (Status register) RB bit: Register bank bit; used to define the general registers . RB = 1: R0_BANK1 to R7_BANK1 are used as general registers. R0_BANK0 to R7_BANK0 accessed[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 34 of 982 REJ09B0023-0400 SSR 31 0 Sav ed status register (SSR) SPC 31 0 Sav ed program counter (SPC) GBR 31 0 Global base register VBR 31 0 V ector base register RS 31 0 Repeat star t register RE 31 0 Repeat end register ME MS 31 16 15 0 Modulo register MOD ME: Modulo end address, MS: Modulo star t addres[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 35 of 982 REJ09B0023-0400 2.1.3 System Registers This LSI has four system re gisters, MACL , MACH, PR and PC ( figure 2.6) . MACH MACL 31 0 PR 31 0 PC 31 0 Multiply and accumulate high and low registers (MACH and MACL) Store the results of multiplicationand accumulation operations. Procedure register (PR) [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 36 of 982 REJ09B0023-0400 When data is read into the upp er 16 bits of a register (bits 31 to 16), the low er 16 bits of the register (bits 15 to 0) are automa tically cleared. A0 and A1 can be st ored in the X or Y m emory by this operatio n, but n o other re gisters can be stored. The third ki nd of oper[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 37 of 982 REJ09B0023-0400 Table 2.2 Dest ination Regi ster in DSP Instructions Guard Bits Register Bits Registers Instructions 39 32 31 16 15 0 A0, A1 DSP Fixed-point, PSHA, PMULS Sign-extended 40-bit result Integer, PDMSB Sign-extended 24-bit res ult Cleared Logical, PSHL Cleared 16-bit result Cleared Dat[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 38 of 982 REJ09B0023-0400 Table 2.3 Source Register in DSP Operations Guard Bits Register Bits Registers Instructions 39 32 31 16 15 0 A0, A1 DSP Fixed-point, PDMSB, PSHA 40-bit data Integer 24-bit data Logical, PSHL, PMULS 16-bit data MOVX/Y.W, MOVS.W 16-bit data Data transfer MOVS.L 32-bit data A0G, A1G [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 39 of 982 REJ09B0023-0400 31 32 39 A0 A0G A1G A1 M0 M1 X0 X1 Y0 Y1 0 1 2 3 4 5 6 7 DC CS [2:0] V N Z GT 8 31 0 (a) DSP Data Registers (b) DSP Status Register (DSR) Reset status DSR: All zeros Others: Undefined Figure 2.7 DSP Registers A0G 32 0 39 31 16 A0 A1 M0 M1 X0 X1 Y0 Y1 0 7 A1G DSR 16 bits 16 bits 8 [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 40 of 982 REJ09B0023-0400 The DSP unit has one contr ol register, the DSP status re gister (DSR). DSR ho lds the status of DSP data operation results (zer o, negative, a nd so on) an d has a DC bit which i s similar t o the T bit in the CPU. The DC bit indicates one of the status fla gs. A DSP dat a proces[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 41 of 982 REJ09B0023-0400 Table 2.4 DSR Register Bi ts Bits Name (Abbreviation) Function 31 to 8 Reserved bits 0: Always read as 0; always use 0 as the writ e value 7 Signed Greater Than bit (GT) Indicates that the operation re sult is positive (except 0), or that operand 1 is greater than operand 2 1: Ope[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 42 of 982 REJ09B0023-0400 DSR is assigned as a system register and the following load/store instructions are provided: STS DSR,Rn; STS.L DSR,@-Rn; LDS Rn,DSR; LDS.L @Rn+,DSR; When DSR is read by an STS instruction, the upp er bits (bits 31 to 8) are all 0. 2.2 Data Formats 2.2.1 Register Dat a Form at (Non[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 43 of 982 REJ09B0023-0400 39 S 31 30 0 –2 8 to +2 8 – 2 –31 39 S 32 31 0 –2 23 to +2 23 – 1 39 S S 31 30 16 15 16 15 0 –1 to +1 – 2 –15 39 31 16 15 0 S 31 0 –2 15 to +2 15 – 1 16 15 31 22 0 –32 to +32 16 15 S 31 21 0 –16 to +16 16 15 S 31 30 0 –1 to +1 – 2 –31 S 31 0 –2 31 t[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 44 of 982 REJ09B0023-0400 2.2.3 Memory D ata Formats Memory data formats are classi fied into byte, word, and long word. Byte data can be accessed from any address, but an add ress error will occur if word data starting from an address other than 2n or longword data starting from an address ot her than 4n [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 45 of 982 REJ09B0023-0400 Table 2.5 Word Data Sign Extension This LSI's CPU Description Example of Other CPU MOV.W @(disp,PC),R1 ADD R1,R0 ........ .DATA.W H'1234 Sign-extended to 32 bits, R1 becomes H'00001234, and is then operated on by the ADD instruction. ADD.W #H'1234,R0 Note: Imme[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 46 of 982 REJ09B0023-0400 Table 2.7 T Bit This LSI's CPU Description Example of Other CPU CMP/GE R1,R0 BT TRGET0 BF TRGET1 If R0 ≥ R1, the T bit is set. A branch is made to TRGET0 if R0 ≥ R1, or to TRGET1 if R0 < R1. CMP.W R1,R0 BGE TRGET0 BLT TRGET1 ADD #–1,R0 CMP/EQ #0,R0 BT TRGET The T bit[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 47 of 982 REJ09B0023-0400 Table 2.9 Absolute Address Referencing Type This LSI's CPU Example of Other CPU Absolute address MOV.L @(disp,PC),R1 MOV.B @R1,R0 ........ .DATA.L H'12345678 MOV.B @H'12345678,R0 16-Bit/32-Bit Displacement: When data is referenced with a 16- or 32-bit di splacement,[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 48 of 982 REJ09B0023-0400 2.4 Instruction Formats 2.4.1 CPU Instruction Addressing Modes The following table shows add r essing modes and effective address calcula tion methods for instructions executed by th e CPU co re. Table 2.11 Addressing Modes and Effe ctive Addresses for CPU Instructions Addressing [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 49 of 982 REJ09B0023-0400 Addressing Mode Instruction Format Effective Address Calculatio n Method Calculation Formula Register indirect with displacement @(disp:4, Rn) Effective address is register Rn contents with 4-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte ), [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 50 of 982 REJ09B0023-0400 Addressing Mode Instruction Format Effective Address Calculatio n Method Calculation Formula PC-relative with displacement @(disp:8, PC) Effective address is PC with 8-bit displacement disp added. After disp is zero- extended, it is multiplied by 2 (word) or 4 (longword), accordin[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 51 of 982 REJ09B0023-0400 Addressing Mode Instruction Format Effective Address Calculatio n Method Calculation Formula Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instructio n is zero-extende d.  #imm:8 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-ext ended. [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 52 of 982 REJ09B0023-0400 X/Y Data Addressi ng : With DSP instructions , the X a nd Y data memory can be accessed simultaneousl y using t he MOVX.W an d MOVY.W i nstructions. Two addres s pointers are provided for DSP instru ctions to enable simultaneous acces s to X and Y data memory. Only pointer ad dres[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 53 of 982 REJ09B0023-0400 ALU AU R8[Ix] R4[Ax] R5[Ax] R9[Iy] R6[Ay] R7[Ay] +2 (INC) +0 (no update) +2 (INC) +0 (no update) Note: Three address processing methods: 1. Increment 2. Index register addition (Ix/Iy) 3. No increment Post-updating is used in all cases. The address pointer can be decremented by se[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 54 of 982 REJ09B0023-0400 The R8 register is the index register (Is) for the address pointer (As). Single data transfer addressing is shown in figure 2. 13. ALU R8[Is] R4[As] R5[As] –2/–4 (DEC) +2/+4 (INC) +0 (no update) R3[As] R2[As] 31 0 31 0 MAB CAB 31 0 Note: Four address processing methods: 1. No [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 55 of 982 REJ09B0023-0400 MOV.L ModAddr,Rn; Rn=ModEnd, ModStart LDC Rn,MOD; ME=ModEnd, MS=ModStart ModAddr: .DATA.W mEnd; ModEnd .DATA.W mStart; ModStart ModStart: .DATA : ModEnd: .DATA The start and end addresses are specified in MS an d ME, then the DMX or DMY bi t is set t o 1. When the X/Y data transfe[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 56 of 982 REJ09B0023-0400 An example of modulo a ddressing is give n below. MS = H'7000; ME=H'7004; R4=H'A50070008; DMX = 1; DMY = 0: (Modulo addr essing setting for address re gister Ax) As a result of the above setting s , the R4 register changes as follows. ; R4: H'A5007000 (Initial [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 57 of 982 REJ09B0023-0400 DSP Addressing Oper ations: DSP addressing o perations in t he pipeline e xecution stage (EX), including m odulo addressi ng, are shown below. if ( Operation is MOVX.W MOVY.W ) { ABx=Ax; ABy=Ay; / * memory access cycle uses ABx and ABy. The addresses to be used have not been updat[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 58 of 982 REJ09B0023-0400 2.4.3 CPU Instruction Formats Table 2.13 sho ws the instruct ion formats, a nd the mea ning of the s ource and de stination operands , for instructions executed by the CPU core. T he meaning of the operands depends on the instruction code. The fo llow ing symbols are used in th e [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 59 of 982 REJ09B0023-0400 Instruction Format Source Operand Destination Operand Sample Instruction mmmm : register direct nnnn : register direct ADD Rm,Rn nm type nnnn xxxx xxxx 15 0 mmmm mmmm : register direct nnnn : register indirect MOV.L Rm,@Rn mmmm : post- increment register indirect (multiply- and-ac[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 60 of 982 REJ09B0023-0400 Instruction Format Source Operand Destination Operand Sample Instruction d type dddd xxxx 15 0 xxxx dddd dddddddd : GBR indirect with displacement R0 (register direct) MOV.L @(disp,GBR),R0 R0 (register direct) dddddddd : GBR indirect with displacement MOV.L @R0,@(disp,GBR) ddddddd[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 61 of 982 REJ09B0023-0400 2.4.4 DSP Instruction Formats This LSI incl udes new inst ructions for digital signal proce ssing. The ne w instructi ons are of the following two kinds. 1. Memory and DSP register double and single data tr ansfer instructions (16-bit length) 2. Parallel processing instructi ons p[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 62 of 982 REJ09B0023-0400 Double and Single Data Transfer Instructions: The form at of doubl e data transfer i nstructions is shown in t able 2.14, a nd that of si ngle data t ransfer instruct ions in table 2.15. Table 2.14 Double Data Tr ansfer Instruction Formats Type Mnemonic 15 14 13 12 11 10 9 8 7 6 5[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 63 of 982 REJ09B0023-0400 Table 2.15 Single Data Tr ansf er In struction F ormats Type Mnemonic 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Single MOVS.W @-As,Ds 1 1 1 1 0 1 As Ds 0:( * ) 0 0 0 0 data MOVS.W @As,Ds 0:R4 1:( * ) 0 1 transfer MOVS.W @As+,Ds 1:R5 2:( * ) 1 0 MOVS.W @As+Ix,Ds 2:R2 3:( * ) 1 1 MOVS.W[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 64 of 982 REJ09B0023-0400 Table 2.16 A-Field Parallel Data Transfer Instructions NOPX MOVX.W @Ax, Dx MOVX.W @Ax+, Dx MOVX.W @Ax+Ix, Dx MOVX.W Da, @Ax MOVX.W Da, @Ax+ MOVX.W Da, @Ax+Ix NOPY MOVY.W @Ay, Dy MOVY.W @Ay+, Dy MOVY.W @Ay+Iy, Dy MOVY.W Da, @Ay MOVY.W Da, @Ay+ MOVY.W Da, @Ay+Iy Mnemonic X memory da[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 65 of 982 REJ09B0023-0400 Table 2.17 B-Field ALU Opera tion Instructions and Multipl y Instructions (1) PSHL #imm, Dz PSHA #imm, Dz Reserved PMULS Se, Sf, Dg Reserved PSUB Sx, Sy, Du PMULS Se, Sf, Dg PADD Sx, Sy, Du PMULS Se, Sf, Dg Reserved PSUBC Sx, Sy, Dz PADDC Sx, Sy, Dz PCMP Sx, Sy Reserved Reserved R[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 66 of 982 REJ09B0023-0400 Table 2.17 B-Field ALU Opera tion Instructions and Multipl y Instructions (2) [if cc] PSHL Sx, Sy, Dz [if cc] PSHA Sx, Sy, Dz [if cc] PSUB Sx, Sy, Dz [if cc] PADD Sx, Sy, Dz Reserved [if cc] PAND Sx, Sy, Dz [if cc] PXOR Sx, Sy, Dz [if cc] POR Sx, Sy, Dz [if cc] PDEC Sx, Dz [if cc][...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 67 of 982 REJ09B0023-0400 2.5 Instruction Set 2.5.1 CP U Instructi on Set The SH-1/SH -2/SH-3 c ompatible instr uction set consists of 67 ba sic instruct ion types di vided into seven functi onal groups , as sho wn in tabl e 2.18. Ta bles 2.19 to 2.24 sh ow the instr uction nota tion, machine code, executi[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 68 of 982 REJ09B0023-0400 Type Kinds of Instruction Op Code Function Number of Instructions 21 MUL Double-precision multi plication (32 × 32 bits) 34 MULS Signed multiplication (16 × 16 bits) Arithmetic operation instructions MULU Unsigned multiplication (16 × 16 bits) NEG Sign inversion NEGC Sign inver[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 69 of 982 REJ09B0023-0400 Type Kinds of Instruction Op Code Function Number of Instructions Branch instructions 9 BF Conditional branch, delayed conditional branch (T = 0) 11 BT Conditional branch, delayed conditional branch (T = 1) BRA Unconditiona l branch BRAF Unconditional branch BSR Branch to subrouti[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 70 of 982 REJ09B0023-0400 The instruction code, operation, an d number of exec ution st ates of the CP U instructions are shown in the following tables, classified by instruction type, using the format show n b elow. Instruction Instruction Code Operation Executi on States T Bit Indicated by mnemonic. Expl[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 71 of 982 REJ09B0023-0400 Data Transfer Instructions Table 2.19 Data Transfer Instructions Instruction Instruction Code Operation Executi on States T Bit MOV #imm,Rn 1110nnnniiiiiiii imm → Sign extension → Rn 1  MOV.W @(disp,PC),Rn 1001nnnndddddddd (disp × 2 + PC) → Sign extension → Rn 1  MO[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 72 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States T Bit MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 Rm → (R0 + Rn) 1 — MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 (R0 + Rm) → Sign exten sion → Rn 1 — MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 (R0 + Rm) → Sign exten sion → Rn 1 — MOV.L[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 73 of 982 REJ09B0023-0400 Arithmetic Operation Instructions Table 2.20 Arithmetic Operation Instructions Instruction Instruction Code Operation Execution States T Bit ADD Rm,Rn 0011nnnnmmmm1100 Rn + Rm → Rn 1 — ADD #imm,Rn 0111nnnniiiiiiii Rn + imm → Rn 1 — ADDC Rm,Rn 0011nnnnmmmm1110 Rn + Rm + T ?[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 74 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States T Bit DMULU.L Rm,Rn 0011nnnnmmmm0101 Unsigned operati on of Rn × Rm → MACH, MACL 32 × 32 → 4 bits 2(5) * 1 — DT Rn 0100nnnn00010000 Rn – 1 → Rn, if Rn = 0, 1 → T, else 0 → T 1 Comparison result EXTS.B Rm,Rn 01[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 75 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States T Bit SUBV Rm,Rn 0011nnnnmmmm1011 Rn–Rm → Rn, Underflow → T 1 Underflow Notes: 1. The normal minimum num ber of execution cycles is tw o, but five cycles are required when the operation result is read from the MAC regis[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 76 of 982 REJ09B0023-0400 Shift Instructions Table 2.22 Shift Instructions Instruction Instruction Code Operation Executi on States T Bit ROTL Rn 0100nnnn00000100 T ← Rn ← MSB 1 MSB ROTR Rn 0100nnnn00000101 LSB → Rn → T 1 LSB ROTCL Rn 0100nnnn00100100 T ← Rn ← T 1 MSB ROTCR Rn 0100nnnn00100101 [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 77 of 982 REJ09B0023-0400 Branch Instructions Table 2.23 Branch Instructions Instruction Instruction Code Operation Execution States T Bit BF label 10001011dddddddd If T = 0, disp × 2 + PC → PC; if T = 1, nop (where label is disp + PC) 3/1 * — BF/S label 10001111dddddddd Delayed bran ch, if T = 0, dis[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 78 of 982 REJ09B0023-0400 System Control Instructions Table 2.24 System Control Instructions Instruction Instruction Code Operation Execution States T Bit CLRMAC 0000000000101000 0 → MACH, MACL 1 — CLRS 0000000001001000 0 → S 1 — CLRT 0000000000001000 0 → T 1 0 LDC Rm,SR 0100mmmm00001110 Rm → S[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 79 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States T Bit LDC.L @Rm+, R4_BANK 0100mmmm11000111 (Rm) → R4_BANK, Rm + 4 → Rm 4 — LDC.L @Rm+, R5_BANK 0100mmmm11010111 (Rm) → R5_BANK, Rm + 4 → Rm 4 — LDC.L @Rm+, R6_BANK 0100mmmm11100111 (Rm) → R6_BANK, Rm + 4 → Rm [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 80 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States T Bit STC R7_BANK,Rn 0000nnnn11110010 R7_BANK → Rn 1 — STC.L SR,@–Rn 0100nnnn00000011 Rn–4 → Rn, SR → (Rn) 1 — STC.L GBR,@–Rn 0100nnnn00010011 Rn–4 → Rn, GBR → (Rn) 1 — STC.L VBR,@–Rn 0100nnnn0010001[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 81 of 982 REJ09B0023-0400 2.6 DSP Extended-Function Instructions 2.6.1 Intr oduction The newly added instructions are classi fied into the foll owing three groups: 1. Additional system control in structions for the CPU unit 2. DSP unit memory -reg ister sing le and double data tran sfer 3. DSP unit paralle[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 82 of 982 REJ09B0023-0400 2.6.2 Added CPU System Contr ol Instructions The new instructions i n this class are treated as part of t he CPU core f unctions, an d therefore al l the added instructions hav e a 16-bit cod e length. All the additio nal instructions belong to the system control i nstruct i o n g[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 83 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States T Bit STS.L DSR,@-Rn 0100nnnn01100010 Rn – 4 → Rn, DSR → (Rn) 1  STS.L A0,@-Rn 0100nnnn01110010 Rn – 4 → Rn, A0 → (Rn) 1  STS.L X0,@-Rn 0100nnnn10000010 Rn – 4 → Rn, X0 → (Rn) 1  STS.L X1,@-Rn 0100n[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 84 of 982 REJ09B0023-0400 2.6.3 Single and Double Data Tran sfer for DSP Data Instructions The new instructions i n this class are prov ide d to reduce the pro gram code size for DSP operations. All the new instructions in this class have a 16-bit code lengt h. Instructio ns in this class are divided into [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 85 of 982 REJ09B0023-0400 Table 2.26 Double Data Transfer Instructions Instruction Instruction Code Operation Execu- tion States DC NOPX 1111000 * 0 * 0 * 00 ** X memory no access 1  X memory data transfer MOVX.W @Ax,Dx 111100A * D * 0 * 01 ** (Ax) → MSW of Dx, 0 → LSW of Dx 1  MOVX.W @Ax+,Dx 111[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 86 of 982 REJ09B0023-0400 Table 2.27 Single Data Transfer Instructions Instruction Instruction Code Operation Execution States DC MOVS.W @-As,Ds 111101AADDDD0000 As – 2 → As, (As) → MSW of Ds, 0 → LSW of Ds 1  MOVS.W @As,Ds 111101AADDDD0100 (As) → MSW of Ds, 0 → LSW of Ds 1  MOVS.W @As+,D[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 87 of 982 REJ09B0023-0400 The correspondence between DSP da ta tran sfer operands a nd registers i s shown i n table 2. 28. CPU cor e registers are used as a pointer address that indicates a memory address. Table 2.28 Correspondence between DSP Data Transf er Operands and Registers Register Ax Ix Dx Ay Iy [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 88 of 982 REJ09B0023-0400 2.6.4 DSP Oper ation Instruc tion Set DSP operation instruction s are in stru ctions for digital signal processing performed by the DSP unit. These instructions have a 32 -b it instruction code, and multip le instructions can be ex ecuted in parallel. The instructio n cod e is div[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 89 of 982 REJ09B0023-0400 Table 2.30 Correspondence between DSP Instruction Operands and Registers ALU/BPU Operations Multiply Operations Register Sx Sy Dz Du Se Sf Dg A0 Yes — Yes Yes — — Yes A1 Yes — Yes Yes Yes Yes Yes M0 — Yes Yes — — — Yes M1 — Yes Yes — — — Yes X0 Yes — Yes [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 90 of 982 REJ09B0023-0400 Table 2.31 DSP Operation Instruction s Instruction Instruction Code Operation Execution States DC PMULS Se,Sf,Dg 111110 ********** 0100eeff0000gg00 Se * Sf → Dg (signed) 1  PADD Sx,Sy,Du PMULS Se,Sf,Dg 111110 ********** 0111eeffxxyygguu Sx + Sy → Du Se * Sf → Dg (signed) [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 91 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States DC DCF PSHA Sx,Sy,Dz 111110 ********** 10010011xxyyzzzz If DC = 0 & Sy > = 0, Sx << Sy → Dz (arithmetic shift) If DC = 0 & Sy < 0, Sx >> Sy → Dz If DC = 1, nop 1  PSHL Sx,Sy,Dz 111110 ********[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 92 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States DC PDMSB Sx,Dz 111110 ********** 10011101xx00zzzz Sx → Dz normalization count shift value 1 * PDMSB Sy,Dz 111110 ********** 1011110100yyzzzz Sx → Dz normalization count shift value 1 * DCT PDMSB Sx,Dz 111110 ********** 10[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 93 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States DC PNEG Sy,Dz 111110 ********** 1110100100yyzzzz 0 – Sy → Dz 1 * DCT PNEG Sx,Dz 111110 ********** 11001010xx00zzzz If DC = 1, 0 – Sx → Dz If DC = 0, nop 1  DCT PNEG Sy,Dz 111110 ********** 1110101000yyzzzz If DC = [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 94 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States DC PDEC Sy,Dz 111110 ********** 1010100100yyzzzz Sy [31:16] – 1 → Dz 1 * DCT PDEC Sx,Dz 111110 ********** 10001010xx00zzzz If DC = 1, Sx [39:16] – 1 → Dz If DC = 0, nop 1  DCT PDEC Sy,Dz 111110 ********** 101010100[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 95 of 982 REJ09B0023-0400 Instruction Instruction Code Operation Execution States DC DCT PSTS MACL,Dz 111110 ********** 110111100000zzzz If DC = 1, MACL → Dz 1  DCF PSTS MACL,Dz 111110 ********** 110111110000zzzz If DC = 0, MACL → Dz 1  PLDS Dz,MACH 111110 ********** 111011010000zzzz Dz → MACH [...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 96 of 982 REJ09B0023-0400 Table 2.32 DC Bit Update Defini ti on s CS [2:0] Condition Mode Description 0 0 0 Carry or borrow mode The DC bit is set if an ALU arithm etic operation generat es a carry or borrow, and is cleared otherwise. When a PSHA or PSHL shift instruction is executed, the last bit data shi[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 97 of 982 REJ09B0023-0400 Condition al Operations and Data T ransfer: Some instructions belonging to thi s class can be executed con ditionall y, as descri bed earlier . The specifie d conditi on is valid only for t he B fiel d of the instruction, and is not v a lid for data transfer instructio ns for whic[...]

Section 2 CPU Rev. 4.00 Sep. 14, 2005 Page 98 of 982 REJ09B0023-0400 Assignment of NOPX and NOPY Ins truction Codes: When there is no data transfer i nstruction to be parallel-processed simultaneously with a DSP operation instruction, an NOPX or NOPY instruction can be written as the data transfer in struction, or the i nstruction ca n be omitte d.[...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 99 of 982 REJ09B0023-0400 Section 3 DSP Operation 3.1 Data Operations of DSP Unit 3.1.1 ALU Fi xed-Point Oper ations Figure 3.1 s hows the ALU arithmeti c operation flow. Table 3.1 sho ws the variati on of thi s type of operation and table 3.2 shows the correspondence bet ween each operand and re[...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 100 of 982 REJ09B0023-0400 Table 3.1 Variation of ALU Fixed-P oint Oper ati ons Mnemonic Function Source 1 Source 2 Destination PADD Addition Sx Sy Dz (Du) PSUB Subtraction Sx Sy Dz (Du) PADDC Addition with carry Sx Sy Dz PSUBC Subtraction wit h borrow Sx Sy Dz PCMP Comparison Sx Sy — PCOPY Dat[...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 101 of 982 REJ09B0023-0400 IF 12 MO VX MO VX MO VX MO VX & P ADD MO VX & P ADD MO VX & P ADD 34 56 ID EX MA/DSP P ADD X0, Y0, A0 MO VX.W @(R4, R8), X0 MO VX.W @R4+, X0 Slot Stage Operation Sequence Example Addressing Addressing Previous cycle result is used. Figure 3.2 O peration Seq[...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 102 of 982 REJ09B0023-0400 Negative Value Mode: CS[2: 0] = 001: The DC flag indicates the same state as the MSB of the operation result. When the result is a negative nu mber, the DC bit shows 1. When it is a positive number, the DC bit shows 0. The AL U always exec utes 40-bit ari thmetic ope ra[...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 103 of 982 REJ09B0023-0400 Signed Greater Than Mode: CS[2:0] = 100: The DC bit indicates whether or not the source 1 data (signed ) is greater tha n the source 2 data (sig ned) as the res ult of com pare operati on PCMP. So, a PCMP o peration sh ould be e xecuted in a dva nce whe n a conditional[...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 104 of 982 REJ09B0023-0400 3.1.2 ALU Integer Operations Figure 3.6 s hows the ALU integer ari thmetic operatio n flow. Table 3.3 show s the variat ion of this type of ope ration. The c orrespondence bet ween each operand and register s is the same as AL U fixed-poi nt operat ions as sh own in ta [...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 105 of 982 REJ09B0023-0400 In ALU integer arithmetic operations, the lower wo rd of the sou rce operand is igno r ed and the lower word of the destination operand is automatically cleared. The guard-b it parts are effective in integer arithmetic op eration s if they are supporte d. Others are ba[...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 106 of 982 REJ09B0023-0400 39 31 0 Soruce 1 0 Destination ALU DSR GT Z N V DC 0 Source 2 Ignored Cleared 39 31 39 31 Guard Guard Guard Figure 3.7 ALU Logical O peration Flow Table 3.4 Variation of ALU Logical Operations Mnemonic Function Source 1 Source 2 Destination PAND Logical AND Sx Sy Dz POR[...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 107 of 982 REJ09B0023-0400 5. Signed Greater Than Mode: CS[2:0] = 100 The DC bit is always cleared. 6. Signed Greater Than or Equal Mo de: CS[2:0] = 101 The DC bit is always cleared. The N bit always i ndicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the [...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 108 of 982 REJ09B0023-0400 Table 3.5 Variation of Fixed-Poin t Mu ltiply Operati on Mnemonic Function Source 1 Source 2 Destination PMULS Signed multiplication Se Sf Dg Table 3.6 Correspondence betw een Operands and Registers Register Se Sf Dg A0   Yes A1 Yes Yes Yes M0   Yes M1  ?[...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 109 of 982 REJ09B0023-0400 3.1.5 Shift Operations Shift operations can use either regi ster or immedi ate value as the s hift amou nt opera nd. Othe r source and des tination ope rands are s pecified by the register. T here are tw o kinds of s hift operations. Ta bl e 3.7 shows t he variat i o n[...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 110 of 982 REJ09B0023-0400 In this arithmetic shift operation, all bits of the source 1 and destination opera nds are activated. The shift amount is specified by the source 2 operand as an inte ger data. T he source 2 o perand can be specified by either a regist er or immediate operand. T he avai[...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 111 of 982 REJ09B0023-0400 Overflow Protection: The S bit in SR is also effective for arithmetic shift operation in the DSP unit. See section 3.1. 8, O ver fl ow Prot ect i o n, fo r det ai l s. Logical Shift: Fig ure 3.10 shows the logical sh if t operation flow. DSR GT Z N V DC Updated 7g 0g 3[...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 112 of 982 REJ09B0023-0400 1. Carry or Borrow M ode: CS [2:0] = 000 The DC bit indicates the last shifted out data as the operation result. 2. Negative Value Mode: CS[ 2:0] = 001 Bit 31 of the operation result is load ed into the DC bit. 3. Zero Value Mode: CS[2:0 ] = 010 The DC bit is set when t[...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 113 of 982 REJ09B0023-0400 Every time a PDMSB operation is execu ted, the DC, N, Z, V, and GT bits in DSR are basically updated in acc ordance wit h the operat ion result . In case of a conditional operation, they are not updated, even thoug h th e specified condition is tr ue, and the operation[...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 114 of 982 REJ09B0023-0400 Table 3.8 Operation Definition of PDMSB Source Data Result for DST Guard Bit Upper Word Lower Word Guard Bit Upper Word 7 g 6 g … 1 g 0 g 3 1 3 0 2 9 2 8 … 3210 7g to 0g 31 to 22 21 20 19 18 17 16 Decimal 0 0 … 0 0 0 0 0 0 … 0000A l l 0 A l l 0 0111 1 1 + 3 1 0 [...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 115 of 982 REJ09B0023-0400 Table 3.9 Variation of PDMSB Operati on Mnemonic Function Source Source 2 Destination PDMSB MSB detection Sx  Dz  Sy Dz The N bit always i ndicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above[...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 116 of 982 REJ09B0023-0400 0 Destination ALU DSR Cleared GT Z N V DC H'00008000 39 31 0 Source 1 or 2 Addition Guard Guard 39 31 Figure 3.12 Rounding Operation Flow 0 H'00 0002 H'00 0001 H'00 0001 8000 H'00 0002 0000 H'00 0002 8000 Rounded result Analog value T rue v[...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 117 of 982 REJ09B0023-0400 3.1.8 Overfl ow Protection The S bit in SR is effective for any arithm etic op erations executed in the DSP un it, including the SH's standard multiply and MAC operations. The S bit in SR, in SH's CPU core, is used as th e overflow p rotection e nable bi t. T[...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 118 of 982 REJ09B0023-0400 3.1.9 Data Tr ansfer Operati on This LSI can execute a max imu m of two data transf er operations between th e DSP register and the on-chip dat a memory in parallel for t he DSP unit . Three types o f data trans fer instructi ons are provided for the DSP unit. 1. Parall[...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 119 of 982 REJ09B0023-0400 X pointer (R4, R5) 0, +2, +R8 XAB [15:1] Y AB [15:1] XDB [15:0] YDB [15:0] 0, +2, +R9 Y pointer (R6, R7) X memory (RAM, ROM) Y memory (RAM, ROM) Not affected f or store and cleared f or load Cannot be specitied X0 X1 Y0 Y1 M0 M1 A0G A1G DSR A0 A1 Figure 3.14 Data Trans[...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 120 of 982 REJ09B0023-0400 Note: D ata transfer by an LDS or STS instruction is possib le si nce DSR is defined as a system register. LAB [31:0] LDB [15:0] –2, 0, +2, +R8 P ointer (R2, R3, R4, R5) Any memory areas Not affected f or store and cleared f or load See description of A0G and A1G. Can[...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 121 of 982 REJ09B0023-0400 LAB [31:0] LDB [31:0] –4, 0, +4, +R8 P ointer (R2, R3, R4, R5) Any memory areas Cannot be specified X0 X1 Y0 Y1 M0 M1 A0G A1G A0 A1 DSR Figure 3.16 S ingle Data -Transfer O peration Flow (Longword ) All data transfer operations are ex ecu ted in the MA stage of the p[...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 122 of 982 REJ09B0023-0400 3.1.10 Local D at a M ove Instructio n The DSP unit of this L SI provides additiona l two inde pendent re gisters, M ACL and M ACH, in order to support SH's standard mu ltiply/MAC operations. They can be also used as temporary storage register s by local data move [...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 123 of 982 REJ09B0023-0400 3.1.11 Operand Conflict When an identical destination operand is specified with multiple parallel instru ctions, data conflict occurs. Table 3.14 shows th e correspondence between eac h operand and reg ister s. Table 3.14 Correspondence be tween Operands and Registers [...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 124 of 982 REJ09B0023-0400 3.2 DSP Addressing 3.2.1 DSP Repeat Control This LSI prepares a special c ont rol mechanism for efficient repeat loop control. An instruction SETRC sets the repeat times into the repeat counter RC (1 2 bits), and an execution mod e in wh ich a program loop executes r ep[...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 125 of 982 REJ09B0023-0400 #imm is 8 bits while RC is 12 bits. Therefor e, to set more than 256 into RC, use Rm. A sample program is show n below. LDRS RptStart; LDRE RptEnd3+4; SETRC #imm; RC = #imm instr0; ; instr1–5 executes repeatedly RptStart: instr1; RptEnd3: instr2; instr3; instr4; RptE[...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 126 of 982 REJ09B0023-0400 5. If a repeat loop has fo ur or more instructions in it, any branch instructions (BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JS R and JMP), repeat c ontrol instructions (SETRC, LDRS and LDRE), load instructions for SR, RS , RE, and the TRAP A instruction must [...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 127 of 982 REJ09B0023-0400 In figure 3. 18, exceptio ns generat ed by inst ructions ma rked as B a nd C are handl ed as foll ows: • Interrupt and DM A address errors An exception is accepted at neither instruction B or C , and the request is not even saved. A request is detected for the fi rst[...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 128 of 982 REJ09B0023-0400 Star t(End): instr – 1 instr0 instr1 instr2 ; A ; B ; C ; A 1. 1 repeated step A: Acceptable f or an y interrupts B and C: Acceptable f or some interrupts RC = 0 : Acceptable f or any interrupts RC > 1 : _ 2. 2 repeated steps 4. 4 repeated steps 5. 5 or more repeat[...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 129 of 982 REJ09B0023-0400 Based on this table, the actual repeat programming for various cases should be described as in the following examples: CASE 1: 1 Repeated Instruct ion LDRS RptStart0+8; LDRE RptStart0+4; SETRC RptCount; - - - - RptStart0: instr0; RptStart: instr1; Repeated instruction [...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 130 of 982 REJ09B0023-0400 CASE 4: 4 or More Repeated Instruct ions LDRS RptStart; LDRE RptEnd3+4; SETRC RptCount; - - - - RptStart0: instr0; RptStart: instr1; Repeated instruction 1 instr2; Repeated instruction 2 instr3; Repeated instruction 3 ----------------------------------------------------[...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 131 of 982 REJ09B0023-0400 CASE 1: 1 Repeated Instruct ion REPEAT RptStart, RptStart, RptCount; - - - - instr0; RptStart: instr1; Repeated instruction instr2; CASE 2: 2 Repeated Instruct ions REPEAT RptStart, RptEnd, RptCount; - - - - instr0; RptStart: instr1; Repeated instruction 1 RptEnd: inst[...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 132 of 982 REJ09B0023-0400 CASE 4: 4 or More Repeated Instruct ions REPEAT RptStart, RptEnd, RptCount; - - - - instr0; RptStart instr1; Repeated instruction 1 instr2; Repeated instruction 2 instr3; Repeated instruction 3 ---------------------------------------------------------- instrN-3; Repeate[...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 133 of 982 REJ09B0023-0400 Table 3.18 Summary of DSP Data Transfer Instructions X and Y Data Transfer Operation (MOVX.W and MOVY.W) Single Data Transfer Operation (MOVS.W and MOVS.L) Address registers Ax: R4 and R5, Ay: R6 and R7 As: R2, R3, R4 and R5 Index register(s) Ix: R8, Iy: R9 Is: R8 Addr[...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 134 of 982 REJ09B0023-0400 Three address operation types: 1. Not update 2. Add-inde x-register (Ix/Iy) 3. Increment All operations are post-update type. T o decrement an address pointer , set –2 in an inde x register . ALU R8 [Ix] R4 [Ax] R5 [Ax] +2 (INC) +0 (Not update) AU R9 [Iy] R6 [A y] R7 [...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 135 of 982 REJ09B0023-0400 ALU R8 [Is] R4 [As] R5 [As] R2 [As] R3 [As] –2/–4 (DEC) +2/+4 (INC) +0 (No update) Four address oper ation types: 1. Not update 2. Add-inde x-register (Is) 3. Increment 4. Decrement P ost-update Pre-update Figure 3.20 DSP Addressing Instructions for MOVS Modulo Add[...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 136 of 982 REJ09B0023-0400 MS and ME are set to specify the start and end a ddresses, a nd then later to set the DMX or DMY bit to 1. When the X/Y data transfer instruction set in DMX/DMY is executed, the a ddress register contents bef ore update are c ompared wit h ME* 1 . If they match, modulo [...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 137 of 982 REJ09B0023-0400 An example is shown below. MS=H'7000; ME=H'7004; R4=H'A5007000; DMX=1; DMY=0 (modulo addressing for address register Ax) As a result of the above setting s , th e R4 register changes as follows. ; R4: H'A5007000 (Initial value) MOVX.W @R4+,Dx ; R4: [...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 138 of 982 REJ09B0023-0400 Addressing Instructions in Execution Stage: A ddress inst ructions, incl uding m odulo addressi ng, are executed in the execution stage of the pip eline. Behavio r of the D SP data addres sing in the execution stage is shown below. if ( Operation is MOVX.W MOVY.W ) { AB[...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 139 of 982 REJ09B0023-0400 / * The value to be added to the address register depends on addressing instructions. For example, (+2 or R8[Ix] or +0) means that +2: if instruction is increment R8[Ix]: if instruction is add-index-register +0: if instruction is not-update * / function modulo ( AddrRe[...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 140 of 982 REJ09B0023-0400 31 15 1 0 R4 [Ax] R5 [Ax] ABx XAB 16-bit X_MEM X R/W Y_MEM Y R/W Y AB 16-bit XDB YDB 16-bit 16-bit X data memory 4 kbytes 31 15 1 0 R6 [A y] R7 [A y] ABy Y data memory 4 kbytes X_MEM and Y_MEM: Select X and Y data memor y Instruction code for X data-transf er operation [...]

Section 3 DSP Operation Rev. 4. 00 Sep. 14, 2005 Page 141 of 982 REJ09B0023-0400 Single-Dat a Transfer Instr uctions ( MOVS.W and M OVS.L): This LSI has single load/store instructions for the DSP registers. It is similar to a load/store in struction for a system register. It transfers data between memor y and DSP dat a registers using LAB a nd LDB [...]

Section 3 DSP Operation Rev. 4.00 Sep. 14, 2005 Page 142 of 982 REJ09B0023-0400 Control LAB=MAB; if ( Ms!=NLS && W/L is word access ) { / * MOVS.W * / if (LS==load) { if (Ds!=A0G && Ds!=A1G) { Ds[31:16] = LDB[15:0]; Ds[15:0] = 0x0000; if (Ds==A0) A0G[7:0] = s ign-extens ion of L DB; if (Ds==A1) A1G[7:0] = s ign-extens ion of L DB; }[...]

Section 4 Clock Pulse Generator (CPG) Rev. 4. 00 Sep. 14, 2005 Page 143 of 982 REJ09B0023-0400 Section 4 Clock Pulse Generator (C PG) This LSI has a clock pulse ge nerat or (CPG) that generat e s an inte rnal clock (I φ ), a pe ripheral clock (P φ ), and a bus clock (B φ ). The CPG consi sts of an oscillator, PLL ci rcuit, and divider ci rcuit. [...]

Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep. 14, 2005 Page 144 of 982 REJ09B0023-0400 CKIO CKIO2 PLL circuit 1 ( × 1, 2, 3, 4) × 1 × 1/2 × 1/3 × 1/4 Clock pulse generator Divider Internal clock (I φ ) Internal bus Bus interface FRQCR: STBCR: STBCR2: STBCR3: STBCR4: [Legend] Frequency control register Standby control register Standby c[...]

Section 4 Clock Pulse Generator (CPG) Rev. 4. 00 Sep. 14, 2005 Page 145 of 982 REJ09B0023-0400 The clock puls e generator bl ocks functi on as follows: PLL Circuit 1: PLL circuit 1 doubles, triples, or quadruple s, the in put clock frequenc y from t he CKIO pin. The multip licatio n rate is set by the frequency control reg ister. When this is done,[...]

Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep. 14, 2005 Page 146 of 982 REJ09B0023-0400 4.2 Input/Output Pins Table 4.1 lis ts the CPG pins and their function s. Table 4.1 Pin Configuration and Func tions of the Clock Pulse Generator Pin Name Symbol I/O Functio n (clock operating modes 2 and 6) Functio n (clock operating mode 7 ) Mode control[...]

Section 4 Clock Pulse Generator (CPG) Rev. 4. 00 Sep. 14, 2005 Page 147 of 982 REJ09B0023-0400 Mode 2: The freque ncy of the signal received from the EXT AL pin or crystal resonator LSI is quadrupled by the PLL circuit 2 before it is supp lie d as the clock signal. This lo wers the freq uency required of t he externally generated clock . Either a c[...]

Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep. 14, 2005 Page 148 of 982 REJ09B0023-0400 PLL frequency multiplier Selectable frequency ra nges (MHz) Clock operating mode FRQCR register setting PLL Circuit 1 PLL Circuit 2 Ratio of internal clock frequencies (I:B:P) Input clock Output clock (CKIO pin) Internal clock Bus clock Peripheral clock 6 [...]

Section 4 Clock Pulse Generator (CPG) Rev. 4. 00 Sep. 14, 2005 Page 149 of 982 REJ09B0023-0400 4.4 Register Descriptions The CPG's control register is ca lled the frequenc y control register (FRQCR). Refer t he section 24, List of Registers, for the addresses of the regist ers and the state of each register in each processor state. 4.4.1 Frequ[...]

Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep. 14, 2005 Page 150 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 8 STC1 STC0 0 0 R/W R/W Frequency multiplication ratio of PLL circuit 1 00: × 1 time 01: × 2 times 10: × 3 time[...]

Section 4 Clock Pulse Generator (CPG) Rev. 4. 00 Sep. 14, 2005 Page 151 of 982 REJ09B0023-0400 4.5 Changing the Frequency The frequenc y of the int ernal clock an d periphe ral clock ca n be change d either by changing t he multiplication rate of PLL circuit 1 or by changing the division rates of divider. All of these are controlled by software t h[...]

Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep. 14, 2005 Page 152 of 982 REJ09B0023-0400 4.6 Notes on Board Design Note on Usin g an External Crystal Reso nator: Place the crystal resonat or, capacitors CL1 and CL2, and feed back resistor R 1 as close to th e XTAL and E XTAL pins as possible. I n addition, to minimize induct ion and thus obtai[...]

Section 4 Clock Pulse Generator (CPG) Rev. 4. 00 Sep. 14, 2005 Page 153 of 982 REJ09B0023-0400 • A pair of Vss and Vcc for the input/ output p ower supply nea rest the USB m odule H3 to H4 • A pair of Vss and Vcc for the A/ D convert er. W19 to U2 0 Notes on Using a PLL Oscilla tor Circuit: In the V cc and Vss con nection pa tte rn for the PL L[...]

Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep. 14, 2005 Page 154 of 982 REJ09B0023-0400[...]

Section 5 Watchdog Timer (WDT) Rev. 4. 00 Sep. 14, 2005 Page 155 of 982 REJ09B0023-0400 Section 5 Watchdog Timer (WDT) This LSI includes the watchdog timer (WDT), wh ich enables reset the LSI on overflow of the counter when the value of the counter has not been updated because of a system malfunction. The WDT is a single channel timer that c ounts [...]

Section 5 Watchdog Timer (WDT) Rev. 4.00 Sep. 14, 2005 Page 156 of 982 REJ09B0023-0400 Figure 5.1 s hows a bl ock diagra m of the WDT. WTCSR Standby control Bus interface WTCNT Divider Clock selector Clock Standby mode Peripheral clock Standby cancellation Reset control Clock selection WDT Overflow Internal reset request Interrupt control Interrupt[...]

Section 5 Watchdog Timer (WDT) Rev. 4. 00 Sep. 14, 2005 Page 157 of 982 REJ09B0023-0400 5.2.2 Watchdog Timer C ontrol/Status Re gister (WTCSR) The watchdog timer control/status register (WTCSR) is an 8-bit read able/writable register composed of bits to select the cl ock used for the count, overflow flags, and timer enable bit. Th e WTCSR regist er[...]

Section 5 Watchdog Timer (WDT) Rev. 4.00 Sep. 14, 2005 Page 158 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 4 WOVF 0 R/W Watchdog Tim er Overflow Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode. 0: No overflow 1: WTCNT has overflowed in watchdog timer mode 3 IOVF 0 R/W[...]

Section 5 Watchdog Timer (WDT) Rev. 4. 00 Sep. 14, 2005 Page 159 of 982 REJ09B0023-0400 5.2.3 Notes on Regi ster Access The watchdog timer counter (WTCNT) and watchd og timer control/statu s register (WTCSR) are more diffic ult to writ e to than other re gisters. The procedure s for rea ding or wri ting to thes e registers are gi ven below. Writing[...]

Section 5 Watchdog Timer (WDT) Rev. 4.00 Sep. 14, 2005 Page 160 of 982 REJ09B0023-0400 5. When the WDT count overflows, t he CPG st arts su pplying the cl ock and the processor resumes operation. The WOVF flag in WTCSR is not set when this happens. 6. Since the WDT continues cou nting from H'00, set the STBY bit in the STBCR register to 0 in t[...]

Section 5 Watchdog Timer (WDT) Rev. 4. 00 Sep. 14, 2005 Page 161 of 982 REJ09B0023-0400 5.3.4 Using In terval T imer Mode When operating in interval timer mode, in terval tim er interrupts are generated at every overflow of the counter. This enables interrupts to b e generated at set periods. 1. Clear the WT/ IT bit in the WTCSR to 0, set the type [...]

Section 5 Watchdog Timer (WDT) Rev. 4.00 Sep. 14, 2005 Page 162 of 982 REJ09B0023-0400[...]

Section 6 Power-Down Modes Rev. 4. 00 Sep. 14, 2005 Page 163 of 982 REJ09B0023-0400 Section 6 Power-Down Modes In the low po wer-consumpt ion modes, operation of some of the int ernal pe ripheral modul es and of the CPU stops. This lead s to red uced power consum ption. These modes are canceled by a reset or interrupt. 6.1 Features 6.1.1 Power- Dow[...]

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 164 of 982 REJ09B0023-0400 Table 6.1 States of Power-Down Modes State * Mode Transition C onditions CPG CPU CPU Register On-Chip Memory On-Chip Peripheral Modules External Memory Canceling Procedure Sleep mode Execute SLEEP instruction with STBY bit cleared to 0 in STBCR Runs Halts Held Halts [...]

Section 6 Power-Down Modes Rev. 4. 00 Sep. 14, 2005 Page 165 of 982 REJ09B0023-0400 • Manual-on reset 1. A low signal is input to the RESETM pin. 2. The WDT counter overflows if WDT starts counting w hile the WT/ IT and RSTS bits of t he WTCSR are set to 1. 6.1.3 Input/Outpu t Pins Table 6.2 lists the pins use d for the power-d ow n modes . Table[...]

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 166 of 982 REJ09B0023-0400 6.2 Register Descriptions The following registers are used in the low po wer-consumption mode s. For th e addresses and access sizes of these registers, see section 24, List of Registe rs. • Standby co ntrol register (STBCR) • Standby co ntrol register 2 (STBCR2)[...]

Section 6 Power-Down Modes Rev. 4. 00 Sep. 14, 2005 Page 167 of 982 REJ09B0023-0400 6.2.2 Standby Control Regi ster 2 (ST BCR2) The standby control reg ister 2 (STBCR2) is a read able/writable 8-bit register that controls the operation of modules in the po wer-do wn mode. STBCR2 is initialized (to H'00) by a power-on reset but retains its prev[...]

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 168 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 2 MSTP5 0 R/W Module Stop 5 When the MSTP5 bit is set to 1, the supply of the clock to the cache memory is halted. 0: The cache memory runs. 1: Clock supply to the cache memory halted . 1 MSTP4 0 R/W Module Stop 4 When the M[...]

Section 6 Power-Down Modes Rev. 4. 00 Sep. 14, 2005 Page 169 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 6  0 R/W Reserved This bit is always read as 0. The write value should always be 0. 5 MSTP35 0 R/W Module Stop 35 When the MSTP35 bit is set to 1, supply of the clock to the CMT0 stops. 0: The CMT0 runs. 1: Supply of the[...]

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 170 of 982 REJ09B0023-0400 6.2.4 Standby Control Regi ster 4 (ST BCR4) STBCR4 is a readable/writable 8-bit reg ister used to select whether or not individual modules operate in power-down mode. STBCR4 is in itialized (to H'00) by a power-on reset, but retains its previous value after a ma[...]

Section 6 Power-Down Modes Rev. 4. 00 Sep. 14, 2005 Page 171 of 982 REJ09B0023-0400 6.3 Operation 6.3.1 Sleep Mode 1. Transition to Sleep Mode Executing the SLEEP inst ruction whe n the STBY bit in ST BCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction[...]

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 172 of 982 REJ09B0023-0400 6.3.2 St andby Mode 1. Transition to Standby Mode The LSI switches from a program execution state to a standby mode by executing the SLEEP instruction when the STBY bit is 1 in STBCR register. In standby mod e, not only the CPU but also the cloc k and on-chi p periph[...]

Section 6 Power-Down Modes Rev. 4. 00 Sep. 14, 2005 Page 173 of 982 REJ09B0023-0400 2. Canceling Standby Mode Standby mode is cancel ed by interrupts ( NMI , IRQ ) or a re set. • Cancelin g with an Interrupt The on-chip WDT can be use d fo r hot start s . When an interrupt request is detected at the rising or falling edge of NMI or IRQ , the cloc[...]

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 174 of 982 REJ09B0023-0400 6.3.3 Modul e Standby Function 1. Transition to Module St andby Fu nction Setting the st andby c ontrol re gister MST P bits to 1 halts the supply of cl ocks to the correspondin g on-chip peripheral m odules (howe ver, the initi al state of t he USB stops). This func[...]

Section 6 Power-Down Modes Rev. 4. 00 Sep. 14, 2005 Page 175 of 982 REJ09B0023-0400 1. Manual Reset CKIO STATUS 1. In manual reset, STATUS = HH (reset) after the current bus cycle is completed and then internal reset is initiated. 2. reset: HH (STATUS1 = High, STATUS0 = High) 3. normal: LL (STATUS1 = Low, STATUS0 = Low) 4. Bcyc: Bus clock cycle Not[...]

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 176 of 982 REJ09B0023-0400 B Standby mode is cancel ed by a manual reset CKIO STATUS 1. 2. 3. 4. 5. If a standby mode is canceled by a manual reset, the WDT stops counting. RESETM must be kept low for the PLL oscillation stabilization time. reset : HH (STATUS1 = High, STATUS0 = High) standby :[...]

Section 6 Power-Down Modes Rev. 4. 00 Sep. 14, 2005 Page 177 of 982 REJ09B0023-0400 B Sleep standby mode is canceled by a manual reset CKIO STATUS 1. RESETM must be kept low until STATUS = reset. 2. reset:HH (STATUS1 = High, STATUS0 = High) 3. sleep:HL(STSTUS1= High, STATUS0= Low) 4. normal:LL (STATUS1 = Low, STATUS0 = Low) 5. Bcyc:Bus clock cycle [...]

Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 178 of 982 REJ09B0023-0400[...]

Section 7 Cache Rev. 4. 00 Sep. 14, 2005 Page 179 of 982 REJ09B0023-0400 Section 7 Cache 7.1 Features The cache specification s are listed in table 7.1. Table 7.1 Cache Specifications Parameter Specification Capacity 16 kbytes Structure Instructions/data mi xed, 4-way set associative Locking Way 2 and wa y 3 are lockable Line size 16 bytes Number o[...]

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 180 of 982 REJ09B0023-0400 7.1.1 Cache Structure The cache mixes dat a and inst ructions an d uses a 4-way set associative system. It is c omposed of four ways (banks), each of which i s divided i nto an ad dress section a nd a dat a section. Ea ch of the address and da ta sections is divide d into 256 e[...]

Section 7 Cache Rev. 4. 00 Sep. 14, 2005 Page 181 of 982 REJ09B0023-0400 Data Array: Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The data array is not initialized by a power-on or manual reset, standby mode, module standby mode, and sleep mode. LRU: With the 4-way set associative system, up to [...]

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 182 of 982 REJ09B0023-0400 7.2 Register Descriptions The cache has the following registers. • Cache control register 1 (CCR1) • Cache control register 2 (CCR2) 7.2.1 Cache Contr ol Register 1 (C CR 1 ) The cache is enabled or d isabled using the CE bit in CCR1. CCR1 also h as the CF b it (which inval[...]

Section 7 Cache Rev. 4. 00 Sep. 14, 2005 Page 183 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 0 CE 0 R/W Cache E nable Indicates whether the cache function is used . 0: Cache not used 1: Cache used 7.2.2 Cache Contr ol Register 2 (C CR 2 ) CCR2 is used to enable or disable the cach e locking function and is valid in cache lock[...]

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 184 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 31 to 17  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 16 LE 0 R/W Lock Enable This bit enables or disables the cache lockin g function. 0: Cache locking mode is entered w hen SR.DSP=1 1: Cac[...]

Section 7 Cache Rev. 4. 00 Sep. 14, 2005 Page 185 of 982 REJ09B0023-0400 Table 7.4 Way to be Replaced when a Cache Miss Occurs in PREF Instruction Cache Locking Mode Bit W3LOAD W3LOCK W2LOAD W2LOCK Way to be Replaced 0 * * * * Decided by LRU (table 7.3) 1 * 0 * 0 Decided by LRU (table 7.3) 1 * 0 0 1 Decided by L RU (table 7.6) 1 0 1 * 0 Decid ed by[...]

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 186 of 982 REJ09B0023-0400 Table 7.7 LRU and Way Replacement (when W2LOCK=0 and W3LO CK= 1) LRU (Bits 5 to 0) Way to be Replaced 000000, 000001, 0000 11, 001011, 100000, 1000 01, 101001, 10101 1 2 000100, 000110, 0001 11, 001111, 010100, 0101 10, 011110, 01111 1 1 110000, 110100, 1110 00, 111001, 111011,[...]

Section 7 Cache Rev. 4. 00 Sep. 14, 2005 Page 187 of 982 REJ09B0023-0400 0 1 255 V U Tag address LW0 LW1 LW2 LW3 Address array (ways 0 to 3) Data array (ways 0 to 3) 31 12 11 4 3 2 1 0 Address CMP0 CMP1 CMP2 CMP3 Physical address [Legend] CMP0: Comparison circuit for way 0 CMP1: Comparison circuit for way 1 CMP2: Comparison circuit for way 2 CMP3: [...]

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 188 of 982 REJ09B0023-0400 7.3.2 Read Access Read Hit: In a read access, instructions and data are transferre d from the cache to the C PU. LRU is updated so that the hit w ay is the latest. Read Miss: An external bus cycle st arts and the entry is u pdated. The way replace d follows tabl e 7.5. Entries [...]

Section 7 Cache Rev. 4. 00 Sep. 14, 2005 Page 189 of 982 REJ09B0023-0400 7.3.5 Write-Back Buffer When the U bit of the entry to be replaced in th e write-back mode is 1, it must be written back to the external memory. To incr ease performance, the entry to be replaced is first transfe rred to the write-back bu ffer and fet ching of ne w entries t o[...]

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 190 of 982 REJ09B0023-0400 7.4 Memory-Mapped Cache To allow software management of t he cache, cache contents can be rea d an d written by means of MOV instructi ons. The cache i s mapped o nto the P4 area. The address ar ray is mappe d onto addresses H'F0000000 to H'F0 FFFFFF, and the data arr[...]

Section 7 Cache Rev. 4. 00 Sep. 14, 2005 Page 191 of 982 REJ09B0023-0400 Data Array Read : The data specified by L (bits 3 and 2) in the address is read from the entry address specified by the addre ss and the entry c orrespondin g to the wa y. Data Array Write: The longword data sp eci fi ed by the data is written to the position specified by L (b[...]

Section 7 Cache Rev. 4.00 Sep. 14, 2005 Page 192 of 982 REJ09B0023-0400 7.4.3 Us age Examples Invalidating Specific Entries Specific cache ent ries can be i nvalidated by writin g 0 to the ent ry's V bit i n the memory mapping cache access. When the A bit is 1, the address tag sp ecifie d by the write data is compared to the address tag within[...]

Section 8 X/Y Memory Rev. 4. 00 Sep. 14, 2005 Page 193 of 982 REJ09B0023-0400 Section 8 X/Y Memory This LSI has on-chip X -RAM and Y-RAM. It can be used by CPU, D SP and DMAC to store instructions or data. 8.1 Features The X/Y Memory features are listed in ta ble 8.1. Table 8 . 1 X/Y Memory Specifications Parameter Features Addressing method Mappin[...]

Section 8 X/Y Memory Rev. 4.00 Sep. 14, 2005 Page 194 of 982 REJ09B0023-0400 8.2 X/Y Memory Access from CPU The X/Y memory can be acc essed by the CPU from spaces P0 a nd P2. Acce ss from space P0 uses the I bus, and access from space P2 use the L bu s. To use the L bus, one cycle access is performed unless page c onflict occ urs. Using t he I bus [...]

Section 8 X/Y Memory Rev. 4. 00 Sep. 14, 2005 Page 195 of 982 REJ09B0023-0400 8.4 X/Y Memory Access from DMAC The X/Y memory can be acc essed by the DMAC via the I bus. Use the a ddresses between H'0500 7000 and H'05008 FFF or H'05017000 and H'05018FFF. 8.5 Usage Note When accessing the X/ Y memory from the CPU and DSP, if the c[...]

Section 8 X/Y Memory Rev. 4.00 Sep. 14, 2005 Page 196 of 982 REJ09B0023-0400[...]

Section 9 Exception Handling Rev. 4. 00 Sep. 14, 2005 Page 197 of 982 REJ09B0023-0400 Section 9 Exception Handling Exception ha ndling is separate fr om normal program pr ocessing, a nd is pe rformed by a routine separate from t he normal pr ogram. For exam ple, if an att empt is made t o execute an undefine d instruction c ode or an inst ruction p[...]

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 198 of 982 REJ09B0023-0400 9.1 Register Descriptions There are three registers for exceptio n handl ing. A regi ster with a n undefi ned initial val ue should be initialized by th e so ftware. • TRAPA exception re gister (T RA) • Exception event register (EXPEVT) • Interrupt event regi[...]

Section 9 Exception Handling Rev. 4. 00 Sep. 14, 2005 Page 199 of 982 REJ09B0023-0400 9.1.2 Exception Eve nt Register (E XPEVT) EXPEVT is as signed to a ddress H'FFF FFFD4 and consi sts of a 12-bit exc eption code. E xception codes to be spe cified in EXPEVT are th ose for resets a nd general e xceptions. These exce ption codes are auto matica[...]

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 200 of 982 REJ09B0023-0400 9.2 Exception Handling Function 9.2.1 Exception Ha ndli n g Flo w In exceptio n handlin g, the co ntents of the program counter (PC) and status register (SR) are sa ved in the saved pr ogram counte r (SPC) and saved status re gister (SSR) , respectivel y, and execu[...]

Section 9 Exception Handling Rev. 4. 00 Sep. 14, 2005 Page 201 of 982 REJ09B0023-0400 The above operations from 1 to 3 are execut ed in sequence. Duri ng these operations, no other exceptions may be accepted. By changing the SPT and SSR before e xecuting the RTE instruction, a status different from that i n effect before the exception ha ndling can[...]

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 202 of 982 REJ09B0023-0400 other than the CPU are no t initialized , the contents of EXPEVT, SPC, and SSR ar e undef ined, and this status is not detected by an external de vice. To enable acceptance of multiple exceptions, the contents of SPC a nd SSR must be sa ved while the BL bit is set [...]

Section 9 Exception Handling Rev. 4. 00 Sep. 14, 2005 Page 203 of 982 REJ09B0023-0400 If multiple general exceptions occur simultaneou sly in the same instruction, the priority is determined as follows. 1. A processing-complet ion type exce ption ge nerated at t he previous i nstruction * 2. A user break before instruction e xecution (re-exec ution[...]

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 204 of 982 REJ09B0023-0400 Table 9.1 Exception Event Vectors Exception Type Current Instruction Exception Event Priority * 1 Exception Order Process at BL=1 Vector Code Vector Offset Power-on reset 1 1 Reset H'A00  Reset Aborted Manual reset 1 2 Reset H'020 — H-UDI reset 1 1 R[...]

Section 9 Exception Handling Rev. 4. 00 Sep. 14, 2005 Page 205 of 982 REJ09B0023-0400 9.3 Individual Exception Operations This section describes the conditio n s for specific exception hand ling, and the processor operations. 9.3.1 Resets Power-On Reset: • Cond itions Power-on reset is request • Op erations Set EXPEVT to H'000, initialize [...]

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 206 of 982 REJ09B0023-0400 Table 9.2 Type of Reset Internal state Type Condition to reset CPU On-chip peripheral module Power-on reset RESETP = Low level Manual reset RESETM = Low level H-UDI reset H-UDI reset command entry Initialization Refer to the re gister configurations in the relevant[...]

Section 9 Exception Handling Rev. 4. 00 Sep. 14, 2005 Page 207 of 982 REJ09B0023-0400 Illegal general instruction exception: • Cond itions  When unde fined c ode not in a delay sl ot is de coded Delayed bra nch inst ructions: JM P, JSR, BR A, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Note: For detai ls on unde fined c ode, refer to SH-3/ SH-3E/SH-[...]

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 208 of 982 REJ09B0023-0400 Uncondition al tr ap: • Cond itions TRAPA instruction execu ted • Types Instructio n synchr onous, pr ocessing-c ompletion t ype • Save address An address of an instruction following TRAPA • Excep tion code H'160 • Remarks The exception is a processi[...]

Section 9 Exception Handling Rev. 4. 00 Sep. 14, 2005 Page 209 of 982 REJ09B0023-0400 DMA address error: • Cond itions  Word data acc essed from ad dresses other t han word boundaries (4 n + 1, 4n + 3)  Longword accessed from addresses other than longwor d bo undaries (4n + 1, 4n + 2, 4n + 3) • Types Instruction s ynchro nous, proc essing[...]

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 210 of 982 REJ09B0023-0400 9.4 Exception Processing While DSP Extension Function is Valid When the DSP extension fun ction is valid (the DSP bit of SR is set to 1), some exception processing acceptance cond itio ns or exception processing may be ch anged. 9.4.1 Illegal Instruction E xception[...]

Section 9 Exception Handling Rev. 4. 00 Sep. 14, 2005 Page 211 of 982 REJ09B0023-0400 • Example 1: Repeat loop consisting of four i nstructions LDRS RptStart ; [A] LDRS RptDtct + 4 ; [A] SETRCT #4 ; [A] instr0 ; [A] RptStart: instr1 ; [A] ……… ; [A] ……… ; [A] RptDtct: RptDtct ; [B] A repeat detection instruction is an instruction three[...]

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 212 of 982 REJ09B0023-0400 • Example 3: Repeat loop consisting of two inst ructions LDRS RptDtct + 6 ; [A] LDRS RptDtct + 4 ; [A] SETRCT #4 ; [A] RptDtct: RptDtct ; [B] A repeat detection instruction is an instruction prior to a repeat start instruction RptStart: RptDtct1 ; [C1][Repeat sta[...]

Section 9 Exception Handling Rev. 4. 00 Sep. 14, 2005 Page 213 of 982 REJ09B0023-0400 Table 9.4 SPC Value When a Re-Execution Ty pe Exception Occurs in Repeat Control Number of Instructions in a Repeat Loop Instruction Where an Exception Occurs 1 2 3 4 or Greater RptDtct RptDtct RptD tct RptDtct RptDtct RptDtct1 RptDtct1 RptDtc t1 RptDtct1 RptDtct1[...]

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 214 of 982 REJ09B0023-0400 An Exception Retained in Repeat Control Period: In the repeat control period, an i nterrupt or some exception will be retained to prev ent an exception accep tance at an instruction where returning from the except ion cannot be performed c orrectly. For detail s, r[...]

Section 9 Exception Handling Rev. 4. 00 Sep. 14, 2005 Page 215 of 982 REJ09B0023-0400 CPU Address Error in Repeat Control Period: If a CPU address error occurs in the re peat control period, the exception is accepted but an ex ception c ode (H'070) indicating t he repeat loop period is specified in the EXPEVT. If a CPU ad dress error occurs in[...]

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 216 of 982 REJ09B0023-0400 9.5 Note on Initializing this LSI This LSI needs to be initialized by a so ftware reset before the power is turned on. Execute the following program im mediately afte r a power- on reset. Note that the following progra m overwrite s contents of CPU general regi ste[...]

Section 9 Exception Handling Rev. 4. 00 Sep. 14, 2005 Page 217 of 982 REJ09B0023-0400 ;----------------------------------------------------------- ; Intialization of sh7641 for power-on reset ;----------------------------------------------------------- ; ATTENTION: ; 1. Please execute below instructions on power-on reset. ; 2. This routine would ov[...]

Section 9 Exception Handling Rev. 4.00 Sep. 14, 2005 Page 218 of 982 REJ09B0023-0400 9.6 Usage Notes 1. An instruct ion assigne d at a delay sl ot of the RTE instructi on is execute d after the contents of the SSR is restored i nto the SR. An acceptance of an e xception related to i nstruction access is determined according to the SR before re st o[...]

Section 10 Interrupt Controller (INTC) Rev. 4. 00 Sep. 14, 2005 Page 219 of 982 REJ09B0023-0400 Section 10 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the prior ity of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the or der of pri ority of eac h interrupt, al lowing the user to proc[...]

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 220 of 982 REJ09B0023-0400 Figure 10.1 show s a bloc k diagram of t he I NTC. DMAC SCIF0 to 2 ADC USB CMT0 and CMT1 MTU0 to MTU4 WDT H-UDI IIC2 8 DMAC: SCIF: ADC: USB: CMT: MTU: WDT: H-UDI: DMA controller Serial communication interfaces (with FIFO) 0 to 2 A/D conv erter USB funcito[...]

Section 10 Interrupt Controller (INTC) Rev. 4. 00 Sep. 14, 2005 Page 221 of 982 REJ09B0023-0400 10.2 Input/Output Pins Table 10.1 sho ws the INTC pi n configuratio n. Table 10.1 Pin Configuration Name Abbreviation I/O Description Nonmaskable interrupt input pin NMI Input Input of interru pt request signal, not maskable by the interrupt mask bits in[...]

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 222 of 982 REJ09B0023-0400 • Interrupt mask register 6 (IMR6) • Interrupt mask register 7 (IMR7) • Interrupt mask register 8 (IMR8) • Interrupt mask register 9 (IMR9) • Interrupt mask register 10 (IMR10) • Interrupt mask clear register 0 (IMCR0) • Interrupt mask clear[...]

Section 10 Interrupt Controller (INTC) Rev. 4. 00 Sep. 14, 2005 Page 223 of 982 REJ09B0023-0400 10.3.1 Interrupt Prio rity Registers B to J (IPRB to IPRJ) IPRB to IPRJ are 16-bit readable/writable registers in which pri ority level s from 0 to 15 are set fo r on-chip peri pheral m odule and IRQ inte rrupts. Th e se registers are initialized to H&ap[...]

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 224 of 982 REJ09B0023-0400 Table 10.2 Interrupt Sources and IPRB to IPRJ Register Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 IPRB WDT Reserved * Reserved * Reserve d * IPRC IRQ3 IRQ2 IRQ1 IRQ0 IPRD IRQ7 IRQ6 IRQ5 IRQ4 IPRE Reserved * SCIF0 SCIF1 ADC0 IPRF ADC1 SCIF2 USB CMT[...]

Section 10 Interrupt Controller (INTC) Rev. 4. 00 Sep. 14, 2005 Page 225 of 982 REJ09B0023-0400 10.3.2 Interrupt Cont rol Register 0 (ICR0) ICR0 is a register that sets the input sign al detection mode of external inter rupt input pin NMI , and indicates the input signal level at the NMI pin. This register is initialized to H'0000 or H'80[...]

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 226 of 982 REJ09B0023-0400 10.3.3 Interrupt Cont rol Register 1 (ICR1) ICR1 is a 16-bit register that specifies the d etection mode for external interrupt input p ins IRQ5 to IRQ0 individually: rising edge, falling edg e, high level, or low level. This register is initialized to H&[...]

Section 10 Interrupt Controller (INTC) Rev. 4. 00 Sep. 14, 2005 Page 227 of 982 REJ09B0023-0400 10.3.4 Interrupt Cont rol Register 3 (ICR3) ICR3 is a 16-bit register that specifies the d etection mode for external interrupt input p ins IRQ7 and IRQ6 indivi dually: risi ng edge, fall ing edge , high level , or low l evel. This regi ster is initializ[...]

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 228 of 982 REJ09B0023-0400 10.3.5 Interrupt Requ est Register 0 (IRR0) IRR0 is an 8 -bit register that indicat es interrupt requests f rom external i nput pins IRQ7 to IRQ0 . This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in st[...]

Section 10 Interrupt Controller (INTC) Rev. 4. 00 Sep. 14, 2005 Page 229 of 982 REJ09B0023-0400 10.3.6 Interrupt Mask Register s 0 to 10 (IMR0 to IMR10) IMR0 to IMR1 0 are 8-bit read able/w ritable registers that mask the IR Q and on-chi p peri pheral module interrupts. When an interrupt so urce is masked, interrupt request s may be mist akenly det[...]

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 230 of 982 REJ09B0023-0400 Table 10.3 Corresponden ce between Interrupt Sources and IMR0 to IMR10 Bit Name (Function Name) Register Name 7 6 5 4 3 2 1 0 IMR0 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 (IRQ) (IRQ) (IRQ) (IRQ) (IRQ) (IRQ) (IRQ) (IRQ) IMR1 TxI0 BRI0 RxI0 ERI0 DEI3 DEI2 D[...]

Section 10 Interrupt Controller (INTC) Rev. 4. 00 Sep. 14, 2005 Page 231 of 982 REJ09B0023-0400 10.3.7 Interrupt Mask Clear Regist ers 0 to 10 (IMCR0 to IMCR10) IMCR0 to IM CR10 are 8-bit writ able register s that clea r the mask settings for the IRQ a nd on- chip peripheral module interrupts. Table 10.4 shows th e relationship between IMCR and eac[...]

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 232 of 982 REJ09B0023-0400 Table 10.4 Corresponden ce between Interrupt Sour ces and IMCR0 to IMCR10 Bit Name (Function Name) Register Name 7 6 5 4 3 2 1 0 IMCR0 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 (IRQ) (IRQ) (IRQ) (IRQ) (IRQ) (IRQ) (IRQ) (IRQ) IMCR1 TxI0 BRI0 RxI0 ERI0 DEI3 D[...]

Section 10 Interrupt Controller (INTC) Rev. 4. 00 Sep. 14, 2005 Page 233 of 982 REJ09B0023-0400 10.4 Interrupt Sources There are fou r types of i nterrupt sources: N MI, H-UDI, IRQ, and on-chip peripheral m odules. Each interrupt has a priority level (0 to 16), with 1 the lowest and 16 the hig hest. Priorit y level 0 masks an interrupt, so th e int[...]

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 234 of 982 REJ09B0023-0400 Edge input interr upt det ect i on requi res in put of a pulse widt h of more than two cycles o n a P clock basis. When using lev el-sensing for IRQ in terrupts, the pin levels must be retained u ntil the CPU samples the pins. Therefore, the inte rrupt so[...]

Section 10 Interrupt Controller (INTC) Rev. 4. 00 Sep. 14, 2005 Page 235 of 982 REJ09B0023-0400 10.4.5 Interrupt Exceptio n Handling and Priority There are three types of i nterrupt so urces: NMI, IRQ, and on-c hip perip heral modules. T he priority of each interrup t source is set within level 0 to level 16; le vel 16 is the highest and level 1 is[...]

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 236 of 982 REJ09B0023-0400 Table 10.5 Interrupt Exception Handling Sources and Priority Interrupt Source Exception Code Interrupt Priory (Initial Value) IPR (Bit Number) Priority within IPR Setting Unit Default Priority NMI H'1C0 16   High H-UDI interrupt H'5E0 15 ?[...]

Section 10 Interrupt Controller (INTC) Rev. 4. 00 Sep. 14, 2005 Page 237 of 982 REJ09B0023-0400 Interrupt Source Exception Code Interrupt Priory (Initial Value) IPR (Bit Number) Priority within IPR Setting Unit Default Priority MTU0 TGI0A H'A80 0 to 15 (0) IPRG (15 to 12) High High TGI0B H'AA0 TGI0C H'AC0 TGI0D H'AE0 Low TCI0V H[...]

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 238 of 982 REJ09B0023-0400 10.5 INTC Operation 10.5.1 Interrupt Sequence The sequence of interru pt op erat i ons is described bel o w. Fi gu re 1 0.2 is a flowc hart of the operations. 1. The interrupt request sources send interrupt request signals to the interrup t controller. 2.[...]

Section 10 Interrupt Controller (INTC) Rev. 4. 00 Sep. 14, 2005 Page 239 of 982 REJ09B0023-0400 I3 to I0: Interrupt mask bits in status register (SR) Program execution state Interrupt generated? SR.BL=0 or sleep mode? Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No NMI? Level 15 interrupt? Set interrupt sourse in INTEVT2 Save SR to S[...]

Section 10 Interrupt Controller (INTC) Rev. 4.00 Sep. 14, 2005 Page 240 of 982 REJ09B0023-0400 10.5.2 Multiple Interrupts When handling multiple in terrupts, an interrup t h andler should include the follo wing procedures: 1. Branch to a specific interr upt handle r correspondi ng to a code set in INT EVT2. The co de in INTEVT2 can be use d as an o[...]

Section 11 User Break Controller (UBC) Rev. 4. 00 Sep. 14, 2005 Page 241 of 982 REJ09B0023-0400 Section 11 User Break Controller (UBC) The user brea k controlle r (UBC) pr ovides funct ions that simpl ify progra m debugging. These functions make it easy to design an effecti ve self-monit oring debu gger, enabli ng the chip t o debug programs wi tho[...]

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 242 of 982 REJ09B0023-0400 Figure 11.1 show s a bloc k diagram of t he U B C . BBRA BARA BAMRA CPU state signals XAB/Y AB IAB LAB Internal bus Access comparator Address comparator Channel A Access comparator Address comparator Data comparator PC trace CONTROL Channel B BBRB BETR BA[...]

Section 11 User Break Controller (UBC) Rev. 4. 00 Sep. 14, 2005 Page 243 of 982 REJ09B0023-0400 11.2 Register Descriptions The user break controller ha s the following regist ers. For details on register addresses and access sizes, refer to s ection 24, List of Regist ers. • Break address register A (BARA) • Break address mask register A (BAMRA[...]

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 244 of 982 REJ09B0023-0400 11.2.2 Break Address Ma sk Register A (BAMRA) BAMRA is a 32-bit readab le/writable register. BAMR A specifies bits maske d in the break address specified by BARA. Bit Bit Name Initial Value R/W Description 31 to 0 BAMA31 to BAMA0 All 0 R/W Break Addr ess [...]

Section 11 User Break Controller (UBC) Rev. 4. 00 Sep. 14, 2005 Page 245 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 5 4 IDA1 IDA0 0 0 R/W R/W Instruction Fetch/Data Access Select A Select the instruction fetch cycle or data access cycle as the bus cycle of the c hannel A break condition. 00: Condition comparison is not perfor[...]

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 246 of 982 REJ09B0023-0400 11.2.4 Break Addres s Register B (BARB ) BARB is a 32-bit readable/writable reg ister. BARB sp ecifies the address used as a break condition in channel B. Control bits CDB1, CDB0, XYE, and XYS in BBRB select one of the four address buses for break condi t[...]

Section 11 User Break Controller (UBC) Rev. 4. 00 Sep. 14, 2005 Page 247 of 982 REJ09B0023-0400 11.2.5 Break Address Ma sk Register B (BAMRB ) BAMRB is a 32-bit readable/writable register. BAM RB specifies bits masked in the break a ddress specified by BARB. Bit Bit Name Initial Value R/W Description 31 to 0 BAMB31 to BAMB0 All 0 R/W Break Addr ess[...]

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 248 of 982 REJ09B0023-0400 Table 11.2 Specifying Break Data Register Bus Selection in BBRB BDB31 to BDB16 BDB15 to BDB0 L bus LDB31 or LDB 0 I bus IDB31 to IDB0 X bus XDB15 to XDB0 Don't care Y bus Don't care YDB15 to YDB 0 Notes: 1. Specify an operand size when including[...]

Section 11 User Break Controller (UBC) Rev. 4. 00 Sep. 14, 2005 Page 249 of 982 REJ09B0023-0400 11.2.8 Break Bus Cycl e Register B (BBRB) Break bus cycle register B (BBRB) is a 16-bit read able/writable register, which specifies (1) X bu s or Y bus, (2) L bus cycle or I bus cycle, (3) inst ruction fetch or data access, (4) rea d or write, and (5) o[...]

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 250 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 5 4 IDB1 IDB0 0 0 R/W R/W Instruction Fetch/Data Access Select B Select the instruction fetch cycle or data access cycle as the bus cycle of the c hannel B break condition. 00: Condition comparison is not perform[...]

Section 11 User Break Controller (UBC) Rev. 4. 00 Sep. 14, 2005 Page 251 of 982 REJ09B0023-0400 11.2.9 Break Control Register (BRCR) BRCR sets the following condition s : 1. Channels A and B are used in two independe nt channel conditions or unde r the seque ntial condition. 2. A break is set before or after instruction execu tion. 3. Specify wheth[...]

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 252 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 13 SCMFDA 0 R/W I Bus Cycle Condition Match Flag A When the I bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clea r this flag, wr[...]

Section 11 User Break Controller (UBC) Rev. 4. 00 Sep. 14, 2005 Page 253 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 6 PCBB 0 R/W PC Break Select B Selects the break timing of the instruction fetch cycle for channel B as before or after instruction executio n. 0: PC break of channel B is set before instruction execution 1: PC [...]

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 254 of 982 REJ09B0023-0400 11.2.10 Execution Times Break Register (BETR) BETR is a 16- bit readable/w ritable regist er. When t he execution -times break c ondition of channel B is enabled, this register specifies th e numb er of execution times to make the break. The maximum numbe[...]

Section 11 User Break Controller (UBC) Rev. 4. 00 Sep. 14, 2005 Page 255 of 982 REJ09B0023-0400 11.2.12 Branch Destinati on Register (BRDR) BRDR is a 32 -bit read-onl y regist er. BRDR stores bits 27 to 0 in the a ddress of t he branch destination instruction. BRD R has th e flag bit that is set to 1 when a branch occurs. This flag bit is cleared t[...]

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 256 of 982 REJ09B0023-0400 11.3 Operation 11.3.1 Flow of the User Break Operati on The flow from setting of break cond itions to user b reak excep tion processing is described below: 1. The break addresses is set i n the break a ddress regi sters (BARA or BARB). The masked addresse[...]

Section 11 User Break Controller (UBC) Rev. 4. 00 Sep. 14, 2005 Page 257 of 982 REJ09B0023-0400  If a logical address issued on the L bus by th e CPU is an address to be cached and a cache miss occurs, its bus cycle is issued as a cache fill cycle on the I bus. In this case, it is issued in longwor ds and its ad dress is r ounded to m atch long [...]

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 258 of 982 REJ09B0023-0400 4. When an instruction fetch cycl e is set for cha nnel B, the break dat a register B (BDRB) is ignored. The refore, break dat a cannot be set for the break of the instruction fetch cycle. 5. If the I bus is set for a break of an instructi on fetch cycle,[...]

Section 11 User Break Controller (UBC) Rev. 4. 00 Sep. 14, 2005 Page 259 of 982 REJ09B0023-0400 word data in bits 31 to 16 in BDRB an d BDMRB when incl uding the valu e of the data bus as a break condition for the MOVS.W @-As,Ds, MOVS.W @As,Ds, MOVS.W @As+,Ds, or MOVS.W @As+Ix,Ds instruction (bits 15 to 0 are ignored ). 4. Access by a PREF instruct[...]

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 260 of 982 REJ09B0023-0400 11.3.5 Sequential Break 1. By setting the SEQ bit in BRCR to 1, th e sequential break is issued when a chan n el B break condition matches after a ch an nel A break conditio n matches. A user break is not g enerated even if a chan nel B break c ondition m[...]

Section 11 User Break Controller (UBC) Rev. 4. 00 Sep. 14, 2005 Page 261 of 982 REJ09B0023-0400 4. When data access (address + dat a) is specified as a brea k condition: When a data value is add ed to th e break conditions, the address of an in struction that is within two instructions of the in struction that matc hed the break co ndition is sa ve[...]

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 262 of 982 REJ09B0023-0400 11.3.8 Usage Examples Break Condition Specified for L Bus Instruction Fetch Cycle : (Example 1-1) • Register specifications BARA = H'00000404 , BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H&a[...]

Section 11 User Break Controller (UBC) Rev. 4. 00 Sep. 14, 2005 Page 263 of 982 REJ09B0023-0400 After an instruction with and address H'0003 7226 is executed, a user break occurs before an instruction with an d address H'0003722E is executed . (Example 1-3) • Register specifications BARA = H'00027128, BAMRA = H'00000000, BBRA [...]

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 264 of 982 REJ09B0023-0400 (Example 1-5) • Register specifications BARA = H'00000500 , BAMRA = H'00000000, BBRA = H'0057, BARB = H'00001000, BAMRB = H'00000000, BBRB = H'0057 , BD RB = H'00000000, BDMRB = H'00000 000, BRCR = H'00000001[...]

Section 11 User Break Controller (UBC) Rev. 4. 00 Sep. 14, 2005 Page 265 of 982 REJ09B0023-0400 Break Condition Specified fo r L Bus Data Access Cycle: (Example 2-1) • Register specifications BARA = H'00123456, BAMRA = H'00000000 , BBRA = H'0064, BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'000[...]

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 266 of 982 REJ09B0023-0400 Break Condition Specified fo r I Bus Data Access Cycle: (Example 3-1) • Register specifications BARA = H'00314156 , BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555, BAMRB = H'00000000, BBRB = H'00A9 , BD RB = H'00[...]

Section 11 User Break Controller (UBC) Rev. 4. 00 Sep. 14, 2005 Page 267 of 982 REJ09B0023-0400 4. When a user break and anothe r exception occur at the same instruction, which has higher priority is determine d according to the pri ority level s define d in table 9.1 in secti on 9, Exception Handlin g. If an exception with h igher priority occurs,[...]

Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 268 of 982 REJ09B0023-0400[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 269 of 982 REJ09B0023-0400 Section 12 Bus State Controller (BSC) The bus state cont roller (B SC) out puts contr ol si gnals for various types of memory that is connected to the external address space and e xternal devices. BSC functions enable this LSI t o connect directly with SR[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 270 of 982 REJ09B0023-0400  Supports low-frequency and pow er-down modes.  Issues MRS and EMRS commands. 6. Byte-selection SRA M interface  Can connect directly to a byt e-selection SRAM 7. Burst MPX-IO interface  Can connect directly to a peri pheral LS I that needs a n[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 271 of 982 REJ09B0023-0400 BSC functi onal bloc k diagra m is show n in fig ure 12.1. CMNCR CS0WCR CS6BWCR RWTCNT CS0BCR CS6BBCR SDCR RTCSR RTCNT RTCOR Comparator Bus mastership controller W ait controller Area controller Internal bus Memory controller Refresh controller [Legend] M[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 272 of 982 REJ09B0023-0400 12.2 Input/Output Pins Table 12.1 shows pin configuration of th e BSC. Table 12.1 Pin Configuration Name I/O Function A25 to A0 Output Address bus D31 to D0 I/O Data bus BS Output Bus cycle start CS0 , CS2 to CS4 Output Chip select CS5A Output Chip select [...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 273 of 982 REJ09B0023-0400 Name I/O Function WE0 Output Indicates that D7 to D0 are b eing written to. Connected to the byte select signal wh en a byte-selection SRAM is connected. Functions as the selection signals for D7 to D0 when SDR AM is connected. RASU RASL Output Connects t[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 274 of 982 REJ09B0023-0400 12.3.2 Shadow Area Areas 0, 2 to 4, 5A, 5B , 6A, a nd 6B are dec oded by a ddresses A 28 to A2 6, which c orrespond t o areas 000 to 110. Address bits 31 to 29 are ig nore d. This means that the range of area 0 addresses, for example, is H'00000000 to[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 275 of 982 REJ09B0023-0400 12.3.3 Address Map The external address space has a ca pacity of 384 Mbytes and is us ed by dividing 8 partial spaces. The kind of memory to be connected and the da ta bus width are specified in each pa rtial space. The address map for the exte rnal addre[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 276 of 982 REJ09B0023-0400 Table 12.3 Address Space Map 2 (CMNCR. M AP = 1) Physical Address Area Memory to be Connected Capacity H'00000000 to H'03FFFFFF Area 0 Normal mem ory Burst ROM (Asynchronous) Burst ROM (Synchronous) 64 Mbytes H'04000000 to H'07FFFFFF Ar[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 277 of 982 REJ09B0023-0400 12.3.4 Area 0 Memory Ty pe and Mem ory Bus Width The memory bus w idth in this LSI can be set for eac h area. In area 0, external pi ns can be used to select word (16 bits), or longword (32 bits) on power-on reset. The correspond ence between the external[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 278 of 982 REJ09B0023-0400 • Refresh timer control/st atus regist er (R TC S R ) • Refresh timer counter (RTCNT) • Refresh time constant register (RTCOR) • Reset wait counter (RWTCNT) 12.4.1 Common Co n trol Register (CM N CR ) CMNCR is a 32-bit register that controls the co[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 279 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 11 BLOCK 0 R/W Bus Clock Specifies whether or not the BREQ signal is received. 0: Receives BREQ. 1: Does not receive BREQ. 10 9 DPRTY1 DPRTY0 0 0 R/W R/W DMA Burst Transfer Priority Specify the priority for a ref[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 280 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 5 DMAIWA 0 R/W Method of ins erting wait state s between access cycles when DMA single address transfer is performed. Specifies the method of in serting the idle cy cles specified by the DMAIW[2:0] bit. Clearing t[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 281 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 0 HIZCNT 0 R/W High-Z Control Specifies the state in software standby mode and b us released for CKIO2, RASU , RASL , CASU , and CASL . 0: High impedance in software standby mod e and bus released for CKIO2, RASU[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 282 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 27 26 25 IWRWD2 IWRWD1 IWRWD0 1 1 1 R/W R/W R/W Idle Cycles for Another Space Read-Write Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target acc[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 283 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 21 20 19 IWRRD2 WRRD1 IWRRD0 1 1 1 R/W R/W R/W Idle Cycles for Read-Read in Another Sp ace Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target [...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 284 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 14 13 12 TYPE2 TYPE1 TYPE0 0 0 0 R/W R/W R/W Specify the type of memory connected to a space. 0000: Normal space 0001: Burst ROM (clock synchronous) 0010: MPX-I/O 0011: Byte-selection SRAM 0100: SDRAM 0101: Reserv[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 285 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 10 9 BSZ1 BSZ0 1 * 1 * R/W R/W Data Bus Size Specify the data bus sizes of spaces. The data bus sizes of areas 2, 3, 4 and 5A are show n below. 00: Reserved (setting prohibited) 01: 8-bit size 10: 16-bit size 11:[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 286 of 982 REJ09B0023-0400 12.4.3 CSn Space W ai t C ontr ol Register ( CSn W CR) (n = 0, 2, 3, 4, 5A, 5B, 6 A, 6B ) This register specifies various wait c ycles for memory accesses. The bit configuration of this register varies as shown below acc ording to the me mory type (TYPE2 t[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 287 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 10 9 8 7 WR3 WR2 WR1 WR0 1 0 1 0 R/W R/W R/W R/W Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 288 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 1 0 HW1 HW0 0 0 R/W R/W Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negati on. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 c[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 289 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 10 9 8 7 WR3 WR2 WR1 WR0 1 0 1 0 R/W R/W R/W R/W Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 290 of 982 REJ09B0023-0400 • CS4WCR Bit Bit Name Initial Value R/W Description 31 to 21  All 0 R Reserve d These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W Byte-Selection SRAM Byte Access Selection Specifies the WEn and RD/ WR signal timing when[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 291 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 12 11 SW1 SW0 0 0 R/W R/W Number of Delay Cycles from Address, CSn Assertion to RD , WE Assertion Specify the number of delay cycles from address and CSn assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 c[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 292 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 0 HW1 HW0 0 0 R/W R/W Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycl[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 293 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 12 11 SW1 SW0 0 0 R/W R/W Number of Delay Cycles from Address, CSn Assertion to RD , WE Assertion Specify the number of delay cycles from address and CSn assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 c[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 294 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 0 HW1 HW0 0 0 R/W R/W Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycl[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 295 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 20 MPX 0 R/W MPX-IO Interface Address Wait Specifies the address cycle insertion wait for MPX-IO interface. This bit setting is valid only when ar ea 5B is specified as MPX-I/O. 0: Inserts no wait cycle 1: Insert[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 296 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 12 11 SW1 SW0 0 0 R/W R/W Number of Delay Cycles from Address, CSn Assertion to RD , WE Assertion Specify the number of delay cycles from address and CSn assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cy[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 297 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 0 HW1 HW0 0 0 R/W R/W Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cyc[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 298 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 10 9 8 7 WR3 WR2 WR1 WR0 1 0 1 0 R/W R/W R/W R/W Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100:[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 299 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 1 0 HW1 HW0 0 0 R/W R/W Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negati on. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 [...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 300 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 10 9 8 7 WR3 WR2 WR1 WR0 1 0 1 0 R/W R/W R/W R/W Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100:[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 301 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 1 0 HW1 HW0 0 0 R/W R/W Number of Delay Cycles from RD , WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD , WEn negation to address, and CSn negation. 00: 0.5 cycles 01: 1.5 cycles[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 302 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 17 16 BW1 BW0 0 0 R/W R/W Number of Burst Wait Cycles Specify the number of wait cycles to be insert ed between the second or later access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 303 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 6 WM 0 R/W External Wait Mask Specific ation Specifies whether or not the external wait input is valid. The specification by this bit is valid ev en when the number of access wait cycle is 0. 0: External wait is [...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 304 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 17 16 BW1 BW0 0 0 R/W R/W Number of Burst Wait Cycles Specify the number of wait cycles to be insert ed between the second or later access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 305 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 10 9 8 7 W3 W2 W1 W0 1 0 1 0 R/W R/W R/W R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 010[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 306 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 1 0 HW1 HW0 0 0 R/W R/W Delay Cycles from RD , WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negati on. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 [...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 307 of 982 REJ09B0023-0400 • CS3WCR Bit Bit Name Initial Value R/W Description 31 to 15  All 0 R Reserve d These bits are always read as 0. The write value should always be 0. 14 13 WTRP1 * WTRP0 0 0 R/W R/W Number of Auto-Precharge Completion Wait Cycles Specify the number of[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 308 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 9  0 R Reserved This bit is always read as 0. The write value should always be 0. 8 7 A3CL1 A3CL0 1 0 R/W R/W CAS Latency for Area 3 Specify the CAS latency for area 3. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11:[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 309 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1 0 WTRC1 * WTRC0 0 0 R/W R/W Number of Idle Cycles from REF Command/Self- Refresh Release to ACTV/REF/MRS Command Specify the [...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 310 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 19 MPXMD 0 R/W Burst MPX-IO Interface Mode Specification Specify the access mode in 16-byte access 0: One 4-burst access by 16-byte transfer 1: Two 2-bursts accesses by quad word (8- byte) transfer Transfer size w[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 311 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 9 8 7 W3 W2 W1 W0 1 0 1 0 R/W R/W R/W R/W Number of Access Wait Cycles Specify the number of wait cycles to be[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 312 of 982 REJ09B0023-0400 Burst ROM (Clock Synchronous): • CS0WCR Bit Bit Name Initial Value R/W Description 31 to 18  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17 16 BW1 BW0 0 0 R/W R/W Number of Burst Wait Cycles Specify the number[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 313 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 10 9 8 7 W3 W2 W1 W0 1 0 1 0 R/W R/W R/W R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 010[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 314 of 982 REJ09B0023-0400 12.4.4 SDRAM Control Register (SDC R) SDCR specifies the method to refresh and acce ss SDRAM, and the types of SDRAMs to be connected. This register is initialized to H'000000 00 by a power-on reset, and it is not initialized by a manual reset and in [...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 315 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 13 DEEP 0 R/W Deep Power-Down Mode This bit is valid for low-power SDRAM. If the RFSH or RMODE bit is set to 1 while this bit is set to 1, the deep power-down entry command is issued and the low- power SDRAM ente[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 316 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 9 PDOWN 0 R Power-Down Mode Specifies whether the SDRAM will enter the power- down mode or not after the access to the external memory other than the SDRAM or to the internal I/O resister. With this bit being set [...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 317 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1 0 A3COL1 A3COL0 0 0 R/W R/W Number of Bits of Column Address for Area 3 Specify the number of bits of the column address for [...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 318 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 6  0 R Reserved This bit is always read as 0. The write value should always be 0. 5 4 3 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select Select the clock input to count-up the refresh timer counter (RTCNT). 000: S[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 319 of 982 REJ09B0023-0400 12.4.6 Refresh Time r Counter (RTCNT) RTCNT is an 8-bit counter that incremen ts using the clock selected by bi ts CKS2 to CKS0 in RTCSR. When RTCNT matches RTCOR, RTCNT is cl ea red to 0. The value in RTCNT returns to 0 after counting up to 255. When th [...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 320 of 982 REJ09B0023-0400 12.4.8 Reset Wait Coun ter (R WT CNT) RWTCNT is a 7-bit counter. This counter starts to increment b y synchr onizing the CKIO aft er a power-on reset is released, a n d stops when t he value reaches H' 007F. External bus access is suspended whil e the[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 321 of 982 REJ09B0023-0400 12.5 Operating Description 12.5.1 Endian/Access Size and Data Alignme nt This LSI supports big endian, in which the 0 ad dr ess is the most significant byte (MSByte) in the byte data. Three data bus width s (8 bi t s, 16 bit s, and 32 bits) are available [...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 322 of 982 REJ09B0023-0400 Table 12.6 16-Bit External Devi ce Acc ess and Data Alignme nt Data Bus Strobe Signals Operation D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3 , DQMUU WE2 , DQMUL WE1 , DQMLU WE0 , DQMLL Byte access at 0   Data 7 to 0    Assert  Byte acces[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 323 of 982 REJ09B0023-0400 Table 12.7 8-Bit External Devi ce Acce ss and Data Alignment Data Bus Strobe Signals Operation D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3 , DQMUU WE2 , DQMUL WE1 , DQMLU WE0 , DQMLL Byte access at 0    Data 7 to 0    Assert Byte access[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 324 of 982 REJ09B0023-0400 12.5.2 Normal Space Interface Basic Timing: For access to a normal space, this LSI uses strobe si gnal output in consideration of the fact that mainly static RAM will be directly con nected. When using SRAM with a byte- selection pin, see section 12.5.8, B[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 325 of 982 REJ09B0023-0400 It is necessary to output the data th at has been read using RD when a buffer is established in the data bus. The R D/ WR signal is in a read state (hi gh output ) when no access has been carried out. Therefore, care must be t aken whe n control ling the [...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 326 of 982 REJ09B0023-0400 CKIO A25 to A0 RD/ WR D15 to D0 DACKn CSn T1 T2 T1 T2 RD WEn BS WAIT D15 to D0 Read Write * Note: * The waveform for DACKn is when active low is specified. Figure 12.5 Continuous Access for Normal Space 2 Bus Width = 16 Bits, Longword Access, CSnWCR.W N Bi[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 327 of 982 REJ09B0023-0400 •••• •••• •••• •••• •••• A16 A0 CS OE I/O7 I/O0 WE •••• •••• •••• •••• A18 A2 CSn RD D31 D24 WE3 D23 D16 WE2 D15 D8 WE1 D7 D0 WE0 This LSI 128k × 8-bit SRAM •••• A16 A0 CS OE[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 328 of 982 REJ09B0023-0400 A16 A0 CS OE I/O7 I/O0 WE •••• •••• •••• •••• A17 A1 CSn RD D15 D8 WE1 D7 D0 WE0 This LSI 128k × 8-bit SRAM •••• A16 A0 CS OE I/O7 I/O0 WE •••• •••• •••• •••• •••• •••?[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 329 of 982 REJ09B0023-0400 12.5.3 Access Wait Control Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to WR0 in CSnWCR. It is possible for areas 4, 5A , and 5B to i nsert wait cycl es independent ly in read access and in write access. The[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 330 of 982 REJ09B0023-0400 When the WM bit in CSnWCR is clear ed to 0, t he external wait input WAIT si gnal is also sampled. WAIT pin sampling is shown in figure 12.1 0. A 2-cycle wait is specified as a sof twar e wait. The WAIT signal is sam pled on the falling e dge of CKIO at th[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 331 of 982 REJ09B0023-0400 12.5.4 CSn Assert Period Expansion The number of cycles from CSn assertion to RD , WEn assertion can be specified by setting bits SW1 and SW0 in CSnW CR. The numb er of cycles from RD , WEn negation to CSn negation can be specified by setting bit s HW1 an[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 332 of 982 REJ09B0023-0400 12.5.5 MPX-I/O Interface Access timing for the MPX space is shown below. In the MPX space, CS5B , AH , RD , and WEn signals control the accessing. The basic access for th e MPX space consists of 2 cycles of a ddress output followed by an access to a normal[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 333 of 982 REJ09B0023-0400 T1 CKIO A25 to A16 CSn RD/ WR RD D7 to D0 or D15 to D0 WEn D7 to D0 or D15 to D0 BS Read Write T2 DACKn * Ta1 Ta2 Ta3 AH Address Address Data Data Tadw Note: * The waveform for DACKn is when active low is specified. Figure 12.13 Access Timing for MPX Spac[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 334 of 982 REJ09B0023-0400 T1 CKIO A25 to A16 CS5B RD/ WR RD D7 to D0 or D15 to D0 WEn D7 to D0 or D15 to D0 BS Read Write T2 DACKn * Ta1 Ta2 Ta3 AH Address Address Data Data Tadw Tw Twx WAIT Note: * The waveform for DACKn is when active low is specified. Figure 12.14 Access Ti ming[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 335 of 982 REJ09B0023-0400 12.5.6 SDRAM Interface SDRAM Direct Connection: The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of r ow address , 8/9/1 0 bits of c olumn a ddress, 4 or less ba nks, and use s the A1 0 pin for setting precharge mode in read[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 336 of 982 REJ09B0023-0400 Figures 12.15 t o 12.17 sho w examples of t he connectio n of the SDR AM with the LSI. As shown i n figure 12. 17, two sets o f SDRAMs of 32 Mbytes or smaller can be connected t o the same CS space by using RASU , RASL , CAS U , and CA SL . In this case, a[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 337 of 982 REJ09B0023-0400 A14 A1 CKE CKIO CSn RASU CASU RASL CASL RD/ WR D15 D0 DQMLU DQMLL 64M SDRAM (1M × 16-bit × 4-bank) . . . A13 A0 CKE CLK CS RAS CAS WE I/O15 I/O0 DQMU DQML . . . . . . . . . This LSI Unused Unused Figure 12.16 Example of 16-Bit Data Width SDRAM Connectio[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 338 of 982 REJ09B0023-0400 A14 A1 CKE CKIO CSn RASU CASU RASL CASL RD/ WR D15 D16 DQMLU DQMLL 64M SDRAM (1M × 16-bit × 4-bank) A13 A0 CKE CLK CS RAS CAS WE I/O15 I/O0 DQMU DQML . . . . . . . . . . . . A13 A0 CKE CLK CS RAS CAS WE I/O15 I/O0 DQMU DQML . . . . . . This LSI Figure 12[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 339 of 982 REJ09B0023-0400 Address Multiplexing: An address multiplexing is specified so that SD RAM can be connected without external mu ltip lexing circuitry according to the setting of bits BSZ1 and BSZ0 in CSnBCR, AxROW[1:0] and AxCOL[1:0] in SDCR. Ta bles 12.8 to 12.13 show th[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 340 of 982 REJ09B0023-0400 Table 12.8 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (1)-1 Setting BSZ 1, 0 A2/3 ROW 1, 0 A2/3 COL 1, 0 11 (32 bits) 00 (11 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pi[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 341 of 982 REJ09B0023-0400 Table 12.8 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (1)-2 Setting BSZ 1, 0 A2/3 ROW 1, 0 A2/3 COL 1, 0 11 (32 bits) 00 (11 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM P[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 342 of 982 REJ09B0023-0400 Table 12.9 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (2)-1 Setting BSZ 1, 0 A2/3 ROW 1, 0 A2/3 COL 1, 0 11 (32 bits) 00 (11 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pi[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 343 of 982 REJ09B0023-0400 Table 12.9 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (2)-2 Setting BSZ 1, 0 A2/3 ROW 1, 0 A2/3 COL 1, 0 11 (32 bits) 00 (11 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM P[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 344 of 982 REJ09B0023-0400 Table 12.10 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (3) Setting BSZ 1, 0 A2/3 ROW 1, 0 A2/3 COL 1, 0 11 (32 bits) 00 (11 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pin[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 345 of 982 REJ09B0023-0400 Table 12.11 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (4)-1 Setting BSZ 1, 0 A2/3 ROW 1, 0 A2/3 COL 1, 0 11 (32 bits) 00 (11 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM [...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 346 of 982 REJ09B0023-0400 Table 12.11 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (4)-2 Setting BSZ 1, 0 A2/3 ROW 1, 0 A2/3 COL 1, 0 11 (32 bits) 00 (11 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM P[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 347 of 982 REJ09B0023-0400 Table 12.12 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (5)-1 Setting BSZ 1, 0 A2/3 ROW 1, 0 A2/3 COL 1, 0 11 (32 bits) 00 (11 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM [...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 348 of 982 REJ09B0023-0400 Table 12.12 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (5)-2 Setting BSZ 1, 0 A2/3 ROW 1, 0 A2/3 COL 1, 0 11 (32 bits) 00 (11 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM P[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 349 of 982 REJ09B0023-0400 Table 12.13 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (6)-1 Setting BSZ 1, 0 A2/3 ROW 1, 0 A2/3 COL 1, 0 11 (32 bits) 00 (11 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM [...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 350 of 982 REJ09B0023-0400 Table 12.13 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (6)-2 Setting BSZ 1, 0 A2/3 ROW 1, 0 A2/3 COL 1, 0 11 (32 bits) 00 (11 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM P[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 351 of 982 REJ09B0023-0400 Burst Read: A burst read occurs in the fo llowing cases wi th this LSI. • Access size in reading is larger than data bus width. • 16-byte transfer in cache error. • 16-byte transfe r in DMAC This LSI always accesses the SDRAM with burst length 1. Fo[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 352 of 982 REJ09B0023-0400 number of cycles from the Tc1 cycle where the RE AD command is output to the Td1 cycle whe re the read data is latched can be specified fo r t he CS2 and CS3 spaces independe ntly, using the A2CL1 and A2CL0 bits in the CS2WCR register or the A3CL1 and A3CL[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 353 of 982 REJ09B0023-0400 Tc4 (Tap) Tr Tc2 Tc3 Tc1 Td4 Tde Td2 Td3 Td1 Trw Tw CKIO A25 to A0 CSn RD/ WR RASL , RASU DQMxx D31 to D0 BS DACKn * 2 A12/A11 * 1 CASL , CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is speci[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 354 of 982 REJ09B0023-0400 Single Read: A read access ends in one cycle whe n data exists in non-cacheab le region a nd the data bus width is larger tha n or equal to access size. As t he burst length is set to 1 in sync hronous DRAM burst read/single write mode, only the required d[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 355 of 982 REJ09B0023-0400 Burst Write: A burst write occurs in the fo llowing cases in this LSI. • Access size in writing is larger than d ata bus width. • Write-back of the cache • 16-byte transfe r in DMAC This LSI always accesses SDRAM wi th burst length 1. For example, w[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 356 of 982 REJ09B0023-0400 Tc4 Tap Tr Tc2 Tc3 Tc1 Trwl CKIO A25 to A0 CSn RD/ WR RASL , RASU DQMxx D31 to D0 BS DACKn * 2 A12/A11 * 1 CASL , CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.21 Basic [...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 357 of 982 REJ09B0023-0400 Single Write: A write access ends in one cycle when data i s written in non-cacheable region a nd the data bus width is large r than or equal to access size. Figure 12.22 shows the sing le write basic timin g. Tap Tr Tc1 Trwl CKIO A25 to A0 CSn RD/ WR RAS[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 358 of 982 REJ09B0023-0400 Bank Active: The synchronous DRAM ba nk function is used to support high-spee d accesses to the same row address. When the B ACTV bit in SDCR is 1, accesses are performed usi ng commands without auto-prec harge (REA D or WRIT) . This f unction is ca lled b[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 359 of 982 REJ09B0023-0400 When bank active mode is set , if only accesse s to the respec tive banks in the area 3 space are considered, as long as accesses to the same row address co ntinue, the operation starts with the cycle in figure 1 2.23 or 12.26, follow ed by repe titio n o[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 360 of 982 REJ09B0023-0400 Tc4 Tc2 Tc3 Tc1 Tnop Td4 Tde Td2 Td3 Td1 CKIO A25 to A0 CSn RD/ WR RASL , RASU DQMxx D31 to D0 BS DACKn * 2 A12/A11 * 1 CASL , CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 361 of 982 REJ09B0023-0400 Tc4 Tpw Tp Tc2 Tc3 Tc1 Td4 Td2 Td3 Td1 Tde Tr CKIO A25 to A0 CSn RD/ WR RASL , RASU DQMxx D31 to D0 BS DACKn * 2 A12/A11 * 1 CASL , CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. [...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 362 of 982 REJ09B0023-0400 Tr Tc1 CKIO A25 to A0 CSn RD/ WR RASL , RASU DQMxx D31 to D0 BS DACKn * 2 A12/A11 * 1 CASL , CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.26 Single Write Timi ng (B ank[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 363 of 982 REJ09B0023-0400 Tnop Tc1 CKIO A25 to A0 CSn RD/ WR RASL , RASU DQMxx D31 to D0 BS DACKn * 2 A12/A11 * 1 CASL , CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.27 Single Write Timing (Ban[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 364 of 982 REJ09B0023-0400 Tpw Tp Tc1 Tr CKIO A25 to A0 CSn RD/ WR RASL , RASU DQMxx D31 to D0 BS DACKn * 2 A12/A11 * 1 CASL , CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.28 Single Write Timing [...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 365 of 982 REJ09B0023-0400 1. Auto-refres hing Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to CKS0 in RTCSR, and the value set by in RT COR. The value of bits CKS2 to CKS0 in RTCOR should be set so as to s atisfy the ref resh inter v al [...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 366 of 982 REJ09B0023-0400 Tpw Tp Trr Trc Trc Trc Hi-z CKIO A25 to A0 CSn RD/ WR RASL , RASU DQMxx D31 to D0 BS DACKn * 2 A12/A11 * 1 CASL , CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.29 Auto-R[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 367 of 982 REJ09B0023-0400 Self-refresh timing is shown in figure 12.30. Settings must be made so that self-refresh clearing and da ta retentio n are perfor med correctly, a nd auto-refres hing is perfo rmed at the correct intervals. When sel f-re freshing is activated from the st [...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 368 of 982 REJ09B0023-0400 Relationship between Refresh Requests and Bus Cycles: If a refresh re quest occur s during bus cycle execution, the refresh cycle must wait for the bus cyc le to be comple ted. If a refres h request occurs while the bus is released by the bus arbitration f[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 369 of 982 REJ09B0023-0400 Tc1 Tr Td1 Tde Tap Tr Tc1 Tnop Trwl Tap (High) CKIO CKE A25 to A0 CSn RD/ WR RASL , RASU DQMxx D31 to D0 BS DACKn * 2 A12/A11 * 1 CASL , CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specif[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 370 of 982 REJ09B0023-0400 Tnop Power-down Tr Tc1 Td1 Tde Tap Power-down CKIO CKE A25 to A0 CSn RD/ WR RASL , RASU DQMxx D31 to D0 BS DACKn * 2 A12/A11 * 1 CASL , CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specifie[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 371 of 982 REJ09B0023-0400 Power-On Sequence: I n order to use sync hronous DR AM, m ode setting must first be perf ormed after powering on. To perform synchronous DRAM initiali zatio n correctly, the bus state controller registers must first be set, fol l owe d b y a writ e to the[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 372 of 982 REJ09B0023-0400 • Setting for Area 3 Burst read/si ngle write (b urst lengt h 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits 2 H'A4FD5440 H'0000440 3 H'A4FD5460 H'000 0460 32 bits 2 H'A4FD5880 H'0000880 3 H'[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 373 of 982 REJ09B0023-0400 Tpw Tp Trr Trc Trc Tmw Hi-Z Tnop Trc Trr Trc REF REF MRS PALL CKIO A25 to A0 CSn RD/ WR RASL , RASU DQMxx D31 to D0 BS DACKn * 2 A12/A11 * 1 CASL , CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active lo[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 374 of 982 REJ09B0023-0400 Table 12.16 Output Addresses when EMRS Command Is Issued Command to be Issued Access Address Access Data Write Access Size MRS Command Issue Address EMRS Command Issue Address CS2 MRS H'A4FD4XX0 H' ******** 16 bits H'0000XX0  CS3 MRS H&ap[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 375 of 982 REJ09B0023-0400 • Deep power-down mode The low-power SDRAM supports the deep power-down mode as a low-power cons umption mode. In the partial self-re fresh function, self-refresh is performe d on a specific area. I n the deep power-down mode, self-refresh will no t be [...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 376 of 982 REJ09B0023-0400 12.5.7 Burst ROM (Clock Asynchronous) Interface The burst ROM (clock async hronous) interface is use d to access a memory with a high-speed rea d function usi ng a method o f address s witching called t he burst m ode or pa ge mode. In a burst ROM (clock a[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 377 of 982 REJ09B0023-0400 CKIO A25 to A0 RD D15 to D0 DACKn * Note: * The waveform for DACKn when active low is specified. WAIT CSn T1 Tw Tw TB2 Twb TB2 Twb TB2 Twb T2 RD/ WR BS Figure 12.36 Burst ROM Access Timing (Clock Asynchronous) (Bus Width = 32 Bits, 16-B yte Transfer (Numb[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 378 of 982 REJ09B0023-0400 CKIO A25 to A0 CSn WEn RD/ WR RD RD D31 to D0 D31 to D0 RD/ WR BS DACKn * Read Write Note: * The wav ef orm for DACKn is when activ e low is specified. T1 T2 High Figure 12.37 Byte-S election RAM Basic Acce ss Timing (BAS = 0)[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 379 of 982 REJ09B0023-0400 T1 T2 High CKIO A25 to A0 CSn WEn RD/ WR RD RD D31 to D0 D31 to D0 RD/ WR BS DACKn * Read Write Note: * The wa vef orm for DACKn is when activ e lo w is specified. Figure 12.38 Byte-S election RAM Basic Acce ss Timing (BAS = 1)[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 380 of 982 REJ09B0023-0400 T2 Th Th T1 Tw High CKIO A25 to A0 CSn WEn RD/ WR RD RD D31 to D0 D31 to D0 RD/ WR BS DACKn * Read Write Note: * The wa vef orm for DACKn is when activ e lo w is specified. Figure 12.39 Byte-Selection S RAM Wait Timing (BAS = 1) (SW[1:0] = 01, WR [3:0] = 0[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 381 of 982 REJ09B0023-0400 A15 A0 CS OE WE I/O15 I/O0 UB LB . . . . . . . . . A17 A2 CSn RD RD/ WR D31 D16 WE3 WE2 D15 D0 WE1 WE0 This LSI . . . A15 A0 CS OE WE I/O15 I/O0 UB LB . . . . . . . . . 64k × 16-bit SRAM Figure 12.40 Example of Connection with 32-Bit Data-Width Byte-Sele[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 382 of 982 REJ09B0023-0400 12.5.9 Burst MPX-I/O Interface Figure 12.42 s hows an exa mple of a co nnection bet ween the LSI a nd an M PX device. Fi gures 12.43 to 12.46 show the burst MPX space access timings. Area 6 can be specified as t he address/data mu ltiplex I/O (MPX-I/O) int[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 383 of 982 REJ09B0023-0400 Tm1 Tmd1w Tmd1 A D Note: * The wav ef orm for DACKn is when activ e low is specified. CKIO D31 to D0 A25 to A0 FRAME CS6B RD/ WR WAIT BS DACKn * Figure 12.43 Burst MPX Space Access Timing (Single Read, No Wait, or Software Wait 1)[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 384 of 982 REJ09B0023-0400 Tm1 Tmd1w Tmd1w Tmd1 AD Note: * The wav ef orm for DACKn is when activ e low is specified. CKIO D31 to D0 A25 to A0 FRAME CS6B RD/ WR WAIT BS DACKn * Figure 12.44 Burst MP X Space Access Timing (Single Write, Software Wait 1, Hardware Wai t 1)[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 385 of 982 REJ09B0023-0400 Tm1 Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 A D0 D1 D2 D3 Note: * The wa vef orm for DACKn is when activ e low is specified. CKIO D31 to D0 A25 to A0 FRAME CS6B RD/ WR WAIT BS DACKn * Figure 12.45 Burst MP X Space Access Timing (Burst Read, No Wait, or Software Wait 1,[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 386 of 982 REJ09B0023-0400 Note: * The wa vef orm for DACKn is when activ e low is specified. CKIO D31 to D0 A25 to A0 FRAME CS6B RD/ WR WAIT BS DACKn * Tm1 Tmd1 Tmd2 Tmd3 Tmd4 A D0 D1 D2 D3 Figure 12.46 Burst MP X Space Access Timing (Burst Write, No Wait, CS6BWCR.MPXM D = 0) 12.5.[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 387 of 982 REJ09B0023-0400 The burst ROM interface pe rforms burst operations for all read accesses. For example, in a longword access over a 16-b it bus, valid 16-bit data is read two times and invalid 16-bit data is read six times. These invalid data rea d cycles increase the mem[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 388 of 982 REJ09B0023-0400 6. Data output from an exte rnal device cause d by DMA si ngle addres s transfer is followed by data output from anothe r device that i ncludes this L SI (DMAIW A = 0) For details, see the description of the DMAIWA bit in the CMNCR register. 7. Data output[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 389 of 982 REJ09B0023-0400 Tables 12.18 t o 12.22 li sts the mini mum numbe r of id le cycles to be insert ed for the normal space interface and the SDRAM int erface. The CSnBCR Idle Setting column in the tables desc ribes the number of idle cycles to be set for IWW, IWRWD, I WRWS,[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 390 of 982 REJ09B0023-0400 Table 12.19 Minimum Number of Idle Cycles between Access Cycles during DMAC Dual Addres s Mode Tra n sfer fo r the Norma l Space Interfac e BSC Register Setting When Access S ize is Less than Bus Width When Access Size Exceeds B us Width CSnWCR. WM Setting[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 391 of 982 REJ09B0023-0400 Table 12.20 Minimum Number of Idle Cycles during DMAC Single Address Mode Transfer to the Normal Space Inter face from the External De vice with DACK (1) Transfer fr om the external de vice with DACK to the nor mal space interface BSC Register Setting * 3[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 392 of 982 REJ09B0023-0400 (2) Transfer from the normal space in terface to the external device with DACK BSC Register Setting * 4 When Access Size is Less than Bus Width CSnWCR.WM Setting CSnBCR Idle Setting Continuous Transfer * 1 Non-Continuous Transfer * 2 1 0 0 3 0 0 1 3 1 1 1 [...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 393 of 982 REJ09B0023-0400 Table 12.21 Minimum Number of Idle Cycles between Access Cycles of CPU and the DMAC Dual Address Mode fo r the SD RAM I nterf ace BSC Register Setting CPU Access DMAC Access CSnBCR Idle Setting CS3WCR. WTRP Setting CS3WCR. TRWL Setting Read to Read Write [...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 394 of 982 REJ09B0023-0400 BSC Register Setting CPU Access DMAC Access CSnBCR Idle Setting CS3WCR. WTRP Setting CS3WCR. TRWL Setting Read to Read Write to Write Read to Write Write to Read Read to Write Write to Read 1 2 3 3/3/3/3 5/5/5/5 3/3/4/ 5 5/5/5/5 3 5 1 3 0 4/4/4/4 3/3/3/3 4[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 395 of 982 REJ09B0023-0400 BSC Register Setting CPU Access DMAC Access CSnBCR Idle Setting CS3WCR. WTRP Setting CS3WCR. TRWL Setting Read to Read Write to Write Read to Write Write to Read Read to Write Write to Read 4 2 0 5/5/5/5 4/4/4/4 5/5/5/ 5 4/4/4/4 5 4 4 2 1 5/5/5/5 4/4/4/4 [...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 396 of 982 REJ09B0023-0400 Table 12.22 Minimum Number of Idle Cycles between Access Cycles of the DMAC Sing le Address Mode for the SDRAM Interface (1) Transfer fr om the external de vice with DACK to the SDRAM interface BSC Register Setting * 2 CMNCR.DMAIW Setting CS3WCR.WTRP Setti[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 397 of 982 REJ09B0023-0400 BSC Register Setting * 2 CMNCR.DMAIW Setting CS3WCR.WTRP Setting CS3WCR.TRWL Setting Minimum Number of Idle Cycles 1 3 2 5 1 3 3 6 2 0 1 3 2 0 2 3 2 0 3 3 2 1 0 3 2 1 1 3 2 1 2 3 2 1 3 4 2 2 0 3 2 2 1 3 2 2 2 4 2 2 3 5 2 3 0 3 2 3 1 4 2 3 2 5 2 3 3 6 4 0 [...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 398 of 982 REJ09B0023-0400 (2) Transfer from the SDR AM inte rface to the exte rnal device with DACK BSC Register Setting * 2 CS3BCR Idle Setting CS3WCR.WTRP Setting Minimum Number of Idle Cycles 0 0 3 0 1 3 0 2 3 0 3 4 1 0 3 1 1 3 1 2 3 1 3 4 2 0 3 2 1 3 2 2 3 2 3 4 4 0 5 4 1 5 4 2[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 399 of 982 REJ09B0023-0400 12.5.12 Bu s Arbitr ation The bus arbitra tion of t his LSI has t he bus master ship in the normal state and releases the bus mastership after receiving a bu s request from another device. Bus mastership is transf erred at the boundary of bus cycles. Name[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 400 of 982 REJ09B0023-0400 The sequence for reclaiming the bu s mastership from an ext ernal device i s described bel ow. 1.5 cycles after the negation of BREQ is detected at the falling edge of CKIO, the bus co n trol signals are driven hig h. The bus enable sig nal is negat ed at [...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 401 of 982 REJ09B0023-0400 12.5.13 Others Reset: The bus state controller (BSC) ca n be initialized co mpletely onl y at powe r-on reset . When a power-on reset occurs, internal clocks are sync hr onized by the reset, then all sign als are negated and output buf fers are tur ne d o[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 402 of 982 REJ09B0023-0400 If the CPU initiates read access for the cache, the cac he is searched. If th e cache stores data, the CPU latches the data and completes the read access. If t he cache does not store data, the CPU performs four contiguous longword read cycles to perform c[...]

Section 12 Bus State Controller (BSC) Rev. 4. 00 Sep. 14, 2005 Page 403 of 982 REJ09B0023-0400 DMA source and destination addresses exist in ex ternal memory space, the next write cycle will not be initiated until the prev ious write cycle is completed. If BSC registers are modifie d while the write buffer is functioning, correct access cannot be p[...]

Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 404 of 982 REJ09B0023-0400[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 405 of 982 REJ09B0023-0400 Section 13 Direct Memory Access Controller (DMAC) This LSI includes the direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed transfe rs between external devices that ha ve DACK (tra nsfer requ[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 406 of 982 REJ09B0023-0400 • Transfer request acknowledge and transf er end signals: Active levels for DACK and TEND can be set inde pendently. Figure 13. 1 shows the block di agram of the DM AC. On-chip peripheral module DMA transfer request signal DMA transfer ackno[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 407 of 982 REJ09B0023-0400 13.2 Input/Output Pins The external pins for DMA C are described below . Table 13.1 lists the configuratio n of the pins that are connec ted to external bus. DMAC has pins for 2 cha nnels (channel s 0 and 1) f or external bus use. Table 13.1 [...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 408 of 982 REJ09B0023-0400 13.3 Register Descriptions Register confi guration is described bel ow. See secti on 24, List of Registers , for the addres ses of these registers and the state of them in eac h processing status. Channel 0: • DMA source address register_0 ([...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 409 of 982 REJ09B0023-0400 13.3.1 DMA Source Addr ess Registers (SAR) DMA source address registers (SAR) are 32-bit read/write registers that specify the source address of a DMA transfer. During a DMA transfe r, these registers indi cate the next source address. Whe n [...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 410 of 982 REJ09B0023-0400 13.3.4 DMA Ch an ne l Control Regi sters (CHCR) DMA channel control registers (CHC R) are 32- b it read/write registers that control the DMA transfer mode. The CHCR is initialized to H'00000000 at reset and retains the current value in th[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 411 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Descriptions 21 to 18  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17 AM 0 R/W Acknowledge Mode AM specifies whether DACK is output in data read cycle or in data writ[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 412 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Descriptions 13 12 SM1 SM0 0 0 R/W R/W Source Address Mode SM1 and SM0 select whether the DMA source addr ess is incremented, decremented, or left fixed. (In single address mode, SM1 and SM0 bits are ign ored whe[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 413 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Descriptions 7 6 DL DS 0 0 R/W R/W DREQ Level and DREQ Edge Select These bits specify the sampling method of the DREQ pin input and the sampling le vel. These bits are valid only in CHCR_0 an d CHCR_1. These bit[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 414 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Descriptions 2 IE 0 R/W Interrupt Enable This bit specifies whether or not an interrupt request is generated to the CPU at the end of the DMA transfer. Setting this bit to 1 generates an interr upt request (DEI) [...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 415 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Descriptions 0 DE 0 R/W DMA Enable This bit enabler or disables the DMA transfer . In an auto request mode, DMA transfer starts by setting the DE bit and DME bit in DMAOR to 1. In this time, all of the bits TE, [...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 416 of 982 REJ09B0023-0400 13.3.5 DMA Oper ati on Register (DM AO R ) The DMA operation register (DMAOR) is a 32-bit re ad/write reg ister that specifies the priority level of channels at the DMA tr ansfer. This register shows the DMA transfer status. The DMAOR is initi[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 417 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 25 24 PR1 PR0 0 0 R/W R/W Priority Mode 1, 0 PR1 and PR0 select the priority level betw een channels when there are transfer requests for multiple channels simultaneously. 00: Fixed mode 1: CH0 > [...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 418 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 16 DME 0 R/W DMA Master Enable DME enables or disables DMA transfers on all channels. If the DME bit and the DE bit corresponding to each channel in CHCR are set to 1s, transfer is enabled in the corr[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 419 of 982 REJ09B0023-0400 If (PR1 and PR0) = (B'10) is specified, the channel priority is d etermined according to th e settings of the round-robin select bits. In this case, the channel prior ity is changed between c hannels whose corresp onding roun d-robin sel[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 420 of 982 REJ09B0023-0400 Table 13.2 Combination of the Rou nd -Robi n Select Bits and Priority Mode Bits Priority L evel Round-robin Select bit Transfer End Pri ority bit High Low Mode No. RC0 RC1 RC2 RC3 CH No. PR1 PR0 0 1 2 3 0 0 0 1 1 CH2 1 0 CH0 CH1 CH3 CH2 0 1 1 [...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 421 of 982 REJ09B0023-0400 13.3.6 DMA Exte nsion Resource S el ector 0 an d 1 (DMARS0 , DM A RS 1) DMARS is a 16-bit read/write register th at sp eci fies the DMA t ransfer sources from peri pheral modules in each channel. DM ARS0 specifies fo r channel s 0 and 1 , DMA[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 422 of 982 REJ09B0023-0400 • DMARS1 Bit Bit Name Initial Value R/W Description 15 14 13 12 11 10 C3MID5 C3MID4 C3MID3 C3MID2 C3MID1 C3MID0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Transfer request module ID for DMA channel 3 (MID). See table 13.3. 9 8 C3RID1 C3RID0 0 0 R/W[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 423 of 982 REJ09B0023-0400 Transfer reque sts from the va ri ous modules are specified by the MID and RID as sh own in table 13.3. Table 13.3 Transfer Request Module/Register ID Peripheral Module Setting Value for One Channel (MID + RID) MID RID Function SCIF0 H'8[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 424 of 982 REJ09B0023-0400 13.4 Operation When th ere is a D MA trans fer requ est, th e DMAC starts the transfer acc ording to the predetermined chan nel pri ority order; when the tr ansfer end conditions are satisfied, it ends the transfer. Transfer s can be req ueste[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 425 of 982 REJ09B0023-0400 Figure 13.2 is a flowchart of this p rocedure. Normal end NMIF = 1 or AE = 1 or DE = 0 or DME = 0? Bus mode, transfer request mode, DREQ detection selection system Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR, DMARS) Transfer (1 transfer u[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 426 of 982 REJ09B0023-0400 13.4.2 DMA Tr ansfer Req uests DMA transfer requests are basically generated in e ither the data tran sfer so urce or destinat i on, b ut they can also be generate d by devices and on-chi p peripheral modules that are neither the source nor th[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 427 of 982 REJ09B0023-0400 Table 13.5 Selecting Exte rnal Request Detection wit h Dl, DS Bits CHCR DL DS Detection of External Request 0 Low level detection 0 1 Falling edge detection 0 High level detection 1 1 Rising edge detection When DREQ i s accepted, the DREQ pin[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 428 of 982 REJ09B0023-0400 On-Chip Peripheral Module Request: In this m ode, the trans fer is performe d in respon se to the DMA transfer request signa l of an on - chip periph eral module. Signals that request DMA transfer include A/D conversion-completed tran sfer re [...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 429 of 982 REJ09B0023-0400 CHCR DMARS RS[3:0] MID RID DMA Transfer Request Source DMA Transfer Request Signal Source Desti- nation Bus Mode 1000 101010 00 MTU0 TGI0A (input capture interrupt/ compare match interrupt) Any Any Burst/ cycle steal 110000 00 MTU1 TGI1A (inp[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 430 of 982 REJ09B0023-0400 These are selected by the PR 1 and the PR0 b its in the DMA operation register (DMAOR). Round-Robin Mode: Each time one word, byte, or l ongword is trans ferred on o ne channel, the priority orde r is rotate d. The channel on whi c h the trans[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 431 of 982 REJ09B0023-0400 Figure 13. 4 shows ho w the pri ority orde r changes when channel 0 and c hannel 3 t ransfers a re requested simultaneously and a channel 1 transfer is requested during t he channel 0 transfer. The DMAC operates as follows: 1. Transfer reques[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 432 of 982 REJ09B0023-0400 13.4.4 DMA Transfe r Types DMA transfer has two types; single ad dress mode tra nsfer and dual a ddress mode transfer. The y depend on the number of bus cycl es of access to source and dest ination. A data tra nsfer timing depends on the bu s [...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 433 of 982 REJ09B0023-0400 Address Modes: 1. Dual Address Mode In the dual address mode, both the transfer source and destina tion are accessed (selected) by an address. The source and des tination can be located externally or internally. DMA transfer requires two bus [...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 434 of 982 REJ09B0023-0400 Figure 13.6 s hows an exam ple of DMA t ransfer timing in dual address mode. CKIO A25 to A0 Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn . D31 to D0 WEn RD DACKn[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 435 of 982 REJ09B0023-0400 DMAC This LSI DACK DREQ External address bus External data bus External memory External device with DACK Data flow Figure 13.7 Data Flow in Single Address Mode Two kinds of transfer are p ossib le in single address mode: (1) transfer between [...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 436 of 982 REJ09B0023-0400 Figure 13.8 s hows exampl e of DMA tr ansfer timing in si ngle address mode. Address output to external memory space Select signal to external memory space Select signal to external memory space Data output from external device with DACK DACK [...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 437 of 982 REJ09B0023-0400 Figure 13.9 s hows an exam ple of DMA t ransf er timing in the cycle steal mode. Transfer conditions shown in the figure are: 1. Dual address mode 2. DREQ low level d e tectio n CPU CPU CPU DMAC DMAC CPU DMAC DMAC CPU DREQ Bus cycle Bus maste[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 438 of 982 REJ09B0023-0400 DREQ CPU CPU Bus cycle CPU DMAC DMAC CPU CPU DMAC DMAC CPU Read/Write Read/Write More than 16 or 64B φ (change by the CPU's condition of using bus) Figure 13.10 Example of DMA Transfer in Cycle Steal In termittent Mode (Dual Address, DRE[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 439 of 982 REJ09B0023-0400 Table 13.9 Relationship of Request Mode s and Bus Modes by DMA Transfer Category Address Mode Transfer Category Request Mode Bus Mode Transfer Size (Bits) Usable Channels External device with DACK and external memory External B/C 8/16/32/128 [...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 440 of 982 REJ09B0023-0400 Bus Mode and Channel Priority Order: When channel 1 is tran sferring data in burst mode and a request arrives for tra ns fer on channel 0, which has hi g her- pri ority, the dat a trans fer on chan nel 0 will begin immediately. In this case, i[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 441 of 982 REJ09B0023-0400 CKIO 1st acceptance 2nd acceptance Acceptance star t Bus cycle DREQ (Rising) DACK (Active-high) CPU CPU CPU DMAC Non sensitive period Figure 13.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection CKIO Bus cycle Bus cycle DRE[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 442 of 982 REJ09B0023-0400 CKIO CPU CPU DMAC CKIO CPU CPU DMAC DMAC 1st acceptance 1st acceptance Acceptance star t Acceptance star t Acceptance star t Bus cycle DREQ (Rising) DACK (Active-high) Bus cycle DREQ (Overrun 1 at high lev el) DACK (Active-high) Non sensitive [...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 443 of 982 REJ09B0023-0400 To execute a longword access to an 8-bit or 16-bit extern al device or t o execute a word access to an 8-bit external device, the DACK and TEND outputs are divided f or data ali gnment as shown in figure 13.1 8. CKIO Address DACKn TENDn WAIT [...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 444 of 982 REJ09B0023-0400 13.4.6 Completion of DMA Transfer The conditions for the co mp letion of DMA transfer differ according to wheth er we are considering completion of transfer o n indivi dual channel s or simultane ous compl etion of transfer on all channels. 1.[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 445 of 982 REJ09B0023-0400 • W h en an add ress e rror oc curs dur ing a re ad cycle : Neither read cycles nor write cycles are gene rated; only the transfer re quest is cleared. However, whe n the tra nsfer-reque st source was a n on-chip peripheral m odule (MT U), [...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 446 of 982 REJ09B0023-0400 6. Note the followings when the DMA tran sfer request is sent from the SC IF. Even wh en the DMA C has comple ted the TCR tim es of tran sfers (the TE bit in CHCR = 1), the DMAC accepts and kee ps the transfer reques t from the SCIF (ma x. one[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 447 of 982 REJ09B0023-0400 • Idle cycles between read-read cycles in the same spaces (IWRRS = 01 or more) • External wait mask specification (WM = 0). In addition t o the above co nditions, the followin g conditions are i ncluded depe nding on t he detection method[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 448 of 982 REJ09B0023-0400 CPU DMAC write Non-sensitive period 1st acceptance 2nd acceptance 3rd acceptance possible Non-sensitive period CPU DMAC write Non-sensitive period 1st acceptance 2nd acceptance 3rd acceptance possible Non-sensitive period CKIO Bus cycle DREQ ([...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4. 00 Sep. 14, 2005 Page 449 of 982 REJ09B0023-0400 CPU CPU DMAC write DMAC write Non-sensitive period 1st acceptance 2nd acceptance 3rd acceptance possible 3rd acceptance possible Non-sensitive period Non-sensitive period 1st acceptance 2nd acceptance Non-sensitive period DREQ (Overrun 1, hig[...]

Section 13 Direct Memory Access Cont roller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 450 of 982 REJ09B0023-0400[...]

Section 14 U Memory Rev. 4. 00 Sep. 14, 2005 Page 451 of 982 REJ09B0023-0400 Section 14 U Memory This LSI has on-chip U memory. It ca n be used by the CP U, DSP, an d DMAC to store instr uctions or data. 14.1 Features The U memory features ar e listed in table 14.1 . Table 14.1 U Memo ry Specifications Parameter Features Addressing method Mapping i[...]

Section 14 U Memory Rev. 4.00 Sep. 14, 2005 Page 452 of 982 REJ09B0023-0400 14.2 U Memory Access from CPU The U memory can be acce ssed by the CPU from spaces P0 and P2. Access from the CPU is via the I bus when U memory is sp ace P0, and vi a the L bus when sp ace P2. To use t he L bus, one cycle access is performed unless pa ge conflict occurs . [...]

Section 14 U Memory Rev. 4. 00 Sep. 14, 2005 Page 453 of 982 REJ09B0023-0400 14.5 Usage Note When accessing the U memory by the C PU or th e DSP, if the cache is on, access must be performed from space P2 (non-cac hea ble space). Operation duri ng access from space P0 ca nnot be guaranteed. When the cache i s off, sp aces P0 and P2 can both be used[...]

Section 14 U Memory Rev. 4.00 Sep. 14, 2005 Page 454 of 982 REJ09B0023-0400[...]

Section 15 User Debugging Interf ace (H-UDI) Rev. 4. 00 Sep. 14, 2005 Page 455 of 982 REJ09B0023-0400 Section 15 User Debu gging Interface (H-UDI) This LSI incorporates a user debugging interface (H-UDI) and advanced us er debugger (AUD) for a boundary scan fun ction and emulator su ppo rt. This section describes the H-UDI. The AUD is a fun ction e[...]

Section 15 User Debugging Interf ace (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 456 of 982 REJ09B0023-0400 15.2 Input/Output Pins Table 15.1 sho ws the pin c onfiguration o f the H-UDI. Table 15.1 Pin Configuration Pin Name Input/Output Description TCK Input Serial data input/output clock pin Data is serially supplied to the H-UDI from the data inp ut pi[...]

Section 15 User Debugging Interf ace (H-UDI) Rev. 4. 00 Sep. 14, 2005 Page 457 of 982 REJ09B0023-0400 15.3 Register Descriptions The H-UDI has the following registers. Re fer the s ection 24, List of Registers, for the addresses and access size for these registers. • Bypass register (SDBPR) • Instruction register (SDIR) • Boundary scan regist[...]

Section 15 User Debugging Interf ace (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 458 of 982 REJ09B0023-0400 Table 15.2 H-UDI Commands Bits 15 to 8 TI7 TI6 TI5 TI4 TI3 TI 2 TI1 TI0 Description 0 0 0 0 — — — — JTAG EXTEST 0 0 1 0 — — — — JTAG CLAMP 0 0 1 1 — — — — JTAG HIGHZ 0 1 0 0 — — — — JTAG SAMPLE/PRELOAD 0 1 1 0 — —[...]

Section 15 User Debugging Interf ace (H-UDI) Rev. 4. 00 Sep. 14, 2005 Page 459 of 982 REJ09B0023-0400 Table 15.3 This LSI Pins and Boundary Scan Register Bits Bit Pin Name I/O Bit Pin Name I/O From TDI 454 AUDATA3/PTJ11 IN 483 D7 IN 453 AUDSYNC/PTJ12 IN 482 D6 IN 452 NMI IN 481 D5 IN 451 IRQ0 /PTJ0 IN 480 D4 IN 450 IRQ1 /PTJ1 IN 479 D3 IN 449 IRQ2 [...]

Section 15 User Debugging Interf ace (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 460 of 982 REJ09B0023-0400 Bit Pin Name I/O Bit Pin Name I/O 424 DPLS/PTB8 OUT 392 CS3 /PTA3 Control 423 A18 OUT 391 CS2 /PTA2 Control 422 A19/PTA8 OUT 390 UCLK/PTB0 Control 421 A20/PTA9 OUT 389 VBUS/PTB1 Control 420 A21/PTA10 OUT 388 SUSPND/PTB2 Control 419 A22/PTA11 OUT 387[...]

Section 15 User Debugging Interf ace (H-UDI) Rev. 4. 00 Sep. 14, 2005 Page 461 of 982 REJ09B0023-0400 Bit Pin Name I/O Bit Pin Name I/O 360 IRQ7 /PTJ7 Control 328 TCLKD/PTF8 IN 359 SCK0/PTH0 Control 327 TCLKC/PTF9 IN 358 CTS0 /PTH1 IN 326 TCLKB/PTF10 IN 357 TxD0/PTH2 IN 325 TCLKA/PTF11 IN 356 RxD0/PTH3 IN 324 POE0 /PTF12 IN 355 RTS0 /PTH4 IN 323 PO[...]

Section 15 User Debugging Interf ace (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 462 of 982 REJ09B0023-0400 Bit Pin Name I/O Bit Pin Name I/O 296 CTS2 /PTH11 OUT 264 PTF4 OUT 295 TxD2/PTH12 OUT 263 PTF5 OUT 294 RxD2/PTH13 OUT 262 PTF6 OUT 293 RTS2 /PTH14 OUT 261 PTF7 OUT 292 TIOC4D/PTE0 OUT 260 PTG8 OUT 291 TIOC4C/PTE1 OUT 259 PTG9/SCL OUT 290 TIOC4B/PTE2[...]

Section 15 User Debugging Interf ace (H-UDI) Rev. 4. 00 Sep. 14, 2005 Page 463 of 982 REJ09B0023-0400 Bit Pin Name I/O Bit Pin Name I/O 232 TIOC2B/PTE8 Control 200 AN2/PTG2 IN 231 TIOC2A/PTE9 Control 199 AN3/PTG3 IN 230 TIOC1B/PTE10 Control 198 AN4/PTG4 IN 229 TIOC1A/PTE11 Control 197 AN5/PTG5 IN 228 TIOC0D/PTE12 Control 196 AN6/PTG6 IN 227 TIOC0C/[...]

Section 15 User Debugging Interf ace (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 464 of 982 REJ09B0023-0400 Bit Pin Name I/O Bit Pin Name I/O 168 D28/PTD12 IN 136 BREQ /PTC6 Control 167 D27/PTD11 IN 135 BACK /PTC7 Control 166 D26/PTD10 IN 134 ASEBRKAK /PTC13 Control 165 DREQ0 /PTC9 OUT 133 CS6B /PTC4 Control 164 DREQ1 /PTC10 OUT 132 CS6A /PTC3 Control 163[...]

Section 15 User Debugging Interf ace (H-UDI) Rev. 4. 00 Sep. 14, 2005 Page 465 of 982 REJ09B0023-0400 Bit Pin Name I/O Bit Pin Name I/O 104 RASU /PTA7 IN 72 RASL /PTA6 OUT 103 CKE/PTA1 IN 71 A17 OUT 102 CASL /PTA4 IN 70 A16 OUT 101 RASL /PTA6 IN 69 A15 OUT 100 A0/PTA0 IN 68 A14 OUT 99 D15 IN 67 A13 OUT 98 D14 IN 66 A12 OUT 97 D13 IN 65 A11 OUT 96 D[...]

Section 15 User Debugging Interf ace (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 466 of 982 REJ09B0023-0400 Bit Pin Name I/O Bit Pin Name I/O 40 D20/PTD4 Control 19 A11 Control 39 D19/PTD3 Control 18 A10 Control 38 D18/PTD2 Control 17 A9 Control 37 D17/PTD1 Control 16 A8 Control 36 D16/PTD0 Control 15 A7 Control 35 RD/ WR Control 14 A6 Control 34 WE0 /DQM[...]

Section 15 User Debugging Interf ace (H-UDI) Rev. 4. 00 Sep. 14, 2005 Page 467 of 982 REJ09B0023-0400 15.3.4 ID Regi ster (S DI D) The ID register (S DID) is a 32-bit rea d-only re gister in whic h SDIDH and SDIDL are connected. Each register is a 16-bit that can be read by CPU. The IDCODE command is set from the H- UDI pin. T his regist er can be [...]

Section 15 User Debugging Interf ace (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 468 of 982 REJ09B0023-0400 15.4 Operation 15.4.1 TAP Controller Figure 15.2 s hows the inter nal states of the TAP contr oller. State tra nsitions basical ly conform with the JTAG standa rd . T est-logic-reset Capture-DR Shift-DR Exit1-DR P ause-DR Exit2-DR Update-DR Select-D[...]

Section 15 User Debugging Interf ace (H-UDI) Rev. 4. 00 Sep. 14, 2005 Page 469 of 982 REJ09B0023-0400 15.4.2 Reset Configuration Table 15. 4 Re set Configura tion ASEMD0 * 1 RESETP TRST Chip State H L L Normal res et and H-UDI reset H Normal reset H L H-UDI reset only H Normal operation L L L Reset hold * 2 H Normal reset H L H-UDI reset only H Nor[...]

Section 15 User Debugging Interf ace (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 470 of 982 REJ09B0023-0400 TDO (when the H-UDI command is set) TCK TDO (when the boundary scan command is set) t TDOD t TDOD Figure 15.3 H-UDI Data Tra nsfer Timing 15.4.4 H-UDI Reset An H-UDI reset is executed by inputting an H-UDI reset assert command in SDIR. An H-UDI rese[...]

Section 15 User Debugging Interf ace (H-UDI) Rev. 4. 00 Sep. 14, 2005 Page 471 of 982 REJ09B0023-0400 15.5 Boundary Scan A command can be set i n SDIR by the H-UDI to place t he H-UDI pins in the boundary scan mode stipulated by JTAG. 15.5.1 Supported Instructions This LSI supports the three essential instru cti ons defined in the JTA G standard (B[...]

Section 15 User Debugging Interf ace (H-UDI) Rev. 4.00 Sep. 14, 2005 Page 472 of 982 REJ09B0023-0400 EXTEST: This instruction is provid ed to test external circuitry when the this LSI is mounted on a printed circ uit boa rd. When thi s instructio n is execut ed, output pins are us ed to output test data (previously set by the SA MPLE/PRELOAD in str[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4. 00 Sep. 14, 2005 Page 473 of 982 REJ09B0023-0400 Section 16 I 2 C Bus Interface 2 (IIC2) The I 2 C bus interface 2 c onforms to and pr ovides a subset of the Philips I 2 C (Inter -IC) bus interface functions. However, the configuration of the re gisters that c ontrol the I 2 C bus di f fers partly fro[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 474 of 982 REJ09B0023-0400 SCL ICCR1 Transfer clock generation circuit Address comparator Interrupt generator Interrupt request Bus state decision circuit Arbitration decision circuit Noise canceler Noise canceler Output control Output control Transmission/ reception control circu[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4. 00 Sep. 14, 2005 Page 475 of 982 REJ09B0023-0400 VccQ * VccQ * SCL in SCL out SCL SDA in SDA out SDA SCL (Master) (Slave 1) (Slave 2) SDA SCL in SCL out SCL SDA in SDA out SDA SCL in SCL out SCL SDA in SDA out SDA Note: * The I 2 C bus power supply and this LSI's power supply (VccQ) must be switc[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 476 of 982 REJ09B0023-0400 16.3 Register Descriptions The I 2 C bus interface 2 has the followi ng registers: • I 2 C bus control register 1 (ICCR1) • I 2 C bus control register 2 (ICCR2) • I 2 C bus mode register (ICMR) • I 2 C bus interrupt enab le register (ICIER) • I[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4. 00 Sep. 14, 2005 Page 477 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 5 4 MST TRS 0 0 R/W R/W Master/Slave Select Transmit/Receive Select In master mode with the I 2 C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave rece[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 478 of 982 REJ09B0023-0400 Table 16.2 Transfer Rate Bit 3 Bit 2 Bit 1 Bit 0 Transfer Rate CKS3 CKS2 CKS1 CKS0 Clock φ =5 MHz φ =10 MHz φ =16.5 MHz φ =30 MHz φ =33 MHz 0 0 0 0 φ /28 179 kHz 357 kHz 589kHz 1071kHz 1179kHz 1 φ /40 125 kHz 250 kHz 413kHz 750kHz 825kHz 1 0 φ /4[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4. 00 Sep. 14, 2005 Page 479 of 982 REJ09B0023-0400 16.3.2 I 2 C Bus Control Register 2 (ICCR2 ) ICCR2 is an 8-bit readable/writab le register that issues start/stop conditions, manipu lates the SDA pin, monit ors the SCL pin, and c ontrols reset in the control part of the I 2 C bus interface 2. Bit Bit [...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 480 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 4 SDAOP 1 R/W SDAO Write Protect This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0. Th[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4. 00 Sep. 14, 2005 Page 481 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 5, 4  All 1  Reserved These bits are always read as 1. 3 BCWP 1 R/W BC Write Protect This bit controls the BC2 to BC0 modifications. When modifying BC2 to BC0, this bit should be clear ed to 0. In clock s[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 482 of 982 REJ09B0023-0400 16.3.4 I 2 C Bus Interrupt Enable Register (ICIER) ICIER is an 8-bit readable/writable register th at enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transf erred, and confirms acknow ledge bits received. ICIER is [...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4. 00 Sep. 14, 2005 Page 483 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 3 STIE 0 R/W Stop Condition Detection Interrupt Enable This bit enables or disables the stop conditio n (STPI) when the STOP bit in ICSR is set . 0: Stop condition detection interrupt request (STPI) is disabled[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 484 of 982 REJ09B0023-0400 16.3.5 I 2 C Bus Status Register (I CSR) ICSR is an 8-bit readable/writable reg ister that confirms interrupt request flags and their status. ICSR is initialized to H ' 00 by a pow er-on reset. Bit Bit Name Initial Value R/W Description 7 TDRE 0 R/W[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4. 00 Sep. 14, 2005 Page 485 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 4 NACKF 0 R/W No Acknowledge Detection Flag [Setting condition] • When no acknowledg e is detected from the receive device in transmission while the ACKE bit in ICIER is 1 [Clearing condition] • When 0 is w[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 486 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 1 AAS 0 R/W Slave Addr ess Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting conditions] • When the slave a[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4. 00 Sep. 14, 2005 Page 487 of 982 REJ09B0023-0400 16.3.7 I 2 C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable reg ister that stores the transmit data. When ICDRT detects the space in the shift re gister (ICDRS), it transfers th e transmi t data which is written in ICDRT to ICDRS[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 488 of 982 REJ09B0023-0400 16.4 Operation The I 2 C bus interface can c ommunicate either in I 2 C bus mode or clocked s ynchron ous serial mode by setting FS in SAR. 16.4.1 I 2 C Bus Format Figure 16. 3 shows the I 2 C bus formats. Figure 16.4 shows the I 2 C bus timing. The firs[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4. 00 Sep. 14, 2005 Page 489 of 982 REJ09B0023-0400 [Legend] S: Start condition. The master device driv es SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device w hen R/W is 1, or from the master device to the [...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 490 of 982 REJ09B0023-0400 TDRE SCL (Master output) SDA (Master output) SDA (Slave output) TEND [5] Write data to ICDRT (third byte) ICDRT ICDRS [2] Instruction of start condition issuance [3] Write data to ICDRT (first byte) [4] Write data to ICDRT (second byte) User processing 1[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4. 00 Sep. 14, 2005 Page 491 of 982 REJ09B0023-0400 16.4.3 Master Receive Operation In master receive mode, the master device outputs th e receive clock, receives data from the slave device, and ret urns an acknowl edge signal. For master rece ive mode operat ion timing, r efer to figures 16.7 and 16.8. [...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 492 of 982 REJ09B0023-0400 TDRE TEND ICDRS ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) [3] Read ICDRR 1 A 21 34 56 78 9 9 A TRS RDRF SCL (Master output) SDA (Master output) SDA (Slave output) Bit 7 Master transmit mode Master receive mode Bit 7 Bit[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4. 00 Sep. 14, 2005 Page 493 of 982 REJ09B0023-0400 RDRF RCVD ICDRS ICDRR Data n-1 Data n Data n Data n-1 [5] Read ICDRR after setting RCVD [6] Issue stop condition [7] Read ICDRR, and clear RCVD [8] Set slave receive mode 1 9 23456789 AA / A SCL (Master output) SDA (Master output) SDA (Slave output) Bit[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 494 of 982 REJ09B0023-0400 5. Clear TDRE. TDRE TEND ICDRS ICDRR 1 A 21 34 56 78 9 9 A TRS ICDRT SCL (Master output) Slave receive mode Slave transmit mode SDA (Master output) SDA (Slave output) SCL (Slave output) Bit 7 Bit 7 Data 1 Data 1 Data 2 Data 3 Data 2 Bit 6 Bit 5 Bit 4 Bit[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4. 00 Sep. 14, 2005 Page 495 of 982 REJ09B0023-0400 TDRE Data n TEND ICDRS ICDRR 1 9 2 34 56 78 9 TRS ICDRT A SCL (Master output) SDA (Master output) SDA (Slave output) SCL (Slave output) Bit 7 Slave transmit mode Slave receive mode Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A [3] Clear TEND [5] Clear TDR[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 496 of 982 REJ09B0023-0400 16.4.5 Slave Receive Operation In slave receive mode, the master de vice outputs the transmit clock and tra nsmit data, and the slave device returns a n acknowledge signal. For slave recei ve mode operation timing, refer to figures 16.11 and 16.12. The r[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4. 00 Sep. 14, 2005 Page 497 of 982 REJ09B0023-0400 ICDRS ICDRR 12 34 56 78 9 9 A A RDRF SCL (Master output) SDA (Master output) SDA (Slave output) SCL (Slave output) User processing Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data 1 [3] Set ACKBT [3] Read ICDRR [4] Read ICDRR Data 2 Data 1 Figure 16[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 498 of 982 REJ09B0023-0400 Transmit Oper ation: In transmit mode, transmit data is output from SDA, in synchron izatio n with the fall of the transfer clock. The transfer clock is outpu t when MST in ICCR1 is 1, and is input when MST is 0. For transmit mode operation ti ming, refe[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4. 00 Sep. 14, 2005 Page 499 of 982 REJ09B0023-0400 Receive Operation: In receive mode, data is latched at the rise of the transfer cl ock. The transfer clock is output whe n MST in ICCR1 is 1, and is input when MST is 0. For receive mode opera tion timing, refer to figure 16.15. The reception pro cedure[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 500 of 982 REJ09B0023-0400 12 78 1 7 8 1 2 SCL MST TRS RDRF ICDRS ICDRR SDA (Input) Bit 0 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 1 Bit 1 User processing Data 1 Data 1 Data 2 Data 2 Data 3 [2] Set MST (when outputting the clock) [3] Read ICDRR [3] Read ICDRR Figure 16.15 Receive M[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4. 00 Sep. 14, 2005 Page 501 of 982 REJ09B0023-0400 16.4.7 Noise Filter The logic levels at the SCL and SDA pin s are ro uted through noise f ilter s before being latched internally. Fi gure 16. 17 shows a block di agram of the noise filter ci rcuit. The noise filter consists of three cascaded latches an[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 502 of 982 REJ09B0023-0400 16.4.8 Exampl e of Use Flowcharts in respective modes that us e the I 2 C bus interface are show n in fig ures 16.18 to 16.21. BBSY=0 ? No TEND=1 ? No Yes Start [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [13] [14] [15] Initialize Set MST and TRS in IC[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4. 00 Sep. 14, 2005 Page 503 of 982 REJ09B0023-0400 No Yes RDRF=1 ? No Yes RDRF=1 ? Last receive - 1? Mater receive mode Clear TEND in ICSR Clear TRS in ICCR1 to 0 Clear TDRE in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR Read RDRF in ICSR Read ICDRR Set ACKBT in ICIER to 1 Set RCVD in ICCR1 to 1 Rea[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 504 of 982 REJ09B0023-0400 TDRE=1 ? Yes Yes No Slave transmit mode Clear AAS in ICSR Write transmit data in ICDRT Read TDRE in ICSR Last byte? Write transmit data in ICDRT Read TEND in ICSR Clear TEND in ICSR Set TRS in ICCR1 to 0 Dummy-read ICDRR Clear TDRE in ICSR End [1] Clear [...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4. 00 Sep. 14, 2005 Page 505 of 982 REJ09B0023-0400 No Yes RDRF=1 ? No Yes RDRF=1 ? Last receive - 1? Slave receive mode Clear AAS in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR Read RDRF in ICSR Read ICDRR Set ACKBT in ICIER to 1 Read ICDRR Read RDRF in ICSR Read ICDRR End No Yes [1] [2] [3] [4] [5][...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 506 of 982 REJ09B0023-0400 16.5 Interrupt Request There are six interrupt requ ests in this module; transmit data em pty, transmit end, receive data full, NACK receive, STOP rec ogn ition, and arbitration lost/overrun error. Tabl e 16.3 shows the contents of eac h interr upt req u[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4. 00 Sep. 14, 2005 Page 507 of 982 REJ09B0023-0400 16.6 Bit Synchronous Circuit In master mode, this module has a possibility th at high level period may be short in the two states described belo w. • When SCL is driven to low by the slave device • When the rising spee d of SCL i s lowered b y the l[...]

Section 16 I 2 C Bus Interface 2 (IIC2) Rev. 4.00 Sep. 14, 2005 Page 508 of 982 REJ09B0023-0400 16.7 Usage Note Start (retransmission) and stop conditio ns should be generated after the fall of the ninth clock pulse has bee n detected. To de tect the fall o f the ninth clock pulse , read the SC LO bit in t he I 2 C Bus Control Regist er 2 (ICC R2).[...]

Section 17 Compare Match Timer (CM T) Rev. 4. 00 Sep. 14, 2005 Page 509 of 982 REJ09B0023-0400 Section 17 Compare Match Timer (CMT) This LSI has an on-c hip compare match ti mer (CMT) c onsisti ng of a tw o-channel 16 -bit timer. The CMT has a16-bit count er, and can ge nerate inte rrupts at set intervals . 17.1 Features CMT has the following feat [...]

Section 17 Compare Match Timer (CM T) Rev. 4.00 Sep. 14, 2005 Page 510 of 982 REJ09B0023-0400 17.2 Register Descriptions The CMT has the following re gisters. Refer the section 24, List of Registe rs and access size for these registers. • Compare match timer star t register_0 (CMSTR_0) • Comp are match timer con tro l/status register_0 (CMCSR_0[...]

Section 17 Compare Match Timer (CM T) Rev. 4. 00 Sep. 14, 2005 Page 511 of 982 REJ09B0023-0400 17.2.2 Compare Match Timer Co ntrol/Status Register (CMCSR) CMCSR is a 16-bit register that indicates comp are match gene ration, ena bles inter rupts or DM A transfer requests, and select s the counter input clock. CMCSR is initialized to H'0000 by [...]

Section 17 Compare Match Timer (CM T) Rev. 4.00 Sep. 14, 2005 Page 512 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select These bits select the clock to be input to CMCNT from four internal clocks obtained by divid ing the peripheral operating clock (P φ ). When the STR bit in CMSTR is set to 1[...]

Section 17 Compare Match Timer (CM T) Rev. 4. 00 Sep. 14, 2005 Page 513 of 982 REJ09B0023-0400 17.3 Operation 17.3.1 Interval Count Operation When an internal clock is sel ected with the CK S1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing us ing the selected clock. When the values in CMCNT and CMCOR match, C[...]

Section 17 Compare Match Timer (CM T) Rev. 4.00 Sep. 14, 2005 Page 514 of 982 REJ09B0023-0400 17.4 Compare Matches 17.4.1 Timing of Compare Match Flag Setting When CMCO R and CMCNT mat ch, a compa re match signal i s generat ed and the CM F bit in CMCSR is set to 1. The compare match signal is g e nerated in th e last state in which the values matc[...]

Section 17 Compare Match Timer (CM T) Rev. 4. 00 Sep. 14, 2005 Page 515 of 982 REJ09B0023-0400 17.4.3 Timing of Compare Match Flag Clearing The CMF bit in CMCSR is cleared by firs t, reading as 1 then writing to 0.[...]

Section 17 Compare Match Timer (CM T) Rev. 4.00 Sep. 14, 2005 Page 516 of 982 REJ09B0023-0400[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 517 of 982 REJ09B0023-0400 Section 18 Multi-Functio n Timer Pulse Unit (MTU) This LSI has an on-c hip mult i-functio n timer pul se unit (M TU) that com prises five 16-bit ti mer channels. The block diagram is shown in figur e 18.1. 18.1 Features • Maximum 16-pulse inp[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 518 of 982 REJ09B0023-0400 Table 18.1 MTU Functions Item Channel 0 Channel 1 Ch annel 2 Channel 3 Channel 4 Count clock φ /1 φ /4 φ /16 φ /64 TCLKA TCLKB TCLKC TCLKD φ /1 φ /4 φ /16 φ /64 φ /256 TCLKA TCLKB φ /1 φ /4 φ /16 φ /64 φ /1024 TCLKA TCLKB TCLKC φ [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 519 of 982 REJ09B0023-0400 Item Channel 0 Channel 1 Ch annel 2 Channel 3 Channel 4 DMA activation TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 520 of 982 REJ09B0023-0400 Internal data bus A/D converter conversion start signal TCNT TGRA TGRB TGRC TGRD TCR TIORH TIER TMDR TIORL TSR Channel 3 TCNT TGRA TGRB TGRC TGRD TMDR TIORL TSR TCR TIORH TIER Channel 4 TCNTS TCDR TCBR TDDR TOER TOCR TGCR BUS I/F Common TCNT TGR[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 521 of 982 REJ09B0023-0400 18.2 Input/Output Pins Table 18.2 MTU Pin Configuration Channel Symbol I/O Function All TCLKA Input External clock A input pin (Channel 1 phase counting m ode A phase input) TCLKB Input External clock B input pi n (Channel 1 phase counting m od[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 522 of 982 REJ09B0023-0400 18.3 Register Descriptions The MTU has the following registers. To distinguish registers in each cha nnel, TCR for channel 0 is expressed a s TCR_0. • Timer control register_0 (TCR_0) • Timer mode register_0 (TMDR_0) • Timer I/O control re[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 523 of 982 REJ09B0023-0400 • Timer I/O control register L_3 (TIORL_3) • Timer interrupt enable register_3 (TIER_3) • Timer status register_3 (TSR_3) • Timer co unter_3 (TCNT_ 3) • Timer general register A_3 (TGRA_ 3) • Timer general register B_3 (TGR B_ 3) ?[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 524 of 982 REJ09B0023-0400 18.3.1 Timer Control Register (TCR) The TCR registers are 8-bit readab le/writable registers that cont rol the TCNT operation for each channel. The MTU has a total of five TCR regist ers, one for each chan nel (channel 0 to 4). TCR register sett[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 525 of 982 REJ09B0023-0400 Table 18.3 CCLR0 to CCLR2 (Ch annels 0, 3, and 4) Channel Bit 7 CCLR2 Bit 6 CCLR1 Bit 5 CCLR0 Description 0, 3, 4 0 0 0 TCNT clearin g disabled 1 TCNT cleared by TGRA compare match/i nput capture 1 0 TCNT cleared by TGRB compare match/input cap[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 526 of 982 REJ09B0023-0400 Table 18.5 TPSC0 to TPSC2 (Channel 0) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 0 Internal clock: counts on P φ /1 1 Internal clock: counts on P φ /4 1 0 Internal clock: counts on P φ /16 1 Internal clock: counts on P φ /[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 527 of 982 REJ09B0023-0400 Table 18.7 TPSC0 to TPSC2 (Channel 2) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 2 0 0 0 Internal clock: counts on P φ /1 1 Internal clock: counts on P φ /4 1 0 Internal clock: counts on P φ /16 1 Internal clock: counts on P φ [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 528 of 982 REJ09B0023-0400 18.3.2 Timer Mode Register (TMDR) The TMDR registers a re 8-bit readab le/ writable re gisters that are used to set the operatin g mode of each channel. The MTU has five TMDR registers, one for each channel. TM DR register settings should be c h[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 529 of 982 REJ09B0023-0400 Table 18.9 MD0 to MD3 Bit 3 MD3 Bit 2 MD2 Bit 1 MD1 Bit 0 MD0 Description 0 0 0 0 Normal o peration 1 Reserved (do not set) 1 0 PWM mode 1 1 PWM mode 2 * 1 1 0 0 Phase counting mode 1 * 2 1 Phase counting mode 2 * 2 1 0 Phase countin g mode 3 *[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 530 of 982 REJ09B0023-0400 18.3.3 Timer I/O Cont rol Register (TIOR) The TIOR registers are 8-bit readable/writable re gisters that control the T GR registers. The MTU has eight TI OR registers, t wo each for channels 0, 3, and 4, an d one each fo r channels 1 and 2. Care[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 531 of 982 REJ09B0023-0400 • TIORL_0, TIORL_3, TIORL_4 Bit Bit Name Initial value R/W Description 7 6 5 4 IOD3 IOD2 IOD1 IOD0 0 0 0 0 R/W R/W R/W R/W I/O Control D3 to D0 Specify the function of TGRD. When TGRD is used as the buffer register of TGRB, this setting is di[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 532 of 982 REJ09B0023-0400 Table 18.10 TIORH_0 ( Channel 0) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_0 Function TIOC0B Pin Function 0 Output hold * 0 1 Initial output is 0 0 output at compare match 0 Initial output is 0 1 output at compare match 0 1 1 [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 533 of 982 REJ09B0023-0400 Table 18.11 TIORL_0 (Channel 0) Description Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 TGRD_0 Function TIOC0D Pin Function 0 0 0 0 Output hold * 1 1 Initial output is 0 0 output at compare match 1 0 Output compare register * 2 Initial output i[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 534 of 982 REJ09B0023-0400 Table 18.12 TIOR_1 (Channel 1) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_1 Function TIOC1B Pin Function 0 0 0 0 Output hold * 1 Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 ou[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 535 of 982 REJ09B0023-0400 Table 18.13 TIOR_2 (Channel 2) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_2 Function TIOC2B Pin Function 0 0 0 0 Output hold * 1 Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 o[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 536 of 982 REJ09B0023-0400 Table 18.14 TIORH_3 ( Channel 3) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_3 Function TIOC3B Pin Function 0 0 0 0 Output hold * 1 Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 537 of 982 REJ09B0023-0400 Table 18.15 TIORL_3 (Channel 3) Description Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 TGRD_3 Function TIOC3D Pin Function 0 0 0 0 Output hold * 1 1 Output compare register * 2 Initial output is 0 0 output at compare match 1 0 Initial output i[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 538 of 982 REJ09B0023-0400 Table 18.16 TIORH_4 ( Channel 4) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_4 Function TIOC4B Pin Function 0 0 0 0 Output hold * 1 Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 539 of 982 REJ09B0023-0400 Table 18.17 TIORL_4 (Channel 4) Description Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 TGRB_4 Function TIOC4B Pin Function 0 0 0 0 Output hold * 1 1 Output compare register * 2 Initial output is 0 0 output at compare match 1 0 Initial output i[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 540 of 982 REJ09B0023-0400 Table 18.18 TIORH_0 ( Channel 0) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_0 Function TIOC0A Pin Function 0 0 0 0 Output hold * 1 Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 541 of 982 REJ09B0023-0400 Table 18.19 TIORL_0 (Channel 0) Description Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 TGRC_0 Function TIOC0C Pin Function 0 0 0 0 Output hold * 1 1 Output compare register * 2 Initial output is 0 0 output at compare match 1 0 Initial output i[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 542 of 982 REJ09B0023-0400 Table 18.20 TIOR_1 (Channel 1) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_1 Function TIOC1A Pin Function 0 0 0 0 Output hold * 1 Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 ou[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 543 of 982 REJ09B0023-0400 Table 18.21 TIOR_2 (Channel 2) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_2 Function TIOC2A Pin Function 0 0 0 0 Output hold * 1 Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 o[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 544 of 982 REJ09B0023-0400 Table 18.22 TIORH_3 ( Channel 3) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_3 Function TIOC3A Pin Function 0 0 0 0 Output hold * 1 Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 545 of 982 REJ09B0023-0400 Table 18.23 TIORL_3 (Channel 3) Description Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 TGRC_3 Function TIOC3C Pin Function 0 0 0 0 Output hold * 1 1 Output compare register * 2 Initial output is 0 0 output at compare match 1 0 Initial output i[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 546 of 982 REJ09B0023-0400 Table 18.24 TIORH_4 ( Channel 4) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_4 Function TIOC4A Pin Function 0 0 0 0 Output hold * 1 Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 547 of 982 REJ09B0023-0400 Table 18.25 TIORL_4 (Channel 4) Description Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 TGRA_4 Function TIOC4C Pin Function 0 0 0 0 Output hold * 1 1 Output compare register * 2 Initial output is 0 0 output at compare match 1 0 Initial output i[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 548 of 982 REJ09B0023-0400 18.3.4 Timer Interrupt Enable Register (TIER) The TIER registers are 8-bit read able/writable registers that control enabling or disabling of interrupt re quests for eac h channel. T he MTU has five TIER regi sters, on e for each cha nnel. Bit B[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 549 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 3 TGIED 0 R/W TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 3 is reserved. [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 550 of 982 REJ09B0023-0400 18.3.5 Timer Status Register (TSR) The TSR registers a re 8-bit readable/writable re gist ers that indicate the status of eac h channel. The MTU has five TSR registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TCFD 1 R [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 551 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 4 TCFV 0 R/(W) Overflow Flag Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Setting conditions] • When the TCNT value overflows (chan ges from [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 552 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 2 TGFC 0 R/(W) Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 553 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 0 TGFA 0 R/(W ) Input Capture/Output Compare Flag A Status flag that indicates t he occurrence of TGRA input capture or compare match. Only 0 can be written, for flag clearing . [Setting conditions] ?[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 554 of 982 REJ09B0023-0400 18.3.8 Timer Start Register (TSTR) TSTR is an 8- bit readable/ writable regi ster that sel ects operat ion/stoppage for channel s 0 to 4. When setti ng the operat ing mode i n TMDR or setting the c ount clock i n TCR, fi rst stop the TC NT count[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 555 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 7 6 SYNC4 SYNC3 0 0 R/W R/W Timer Synchro 4 and 3 These bits are used to select whether operation is independent of or synchronized with other ch annels. When synchronous operati on is selected, the TC[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 556 of 982 REJ09B0023-0400 18.3.10 Timer Output Master Enabl e Register (TOER) TOER is an 8 -bit readabl e/writa ble register that ena bles/dis ables output settings fo r output pins TIOC4D, TI OC4C, TIOC 3D, TIOC4B , TIOC4A , and TIOC 3B. These pi ns do not output correc[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 557 of 982 REJ09B0023-0400 18.3.11 Timer Output Co ntrol Register (TOCR) TOCR is an 8-bit readable/writab le register that enables/disab les PWM synchronized togg le output in c omplementar y PWM mode/ reset synchronized PWM mode, a nd cont rols output l evel inversio n [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 558 of 982 REJ09B0023-0400 Table 18.27 Output Level Select Function Bit 1 Function Compare Match Output OLSP Initial Output Active Level Increment Count Decrement Count 0 High level Low level Low level High l evel 1 Low level High level High level Low level Figure 18.2 s [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 559 of 982 REJ09B0023-0400 18.3.12 Timer Gate Cont rol Re giste r (TGCR) TGCR is an 8-bit readable/writab le reg ister that controls the waveform outp u t necessary for brushless DC motor co ntrol in reset-synchro nized PWM m ode/compl ementary P WM mode. T hese register[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 560 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 3 FB 0 R/W External Feedback Signal Enable This bit selects whether the switching of the output of the positive/reverse phase is c arried out automatically with the MTU/channel 0 TGRA, TGRB, TGRC input [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 561 of 982 REJ09B0023-0400 18.3.13 Timer Subcounter (TCNTS) TCNTS is a 16 -bit read-onl y counter that is used only in compl ementary P WM mode. Note: Accessing TCNTS in 8-bit units is prohibited. Alw ays access in 16-b it units. 18.3.14 Timer Dead Time Data Regi ster (T[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 562 of 982 REJ09B0023-0400 18.3.17 Bus Master Interface The timer counters (TCNT), general reg isters ( TGR), timer subcounter (TCNTS), timer period buffer register (TCBR), and timer dead time data re gister (TDDR), and timer p eriod data register (TCDR) are 1 6-bit regi [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 563 of 982 REJ09B0023-0400 Example of Count Operation Setting Proc edure: Figure 18.3 shows a n example of the count operation setting procedu r e. Operation selection Select counter clock Periodic counter Select counter clearing source Select output compare register Set[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 564 of 982 REJ09B0023-0400 TCNT value H'FFFF H'0000 CST bit TCFV Time Figure 18.4 Free-Running Counter Operation When compare match is selected as the TC NT cl earing source, the TCNT co unter for the relevant channel perfor ms periodic c ount operati on. The TG[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 565 of 982 REJ09B0023-0400 Example of Setting Pr ocedure for Wa veform Output by Compare Match: Fi g ure 18 . 6 sh ows an example of the setting procedure fo r waveform output by comp are match Output selection Select waveform output mode Set output timing Start count op[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 566 of 982 REJ09B0023-0400 Figure 18.8 shows an ex ample of toggle output. In this example, TCNT has b een designated as a periodic co unt er (with c ounter cl earing on compare match B ), and settin gs have bee n made such that the output is toggled by both c ompare matc[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 567 of 982 REJ09B0023-0400 Example of Input Capture Operation Setting Procedure: Figure 18.9 shows an exa mple of t he input capture operation setting procedure. Input selection Select input capture input Start count <Input capture operation> [1] [2] [1] Designate [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 568 of 982 REJ09B0023-0400 TCNT value H'0180 H'0000 TIOCA TGRA H'0010 H'0005 Counter cleared by TIOCB input (falling edge) H'0160 H'0005 H'0160 H'0010 TGRB H'0180 TIOCB Time Figure 18.10 Example of Input Capture Operation 18.4.[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 569 of 982 REJ09B0023-0400 Example of S ynchronous O peration Setti ng Procedure: Figure 18.11 show s an ex ample of the synchronous operatio n setting procedure. No Yes Set synchronous operation <Synchronous presetting> <Counter clearing> <Synchronous cle[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 570 of 982 REJ09B0023-0400 Example of Synchronous O peration: Fi gure 18.1 2 shows an e xample of synchron ous operatio n. In this exam ple, synchr onous operat ion and PWM mode 1 have been designate d for cha nnels 0 to 2, TGRB_0 compare match has been set as the channel[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 571 of 982 REJ09B0023-0400 18.4.3 Buffer Operation Buffer operation , provided for chan nels 0, 3, and 4, enab les TGRC an d TGRD to be used as buff er registers. Buffer operation diffe rs depending on wheth e r TGR has be en desi g nat ed as an input ca p t ure register[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 572 of 982 REJ09B0023-0400 • When TGR is an inpu t capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to th e buffer register. This operation is illustrated in fi[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 573 of 982 REJ09B0023-0400 Examples of Buffer Oper at i on: • When TGR is an output com pare re gi st er Figure 18.16 shows an operat i on exam pl e in whic h PWM mode 1 has been desig nated for channel 0, and buffe r o perati o n has bee n designated for TG R A a nd T[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 574 of 982 REJ09B0023-0400 TCNT value H'09FB H'0000 TGRC Time H'0532 TIOCA TGRA H'0F07 H'0532 H'0F07 H'0532 H'0F07 H'09FB Figure 18.17 Example of Buffer Operat io n (2) 18.4.4 Cascaded Operation In cascaded ope ration, two 16-b[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 575 of 982 REJ09B0023-0400 Example of Cascaded Oper ation Setting Procedure: Figure 18.18 shows an example of th e setting procedure for cascaded operation. Cascaded operation Set cascading Start count <Cascaded operation> [1] [2] [1] Set bits TPSC2 to TPSC0 in the[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 576 of 982 REJ09B0023-0400 18.4.5 PWM Modes In PWM mode , PWM wave forms are o utput from t he outpu t pins. The output le vel can be select ed as 0, 1, or toggle output i n respon se to a compare match of each T GR. TGR registers settings can be used to output a PWM wave[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 577 of 982 REJ09B0023-0400 The correspon dence between PWM output pi ns and regist ers is show n in table 1 8.31. Table 18.31 PWM Out p ut Registers and Outp ut Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 TGRA_0 TIOC0A TGRB_0 TIOC0A TIOC0B TGRC_0 TIOC0C 0 TG[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 578 of 982 REJ09B0023-0400 Example of PWM Mode Setting Procedure: Fi gure 18.20 s hows an exa mple of the PWM mode setting procedu re. PWM mode Select counter clock Select counter clearing source Select waveform output level Set TGR Set PWM mode Start count <PWM mode&g[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 579 of 982 REJ09B0023-0400 Figure 18.22 sh ow s an example of PWM mode 2 oper ation. In this exam ple, synchr onous operati on is de signated fo r channels 0 and 1, TGR B_1 com pare match is set as the TCNT clearing source, and 0 is set f or the init ial output val ue an[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 580 of 982 REJ09B0023-0400 Figure 18.23 sh ow s examples of PWM wav eform output with 0% du ty cy cle and 100% duty cy cle in PWM mode. TCNT value TGRA H'0000 TIOCA Time TGRB 0% duty cycle TGRB rewritten TGRB rewritten TGRB rewritten TCNT value TGRA H'0000 TIOCA[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 581 of 982 REJ09B0023-0400 18.4.6 Phase Counting Mode In phase counting mode, the phase difference betw een t wo external clock inputs is detected a nd TCNT counts up or down acc ordingly. T his mode can be set for c hannels 1 and 2 . When pha s e counting mod e is set, [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 582 of 982 REJ09B0023-0400 Example of Phase Countin g Mode Setting Procedure: Fi gure 18.24 shows an example of the phase countin g mode setti ng procedure. Phase counting mode Select phase counting mode Start count <Phase counting mode> [1] [2] [1] Select phase cou[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 583 of 982 REJ09B0023-0400 Table 18.33 Up /Down-Count Condit io ns in Phase Counting Mode 1 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation High level Up-count Low level Low level High level High level Down-count Low level High level Low[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 584 of 982 REJ09B0023-0400 Table 18.34 Up /Down-Count Condit ions in Phase Countin g Mode 2 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation High level Don't care Low level Don't care Low level Don't care High level Up-count[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 585 of 982 REJ09B0023-0400 Table 18.35 Up /Down-Count Condit io ns in Phase Counting Mode 3 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation High level Don't care Low level Don't care Low level Don't care High level Up-coun[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 586 of 982 REJ09B0023-0400 Table 18.36 Up /Down-Count Condit ions in Phase Countin g Mode 4 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation High level Up-count Low level Low level Don't care High level High level Down-count Low level[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 587 of 982 REJ09B0023-0400 TCNT_1 TCNT_0 Channel 1 TGRA_1 (speed period capture) TGRA_0 (speed control period) TGRB_1 (position period capture) TGRC_0 (position control period) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 TCLKA TCLKB Edge detection ci[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 588 of 982 REJ09B0023-0400 18.4.7 Reset-Synchronized PWM Mode In the reset-sy nchronized P WM mode, t hree-phase output of positive a nd negative PWM waveforms tha t share a comm on wave transi tion poi nt can be o btained by com bining chan nels 3 and 4. When set for r e[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 589 of 982 REJ09B0023-0400 Procedure for Selecting the Reset-Synchr onized PWM Mode: Fi gure 18.3 0 shows an e xample of procedure for selecting t he reset sy nchronized PWM mode. 7 1 2 3 4 Stop counting Select counter clock and counter clear source Set TGR Reset-synchro[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 590 of 982 REJ09B0023-0400 Reset-Synchronized PWM Mode Operati on: Fi gure 18.31 s hows an exampl e of operat ion in the reset-synchronized PWM mode. TCNT_3 and TCNT_4 operate as up coun ter s. The counter is cleared when a TCNT_3 an d TGRA_3 compare-match o ccurs, and th[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 591 of 982 REJ09B0023-0400 18.4.8 Complementary PWM Mode In the comple mentary PWM mode, three- phase output o f non-overla pping posi tive and negati ve PWM waveforms ca n be obt a ined by combini n g c han nel s 3 and 4. In compleme ntary PWM mode, TIOC 3B, TIOC 3D, TI[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 592 of 982 REJ09B0023-0400 Table 18.40 Register Settings for Complementary PWM Mode Channel Counter/Register Descri ption Read/Write from CPU 3 TCNT_3 Start of up-count from value set in dead time register Maskable by PTE/PEMTURWE setting * TGRA_3 Set TCNT_3 upper lim it [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 593 of 982 REJ09B0023-0400 TGRC_3 TDDR TCNT_3 TGRD_3 TGRD_4 TGRC_4 TGRB_3 Temp 1 TGRA_4 Temp 2 TGRB_4 Temp 3 TCNTS TCNT_4 TGRA_3 TCDR TCBR Comparator Comparator Match signal Match signal Output controller Output protection circuit PWM cycle output PWM output 1 PWM output[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 594 of 982 REJ09B0023-0400 Example of C omplementary P WM Mode Set ting Procedure An example of the complemen tary PWM mode se tting procedure is shown in figure 18.33. Complementary PWM mode Stop count operation Counter clock, counter clear source selection Brushless DC [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 595 of 982 REJ09B0023-0400 Outline of Complement ar y PWM Mode Operatio n In complementary PWM mode, 6-ph ase PWM output is possible. Figure 18.34 illu str ates counter operation in complementar y PWM mode, a nd figure 18.35 shows an exampl e of comple mentary PWM mode o[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 596 of 982 REJ09B0023-0400 Counter value TGRA_3 TCDR TDDR H'0000 TCNT_4 TCNTS TCNT_3 TCNT_3 TCNT_4 TCNTS Time Figure 18.34 Complementary PWM Mode Counter Operation Register Operation: In c omplementary P WM mode, ni ne registers are used, com prising com pare registe[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 597 of 982 REJ09B0023-0400 with the counter. In this interval, th erefore, there are two compare match registers for one-phase output, wit h the compa re register co ntaining the pre-chang e data, and the temporary register containing t he new data. I n this interval , t[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 598 of 982 REJ09B0023-0400 Initialization: In complementary PWM mode, there are si x registers that must be initialized. Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register (TMDR), the following initial register values must be set. TGRC_3[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 599 of 982 REJ09B0023-0400 Dead Time Setting: In c omplementar y PWM mode, PWM puls es are output wi th a non- overlapping relationsh ip between the positive and neg ative phases. This non-overlap time is called the dead time. The non-overlap time is set in the timer dea[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 600 of 982 REJ09B0023-0400 Counter value TGRC_3 update TGRA_3 update TGRA_3 TCNT_3 TCNT_4 Time Figure 18.36 Example of PWM Cycle Updating Register Data Upda ti ng : In complementary PWM mode, the buff er register is used to update the data in a compare re gister. T he upd[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 601 of 982 REJ09B0023-0400 Data update timing: counter crest and trough Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to comp[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 602 of 982 REJ09B0023-0400 Initial Output in Complementary PWM Mode: In comp lemen tary PWM mode, the initial output is determined by t he setti ng of bits O LSN and OLSP in the timer output c ontrol regi ster (TOCR). This initial outpu t is th e PWM pulse non-active leve[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 603 of 982 REJ09B0023-0400 Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3, 4 value TGR_4 TDDR TCNT_3 TCNT_4 Initial output Time Active level TCNT_3, 4 count start ([...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 604 of 982 REJ09B0023-0400 Complementary PWM Mode PWM O utput Generation Method: In complem entary PWM mode, 3-phase output is pe rf o rme d of PWM waveform s wi th a non- ove rlap time between the positive and n egative phases. This non- ov erlap time is called the dead [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 605 of 982 REJ09B0023-0400 T2 period T1 period T1 period ab c a' b' d TGR3A_3 TCDR TDDR H'0000 Positive phase Negative phase Figure 18.40 Example of Complementar y PWM Mode Waveform O utput (1)[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 606 of 982 REJ09B0023-0400 T2 period T1 period T1 period TGRA_3 TCDR TDDR H'0000 Positive phase Negative phase c d a a b b Figure 18.41 Example of Complementar y PWM Mode Waveform O utput (2)[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 607 of 982 REJ09B0023-0400 ab c a' b' d T1 period T2 period T1 period TGRA_3 TCDR TDDR H'0000 Positive phase Negative phase Figure 18.42 Example of Complementar y PWM Mode Waveform O utput (3)[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 608 of 982 REJ09B0023-0400 Complementary PWM Mode 0% and 100% Duty Output: In complementary PWM mode, 0% and 100% duty cycles can be out put as re quired. Figu res 18.43 to 1 8.47 show output exa mples. 100% duty output is perfor med when t he data re gister value is set [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 609 of 982 REJ09B0023-0400 T2 period T1 period T1 period TGRA_3 TCDR TDDR H'0000 Positive phase Negative phase a c d a b b Figure 18.44 Example of Complementar y PWM Mode 0% and 100% W aveform Out put (2) T2 period T1 period T1 period a b c d TGRA_3 TCDR TDDR H&apos[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 610 of 982 REJ09B0023-0400 TGRA_3 TCDR TDDR H'0000 Positive phase Negative phase T2 period T1 period T1 period a b c b' d a' Figure 18.46 Example of Complementar y PWM Mode 0% and 100% W aveform Out put (4) ca d b T2 period T1 period T1 period TGRA_3 TCDR T[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 611 of 982 REJ09B0023-0400 Toggle Out put Synchronized with PWM Cycle: In complementar y PWM mode, toggle ou tpu t can be perform ed in sync hronization wi th the PWM carrier cycle by setting the PSYE bit to 1 in the timer outp ut control register (TOC R). An exam ple of[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 612 of 982 REJ09B0023-0400 Counter Clearing by another Channel: I n complement ary PWM mode, b y setting a mode f or synchronizati on with a nother chan nel by means of the time r synchro re gister (T SYR), an d selecting synchronou s clearing with bits CCLR2 to CCLR0 in [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 613 of 982 REJ09B0023-0400 Example of AC Synchronou s Motor (Brush less DC Motor) Dri ve Waveform Output: In complementar y PWM mode, a brushless DC motor can easily be cont rolled usin g the timer gate control regist er (TGCR). Figures 18 .50 to 18 .53 show exa mples of[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 614 of 982 REJ09B0023-0400 External input TIOC0A pin TIOC0B pin TIOC0C pin TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin 6-phase output When BCD = 1, N = 1, P = 1, FB = 0, output active level = high Figure 18.51 Example of Output Phase S witching by Ex[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 615 of 982 REJ09B0023-0400 TGCR UF bit VF bit WF bit TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin 6-phase output When BCD = 1, N = 1, P = 1, FB = 1, output active level = high Figure 18.53 Example of Outp ut Ph ase Swi tchi n g by Mea ns of UF, VF, W[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 616 of 982 REJ09B0023-0400 Some registers in channels 3 and 4 conce rned are list ed below: tot al 21 regi sters of TCR _3 and TCR_4; TMD R_3 and TM DR_4; TI ORH_3 and TIORH_4; TIORL_3 a nd TIORL _4; TIER_3 a nd TIER_4; TCNT_3 and TCNT_4 ; TGRA _3 and TGR A_4; TGRB _3 and[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 617 of 982 REJ09B0023-0400 Table 18.42 MTU Interrupts Channel Name Interrupt Source Interrupt Flag DMA Activation Priority 0 TGI0A TGRA_0 input capture/ co mpare match TGFA_0 Possible High TGI0B TGRB _0 input capture/com pare match TGFB_0 Not possible TGI0C TGRC_0 input [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 618 of 982 REJ09B0023-0400 Overflow Interrupt : An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channe l. The in terrupt request is cleared by clearing th e TCFV flag to 0. The MT[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 619 of 982 REJ09B0023-0400 18.6 Operation Timing 18.6.1 Input/Output Timing TCNT Count Timing: Figure 18.54 shows TCNT count timing in internal clock operation, and figure 18.55 s hows TCNT c ount timi ng in exter nal clock o peration (norm al mode), a nd figure 18.56 sh[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 620 of 982 REJ09B0023-0400 P φ External clock TCNT input clock TCNT Falling edge Falling edge Rising edge N-1 N N+1 Figure 18.56 Count Timing in External Clock Operation (P hase Countin g Mode) Output Compare Output Timing: A compare matc h signal is generated in the fin[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 621 of 982 REJ09B0023-0400 P φ TCNT input clock TCNT N N+1 TGR Compare match signal TIOC pin N Figure 18.58 Output Compare O utput Timing (Complementary PWM Mode/Res et S ynchronous PW M Mode) Input Capture Si gnal T iming: Figu re 18.59 s hows input captu re signal t i[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 622 of 982 REJ09B0023-0400 Timing for Counter Clearing by Compare Matc h/Inpu t Capture: Fi g u re 18.6 0 s how s the timing when co unter clearing on comp are match is specified , and figure 18.61 sh ows the timing when cou nter clear ing on input ca p ture is spec ified[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 623 of 982 REJ09B0023-0400 Buffer Operation Timing: Figures 18.62 an d 18.63 sh ow the timi ng in buffe r operati on. TGRA, TGRB Compare match signal TCNT TGRC, TGRD n N N n n+1 P φ Figure 18.62 Buffer Oper at ion Timing (Compare Match) TGRA, TGRB TCNT Input capture sig[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 624 of 982 REJ09B0023-0400 18.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 18.64 shows the timing fo r setting of t he TGF flag i n TSR on c ompare match, an d TGI inter rupt reque st signal timin g. TGR TCNT TCNT input clock N N N+[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 625 of 982 REJ09B0023-0400 TCFV Flag/TCFU Flag Setting Timing: Figure 18.66 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrup t request signal timing. Figure 18.67 shows the timing for setting of the TCFU flag in TSR on underflow, and TC[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 626 of 982 REJ09B0023-0400 Status Flag Clearing Timing: After a status flag is read as 1 by the C PU, it is cleared by writing 0 to it. When the DMA is activated, th e flag is cleared automatically. Figure 18.68 shows the timing for st atus flag cl earing by t he CPU, and[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 627 of 982 REJ09B0023-0400 18.7 Usage Notes 18.7.1 Module Standby Mode Setting MTU operatio n can be di sabl ed or enabled using the mo d ul e stan db y regi s t er. 18.7.2 Input Clock Restrictions The input cloc k pulse wi dth must be at least 1.5 st ates in the case of[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 628 of 982 REJ09B0023-0400 18.7.3 Caution on Pe riod Settin g When cou nter clea ring on com p are match is set, TCNT is cleared in the final state in which it matches the TGR value (the poi nt at which the count val ue matched by TCNT is updated). Consequently , the actu[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 629 of 982 REJ09B0023-0400 18.7.5 Conflict between TCNT Wr ite and Increment Operati ons If incrementing occurs i n the T2 state of a TC NT write cycle, th e TCNT write takes precedence and TCNT is not incremented. Figure 18.72 shows the timing in this case. TCNT input c[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 630 of 982 REJ09B0023-0400 18.7.6 Conflict between TG R Write and Compare Match When a compare match occurs in the T2 state of a TGR wri te cycle, the TGR write is e xecuted and the compare match signal is ge nerated. Figure 18.73 shows the timing in this case. Compare ma[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 631 of 982 REJ09B0023-0400 Compare match buffer signal Compare match signal Write signal Address P φ Buffer register address Buffer register TGR write cycle T1 T2 M TGR N M Buffer register write data Figure 18.74 Conflict between Buffer Register Write and Compare Match [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 632 of 982 REJ09B0023-0400 18.7.8 Conflict between TG R Read and Input Capture If an input ca pture signal i s generate d in the T2 stat e of a TGR read cycle, the data that is read will be that in the buffer after input cap ture transfer. Figure 18.76 shows the timing in[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 633 of 982 REJ09B0023-0400 18.7.9 Conflict between TG R Write and Input Capture If an input ca pture signal i s generate d in the T2 state of a T GR write cycle, the input capture operation takes precedence and the wr ite to TGR is not performed. Figure 18.77 shows the t[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 634 of 982 REJ09B0023-0400 18.7.10 Conflict between Buffer Re gister Write and Input Capture If an input ca pture signal i s generate d in the T2 st ate of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer regist er is not pe[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 635 of 982 REJ09B0023-0400 T1 T2 H'FFFE H'FFFF N N + 1 H'FFFF M M N P QP M Disabled TCNT_2 write data TCNT_2 address TCNT write cycle P φ Address Write signal TCNT_2 TGR2A_2 to TGR2B_2 Ch2 compare- match signal A/B TCNT_1 input clock TCNT_1 TGRA_1 Ch1 com[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 636 of 982 REJ09B0023-0400 18.7.12 Coun ter Val u e during Co mplementary PWM Mode Stop When count ing operati on is stop ped with TC NT_3 and TC NT_4 i n comple mentary PWM mode, TCNT_3 has t he timer dead t ime register ( TDDR) val ue, and TCNT_ 4 is set to H'0 000[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 637 of 982 REJ09B0023-0400 buffer register for TGRA_ 3. At the same time, TGRC _4 functi ons as the buf fer register for TRGA_4, while the TCBR functions as the TCDR's buffer register. 18.7.14 Reset Sync PWM Mode Buffer Oper ation and Compare Matc h Flag When settin[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 638 of 982 REJ09B0023-0400 18.7.15 Overflow Flags in Reset Sync PWM Mode When set to reset sync PWM mode, TCNT_3 an d TCNT_4 start counting when the CST3 bit of TSTR is set to 1. At this p oint, TCNT_4's c ount clock source and c ount edge obey the TC R_3 setting. In[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 639 of 982 REJ09B0023-0400 Counter clear signal TCNT TCNT input clock P φ H'FFFF H'0000 TGF TCFV Disabled Figure 18.83 Conflict between Overf low and Co un ter Clearing 18.7.17 Conflict between TCNT Write and Overflow/Underflow If there is an up-count or dow n[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 640 of 982 REJ09B0023-0400 18.7.18 Cautions on Transition fr om Normal Operati on or PWM Mode 1 to Reset-Synchron ous PWM Mode When making a transitio n from chan nel 3 or 4 n ormal operation or PWM mo de 1 to reset - synchronous PWM mode , if th e counter is halted with [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 641 of 982 REJ09B0023-0400 18.8 MTU Output Pin Initialization 18.8.1 Operating Modes The MTU has t he followin g six operat ing modes. Waveform o utput is pos sible in all of these modes. • Normal mode (channels 0 to 4) • PWM mode 1 (channels 0 to 4) • PWM mode 2 ([...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 642 of 982 REJ09B0023-0400 18.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc. If an erro r occurs d uring MT U operatio n, MTU o utput shoul d be cut by the system. C utoff is performed by switchi ng the pi n output to por t output with th e PFC an[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 643 of 982 REJ09B0023-0400 18.8.4 Overview of Initi alization P rocedures and Mode Transit ions in Case of Error during Operation, Etc. • When making a transit ion to a mode (Norm al, PWM1, P WM2, PCM ) in whic h the pi n output level is selected by the timer I/O contr[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 644 of 982 REJ09B0023-0400 (1) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Nor mal M ode Figure 18.8 5 sh ows an explanator y diagram of the case where an error occurs in normal mode and operation is restarted in normal mode aft[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 645 of 982 REJ09B0023-0400 (2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 18.8 6 sh ows an explanator y diagram of the case where an error occurs in normal mode and operation i s restarte d in PWM mo de 1 aft[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 646 of 982 REJ09B0023-0400 (3) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2 Figure 18.8 7 sh ows an explanator y diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after r[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 647 of 982 REJ09B0023-0400 (4) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in P hase Counti ng Mode Figure 18.8 8 sh ows an explanator y diagram of the case where an error occurs in normal mode and operation is restarted in phase [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 648 of 982 REJ09B0023-0400 (5) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Complementary P WM Mode Figure 18.8 9 sh ows an explanator y diagram of the case where an error occurs in normal mode and operation is restarted i n comp[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 649 of 982 REJ09B0023-0400 (6) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Reset-S ynchronous PW M Mode Figure 18.9 0 sh ows an explanator y diagram of the case where an error occurs in normal mode and operation is restarted in[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 650 of 982 REJ09B0023-0400 (7) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Nor mal M ode Figure 18.91 sh ows an explanatory d iagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 651 of 982 REJ09B0023-0400 (8) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1 Figure 18.92 sh ows an explanatory d iagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mod e 1 after re[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 652 of 982 REJ09B0023-0400 (9) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2 Figure 18.93 sh ows an explanatory d iagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mod e 2 after re-[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 653 of 982 REJ09B0023-0400 (10) Operation when Error Occ urs during PWM Mode 1 Operation, and Operation is Restarted in P hase Counti ng Mode Figure 18.94 sh ows an explanatory d iagram of the case where an error occurs in PWM mode 1 and operation i s restarted in phase [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 654 of 982 REJ09B0023-0400 (11) Operation when Error Occ urs during PWM Mode 1 Operation, and Operation is Restarted in Complementary P WM Mode Figure 18.95 sh ows an explanatory d iagram of the case where an error occurs in PWM mode 1 and operation is restarted in co mp [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 655 of 982 REJ09B0023-0400 (12) Operation when Error Occ urs during PWM Mode 1 Operation, and Operation is Restarted in Reset-S ynchronous PW M Mode Figure 18.96 sh ows an explanatory d iagram of the case where an error occurs in PWM mode 1 and operation is r estar ted i[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 656 of 982 REJ09B0023-0400 (13) Operation when Error Occ urs during PWM Mode 2 Operation, and Operation is Restarted in Nor mal M ode Figure 18.97 sh ows an explanatory d iagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode afte[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 657 of 982 REJ09B0023-0400 (14) Operation when Error Occ urs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1 Figure 18.98 sh ows an explanatory d iagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mod e 1 after [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 658 of 982 REJ09B0023-0400 (15) Operation when Error Occ urs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2 Figure 18.99 sh ows an explanatory d iagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mod e 2 after r[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 659 of 982 REJ09B0023-0400 (16) Operation when Error Occ urs during PWM Mode 2 Operation, and Operation is Restarted in P hase Counti ng Mode Figure 18.100 show s an explanatory d iagram of the case where an error occurs in PWM mode 2 and operation i s restarted in phase[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 660 of 982 REJ09B0023-0400 (17) Operation when Error Oc c urs during Phase Counting Mode Operati on, and Operation is Restarted i n Normal Mo de Figure 18.101 show s an explanatory d iagram of the case where an error oc curs in phase counting mode and oper ation is rest a[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 661 of 982 REJ09B0023-0400 (18) Operation when Error Oc c urs during Phase Counting Mode Operati on, and Operation is Restarted in PW M Mode 1 Figure 18.102 show s an explanatory di ag ram of th e case where an error oc cu rs in phase counting mode and ope ration is rest[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 662 of 982 REJ09B0023-0400 (19) Operation when Error Oc c urs during Phase Counting Mode Operati on, and Operation is Restarted in PW M Mode 2 Figure 18.103 show s an explanatory d iagram of the case where an error oc curs in phase counting mode and ope ration is restarte[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 663 of 982 REJ09B0023-0400 (20) Operation when Error Oc c urs during Phase Counting Mode Operati on, and Operation is Restarted in Ph ase Counting Mode Figure 18.104 show s an explanatory di ag ram of th e case where an error oc cu rs in phase counting mode and oper atio[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 664 of 982 REJ09B0023-0400 (21) Operation when Error Occ urs during Complementar y PWM Mode Opera ti o n, an d Operation is Restarted in Normal Mode Figure 18.105 show s an explanatory d iagram of the case where an error occurs in complementary PWM mode an d operatio n is[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 665 of 982 REJ09B0023-0400 (22) Operation when Error Occ urs during Complementar y PWM Mode Opera ti o n, an d Operation is Restar ted in PWM Mode 1 Figure 18.106 show s an explanatory d iagram of the case where an error occurs in complementary PWM mode an d operati on i[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 666 of 982 REJ09B0023-0400 (23) Operation when Error Occ urs during Complementar y PWM Mode Opera ti o n, an d Operation is Restarted in Complementary PWM Mode Figure 18.107 show s an explanatory d iagram of the case where an error occurs in complementary PWM mode an d op[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 667 of 982 REJ09B0023-0400 (24) Operation when Error Occ urs during Complementar y PWM Mode Opera ti o n, an d Operation is Restarted in Complementary PWM Mode Figure 18.108 show s an explanatory d iagram of the case where an error occurs in complementary PWM mode an d o[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 668 of 982 REJ09B0023-0400 (25) Operation when Error Occ urs during Complementar y PWM Mode Opera ti o n, an d Operation is Restarted in Reset-S ynchronous PWM Mode Figure 18.109 show s an explanatory d iagram of the case where an error occurs in complementary PWM mode an[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 669 of 982 REJ09B0023-0400 (26) Operation when Error Oc c urs during Reset-Synchr onous PWM Mode Oper ation, and Operation is Restarted in Normal Mode Figure 18.110 show s an explanatory d iagram of the case where an error occurs in reset- synchronous PWM mod e an d oper[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 670 of 982 REJ09B0023-0400 (27) Operation when Error Oc c urs during Reset-Synchron ous PWM Mode Oper ation, and Operation is Restar ted in PWM Mode 1 Figure 18.111 show s an explanatory d iagram of the case where an error occurs in reset- synchronous PWM mode and op erat[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 671 of 982 REJ09B0023-0400 (28) Operation when Error Oc c urs during Reset-Synchr onous PWM Mode Oper ation, and Operation is Restarted in Complementary PWM Mode Figure 18.112 show s an explanatory d iagram of the case where an error occurs in reset- synchronous PWM mode[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 672 of 982 REJ09B0023-0400 (29) Operation when Error Oc c urs during Reset-Synchron ous PWM Mode Oper ation, and Operation is Restarted in Reset-S ynchronous PWM Mode Figure 18.113 show s an explanatory d iagram of the case where an error occurs in reset- synchronous PWM [...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 673 of 982 REJ09B0023-0400 18.9 Port Output Enable (POE) The port output enable (POE) can be used to es tablish a high-impedance state for high-cu rrent pins, by cha nging t he POE0 to POE3 pin i nput, depe nding on the out put stat us of the hi gh-curre nt pins (TIOC 3B[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 674 of 982 REJ09B0023-0400 The POE has input-level detectio n circuitry and outp ut-level detecti on circuit ry, as shown i n the block diagram of fig u re 18 .1 1 4. TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D POE3 POE2 POE1 POE0 Output level detection circuit Output level[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 675 of 982 REJ09B0023-0400 18.9.2 Pin Configuration Table 18.44 Pin Configuration Name Abbreviation I/O Description Port output enable input pins POE0 to POE3 Input Input request signals to make high- current pins high-impedance state Table 18.45 s hows out put-level com[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 676 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 15 POE3F 0 R/(W) * POE3 Flag This flag indicates that a high impedance req uest has been input to the POE3 pin [Clear condition] • By writing 0 to POE3F after reading a POE3F = 1 [Set condition] • W[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 677 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 11 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 PIE 0 R/W Port Interrupt Enable This bit enables/disables interrupt requ ests when any of the POE0F t[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 678 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 3 2 POE1M1 POE1M0 0 0 R/W R/W POE1 mode 1, 0 These bits select the input mode of the POE1 pin. 00: Accept request on falling edge of POE1 input 01: Accept request when POE1 input has been sampled for 16[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 679 of 982 REJ09B0023-0400 Output Level Contr ol/Statu s Register (O CSR): OCSR is a 16-bit reada ble /writable register that controls t he enable/ disable of both out put le vel co mparison and inte rrupts, and indicates status. If the OSF bit is set to 1, the high curr[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 680 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 9 OCE 0 R/W Output Level Compare Enable This bit enables the start of output level comparisons. When setting this bit to 1, pay attention to the output pin combinations shown in ta ble 18.43, Mode Trans[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 681 of 982 REJ09B0023-0400 18.9.4 Operation Input Level Detection Operati on: If the in put condit ions set by t he ICSR1 occur on any of the POE0 to POE3 pins, all high-current pins be come high-imp e dance state. Howeve r, o nl y whe n the general inp ut/outp ut functi[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 682 of 982 REJ09B0023-0400 2. Low-Level Detection Figure 18.116 shows the low-lev e l d etection operation. Sixteen continuous lo w levels are sampled wit h the samplin g clock establi shed by the ICSR1. If even one high level is det ected during this interval, the low le[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4. 00 Sep. 14, 2005 Page 683 of 982 REJ09B0023-0400 Release from High-Impedance S tate: High-c urrent pi ns that have e ntered hi gh-impeda nce state due to input-level de tection can be released either by returning them to their initial state with a power-on reset, or by clearing all of th e bi[...]

Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 684 of 982 REJ09B0023-0400[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 685 of 982 REJ09B0023-0400 Section 19 Serial Communi cation Interface with FIFO (SCIF) 19.1 Overview This LSI has a three-channel serial communication interface with FIFO (SCIF) that supports both asynchronous and clock synchronous serial co mmuni cation. It al[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 686 of 982 REJ09B0023-0400 • Internal or external tran smit/receive clock source: From either ba ud rate generator (internal) or SCK pin (exter nal) • Four types of interrupts: Tr ansmit-FIFO-data-empty, break , receive-FIFO-data-full, and receive-error inte[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 687 of 982 REJ09B0023-0400 Module data bus SCFRDR (16 stage) SCRSR RxD TxD SCK CTS RTS SCFTDR (16 stage) SCTSR SCSMR SCLSR SCFDR SCFCR SCFSR SCBRRn Parity generation Parity check Transmission/ reception control Baud rate generator Clock External clock P φ P φ[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 688 of 982 REJ09B0023-0400 19.2 Pin Configuration The SCIF has the serial pins summarized in ta ble 19.1. Table 19.1 SCIF Pins Channel Pin Name A bbreviation I/O Function Serial clock pin SCK0 I/O Clock I/O Receive data pin RxD0 Input Receive data input Transmit[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 689 of 982 REJ09B0023-0400 19.3 Register Description The SCIF has the following regist ers. These registers specify th e data format and bit rate, and control the transmitter and receiver sections. • Receive FIFO data re gister_0 (SCFRDR_0) • Transmit FIFO [...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 690 of 982 REJ09B0023-0400 19.3.1 Receive Shift Register (SCRSR) The receive shift register (SCRSR) receives serial data. Data input at the RxD pin is l oaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byt[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 691 of 982 REJ09B0023-0400 19.3.4 Transmit FIFO Data Register (SCFTDR) The transmit FIFO data register (SCFTDR) i s a 16 -byte FIFO register that stores data for serial transmission. When t he SCIF detects that the tran smit shift re gister (SC TSR) is empt y, [...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 692 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 6 CHR 0 R/W Character Length Selects 7-bit or 8-bit data in asynchronous mode. In the synchronous mode, the data length is alway s eight bits, regardless of the CHR setting. 0: 8-bit data 1: 7[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 693 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 4 O/ E 0 R/W Parity mode Selects even or odd parity when par ity bits are added and checked. The O/ E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 694 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1, 0 Select the internal clock source of the on-chi p baud rate gene[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 695 of 982 REJ09B0023-0400 19.3.6 Serial Control Re gister (SC SCR) The serial control register (SCS CR) ope rates the SCIF transmit ter/receiver, ena bles/disables interrupt requests, and selects the transmit/recei v e clock source. The CPU can always read and[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 696 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 6 RIE 0 R/W Receive Interrupt Enabl e Enables or disables the receive-data-fu ll (RXI) interrupts requested when the RDF flag or DR flag in serial status register (SCFSR ) is set to1, receive-[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 697 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 4 RE 0 R/W Receive Enable Enables or disables the SCIF serial receiver. 0: Receiver disabled * 1 1: Receiver enabled * 2 Notes: 1. Clearing RE to 0 does not affect the receive flags (DR, ER, [...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 698 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1 0 CKE1 CKE0 0 0 R/W R/W Clock Enable 1, 0 Select the SCIF clock source and enab le or disable clock outpu[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 699 of 982 REJ09B0023-0400 19.3.7 Serial Status Register (SCF SR ) The serial status register (SCF SR) is a 16-bit re gist er. The uppe r 8 bits indicate the num ber of receives errors in the SCFRDR data, an d the lower 8 bits indicate the status flag indicatin[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 700 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 7 ER 0 R/(W) * Receiv e Error Indicates the occurrence of a framing error, or of a parity error when receiving data that includes parity. * 1 0: Receiving is in progress or has en ded normally[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 701 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 6 TEND 0 R/(W) * Transmit End Indicates that when the last bit of a serial character was transmitted, SCFTDR did not contain valid data, so transmission has ended. 0: Transmission is in progr[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 702 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 5 TDFE 0 R/(W) * Transmit FIFO Data Empty Indicates that data has been transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the quantity of data in[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 703 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 4 BRK 0 R/(W) * Break Detection Indicates that a break signal has been detect ed in receive data. 0: No break signal received [Clearing conditions] • BRK is cleared to 0 when the chip is a [...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 704 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 2 PER 0 R Parity Error Indicates a parity error in the data read from the next receive FIFO data register (SCFRDR) in asynchronous mode. 0: No receive parity error occurred in the next data re[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 705 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 1 RDF 0 R/(W) * Receive FIFO Data Full Indicates that receive data has been transfer red to the receive FIFO data register (SCFRDR), and the quantity of data in SCF RDR has become more than t[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 706 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 0 DR 0 R/(W) * Receive Data Ready Indicates that the quantity of data in the receive FIFO data register (SCFRDR) is less than the specified receive trigger number, and that the next dat a has [...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 707 of 982 REJ09B0023-0400 19.3.8 Bit Rate Register (SCB RR) The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in th e serial mode register (SC SMR), determi nes the se[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 708 of 982 REJ09B0023-0400 Table 19.3 lists examples of SCBRR settings in as ynchronous mode, and table 19.4 lists examp les of SCBRR settings in synchron ou s mode. Table 19.3 Bit Rates and SCBRR Settings in As ynchronous Mode P φ (MHz) 5 6 6.144 Bit Rate (bit[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 709 of 982 REJ09B0023-0400 P φ (MHz) 10 12 12.28 8 14.7456 Bit Rate (bits/s) n N Error ( % ) n N Error ( % ) n N Error ( % ) n N Error ( % ) 110 2 177 –0.25 2 212 0.03 2 217 0.08 3 64 0.70 150 2 129 0.16 2 155 0.16 2 159 0.00 2 191 0.00 300 2 64 0.16 2 77 0.[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 710 of 982 REJ09B0023-0400 P φ (MHz) 24.576 28.7 30 33 Bit Rate (bits/s) n N Error ( % ) n N Error ( % ) n N Error ( % ) n N Error ( % ) 110 3 108 0.08 3 126 0.31 3 132 0.13 3 145 0.33 150 3 79 0.00 3 92 0.46 3 97 –0.35 3 106 0.39 300 2 159 0.00 2 186 –0.08[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 711 of 982 REJ09B0023-0400 Table 19.4 Bit Rates and SCBRR Settings in S ynchronous Mode P φ (MHz) 5 8 16 28.7 30 33 Bit Rate (bits/s) n N n N n N n N n N n N 110 — — — — — — — — — — — — 250 3 77 3 124 3 249 — — — — — — 500 3[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 712 of 982 REJ09B0023-0400 Table 19.5 in dicates the maxi mum bit rat es in asynchron ous mode whe n the baud rat e generat or is used. Tables 19.6 an d 19.7 list the maximum rates for external clo ck input. Table 19.5 Maximum Bit Rates for V ariou s Frequenc ie[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 713 of 982 REJ09B0023-0400 Table 19.6 Maximum Bit Rates wi th External Clock Input (Async hronous Mode) P φ (MHz) External Input Clock (MH z) Maximum Bit Rate (bits/s) 5 1.2500 78125 4.9152 1.2288 76800 8 2.0000 125000 9.8304 2.4576 153600 12 3.0000 187500 14.[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 714 of 982 REJ09B0023-0400 19.3.9 FIFO Control Regist er (SCFCR) The FIFO control register (SCFCR) resets the quantity of data in the transmit and receive FIFO registers, sets the trigger data qu antity, and contains an en able bit for loop-back testing. SCFCR c[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 715 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description Receive FIFO Data Trigger Set the quantity of receive data which sets the receiv e data full (RDF) flag in the serial status register (SCFSR). The RDF flag is set when the quantity of receive[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 716 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 2 TFRST 0 R/W Transmit FIFO Data Register Reset Disables the transmit data in the transmit FIFO data register and resets the data to the empty state. 0: Reset operation disabl ed * 1: Reset op[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 717 of 982 REJ09B0023-0400 19.3.10 FIFO Data Count R egister (SCFDR) SCFDR is a 16-bit register which indicates the qu antity of data stored in the transmit FIFO data register (SCFT DR) and t he receive F IFO data regi ster (SCFR DR). It indi cates the quantity[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 718 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 15 to 8 — All 0 R Reserved These bits are always read as 0. The write value shou ld always be 0. 7 RTSIO 0 R/W RTS Port Input/Output Indicates the input or output of RTS pin. When RTS pin is[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 719 of 982 REJ09B0023-0400 Bit Bit Name Initial value R/W Description 3 SCKIO 0 R/W SCK Port Input/Output Indicates the input or output of SCK pin. When SCK pin is used as port outputting the SCKDT bit, the CKE1, CKE0 bit of serial control regist er (SCSCR) sho[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 720 of 982 REJ09B0023-0400 19.3.12 Line Status Register (SCLSR) The CPU can alway s read or write to SCLSR, bu t cannot writ e 1 to the OR ER fla g. This flag can be cleared to 0 only if i t has first been read (a fter being set t o 1). SCL SR is init ialized to[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 721 of 982 REJ09B0023-0400 19.4 Operation 19.4.1 Overview For serial communication, th e SCIF has an asynchronous mode in which characters are synchronized ind ividu ally, and a synchronous mode in which communication is synchron ized with clock pulses. The SCI[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 722 of 982 REJ09B0023-0400 Table 19.8 SCSMR Settings and SCIF Communicati on Formats SCSMR Settings SCIF Communication Format Bit 7 C/ A Bit 6 CHR Bit 5 PE Bit 3 STOP Mode Data Length Pari ty Bit Stop Bit Length 0 0 0 0 8 bits Not set 1 bit 1 2 bits 1 0 Set 1 bi[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 723 of 982 REJ09B0023-0400 19.4.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received ch aracter begins with a start bit an d ends with a stop bit. Serial comm uni cation is sync hronized one c haracter at a time. The transmitting [...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 724 of 982 REJ09B0023-0400 Transmit/Receive Formats: Table 19.10 lis ts the 8 comm unicati on format s that can be selected in asynchro nous mode. T he format is select ed by sett ings in the se rial mode re gister (SCS MR). Table 19.10 Serial Communication Form[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 725 of 982 REJ09B0023-0400 Transmitting and Receiving Data: • SCIF Initialization (Asynchronous Mode) Before transmitting or receivi ng, clear the TE and RE bits to 0 in the serial cont rol register (SCSCR), then initialize the SCIF as follo ws. When ch angin[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 726 of 982 REJ09B0023-0400 Figure 19.3 shows a sample flowchart for initializing th e SCIF. Start of initialization Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 Set CKE1 and CKE0 bits in SCSCR (leaving TE, RE, TIE, and RIE bits clear[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 727 of 982 REJ09B0023-0400 • Transmitting Serial Da ta (Asynchronous Mode) Figure 19.4 s hows a sample flow chart fo r serial transmission. Use the following procedure for serial data transm ission af ter enab ling the SCI F for tran sm ission. Start of trans[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 728 of 982 REJ09B0023-0400 In serial trans mission, the SCIF operat es as descri bed below . 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmit[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 729 of 982 REJ09B0023-0400 Figure 19.5 s hows an exam ple of the operation for transmission. 1 0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1 1 TDFE TEND Serial data Start bit Data Parity bit Stop bit Start bit Idle state (mark state) Data Parity bit Stop bit TXI interrupt [...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 730 of 982 REJ09B0023-0400 • Receiving Serial Data (Asynchronous Mode) Figures 19.7 and 19.8 show a sample flowchart for ser ial reception. Use the following procedure for serial data r eception after enabling th e SCIF for reception. Start of reception Read E[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 731 of 982 REJ09B0023-0400 Error handling Receive error handling ER = 1? BRK = 1? Break handling DR = 1? Read receive data in SCFRDR Clear DR, ER, BRK flags in SCFSR, and ORER flag in SCLSR, to 0 End Yes Yes Yes No Overrun error handling ORER = 1? Yes No No No [...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 732 of 982 REJ09B0023-0400 In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmissio n line, and if a 0 start bit is detected, performs internal synchronization an d starts reception. 2. The received data is stored in SCRSR [...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 733 of 982 REJ09B0023-0400 1 0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0/1 0 RDF FER Serial data Start bit Data Parity bit Stop bit Start bit Data Parity bit Stop bit RXI interrupt request One frame Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt hand[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 734 of 982 REJ09B0023-0400 Figure 19.11 show s th e general format in synchro nou s serial communication . Don't care Don’t care One unit of transfer data (character or frame) Bit 0 Serial data Synchronization clock Bit 1 Bit 3 Bit 4 Bit 5 LSB MSB Bit 2 B[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 735 of 982 REJ09B0023-0400 Figure 19.12 shows a sample flowch art for initializing the SCIF. Start of initialization Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 to clear the FIFO buffer After reading BRK, DR, and ER flags in SCFSR,[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 736 of 982 REJ09B0023-0400 • Transmitting Serial Data (Synchron ous Mode) Figure 19.13 shows a sample flowch art for transmitting serial data. Use the follow ing proced ure for serial data transmissi on after e nabling the SCIF for t ransmission. Start of tran[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 737 of 982 REJ09B0023-0400 In serial trans mission, the SCIF operat es as descri bed below . 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmi[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 738 of 982 REJ09B0023-0400 • Receiving Serial Data (Synchronous Mode) Figure 19.15 shows a sa mple flowchart for receiving seri al data. When switching from asynchronous mode to synchronou s mod e without SCIF initialization, make sure that ORER, PER, and FER [...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 739 of 982 REJ09B0023-0400 Error handling Clear ORER flag in SCLSR to 0 End Overrun error handling ORER = 1? Yes No Figure 19.16 Sample Flowc hart for Receiving Serial Data (2)[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 740 of 982 REJ09B0023-0400 In serial reception, the SCIF operates as described below. 1. The SCIF synchronizes with serial clock input or output and starts th e reception. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving t [...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 741 of 982 REJ09B0023-0400 • Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode) Figure 19.18 shows a samp le flowchart for transm itting and receiving serial data simultaneously. Use the following procedure for the simultaneous transmiss[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 742 of 982 REJ09B0023-0400 19.5 SCIF Interrupts and DMAC The SCIF has four i nterrupt sources: transmi t-FIFO-data-empty (TXI), re ceive-error (ERI), receive-data-full (RXI), and break (BRI). Table 19.11 s hows the inte rrupt sources a nd their or der of priorit[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 743 of 982 REJ09B0023-0400 Table 19.11 SCIF Interrupt Sources Interrupt Source Description DMAC Activation Priority on Reset Release ERI Interrupt initiated by receive error (ER) Not possible High RXI Interrupt initiated by rece ive data FIFO full (RDF) or data[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 744 of 982 REJ09B0023-0400 The number of receive data bytes in SCFR DR can be found from the l owe r 8 bits of the FIFO data count re gister (SC FDR). 3. Break Detection and Processing Break signals c an be detected by reading t he RxD pi n directly whe n a fram[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4. 00 Sep. 14, 2005 Page 745 of 982 REJ09B0023-0400 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 1314 15 0 1 2 3 4 5 D0 D1 16 clocks 8 clocks Base clock Receive data (RxD) Start bit –7.5 clocks +7.5 clocks Synchronization sampling timing Data sampling timing Fig[...]

Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 4.00 Sep. 14, 2005 Page 746 of 982 REJ09B0023-0400 6. When Using the DMAC  Using an E xternal Cl ock in C hock Sync hronous M ode: When using an external cloc k as the synchr onization cl ock, after SC FTDR is updat ed by the DMAC, an external clock shou ld be input af ter at least [...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 747 of 982 REJ09B0023-0400 Section 20 USB Function Module 20.1 Features • Incorporates UDC (USB device co ntroller) con forming to t he USB sta ndard Automatic pr ocessing of USB protoc ol Automatic pr ocessing of US B standard c ommands for en dpoint 0 (s ome comman ds and class/vendor[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 748 of 982 REJ09B0023-0400 • Powe r mo de: Self-powered , bus-powered 20.1.1 Block Diagram Status and control registers Internal peripheral bus UDC: USB device controller FIFO (288 bytes) Interrupt requests DMA transfer requests Clock (48 MHz) UDC USB function module To transceiver Figur[...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 749 of 982 REJ09B0023-0400 In on-chip tran sceiver b ypa ss mode (the XVE R OFF bit of the USB XVERCR register is 1) , a Philips PDIU SBP11 Seri es transceiver or compatible product can be connected (w hen using a compatible produ c t, carry ou t evaluation and investig ation with the man[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 750 of 982 REJ09B0023-0400 20.3.1 USB Interrupt Fl ag Registe r 0 (USBIF R0) Together with US B interrupt flag registers 1 (USBIFR1) and 2 (USBIFR 2), USBIFR0 indicates interrupt status information req uired by the application. When an interrupt occurs, the corresponding bit is set to 1 an[...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 751 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 2 EP0oTS 0 R/W EP0o Receive Complete This bit is set to 1 when endpoint 0 receives data from the host normally, stores the data in the FIFO buffer, and returns an ACK handshake to the host. 1 EP0iTR 0 R/W EP0i Transfer [...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 752 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 2 EP3TR 0 R/W EP3 Transfer Request This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 3 is received from the host. A NACK handshake is returned to the host until data is w[...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 753 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 1 CFGV 0 R Configuration Value Status bit for monitoring the c onfiguration value. This is a status bit and cannot be cleared. 0 SETC 0 R/W SET_CONFIGURATION Request Detection This bit is set to 1 wh en the SET_CONFIGUR[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 754 of 982 REJ09B0023-0400 20.3.5 USB Interrupt Sel ect Register 1 (USBISR1) USBISR1 selects the vector number s of the interrupt requests i ndicated in USB interrupt flag register 1 (USBIFR1). If the USB issues an interr upt request to the INTC when the c orresponding bit in USBISR1 is cl[...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 755 of 982 REJ09B0023-0400 20.3.7 USB Interrupt Enable Regi ster 1 (U SB IE R1 ) USBIER1 enables th e interrupt requests indicated in USB interru pt flag register 1 (U SBIFR1). When an interrupt flag is set while th e correspo nding bit in USBIER1 is set to 1, an in terrup t request is se[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 756 of 982 REJ09B0023-0400 20.3.9 USBEP0i Data Register (U SB E PD R0i ) USBEPDR0i is an 8-byte transmit FIFO buffer for en dpoint 0, holding one packet of tran smit data for control IN. Transmit data is fixed by writing one packet of data and settin g the EP0iPKTE bit in the trigger regis[...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 757 of 982 REJ09B0023-0400 20.3.11 USBEP0s Data Register (USBE P D R0s ) USBEPDR0 s is an 8-byte FIFO buffer specifically for e ndpoint 0 setup command reception and stores an 8-byte command dat a that is sent in the set up stage. USBEPDR0s r eceives only commands requiring pro cessing on[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 758 of 982 REJ09B0023-0400 20.3.13 USBEP2 Da ta Regi ster ( US BEPDR2) USBEPDR2 is a 128-b yte transmit FIFO buffe r for endpoint 2. USBEP DR2 has a dual-buffe r configuration, and has a capa city of twice the maxi mum packet size. When tr ansmit data is written to this FIFO buffer and the[...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 759 of 982 REJ09B0023-0400 20.3.16 USBEP1 Rece ive Data Size Register (USBEPSZ1) USBEPSZ1 indicates, in bytes, the amount of da ta received from the host by endpoint 1. The endpoint 1 FIFO buffer has a dual-FIFO configura tion. The receive data si ze indicated by this register refers to t[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 760 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 2 EP0sRDFN 0 W EP0s Read Co mplete Write 1 to this bit after EP0s command FIFO data has been read. Writing 1 to this bit enables transmission/reception of data in the followin g data stage. A NACK handshake is returned i[...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 761 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 4 EP2DE 0 R EP2 Data Pres ent This bit is set when the endpoint 2 FIFO buffer contains valid data 3 to 1  All 0 R Reserved The write value should always be 0. 0 EP0iDE 0 R EP0i Data Present This bit is set when the e[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 762 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 0 EP0iCLR 0 W EP0i Clear When 1 is written to this bit, the endpoint 0 transmit FIFO buffer is initialized. 20.3.20 USBDMA Transfer Setti ng Regi ster (USBDM AR) USBDMAR en ables DMA t ransfer bet ween the end point 1 a [...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 763 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 0 EP1DMAE 0 R/W Endpoint 1 DMA Transfer Enable When this bit is set, DMA transfer is enabled from the endpoint 1 receive FIFO buffer to memory. If there is at least one byte of receive data in the FIFO buffer, a transfe[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 764 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 2 EP2STL 0 R/W EP2 Stall When this bit is set to 1, endpoint 2 is placed in the stall state. 1 EP1STL 0 R/W EP1 Stall When this bit is set to 1, endpoint 1 is placed in the stall state. 0 EP0STL 0 R/W EP0 Stall When this[...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 765 of 982 REJ09B0023-0400 20.3.23 USB Bus Power Control Register (USBCTRL) This LSI can operate using a bu s po wer cont rol met h od . Fo r det ai l s of the bus po wer cont rol method, see section 20.9, US B Bus Power C ont r ol Meth o d. USBCTRL can be initialized to H ' 00 by a [...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 766 of 982 REJ09B0023-0400 20.4 Operation 20.4.1 Cable Connection Cable disconnected VBUS pin = 0 V UDC core reset USB cable connection USBIFR1/VBUS = 1 USB bus connection interrupt UDC core reset release Bus reset reception USBIFR0/BRST = 1 Bus reset interrupt Wait for setup command recep[...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 767 of 982 REJ09B0023-0400 Also, in appli cations that re quire connect ion detecti on regardle ss of D+ pul l-up contr ol, detectio n should be car ried out using IRQx or a genera l input p ort. For details, see sect ion 20.8, E xample of USB External Circuitry. 20.4.2 Cable Disconnectio[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 768 of 982 REJ09B0023-0400 20.4.3 Control Transfer Control tra nsfer consist s of three stage s: setup, data (not al ways include d), and stat us (figure 20.4). The data stage comprises a number of bus transactions. Operatio n flowcharts for each stage are shown below. Control IN Setup sta[...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 769 of 982 REJ09B0023-0400 Setup Stage: USB function Application SETUP token reception Receive 8-byte command data in EP0s To data stage Set setup command reception complete flag (USBIFR0/SETUP TS = 1) Automatic processing by this module Clear SETUP TS flag (USBIFR0/SETUP TS = 0) Clear EP[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 770 of 982 REJ09B0023-0400 Data Stage (Cont r ol-IN): The application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If th e resu lt of command data an alysis is that the data stage is in-tra nsfer, one packet of data to be[...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 771 of 982 REJ09B0023-0400 Data Stage (Cont r ol-OUT): The application first analyzes comm and data from the host in the setup stage, and determines the s ubsequent data stage di rection. If the result o f command data analysis is that the data stage is OUT-transfe r, the application wa i[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 772 of 982 REJ09B0023-0400 Status Stage (Control-I N): The cont rol-IN stat us stage start s with an OUT t oken from the host. The application receives 0-byte data from the host, a nd ends control transfer. USB function Application OUT token reception 0-byte reception from host End of cont[...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 773 of 982 REJ09B0023-0400 Status Stage (Control-O UT): The control-OUT status stage starts with an IN token from the host. Wh en an IN tok en is receiv ed at th e start of the status stage, there is not yet any data in the EP0iFIFO, and so an EP0i transfe r request interrupt is generated[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 774 of 982 REJ09B0023-0400 20.4.4 EP1 Bulk-OUT Transfer (Dual FIFOs) EP1 has two 64-byte FIFOs, but the user ca n perform data reception and receive data reads without being aware of this du al-FIFO configuration. When one FIFO is full after recep tion is co mpleted, the USBIFR0/ EP1 FULL [...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 775 of 982 REJ09B0023-0400 USB function Application OUT token reception Data reception from host Set EP1 FIFO full status (USBIFR0/EP1 FULL = 1) Clear EP1 FIFO full status (USBIFR0/EP1 FULL = 0) Read USBEP1 receive data size register (USBEPSZ1) Read data from USBEP1 data register (USBEPDR[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 776 of 982 REJ09B0023-0400 20.4.5 EP2 Bulk-IN Transfer (Dual FIFOs) EP2 has two 64-byte FIFOs, but the user can perform data transmissi on and tra nsmit data w rites without being aware of this du al-FIFO configura tion. However, one data wri t e is per fo r med f or one FIFO. Fo r example[...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 777 of 982 REJ09B0023-0400 USB function Application IN token reception Data transmission to host Clear EP2 transfer request flag (USBIFR0/EP2 TR = 0) Enable EP2 FIFO empty interrupt (USBIER0/EP2 EMPTY = 1) USBIER0/EP2 EMPTY interrupt Write one packet of data to USBEP2 data register (USBEP[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 778 of 982 REJ09B0023-0400 20.4.6 EP3 Interrupt-IN Transfer USB function Application IN token reception Data transmission to host Set EP3 transmission complete flag (USBIFR1/EP3 TS = 1) Write data to USBEP3 data register (USBEPDR3) Write 1 to EP3 packet enable bit (USBTRG/EP3 PKTE = 1) Cle[...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 779 of 982 REJ09B0023-0400 20.5 Processing of USB Standard Commands and Class/Vendor Commands 20.5.1 Processing of Commands Transmitted by Control Tr ansfer A command transmitted from the host by control transfer may require decoding and ex ecution of command proc essing on the a pplicati[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 780 of 982 REJ09B0023-0400 20.6 Stall Operations This section de scribes stall operations i n the USB function module. T here are two cases in whic h the USB function modu le stall function is used: • When the applicati on forcibly sta lls an endpoint for some reason • When a stall is [...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 781 of 982 REJ09B0023-0400 (1) Transition from normal operation to stall (1-1) Transaction request USB Reference (1-2) STALL handshake Stall To (2-1) or (3-1) Normal status restored (1-3) (2) When Clear Feature is sent after USBEPSTL is cleared (2-1) STALL handshake Transaction request (2[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 782 of 982 REJ09B0023-0400 20.6.2 Automatic Stall by USB F unction Mod ule When a stall setting is mad e with th e Set Featur e command, or in t he event of a USB specification violation, the USB function modu le automatically sets the internal status b it for the relevant endpoint without[...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 783 of 982 REJ09B0023-0400 (1) Transition from normal operation to stall (1-1) (2) When transaction is performed when internal status bit is set, and Clear Feature is sent (2-1) STALL handshake Transaction request STALL handshake (2-2) Clear Feature command (3) When Clear Feature is sent [...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 784 of 982 REJ09B0023-0400 20.7 DMA Transfer This module al lows DM AC transfe r for en dpoints 1 a nd 2, e xcluding tra nsfer of word an d longword. If endpoint 1 contains at least on e byte of va lid receive data, a DMA transfer request is issued to endpoint 1. If there is n o valid dat [...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 785 of 982 REJ09B0023-0400 20.7.2 DMA Transfe r for Endpoi nt 2 When the transmi t t ed data fo r EP2 is tra nsfe rred by DMA when t he data on one side of FIFO (64 bytes) becomes full an equiv alent processing of writing 1 to the USBTRG/PKTE bit is automatically performed in the modu le.[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 786 of 982 REJ09B0023-0400 20.8 Example of USB Exter nal Circuitry USB Transceiver: When a n on-chip t ransceiver is not used, a USB transceiver IC (such as a PDIUSBP11) must be connected extern ally. The USB transceiver manufactu r er should be consulted concerning the recommende d circui[...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 787 of 982 REJ09B0023-0400 USB module General output port, etc. IC that allows voltage application when the system (LSI) power is off. IC that allows voltage application when the system (LSI) power is off. This LSI USB connector USB cable VBUS VBUS GND D+ D+ D- D- 5 V Note: Operation cann[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 788 of 982 REJ09B0023-0400 This LSI USB module General output port, etc. IC that allows voltage application when the system (LSI) power is off. IC that allows voltage application when the system (LSI) power is off. USB connector USB cable VBUS VBUS TXENL TXDMNS TXDPLS XVDATA DPLS GND DMNS [...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 789 of 982 REJ09B0023-0400 20.9 USB Bus Power Control Method 20.9.1 USB Bus Power Control Operation This LSI can operate usin g a USB b us po we r control meth od . The following describes notes on th e LSI using the USB bus power control method . Changing to High -Power Functi on: Acco r[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 790 of 982 REJ09B0023-0400 This LSI IRQ1 IRQ1_SUSPEND USBCTRL/ SUSPEND USBIFR2/ SUSPS USBIFR2/ AWAKE IRQ0_AWAKE IRQ0 0 S Q 1 0 1 USB suspend signal (internal signal) AWAKE signal (internal signal) IRQ1 interrupt IRQ0 interrupt Interrupt controller (INTC) S Q Figure 20.19 IRQ0 and IRQ1 Inte[...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 791 of 982 REJ09B0023-0400 Normal routine USIHP interrupt routine Power On Reset Set STBCR4/MSTP46 to 1 (exit USB module stop mode) Set USBIER2/SETC to 1 (Configuration set interrupt) Clear USBIER2/SETC Clear USBIFR2/SETC Confirm USBIFR2/CFGV=1 (confirm that a trasition to high-power func[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 792 of 982 REJ09B0023-0400 Normal routine IRQ1 interrupt routine Normal state Clear IRR0/IRQ1R of INTC Save SSR and SPC to memory Set STBCR/STBY SLEEP instruction Set SR/I[3:0] to the IRQ1 priority Clear IRR0/IRQ0R of INTC RTE instruction Clear USBIFR2/SUSPS and AWAKE (clear detection of U[...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 793 of 982 REJ09B0023-0400 Normal routine IRQ0 interrupt routine IRQ1interrupt routine Normal state or standby mode Clear IRR0/IRQ0R of INTC Clear IRR0/IRQ1R of INTC Clear USBIFR2/SUSPS and AWAKE Set SR/I[3:0] to the IRQ0 priority RTE instruction RTE instruction RTE instruction Restore SS[...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 794 of 982 REJ09B0023-0400 20.10 Notes on Usage 20.10.1 Receiving Setup Data Note that the following whe n 8-byte setup data is receive d by USBEPDR0s. 1. The USB must always receive the set up comma nd. Therefore, writing from the USB bus has priority over reading from the CPU. When th e [...]

Section 20 USB Function Module Rev. 4. 00 Sep. 14, 2005 Page 795 of 982 REJ09B0023-0400 20.10.4 Assigning Interrupt Source for EP0 Interrupt sources (b its 0 to 3) for EP0 that are assigned to USBIFR0 of this module must be assigned to t he same interr upt pin usi ng USBISR 0. 20.10.5 Clearing FIFO wh en Setting DMA Transfer Clearing the e ndpoint [...]

Section 20 USB Function Module Rev. 4.00 Sep. 14, 2005 Page 796 of 982 REJ09B0023-0400 TR interrupt routine TR interr upt routine CPU USB Clear TR flag, Write transmit data, and TRG/PKTE IN token Check NAK Set TR flag Host NAK IN token Check NAK Set TR flag (flag is set again) NAK IN token Data transmission ACK Figure 20.24 Timing for Se tting the [...]

Section 21 A/D Converter Rev. 4. 00 Sep. 14, 2005 Page 797 of 982 REJ09B0023-0400 Section 21 A/D Converter This LSI includes a 10-bit successive-approximation A/D con verter all owing selectio n of up t o eight analog i nput cha nnels. The A/D converter is composed of two independent modu les, A/D0 and A/D1. 21.1 Features A/D conve rter features ar[...]

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 798 of 982 REJ09B0023-0400 21.1.1 Block Diagram Figure 21.1 show s a bloc k diagram of t he A / D con vert er . AVcc and AVs s for both A/D modul es are common pins in the c hip. ADI0 interrupt signal ADCSR 0: ADDRA 0: ADDRB 0: ADDRC 0: ADDRD 0: ADCR: [Legend] A/D 0 control/status register A/D 0[...]

Section 21 A/D Converter Rev. 4. 00 Sep. 14, 2005 Page 799 of 982 REJ09B0023-0400 21.1.2 Input Pins Table 21.1 su mmarizes the A/D c onverter' s input pi ns. The eight analog i nput pins are divided i nto two grou ps: A/D0 ( AN0 to AN3 ), and A/ D1 (AN4 t o AN7). AV CC and AV SS are the power supply inputs for the analog circu its in the A/D c[...]

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 800 of 982 REJ09B0023-0400 21.1.3 Register Configuration The A/D converter's registers are su mmarized below. • A/D0 data regist er A (ADDR A0) • A/D0 data regist er B (ADDR B0) • A/D0 data regist er C (ADDR C0) • A/D0 data regist er D (ADDR D0) • A/D0 co ntrol/status register (AD[...]

Section 21 A/D Converter Rev. 4. 00 Sep. 14, 2005 Page 801 of 982 REJ09B0023-0400 Table 21.2 Analog Input Cha nnels and A/D Data Registers Analog Input Channel A/D Data Register Module AN0 ADDRA0 AN1 ADDRB0 AN2 ADDRC0 AN3 ADDRD0 A/D0 AN4 ADDRA1 AN5 ADDRB1 AN6 ADDRC1 AN7 ADDRD1 A/D1 21.2.2 A/D Control/St atus Registers (A DC SR0, ADCSR1) ADCSR is a [...]

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 802 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Desc ription 14 ADIE 0 R/W A/D Interrupt Enable Enables or disables the inte rrupt (ADI) requested at the end of A/D conversion. Set the ADIE bit while A/D conversion is not being made. 0: A/D end interrupt request (ADI) is disabled 1: A/[...]

Section 21 A/D Converter Rev. 4. 00 Sep. 14, 2005 Page 803 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Desc ription 10 to 8  All 0 R Reserve d These bits are always read as 0. The write value shou ld always be 0. 7 6 CKS1 CKS0 0 1 R/W R/W Clock Select Selects the A/D conversion time. Clear the ADST bit to 0 before changing the conversi[...]

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 804 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Desc ription 1 0 CH1 CH0 0 0 R/W R/W Channel Select These bits and the MULTI bi t select the analog input channels. Clear the ADST bit to 0 before changin g the channel selection. • In the case of ADCSR0 (A/D0) Single mode Multi mode or[...]

Section 21 A/D Converter Rev. 4. 00 Sep. 14, 2005 Page 805 of 982 REJ09B0023-0400 21.3 Operation The A/D converter operates by su ccessive approximations with 10 -bit resolution. It has three operating m odes: single mode, mult i mode, and sca n mode. 21.3.1 Single Mode Single mode should be select ed whe n only one A/D conve r si on on one ch anne[...]

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 806 of 982 REJ09B0023-0400 Channel 0 (AN0) operating ADIE ADST ADF Channel 1 (AN1) operating Channel 2 (AN2) operating Channel 3 (AN3) operating ADDRA ADDRB ADDRC ADDRD Waiting Waiting Waiting Waiting Waiting Waiting A/D conversion starts Set * Set * Set * Clear * Clear * A/D conversion result 1[...]

Section 21 A/D Converter Rev. 4. 00 Sep. 14, 2005 Page 807 of 982 REJ09B0023-0400 Typical operations when three cha nnels in A/D0 (AN0 to AN2) a re selected in multi mode are described next . Figure 21. 3 shows a tim ing diagram for this exam ple. 1. Multi mode is selected (MULTI = 1), channel group A/D0 is selected, analo g input channels AN0 to A[...]

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 808 of 982 REJ09B0023-0400 21.3.3 Scan Mode Scan mode is useful for monitor ing an alog inputs in a group of one or more ch annels. When the ADST bit in the A/D control/status register (ADCSR0 or ADCSR1) is set to 1 by software, A/D conversion starts on the first ch ann el in the group (A/D0 whe[...]

Section 21 A/D Converter Rev. 4. 00 Sep. 14, 2005 Page 809 of 982 REJ09B0023-0400 ADST ADF Channel 0 (AN0) operating Channel 1 (AN1) operating Channel 2 (AN2) operating Channel 3 (AN3) operating ADDRA0 ADDRB0 ADDRC0 ADDRD0 Waiting Waiting Waiting Waiting Waiting Waiting Waiting Waiting Waiting Transfer A/D conversion 1 A/D conversion 4 A/D conversi[...]

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 810 of 982 REJ09B0023-0400 21.3.5 A/D Converter Activatio n by MTU The A/D converter can be indep enden tly activated by an A/D conver sion request from the MTU or CSL. To activate the A/D converter by the MTU, set the A/D trigger enable bit (TRGE). After th is bit setting has bee n made, the AD[...]

Section 21 A/D Converter Rev. 4. 00 Sep. 14, 2005 Page 811 of 982 REJ09B0023-0400 P φ Write signal ADF ADCSR write cycle Input sampling timing t D : A/D conversion start delay t SPL : Input sampling time t CONV : A/D conversion time [Legend] Address ADCSR address t D t SPL t CONV Figure 21.5 A/D Conversion Timing Table 21.3 A/D Conversio n Time (S[...]

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 812 of 982 REJ09B0023-0400 21.4 Interrupt and DMAC Transfer Request The A/D converter generates an inter ru pt (ADI0 and ADI1) or DMAC activation sign al at the end of A/D con version. These req uests are enabl ed or disa bled by the A DIE bit or the DMASL bi t in ADCSR. When the DM AC is activa[...]

Section 21 A/D Converter Rev. 4. 00 Sep. 14, 2005 Page 813 of 982 REJ09B0023-0400 21.5 Definitions of A/D Conversion Accuracy The A/D converter compar es an analog value inpu t fro m an analog input channe l with its analog reference val ue and conve rts it to 10- bit digit al data. The a bsolute accurac y of this A/D conversio n is the deviati on [...]

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 814 of 982 REJ09B0023-0400 0F S 111 110 101 100 011 010 001 000 Analog input voltage (3) Quantization error (4) Nonlinearity error (2) Full-scale error Ideal A/D conversion characteristic Digital output FS: Full-scale voltage FS Analog input voltage Actual A/D convertion characteristic (1) Offse[...]

Section 21 A/D Converter Rev. 4. 00 Sep. 14, 2005 Page 815 of 982 REJ09B0023-0400 21.6 Usage Notes When using the A/D converter, note the following po in ts. 21.6.1 Setting Analog Input Voltage Permanent damage to the LSI may result if the following voltag e ranges are exceeded. 1. Analog input rang e : Dur ing A/D conversion, voltag es on the anal[...]

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 816 of 982 REJ09B0023-0400 21.6.4 Influences on Absolute Precision Adding capacitance results in coupling with GND, and therefor e noise in GND may adversely affect absolute precision . Be sure to make the connection t o an electrically stable GND such as AVss. Care is also required to insure th[...]

Section 21 A/D Converter Rev. 4. 00 Sep. 14, 2005 Page 817 of 982 REJ09B0023-0400 0.01 µ F 10 µ F AV CC AN0 to AN7 AV SS This LSI * 1 1. 100 Ω 0.1 µ F Note: Value are referene value. * 2 R in 2. R in : input impedance Figure 21.7 Example of Anal o g Inp ut P r otec tion Circuit AN0 to AN7 3 k Ω 20 pF to A/D converter Note: Value are referene[...]

Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 818 of 982 REJ09B0023-0400[...]

Section 22 Pin Function Controller (PFC) Rev. 4. 00 Sep. 14, 2005 Page 819 of 982 REJ09B0023-0400 Section 22 Pin Function Controller (PFC) The pin functi on control ler (PFC) i s composed of registers for selecting t he functio n of multiplexed pins and the input/output d irection. The pin function and input/o u tput direction can be selected for e[...]

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 820 of 982 REJ09B0023-0400 Port Port Functi on (Related Module) Other Function (Related Module) C PTC15 input/output (por t) STATUS1 output (CPG) PTC14 input/output (port) STATUS0 output (CPG) PTC13 input/o utput (port) ASEBRKAK output (CPU) PTC12 input/o utput (port) DACK1 outpu[...]

Section 22 Pin Function Controller (PFC) Rev. 4. 00 Sep. 14, 2005 Page 821 of 982 REJ09B0023-0400 Port Port Functi on (Related Module) Other Function (Related Module) E PTE15 input/output (port) TIOC0A input/output (MTU) PTE14 input/output (port) TIOC0B input/output (MTU) PTE13 input/output (port) TIOC0C input/output (MTU) PTE12 input/output (port)[...]

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 822 of 982 REJ09B0023-0400 Port Port Functi on (Related Module) Other Function (Related Module) G PTG13 input/output (port)  PTG12 input/output (port)  PTG11 input/output (port)  PTG10 input/output (port) SDA input/outp ut (IIC2) PTG9 input/output (port) SDL input/output[...]

Section 22 Pin Function Controller (PFC) Rev. 4. 00 Sep. 14, 2005 Page 823 of 982 REJ09B0023-0400 Port Port Functi on (Related Module) Other Function (Related Module) J PTJ12 input/output (port) AUDSYNC output (AUD) PTJ11 input/out put (port) AUDATA3 output (AUD) PTJ10 input/out put (port) AUDATA2 output (AUD) PTJ9 input/out put (port) AUDATA1 outp[...]

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 824 of 982 REJ09B0023-0400 22.1.1 Port A Control R egist er (PACR) PACR is a 32-bit readable/writab le register that selects the pin function s . PACR is initialized to H ' 00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in slee[...]

Section 22 Pin Function Controller (PFC) Rev. 4. 00 Sep. 14, 2005 Page 825 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 7 6 PA3MD2 PA3MD1 0 0 R/W R/W 5 4 PA2MD2 PA2MD1 0 0 R/W R/W 3 2 PA1MD2 PA1MD1 0 0 R/W R/W 1 0 PA0MD2 PA0MD1 0 0 R/W R/W PAn Mode 2 and 1 The combination of bits PAnMD2 and PAnMD1 (n = 0 to 14) controls the pin[...]

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 826 of 982 REJ09B0023-0400 22.1.2 Port B Control Register (PBCR) PBCR is a 32-bit readable/writable register th at selects the pin functions. PBCR is initialized to H ' 00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mo[...]

Section 22 Pin Function Controller (PFC) Rev. 4. 00 Sep. 14, 2005 Page 827 of 982 REJ09B0023-0400 22.1.3 Port C Control R egist er (PCCR) PCCR is a 32-bit readable/writable register th at selects the pin functions. PCCR is initialized to H ' 0C000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep[...]

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 828 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 7 6 PC3MD2 PC3MD1 0 0 R/W R/W 5 4 PC2MD2 PC2MD1 0 0 R/W R/W 3 2 PC1MD2 PC1MD1 0 0 R/W R/W 1 0 PC0MD2 PC0MD1 0 0 R/W R/W PCn Mode 2 and 1 The combination of bits PCnMD2 and PCn MD1 (n = 0 to 15) controls the pin[...]

Section 22 Pin Function Controller (PFC) Rev. 4. 00 Sep. 14, 2005 Page 829 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 17 16 PD8MD2 PD8MD1 0/1 0/1 R/W R/W 15 14 PD7MD2 PD7MD1 0/1 0/1 R/W R/W 13 12 PD6MD2 PD6MD1 0/1 0/1 R/W R/W 11 10 PD5MD2 PD5MD1 0/1 0/1 R/W R/W 9 8 PD4MD2 PD4MD1 0/1 0/1 R/W R/W 7 6 PD3MD2 PD3MD1 0/1 0/1 R/W R[...]

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 830 of 982 REJ09B0023-0400 22.1.5 Port E Control Register (PECR) PECR is a 32-bit readable/writable register th at selects th e pin functions. PECR is initialized to H ' 00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep m[...]

Section 22 Pin Function Controller (PFC) Rev. 4. 00 Sep. 14, 2005 Page 831 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 7 6 PE3MD2 PE3MD1 0 0 R/W R/W 5 4 PE2MD2 PE2MD1 0 0 R/W R/W 3 2 PE1MD2 PE1MD1 0 0 R/W R/W 1 0 PE0MD2 PE0MD1 0 0 R/W R/W PEn Mode 2 and 1 The combination of bits PEnMD2 and PEnMD1 (n = 0 to 15) controls the pin[...]

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 832 of 982 REJ09B0023-0400 22.1.6 Port E I/O Register (PEIOR) PEIOR is a 16-bit readable/writable register that selects the input/output di rection of the p ort E pins. The PE15IOR to PE0IOR bits corresp ond to t he PE15/TIO C0A to PE0/T IOC4D pi ns. PEIOR is valid only when the [...]

Section 22 Pin Function Controller (PFC) Rev. 4. 00 Sep. 14, 2005 Page 833 of 982 REJ09B0023-0400 22.1.7 Port E MTU R/W Enable Register (PEMTURWER) PEMTURWER is a 16-bit readable/writabl e regist er that a llows access of the MTU registers. PEMTURWER is initialized to H ' 0001 by a power-on reset, and it is not initialized by a manual reset, i[...]

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 834 of 982 REJ09B0023-0400 22.1.8 Port F Control Register (PFCR) PFCR is a 32-bit readable/writable register that selects the pin functions. PFCR is initialize d to H ' 00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mo[...]

Section 22 Pin Function Controller (PFC) Rev. 4. 00 Sep. 14, 2005 Page 835 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 15 14 PF7MD2 PF7MD2 0 0 R/W R/W 13 12 PF6MD2 PF6MD2 0 0 R/W R/W 11 10 PF5MD2 PF5MD2 0 0 R/W R/W 9 8 PF4MD2 PF4MD2 0 0 R/W R/W 7 6 PF3MD2 PF3MD2 0 0 R/W R/W 5 4 PF2MD2 PF2MD2 0 0 R/W R/W 3 2 PF1MD2 PF1MD2 0 0 R[...]

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 836 of 982 REJ09B0023-0400 22.1.9 Port G Control Register (PGCR) PGCR is a 32-bit readable/writab le register that selects the pin function s. PGCR is initial ized to H ' 00000000 by a power-on reset, and it is not initialized by a manual reset, in the standby mode, or in th[...]

Section 22 Pin Function Controller (PFC) Rev. 4. 00 Sep. 14, 2005 Page 837 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 15 14 PG7MD2 PG7MD2 0 0 R/W R/W 13 12 PG6MD2 PG6MD2 0 0 R/W R/W 11 10 PG5MD2 PG5MD2 0 0 R/W R/W 9 8 PG4MD2 PG4MD2 0 0 R/W R/W 7 6 PG3MD2 PG3MD2 0 0 R/W R/W 5 4 PG2MD2 PG2MD2 0 0 R/W R/W 3 2 PG1MD2 PG1MD2 0 0 R[...]

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 838 of 982 REJ09B0023-0400 22.1.10 Port H Contr ol Register (PHCR) PHCR is a 32-bit readable/writab le register that selects the pin function s . PHCR is initialized to H ' 00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in slee[...]

Section 22 Pin Function Controller (PFC) Rev. 4. 00 Sep. 14, 2005 Page 839 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 7 6 PH3MD2 PH3MD2 0 0 R/W 5 4 PH2MD2 PH2MD2 0 0 R/W 3 2 PH1MD2 PH1MD2 0 0 R/W 1 0 PH0MD2 PH0MD2 0 0 R/W PHn Mode 2 and 1 The combination of bits PHnMD2 and PHn MD1controls the pin functions. (n = 0 to 14) 00: [...]

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 840 of 982 REJ09B0023-0400 Bit Bit Name Initial Value R/W Description 13 12 PJ6MD2 PJ6MD2 0 0 R/W 11 10 PJ5MD2 PJ5MD2 0 0 R/W 9 8 PJ4MD2 PJ4MD2 0 0 R/W 7 6 PJ3MD2 PJ3MD2 0 0 R/W 5 4 PJ2MD2 PJ2MD2 0 0 R/W 3 2 PJ1MD2 PJ1MD2 0 0 R/W 1 0 PJ0MD2 PJ0MD2 0 0 R/W PJn Mode 2 and 1 The com[...]

Section 22 Pin Function Controller (PFC) Rev. 4. 00 Sep. 14, 2005 Page 841 of 982 REJ09B0023-0400 22.2 I/O Buffer Internal Block Diagram 22.2.1 I/O Buffer with Weak Keeper All the I/O buffers exce pt PTG10, PTG9, an d PTG 7 t o PTG 0 (IIC2 and analog pins ) list ed in table 22.1 have weak keepers that consist o f two inverter s to keep the status o[...]

Section 22 Pin Function Controller (PFC) Rev. 4.00 Sep. 14, 2005 Page 842 of 982 REJ09B0023-0400 SDA input data SCL input data SDA output data SCL output data PTG[10] output enable PTG[9] output enable PTG[10] output data PTG[9] output data PTG[10] input data PTG[9] input data PTG[10] /SD A PTG[9] /SCL Figure 22.2 Internal Block Diag ram of I/O Buf[...]

Section 23 I/O Ports Rev. 4. 00 Sep. 14, 2005 Page 843 of 982 REJ09B0023-0400 Section 23 I/O Ports This LSI has nine 16 -bit ports (ports A to J). All port pins are mult iplexed with othe r pin fu nctions (the pin functi on cont r oll e r ( PFC ) ha ndl es the selection of pin funct i o ns ). Each p ort has a data register which stores data for the[...]

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 844 of 982 REJ09B0023-0400 23.1.2 Port A Data Register (PADR) PADR is a 15-bit readable/writable reg ister with one reserved bit that stores data for pins PTA14 to PTA0. PADR is initialized to H ' 0000 by a power-on reset, but it retains its pr evious value by a manual reset, in standby mode or[...]

Section 23 I/O Ports Rev. 4. 00 Sep. 14, 2005 Page 845 of 982 REJ09B0023-0400 Table 23.1 Port A Data Register (PADR) Re ad/Write Operati ons PAnMD2 PAnMD1 Pin Function Read Write 0 0 Input Pin state Data is wri tten to PADR, but does not affect pin state. 1 Output PADR value Data is written to PADR and the value is output from the pin. 1 0 Reserved[...]

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 846 of 982 REJ09B0023-0400 23.2.2 Port B Data Register (PBDR) PBDR is a 9 -bit readable/ writable re gister wi th seven reserved bi ts that stores data for pi ns PTB8 to PTB0. PBDR is initialized to H ' 0000 by a po wer-on reset , but it retai ns its previo us value by a manual reset, in standb[...]

Section 23 I/O Ports Rev. 4. 00 Sep. 14, 2005 Page 847 of 982 REJ09B0023-0400 23.3 Port C Port C is a 16-bit input/output port with the pin configuration sh own in figure 23.3. Each pin is controlled by the port C cont rol register (PCCR) i n the PFC . Po r t C PTC15 (input/output)/ST A TUS1 (output) PTC14 (input/output)/ST A TUS0 (output) PTC13 (i[...]

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 848 of 982 REJ09B0023-0400 23.3.2 Port C Data Register (PCDR) PCDR is a 16-bit readable/writable reg ister th at stores data for pins PTC15 to PTC 0. PCDR is initialized to H ' 0000 by a pow er-on reset, b ut it retai ns its previo us value by a man ual reset, i n standby mode, or in sleep m od[...]

Section 23 I/O Ports Rev. 4. 00 Sep. 14, 2005 Page 849 of 982 REJ09B0023-0400 Table 23.3 Port C Data Register (PCDR) Re ad/Write Operati ons PCnMD2 PCnMD1 Pin State Read Write 0 0 Input Pin state Data is writt en to PCDR, but does not affect pin state. 1 Output PCDR value Data is written to PCDR an d the value is output from the pin. 1 0 Reserved ?[...]

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 850 of 982 REJ09B0023-0400 23.4.1 Register Description Port D has the followin g register. • Port D data register (PDDR) 23.4.2 Port D Data Register (PDDR ) PDDR is a 16-bit readable/writable reg ister th at stores data for pi ns PTD15 to PTD0. PD DR is initialized to H ' 0000 by a po wer-on [...]

Section 23 I/O Ports Rev. 4. 00 Sep. 14, 2005 Page 851 of 982 REJ09B0023-0400 Table 23.4 Port D Data Register (PDDR) Re ad/Write Operati ons PDnMD2 PDnMD1 Pin State Read Write 0 0 Input Pin state Data is writt en to PDDR, but does not affect pin state. 1 Output PDDR value Data is written to PDDR an d the value is output from the pin. 1 0 Reserved ?[...]

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 852 of 982 REJ09B0023-0400 23.5.1 Register Description Port E has the following register. • Port E data register (PEDR) 23.5.2 Port E Data Register (PEDR) PEDR is a 16-bit readable/writable reg ister th at st ores data for pins PTE15 to PTE0 . The PEDR is initialized to H ' 0000 by a pow er-o[...]

Section 23 I/O Ports Rev. 4. 00 Sep. 14, 2005 Page 853 of 982 REJ09B0023-0400 Table 23.5 Port E Data Regist er (PEDR) Read/Write Operations PEnMD2 PEnMD1 Pin State Read Write 0 0 Input Pin state Data is wri tten to PEDR, but does not affect pin state. 1 Output PEDR value Data is written to PEDR and the value is output from the pin. 1 0 Reserved [...]

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 854 of 982 REJ09B0023-0400 23.6.1 Register Description Port F has the following register. • Port F data register (PFDR) 23.6.2 Port F Data Register (PFDR) PFDR is a 16-bit readable/writable register that stores data for pins PTF15 to PTF0. PFDR is initialized to H ' 0000 by a pow er-on reset,[...]

Section 23 I/O Ports Rev. 4. 00 Sep. 14, 2005 Page 855 of 982 REJ09B0023-0400 Table 23.6 Port F Data Re gister (PFDR) Read/Write Op erations (PF15DT to PF8DT) PFnMD2 PFnMD1 Pin State Read Write 0 0 Input Pin state Data is wri tten to PFDR, but does not affect pin state. 1 Output PFDR value Data is written to PFDR and the value is output from the pi[...]

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 856 of 982 REJ09B0023-0400 23.7 Port G Port G comp rises a 6- bit input /output port and a n 8-bit input p ort with t he pin con figuratio n shown in figure 23 .7. Each pin is control led by the port G c ontrol r egister (PGC R) in the PFC . Po r t G PTG13 (input/output) PTG12 (input/output) PTG11 ([...]

Section 23 I/O Ports Rev. 4. 00 Sep. 14, 2005 Page 857 of 982 REJ09B0023-0400 23.7.2 Port G Data Register (PGDR) PGDR a register that includes si x readable/writable and eight readable b its with two reserved bits that store data for pins PTG13 to PTG0. PGDR13 to PGDR8 are initialized to H ' 00 by a powe r- on reset , but t hey ret ai n their [...]

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 858 of 982 REJ09B0023-0400 Table 23.8 Port G Data Register (PGDR) Read/ Wr ite Operations (PG1 3DT to PG11DT, PG8DT) PGnMD2 PGnMD1 Pin State Read Write 0 0 Input Pin state Data is wri tten to PGDR, but does not affect pin state. 1 Output PGDR value Data is written to PGDR and the value is output fro[...]

Section 23 I/O Ports Rev. 4. 00 Sep. 14, 2005 Page 859 of 982 REJ09B0023-0400 23.7.3 Port G Internal Bl ock Diagram Pins PTG7 to PTG0 are multiplexed with the A /D converter. (See section 22, Pin Fun ction Controller (PFC).) The statuses of these pins are read only when th e PGDR is read, but a re always input to the A/D conv erter. Figure 23. 8 sh[...]

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 860 of 982 REJ09B0023-0400 23.8 Port H Port H comprises a 15-bit inpu t/output port with th e pin configuratio n shown in figur e 23.9. Each pin is contr olled by the port H cont rol register ( PHCR) in t he PFC. Po r t H PTH14 (input/output)/ RTS2 (input/output) PTH13 (input/output)/RXD2 (input) PT[...]

Section 23 I/O Ports Rev. 4. 00 Sep. 14, 2005 Page 861 of 982 REJ09B0023-0400 23.8.2 Port H Data Register (PHDR) PHDR is a 15-bit readable/writable reg ister with one reserved bit that stores data for pins PTH14 to PTH0. PHDR is initialized to H ' 0000 by a power-on reset, but it retains its pr evious value by a manual reset, in standby mode, [...]

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 862 of 982 REJ09B0023-0400 Table 23.11 Port H Data Register (PHDR) Read/Write Operations PHnMD2 PHnMD1 Pin State Read Write 0 0 Input Pin state Data is writt en to PHDR, but does not affect pin state. 1 Output PHDR value Data is written to PHDR and the value is output from the pin. 1 0 Reserved  [...]

Section 23 I/O Ports Rev. 4. 00 Sep. 14, 2005 Page 863 of 982 REJ09B0023-0400 23.9.2 Po rt J Data Register (PJDR) PJDR is a 13-bit readable/writable register with thre e reserved bits that stores data for pins PTJ12 to PTJ0. The PJDR is initializ ed to H ' 0000 by a power-on reset, but it retains its prev ious value by a manual reset, in stand[...]

Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 864 of 982 REJ09B0023-0400[...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 865 of 982 REJ09B0023-0400 Section 24 List of Registers This section gi ves informat ion on the on-chip I/O register s and is confi gured as desc ribed below. 1. Register Addresses (by functional mo dule, in order of the c orrespon ding section numbers) • Descriptions by funct ional modul[...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 866 of 982 REJ09B0023-0400 24.1 Register Address es (by functional module, in order of the corresponding section numbers) Entries under Access size indicates numbers of bits. Note: Access to unde fined or rese rved addresses is prohibit ed. Since ope ration or co ntinued operation is not gua[...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 867 of 982 REJ09B0023-0400 Register Name Abbreviation Bi t No. Address Module Access States Interrupt mask register 0 IMR0 8 H'A408 0040 INTC 8 Interrupt mask register 1 IMR1 8 H'A408 0042 8 Interrupt mask register 2 IMR2 8 H'A408 0044 8 Interrupt mask register 4 IMR4 8 H&apo[...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 868 of 982 REJ09B0023-0400 Register Name Abbreviation Bi t No. Address Module Access States Break data register B BDRB 32 H'A4FFFF90 UBC 32 Break data mask register B BDMRB 32 H'A4FFFF94 32 Break control register BRCR 32 H'A4FFFF98 32 Execution Times Break Register BETR 16 H&a[...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 869 of 982 REJ09B0023-0400 Register Name Abbreviation Bi t No. Address Module Access States Refresh timer control/status re gister RTCSR 16 H'A4FD0048 BSC 32 * 3 Refresh timer counter RTCNT 16 H'A4FD004C 32 * 3 Refresh time constant register RTCOR 16 H'A4FD0050 32 * 3 Reset w[...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 870 of 982 REJ09B0023-0400 Register Name Abbreviation Bi t No. Address Module Access States I 2 C bus control register 1 ICCR1 8 H'A447 0000 II C2 8 I 2 C bus control register 2 ICCR2 8 H'A447 0001 8 I 2 C bus mode register ICMR 8 H'A447 0002 8 I 2 C bus interrupt enable re gi[...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 871 of 982 REJ09B0023-0400 Register Name Abbreviation Bi t No. Address Module Access States Timer output control register TOCR 8 H'A449 000B MTU 8/16/32 Timer gate control register TGCR 8 H'A449 000D 8 Timer counter_3 TCNT_3 16 H'A449 0010 16/32 Timer counter_4 TCNT_4 16 H&ap[...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 872 of 982 REJ09B0023-0400 Register Name Abbreviation Bi t No. Address Module Access States Timer control register_1 TCR_1 8 H'A449 0080 MTU 8/16 Timer mode register_1 TMDR_1 8 H'A449 0081 8/16 Timer I/O control register _1 TIOR_1 8 H'A449 0082 8 Timer interrupt enable regis t[...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 873 of 982 REJ09B0023-0400 Register Name Abbreviation Bi t No. Address Module Access States Bit rate register_1 SCBR R_1 8 H'A441 0004 SCIF 8 Serial control register_1 SCSCR_1 16 H'A441 0008 16 Transmit FIFO data register_1 SCFTDR_1 8 H'A441 000C 8 Serial status register_1 SC[...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 874 of 982 REJ09B0023-0400 Register Name Abbreviation Bi t No. Address Module Access States USB interrupt enable register 1 USBIER1 8 H'A448 000D USB 8 USBEP1 receive data size register USBEPSZ1 8 H'A448 000F 8 USB interrupt select register 1 USBISR1 8 H'A448 0010 8 USB DMA tr[...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 875 of 982 REJ09B0023-0400 Register Name Abbreviation Bi t No. Address Module Access States Port J control register PJCR 32 H'A443 0020 PFC 8/16/32 Port E I/O register PEIOR 16 H'A443 0038 8/16 Port E MTU R/W enable register PEMTURWER 16 H'A443 003A 8/16 — — — — — ?[...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 876 of 982 REJ09B0023-0400 24.2 Register Bits Register addre sses and bit names of t he on-chip peripheral mo dules are descri bed below . Each line cove rs eight bits , and 16- bit and 32-bit registers are shown as 2 or 4 lines, res pectivel y. Register Abbreviation Bit 31/23/15/7 Bit 30/22[...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 877 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi t 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module EXPEVT — — — — — — — — Exception — — — — — — — — handling — — — — IPRF IPR15[...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 878 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi t 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module IMCR9 I MC7 IMC6 IMC5 IMC4 IMC3 IMC2 IMC1 IMC0 INTC IMCR10 IMC7 IMC6 IMC5 IMC4 IMC3 IMC2 IMC1 IMC0 IRR0 IRQ7R IRQ6R I[...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 879 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi t 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module BETR — — — — BET11 BET10 BET9 BET8 UBC BET7 BET6 BET5 BET4 BET3 BET2 BET1 BET0 BARB BAB31 BAB30 BAB29 BAB28 [...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 880 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi t 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module CMNCR — — — — — — — — BSC — — — — — — — — WAITSEL — — MAP BLOCK DPRTY1 DPRTY0 DMA[...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 881 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi t 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module CS6ABCR — IWW2 IWW1 IWW0 IWRW D2 IWRWD1 IWRWD0 IWRWS2 BSC IWRWS1 I WRWS0 IWRRD2 IWRRD1 IWRRD0 IWRRS2 IWRRS1 IWRRS0[...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 882 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi t 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module CS3WCR * 1 — — — — — — — — BSC — — — BAS — — — — — — — — — WR3 WR2 WR1 WR0 WM[...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 883 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi t 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module CS6BWCR * 1 — — — — — — — — BSC — — — BAS — — — — — — — SW1 SW0 WR3 WR2 WR1 WR0 [...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 884 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi t 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module D M A T C R _ 0 D M A C CHCR_0 TC — — — — — — — DO TL — — — — AM AL DM1 DM0 SM1 SM0 RS3 RS2 RS1[...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 885 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi t 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module D A R _ 2 D M A C D M A T C R _ 2 CHCR_2 TC — — — — — — — — — — — — — — — DM1 DM0 SM1 [...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 886 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi t 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module DMAOR — — CMS1 CMS0 — — PR1 PR0 DMAC — — — — — AE NMIF DME — — — — — — — — — — [...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 887 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi t 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module CMSTR_1 — — — — — — — — CMT — — — — — — — STR CMCSR_1 — — — — — — — — [...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 888 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi t 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module T G R B _ 3 M T U T G R A _ 4 T G R B _ 4 T C N T S T C B R T G R C _ 3 T G R D _ 3 T G R C _ 4 T G R D _ 4 TSR_3 TCF[...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 889 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi t 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module T G R A _ 0 M T U T G R B _ 0 T G R C _ 0 T G R D _ 0 TCR_1 CCLR2 CCLR1 CCLR0 CKEG 1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_1 [...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 890 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi t 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module ICSR1 POE3F POE2F POE1F POE0F — — — PIE MTU POE3M1 POE3M0 POE2M1 POE2M0 POE1M1 POE1M0 POE0M1 POE0M0 OCSR OSF ?[...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 891 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi t 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module SCFCR_1 — — — — — RSTRG2 RSTRG1 RSTRG0 SCIF RTRG1 RTRG0 TTRG1 TTRG0 MCE TFRST RFRST LOOP SCFDR_1 — — ?[...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 892 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi t 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module USBEPSZ0o — — — — — — — — USB USBEPDR0s D7 D6 D5 D4 D3 D2 D1 D0 USBDASTS — — EP3DE EP2DE — — [...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 893 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi t 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module ADDRD1 ADC — — — — — — ADCSR0 ADF ADIE ADST DMASL TRGE — — — CKS1 CKS0 MULTI1 MULTI0 — — CH1 C[...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 894 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi t 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module PFCR PF15MD2 PF15MD1 PF14MD2 PF14MD1 PF13MD2 PF13MD1 PF12MD2 PF12MD1 PFC PF11MD2 PF11MD1 PF10MD2 PF10MD1 PF9MD2 PF9MD[...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 895 of 982 REJ09B0023-0400 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bi t 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module PFDR PF15DT PF14DT PF13DT PF12DT PF 11DT PF10DT PF9DT PF8DT PORT PF7DT PF6DT PF5DT PF4DT PF3DT PF2DT PF1DT PF0DT PGD[...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 896 of 982 REJ09B0023-0400 24.3 Register States in Each Operating Mode Register Abbreviation Power-On Reset Manual Reset Software Standby Module Standby Sleep Module FRQCR Initialized * 1 Retained Retained  Retained CPG WTCNT Initialized * 1 Retained Retained  Retained WDT WTCSR Initia[...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 897 of 982 REJ09B0023-0400 Register Abbreviation Power-On Reset Manual Reset Software Standby Module Standby Sleep Module IMCR0 Initialized Initialized Retained  Retained INTC IMCR1 Initialized Initialized Retained  Retained IMCR2 Initialized Initialized Retained  Retained IMCR4 In[...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 898 of 982 REJ09B0023-0400 Register Abbreviation Power-On Reset Manual Reset Software Standby Module Standby Sleep Module BBRA Initialized Retained Retained Retained Retained UBC BRDR Undefined * 2 Retained Retained Retained Retained CMNCR Initialized Ret ained Retained  Retained BSC CS0B[...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 899 of 982 REJ09B0023-0400 Register Abbreviation Power-On Reset Manual Reset Software Standby Module Standby Sleep Module DAR_1 Undefined Undefined Retained Retained Retained DMAC DMATCR_1 Undefined Undefined Retained Retained Retained CHCR_1 Initialized Initialized Retained Retained Retain[...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 900 of 982 REJ09B0023-0400 Register Abbreviation Power-On Reset Manual Reset Software Standby Module Standby Sleep Module CMCOR_0 Initialized Retained Retained Retained Retained CMT CMSTR_1 Initialized Retained Retained Retained Retained CMCSR_1 Initialized Retained Retained Retained Retaine[...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 901 of 982 REJ09B0023-0400 Register Abbreviation Power-On Reset Manual Reset Software Standby Module Standby Sleep Module TGRD_3 Initialized Retained Initialized Initialized Retained MTU TGRC_4 Initialized Retained Initialized Initialized Retained TGRD_4 Initialized Retained Initialized Ini[...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 902 of 982 REJ09B0023-0400 Register Abbreviation Power-On Reset Manual Reset Software Standby Module Standby Sleep Module TIER_2 Initialized Retained Init ialized Initialized Retained MTU TSR_2 Initialized Retained Initialized Initialized Retained TCNT_2 Initialized Retained Init ialized Ini[...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 903 of 982 REJ09B0023-0400 Register Abbreviation Power-On Reset Manual Reset Software Standby Module Standby Sleep Module SCSCR_2 Initialized Retained Re tained Retained Retained SCIF SCFTDR_2 Undefined Retained Retained Retained Retained SCFSR_2 Initialized Retained Retained Retained Retai[...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 904 of 982 REJ09B0023-0400 Register Abbreviation Power-On Reset Manual Reset Software Standby Module Standby Sleep Module USBIER2 Initialized Retained Retained Retained Retained USB USBCTRL Initialized Retained Retained Retained Retained ADDRA0 Initialized Retained Initialized Initialized Re[...]

Section 24 List of Registers Rev. 4. 00 Sep. 14, 2005 Page 905 of 982 REJ09B0023-0400 Register Abbreviation Power-On Reset Manual Reset Software Standby Module Standby Sleep Module PFDR Initialized Retained Retained — Retained PORT PGDR Initialized * 3 Retained Retained — Retained PHDR Initialized Ret ained Retained — Retained PJDR Initialize[...]

Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 906 of 982 REJ09B0023-0400[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 907 of 982 REJ09B0023-0400 Section 25 Electrical Characteristi cs The specifications shown in th is section are preliminary. After the characteristics ha ve been evaluated, the sp ecifications may be ch anged without n otice. 25.1 Absolute Maximum Ratings Table 25.1 lists the abso[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 908 of 982 REJ09B0023-0400 25.1.1 Power-On Sequence Supply the power so that Vc cQ (3.3-V s ystem) and Vcc ( 1 .8-V system) are supplied simultaneously or Vcc is supplied after VccQ is supplied. Recommended value s for the power-on p rocedure a re shown belo w. V CC Q (min.) voltag[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 909 of 982 REJ09B0023-0400 Table 25.2 Recommended Values for Power-On/Off Sequence Item Symbol Max. Permissible Value Unit Time lag between VccQ and Vcc when turning on tpwu 1 ms Time lag between VccQ and Vcc when turning off tpwd 1 ms Unsettling operation time tunc 100 ms Notes: [...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 910 of 982 REJ09B0023-0400 25.2 DC Characteristics Tables 25.3 and 25.4 list DC characteristics. Table 25.3 DC Characteristics (1) [Common Ite ms] Conditions: Ta = − 40°C to + 85°C Item Symbol Min. Typ. Max. Unit Test Conditions Current consumption * 1 Normal operation I CC * 2[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 911 of 982 REJ09B0023-0400 Table 25.3 DC Characteristic s (2) [Exc ept for I 2 C- an d USB-Related Pins] Conditions : V CC = V CC (PLL1, PLL 2) = 1.8 V ± 5%, V CC Q = 3.0 V to 3.6 V, A V CC = 3.0 V to 3 .6 V, V SS = V SS (PLL1, PLL2 ) = AV SS = 0 V, Ta = − 40°C to + 85°C Item[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 912 of 982 REJ09B0023-0400 Item Symbol Min. Typ. Max. Unit Test Con ditions V T + V CC Q × 0.9 — — V V T − — — V CC Q × 0.2 V Schmitt trigger input characteristic s TIOC0A to TIOC0D, TIOC1A, TIOC1B, TIOC2A, TIOC2B, TIOC3A to TIOC3D, TIOC4A to TIOC4D, TCLKA to TCLKD, SCK[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 913 of 982 REJ09B0023-0400 Table 25.3 DC Characteristic s (3) [I 2 C-Related Pins * ] Conditions : V CC Q = 3.0 V to 3.6 V, V CC = 1.8 V ± 5% , V SS Q = V SS = 0 V, Ta = − 40°C to + 85°C Item Symbol Min. Typ. Max. Unit Test Conditions Power supply V CC Q 3.0 3.3 3.6 V Input h[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 914 of 982 REJ09B0023-0400 Table 25.3 DC Charac teristics ( 5) [USB Transcei ver-Related Pin s * ] Conditions: Ta = − 40°C to + 85°C Item Symbol Min. Typ. Max. Unit Test Conditions Differential input sensitivity V DI 0.2 — — V  (DP) – (DM)  Differential common mode [...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 915 of 982 REJ09B0023-0400 25.3 AC Characteristics Signals input to this LS I are basicall y handled as signals in sync hronizatio n with a clock . The setup and hold times for input pins must be followe d. Table 25.5 Maximum Operating Frequency Conditions : V CC Q = 3.0 V to 3.6 [...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 916 of 982 REJ09B0023-0400 25.3.1 Clock Timing Table 25.6 Clock Timing Conditions : V CC Q = 3.0 V to 3.6 V, V CC = 1. 8 V ± 5%, A V CC = 3.0 V to 3.6 V, V SS Q = V SS = AV SS = 0 V, Ta = − 40°C to + 85°C Item Symbol Min. Max. Unit Figure(s) EXTAL clock input frequency f EX 10[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 917 of 982 REJ09B0023-0400 t EXH t EXF t EXR t EXL t EXcyc V IH V IH V IH 1/2 V CC 1/2 V CC V IL V IL EXTAL * (input) Note: * When the clock is input on the EXTAL pin. Figure 25.2 EXTAL Clock Input Timing t CKIH t CKIF t CKIR t CKIL t CKIcyc V IH V IH V IH 1/2 V CC Q 1/2 V CC Q V [...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 918 of 982 REJ09B0023-0400 V CC min t RESP/MW t RESP/MS t OSC1 V CC RESETP RESETM CKIO, Internal clock Note: Oscillation settling time when the internal oscillator is used. Oscillation settling time Figure 25.5 Oscillatio n Settling Timing (Power-On) CKIO CKIO2 t phckio2 Figure 25.[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 919 of 982 REJ09B0023-0400 CKIO, Internal clock Oscillation settling time Standby period Note: Oscillation settling time when the internal oscillator is used. t OSC3 NMI , IRQ Figure 25.8 Oscilla tion Settling Ti ming (Sta ndby Mode Canceled by NMI or IRQ )[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 920 of 982 REJ09B0023-0400 25.3.2 Control Signal Timing Table 25.7 Control Signal Timing Conditions : V CC Q = 3.0 V to 3.6 V, V CC = 1. 8 V ± 5% , AV CC = 2.7 V to 3.6 V, V SS Q = V SS = AV SS = 0 V, Ta = − 40°C to + 85°C B φ = 50 MHz * 2 Item Symbol Min. Max. Unit Figure(s)[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 921 of 982 REJ09B0023-0400 CKIO t RESPS/MS t RESPS/MS RESETP RESETM t RESPW/MW Figure 25.9 Reset Input Timing CKIO RESETP RESETM t RESPH/MH t RESPS/MS V IH V IL NMI t NMIH t NMIS V IH V IL I RQ7 to IRQ0 t IRQH t IRQS V IH V IL Figure 25.10 Int errupt Input Timing[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 922 of 982 REJ09B0023-0400 CKIO (HIZCNT = 1) BREQ BACK A25 to A0, D31 to D0 RD , RD/ WR , RASU/L , CASU/L , CSn , WEn , BS , CKE CKIO (HIZCNT = 0) BREQH t BOFF2 t BREQS t BACKD t BACKD t BREQH t BREQS t BON1 t BOFF1 t BOFF2 t BON2 t BON2 t When HZCNT = 1 When HZCNT = 0 Figure 25.11[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 923 of 982 REJ09B0023-0400 25.3.3 AC Bus Timing Table 25.8 Bus Timing Conditions: Clock mode 2/6/ 7, V CC Q = 3.0 V t o 3.6 V , V SS Q = 0 V, Ta = − 40°C to + 85°C B φ = 50 MHz * Item Symbol Min. Max. Unit Figure(s) Address delay time 1 t AD1 1 12 ns 25.13 to 2 5.39 Address d[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 924 of 982 REJ09B0023-0400 B φ = 50 MHz * Item Symbol Min. Max. Unit Figure(s) Write data delay time 1 t WDD1 — 14 ns 25.13 to 2 5.21 Write data delay time 2 t WDD2 — 14 ns 25.27 to 25.30, 25.34 to 25.36 Write data delay time 3 t WDD3 — 1/2t cyc + 14 ns 25.40 Write enable ho[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 925 of 982 REJ09B0023-0400 25.3.4 Basic Timing T1 t AD1 t AS t CSD1 T2 t AD1 t RWD 1 t RWD 1 t CSD1 t RSD t RSD t AH t RDH1 t RDS1 t WED1 t WED1 t AH t BSD t BSD t DACD t DACD t WDH1 t WDD1 CKIO A25 to A0 CSn RD/ WR RD D31 to D0 Read WEn BS DACKn * Note: * W a vef orm for DACKn wh[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 926 of 982 REJ09B0023-0400 T1 t AD1 t AS t CSD1 Tw T2 t AD1 t RWD1 t RWD1 t CSD1 t RSD t RSD t AH tRDH1 t RDS1 t WED1 t WED1 t AH t BSD t BSD t WTH1 t WTS1 t DACD t DACD t WDH1 t WDD1 WAIT Note: * W a vef orm for DACKn when activ e low is selected. CKIO A25 to A0 CSn RD/ WR RD D31 [...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 927 of 982 REJ09B0023-0400 T1 t AD1 t AS t CSD1 Tw X T2 t AD1 t RWD1 t RWD1 t CSD1 t RSD t RSD t AH t RDH1 t RDS1 t WED1 t WED1 t AH t BSD t BSD t WTH1 t WTS1 t WTH1 t WTS1 t DACD t DACD t WDH1 t WDD1 WAIT Note: * W a vef orm for DACKn when activ e low is selected. CKIO A25 to A0 [...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 928 of 982 REJ09B0023-0400 T1 t AD1 t AS t CSD1 Tw X T2 t AD1 t RWD1 t RWD1 t CSD1 t RSD t RSD t AH t RDH1 t RDS1 t WED1 t WED1 t AH t BSD t BSD t WTH2 t WTS2 t WTH2 t WTS2 t DACD t DACD t WDH1 t WDD1 WAIT Note: * W a vef orm for DACKn when activ e low is selected. CKIO A25 to A0 C[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 929 of 982 REJ09B0023-0400 t AD1 t AD1 T1 t RWD 1 t RSD t WED1 t WED1 t WED1 t RDS1 t RDS1 t RDH1 t RDH1 t AS t RSD t RSD t AH t RSD t AH t WED1 t AH t AH t CSD1 t WDD1 t WDH1 t WDH1 t WDD1 t BSD t BSD t DACD t DACD t DACD t DACD t BSD t BSD t RWD1 t RWD 1 t RWD 1 t CSD1 t CSD1 t [...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 930 of 982 REJ09B0023-0400 Ta 1 Ta 2 Ta 3 T1 Tw Tw T 2 t AD1 t CSD1 t AD1 t RWD1 t RWD1 t CSD1 t RSD t RSD t RDS1 t WED1 t WED1 Data Data t BSD t BSD t WTH1 t WTS1 t AHD t AHD t WTH1 t WTS1 t DACD t DACD Address t WDH1 t WDD1 t MAD CKIO A25 to A0 CS5B RD/ WR RD AH D15 to D0 Read WE[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 931 of 982 REJ09B0023-0400 Tm1 t AD1 t CSD1 Tmd1w Tmd1 t AD1 t RWD1 t FMD t WDD1 t FMD t FMD t RWD 1 t CSD1 CKIO A25 to A0 CS6B RD/ WR D31 to D0 D31 to D0 Read BS FRAME WAIT WEn RD Write t WDH1 t WDD1 t RDS2 t WDD1 t BSD t DACD t DACD t WTH1 t WTS1 t BSD t WDH1 t WDH1 t RDH2 Note:[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 932 of 982 REJ09B0023-0400 25.3.5 Bus Cycle of Byte-Selection SRAM Th t AD1 t RSD t RSD t RDS1 t CSD1 t RWD1 T1 T wx T2 Tf t WDD1 t BSD t WDH1 t RDH1 t AD1 t CSD1 CKIO A25 to A0 CSn WEn RD D31 to D0 D31 to D0 Read RD/ WR RD/ WR BS WAIT Write t DACD t DACD t BSD t WTS1 t WTS1 t RWD1[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 933 of 982 REJ09B0023-0400 Th t AD1 t RSD t RSD t RDS1 t CSD1 T1 T wx T2 Tf t RWD1 t WDD1 t BSD t RWD1 t RWD 1 t WDH1 t RDH1 t AD1 t CSD1 CKIO A25 to A0 CSn WEn RD D31 to D0 D31 to D0 Read RD/ WR RD/ WR BS WAIT DACKn , TENDn * Note: * W a vef orm for DACKn and TENDn when activ e l[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 934 of 982 REJ09B0023-0400 25.3.6 Burst ROM Read Cycle T1 t AD1 t RSD t RDS3 t RSD t CSD1 t AS Tw Tw x T 2 B Tw b T2B t AD2 t AD2 t CSD1 CKIO A25 to A0 CSn RD/ WR D31 to D0 WEn BS RD WAIT Note: * W a vef orm for DACKn and TENDn when activ e low is selected. DACKn , TENDn * t AD1 t [...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 935 of 982 REJ09B0023-0400 25.3.7 Synchronous DRAM Timing Tc1 T r Tcw Td1 Tde t AD1 t AD1 t CSD1 t AD1 t RWD 1 t RWD 1 t CSD1 t AD1 t AD1 t AD1 t RDH2 t RDS2 CKIO A25 to A0 CSn RD/ WR A12/A11 * 1 D31 to D0 t RASD1 t RASD1 RASU/L Row address ReadA command Column address t CASD1 t C[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 936 of 982 REJ09B0023-0400 Tr w T r Tc1 Tcw Td1 Tde T ap t AD1 t AD1 t CSD1 t AD1 t RWD 1 t RWD1 t CSD1 t AD1 t AD1 t AD1 t RDH2 t RDS2 CKIO A25 to A0 CSn RD/ WR A12/A11 * 1 D31 to D0 t RASD1 t RASD1 RASU/L Row address ReadA command Column address t CASD1 t CASD1 CASU/L t BSD t BSD[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 937 of 982 REJ09B0023-0400 TC1 TC2 Td1 Td2 Td3 Td4 T r Tc3 Tc4 Tde t AD1 t AD1 t CSD1 t AD1 t AD1 t AD1 t AD1 t RWD1 t RWD1 t CSD1 t AD1 t AD1 t AD1 t AD1 t RDH2 t RDS2 CKIO A25 to A0 CSn RD/ WR A12/A11 * 1 D31 to D0 t RASD1 t RASD1 RASU/L Row address ReadA command Read command Co[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 938 of 982 REJ09B0023-0400 Tc1 Tc2 Td1 Td2 Td3 Td4 T r T rw Tc3 Tc4 Tde t AD1 t AD1 t CSD1 t AD1 t AD1 t AD1 t AD1 t RWD 1 t RWD1 t CSD1 t AD1 t AD1 t AD1 t AD1 t RDH2 t RDS2 CKIO A25 to A0 CSn RD/ WR A12/A11 * 1 D31 to D0 t RASD1 t RASD1 RASU/L Row address Read command Column addr[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 939 of 982 REJ09B0023-0400 Tr w l T r Tc1 t AD1 t CSD1 t AD1 t AD1 t RWD 1 t RWD1 t RWD1 t CSD1 t AD1 t AD1 t AD1 CKIO A25 to A0 CSn RD/ WR A12/A11 * 1 D31 to D0 t RASD1 t RASD1 RASU/L Row address WriteA command Column address t CASD1 t CASD1 CASU/L t BSD t BSD (High) BS CKE t DQM[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 940 of 982 REJ09B0023-0400 Tr w T c 1 Tr w l Tr Tr w t AD1 t CSD1 t AD1 t AD1 t RWD1 t RWD1 t RWD1 t CSD1 t AD1 t AD1 t AD1 CKIO A25 to A0 CSn RD/ WR A12/A11 * 1 D31 to D0 t RASD1 t RASD1 RASU/L Row address WriteA command Column address t CASD1 t CASD1 CASU/L t BSD t BSD (High) BS [...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 941 of 982 REJ09B0023-0400 Tc2 Tc3 Tc4 T rwl T r Tc1 t AD1 t CSD1 t AD1 t AD1 t AD1 t AD1 t AD1 t RWD 1 t RWD 1 t RWD1 t CSD1 t AD1 t AD1 t AD1 t AD1 CKIO A25 to A0 CSn RD/ WR A12/A11 * 1 D31 to D0 t RASD1 t RASD1 RASU/L Row address WriteA command WRIT command Column address t CAS[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 942 of 982 REJ09B0023-0400 Tc2 Tc3 Tc4 T rwl T r Tc1 Tr w t AD1 t CSD1 t AD1 t AD1 t AD1 t AD1 t AD1 t RWD1 t RWD 1 t RWD1 t CSD1 t AD1 t AD1 t AD1 t AD1 CKIO A25 to A0 CSn RD/ WR A12/A11 * 1 D31 to D0 t RASD1 t RASD1 RASU/L Row address WriteA command WRIT command Column address t [...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 943 of 982 REJ09B0023-0400 Tc3 Tc4 Tde T r Tc2 Td1 Td2 Td3 Td4 Tc1 t CSD1 t AD1 t AD1 t AD1 t AD1 t AD1 t AD1 t RWD 1 t RWD1 t CSD1 t AD1 t AD1 t AD1 t RASD1 t RASD1 Row address Read command Column address t CASD1 t CASD1 t BSD t BSD (High) t DQMD1 t DQMD1 t DACD t DA CD t RDH2 t [...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 944 of 982 REJ09B0023-0400 Tc2 Tc4 Tde Tc1 Tc3 Td1 Td2 Td3 Td4 t CSD1 t AD1 t AD1 t AD1 t RWD1 t RWD1 t CSD1 t AD1 t AD1 t RASD1 Read command Column address t CASD1 t CASD1 t BSD t BSD (High) t DQMD1 t DQMD1 t DACD t DACD t RDH2 t RDS2 t RDH2 t RDS2 CKIO A25 to A0 CSn RD/ WR A12/A1[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 945 of 982 REJ09B0023-0400 Tc3 Tc4 Tde Tc2 Td1 Td2 Td3 Td4 Tc1 Tr Tr w Tp t CSD1 t AD1 t AD1 t AD1 t AD1 t AD1 t AD1 t RWD1 t RWD1 t RWD1 t CSD1 t AD1 t AD1 t AD1 t AD1 t RASD1 t RASD1 t RASD1 t RASD1 Read command Column address Row address t CASD1 t CASD1 t BSD t BSD (High) t DQM[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 946 of 982 REJ09B0023-0400 CKIO A25 to A0 CSn RD/ WR A12/A11 * 1 D31 to D0 RASU/L CASU/L BS CKE DQMxx DACKn * 2 Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Tc2 Tc3 Tc4 T r Tc1 t AD1 t CSD1 t AD1 t AD1 t AD1 t AD1 t[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 947 of 982 REJ09B0023-0400 Tc2 Tc3 Tc4 Tnop Tc1 t AD1 t CSD1 t AD1 t AD1 t AD1 t AD1 t RWD 1 t RWD1 t RWD1 t CSD1 t AD1 t AD1 t AD1 Write command Column address t CASD1 t CASD1 t BSD t BSD (High) t DQMD1 t DQMD1 t DACD t DACD t WDH2 t WDD2 t WDH2 t WDD2 CKIO A25 to A0 CSn RD/ WR A[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 948 of 982 REJ09B0023-0400 Tc2 Tc3 Tc4 Tr Tpw Tp Tc1 t AD1 t CSD1 t AD1 t AD1 t AD1 t RWD1 t RWD 1 t RWD 1 t RWD 1 t CSD1 t RASD1 t RASD1 t RASD1 t RASD1 t AD1 t AD1 t AD1 t AD1 Writecommand Row address t AD1 t AD1 Column address t CASD1 t CASD1 t BSD t BSD (High) t DQMD1 t DQMD1 t[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 949 of 982 REJ09B0023-0400 Tr c Tr c Tr r Tpw Tp T rc t CSD1 t AD1 t AD1 t RWD1 t RWD1 t RWD1 t CSD1 t CSD1 t CSD1 t RASD1 t RASD1 t RASD1 t RASD1 t AD1 t AD1 t CASD1 t CASD1 (High) (Hi-Z) * 3 CKIO A25 to A0 CSn RD/ WR A12/A11 * 1 D31 to D0 RASU/L CASU/L BS CKE DQMxx DACKn * 2 Not[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 950 of 982 REJ09B0023-0400 Tr c Tr c Tr c Tr c Tr r Tpw Tp t CSD1 t AD1 t AD1 t RWD 1 t RWD 1 t RWD1 t CSD1 t CSD1 t CSD1 t RASD1 t RASD1 t RASD1 t RASD1 t AD1 t AD1 t CASD1 t CASD1 (Hi-Z) * 3 t CKED1 t CKED1 CKIO A25 to A0 CSn RD/ WR A12/A11 * 1 D31 to D0 RASU/L CASU/L BS CKE DQMx[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 951 of 982 REJ09B0023-0400 T rc T rc T rc Tmw Tde Tr r Tr r Tpw Tp T rc t CSD1 t AD1 t AD1 t AD1 P ALL REF REF MRS t RWD1 t R WD1 t RWD 1 t CSD1 t CSD1 t CSD1 t RASD1 t RASD1 t RASD1 t RASD1 t AD1 t AD1 t CASD1 t CASD1 (Hi-Z) * 3 t CSD1 t CSD1 t RASD1 t RASD1 t CASD1 t CASD1 t CSD[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 952 of 982 REJ09B0023-0400 T r Tc Tnop T rw1 T ap Ta p Tde Td1 Tc Tr t AD3 t AD3 CKIO A25 to A0 CSn RD/ WR A12/A11 * 1 D31 to D0 RASU/L CASU/L BS CKE DQMxx DACKn, TENDn * 2 t AD3 t AD3 t AD3 t AD3 Row address Column address t AD3 t AD3 t AD3 t AD3 t AD3 t AD3 t AD3 t CSD2 t RWD2 t [...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 953 of 982 REJ09B0023-0400 Tr c Tr c Tr c Tr r Tpw Tp (Hi-Z) * 3 t AD3 t AD3 t CSD2 t CSD2 t CSD2 t CSD2 t CASD2 t DQMD2 t CASD2 t CASD2 t RASD2 t CKED2 t CKED2 t RASD2 t RASD2 t RWD2 t RWD2 t RASD2 t AD3 t AD3 CKIO A25 to A0 CSn RD/ WR A12/A11 * 1 D31 to D0 RASU/L CASU/L BS CKE D[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 954 of 982 REJ09B0023-0400 25.3.8 Peripheral Mo dule Signal Timing Table 25.9 Peripheral Module Signal Timing Conditions : V CC Q = 3.0 V to 3.6 V, V CC = 1.8 V ± 5%, AV CC = 3. 0 V to 3. 6 V, V SS = V SS Q = AV SS = 0 V, Ta = − 40°C to + 85°C Module Item Symbol Min. Max. Unit[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 955 of 982 REJ09B0023-0400 t Scyc t TXD SCK TxD (data transmission) RxD (data reception) t RXH t RXS Figure 25.43 SCIF In put/Output Timing in Synchron ous Mode t PORTS CKIO Ports 7 to 0 (read) Ports 7 to 0 (write) t PORTH t PORTD Figure 25.44 I/O Port Timing t DRQS t DRQH CKIO DR[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 956 of 982 REJ09B0023-0400 25.3.9 Multi Function Timer Pulse U nit Timing Table 25.10 lists the multi function timer pulse unit timing. Table 25.10 Multi Function Timer Pulse Uni t Timing Conditions : V CC = 1.8 V ± 5%, V CC Q = AV CC = 3.0 V to 3.6 V, V SS = V SS Q = AV SS = 0 V,[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 957 of 982 REJ09B0023-0400 25.3.10 POE Module Signal Timing Table 25.11 Output Enable (POE ) Timing Conditions : V CC = 1.8 V ± 5%, V CC Q = AV CC = 3.0 V to 3.6 V, V SS = V SS Q = AV SS = 0 V, Ta = − 40°C to + 85°C Item Symbol Min. Max. Unit Figure(s) POE input setup time t [...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 958 of 982 REJ09B0023-0400 25.3.11 I 2 C Module Si gnal Ti ming Table 25.12 I 2 C Bus Interface Timing Normal Conditions: V CC = 1.8 V ± 5%, AV CC = V CC Q = 3.0 V to 3.6 V, V SS = AV SS = V SS Q = 0 V, Ta = − 40°C to + 85°C Specifications Item Symbol Test Conditions Min. Typ.[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 959 of 982 REJ09B0023-0400 SCL V IH V IL t ST AH t BUF P * S * t SF t SR t SCL t SDAH t SCLH t SCLL SD A Sr * t ST AS t SP t STOS t SDAS P * [Legend] S: Start condition P: Stop condition Sr: Start condition for retransmission Figure 25.50 I 2 C Bus Interface Input/Output Timing[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 960 of 982 REJ09B0023-0400 25.3.12 H-UDI Related Pin Timin g Table 25.13 H-UDI Related Pin Timin g Conditions : V CC Q = 3.0 V to 3.6 V, V CC = 1.8 V ± 5%, AV CC = 3. 0 V to 3. 6 V, V SS = V SS Q = AV SS = 0 V, Ta = − 40°C t o + 85°C Item Symbol Min. Max. Unit Figure(s) TCK cy[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 961 of 982 REJ09B0023-0400 t TRSTS t TRSTH TRST R ESETP Figure 25.52 TRST Input Timing (Reset-Hold State ) TCK TMS TDI TDO When boundary scan is not performed When boundary scan is performed t TDIS t TDIH t TCKcyc t TMSS t TMSH t TDOD t TDOD Figure 25.53 H-UDI Data Transfer Timing[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 962 of 982 REJ09B0023-0400 25.3.13 USB Module Signal Timing Table 25.14 USB Module Clock Timing Conditions : V CC = 1.8 V ± 5%, V CC Q = 3.0 V to 3.6 V, AV CC = 3.0 V to 3.6 V, V SS = V SS Q = AV SS = 0 V, Ta = − 40°C to + 85°C Item Symbol Min. Max. Unit Figure(s) Frequency (4[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 963 of 982 REJ09B0023-0400 25.3.14 USB Transceiver Timing Table 25.15 USB Transceiver Timing Conditions : V CC = 1.8 V ± 5%, V CC Q = 3.0 V to 3.6 V, AV CC = 3.0 V to 3.6 V, V SS = V SS Q = AV SS = 0 V, Ta = − 40°C to + 85°C Item Symbol Min. Typ. Max. Unit Test Conditions Ris[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 964 of 982 REJ09B0023-0400 25.3.15 AC Characteristi cs Measurement Conditio ns • I/O signal reference level: V CC Q/2 (V CC Q = 3.0 to 3.6 V, V CC = 1.8 V ± 5%) • Input pu lse level: V SS Q to 3.0 V (where RESETP , RESETM , ASEMD0 , NMI , TRST , EXTAL , CKIO, TCK, MD0, MD2, MD[...]

Section 25 Electric al Characteristics Rev. 4. 00 Sep. 14, 2005 Page 965 of 982 REJ09B0023-0400 25.4 A/D Conver ter Characteristics Table 25.16 lists the A/D converter characteristics. Table 25.16 A/D Converter Characteristics Conditions : V CC Q = 3.0 to 3.6 V, V CC = 1.8 V ± 5%, AV CC = 2.7 V t o 3.6 V, V SS Q = V SS = AV SS = 0 V, Ta = − 40 ?[...]

Section 25 Electric al Characteristics Rev. 4.00 Sep. 14, 2005 Page 966 of 982 REJ09B0023-0400[...]

Appendix Rev. 4. 00 Sep. 14, 2005 Page 967 of 982 REJ09B0023-0400 Appendix A. Pin States A.1 When Other Function is Selected Table A.1 Pin States in Reset State, P ower Down Mode, and Bus-Release d States When Other Function is Selected Reset State Power Down Mode Type Pin Name Power-On Manual Software Standby Sleep Bus- Released Reset Clock EXTAL [...]

Appendix Rev. 4.00 Sep. 14, 2005 Page 968 of 982 REJ09B0023-0400 Reset State Power Down Mode Type Pin Name Power-On Manual Software Standby Sleep Bus- Released Reset Data bus D[15:0] Z I Z I Z D[31:16] Z+ I+ Z+ I+ Z+ * 6 Bus control CS0 H O Z/H * 3 O Z CS6[A,B] CS5[A,B] CS[2:4] Z+ O Z+/H * 3 O Z+ BS H O Z/H * 3 O Z CAS[U,L] RAS[U,L] Z+ O O/Z+ * 2 O[...]

Appendix Rev. 4. 00 Sep. 14, 2005 Page 969 of 982 REJ09B0023-0400 Reset State Power Down Mode Type Pin Name Power-On Manual Software Standby Sleep Bus- Released Reset SCIF[2:0] RxD[2:0] Z+ I+ Z+ I+ I+ TxD[2:0] Z+ O/Z+ O/Z+ * 4 O/Z+ O/Z+ SCK[2:0] Z+ I+/O K/Z+ * 4 I+/O I+/O RTS[2:0] Z+ I+/O K/Z+ * 4 I+/O I+/O CTS[2:0] Z+ I+/O K/Z+ * 4 I+/O I+/O AUD A[...]

Appendix Rev. 4.00 Sep. 14, 2005 Page 970 of 982 REJ09B0023-0400 [Legend] I: Input I+: Input with weak keeper I++: Input with pull-up MOS O: Output L: Low level output H: High level output Z: Hi-Z (The pin must not be open since the int e rmediate level at this pin caused a pass th ough current in the LSI.) Z+: Hi-Z with weak keeper Z++: Hi-Z with [...]

Appendix Rev. 4. 00 Sep. 14, 2005 Page 971 of 982 REJ09B0023-0400 A.2 When I/O Port is Selected Table A.2 Pin States in Reset State, P ower Down Mode, and Bus-Release d States When I/O Port is Selected Reset State Power Down Mode Pin Name Power-On Manual Software Standby Sleep Bus-Released Reset PTA[14:0] Z+ I+/O Z+/K * I+/O I+/O PTB[8:0] Z+ I+/O Z[...]

Appendix Rev. 4.00 Sep. 14, 2005 Page 972 of 982 REJ09B0023-0400 B. Product Lineup Product Model Package (Code) SH7641 HD64 17641BP100 (100 MHz version) P-LFBGA1717-256 * Note: * For details of p ackages, please contac t your nearest Renesas Techno logy sales representative.[...]

Appendix Rev. 4. 00 Sep. 14, 2005 Page 973 of 982 REJ09B0023-0400 C. Package Dimensions Package Code JEDEC JEITA P-LFBGA-1717-256 – – 0.35 to 0.45 0.20 0.15 C C 0.15 (4 × ) C 1.40 Max φ 0.08 φ 0.15 φ 0.44 to 0.64 (256 × ) M C M C A B 0.80 B A A1 CORNER 20 19 A B C D E F G H J K L M N P R T U V W Y 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2[...]

Appendix Rev. 4.00 Sep. 14, 2005 Page 974 of 982 REJ09B0023-0400[...]

Rev. 4. 00 Sep. 14, 2005 Page 975 of 982 REJ09B0023-0400 Main Revisions and Add itions in this Edition Item Page Revisions (S ee Manual for Details) General Precautions on Handling of Product iv 5. added. Section 9 Exception Handling 9.5 Note on Initializing this LSI 217 ; MOV.W #H'FF40,R10; MOV.L #H'A4FC0000,R8; MOV #H'10,R9; MOV.B [...]

Rev. 4.00 Sep. 14, 2005 Page 976 of 982 REJ09B0023-0400 Item Page Revisions (S ee Manual for Details) Section 25 Electrical Characteristics Figure 25.37 Synchronous DRAM Auto-Refreshing Timing (WTRP = 1 Cycle, WTRC = 3 Cycles) Figure 25.38 Synchronous DRAM Self-Refreshing Timing (WTRP = 1 Cycle) Figure 25.39 Synchronous DRAM Mode Register Write Tim[...]

Rev. 4. 00 Sep. 14, 2005 Page 977 of 982 REJ09B0023-0400 Index Numerics 16-Bit/32-Bit di splacement ....................... 47 A A/D conversion tim e ............................... 810 A/D converter ......................................... 797 A/D Converter Characteristics ................ 965 Absolute addresses ..................................[...]

Rev. 4.00 Sep. 14, 2005 Page 978 of 982 REJ09B0023-0400 Direct Memory Access Contr oller .......... 405 Divider .................................................... 145 DMA address error ................................. 209 DSP addressing ....................................... 124 DSP data instructions................................ 84 DSP opera[...]

Rev. 4. 00 Sep. 14, 2005 Page 979 of 982 REJ09B0023-0400 Multiply and accumulate high register ..... 26 Multiply and accumulate low register....... 26 Multiply/multiply-and -accumulate operations ................................................. 45 N NMI interrupt.......................................... 233 Noise canceler.........................[...]

Rev. 4.00 Sep. 14, 2005 Page 980 of 982 REJ09B0023-0400 ICDRS ................................................ 487 ICDRT ................................................ 487 ICIER.................................................. 482 ICMR .................................................. 480 ICR ....................................................[...]

Rev. 4. 00 Sep. 14, 2005 Page 981 of 982 REJ09B0023-0400 USBEPDR0i ....................................... 756 USBEPDR0o ...................................... 756 USBEPDR0s....................................... 757 USBEPSTL......................................... 763 USBEPSZ0o ....................................... 758 USBEPSZ1 ................[...]

Rev. 4.00 Sep. 14, 2005 Page 982 of 982 REJ09B0023-0400 X X/Y data addressing.................................. 52 X/Y memory ........................................... 193[...]

Renesas 32-Bit RISC Microcomputer Hardware Manual SH7641 Publication Date: Rev.1.00 Sep 19, 2003 Rev.4.00 Sep 14, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.  2005. Renesas Technology Corp., All rights reserved. Printe[...]

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Refer to " http://www.renesas.com/en/network " for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) [...]

[...]

SH7641 Hardware Manual[...]