Siemens S7-300 manual

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Table of contents for the manual

  • Page 1

    Preface Guide to the S7-300 documentation 1 Operating and display elements 2 Communication 3 Memory concept 4 Cycle and reaction times 5 Technical data of CPU 31xC 6 Technical data of CPU 31x 7 Appendix A SIMATIC S7-300 CPU 31xC and CPU 31x, Technical data Manual Edition 08/2004 A5E00105475-05 This manual is part of t he documentation package with [...]

  • Page 2

    Safety Guidelines This manual contains notices which y ou should observe to ensure your own persona l safe ty as well as to avoid property damage. The notices ref erring to your per sonal safety are highlighted in the manu al by a safety alert symbol, notices referring to pr operty damage only hav e no safet y alert symbol. Danger indicates an immi[...]

  • Page 3

    CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 iii Preface Purpose of the Manual This manual contains all the informatio n you will need concerni ng the configuration, communication, memory concept, cyc le, response times and techni cal data for the CPUs. You will then learn the points to conside r when upgrading to on[...]

  • Page 4

    Preface CPU 31xC and CPU 31x, Technical data iv Manual, Edition 08/2004, A5E00105475-05 Note There you can obtain the descri ptions of all current modules. F or new modules, or modules of a more recent version, we re serve the right to include a Pro duct Information containing latest information. Approvals The SIMATIC S7-300 product serie s has the[...]

  • Page 5

    Preface CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 v Documentation classification This manual is part of the S7-3 00 documentation package. Name of the manual Description YOU ARE READING the Manual • CPU 31xC and CPU 31x, Technical dat a Control and display eleme nts, communication, memory concept, cycle and resp[...]

  • Page 6

    Preface CPU 31xC and CPU 31x, Technical data vi Manual, Edition 08/2004, A5E00105475-05 Additional information required: Name of the manual Description Reference Manua l System software for S7 -300/400 system and standard functions Description of the SFCs, SFBs and OBs. This manual is part of the STEP 7 documentation package. For further informatio[...]

  • Page 7

    CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 vii Table of contents Preface ....................................................................................................................... ............................... iii 1 Guide to the S7- 300 document ation .................................................[...]

  • Page 8

    Table of contents CPU 31xC and CPU 31x, Technical data viii Manual, Edition 08/2004, A5E00105475-05 4 Memory concept ............................................................................................................... ...................... 4-1 4.1 Memory areas and retentivity .............................................................[...]

  • Page 9

    Table of contents CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 ix 6.5 CPU 314C-2 PtP and CPU 314C-2 DP ................................................................................... 6-21 6.6 Technical data of the int egrated I/O ....................................................................................[...]

  • Page 10

    Table of contents CPU 31xC and CPU 31x, Technical data x Manual, Edition 08/2004, A5E00105475-05 Tables Table 1-1 Application ar ea covered by this ma nual ...................................................................................... ii i Table 1-1 Ambient influence on the au tomation syste m (AS) ..........................................[...]

  • Page 11

    Table of contents CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 xi Table 4-1 Retentivity of the RAM ......................................................................................................... ...... 4-2 Table 4-2 Retentive behavi or of memory objects (applies to all CPUs with DP/MPI-SS (31x-2 P N/DP) .. [...]

  • Page 12

    Table of contents CPU 31xC and CPU 31x, Technical data xii Manual, Edition 08/2004, A5E00105475-05 Table 7-1 Availabl e MMCs ................................................................................................................. ........ 7-2 Table 7-2 Maximum number of loadab le blocks on the MMC ..........................................[...]

  • Page 13

    CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 1-1 Guide to the S7-300 documentation 1 Overview There you find a guide leading you through the S7-300 docume nta tion. Selecting and configuring Table 1-1 Ambient influence on the automation system (AS) Information on.. is available in ... What provisions do I have to mak[...]

  • Page 14

    Guide to the S7-300 documentation CPU 31xC and CPU 31x, Technical data 1-2 Manual, Edition 08/2004, A5E00105475-05 Table 1-3 Communication between sensors/actuators and the PLC Information on.. is available in ... Which module is suitable for my sensor/actuator? For CPU: CPU 3 1xC and CPU 31x Manual, Technical Data For signal modules: Referenc e ma[...]

  • Page 15

    Guide to the S7-300 documentation CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 1-3 Table 1-6 CPU performance Information on.. is available in ... Which memory concept is best sui ted to my applic ation? CPU 31xC and CPU 31x Man ual, Technical Data How do I insert and remove Micro Memory Cards? S7-300, CPU 31xC and CP[...]

  • Page 16

    Guide to the S7-300 documentation CPU 31xC and CPU 31x, Technical data 1-4 Manual, Edition 08/2004, A5E00105475-05 Table 1-9 Supplementary features Information on.. is available in ... How to implement monitor and modify functions (Human Machine Interface) For text-based displays: The relevant Man ual For Operator Panels: The relevant Manual For Wi[...]

  • Page 17

    CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 2-1 Operating and display elements 2 2.1 Operating and display elements: CPU 31xC Operating and display elements of CPU 31xC SF BF DC5V RUN STOP RUN STOP MRES FRCE X1 X2 X11 X12 MMC 1 2 3 4 5 6 7 The figures show the following CPU el ements (1) Status and error displays (2[...]

  • Page 18

    Operating and display elements 2.1 Operating and display element s: CPU 31xC CPU 31xC and CPU 31x, Technical data 2-2 Manual, Edition 08/2004, A5E00105475-05 The figure below illustrates t he integrated digital and analog I/Os of the CPU with open front covers. SF BF DC5V FRCE RUN STOP RUN STOP MRES X11 X12 2 2 1 3 1 2 3 Figure 2-1 Integrated I/Os [...]

  • Page 19

    Operating and display ele ments 2.1 Operating and display elements: CP U 31xC CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 2-3 Mode selector switch Use the mode selector switch to set the CPU operating mode. Table 2-1 Positions of the mode selector switch Position M eaning Description RUN RUN mode The CPU execut es t[...]

  • Page 20

    Operating and display elements 2.1 Operating and display element s: CPU 31xC CPU 31xC and CPU 31x, Technical data 2-4 Manual, Edition 08/2004, A5E00105475-05 2.1.1 Status and Error Indicators: CPU 31xC LED designa tion Color Meaning SF red Hardware or software error BF (for CPUs with DP interface only) red Bus error DC5V green 5-V power for CP U an[...]

  • Page 21

    Operating and display ele ments 2.2 Operating and display elements: CP U 31x CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 2-5 2.2 Operating and display elements: CPU 31x 2.2.1 Operating and display el ements: CPU 312, 314, 315-2 DP: Operating and display elements SF BF DC5V RUN STOP RUN STOP MRES FRCE X2 X1 MMC 1 2 3[...]

  • Page 22

    Operating and display elements 2.2 Operating and display elements: CP U 31x CPU 31xC and CPU 31x, Technical data 2-6 Manual, Edition 08/2004, A5E00105475-05 Slot for the SIMATIC Micro Memory Card (MMC) A SIMATIC Micro Memory Card (MMC ) is used as memory module. You can use MMCs as load memory and as portable storage me dium. Note These CPUs do not[...]

  • Page 23

    Operating and display ele ments 2.2 Operating and display elements: CP U 31x CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 2-7 2.2.2 Operating and displa y elements: CPU 317-2 DP Operating and display elements RUN STOP MRES BF1 BF2 SF DC5V FRCE RUN STOP X2 X1 MMC 1 2 3 4 5 6 7 The figures show the following CPU el eme[...]

  • Page 24

    Operating and display elements 2.2 Operating and display elements: CP U 31x CPU 31xC and CPU 31x, Technical data 2-8 Manual, Edition 08/2004, A5E00105475-05 Slot for the SIMATIC Micro Memory Card (MMC) A SIMATIC Micro Memory Card (MMC ) is used as memory module. You can use MMCs as load memory and as portable storage me dium. Note These CPUs do not[...]

  • Page 25

    Operating and display ele ments 2.2 Operating and display elements: CP U 31x CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 2-9 2.2.3 Operating and display elements: CPU 31x-2 PN/DP Operating and display elements RUN STOP MRES BF1 SF DC5V FRCE RUN STOP X1 LINK RX / TX MAC-ADD.: X1-X2-X3 X4-X5-X6 X2 BF2 MMC 1 2 3 4 5 6 [...]

  • Page 26

    Operating and display elements 2.2 Operating and display elements: CP U 31x CPU 31xC and CPU 31x, Technical data 2-10 Manual, Edition 08/2004, A5E00105475-05 Slot for the SIMATIC Micro Memory Card (MMC) A SIMATIC Micro Memory Card (MMC ) is used as memory module. You can use MMCs as load memory and as portable storage me dium. Note These CPUs do no[...]

  • Page 27

    Operating and display ele ments 2.2 Operating and display elements: CP U 31x CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 2-11 2.2.4 Status and error displays of the CPU 31x General status and error displays Table 2-6 General status and er ror displays of the CPU 31x LED designa tion Color Meani ng SF red Hardware or[...]

  • Page 28

    Operating and display elements 2.2 Operating and display elements: CP U 31x CPU 31xC and CPU 31x, Technical data 2-12 Manual, Edition 08/2004, A5E00105475-05[...]

  • Page 29

    CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 3-1 Communication 3 3.1 Interfaces 3.1.1 Multi-Point Interface (MPI) Availability All CPUs described in this manual are equipped with an MPI interface X1. A CPU equipped with an MPI/DP inte rface is configured and su ppl ied as MPI. To use the DP interface, set DP interfac[...]

  • Page 30

    Communication 3.1 Interfaces CPU 31xC and CPU 31x, Technical data 3-2 Manual, Edition 08/2004, A5E00105475-05 Devices capable of MPI communication • PG/PC • OP/TP • S7-300 / S7-400 with MPI interface • S7-200 (19.2 kbps only) 3.1.2 PROFIBUS DP Availability CPUs with “DP“ name suffix are equipped at least with a DP X2 i nterface. The 315[...]

  • Page 31

    Communication 3.1 Interfaces CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 3-3 Note (for DP interface in slave mode only) When you disable the Commissioning / Debug mode / Routing check box in the DP interface properties dialog in STEP 7, all user-specific transmi ssion rat e settings will be ignored, and the transmis[...]

  • Page 32

    Communication 3.1 Interfaces CPU 31xC and CPU 31x, Technical data 3-4 Manual, Edition 08/2004, A5E00105475-05 Devices capable of PROFINET (PN) communication • PROFINET IO components (for exa mple, interface module IM 151-3 PN in an ET 200S) • S7-300 / S7-400 with PROFINET inte rface (for exa mple, CPU 317-2 PN/DP or CP 343-1 PN) • Active netw[...]

  • Page 33

    Communication 3.1 Interfaces CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 3-5 3.1.4 Point to Point (PtP) Availability CPUs with a “PtP“ name suffix are equipped with a PtP X2 interf ace. Properties Using the PtP interface of your CPU, you can connect external d evices with serial interface. You can operate such a[...]

  • Page 34

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data 3-6 Manual, Edition 08/2004, A5E00105475-05 3.2 Communication services 3.2.1 Overview of communication services Selecting the communication service You need to decide on a communi cation service, based on functio nality requirements. Your choice of communication servi c [...]

  • Page 35

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 3-7 See also Distribution and availability o f S7 connection resources (Page 3-29) Connection resources fo r routing (Page 3-31) 3.2.2 PG communication Properties PG communication is used to exch ang e data between engineering s ta[...]

  • Page 36

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data 3-8 Manual, Edition 08/2004, A5E00105475-05 Reference • Details on SFCs are found in the Instruct ion list , for more details refer to the STEP 7 Online Help or to the System and Standard Functions Reference Manual . • For further information on communicatio n, refer[...]

  • Page 37

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 3-9 3.2.6 Global data commu nication (MPI only) Properties Global data communication is used for cycli c exchange of global data via MPI subnets (for example, I, Q, M) between SIMATIC S7 CPUs (data exchange withou t acknowledgement[...]

  • Page 38

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data 3-10 Manual, Edition 08/2004, A5E00105475-05 GD resources of the CPUs Table 3-4 GD resources of the CPUs Parameters CPU 31xC, 312, 314 CPU 315- 2 DP, 315-2 PN/DP, 317 Number of GD circuits per CPU Max. 4 Max. 8 GD packets transmitted per GD circuit Max. 1 Max. 1 GD packe[...]

  • Page 39

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 3-11 Routing network nodes: MPI - DP Gateways between subnet s are rout ed in a SIMATIC station that i s equipped with interfaces to the respective subnets. The fi gure below shows CPU 1 (DP mas ter) acting as router for subnets 1 [...]

  • Page 40

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data 3-12 Manual, Edition 08/2004, A5E00105475-05 Routing network nodes: MPI – DP - Ethernet CPU 1 (e.g. 315-2 DP) PN Subnet 3 (PROFInet) PN PG Subnet 2 (PROFIBUS) DP (master) MPI Subnet 1 (MPI) MPI/DP (active slave) CPU 2 (317-2 PN/DP) CPU 3 (317-2 PN/DP) Number of routed [...]

  • Page 41

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 3-13 Requirements • The station modules are "capabl e of routing" (CPUs o r CPs). • The network configuration doe s not exceed project limits. • The modules have loaded the conf iguration data containing the l atest[...]

  • Page 42

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data 3-14 Manual, Edition 08/2004, A5E00105475-05 Routing: Example of a TeleService application The figure below shows the exampl e of an application for remote maintenance of an S7 station using a PG. The connec tion to other subnets is here established via modem connectio n[...]

  • Page 43

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 3-15 Reference • on configuring in STEP 7 is found in the Configuring Hardware and Conne ctions in STEP 7 manual • of a basic nature is contain ed in the Communication with SIMATIC Manual. • on the TeleService adapter can be [...]

  • Page 44

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data 3-16 Manual, Edition 08/2004, A5E00105475-05 3.2.9 Data consistency Properties A data area is considered consistent, if the operating system c an read/write access the data area in a continuous blo ck. Dat a exchanged collectively between the stations should belong toget[...]

  • Page 45

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 3-17 Objectives in PROFINET The objectives in PROFINET are: • An open Ethernet standard for aut omation based on Industri al Ethernet Industrial Ethernet and standard Ethernet components ca n be use d together, however, Industria[...]

  • Page 46

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data 3-18 Manual, Edition 08/2004, A5E00105475-05 Extent of PROFINET CBA and PROFINET IO PROFINET IO and CBA r epresent two different v iews of automation devices on Industrial Ethernet. 352),1(7 &RPSRQHQW9LHZ 352),1(7&%$ ,2'DWD9LHZ 352),1(7,[...]

  • Page 47

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 3-19 3.2.10.1 PROFINET IO System Extended Functions of PROFINET IO The following graphic shows the new fu nctions of PROFINET IO &38 [ 31'3 (7 '36/$9( 5RXWHU 6ZLWFK ,2?[...]

  • Page 48

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data 3-20 Manual, Edition 08/2004, A5E00105475-05 Requirements • CPUs as of Firmware 2.3.0 (for example CPU 315-2 PN/DP) • STEP 7, as of Version 5.3 + Service Pack 1 Reference You will find information on the topic of PROFINET in the follo wing sources: • in the System [...]

  • Page 49

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 3-21 Comparison of the System and Standard Functions of PROFINET IO and PROFIBUS DP For CPUs with an integrated PRO FINET interface, the table below provides you with an overview of: • System and standard functions for SIMATIC th[...]

  • Page 50

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data 3-22 Manual, Edition 08/2004, A5E00105475-05 The following table provides you with an ove rview of the system and standard functions for SIMATIC, whose functionality mus t be implemented by other funct ions whe n converting from PROFIBUS DP to PROFINET IO. Table 3-7 Syst[...]

  • Page 51

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 3-23 3.2.10.3 System status lists (SSLs) in PROFINET IO Chapter Content This chapter explain s the following: • Which SSLs are intended f or PROFINET • Which SSLs are intended for PRO FIBUS DP • Which SSLs are intended f or b[...]

  • Page 52

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data 3-24 Manual, Edition 08/2004, A5E00105475-05 Detailed Information For detailed descriptions of the individual system status lists , refer to the manual System Software for S7-300/400 System and Standa rd Functions . 3.2.10.4 Open communication via Industrial Ethernet Req[...]

  • Page 53

    Communication 3.2 Communication servi ces CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 3-25 Establishing a connection for communication FB 65 "TCON" establishes communi cation between t he CPU and a co mmunication partner. You can establish up to eight c onnections. The CPU automaticall y monitors and holds[...]

  • Page 54

    Communication 3.3 S7 connections CPU 31xC and CPU 31x, Technical data 3-26 Manual, Edition 08/2004, A5E00105475-05 3.2.10.5 SNMP communication service Availability The SNMP communication service i s available for CPUs with integ rated PROFINET interface and Firmware 2.3.0 or higher. Properties SNMP (Simple Network Management Protocol) is a standard[...]

  • Page 55

    Communication 3.3 S7 connections CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 3-27 Connection points An S7 connection between module s with communication capability is established betwe en connection points. The S7 connecti on always ha s two conn ection points: The active and passive connection points: • The activ[...]

  • Page 56

    Communication 3.3 S7 connections CPU 31xC and CPU 31x, Technical data 3-28 Manual, Edition 08/2004, A5E00105475-05 Assigning connections in the program In S7 basic communication, and in open Industrial Ethern et comm unication with TCP/IP, the user program establishes the co nne ction. The CPU operating syst em initiates the connection. S7 basic co[...]

  • Page 57

    Communication 3.3 S7 connections CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 3-29 3.3.3 Distribution and availabi lity of S7 connection resources Distribution of connection resources Table 3-10 Distribution of connections Communication servic e Distribution PG communication OP communication S7 basic communication In[...]

  • Page 58

    Communication 3.3 S7 connections CPU 31xC and CPU 31x, Technical data 3-30 Manual, Edition 08/2004, A5E00105475-05 Availability of connection resources Table 3-11 Availabi lity of connection resources Reserved for CPU Total number connection resources PG communi cation OP communica tion S7 basic communi cation Free S7 connections 312C 6 1 to 5, def[...]

  • Page 59

    Communication 3.3 S7 connections CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 3-31 3.3.4 Connection resources for routing Number of connection resources for routing The CPUs with DP interface pro vi de a different number of connec tion resources for the routing function: Table 3-12 Number of routing conn ection resou[...]

  • Page 60

    Communication 3.4 DPV1 CPU 31xC and CPU 31x, Technical data 3-32 Manual, Edition 08/2004, A5E00105475-05 3.4 DPV1 New automation and process e ngin eering tasks require the range of functions performed by the existing DP protocol to be extended. In addition to cyclical communication functions, acyclical access to non-S7 field devices is another i m[...]

  • Page 61

    Communication 3.4 DPV1 CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 3-33 Interrupt blocks with DPV1 functionality Table 3-13 Interrupt block s with DPV1 functionality OB Functionality OB 40 Process interrupt OB 55 Status interrupt OB 56 Update interrupt OB 57 Vendor-specific interrupt OB 82 Diagnostic interrupt Note [...]

  • Page 62

    Communication 3.4 DPV1 CPU 31xC and CPU 31x, Technical data 3-34 Manual, Edition 08/2004, A5E00105475-05[...]

  • Page 63

    CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 4-1 Memory concept 4 4.1 Memory areas and retentivity 4.1.1 CPU memory areas The three memory areas of your CPU: CPU Loading memory (located on the MMC) Memory of the CPU System memory Working memory MMC Load memory The load memory is located on a Mi cro Memory Ca rd (MMC)[...]

  • Page 64

    Memory concept 4.1 Memory areas and retentivity CPU 31xC and CPU 31x, Technical data 4-2 Manual, Edition 08/2004, A5E00105475-05 System memory The RAM system memory is integr ated in the CPU and cannot be e x panded. It contains • the address areas for address area memory bits, timers and coun ter s • the process image of the I/Os • local dat[...]

  • Page 65

    Memory concept 4.1 Memory areas and retentivity CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 4-3 Retentive data in RAM Therefore, the contents of retentive DBs are always retentive a t restart and POWER ON/OFF. CPUs V2.1.0 or higher also supp ort volatile DBs (the volatile DBs are initialized at restart of POWER OFF-[...]

  • Page 66

    Memory concept 4.1 Memory areas and retentivity CPU 31xC and CPU 31x, Technical data 4-4 Manual, Edition 08/2004, A5E00105475-05 Retentive behavior of a DB for CPUs with firmware >= V2.1.0 For these CPUs you can specify in STEP 7 (beginning with versio n 5.2 + SP 1), or at SFC 82 CREA_DBL (parameter AT TRIB -> N ON_RETAIN bit), whether a DB a[...]

  • Page 67

    Memory concept 4.1 Memory areas and retentivity CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 4-5 4.1.4 Address areas of system memory System memory of the S7 CPUS is o rganized in address are as (ref er to the table below). In a corresponding operation of your user program, you address dat a directly in the relevant [...]

  • Page 68

    Memory concept 4.1 Memory areas and retentivity CPU 31xC and CPU 31x, Technical data 4-6 Manual, Edition 08/2004, A5E00105475-05 Process image update The operating system updates t he process image periodicall y. The figure below shows the sequence of this operation within a cycle. Cycle time Startup PIO PII User program CCP (OS) Startup program Pr[...]

  • Page 69

    Memory concept 4.1 Memory areas and retentivity CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 4-7 Configurable process image with CPU317 (FW V2.3.0 or higher) IN STEP 7, you can define a user-specific size of the I/O proce ss images between 0 to 2048 for a CPU317, FW V2 .3.0 or higher. Note the information below: Note[...]

  • Page 70

    Memory concept 4.1 Memory areas and retentivity CPU 31xC and CPU 31x, Technical data 4-8 Manual, Edition 08/2004, A5E00105475-05 Local data Local data store: • the temporary variables of code bl ocks • the start information of the OBs • transfer parameters • intermediate results Temporary Variables When you create blocks, you can declare te[...]

  • Page 71

    Memory concept 4.1 Memory areas and retentivity CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 4-9 4.1.5 Properties of the Micro Memory Card (MMC) The MMC as memory module for the CPU The memory module used on your CP U is a SIMATIC Micro Memory Ca rd (MMC.) You can use MMCs as load memory or as a portable storage medi[...]

  • Page 72

    Memory concept 4.1 Memory areas and retentivity CPU 31xC and CPU 31x, Technical data 4-10 Manual, Edition 08/2004, A5E00105475-05 MMC copy protection Your MMC has an internal serial n umber that provides copy prote ction at user level. You can read this serial number from the SSL partial list 011 C H index 8 using SFC 51 "RDSYSST." You ca[...]

  • Page 73

    Memory concept 4.2 Memory functions CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 4-11 4.2 Memory functions 4.2.1 General: Memory functions Memory functions Memory functions are used to generate, modify or delete entire user p rograms or s pecific blocks. You can also ensure tha t your project data are retained by arc[...]

  • Page 74

    Memory concept 4.2 Memory functions CPU 31xC and CPU 31x, Technical data 4-12 Manual, Edition 08/2004, A5E00105475-05 Note This function is only permitted when the CPU is in STOP mode. L oad memory is cleared if the load operation could not be completed due to power los s or illegal block data. 4.2.3 Handling with modules 4.2.3.1 Download of new bl[...]

  • Page 75

    Memory concept 4.2 Memory functions CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 4-13 4.2.3.3 Deleting blocks Deleting blocks When you delete a block, it i s deleted from load memory. In STE P 7, you can also delete blocks with the user program (DBs also with SFC 23 "DEL_DB"). R AM used by this block is rel[...]

  • Page 76

    Memory concept 4.2 Memory functions CPU 31xC and CPU 31x, Technical data 4-14 Manual, Edition 08/2004, A5E00105475-05 Restart (warm start) • All retentive DBs retain their ac tual value (non-retentive DB s are also supported by CPUs with Firmware >= V2.1.0 . Non-retentive DBs receive their initia l values). • The values of all retentive M, C[...]

  • Page 77

    Memory concept 4.2 Memory functions CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 4-15 4.2.5 Recipes Introduction A recipe repr esents a colle cti on of user data. You can implemen t a simple recipe co ncept using static DBs. In this case, the rec ipes should have the sam e structure (lengt h). One DB should exist per[...]

  • Page 78

    Memory concept 4.2 Memory functions CPU 31xC and CPU 31x, Technical data 4-16 Manual, Edition 08/2004, A5E00105475-05 Note As a precaution against loss of data, alwa ys make sure that you do not exceed the maximum number of delete/write operations. Also refer to the SI MATIC Micro Memory Card (MMC) section in the "Struc ture and Communication [...]

  • Page 79

    Memory concept 4.2 Memory functions CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 4-17 4.2.6 Measured va lu e log files Introduction Measured values are generated when the CPU executes the user p r ogram. These values are to be logged and analyzed. Processing sequence Acquisition of measured values: • The CPU writes[...]

  • Page 80

    Memory concept 4.2 Memory functions CPU 31xC and CPU 31x, Technical data 4-18 Manual, Edition 08/2004, A5E00105475-05 The data written to load memory are portable and rete ntive on C PU memory res et. Evaluation of measured values: • Measured value DBs save d to load memory can be uploaded an d eva luated by other communication partners (P G, PC,[...]

  • Page 81

    Memory concept 4.2 Memory functions CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 4-19 4.2.7 Backup of project data to a Micro Memory Card (MMC) Function principle Using the Save project to Memory Card and Fetch project from Memory Card func tions, you can save all project data to a SIMATIC Micro Memo ry Card, and r e[...]

  • Page 82

    Memory concept 4.2 Memory functions CPU 31xC and CPU 31x, Technical data 4-20 Manual, Edition 08/2004, A5E00105475-05[...]

  • Page 83

    CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 5-1 Cycle and reaction times 5 5.1 Overview Overview This section contains detailed information about the following topics: • Cycle time • Reaction time • Interrupt response time • Sample calculations Reference: Cycle time You can view the cycle time of y our user [...]

  • Page 84

    Cycle and reaction times 5.2 Cycle time CPU 31xC and CPU 31x, Technical data 5-2 Manual, Edition 08/2004, A5E00105475-05 5.2 Cycle time 5.2.1 Overview Introduction This section explains what we mean b y the term "cycle time", wh at it consists of, and how you can calcu late it. Meaning of the term cycle time The cycle time represents the [...]

  • Page 85

    Cycle and reaction times 5.2 Cycle time CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 5-3 Sequence of cyclic program processing The table and figure below show the ph ases in cyclic program pr ocessing. Table 5-1 Cyclic program processing Step Sequence 1 The operating system initiat es cycle time monitoring. 2 The CPU[...]

  • Page 86

    Cycle and reaction times 5.2 Cycle time CPU 31xC and CPU 31x, Technical data 5-4 Manual, Edition 08/2004, A5E00105475-05 Extending the cycle time Always make allowances for the e xtension of the cycle time of a user program due to: • Time-based interrupt processing • Process interrupt processing • Diagnostics and error pro cessing • Communi[...]

  • Page 87

    Cycle and reaction times 5.2 Cycle time CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 5-5 5.2.2 Calculati ng the cycle time Introduction The cycle time is derived from the sum of the following influen cing factors. Process image update The table below shows the time a CPU requires to update the pro cess image (process[...]

  • Page 88

    Cycle and reaction times 5.2 Cycle time CPU 31xC and CPU 31x, Technical data 5-6 Manual, Edition 08/2004, A5E00105475-05 Table 5-4 CPU 31x: Data for calc ulating the proc ess image (PI) transfer time Const. Portions CPU 312 CPU 314 CPU 31 5 CPU 317 K Base load 150 μs 100 μs 100 μs 50 μs A per byte in modul e rack 0 37 μs 35 μs 37 μs 15 μs B[...]

  • Page 89

    Cycle and reaction times 5.2 Cycle time CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 5-7 Operating system processing time at the scan cycle checkpoint The table below shows the operat ing system processing time at t he scan cycle checkpoint of the CPUs. These times are calcul ated without taking into consid eration t[...]

  • Page 90

    Cycle and reaction times 5.2 Cycle time CPU 31xC and CPU 31x, Technical data 5-8 Manual, Edition 08/2004, A5E00105475-05 Extension of the cycle time due to error Table 5-8 Cycle time extension as a result of errors Type of error Pr ogramming e rrors I/O access errors 312C 600 μs 600 μs 313C 400 μs 400 μs 313C2 400 μs 400 μs 314C-2 400 μs 400[...]

  • Page 91

    Cycle and reaction times 5.2 Cycle time CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 5-9 Maximum cycle time In STEP 7 you can modify the default maximum cycle time. OB80 is called o n when this time expires. In this block you can sp ecify the CPUs res ponse to thi s timeout error. The CPU switches to STOP mode if OB8[...]

  • Page 92

    Cycle and reaction times 5.2 Cycle time CPU 31xC and CPU 31x, Technical data 5-10 Manual, Edition 08/2004, A5E00105475-05 Physical cycle time depending on communication load The figure below describes t he non-linear depen dency of the phy sical cy cle time on communication load. In o ur s ample we have chosen a cycle time o f 10 ms. 0% 10 % 20 % 3[...]

  • Page 93

    Cycle and reaction times 5.2 Cycle time CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 5-11 5.2.5 Cycle time extension as a result of testin g and commissioning functions Runtimes The runtimes of the testing and commissioning functio ns are ope rating system runtimes, so they are the same for every CP U. Initially, the[...]

  • Page 94

    Cycle and reaction times 5.2 Cycle time CPU 31xC and CPU 31x, Technical data 5-12 Manual, Edition 08/2004, A5E00105475-05 Note The use of CBA with cyclical PRO FINET interconnections require s the use of switches to maintain the performance data . 100-Mbit full-duplex operation i s mandatory with cyclical PROFINET interconnections. The following gr[...]

  • Page 95

    Cycle and reaction times 5.2 Cycle time CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 5-13 Additional marginal conditions The maximum cycle load through comm unication in the measurement is 20 %. The lower graphic show s that the OB1 cycle is influenced by increasing the cyclical PROFINET interconnections to r emote p[...]

  • Page 96

    Cycle and reaction times 5.3 Response time CPU 31xC and CPU 31x, Technical data 5-14 Manual, Edition 08/2004, A5E00105475-05 5.3 Response time 5.3.1 Overview Definition of response time The response time is the time between the dete ction of an input signal and the change of a linked output signal. Fluctuation width The physical response time lies [...]

  • Page 97

    Cycle and reaction times 5.3 Response time CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 5-15 DP cycle times in the PROFIBUS DP network If you have configured your PROFIBU S DP master sys tem in STEP 7 , STEP 7 c alculates the typical DP cycle time to be expected. You c an then view the DP cycle time of your configura[...]

  • Page 98

    Cycle and reaction times 5.3 Response time CPU 31xC and CPU 31x, Technical data 5-16 Manual, Edition 08/2004, A5E00105475-05 5.3.2 Shortest response time Conditions for the shortest response time The figure below shows the conditions u nder which the shortest response time is reached. Delay of inputs Immediately before reading in the PII, the statu[...]

  • Page 99

    Cycle and reaction times 5.3 Response time CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 5-17 5.3.3 Longest response time Conditions for the longest response time The figure below shows the conditions u nder which the longest r esponse time is reached. Response time While reading in the PII, the status of the monitore[...]

  • Page 100

    Cycle and reaction times 5.3 Response time CPU 31xC and CPU 31x, Technical data 5-18 Manual, Edition 08/2004, A5E00105475-05 Calculation The (longest) response time is the sum of: Table 5-11 Formula: Long est response time 2 x process image transfe r time for the inputs + 2 x process image transfer ti me for the outputs + 2 x program processi ng ti[...]

  • Page 101

    Cycle and reaction times 5.4 Calculating method for cal culating the cycle/response time CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 5-19 5.4 Calculating method for calculating the cycle/response time Introduction This section gives you an ove rvi ew of how to calculate the cycl e/response time. Cycle time 1. Determ[...]

  • Page 102

    Cycle and reaction times 5.4 Calculating method for cal cul ating the cycle/response time CPU 31xC and CPU 31x, Technical data 5-20 Manual, Edition 08/2004, A5E00105475-05 Response time Table 5-12 Calculati ng the response time Shortest response time L ongest response time - Multiply the physical cycle time by factor 2. Now add I/O delay. Now add t[...]

  • Page 103

    Cycle and reaction times 5.5 Interrupt response time CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 5-21 5.5 Interrupt response time 5.5.1 Overview Definition of interrupt response time The interrupt response time is t he time that expires between th e firs t occurrence of an interrupt signal and the call of t he first[...]

  • Page 104

    Cycle and reaction times 5.5 Interrupt response time CPU 31xC and CPU 31x, Technical data 5-22 Manual, Edition 08/2004, A5E00105475-05 Calculation The formula below show how you c an calculate the minimum and ma ximum interrupt response tim es. Table 5-14 Process/diagn ostic interrupt response times Calculation of the minim um and maximum interrupt[...]

  • Page 105

    Cycle and reaction times 5.5 Interrupt response time CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 5-23 Process interrupt processing Process interrupt processing begi ns after process interrupt OB4 0 is called. Higher-prio rity interrupts stop process interrup t processing. D irec t I/O access is executed during runti[...]

  • Page 106

    Cycle and reaction times 5.6 Sample calculations CPU 31xC and CPU 31x, Technical data 5-24 Manual, Edition 08/2004, A5E00105475-05 5.6 Sample calculations 5.6.1 Example of cycl e time calculation Installation You have configured an S7300 and equipped it with followin g mo dules in rack "0": • a CPU 314C-2 • 2 digital input modules [...]

  • Page 107

    Cycle and reaction times 5.6 Sample calculations CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 5-25 Calculating the longest response time Longest response time: 6.8 ms x 2 = 13.6 ms. • I/O delay can be neglected. • Neither PROFIBUS DP, nor PROFINET IO are being used, so you do not have to make allowances for any D[...]

  • Page 108

    Cycle and reaction times 5.6 Sample calculations CPU 31xC and CPU 31x, Technical data 5-26 Manual, Edition 08/2004, A5E00105475-05 Calculating the physical cycle time Under consideration of communication load: 12.5 ms * 100 / (100-40) = 20.8 ms. Thus, under consider ation of time-sharing factors, the actual cycle time is 21 ms . Calculation of the [...]

  • Page 109

    Cycle and reaction times 5.6 Sample calculations CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 5-27 5.6.3 Example of interrupt respons e time calculation Installation You have assembled an S7-300, c onsisting of one CPU 314C-2 and four digital modules in the CPU rack. One of the digita l input modules is an SM 321; DI[...]

  • Page 110

    Cycle and reaction times 5.6 Sample calculations CPU 31xC and CPU 31x, Technical data 5-28 Manual, Edition 08/2004, A5E00105475-05[...]

  • Page 111

    CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-1 Technical data of CPU 31xC 6 6.1 General technical data 6.1.1 Dimensions of CPU 31xC Each CPU features the same heigh t and depth, only the width dim ensions differ. • Height: 125 mm • Depth: 115 mm, or 180 mm with opened front cover. Width of CPU CPU Width CPU 312[...]

  • Page 112

    Technical data of CPU 31xC 6.1 General technical data CPU 31xC and CPU 31x, Technical data 6-2 Manual, Edition 08/2004, A5E00105475-05 6.1.2 Technical data of the Micro Memory Card (MMC) Plug-in SIMAT IC Micro M emory Ca rds The following memory modules are avail able: Table 6-1 Available MMCs Type Order number Required for a firm ware update via M[...]

  • Page 113

    Technical data of CPU 31xC 6.2 CPU 312C CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-3 6.2 CPU 312C Technical data Table 6-3 Technical data of CPU 312C Technical dat a CPU and version Order number 6ES7 312-5BD01-0AB0 • Hardware version 01 • Firmware version V2.0 • Associated programming package STEP 7 as of V[...]

  • Page 114

    Technical data of CPU 31xC 6.2 CPU 312C CPU 31xC and CPU 31x, Technical data 6-4 Manual, Edition 08/2004, A5E00105475-05 Technical dat a IEC Timers Yes • Type SFB • Number unlimited (l imited on ly by RAM size) Data areas and their r etentivity Flag bits 128 bytes • Retentive memory Configurable • Default retentivity MB0 to MB15 Clock flag [...]

  • Page 115

    Technical data of CPU 31xC 6.2 CPU 312C CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-5 Technical dat a Assembly Racks Max. 1 Modules per rack Max. 8 Number of DP masters • Integrated None • Via CP Max. 1 Number of function modules and communic ation processors you can operate • FM Max. 8 • CP (PtP) Max. 8 ?[...]

  • Page 116

    Technical data of CPU 31xC 6.2 CPU 312C CPU 31xC and CPU 31x, Technical data 6-6 Manual, Edition 08/2004, A5E00105475-05 Technical dat a Block status Yes Single step Yes Breakpoints 2 Diagnostic buffer Yes • Number of entries (not configurable) Max. 100 Communication functions PG/OP communication Yes Global data communication Yes • Number of GD[...]

  • Page 117

    Technical data of CPU 31xC 6.2 CPU 312C CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-7 Technical dat a Functionali ty • MPI Yes • PROFIBUS DP No • Point-to-point c ommunication No MPI Services • PG/OP communication Yes • Routing No • Global data communication Yes • S7 basic communication Yes • S7 co[...]

  • Page 118

    Technical data of CPU 31xC 6.3 CPU 313C CPU 31xC and CPU 31x, Technical data 6-8 Manual, Edition 08/2004, A5E00105475-05 Technical dat a I 2 t 0.7 A 2 s External fusing of power supply lines (recommended) LS switch Type C min. 2 A, LS switch Type B min. 4 A Power loss Typically 6 W Reference In Chapter Specifications of the integrated I/O you can f[...]

  • Page 119

    Technical data of CPU 31xC 6.3 CPU 313C CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-9 Technical dat a Timers/counters and their ret entivity S7 counters 256 • Retentive memory Configurable • Default from C0 to C7 • Counting range 0 to 999 IEC Counters Yes • Type SFB • Number unlimited (l imited on ly by [...]

  • Page 120

    Technical data of CPU 31xC 6.3 CPU 313C CPU 31xC and CPU 31x, Technical data 6-10 Manual, Edition 08/2004, A5E00105475-05 Technical dat a Address areas (I/O) Total I/O address area max. 1024 bytes/1024 bytes (can be freely addressed) I/O process image 128 bytes/128 bytes Digital channels Max. 1016 • of those local Max. 992 • Integrated channels[...]

  • Page 121

    Technical data of CPU 31xC 6.3 CPU 313C CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-11 Technical dat a Process diagnostics messages Yes • Simultaneously enabled interr upt S blocks Max. 20 Testing and commissio ning functions Status/control variables Yes • Variables Inputs, outputs, memory bits, DBs, timers, c[...]

  • Page 122

    Technical data of CPU 31xC 6.3 CPU 313C CPU 31xC and CPU 31x, Technical data 6-12 Manual, Edition 08/2004, A5E00105475-05 Technical dat a can be used for • PG communication – Reserved (default) – Configurable Max. 7 1 from 1 to 7 • OP communication – Reserved (default) – Configurable Max. 7 1 from 1 to 7 • S7 basic communication – R[...]

  • Page 123

    Technical data of CPU 31xC 6.3 CPU 313C CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-13 Technical dat a Integrated I/O • Default addresses of the integrated – Digital inputs – Digital outputs – Analog inputs – Analog outputs 124.0 to 126.7 124.0 to 125.7 752 to 761 752 to 755 Integrated functions Counters[...]

  • Page 124

    Technical data of CPU 31xC 6.4 CPU 313C-2 PtP and CPU 313C-2 DP CPU 31xC and CPU 31x, Technical data 6-14 Manual, Edition 08/2004, A5E00105475-05 6.4 CPU 313C-2 PtP and CPU 313C-2 DP Technical data Table 6-5 Technical data for CPU 313C-2 PtP/ CPU 313C-2 DP Technical dat a CPU 313C-2 PtP CPU 313C-2 DP CPU and version CPU 313C-2 PtP CPU 313C-2 DP Ord[...]

  • Page 125

    Technical data of CPU 31xC 6.4 CPU 313C-2 PtP and CPU 313C-2 DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-15 Technical dat a CPU 313C-2 PtP CPU 313C-2 DP Data areas and their r etentivity CPU 313C-2 PtP CPU 313C-2 DP Flag bits 256 bytes • Retentive memory Configurable • Default retentivity MB0 to MB15 Clock [...]

  • Page 126

    Technical data of CPU 31xC 6.4 CPU 313C-2 PtP and CPU 313C-2 DP CPU 31xC and CPU 31x, Technical data 6-16 Manual, Edition 08/2004, A5E00105475-05 Technical dat a CPU 313C-2 PtP CPU 313C-2 DP Number of function modules and communication processors you can operate • FM Max. 8 • CP (PtP) Max. 8 • CP (LAN) Max. 6 Time-of-day CPU 313C-2 PtP CPU 31[...]

  • Page 127

    Technical data of CPU 31xC 6.4 CPU 313C-2 PtP and CPU 313C-2 DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-17 Technical dat a CPU 313C-2 PtP CPU 313C-2 DP Communication functions CPU 313C-2 PtP CPU 313C-2 D P PG/OP communication Yes Global data communication Yes • Number of GD circuits 4 • Number of GD packet[...]

  • Page 128

    Technical data of CPU 31xC 6.4 CPU 313C-2 PtP and CPU 313C-2 DP CPU 31xC and CPU 31x, Technical data 6-18 Manual, Edition 08/2004, A5E00105475-05 Technical dat a CPU 313C-2 PtP CPU 313C-2 DP MPI Services • PG/OP communication Yes • Routing No Yes • Global data communication Yes • S7 basic communication Yes • S7 communication – As server[...]

  • Page 129

    Technical data of CPU 31xC 6.4 CPU 313C-2 PtP and CPU 313C-2 DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-19 Technical dat a CPU 313C-2 PtP CPU 313C-2 DP DP slave Number of connections – 8 Services • PG/OP communication – Yes • Routing – Yes (only if interface is active) • Global data communication ?[...]

  • Page 130

    Technical data of CPU 31xC 6.4 CPU 313C-2 PtP and CPU 313C-2 DP CPU 31xC and CPU 31x, Technical data 6-20 Manual, Edition 08/2004, A5E00105475-05 Technical dat a CPU 313C-2 PtP CPU 313C-2 DP Integrated functions Counters 3 channels (see the Manual Technologic al Functions ) Frequency counters 3 channels, m ax. 30 kHz (see the Manual Technological F[...]

  • Page 131

    Technical data of CPU 31xC 6.5 CPU 314C-2 PtP and CPU 314C-2 DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-21 6.5 CPU 314C-2 PtP and CPU 314C-2 DP Technical data Table 6-6 Technical data of CPU 314C-2 PtP and CPU 314 C-2 DP Technical dat a CPU 314C-2 PtP CPU 314C-2 DP CPU and version CPU 314C-2 PtP CPU 314C-2 DP [...]

  • Page 132

    Technical data of CPU 31xC 6.5 CPU 314C-2 PtP and CPU 314C-2 DP CPU 31xC and CPU 31x, Technical data 6-22 Manual, Edition 08/2004, A5E00105475-05 Technical dat a CPU 314C-2 PtP CPU 314C-2 DP Data areas and their r etentivity CPU 314C-2 PtP CPU 314C-2 DP Flag bits 256 bytes • Retentive memory Configurable • Default retentivity MB0 to MB15 Clock [...]

  • Page 133

    Technical data of CPU 31xC 6.5 CPU 314C-2 PtP and CPU 314C-2 DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-23 Technical dat a CPU 314C-2 PtP CPU 314C-2 DP Number of function modules and communication processors you can operate • FM Max. 8 • CP (PtP) Max. 8 • CP (LAN) Max. 10 Time-of-day CPU 314C-2 PtP CPU 3[...]

  • Page 134

    Technical data of CPU 31xC 6.5 CPU 314C-2 PtP and CPU 314C-2 DP CPU 31xC and CPU 31x, Technical data 6-24 Manual, Edition 08/2004, A5E00105475-05 Technical dat a CPU 314C-2 PtP CPU 314C-2 DP Communication functions CPU 314C-2 PtP CPU 314C-2 D P PG/OP communication Yes Global data communication Yes • Number of GD circuits 4 • Number of GD packet[...]

  • Page 135

    Technical data of CPU 31xC 6.5 CPU 314C-2 PtP and CPU 314C-2 DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-25 Technical dat a CPU 314C-2 PtP CPU 314C-2 DP MPI Number of connections 12 Services • PG/OP communication Yes • Routing No Yes • Global data communication Yes • S7 basic communication Yes • S7 co[...]

  • Page 136

    Technical data of CPU 31xC 6.5 CPU 314C-2 PtP and CPU 314C-2 DP CPU 31xC and CPU 31x, Technical data 6-26 Manual, Edition 08/2004, A5E00105475-05 Technical dat a CPU 314C-2 PtP CPU 314C-2 DP DP slave Number of connections – 12 Services • PG/OP communication – Yes • Routing – Yes (only if interface is active) • Global data communication [...]

  • Page 137

    Technical data of CPU 31xC 6.5 CPU 314C-2 PtP and CPU 314C-2 DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-27 Technical dat a CPU 314C-2 PtP CPU 314C-2 DP Integrated functions Counters 4 channels (see the Manual Technologic al Functions ) Frequency counters 4 channels, m ax. 60 kHz (see the Manual Technological F[...]

  • Page 138

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data 6-28 Manual, Edition 08/2004, A5E00105475-05 6.6 Technical data of the integrated I/O 6.6.1 Arrangement and usa ge of integrated I/Os Introduction Integrated I/Os of CPU s 31xC can be used for technological func tions or as standard I/O. The fig[...]

  • Page 139

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-29 Block diagram of the integrated digital I/O CPU interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2M 1M 1L+[...]

  • Page 140

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data 6-30 Manual, Edition 08/2004, A5E00105475-05 CPU 313C, CPU 313C-2 DP/PtP, CPU 314C-2 DP/Pt P: DI/DO (connecto rs X11 and X12) 1 2 3 4 5 6 8 7 9 10 11 12 13 14 16 15 17 18 20 19 Standard DI Posi- tioning X11 of CPU 313C-2 PtP/DP X12 of CPU 314C-2[...]

  • Page 141

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-31 Block diagram of integrated digital I/O of CPUs 313C/313C-2/314 C-2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CPU interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2L+ 3M [...]

  • Page 142

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data 6-32 Manual, Edition 08/2004, A5E00105475-05 CPU 313C/314C-2: Pin-out of the integrated AI/AO and DI (connec tor X11) 1 2 3 4 5 6 8 7 9 10 11 12 13 14 16 15 17 18 20 19 Standard Positioning AI (Ch0) AI (Ch1) AI (Ch2) AI (Ch3) PT 100 (Ch4) AO (Ch[...]

  • Page 143

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-33 Simultaneous usage of technological functions and standard I/O Technological functions an d stand ard I/O can be used simultaneo usly with appropriate hardware. For example, you can use all digital in[...]

  • Page 144

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data 6-34 Manual, Edition 08/2004, A5E00105475-05 6.6.2 Analog I/O Wiring of the current/voltage inputs The figure below shows the wiring diagra m of the current/voltage inputs operated with 2-/4-wire measuring transducers. 2-wire signal converter AI[...]

  • Page 145

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-35 Measurement principle 31xC CPUs use the measurement prin ciple of actual value encodin g. Here, they operate with a sampling rate of 1 kHz. T hat is , a new value is availabl e at the peripheral input[...]

  • Page 146

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data 6-36 Manual, Edition 08/2004, A5E00105475-05 Input filters (software filter) The current / voltage inputs have a software filter for the inp ut signals which can be programmed with STEP 7. It filters the configured interference frequency (50/60 [...]

  • Page 147

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-37 In the two graphics below we illustrate h ow the 50 Hz and 60 Hz interference suppressi on work 1.05 ms Value 1 Value 2 Value 3 ... Value 19 Value 20 Value 1 Value 2 Value 3 ... Value 19 Value 20 1.05[...]

  • Page 148

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data 6-38 Manual, Edition 08/2004, A5E00105475-05 Value 1 Value 2 Value 3 ... Value 16 Value 17 Value 1 Value 2 Value 3 ... Value 16 Value 17 1.05 ms 1.05 ms 1.05 ms 1.05 ms 1.05 ms 1.05 ms 1.05 ms 1.05 ms 1.05 ms 1.05 ms Example of a 60-Hz parasitic[...]

  • Page 149

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-39 6.6.3 Configuration Introduction You configure the integrated I/O of CPU 31xC with STEP 7. Alway s make these settings when the CPU is in STOP. The generated paramete rs are downloade d from the PG to[...]

  • Page 150

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data 6-40 Manual, Edition 08/2004, A5E00105475-05 Byte 0 7 7 7 7 7 Byte 1 Byte 2 Byte 4 Byte 5 Byte 8 7 Byte 9 7 Byte 6 00 01 10 11 : B B B B : : : 3 0,1 ms 0,5 ms 15 ms ms 0: 1: 00 B 7 0 Bit-Nr . Byte 0 0 Bit-Nr . 0 Bit-Nr . 0 Bit-Nr . 0 Bit-Nr . 0 [...]

  • Page 151

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-41 Parameters of standard DO There are no parameters for standard digital outputs. Parameters of standard AI The table below gives you an ov erview of the parameters for sta ndard analog inputs. Table 6-[...]

  • Page 152

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data 6-42 Manual, Edition 08/2004, A5E00105475-05 Parameters of standard AO The table below gives you an ov erview of standard analog o utput parameters (see also Chapter 4.3 in the Module Data Reference Manual). Table 6-10 Paramet ers of standard AO[...]

  • Page 153

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-43 reserved Unit of measure reserved Default setting: Celsius Fahrenheit Kelvin Parasitic frequency suppression integration time of channel AI 0 Default setting: Measuring range of channel AI 0 (settings[...]

  • Page 154

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data 6-44 Manual, Edition 08/2004, A5E00105475-05  %LW1U  %LW1U %WH %WH   %WH  0: 2: 3: 4: 8: 9: 9 H H H H H H H 0 … 20 mA 4 … 20 mA +/- 20 mA 0…1 0V +/- 10 V 0: 1: 3: 9 H H H H Out[...]

  • Page 155

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-45 6.6.4 Interrupts Interrupt inputs All digital inputs of the on-boar d I/O of CPUs 31xC can be used as interrupt inputs. You can specify interrupt beha vior for each individual input in your parameter [...]

  • Page 156

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data 6-46 Manual, Edition 08/2004, A5E00105475-05 31 30 29 28 27 26 25 24 16 15 … 8 7654321 … Bit no. PRAL: process interrupt Inputs are designated with default addresses. reserved 23 PRAL from E124.0 PRAL from E124.7 PRAL from E125.0 PRAL from E[...]

  • Page 157

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-47 Technical data Table 6-12 Technic al data of digital inputs Technical dat a CPU 312C CPU 313C CPU 313C-2 CPU 314C-2 Module-specific d ata CPU 312C CPU 313C CPU 313C -2 CPU 314C-2 Number of inputs 10 2[...]

  • Page 158

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data 6-48 Manual, Edition 08/2004, A5E00105475-05 Technical dat a CPU 312C CPU 313C CPU 313C-2 CPU 314C-2 Data for the selection of an enc oder for standard DI CPU 312C CPU 313C CPU 31 3C-2 CPU 314C-2 Input voltage • Rated value 24 VDC • For sign[...]

  • Page 159

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-49 Technical data Table 6-13 Technic al dat a of digita l outputs Technical dat a CPU 312C CPU 313C CPU 313C-2 CPU 314C-2 Module-specific d ata CPU 312C CPU 313C CPU 313C -2 CPU 314C-2 Number of outputs [...]

  • Page 160

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data 6-50 Manual, Edition 08/2004, A5E00105475-05 Technical dat a CPU 312C CPU 313C CPU 313C-2 CPU 314C-2 Data for the selection of an actu ator for standard DI CPU 312C CPU 313C CPU 31 3C-2 CPU 314C-2 Output voltage • For signal "1" Min.[...]

  • Page 161

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-51 6.6.8 Analog inputs Introduction This chapter contains the specif ications for analog outputs of CPUs 31xC. The table includes the following CPUs: • CPU 313C • CPU 314C-2 DP • CPU 314C-2 PtP Tec[...]

  • Page 162

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data 6-52 Manual, Edition 08/2004, A5E00105475-05 Technical dat a Time constant of the in put filter 0,38 ms Basic processing time 1 ms Interference suppressi on, error limits Interference voltage su ppression for f = nx (f1 ± 1 %), (f1 = i nterfere[...]

  • Page 163

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-53 Technical dat a Connection of signal generators • For voltage measurement Possible • For current measurement – as 2-wire measuring transducer – as 4-wire measuring transducer Possible, with ex[...]

  • Page 164

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data 6-54 Manual, Edition 08/2004, A5E00105475-05 Technical dat a Permitted potential difference • between M ANA and M internal (U ISO ) 75 VDC / 60 VAC Insulation test voltage 600 VDC Analog value ge neration Resolution (including overdriv e) 11 b[...]

  • Page 165

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 6-55 Technical dat a Voltage output • Short-circuit protection Yes • Short-circuit current Typically 55 mA Current output • No-load voltage Typically 17 V Destruction limit for externally applied vo [...]

  • Page 166

    Technical data of CPU 31xC 6.6 Technical data of the integrated I/O CPU 31xC and CPU 31x, Technical data 6-56 Manual, Edition 08/2004, A5E00105475-05[...]

  • Page 167

    CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-1 Technical data of CPU 31x 7 7.1 General technical data 7.1.1 Dimensions of CPU 31x Each CPU features the same heigh t and depth, only the width dim ensions differ. • Height: 125 mm • Depth: 115 mm, or 180 mm with opened front cover. 40 115 65 125 Figure 7-1 Dimensi[...]

  • Page 168

    Technical data of CPU 31x 7.1 General technical data CPU 31xC and CPU 31x, Technical data 7-2 Manual, Edition 08/2004, A5E00105475-05 7.1.2 Technical data of the Micro Memory Card (MMC) Plug-in SIMAT IC Micro M emory Ca rds The following memory modules are avail able: Table 7-1 Available MMCs Type Order number Required for a firm ware update via MM[...]

  • Page 169

    Technical data of CPU 31x 7.2 CPU 312 CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-3 7.2 CPU 312 Technical data Table 7-3 Technical dat a for the CPU 312 Technical dat a CPU and version Order number 6ES7312-1AD10-0AB0 • Hardware version 01 • Firmware version V2.0.0 • Associated programming package STEP 7 as o[...]

  • Page 170

    Technical data of CPU 31x 7.2 CPU 312 CPU 31xC and CPU 31x, Technical data 7-4 Manual, Edition 08/2004, A5E00105475-05 Technical dat a Data areas and their r etentivity Flag bits 128 bytes • Retentive memory Yes • Default retentivity MB0 to MB15 Clock flag bits 8 (1 byte per flag bit) Data blocks 511 (DB 1 to DB 511) • Length 16 KB Local data[...]

  • Page 171

    Technical data of CPU 31x 7.2 CPU 312 CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-5 Technical dat a Number of function modules and communic ation processors you can operate • FM Max. 8 • CP (PtP) Max. 8 • CP (LAN) Max. 4 Time-of-day Real-time clock Yes (SW clock) • Buffered No • Accuracy Deviation per da[...]

  • Page 172

    Technical data of CPU 31x 7.2 CPU 312 CPU 31xC and CPU 31x, Technical data 7-6 Manual, Edition 08/2004, A5E00105475-05 Technical dat a Communication functions PG/OP communication Yes Global data communication Yes • Number of GD circuits 4 • Number of GD packets – Sending stations – Receiving stations Max. 4 Max. 4 Max. 4 • Length of GD pa[...]

  • Page 173

    Technical data of CPU 31x 7.2 CPU 312 CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-7 Technical dat a MPI Services • PG/OP communication Yes • Routing No • Global data communication Yes • S7 basic communication Yes • S7 communication – As server – As client Yes No • Transmission rates 187.5 kbps Prog[...]

  • Page 174

    Technical data of CPU 31x 7.3 CPU 314 CPU 31xC and CPU 31x, Technical data 7-8 Manual, Edition 08/2004, A5E00105475-05 7.3 CPU 314 Technical data for the CPU 314 Table 7-4 Technical dat a for the CPU 314 Technical dat a CPU and version Order number 6ES7314-1AF10-0AB0 • Hardware version 01 • Firmware version V 2.0.0 • Associated programming pa[...]

  • Page 175

    Technical data of CPU 31x 7.3 CPU 314 CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-9 Technical dat a Data areas and their r etentivity Flag bits 256 bytes • Retentive memory Yes • Default retentivity MB0 to MB15 Clock flag bits 8 (1 byte per flag bit) Data blocks • Number 511 (DB 1 to DB 511) • Length 16 KB[...]

  • Page 176

    Technical data of CPU 31x 7.3 CPU 314 CPU 31xC and CPU 31x, Technical data 7-10 Manual, Edition 08/2004, A5E00105475-05 Technical dat a Number of function modules and communic ation processors you can operate • FM Max. 8 • CP (PtP) Max. 8 • CP (LAN) Max. 10 Time-of-day Real-time clock Yes (HW clock) • Buffered Yes • Buffered period Typica[...]

  • Page 177

    Technical data of CPU 31x 7.3 CPU 314 CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-11 Technical dat a • Number of entries (not configurable) Max. 100 Communication functions PG/OP communication Yes Global data communication Yes • Number of GD circuits 4 • Number of GD packets – Sending stations – Receivin[...]

  • Page 178

    Technical data of CPU 31x 7.3 CPU 314 CPU 31xC and CPU 31x, Technical data 7-12 Manual, Edition 08/2004, A5E00105475-05 Technical dat a MPI Services • PG/OP communication Yes • Routing No • Global data communication Yes • S7 basic communication Yes • S7 communication – As server – As client Yes Yes No (but via CP and loadable FBs) •[...]

  • Page 179

    Technical data of CPU 31x 7.4 CPU 315-2 DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-13 7.4 CPU 315-2 DP Technical data Table 7-5 Technical data for the CPU 315-2 DP Technical dat a CPU and version Order number 6ES7315- 2AG10-0AB0 • Hardware version 01 • Firmware version V 2.0.0 • Associated programming pa[...]

  • Page 180

    Technical data of CPU 31x 7.4 CPU 315-2 DP CPU 31xC and CPU 31x, Technical data 7-14 Manual, Edition 08/2004, A5E00105475-05 Technical dat a Data areas and their r etentivity Flag bits 2048 bytes • Retentive memory Yes • Default retentivity MB0 to MB15 Clock flag bits 8 (1 byte per flag bit) Data blocks • Number 1023 (DB 1 to DB 1023) • Len[...]

  • Page 181

    Technical data of CPU 31x 7.4 CPU 315-2 DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-15 Technical dat a Number of function modules and communic ation processors you can operate • FM Max. 8 • CP (PtP) Max. 8 • CP (LAN) Max. 10 Time-of-day Real-time clock Yes (HW clock) • Buffered Yes • Buffered period T[...]

  • Page 182

    Technical data of CPU 31x 7.4 CPU 315-2 DP CPU 31xC and CPU 31x, Technical data 7-16 Manual, Edition 08/2004, A5E00105475-05 Technical dat a Diagnostic buffer Yes • Number of entries (not configurable) Max. 100 Communication functions PG/OP communication Yes Global data communication Yes • Number of GD circuits 8 • Number of GD packets – Se[...]

  • Page 183

    Technical data of CPU 31x 7.4 CPU 315-2 DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-17 Technical dat a Functionali ty • MPI Yes • PROFIBUS DP No • Point-to-point c ommunication No MPI Services • PG/OP communication Yes • Routing Yes • Global data communication Yes • S7 basic communication Yes • [...]

  • Page 184

    Technical data of CPU 31x 7.4 CPU 315-2 DP CPU 31xC and CPU 31x, Technical data 7-18 Manual, Edition 08/2004, A5E00105475-05 Technical dat a DP slave Services • PG/OP communication Yes • Routing Yes (only if interface is active) • Global data communication No • S7 basic communication No • S7 communication No • Direct data exchange Yes ?[...]

  • Page 185

    Technical data of CPU 31x 7.5 CPU 315-2 PN/DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-19 7.5 CPU 315-2 PN/DP Technical data Table 7-6 Technical data for the CPU 315-2 PN/DP Technical dat a CPU and version Order number 6ES7315-2EG10-0AB 0 • Hardware version 01 • Firmware version V 2.3.0 • Associated progr[...]

  • Page 186

    Technical data of CPU 31x 7.5 CPU 315-2 PN/DP CPU 31xC and CPU 31x, Technical data 7-20 Manual, Edition 08/2004, A5E00105475-05 Technical dat a IEC Timers Yes • Type SFB • Number Unlimited (limited only by RAM size) Data areas and their r etentivity Flag bits 2048 bytes • Retentive memory Configurable • Default retentivity From MB0 to MB15 [...]

  • Page 187

    Technical data of CPU 31x 7.5 CPU 315-2 PN/DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-21 Technical dat a Assembly Racks Max. 4 Modules per rack 8 Number of DP masters • Integrated 1 • via CP 2 Number of function modules and co mm unication processors you can operate • FM Max. 8 • CP (PtP) Max. 8 • CP[...]

  • Page 188

    Technical data of CPU 31x 7.5 CPU 315-2 PN/DP CPU 31xC and CPU 31x, Technical data 7-22 Manual, Edition 08/2004, A5E00105475-05 Technical dat a • Number of variables – Of those as status variable – Of those as cont rol variable 30 Max. 30 Max. 14 Forcing • Variables Inputs/Outputs • Number of variables Max. 10 Block status Yes Single step[...]

  • Page 189

    Technical data of CPU 31x 7.5 CPU 315-2 PN/DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-23 Technical dat a Routing • Interface X1 configured as – MPI – DP master – DP slave (active) • Interface X2 configured as PROFINET Yes Max. 10 Max. 24 Max. 14 Max. 24 CBA (at 50 % communic ation load) • Maximum d[...]

  • Page 190

    Technical data of CPU 31x 7.5 CPU 315-2 PN/DP CPU 31xC and CPU 31x, Technical data 7-24 Manual, Edition 08/2004, A5E00105475-05 Technical dat a MPI Services • PG/OP communication Yes • Routing Yes • Global data communication Yes • S7 basic communication Yes • S7 communication – As server – As client Yes Yes No (but via CP and loadable[...]

  • Page 191

    Technical data of CPU 31x 7.5 CPU 315-2 PN/DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-25 Technical dat a Functionali ty • PROFINET Yes • MPI No • PROFIBUS DP No • Point-to-point c ommunication No Services • PG communication Yes • OP communication Yes • S7 communication – Max. configurable inter[...]

  • Page 192

    Technical data of CPU 31x 7.6 CPU 317-2 DP CPU 31xC and CPU 31x, Technical data 7-26 Manual, Edition 08/2004, A5E00105475-05 Technical dat a Voltages and curre nts Power supply (rated value) 24 VDC • Permitted range 20.4 V to 28.8 V Current consumption (no-load oper ation) 100 mA Inrush current Typically 2.5 A I 2 t Min. 1 A 2 s External fusing o[...]

  • Page 193

    Technical data of CPU 31x 7.6 CPU 317-2 DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-27 Technical dat a Timers/counters and their ret entivity S7 counters 512 • Retentive memory Configura ble • Default from C0 to C7 • Counting range 0 to 999 IEC Counters Yes • Type SFB • Number Unlimited (limited only [...]

  • Page 194

    Technical data of CPU 31x 7.6 CPU 317-2 DP CPU 31xC and CPU 31x, Technical data 7-28 Manual, Edition 08/2004, A5E00105475-05 Technical dat a FCs See the Instruct ion List • Number 2048 (FC 0 to FC 2047) • Length 64 KB Address areas (I/O) Total I/O address area max . 8192 bytes/8192 bytes (can be freely addressed) Distributed max. 8192 bytes I/O[...]

  • Page 195

    Technical data of CPU 31x 7.6 CPU 317-2 DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-29 Technical dat a S7 signaling functions Number of stations tha t can be logged on for signaling functions 32 (depends on the number of connecti ons configured for PG / OP and S7 basic communication) Process diagnostics message[...]

  • Page 196

    Technical data of CPU 31x 7.6 CPU 317-2 DP CPU 31xC and CPU 31x, Technical data 7-30 Manual, Edition 08/2004, A5E00105475-05 Technical dat a Number of connections 32 can be used for • PG communication – Reserved (default) – Configurable Max. 31 1 1 to 31 • OP communication – Reserved (default) – Configurable Max. 31 1 1 to 31 • S7-bas[...]

  • Page 197

    Technical data of CPU 31x 7.6 CPU 317-2 DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-31 Technical dat a Transmission speed Up to 12 Mbps Number of DP slaves 124 Address range per DP slave max. 244 bytes DP slave (except for DP s lave at both interfaces) Services • Routing Yes (only if interface is active) • [...]

  • Page 198

    Technical data of CPU 31x 7.6 CPU 317-2 DP CPU 31xC and CPU 31x, Technical data 7-32 Manual, Edition 08/2004, A5E00105475-05 Technical dat a DP slave (except for DP s lave at both interfaces) Services • PG/OP communication Yes • Routing Yes (only if interface is active) • Global data communication No • S7 basic communication No • S7 commu[...]

  • Page 199

    Technical data of CPU 31x 7.7 CPU 317-2 PN/DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-33 7.7 CPU 317-2 PN/DP Technical data Table 7-8 Technical data for the CPU 317-2 PN/DP Technical dat a CPU and version Order number 6ES7317-2EJ10-0AB0 • Hardware version 01 • Firmware version V 2.3.0 • Associated progra[...]

  • Page 200

    Technical data of CPU 31x 7.7 CPU 317-2 PN/DP CPU 31xC and CPU 31x, Technical data 7-34 Manual, Edition 08/2004, A5E00105475-05 Technical dat a IEC Timers Yes • Type SFB • Number Unlimited (limited only by RAM size) Data areas and their r etentivity Flag bits 4096 bytes • Retentive memory Configurable • Default retentivity From MB0 to MB15 [...]

  • Page 201

    Technical data of CPU 31x 7.7 CPU 317-2 PN/DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-35 Technical dat a Analog channels 4096/4096 of those local 256/256 Assembly Racks Max. 4 Modules per rack 8 Number of DP masters • Integrated 1 • via CP 2 Number of function modules and co mm unication processors you can[...]

  • Page 202

    Technical data of CPU 31x 7.7 CPU 317-2 PN/DP CPU 31xC and CPU 31x, Technical data 7-36 Manual, Edition 08/2004, A5E00105475-05 Technical dat a • Number of variables – Of those as status variable – Of those as cont rol variable 30 Max. 30 Max. 14 Forcing • Variables Inputs/Outputs • Number of variables Max. 10 Block status Yes Single step[...]

  • Page 203

    Technical data of CPU 31x 7.7 CPU 317-2 PN/DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-37 Technical dat a Routing • Interface X1 configured as – MPI – DP master – DP slave (active) • Interface X2 configured as – PROFINET Yes Max. 10 Max. 24 Max. 14 Max. 24 CBA (at 50 % communic ation load) • Maxim[...]

  • Page 204

    Technical data of CPU 31x 7.7 CPU 317-2 PN/DP CPU 31xC and CPU 31x, Technical data 7-38 Manual, Edition 08/2004, A5E00105475-05 Technical dat a MPI Services • PG/OP communication Yes • Routing Yes • Global data communication Yes • S7 basic communication Yes • S7 communication – As server – As client Yes Yes No (but via CP and loadable[...]

  • Page 205

    Technical data of CPU 31x 7.7 CPU 317-2 PN/DP CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 7-39 Technical dat a Functionali ty • PROFINET Yes • MPI No • PROFIBUS DP No • Point-to-point c ommunication No Services • PG communication Yes • OP communication Yes • S7 communication – Max. configurable inter[...]

  • Page 206

    Technical data of CPU 31x 7.7 CPU 317-2 PN/DP CPU 31xC and CPU 31x, Technical data 7-40 Manual, Edition 08/2004, A5E00105475-05 Technical dat a Voltages and curre nts Power supply (rated value) 24 VDC • Permitted range 20.4 V to 28.8 V Current consumption (no-load oper ation) 100 mA Inrush current Typically 2.5 A I 2 t Min. 1 A 2 s External fusin[...]

  • Page 207

    CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 A-1 Appendix A A.1 Information about upgrading to a CPU 31xC or CPU 31x A.1.1 Area of applic ability Who should read this information? You are already using a CPU fr om the SIEMENS S7-300 se ries and now want to upgrade to a new device. Please note that problems may oc cur[...]

  • Page 208

    Appendix A.1 Information about upgrading to a CPU 31xC or CPU 31x CPU 31xC and CPU 31x, Technical data A-2 Manual, Edition 08/2004, A5E00105475-05 ... then please note if you upgrade to one of the following CPU s From version CPU Order number Firmware Hardware Hereafter called 312 6ES7312-1AD 10-0AB0 V2.0.0 01 312C 6ES73 12-5BD01-0AB0 V2.0.0 01 313[...]

  • Page 209

    Appendix A.1 Information about upgradi ng to a CPU 31x C or CPU 31x CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 A-3 Note If you are using SFC 56 "WR_DPAR M" or SFC 57 "PARM_MOD", you sh ould a lways evaluate the SFC's BUSY bit. • SFC 13 "DPNRM_DG" On CPUs 312 IFM to 318-2 DP, thi[...]

  • Page 210

    Appendix A.1 Information about upgrading to a CPU 31xC or CPU 31x CPU 31xC and CPU 31x, Technical data A-4 Manual, Edition 08/2004, A5E00105475-05 SFCs that may return other results You can ignore the following poi nts if you only use logical add re ssing in your user progra m. When using addres s conversion in your user program (SFC 5 "GADR _[...]

  • Page 211

    Appendix A.1 Information about upgradi ng to a CPU 31x C or CPU 31x CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 A-5 A.1.4 Runtimes that change while the program is running Runtimes that change while the program is running If you have created a user progr am that has been fine-tuned in relation to certain processing [...]

  • Page 212

    Appendix A.1 Information about upgrading to a CPU 31xC or CPU 31x CPU 31xC and CPU 31x, Technical data A-6 Manual, Edition 08/2004, A5E00105475-05 A.1.6 Reusing existing hardware configurations Reusing existing hardware configurations If you reuse the configuration o f a CPU 312 IFM to 318-2 DP for a CPU 31xC/31x, the CPU 31xC/31x may not run corre[...]

  • Page 213

    Appendix A.1 Information about upgradi ng to a CPU 31x C or CPU 31x CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 A-7 A.1.8 Using consistent data area s in the process image of a DP slave system Consistent data The table below illustrates the points to consider with respect to communication in a DP master system if yo[...]

  • Page 214

    Appendix A.1 Information about upgrading to a CPU 31xC or CPU 31x CPU 31xC and CPU 31x, Technical data A-8 Manual, Edition 08/2004, A5E00105475-05 A.1.9 Load memory concept for the CPU 31xC/31x Load memory concept for the CPU 31xC/31x On CPUs 312 IFM to 318-2 DP, the load memory is integrated into the CPU and may be extended with a memory card, The[...]

  • Page 215

    Appendix A.1 Information about upgradi ng to a CPU 31x C or CPU 31x CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 A-9 A.1.12 Changed retentive behavior for CPUs with firmware >= V2. 1.0 Changed retentive behavior for CPUs with firmware >= V2.1.0 For data blocks for these CPUs • you can set the retentive resp o[...]

  • Page 216

    Appendix A.1 Information about upgrading to a CPU 31xC or CPU 31x CPU 31xC and CPU 31x, Technical data A-10 Manual, Edition 08/2004, A5E00105475-05 A.1.14 Using loadable blocks for S7 communication for the integ rated PROFINET interface If you have already used S7 comm unication via CP with loadabl e FBs (FB 8, FB 9, FB 12 – FB 15 and FC 62 with [...]

  • Page 217

    CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 Glossary-1 Glossary Accumulator Accumulators represent CPU regist er and are used a s buffer memo ry for downl oad, transfer, comparison, calculatio n and conversion operations. Address An address is the identifier of a specific address or address a rea. Examples: Input I [...]

  • Page 218

    Glossary CPU 31xC and CPU 31x, Technical data Glossary-2 Manual, Edition 08/2004, A5E00105475-05 Backup memory Backup memory ensures buffering of the memory are as of a CPU wi thout backup battery. It backs up a configurable number of timers, counters, flag bits, data bytes and retentive timers, counters, flag bits and data bytes). Bus A bus is a c[...]

  • Page 219

    Glossary CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 Glossary-3 Compress The PG online function "Compress" is used to rearrange all vali d blocks in CPU RAM in one continuous area of user memory, s tarting at the lowest address. This eliminates fragmentation which occurs when blocks are deleted o r edited.[...]

  • Page 220

    Glossary CPU 31xC and CPU 31x, Technical data Glossary-4 Manual, Edition 08/2004, A5E00105475-05 Data, temporary Temporary data represent local data of a block. They are stored in the L-stack when the block is executed. After the block has been proc essed, these da ta are no longer available. Default Router The default router is the router that is [...]

  • Page 221

    Glossary CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 Glossary-5 Diagnostic buffer The diagnostics buffer represe nts a buffered memory area in the CPU. It stores diagnostic events in the order of their occurrence. Diagnostic Interrupt Modules capable of diagnostics operations repo rt detected syste m errors to the C[...]

  • Page 222

    Glossary CPU 31xC and CPU 31x, Technical data Glossary-6 Manual, Edition 08/2004, A5E00105475-05 Error response Reaction to a runtime error. Reac tions of the operating system: It sets the automation system to STOP, indicates the e rror, or calls an OB in which th e user can program a reaction. ERTEC See ASIC Fast Ethernet Fast Ethernet describes t[...]

  • Page 223

    Glossary CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 Glossary-7 Function block According to IEC 1131-3, a function block (FB) is a --> code bl ock with --> static data. An FB allows the user program to pass parameters. Function blocks are therefore suitable for programming frequentl y occurring complex functio[...]

  • Page 224

    Glossary CPU 31xC and CPU 31x, Technical data Glossary-8 Manual, Edition 08/2004, A5E00105475-05 Chassis ground is the totality of all the interco nnected passiv e parts of a piece of equipment on which dangerous fault-voltage cann ot occur. GSD file The properties of a PROFINET de vice are described in a GSD file (General Station Description) that[...]

  • Page 225

    Glossary CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 Glossary-9 Interrupt, delay The delay interrupt belongs to one of the priority classes in S IMATIC S7 program processing. It is generated on expi ration of a time started in the user program. A corresponding OB will be processed. See Interrupt, delay Interrupt, di[...]

  • Page 226

    Glossary CPU 31xC and CPU 31x, Technical data Glossary-10 Manual, Edition 08/2004, A5E00105475-05 IO device See PROFINET IO Controller See PROFINET IO Device See PROFINET IO Supervisor See PROFINET IO System IO supervisor See PROFINET IO Controller See PROFINET IO Device See PROFINET IO Supervisor See PROFINET IO System IO system See PROFINET IO Sy[...]

  • Page 227

    Glossary CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 Glossary-11 MAC address Each PROFINET device is assig ned a worldwi de unique device id en tifier in the factory. This 6-byte long device identif ier is the MAC address. The MAC address is divid ed up as follows: • 3 bytes vendor identifier a nd • 3 bytes devi[...]

  • Page 228

    Glossary CPU 31xC and CPU 31x, Technical data Glossary-12 Manual, Edition 08/2004, A5E00105475-05 Nesting depth A block can be called from another by means of a block call. Nesting depth is referred to as the number of simultaneously calle d code blocks. Network A network is a larger communication system that allows d ata exc hange between a large [...]

  • Page 229

    Glossary CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 Glossary-13 suitable basic factory settin g which can be cus tomized in STEP 7 . There are static and dynamic pa rameters Parameters, dynamic Unlike static parameters, you ca n chang e dynamic module parame t ers during runtime by calling an SFC in the user progr [...]

  • Page 230

    Glossary CPU 31xC and CPU 31x, Technical data Glossary-14 Manual, Edition 08/2004, A5E00105475-05 Process interrupt A process interrupt is triggered by interrupt-triggering module s as a result of a specific event in the process. The process interrupt is reported to the CPU. T he assigned organizatio n block will be processed accord ing to interrup[...]

  • Page 231

    Glossary CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 Glossary-15 PROFINET Within the framework of Totally In tegrated Automation (TIA), PR OFINET repre sents a consequent enhancement of: • PROFIBUS DP, the proven field bus, and • Industrial Ethernet, the communi cation bus at cell level. Experience gained from b[...]

  • Page 232

    Glossary CPU 31xC and CPU 31x, Technical data Glossary-16 Manual, Edition 08/2004, A5E00105475-05 PROFINET IO Within the framework of PROFINET, PROFINET IO is a communicatio n conc ept for the implementation of modular, distributed applications. PROFINET IO allows you to creat e automation solutions, which ar e familiar to you from PROFIBUS. That i[...]

  • Page 233

    Glossary CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 Glossary-17 Proxy The PROFINET device with proxy functionality is the substitute for a PROFIBUS device on Ethernet. The proxy functionality allows a PROFIBUS device to c ommunicate not only with its master but also with all nodes on PROFINET. You can integrate exi[...]

  • Page 234

    Glossary CPU 31xC and CPU 31x, Technical data Glossary-18 Manual, Edition 08/2004, A5E00105475-05 Restart On CPU start-up (e.g. after is swi tched from STOP to RUN mode v ia selector switch or with POWER ON), OB100 (restart) is i nitially executed, pri or to cycl ic program execution (OB1). On restart, the input process image is read in and the STE[...]

  • Page 235

    Glossary CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 Glossary-19 Signal module Signal modules (SM) form the inte rface between the pro cess and the PLC. There are digital input and output modules (input/ output module, digital) and ana log input and output modules (input/output module, analog). SIMATIC Name of produ[...]

  • Page 236

    Glossary CPU 31xC and CPU 31x, Technical data Glossary-20 Manual, Edition 08/2004, A5E00105475-05 STEP 7 Engineering system. Contai ns pro gramming software for the creat ion of user programs for SIMATIC S7 controllers. Subnet mask The bits set in the subnet mas k decides the part of the IP addr ess that contains t he address of the subnet/network.[...]

  • Page 237

    Glossary CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 Glossary-21 System diagnostics System diagnostics refers to t he detection, evaluation and si gn aling of errors which o ccur within the PLC, Examples of such error/faults incl ude: Program errors or failures on modules. System errors can be i ndicated by LEDs or [...]

  • Page 238

    Glossary CPU 31xC and CPU 31x, Technical data Glossary-22 Manual, Edition 08/2004, A5E00105475-05 Token Allows access to the bus for a limited time. Topology Structure of a network. Common stru ctures include: • Bus topology • Ring topolo gy • Star topology • Tree topolo gy Transmission rate Data transfer rate (in bps) Twisted Pair Fast Eth[...]

  • Page 239

    Glossary CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 Glossary-23 WAN Network with a span beyond that o f a local area network allowin g, for example, intercontinental operation. Legal r ights do not belong to the u ser but to the provider of the transmission networks.[...]

  • Page 240

    Glossary CPU 31xC and CPU 31x, Technical data Glossary-24 Manual, Edition 08/2004, A5E00105475-05[...]

  • Page 241

    CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 Index-1 Index A Aim of this Documentation, iii Analog inputs Configuration, 6-41 Not connected, 6-38 Technical data, 6-51 Analog outputs Not connected, 6-38 Technical data, 6-53 Applicability of this manual, A-1, A-2 Application area covered by this manual , iii Applicatio[...]

  • Page 242

    Index CPU 31xC and CPU 31x, Technical data Index-2 Manual, Edition 08/2004, A5E00105475-05 D Data consistency, 3-16 Diagnostics Standard I/O, 6-46 Technological functions, 6-46 Differences between the CPUs, 2-3 Digital inputs Configuration, 6-39 Technical data, 6-47 Digital outputs Configuration, 6-41 Fast, 6-48 Technical data, 6-49 Download of blo[...]

  • Page 243

    Index CPU 31xC and CPU 31x, Technical data Manual, Edition 08/2004, A5E00105475-05 Index-3 P Power supply Connector, 2-3, 2-6, 2-8, 2-10 Process interrupt processing, 5-23 PROFIBUS, 3-16, Glossary-15 PROFIBUS International, 3-17 PROFINET Implementation, 3-17 PROFINET, 3-4, 3-16 interface, 3-3 Objectives, 3-17 PROFINET CBA, 3-17 PROFINET IO, 3-17 PR[...]

  • Page 244

    Index CPU 31xC and CPU 31x, Technical data Index-4 Manual, Edition 08/2004, A5E00105475-05 T Technical data Analog inputs, 6-51 Analog outputs, 6-53 CPU 312C, 6-3, 7-3, 7-8, 7-13, 7-26, 7-33 CPU 313C, 6-8 CPU 313C-2 DP, 6-14 CPU 313C-2 PtP, 6-14 CPU 314C-2 DP, 6-21 CPU 314C-2 PtP, 6-21 Digital inputs, 6-47 Digital outputs, 6-49 U Upload, 4-12, 4-13[...]