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Texas Instruments ADS61xx manual

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Table of contents for the manual

  • Page 1

    ADS61xx and ADS61B23EVM User's Guide Literature Number: SLAU206B September 2007 – Revised April 2008[...]

  • Page 2

    2 SLAU206B – September 2007 – Revised April 2008 Submit Documentation Feedback[...]

  • Page 3

    Contents 1 Overview ............................................................................................................................. 5 1.1 ADS61xx/ADS61B23 EVM Quick-Start Procedure ................................................................... 5 2 Circuit Description ...............................................................[...]

  • Page 4

    www.ti.com List of Figures 1 TI ADC SPC Interface Screen ........................................................................................... 10 2 Top Silkscreen .............................................................................................................. 16 3 Component Side ..................................................[...]

  • Page 5

    1 Overview 1.1 ADS61xx/ADS61B23 EVM Quick-Start Procedure User's Guide SLAU206B – September 2007 – Revised April 2008 This user's guide gives a general overview of the evaluation module (EVM) and provides a general description of the features and functions to be considered while using this module. This manual is applicable to the ADS6[...]

  • Page 6

    2 Circuit Description 2.1 Schematic Diagram 2.2 ADC Circuit Function 2.2.1 ADC Operational Mode 2.2.2 EVM Power Connections 2.2.3 ADC Analog Inputs Circuit Description www.ti.com The schematic diagram for the EVM is in Section 6.3 . The following sections describe the function of individual circuits. See the relevant data sheet for device operating[...]

  • Page 7

    2.2.4 ADC Clock Input 2.2.5 ADC Digital Outputs www.ti.com Circuit Description Note that the THS4509 used on this EVM is pinout compatible with the THS4508 , THS4511 , THS4513 , and THS4520 . Users can easily interchange the amplifier on this EVM and pick the appropriate amplifier based on common-mode range, power supplies, and frequency of operati[...]

  • Page 8

    2.2.6 Jumper Selections Circuit Description www.ti.com Table 1. Breakout Board Pin Assignments ADS6122/23/B23/24/25 J4 PIN ADS6142/43/44/45 DESCRIPTION DESCRIPTION 1 GND GND 2 CLK CLK 3 GND GND 4 NC NC 5 GND GND 6 NC Data bit 0 (LSB) 7 GND GND 8 NC Data bit 1 9 GND GND 10 Data bit 0 (LSB) Data bit 2 11 GND GND 12 Data bit 1 Data bit 3 13 GND GND 14[...]

  • Page 9

    www.ti.com Circuit Description Table 2. Jumpers Description Reference Designator Default Selection Optional Selection Parallel mode: SEN pin J1 5–6, Offset binary, CMOS output Multiple choices voltage bias SEN control J2 2–3, EVM controlled 1–2, USB or FPGA controlled ADC control mode J3 2–3, Parallel mode 1–2, serial mode Parallel mode: [...]

  • Page 10

    3 TI ADC SPI Control Interface 3.1 Installing the ADC SPI Control Software TI ADC SPI Control Interface www.ti.com This section describes the software features accompanying the EVM kit. The TI ADC SPI control software provides full control of the SPI interface, allowing users to write to any of the ADC registers found in the ADC data sheet. For mos[...]

  • Page 11

    3.2 Setting Up the EVM for ADC SPI Control 3.3 Using the TI ADC SPI Interface Software 3.3.1 SPI Register Writes 3.3.2 SPI Register Write Using a Script File 3.3.2.1 ADS61xx Frequently Used Registers www.ti.com TI ADC SPI Control Interface Users who wish to use the ADC SPI interface must supply 5 VDC to J20, which provides power to the USB circuit.[...]

  • Page 12

    TI ADC SPI Control Interface www.ti.com Table 4. ADS61xx Frequently Used Registers Default Value Alternate Value ADS61xx Reset 2s Complement Straight Binary CMOS DDR LVDS Powerdown: OFF Powerdown On No Course Gain 3.5-dB Course Gain INT Reference EXT Reference Bit-Wise (LVDS Only) Byte-Wise Test Mode: None Multiple Options 12 SLAU206B – September[...]

  • Page 13

    4 Connecting to FPGA Platforms 4.1 TSW1100 4.2 TSW1200 www.ti.com Connecting to FPGA Platforms The ADS61xx/ADS61B23 EVM provides several connection options to mate the EVM to various FPGA development platforms and FPGA-based capture boards. Using the accompanying CMOS breakout board, users can easily mate TI's TSW1100 capture board to the ADS6[...]

  • Page 14

    5 ADC Evaluation 5.1 Hardware Selection 5.1.1 Analog Input Signal Generator 5.1.2 Clock Signal Generator ADC Evaluation www.ti.com This section describes how to set up a typical ADC evaluation system that is similar to what TI uses to perform testing for data-sheet generation. Consequently, the information in this section is generic in nature and i[...]

  • Page 15

    5.2 Coherent Input Frequency Selection www.ti.com ADC Evaluation Typical ADC analysis requires users to collect the resulting time-domain data and perform a Fourier transform to analyze the data in the frequency domain. A stipulation of the Fourier transform is that the signal must be continuous-time; however, this is impractical when looking at a [...]

  • Page 16

    6 Physical Description 6.1 PCB Layout Physical Description www.ti.com This section describes the physical characteristics and PCB layout of the EVM. The EVM is constructed on a four-layer, 0.062-inch thick PCB using FR-4 material. The individual layers are shown in Figure 2 through Figure 6 . The layout features a split ground plane; however, simil[...]

  • Page 17

    www.ti.com Physical Description Figure 3. Component Side SLAU206B – September 2007 – Revised April 2008 17 Submit Documentation Feedback[...]

  • Page 18

    Physical Description www.ti.com Figure 4. Ground Plane 1 18 SLAU206B – September 2007 – Revised April 2008 Submit Documentation Feedback[...]

  • Page 19

    www.ti.com Physical Description Figure 5. Power Plane 1 SLAU206B – September 2007 – Revised April 2008 19 Submit Documentation Feedback[...]

  • Page 20

    Physical Description www.ti.com Figure 6. Bottom Side 20 SLAU206B – September 2007 – Revised April 2008 Submit Documentation Feedback[...]

  • Page 21

    6.2 Bill of Materials www.ti.com Physical Description Table 5. Bill of Materials Qty Reference Not Part Foot Print Part Number Manufacturer Installed 5 C1, C5, C8, C52, 33 µ F TANT_B B45196H2336M209 Kemet C54 5 C2, C9, C30, C56, 10 µ F 805 ECJ-2FB0J106K Panasonic C57 3 C3, C6, C31 1 µ F 603 ECJ-1VB1A105K Panasonic 43 C4, C7, 0.1 µ F 603 ECJ-1VB[...]

  • Page 22

    Physical Description www.ti.com Table 5. Bill of Materials (continued) Qty Reference Not Part Foot Print Part Number Manufacturer Installed 0 R33 Not 200 Ω 402 ERJ-2RKF2000X Panasonic installed 2 R36, R48 348 Ω 603 ERJ-3EKF3480V Panasonic 0 R37, R45 Not 499 Ω 603 ERJ-3EKF4990V Panasonic installed 2 R39, R43 69.8 Ω 603 ERJ-3EKF69R8V Panasoni[...]

  • Page 23

    6.3 EVM Schematics PD VREF1 SIGNAL_IN +5V_AMP -VSS_AMP +5V_AMP AGND AMP+ AMP- AMP+ AMP- VREF SH2 IN_M SH2 IN_P SH2 VREF SH2 Default:Short2-3 Default:Short1-2 Default:Short1-2 R26 0OHM R26 0OHM R44 100 R44 100 C76 18pF C76 18pF T1 TC4-1W T1 TC4-1W 3 2 1 6 5 4 C34 .1uF C34 .1uF 1 2 R43 69.8 R43 69.8 R37 499 DoNotInstall [...]

  • Page 24

    ICLKP ICLKM SEN SDA SCLOCK PDWN SEN RESET SCLOCK +3.3VD +3.3V A +3.3VD +3.3VD +3.3VD +3.3VD +3.3VD +3.3VD IN_M SH1 IN_P SH1 D2_D3_P SH4 D0_D1_P SH4 D0_D1_M SH4 D2_D3_M SH4 D4_D5_P SH4 D4_D5_M SH4 D6_D7_P SH4 D6_D7_M SH4 ICLKP SH3 ICLKM SH3 ADCRESET SH5 SDA T A SH5 VREF SH1 PDN SH5 CS SH5 SCLK SH5 FPGA_SEN SH4 FPGA_SCLK SH4 FPGA_SDA T A SH4 CLKOUTP [...]

  • Page 25

    ADCCLK- CLKOUT CLKOUT ADCCLK+ CLK- CLK+ +3.3V_AUX +3.3V_AUX +3.3V_AUX CDC_CLKM SH4 CDC_CLKP SH4 ICLKP SH2 ICLKM SH2 Default:Short2-3 Default:Short1-2 Default:Short1-2 Default:Short1-2 R29 49.9 1/10W 1% R29 49.9 1/10W 1% C16 .1uF 16V C16 .1uF 16V 1 2 R60 130 R60 130 1 2 C32 .1uF 16V C32 .1uF 16V 1 2 R31 49.9 R31 49.9 JP8 JP8[...]

  • Page 26

    D12_D13_P SH2 D12_D13_M SH2 D10_D1 1_P SH2 D10_D1 1_M SH2 D8_D9_P SH2 D8_D9_M SH2 CLKOUTP SH2 CLKOUTM SH2 D6_D7_P SH2 D6_D7_M SH2 D4_D5_P SH2 D4_D5_M SH2 D2_D3_P SH2 D2_D3_M SH2 D0_D1_P SH2 D0_D1_M SH2 CDC_CLKP SH3 CDC_CLKM SH3 FPGA_SCLK SH2 FPGA_SEN SH2 FPGA_SDA T A SH2 J10 CONN_QTH_30X2-D-A J10 CONN_QTH_30X2-D-A 2 4 6 8 10 12 14 16 18 20 22 24 26[...]

  • Page 27

    +3.3VD_IN 5V_IN +3.3V A_IN +3.3V A +3.3VD 5V +5V_AMP C3 1uF C3 1uF 1 2 C4 .1uF C4 .1uF 1 2 J13 RED +3.3V A_IN J13 RED +3.3V A_IN C30 10uF 6.3V C30 10uF 6.3V 1 2 L1 68 L1 68 1 2 + C8 33uF + C8 33uF 1 2 + C52 33UF 10V + C52 33UF 10V 1 2 + C1 33uF + C1 33uF 1 2 L2 68 L2 68 1 2 C53 .1uF 16V C53 .1uF 16V + C5 33uF + C5 33uF 1 2 J20 RED +5V_IN J20 RED +5[...]

  • Page 28

    GND D6 D9 D1 D3 D7 D5 CLK D13 D0 D2 D8 D10 D12 D1 1 D4 D7 D6 D5 D4 D3 D2 D1 D0 D13 D12 D1 1 D10 D9 D8 CLK J1 CONN_QSH_30X2-D-A J1 CONN_QSH_30X2-D-A 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 1 1 13 15 17 19 21 23 25 27 29 31 33 35 37 39 G1 G2 G3 G4 G5 G6 G7 G8 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 [...]

  • Page 29

    EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling th[...]

  • Page 30

    IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders[...]