Texas Instruments SM320C6455-EP manual

SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR Data Manual JANUARY 2008 SPRS462B[...]

SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR Data Manual Literature Number: SPRS462B SEPTEMBER 2007 – Revised JANUARY 2008 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of a[...]

Contents SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 1 Features .............................................................................................................................. 7 1.1 ZTZ/GTZ BGA Package (Bottom View) ...........................................................[...]

SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 6.2 Recommended Operating Conditions .................................................................................. 101 6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise [...]

SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.8.2 PLL2 Controller Memory Map ................................................................................ 153 7.8.3 PLL2 Controller Register Descriptions ...................................................................... 153 7.8.3.1 P[...]

SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.17 Enhanced Turbo Decoder Coprocessor (TCP2) ...................................................................... 221 7.17.1 TCP2 Device-Specific Information ........................................................................... 221 7.17[...]

www.ti.com 1 Features SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Parameters • Controlled Baseline • Endianess: Little Endian, Big Endian – One Assembly Site – Test Site • 64 Bit External Memory Interface (EMIFA) – One Fabrication Site – Glueless Interface to Asynchronous Mem[...]

www.ti.com 1.1 ZTZ/GTZ BGA Package (Bottom View) ZTZ/GTZ 697-PIN BALL GRID ARRA Y (BGA) P ACKAGE ( BOTT OM VIEW ) A 2 B 1 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 27 28 29 AG AH AJ NOTE: The ZTZ mechanical package designator represents the version of the GTZ package with[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multiply through[...]

www.ti.com 1.3 Functional Block Diagram L2 Memory Controller (Memory Protect/ Bandwidth Mgmt) Serial Rapid I/O DDR2 Mem Ctlr System (B) C64x+ DSP Core Data Path B B Register File B31−B16 B15−B0 Instruction Fetch Data Path A A Register File A31−A16 A15−A0 Device Configuration Logic .L1 .S1 .M1 xx xx .D1 .D2 .M2 xx xx .S2 .L2 64 SBSRAM SRAM L[...]

www.ti.com 2 Device Overview 2.1 Device Characteristics SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-1 , provides an overview of the C6455 DSP. The tables show significant features of the C6455 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and th[...]

www.ti.com 2.2 CPU (DSP Core) Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-1. Characteristics of the C6455 Processor (continued) HARDWARE FEATURES C6455 Process Technology µ m 0.09 µ m Product Preview (PP), Advance Information (AI), Product Status (2) PD or Production [...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Other new features include: • SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size ass[...]

www.ti.com src2 src2 .D1 .M1 .S1 .L1 long src odd dst src2 src1 src1 src1 src1 even dst even dst odd dst dst1 dst src2 src2 src2 long src DA1 ST1b LD1b LD1a ST1a Data path A Odd register file A (A1, A3, A5...A31) Odd register file B (B1, B3, B5...B31) .D2 src1 dst src2 DA2 LD2a LD2b src2 .M2 src1 dst1 .S2 src1 even dst long src odd dst ST2a ST2b lo[...]

www.ti.com 2.3 Memory Map Summary SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-2 shows the memory map address ranges of the C6455 device. The external memory configuration register address ranges in the C6455 device begin at the hex address location 0x7000 0000 for EMIFA and hex add[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-2. C6455 Memory Map Summary (continued) MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE EMAC Descriptor Memory 8K 02C8 2000 - 02C8 3FFF Reserved 496K 02C8 4000 - 02CF FFFF RapidIO Control Registers 256K 02D0 0000 [...]

www.ti.com 2.4 Boot Sequence 2.4.1 Boot Modes Supported SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections and the DSP's internal registers are programmed with predetermined values[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 software such as Code Composer Studio. For the PCI host boot, the CPU is out of reset, but it executes an IDLE instruction until a DSP interrupt is generated by the host. The host can generate a DSP interrupt through the PCI peripheral[...]

www.ti.com 2.4.2 2nd-Level Bootloaders SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The SRIO boot is a software boot mode. Any of the boot modes can be used to download a 2nd-level bootloader. A 2nd-level bootloader allows for any level of customization to current boot methods as well as de[...]

www.ti.com 2.5 Pin Assignments 2.5.1 Pin Map AG AF AE AD AC AB AA Y W V U T R 13 12 1 1 10 9 8 7 6 5 4 3 2 1 13 12 1 1 10 9 8 7 6 5 4 3 2 1 CLKR1/ GP[0] HD15/ AD15 HD2/ AD2 URADDR0/ PGNT/ GP[12] HD22/ AD22 DV DD 33 RSV15 UXADDR1/ PIDSEL RSV16 HDS1/ PSERR HINT/ PFRAME DV DD 33 HHWIL/ PCLK V SS HD12/ AD12 HD24/ AD24 RSV03 HD20/ AD20 HD18/ AD18 HD6/ A[...]

www.ti.com AG AF AE AD AC AB AA Y W V U T R 17 18 19 20 21 22 23 24 25 26 27 28 29 17 18 19 20 21 22 23 24 25 26 27 28 29 SDA AED27 V SS ASADS/ ASRE AED17 AHOLD PLL V1 AEA13/ LENDIAN AEA4/ SYSCLKOUT _EN AEA5/ MCBSP1 _EN AEA6/ PCI66 AECLKOUT ACE5 ACE4 ABA0/ DDR2_EN ABE7 ACE2 RSV41 AAOE/ ASOE RSV42 RSV44 ABE2 ABE0 AED29 AED31 ACE3 AEA1/ CFGGP1 AEA1 1[...]

www.ti.com C D E F G H J K L M N P 17 18 19 20 21 22 23 24 25 26 27 28 29 17 18 19 20 21 22 23 24 25 26 27 28 29 RSV09 AED52 DV DD 33 V SS V SS V SS AECLKIN AEA9/ MACSEL0 CLKIN1 DV DD 33 AEA15/ AECLKIN _SEL AED40 AED44 AED42 AED34 ABE6 AED32 ABE4 AEA18/ BOOT MODE2 AED37 ABUSREQ AED46 AEA16/ BOOT MODE0 AEA19/ BOOT MODE3 AHOLDA AEA10/ MACSEL1 V SS V [...]

www.ti.com A D E F G H J K L M N P 13 12 1 1 10 9 8 7 6 5 4 3 2 1 13 12 1 1 10 9 8 7 6 5 4 3 2 1 RGRXD2 RGTXD3 DV DD 33 UXDA T A2/ MTXD2 V SS UXDA T A0/ MTXD0/ RMTXD0 CV DD MON UXDA T A6/ MTXD6 V SS URADDR3/ PREQ/ GP[15] URADDR2/ PINT A/ GP[14] URDA TA2/ MRXD2 URDA TA3/ MRXD3 URDA TA0/ MRXD0/ RMRXD0 V SS UXDA T A3/ MTXD3 UXSOC/ MCOL URDA TA5/ MRXD5[...]

www.ti.com 2.6 Signal Groups Description • TRST IEEE Standard 1 149.1 (JT AG) Emulation Reserved Reset and Interrupts Control/Status TDI TDO TMS TCK NMI RESET RSV03 RSV04 Clock/PLL1 and PLL Controller CLKIN1 EMU0 EMU1 SYSCLK4/GP[1] (A) EMU14 EMU15 EMU16 EMU17 RSV02 EMU18 RSV07 RSV09 RSV05 RSV43 RSV44 RSV42 • • • • • RESETST A T CLKIN2 P[...]

www.ti.com A. This pin functions as GP[1] by default. For more details, see the Device Configuration section of this document. B. These McBSP1 peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins. For more details, see the Device Configuration section of this document. C. These UT OPI[...]

www.ti.com ACE4 (A ) AECLKOUT AED[63:0] ACE3 (A ) ACE2 (A ) AEA[19:0] AARDY Data Memory Map Space Select Address Byte Enables 64 20 External Memory I/F Control EMIF A (64-bit Data Bus) AECLKIN AHOLD AHOLDA ABUSREQ Bus Arbitration ABE3 ABE2 ABE1 ABE0 ASWE/AA WE DDR2CLKOUT DED[31:0] DCE0 DEA[13:0] Data Memory Map Space Select Address Byte Enables 32 [...]

www.ti.com McBSPs (Multichannel Buffered Serial Ports) (B) CLKX0 FSX0 DX0 CLKR0 FSR0 DR0 T ransmit McBSP0 Receive Clock CLKX1/GP[3] FSX1/GP[1 1] DX1/GP[9] CLKR1/GP[0] FSR1/GP[10] DR1/GP[8] T ransmit McBSP1 Receive Clock HHWIL/PCLK HCNTL0/PST OP HCNTL1/PDEVSEL Data Register Select Half-W ord Select Control HPI (A ) (Host-Port Interface) 32 HAS/PP AR[...]

www.ti.com RGTXCTL, RGRXCTL URSOC/MRXER/RMRXER, URENB/MRXDV , URCLA V/MCRS/RMCRSDV , UXSOC/MCOL, UXENB/MTXEN/RMTXEN Ethernet MAC (EMAC) and MDIO (B) UXADDR3/MDIO UXADDR4/MDCLK MDIO Clock Clocks Error Detect and Control Input/Output Receive RGMDIO RGMDCLK RGTXD[3:0] A. RGMII signals are mutually exclusive to all other EMAC signals. B. These EMAC pin[...]

www.ti.com URADDR2/PINT A/GP[14] Control/Status URADDR4/PCLK/GP[2] URDA T A0/MRXD0/RMRXD0 URDA T A1/MRXD1/RMRXD1 URADDR3/PREQ /GP[15] URADDR1/PRST /GP[13] URADDR0/PGNT /GP[12] Receive URDA T A7/MRXD7 URDA T A4/MRXD4 URDA T A3/MRXD3 URDA T A2/MRXD2 URCLA V/MCRS/RMCRSDV URENB/MRXDV URDA T A5/MRXD5 URDA T A6/MRXD6 URSOC/MRXER/RMRXER URCLK/MRCLK Clock [...]

www.ti.com 2.7 Terminal Functions SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The terminal functions table ( Table 2-3 ) identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin ha[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS RESET AG14 I Device reset Nonmaskable interrupt, edge-driven (rising edge) Any noise on th[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. URADDR2/ PINTA (5) / UTOPIA received address pin 2 (URADDR2) ( I ) or PCI interrupt A ( O/Z ) or P3 I/O/Z GP[14] GP[14] ( I/O/Z ) default] URADD[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. EMIFA (64 BIT) - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY ABA1/EMIFA_EN V25 O/Z IPD EMIFA bank address control (ABA[1:0]) • Active-low ba[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. EMIFA (64 BIT) - ADDRESS AEA19/BOOTMODE3 N25 EMIFA external address (word address) ( O/Z ) Controls initialization of the DSP modes at reset ( I[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. AEA10/MACSEL1 M25 • EMAC/MDIO interface select bits (MACSEL[1:0]) If the EMAC and MDIO peripherals are enabled, AEA12 pin (UTOPIA_EN AEA9/MACS[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. EMIFA (64 BIT) - DATA AED63 F25 AED62 A27 AED61 C27 AED60 C28 AED59 E27 AED58 D28 AED57 D27 AED56 F27 AED55 G25 AED54 G26 AED53 A28 AED52 F28 AE[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. AED21 AD29 AED20 AJ28 AED19 AF29 AED18 AH28 AED17 AE29 AED16 AG28 AED15 AF28 AED14 AH26 AED13 AE28 AED12 AE26 AED11 AD26 I/O/Z IPU EMIFA externa[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. DSDDQS3 E23 I/O/Z DSDDQS2 E20 I/O/Z DDR2 Memory Controller data strobe [3:0] positive DSDDQS1 E8 I/O/Z DSDDQS0 E11 I/O/Z DSDDQS3 D23 I/O/Z DDR2 [...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. DDR2 MEMORY CONTROLLER (32 BIT) - DATA DED31 B25 DED30 A25 DED29 B24 DED28 A24 DED27 D22 DED26 C22 DED25 B22 DED24 A22 DED23 D21 DED22 C21 DED21[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. MULTICHANNEL BUFFERED SERIAL PORT 1 AND MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP1 and McBSP0) McBSP external clock source (as opposed to inter[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. UXDATA7/MTXD7 N5 UXDATA6/MTXD6 M3 UTOPIA 8 bit transmit data bus ( I/O/Z ) [default] or EMAC MII 4 bit transmit data bus ( I/O/Z ) [default] or [...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. RAPIDIO SERIAL PORT RIOCLK AF15 I RapidIO serial port source (reference) clock RIOCLK AG15 I Negative RapidIO serial port source (reference) clo[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. URDATA7/MRXD7 M2 URDATA6/MRXD6 H2 UTOPIA 8 bit Receive Data Bus ( I ) [default] or EMAC receive data bus for MII URDATA5/MRXD5 L2 [default], RMI[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. ETHERNET MAC (EMAC) [RGMII] If the Ethernet MAC (EMAC) and MDIO are enabled (AEA12 driven low [UTOPIA_EN = 0]), there are two additional configu[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. Reserved. This pin must be connected to ground (V SS ) via a 200- Ω resistor for proper device operation. NOTE: If the RGMII mode of the EMAC [...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. SUPPLY VOLTAGE MONITOR PINS Die-side 1.2-V core supply (CV DD ) voltage monitor pin. The monitor pins indicate the voltage on the die and, there[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. U16 SRIO interface supply: 1.25-V core supply voltage (-1000 and -1200 devices) V15 DV DDRM S 1.2-V core supply voltage (-850 and -720 devices).[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. A29 E26 E28 G2 H23 H28 J6 J24 K1 K7 K23 L24 M7 M23 M28 N24 P6 P28 R1 R6 R23 DV DD33 T7 S 3.3-V I/O supply voltage T24 U23 V1 V7 V24 W23 Y7 Y24 A[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. AD5 AD7 AD14 AD18 AD22 AD24 AE6 AE8 AE15 AF1 AF16 DV DD33 AF24 S 3.3-V I/O supply voltage AG12 AG17 AG23 AH14 AH16 AH24 AJ1 AJ7 AJ15 AJ25 AJ29 L[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. R18 T11 T13 T15 T17 T19 U12 1.25-V core supply voltage (-1000 and -1200 devices) CV DD S 1.2-V core supply voltage (-850 and -720 devices) U14 U[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. F20 F22 F24 G1 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 H6 H24 V SS GND Ground pins H29 J7 J23 K2 K6 K24 L7 L11 L13 L15 L17 L19 L23 M6 M12 M14 Submi[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. M16 M18 M24 M26 M29 N2 N13 N15 N17 N19 N23 P7 P12 P14 P16 P18 P29 V SS GND Ground pins R2 R7 R11 R13 R15 R17 R19 R24 T6 T12 T14 T16 T18 T23 U7 U[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. U15 U17 U19 U24 V2 V6 V12 V14 V16 V18 V23 W7 W11 W13 W15 W17 V SS GND Ground pins W19 W24 Y6 Y23 AA2 AA7 AA24 AB6 AB23 AC7 AC8 AC10 AC12 AC14 AC[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. AC20 AC22 AC24 AC28 AD6 AD13 AD15 AD17 AD19 AD21 AD23 AE4 AE7 AE16 AE18 AE20 AE22 AE24 V SS GND Ground pins AF2 AF19 AF21 AG13 AG16 AG20 AG24 AH[...]

www.ti.com 2.8 Development 2.8.1 Development Support 2.8.2 Device Support 2.8.2.1 Device and Development-Support Tool Nomenclature SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 In case the customer would like to develop their own features and software on the C6455 device, TI offers an extens[...]

www.ti.com SM=Qualifieddevice SM=HiRel(non-38535) A = 40 C to 1 05 C ( exten ded tem perat ure) - º º S = 55 C to 105 C (exten ded tem perat ure) - º º 2.8.2.2 Documentation Support SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 TI device nomenclature also includes a [...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 C6000 DSP platforms. SPRU970 TMS320C645x DSP DDR2 Memory Controller User's Guide. This document describes the DDR2 memory controller in the C645x digital-signal processors (DSPs). SPRU966 TMS320C645x DSP Enhanced DMA (EDMA3) Contr[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 signal processor (DSPs) of the C6000™ DSP family has been designed to perform this operation for IS2000 and 3GPP wireless standards. This document describes the operation and programming of the TCP. SPRUE48 TMS320C645x DSP Universal [...]

www.ti.com 3 Device Configuration 3.1 Device Configuration at Device Reset SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 On the C6455 device, certain device configurations like boot mode, pin multiplexing, and endianess, are selected at device reset. The status of the peripherals (enabled/di[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-1. C6455 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued) CONFIGURATION IPD/ NO. FUNCTIONAL DESCRIPTION PIN IPU (1) HPI peripheral bus width select (HPI_WIDTH). 0 HPI operates in HPI16 mode (default). HPI[...]

www.ti.com 3.2 Peripheral Configuration at Device Reset SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-1. C6455 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued) CONFIGURATION IPD/ NO. FUNCTIONAL DESCRIPTION PIN IPU (1) SYSCLKOUT Enable bit (SYSCLKOUT_EN). Select[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-2. PCI_EN, PCI66, PCI_EEAI, and HPI_WIDTH Peripheral Selection (HPI and PCI) CONFIGURATION PIN SETTING (1) PERIPHERAL FUNCTION SELECTED PCI66 PCI_EEAI HPI_WIDTH PCI_EN PIN HPI DATA HPI DATA 32 BIT PCI PCI AEA6 PIN AEA8 PIN AEA1[...]

www.ti.com 3.3 Peripheral Selection After Device Reset SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 On the C6455 device, peripherals can be in one of several states. These states are listed in Table 3-4 . Table 3-4. Peripheral States PERIPHERALS THAT CAN BE STATE DESCRIPTION IN THIS STATE H[...]

www.ti.com Reset Static Powerdown Disabled Enable In Progress Enabled Unlock the PERCFG0 register by using the PERLOCK register . W rite to the PERCFG0 register within 16 SYSCLK3 clock cycles to change the state of the peripherals. Poll the PERST A T registers to verify state change. SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – S[...]

www.ti.com 3.4 Device State Control Registers SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The C6455 device has a set of registers that are used to control the status of its peripherals. These registers are shown in Table 3-5 and described in the next sections. NOTE The device state control[...]

www.ti.com 3.4.1 Peripheral Lock Register Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 When written with correct 32 bit key (0x0F0A0B00), the Peripheral Lock Register (PERLOCK) allows one write to the PERCFG0 register within 16 SYSCLK3 cycles. NOTE The instructions that write to[...]

www.ti.com 3.4.2 Peripheral Configuration Register 0 Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The Peripheral Configuration Register (PERCFG0) is used to change the state of the peripherals. One write is allowed to this register within 16 SYSCLK3 cycles after the correct key [...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-7. Peripheral Configuration Register 0 (PERCFG0) Field Descriptions (continued) Bit Field Value Description 16 McBSP1CTL Mode control for McBSP1 0 Set McBSP1 to disabled mode 1 Set McBSP1 to enabled mode 15 Reserved Reserved. 1[...]

www.ti.com 3.4.3 Peripheral Configuration Register 1 Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The Peripheral Configuration Register (PERCFG1) is used to enable the EMIFA and DDR2 Memory Controller. EMIFA and the DDR2 Memory Controller do not have corresponding status bits in[...]

www.ti.com 3.4.4 Peripheral Status Registers Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The Peripheral Status Registers (PERSTAT0 and PERSTAT1) show the status of the C6455 peripherals. 31 30 29 27 26 24 Reserved HPISTAT McBSP1STAT R-0 R-0 R-0 23 21 20 18 17 16 McBSP0STAT I2CS[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-9. Peripheral Status Register 0 (PERSTAT0) Field Descriptions (continued) Bit Field Value Description 17:15 GPIOSTAT GPIO status 000 GPIO is in the disabled state 001 GPIO is in the enabled state 011 GPIO is in the static power[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 31 16 Reserved R-0 15 6 5 3 2 0 Reserved UTOPIASTAT PCISTAT R-0 R-0 R-0 LEGEND: R = Read only; - n = value after reset Figure 3-7. Peripheral Status Register 1 (PERSTAT1) - 0x02AC 0018 Table 3-10. Peripheral Status Register 1 (PERSTAT1[...]

www.ti.com 3.4.5 EMAC Configuration Register (EMACCFG) Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The EMAC Configuration Register (EMACCFG) is used to assert and deassert the reset of the Reduced Media Independent Interface (RMII) logic of the EMAC. For more details on how to [...]

www.ti.com 3.4.6 Emulator Buffer Powerdown Register (EMUBUFPD) Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The Emulator Buffer Powerdown Register (EMUBUFPD) is used to control the state of the pin buffers of emulator pins EMU[18:2]. These buffers can be powered down if the devi[...]

www.ti.com 3.5 Device Status Register Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The device status register depicts the device configuration selected upon device reset. Once set, these bits will remain set until a device reset. For the actual register bit names and their assoc[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-13. Device Status Register (DEVSTAT) Field Descriptions (continued) Bit Field Value Description 15 SYSCLKOUT_EN SYSCLKOUT Enable (SYSCLKOUT_EN) status bit Shows the status of which function is enabled on the SYSCLK4/GP[1] muxed[...]

www.ti.com 3.6 JTAG ID (JTAGID) Register Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-13. Device Status Register (DEVSTAT) Field Descriptions (continued) Bit Field Value Description 3:0 BOOTMODE[3:0] Boot mode configuration bits Shows the status of what device boot mode [...]

www.ti.com 3.7 Pullup/Pulldown Resistors 3.8 Configuration Examples SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Proper board design should ensure that input pins to the C6455 device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The C[...]

www.ti.com Shadingdenotesaperipheralmodulenotavailableforthisconfiguration. UTOPIA McBSP0 TIMER0 EMIF A GPIO PLL2 andPLL2 Controller TIMER1 PLL1 andPLL1 Controller DDR2 EMIF VCP2 AED[63:0] 64 AECLKIN, AARDY , AHOLD AEA[22:3], ACE[3:0] , ABE[7:0], AECLKOUT , ASDCKE, AHOLDA, ABUSREQ, ASADS /ASRE , AAOE/ASOE, AA WE /AS[...]

www.ti.com Shadingdenotesaperipheralmodulenotavailableforthisconfiguration. UTOPIA McBSP0 TIMER0 EMIF A GPIO TIMER1 PLL1 andPLL1 Controller DDR2 EMIF VCP2 AED[63:0] 64 AECLKIN, AARDY , AHOLD AEA[22:3], ACE[3:0] , ABE[7:0], AECLKOUT , ASDCKE, AHOLDA, ABUSREQ, ASADS /ASRE , AAOE/ASOE, AA WE /ASWE SCL SDA CLKIN1,PLL V1[...]

www.ti.com 4 System Interconnect 4.1 Internal Buses, Bridges, and Switch Fabrics SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 On the C6455 device, the C64x+ Megamodule, the EDMA3 transfer controllers, and the system peripherals are interconnected through two switch fabrics. The switch fabri[...]

www.ti.com 4.2 Data Switch Fabric Connections SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Figure 4-1 shows the connection between slaves and masters through the data switched central resource (SCR). Masters are shown on the right and slaves on the left. The data SCR connects masters to sla[...]

www.ti.com Serial RapidIO (Descriptor) EMAC HPI M M M 128-bit (SYSCLK2) M3 M0 S S M M M M S TCP2 VCP2 S McBSPs S UTOPIA S DDR2 Memory Controller S EMIF A S PCI S MASTER SLA VE S M Bridge CFG SCR S Bridge PCI M EDMA3 Channel Controller EDMA3 Transfer Controllers Megamodule M1 M2 S3 S0 S1 S2 M Serial RapidIO (Data) S S Events M Megamodule Data SCR Br[...]

www.ti.com 4.3 Configuration Switch Fabric SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 4-1. SCR Connection Matrix DDR2 MEMORY TCP2 VCP2 McBSPs UTOPIA2 CONFIGURATION SCR PCI EMIFA MEGAMODULE CONTROLLER TC0 Y Y N N N N Y Y Y TC1 N N Y Y Y Y Y Y Y TC2 N N N N N Y Y Y Y TC3 N N N N N Y Y[...]

www.ti.com Megamodule M CFG SCR S M M S TCP2 VCP2 S McBSPs S UTOPIA S T imers S HPI S PCI S S Bridge 7 GPIO S EMAC/MDIO M Data SCR S S I2C S S PLL Controllers (A) S S Device Configuration Registers (A) EDMA3 TC0 S EDMA3 TC1 S Serial RapidIO S S EDMA3 TC2 S EDMA3 CC S S EDMA3 TC3 S M M 32 (SYSCLK3) 32 (SYSCLK2) 32 (SYSCLK2) MUX 32 (SYSCLK2) 32 (SYSC[...]

www.ti.com 4.4 Bus Priorities SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 On the C6455 device, bus priority is programmable for each master. The register bit fields and default priority levels for C6455 bus masters are shown in Table 4-2 . The priority levels should be tuned to obtain the [...]

www.ti.com 5 C64x+ Megamodule A register file Data path 1 Data path 2 B register file D2 S2 xx xx M2 L2 Instruction decode M1 xx xx L1 S1 D1 16/32−bit instruction dispatch Instruction fetch SPLOOP buf fer 64 64 C64x+ CPU 256 32 L1D cache/SRAM Bandwidth management Memory protection L1 data memory controller IDMA 256 256 Bandwidth management L1 pro[...]

www.ti.com 4K bytes 8K bytes 16K bytes L1P memory 00E0 0000h 00E0 4000h 00E0 6000h 00E0 7000h 00E0 8000h direct mapped SRAM 1/2 dm 3/4 SRAM SRAM 7/8 All SRAM 000 001 010 01 1 100 Block base address L1P mode bits cache 4K bytes cache direct mapped cache direct mapped cache 4K bytes 8K bytes 16K bytes L1D memory 00F0 0000h 00F0 4000h 00F0 6000h 00F0 [...]

www.ti.com 32K bytes 32K bytes 64K bytes 128K bytes 1840K bytes L2 memory 0080 0000h 009C 0000h 009E 0000h 009F 0000h 009F 8000h 00A0 0000h 7/8 SRAM 4-way cache 4-way cache SRAM 15/16 4-way 31/32 SRAM 4-way SRAM 63/64 All SRAM 000 001 010 01 1 1 1 1 Block base address L2 mode bits cache SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B ?[...]

www.ti.com 5.2 Memory Protection 5.3 Bandwidth Management SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages[...]

www.ti.com 5.4 Power-Down Control 5.5 Megamodule Resets SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The C64x+ Megamodule supports the ability to power-down various parts of the C64x+ Megamodule. The power-down controller (PDC) of the C64x+ Megamodule can be used to power down L1P, the cach[...]

www.ti.com 5.6 Megamodule Revision SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The version and revision of the C64x+ Megamodule can be read from the Megamodule Revision ID Register (MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in Figure 5-5 and described in Table[...]

www.ti.com 5.7 C64x+ Megamodule Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-4. Megamodule Interrupt Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0180 0000 EVTFLAG0 Event Flag Register 0 (Events [31:0]) 0180 0004 EVTFLAG1 Event Flag Register 1 0180 0008 [...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-4. Megamodule Interrupt Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0180 0188 INTDMASK Dropped Interrupt Mask Register 0180 0188 - 0180 01BC - Reserved 0180 01C0 EVTASRT Event Asserting Register 0180 01C4 - 01[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-8. Megamodule Cache Configuration Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 0000 L2CFG L2 Cache Configuration Register 0184 0004 - 0184 001F - Reserved 0184 0020 L1PCFG L1P Configuration Register 0184 0024 L1PCC L1[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-8. Megamodule Cache Configuration Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 8298 MAR166 Controls EMIFA CE2 Range A600 0000 - A6FF FFFF 0184 829C MAR167 Controls EMIFA CE2 Range A700 0000 - A7FF FFFF 018[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-8. Megamodule Cache Configuration Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 8354 MAR213 Controls EMIFA CE5 Range D500 0000 - D5FF FFFF 0184 8358 MAR214 Controls EMIFA CE5 Range D600 0000 - D6FF FFFF 018[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-9. Megamodule L1/L2 Memory Protection Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 A210 L2MPPA4 L2 memory protection page attribute register 4 0184 A214 L2MPPA5 L2 memory protection page attribute register[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-9. Megamodule L1/L2 Memory Protection Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 A648 L1PMPPA18 L1P memory protection page attribute register 18 0184 A64C L1PMPPA19 L1P memory protection page attribute r[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-10. CPU Megamodule Bandwidth Management Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0182 0200 EMCCPUARBE EMC CPU Arbitration Control Register 0182 0204 EMCIDMAARBE EMC IDMA Arbitration Control Register 0182 0208 EMCSDMAAR[...]

www.ti.com 6 Device Operating Conditions 6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless 6.2 Recommended Operating Conditions SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Otherwise Noted) (1) Supply voltage range: CV DD (2) -0.5 V to 1.5 V DV DD33 (2) -0.5 V to 4.[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Recommended Operating Conditions (continued) MIN NOM MAX UNIT V SS Supply ground 0 0 0 V 3.3 V pins (except PCI-capable and 2 V I2C pins) PCI-capable 0.5DV DD33 DV DD33 + 0.5 V pins (1) V IH High-level input voltage I2C pins 0.7DV DD33[...]

www.ti.com 6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Operating Case Temperature (Unless Otherwise Noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT 3.3-V pins (except DV DD33 = MIN, PCI-capable and I2C 0.8DV[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) (continued) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT AECLKOUT, CLKR1/GP[0], CLKX1/GP[3], 8 mA SYSCLK4/GP[...]

www.ti.com 7 C64x+ Peripheral Information and Electrical Specifications 7.1 Parameter Information T ransmission Line 4.0 pF 1.85 pF Z0 = 50 Ω (see Note) T ester Pin Electronics Data Sheet T iming Reference Point Output Under T est NOTE: This data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and i[...]

www.ti.com 7.1.3 Timing Parameters and Board Routing Analysis 1 2 3 4 5 6 7 8 10 1 1 AECLKOUT (Output from DSP) AECLKOUT (Input to External Device) Control Signals (A) (Output from DSP) Control Signals (Input to External Device) Data Signals (B) (Output from External Device) Data Signals (B) (Input to DSP) 9 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL[...]

www.ti.com 7.2 Recommended Clock and Control Signal Transition Behavior 7.3 Power Supplies 7.3.1 Power-Supply Sequencing DV DD33 CV DD12 All other power supplies 1 2 7.3.2 Power-Supply Decoupling 7.3.3 Power-Down Operation SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 All clocks and control [...]

www.ti.com 7.3.4 Preserving Boundary-Scan Functionality on RGMII and DDR2 Memory Pins SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Peripherals used for booting, like I2C and HPI, are automatically enabled after device reset. It is not possible to disable these peripherals after the boot pro[...]

www.ti.com 7.4 Enhanced Direct Memory Access (EDMA3) Controller SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped slave endpoints on the device. The EDMA3 services software-driven paging trans[...]

www.ti.com 7.4.1 EDMA3 Device-Specific Information 7.4.2 EDMA3 Channel Synchronization Events SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant addressing mode is applicable to a very limited set [...]

www.ti.com 7.4.3 EDMA3 Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-3. C6455 EDMA3 Channel Synchronization Events (continued) EDMA BINARY EVENT NAME EVENT DESCRIPTION CHANNEL 18-19 - - None 20 001 0100 INTDST1 RapidIO Interrupt 1 21-27 - - None 28 [...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 0120 DCHMAP8 DMA Channel 8 Mapping Register 02A0 0124 DCHMAP9 DMA Channel 9 Mapping Register 02A0 0128 DCHMAP10 DMA Channel 10 Mappi[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 01DC DCHMAP55 DMA Channel 55 Mapping Register 02A0 01E0 DCHMAP56 DMA Channel 56 Mapping Register 02A0 01E4 DCHMAP57 DMA Channel 57 M[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 0368 DRAE5 DMA Region Access Enable Register for Region 5 02A0 036C DRAEH5 DMA Region Access Enable Register High for Region 5 02A0 [...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 0490 Q2E4 Event Queue 2 Entry Register 4 02A0 0494 Q2E5 Event Queue 2 Entry Register 5 02A0 0498 Q2E6 Event Queue 2 Entry Register 6[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 081C MPPA4 Memory Protection Page Attribute Register 4 02A0 0820 MPPA5 Memory Protection Page Attribute Register 5 02A0 0824 MPPA6 M[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 200C ECRH Event Clear Register High 02A0 2010 ESR Event Set Register 02A0 2014 ESRH Event Set Register High 02A0 2018 CER Chained Ev[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-5. EDMA3 Parameter RAM (1) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 4000 - 02A0 401F - Parameter Set 0 02A0 4020 - 02A0 403F - Parameter Set 1 02A0 4040 - 02A0 405F - Parameter Set 2 02A0 4060 - 02A0 407F - Parameter Set 3 [...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-6. EDMA3 Transfer Controller 0 Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A2 0284 DFSRCBREF Destination FIFO Set Destination Address B Reference Register 02A2 0288 DFDSTBREF Destination FIFO Set Destination[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-7. EDMA3 Transfer Controller 1 Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A2 8240 SAOPT Source Active Options Register 02A2 8244 SASRC Source Active Source Address Register 02A2 8248 SACNT Source Active Cou[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-8. EDMA3 Transfer Controller 2 Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A3 0008 - 02A3 00FC - Reserved 02A3 0100 TCSTAT EDMA3TC Channel Status Register 02A3 0104 - 02A3 011C - Reserved 02A3 0120 ERRSTAT E[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-8. EDMA3 Transfer Controller 2 Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A3 03C4 DFSRC3 Destination FIFO Source Address Register 3 02A3 03C8 DFCNT3 Destination FIFO Count Register 3 02A3 03CC DFDST3 Destin[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-9. EDMA3 Transfer Controller 3 Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A3 8350 DFBIDX1 Destination FIFO BIDX Register 1 02A3 8354 DFMPPRXY1 Destination FIFO Memory Protection Proxy Register 1 02A3 8358 -[...]

www.ti.com 7.5 Interrupts 7.5.1 Interrupt Sources and Interrupt Controller SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The CPU interrupts on the C6455 device are configured through the C64x+ Megamodule Interrupt Controller. The interrupt controller allows for up to 128 system events to be [...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-10. C6455 System Event Mapping (continued) EVENT NUMBER INTERRUPT EVENT DESCRIPTION 41 XINT0 McBSP0 transmit interrupt 42 RINT1 McBSP1 receive interrupt 43 XINT1 McBSP1 transmit interrupt 44 - 50 Reserved Reserved. Do not use. [...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-10. C6455 System Event Mapping (continued) EVENT NUMBER INTERRUPT EVENT DESCRIPTION Reserved. These system events are not connected and, therefore, 102 - 112 Reserved not used. 113 (1) L1P_ED1 L1P single bit error detected duri[...]

www.ti.com 7.5.2 External Interrupts Electrical Data/Timing 2 1 NMI SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-11. Timing Requirements for External Interrupts (1) (see Figure 7-6 ) -720 -850 A-1000/-1000 NO. UNIT -1200 MIN MAX 1 t w(NMIL) Width of the NMI interrupt pulse low 6P ns[...]

www.ti.com 7.6 Reset Controller 7.6.1 Power-on Reset ( POR Pin) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The reset controller detects the different type of resets supported on the C6455 device and manages the distribution of those resets throughout the device. The C6455 device has sever[...]

www.ti.com 7.6.2 Warm Reset ( RESET Pin) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 all the system clocks are invalid at this point. – The RESETSTAT pin stays asserted (low), indicating the device is in reset. 3. The POR pin may now be deasserted (driven high). When the POR pin is deass[...]

www.ti.com 7.6.3 Max Reset 7.6.4 System Reset 7.6.5 CPU Reset SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Section 2.4 , Boot Sequence ). NOTE The POR pin should be held inactive (high) throughout the Warm Reset sequence. Otherwise, if POR is activated (brought low), the minimum POR pulse w[...]

www.ti.com 7.6.6 Reset Priority SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 If any of the above reset sources occur simultaneously, the PLLCTRL only processes the highest priority reset request. The rest request priorities are as follows (high to low): • Power-on Reset • Maximum Reset [...]

www.ti.com 7.6.7 Reset Controller Register 7.6.7.1 Reset Type Status Register Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The reset type status (RSTYPE) register (029A 00E4) is the only register for the reset controller. This register falls in the same memory range as the PLL1 [...]

www.ti.com 7.6.8 Reset Electrical Data/Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-14. Timing Requirements for Reset (1) (2) (3) (see Figure 7-8 and Figure 7-9 ) -720 -850 A-1000/-1000 NO. UNIT -1200 MIN MAX 5 t w(POR) Pulse duration, POR low 256D (4) ns 6 t w(RESET) Pulse d[...]

www.ti.com CLKIN1 PCLK RESET RESETST A T SYSREFCLK (PLL1C) Z Group POR SYSCLK3 SYSCLK4 SYSCLK5 AECLKOUT (Internal) Boot and Device Configuration Pins Low Group High Group CLKIN2 Internal Reset PLL2C SYSREFCLK (PLL2C) SYSCLK1 (PLL2C) SYSCLK2 5 9 7 8 Undefined Undefined Low High-Z Undefined High PLL2 Unlocked PLL2 Locked (A) PLL2 Unlocked Clock V ali[...]

www.ti.com CLKIN1 CLKIN2 POR RESET (A)(B) RESETST A T Boot and Device Configuration Pins (C) 9 7 6 8 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 A. RESET should only be used after device has been powered up. For more details on the use of the RESET pin, see Section 7.6 , Reset Controller .[...]

www.ti.com 7.7 PLL1 and PLL1 Controller SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The primary PLL controller generates the input clock to the C64x+ megamodule (including the CPU) as well as most of the system peripherals such as the multichannel buffered serial ports (McBSPs) and the ext[...]

www.ti.com 1 0 0 1 DIVIDER D4 CLKIN1 (B) PLLEN (PLLCTL.[0]) SYSCLK2 SYSCLK3 AECLKIN (External EMIF Clock Input) EMIF A DIVIDER PREDIV DIVIDER D2 (A) DIVIDER D3 (A) AECLKOUT PLL V1 C2 C1 EMI Filter +1.8 V 560 pF 0.1 m F SYSCLK5 (Emulation and T race) SYSREFCLK (C64x+ MegaModule) AECLKINSEL (AEA[15] pin) DIVIDER D5 PLL1 Controller (EMIF Input Clock) [...]

www.ti.com 7.7.1.2 PLL1 Controller Operating Modes 7.7.1.3 PLL1 Stabilization, Lock, and Reset Times SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 • SYSCLK4 is used as the internal clock for the EMIFA. It is also used to clock other logic within the DSP. • SYSCLK5 clocks the emulation an[...]

www.ti.com 7.7.2 PLL1 Controller Memory Map SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1 with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). The PLL1 lo[...]

www.ti.com 7.7.3 PLL1 Controller Register Descriptions 7.7.3.1 PLL1 Control Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 This section provides a description of the PLL1 controller registers. For details on the operation of the PLL controller module, see the TMS320C645x DSP Software[...]

www.ti.com 7.7.3.2 PLL Multiplier Control Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL multiplier control register (PLLM) is shown in Figure 7-12 and described in Table 7-20 . The PLLM register defines the input reference clock frequency multiplier in conjunction with the P[...]

www.ti.com 7.7.3.3 PLL Pre-Divider Control Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL pre-divider control register (PREDIV) is shown in Figure 7-13 and described in Table 7-21 . 31 16 Reserved R-0 15 14 5 4 0 PREDEN Reserved RATIO R/W-1 R-0 R/W-2h LEGEND: R/W = Read/Write[...]

www.ti.com 7.7.3.4 PLL Controller Divider 4 Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL controller divider 4 register (PLLDIV4) is shown in Figure 7-14 and described in Table 7-22 . Besides being used as the EMIFA internal clock, SYSCLK4 is also used in other parts of the [...]

www.ti.com 7.7.3.5 PLL Controller Divider 5 Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL controller divider 5 register (PLLDIV5) is shown in Figure 7-15 and described in Table 7-23 . 31 16 Reserved R-0 15 14 5 4 0 D5EN Reserved RATIO R/W-1 R-0 R/W-3 LEGEND: R/W = Read/Write[...]

www.ti.com 7.7.3.6 PLL Controller Command Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is shown in Figure 7-16 and described in Table 7-24 . 31 16 Reserved R-0 15 2 1 0 Reserved Rsvd GOSE[...]

www.ti.com 7.7.3.7 PLL Controller Status Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in Figure 7-17 and described in Table 7-25 . 31 16 Reserved R-0 15 1 0 Reserved GOSTAT R-0 R-0 LEGEND[...]

www.ti.com 7.7.3.8 PLL Controller Clock Align Control Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL controller clock align control register (ALNCTL) is shown in Figure 7-18 and described in Table 7-26 . 31 16 Reserved R-0 15 5 4 3 2 0 Reserved ALN5 ALN4 Reserved R-0 R-1 R-1 [...]

www.ti.com 7.7.3.9 PLLDIV Ratio Change Status Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Whenever a different ratio is written to the PLLDIV n registers, the PLLCTRL flags the change in the PLLDIV ratio change status registers (DCHANGE). During the GO operation, the PLL controlle[...]

www.ti.com 7.7.3.10 SYSCLK Status Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The SYSCLK status register (SYSTAT) shows the status of the system clocks (SYSCLK n ). SYSTAT is shown in Figure 7-20 and described in Table 7-28 . 31 16 Reserved R-0 15 8 Reserved R-0 7 543210 Reserved [...]

www.ti.com 7.7.4 PLL1 Controller Input and Output Clock Electrical Data/Timing CLKIN1 2 3 4 4 5 1 SYSCLK4 3 4 4 2 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-29. Timing Requirements for CLKIN1 Devices (1) (2) (3) (see Figure 7-21 ) -720 -850 A-1000/-1000 -1200 NO. UNIT PLL MODES x1[...]

www.ti.com 7.8 PLL2 and PLL2 Controller PLL V2 PLL2 SYSCLK2(FromPLL1Controller) SYSCLK1 DDR2 Memory Controller EMAC CLKIN2 (B)(C) C162 560 pF EMIFilter +1.8V C161 0.1 F m PLL2Controller TMS320C6455DSP PLLM x20 /2 1 0 /x (A) 1 SYSREFCLK SYSCLK3(FromPLL1Controller) PLLREF PLLOUT DIVIDERD1 SM320C6455-EP FIXED-POINT DIG[...]

www.ti.com 7.8.1 PLL2 Controller Device-Specific Information 7.8.1.1 Internal Clocks and Maximum Operating Frequencies 7.8.1.2 PLL2 Controller Operating Modes SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 As shown in Figure 7-23 , the output of PLL2, PLLOUT, is divided by 2 and directly fed [...]

www.ti.com 7.8.2 PLL2 Controller Memory Map 7.8.3 PLL2 Controller Register Descriptions SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The memory map of the PLL2 controller is shown in Table 7-32 . Note that only registers documented here are accessible on the C6455. Other addresses in the PL[...]

www.ti.com 7.8.3.1 PLL Controller Divider 1 Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL controller divider 1 register (PLLDIV1) is shown in Figure 7-24 and described in Table 7-33 . 31 16 Reserved R-0 15 14 5 4 0 D1EN Reserved RATIO R/W-1 R-0 R/W-1 LEGEND: R/W = Read/Write[...]

www.ti.com 7.8.3.2 PLL Controller Command Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is shown in Figure 7-25 and described in Table 7-34 . 31 16 Reserved R-0 15 2 1 0 Reserved Rsvd GOSE[...]

www.ti.com 7.8.3.3 PLL Controller Status Register 7.8.3.4 PLL Controller Clock Align Control Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in Figure 7-26 and described in Table 7-35 . 31 1[...]

www.ti.com 7.8.3.5 PLLDIV Ratio Change Status Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Whenever a different ratio is written to the PLLDIV1 register, the PLLCTRL flags the change in the DCHANGE status register. During the GO operation, the PLL controller will only change the di[...]

www.ti.com 7.8.3.6 SYSCLK Status Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The SYSCLK status register (SYSTAT) shows the status of the system clock (SYSCLK1). SYSTAT is shown in Figure 7-29 and described in Table 7-38 . 31 16 Reserved R-0 15 1 0 Reserved SYS1ON R-0 R-1 LEGEND: R[...]

www.ti.com 7.8.4 PLL2 Controller Input Clock Electrical Data/Timing CLKIN2 2 3 4 4 5 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-39. Timing Requirements for CLKIN2 (1) (2) (3) (see Figure 7-30 ) -720 -850 A-1000/-1000 NO. UNIT -1200 MIN MAX 1 t c(CLKIN2) Cycle time, CLKIN2 37.5 8[...]

www.ti.com 7.9 DDR2 Memory Controller 7.9.1 DDR2 Memory Controller Device-Specific Information SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The 32 bit, 533-MHz (data rate) DDR2 Memory Controller bus of the C6455 is used to interface to JESD79D-2A standard-compliant DDR2 SDRAM devices. The D[...]

www.ti.com 7.9.2 DDR2 Memory Controller Peripheral Register Description(s) 7.9.3 DDR2 Memory Controller Electrical Data/Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-40. DDR2 Memory Controller Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 7800 0000 MIDR DDR2 Memory Control[...]

www.ti.com 7.10 External Memory Interface A (EMIFA) 7.10.1 EMIFA Device-Specific Information SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The EMIFA can interface to a variety of external devices or ASICs, including: • Pipelined and flow-through Synchronous-Burst SRAM (SBSRAM) • ZBT (Zer[...]

www.ti.com 7.10.2 EMIFA Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-41. EMIFA Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 7000 0000 MIDR Module ID and Revision Register 7000 0004 STAT Status Register 7000 0008 - Reserved 7000 000C - 7000 001[...]

www.ti.com 7.10.3 EMIFA Electrical Data/Timing AECLKIN 2 3 4 4 5 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-42. Timing Requirements for AECLKIN for EMIFA (1) (2) (see Figure 7-31 ) -720 -850 A-1000/-1000 NO. UNIT -1200 MIN MAX 1 t c(EKI) Cycle time, AECLKIN 6 (3) 40 ns 2 t w(EKI[...]

www.ti.com 5 6 2 AECLKIN AECLKOUT1 4 4 1 3 7.10.3.1 Asynchronous Memory Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-43. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the EMIFA Module (1) (2) (3) (see Figure 7-32 ) -720 -850 A-1000/-1000 NO.[...]

www.ti.com AECLKOUT ACEx ABE[7:0] AEA[19:0]/ ABA[1:0] AED[63:0] AAOE/ASOE ( A) AR/W AA WE/ASWE ( A) AARDY (B ) Byte Enables Address Read Data Hold = 1 2 Strobe = 4 Setup = 1 2 2 4 10 10 1 1 1 3 A AAOE/ASOE and AAWE /ASWE operate as AAOE (identified under select signals) and AA WE , respectively , during asynchronous memory accesses. B Polarity of t[...]

www.ti.com AECLKOUT ACEx ABE[7:0] AEA[19:0]/ ABA[1:0] AED[63:0] AAOE/ASOE (A ) AR/W AA WE/ASWE ( A) AARDY (B ) Byte Enables Address W rite Data Hold = 1 12 Strobe = 4 Setup = 1 12 12 12 12 13 13 1 1 1 1 1 1 1 1 1 1 A AAOE/ASOE and AA WE /ASWE operate as AAOE (identified under select signals) and AA WE , respectively , during asynchronous memory acc[...]

www.ti.com 7.10.3.2 Programmable Synchronous Interface Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-46. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module (see Figure 7-36 ) -720 -850 A-1000/-1000 NO. UNIT -1200 MIN MAX 6 t su(EDV-EKOH) Setup t[...]

www.ti.com AECLKOUT ACEx ABE[7:0] AEA[19:0]/ABA[1:0] AED[63:0] ASADS/ASRE (B) AAOE/ASOE (B ) AA WE/ASWE ( B) BE1 BE2 BE3 BE4 Q1 Q2 Q3 9 1 4 5 8 9 6 7 3 1 2 BE1 BE2 BE3 BE4 EA1 EA2 EA4 8 READ latency = 2 EA3 A The following parameters are programmable via the EMIF A Chip Select n Configuration Register (CESECn): − Read latency (R_L TNCY): 1-, 2-, [...]

www.ti.com AECLKOUT ACEx ABE[7:0] AEA[19:0]/ABA[1:0] AED[63:0] ASADS/ASRE (B) AAOE/ASOE (B) AA WE /ASWE (B) BE1 BE2 BE3 BE4 Q1 Q2 Q3 1 1 3 12 10 4 2 1 8 5 8 EA1 EA2 EA3 EA4 10 W rite Latency = 1 (B) 1 Q4 12 A The following parameters are programmable via the EMIF A Chip Select n Configuration Register (CESECn): − Read latency (R_L TNCY): 1-, 2-, [...]

www.ti.com 7.10.4 HOLD/ HOLDA Timing HOLD HOLDA EMIF Bus (A) DSP Owns Bus External Requestor Owns Bus DSP Owns Bus DSP DSP 1 3 2 5 4 AECLKOUT SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-48. Timing Requirements for the HOLD/ HOLDA Cycles for EMIFA Module (1) (see Figure 7-39 ) -720 [...]

www.ti.com 7.10.5 BUSREQ Timing AECLKOUTx 1 ABUSREQ 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-50. Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles for EMIFA Module (see Figure 7-40 ) -720 -850 A-1000/-1000 NO. PARAMETER UNIT -1200 MIN MAX 1 [...]

www.ti.com 7.11 I2C Peripheral 7.11.1 I2C Device-Specific Information SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The inter-integrated circuit (I2C) module provides an interface between a C64x+ DSP and other devices compliant with Philips Semiconductors Inter-IC bus (I 2 C bus) specificati[...]

www.ti.com Clock Prescale I2CPSC Peripheral Clock (CPU/6) I2CCLKH Generator Bit Clock I2CCLKL Noise Filter SCL I2CXSR I2CDXR T ransmit T ransmit Shift T ransmit Buffer I2CDRR Shift I2CRSR Receive Buffer Receive Receive Filter SDA I2C Data Noise I2COAR I2CSAR Slave Address Control Address Own I2CMDR I2CCNT Mode Data Count V ector Interrupt Interrupt[...]

www.ti.com 7.11.2 I2C Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-51. I2C Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02B0 4000 ICOAR I2C own address register 02B0 4004 ICIMR I2C interrupt mask/status register 02B0 4008 ICSTR I2C interrupt s[...]

www.ti.com 7.11.3 I2C Electrical Data/Timing 7.11.3.1 Inter-Integrated Circuits (I2C) Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-52. Timing Requirements for I2C Timings (1) (see Figure 7-42 ) -720 -850 A-1000/-1000 NO. UNIT -1200 STANDARD MODE FAST MODE MIN MAX MIN MAX 1 t [...]

www.ti.com 10 8 4 3 7 12 5 6 14 2 3 13 Stop Start Repeated Start Stop SDA SCL 1 1 1 9 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Figure 7-42. I2C Receive Timings Table 7-53. Switching Characteristics for I2C Timings (1) (see Figure 7-43 ) -720 -850 A-1000/-1000 NO. PARAMETER UNIT -1200 ST[...]

www.ti.com 25 23 19 18 22 27 20 21 17 18 28 Stop Start Repeated Start Stop SDA SCL 16 26 24 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Figure 7-43. I2C Transmit Timings C64x+ Peripheral Information and Electrical Specifications 178 Submit Documentation Feedback[...]

www.ti.com 7.12 Host-Port Interface (HPI) Peripheral 7.12.1 HPI Device-Specific Information 7.12.2 HPI Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The C6455 device includes a user-configurable 16 bit or 32 bit Host-port interface (HPI16/HPI32). The AEA14 [...]

www.ti.com 7.12.3 HPI Electrical Data/Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-55. Timing Requirements for Host-Port Interface Cycles (1) (2) (see Table 7-56 through Figure 7-51 ) -720 -850 A-1000/-1000 NO. UNIT -1200 MIN MAX 9 t su(HASL-HSTBL) Setup time, HAS low before [...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-56. Switching Characteristics for Host-Port Interface Cycles (1) (2) (see Table 7-56 through Figure 7-51 ) -720 -850 A-1000/-1000 NO. PARAMETER UNIT -1200 MIN MAX Case 1. HPIC or HPIA read 5 15 Case 2. HPID read with no 9 * M +[...]

www.ti.com HCS HAS HCNTL[1:0] HR/W HHWIL HSTROBE (A ) HD[15:0] HRDY (B) 16 15 37 13 14 16 15 37 13 3 1 2 3 1 2 38 7 4 6 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT( HDS1 XOR HDS2)] OR HCS. B. Depending on the[...]

www.ti.com HCS HAS HR/W HHWIL HSTROBE (A ) HD[15:0] HRDY (B) 2 3 1 37 9 10 14 2 38 12 1 1 12 1 1 12 1 1 13 7 6 1 3 13 37 9 10 36 HCNTL[1:0] 12 1 1 12 1 1 12 1 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT( HD[...]

www.ti.com HCS HAS HCNTL[1:0] HR/W HHWIL HSTROBE (A ) HD[15:0] HRDY (B) 34 5 17 18 17 18 34 5 4 38 37 13 16 15 14 13 16 15 37 35 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT( HDS1 XOR HDS2)] OR HCS. B. Dependi[...]

www.ti.com HCS HAS HCNTL[1:0] HR/W HHWIL HSTROBE (A ) HD[15:0] HRDY (B) 5 34 17 18 13 10 12 9 37 12 12 1 1 1 1 1 1 17 18 14 1 1 1 1 1 1 37 10 9 13 12 12 12 5 34 38 35 36 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2:[...]

www.ti.com 15 16 3 2 4 1 38 13 7 6 HCS (input) HAS (input) HSTROBE (A ) (input) HR/W (input) HRDY (B) (output) HD[31:0] (output) HCNTL[1:0] (input) 37 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT( HDS1 XOR HDS[...]

www.ti.com 36 1 1 10 12 9 1 38 13 2 3 6 HCS (input) HAS (input) HSTROBE (A ) (input) HR/W (input) HRDY (B) (output) HD[31:0] (output) HCNTL[1:0] (input) 7 37 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT( HDS1 [...]

www.ti.com 17 15 38 5 16 13 18 34 35 4 HCS (input) HAS (input) HSTROBE (A ) (input) HR/W (input) HRDY (B) (output) HD[31:0] (input) HCNTL[1:0] (input) 37 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT( HDS1 XOR [...]

www.ti.com HRDY (B) (output) 5 1 1 9 17 18 34 HAS (input) HR/W (input) HSTROBE (A ) (input) HCS (input) 35 36 38 HD[31:0] (input) HCNTL[1:0] (input) 10 12 13 37 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT( HD[...]

www.ti.com 7.13 Multichannel Buffered Serial Port (McBSP) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The McBSP provides these functions: • Full-duplex communication • Double-buffered data registers, which allow a continuous data stream • Independent framing and clocking for receive [...]

www.ti.com 7.13.1 McBSP Device-Specific Information 7.13.1.1 McBSP Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The CLKS signal is shared by both McBSP0 and McBSP1 on this device. Also, the CLKGDV field of the Sample Rate Generator Register (SRGR) must alw[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-58. McBSP 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS The CPU and EDMA controller can only read 0290 0000 DRR1 McBSP1 Data Receive Register via Configuration Bus this register; they cannot write to it. 3400 000[...]

www.ti.com 7.13.2 McBSP Electrical Data/Timing 7.13.2.1 Multichannel Buffered Serial Port (McBSP) Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-59. Timing Requirements for McBSP (1) (see Figure 7-52 ) -720 -850 A-1000/-1000 NO. UNIT -1200 MIN MAX 2 t c(CKRX) Cycle time, CLKR/X[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-60. Switching Characteristics Over Recommended Operating Conditions for McBSP (see Figure 7-52 ) (continued) -720 -850 A-1000/-1000 NO. PARAMETER UNIT -1200 MIN MAX 3 t w(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X i[...]

www.ti.com Bit(n-1) (n-2) (n-3) Bit 0 Bit(n-1) (n-2) (n-3) 14 12 1 1 10 9 3 3 2 8 7 6 5 4 4 3 1 3 2 CLKS CLKR FSR (int) FSR (ext) DR CLKX FSX (int) FSX (ext) FSX (XDA TDL Y=00b) DX 13 (A) 13 (A) 2 1 CLKS FSR external CLKR/X (no need to resync) CLKR/X (needs resync) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – R[...]

www.ti.com Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 CLKX FSX DX DR SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-62. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (1) (2) (see Figure 7-54 ) -720 -850 A-1000/-100[...]

www.ti.com Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 4 3 7 6 2 1 CLKX FSX DX DR 5 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-64. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (1) (2) (see Figure 7-55 ) -720 -850 A-1000/-1000 [...]

www.ti.com Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 CLKX FSX DX DR SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-66. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (1) (2) (see Figure 7-56 ) -720 -850 A-1000/-100[...]

www.ti.com Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 5 4 3 7 6 2 1 CLKX FSX DX DR SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-68. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (1) (2) (see Figure 7-57 ) -720 -850 A-1000/-1000 [...]

www.ti.com 7.14 Ethernet MAC (EMAC) Configuration Bus DMA Memory T ransfer Controller Peripheral Bus EMAC Control Module EMAC Module MDIO Module MDIO Bus EMAC/MDIO Interrupt Interrupt Controller Ethernet Bus SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The Ethernet Media Access Controller ([...]

www.ti.com 7.14.1 EMAC Device-Specific Information SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Interface Modes The EMAC module on the C6455 supports four interface modes: Media Independent Interface (MII), Reduced Media Independent Interface (RMII), Gigabit Media Independent Interface (GMI[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-70. EMAC/MDIO Multiplexed Pins (MII, RMII, and GMII Modes) BALL NUMBER DEVICE PIN NAME MII RMII GMII (MAC_SEL = (MAC_SEL = (MAC_SEL = 00b) 01b) 10b) J2 URDATA0/MRXD0/RMRXD0 MRXD0 RMRXD0 MRXD0 H3 URDATA1/MRXD1/RMRXD1 MRXD1 RMRXD[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Interface Mode Clocking The on-chip PLL2 and PLL2 Controller generate the clocks to the EMAC module in RGMII or GMII mode. When the EMAC is enabled with these modes, the input clock to the PLL2 Controller (CLKIN2) must have a 25-MHz fr[...]

www.ti.com 7.14.2 EMAC Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-71. Ethernet MAC (EMAC) Control Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02C8 0000 TXIDVER Transmit Identification and Version Register 02C8 0004 TXCONTROL Transmit Contro[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-71. Ethernet MAC (EMAC) Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02C8 0158 RX6FREEBUFFER Receive Channel 6 Free Buffer Count Register 02C8 015C RX7FREEBUFFER Receive Channel 7 Free Buffer Count Regi[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-71. Ethernet MAC (EMAC) Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME Transmit Channel 3 Completion Pointer (Interrupt Acknowledge) 02C8 064C TX3CP Register Transmit Channel 4 Completion Pointer (Interru[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-72. EMAC Statistics Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME Receive Octet Frames Register 02C8 0230 RXOCTETS (Total number of received bytes in good frames) Good Transmit Frames Register 02C8 0234 TXGOODFR[...]

www.ti.com 7.14.3 EMAC Electrical Data/Timing 7.14.3.1 EMAC MII and GMII Electrical Data/Timing MRCLK (Input) 2 3 1 4 4 MTCLK (Input) 2 3 1 4 4 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-75. Timing Requirements for MRCLK - MII and GMII Operation (see Figure 7-59 ) -720 -850 A-1000[...]

www.ti.com GMTCLK (Output) 2 3 1 4 4 MRCLK (Input) 1 2 MRXD7−MRXD4(GMII only), MRXD3−MRXD0, MRXDV , MRXER (Inputs) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-77. Switching Characteristics Over Recommended Operating Conditions for GMTCLK - GMII Operation (see Figure 7-61 ) -720[...]

www.ti.com 1 MTCLK (Input) MTXD7−MTXD4(GMII only), MTXD3−MTXD0, MTXEN (Outputs) 1 GMTCLK (Output) MTXD7−MTXD0, MTXEN (Outputs) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-79. Switching Characteristics Over Recommended Operating Conditions for EMAC MII and GMII Transmit 10/100[...]

www.ti.com 7.14.3.2 EMAC RMII Electrical Data/Timing RMREFCLK (Input) 1 2 3 3 1 RMREFCLK (Input) MTXD1-MTXD0, MTXEN (Outputs) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The RMREFCLK pin is used to source a clock to the EMAC when it is configured for RMII operation. The RMREFCLK frequency [...]

www.ti.com RMREFCLK (Input) 1 2 3 3 4 5 MRXD1-MRXD0, MCRSDV , MRXER (Inputs) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-83. Timing Requirements for EMAC RMII Input Receive for 100 Mbps (1) (see Figure 7-67 ) -720 -850 A-1000/-1000 NO. UNIT -1200 MIN MAX Setup time, receive selecte[...]

www.ti.com 7.14.3.3 EMAC RGMII Electrical Data/Timing RGREFCLK (Output) 2 3 4 4 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 An extra clock signal, RGREFCLK, running at 125 MHz is included as a convenience to the user. Note that this reference clock is not a free-running clock. This shoul[...]

www.ti.com RXD[3:0] (A) RXCTL (A) RXC (at DSP) (B) 5 RXERR RXDV 6 1st Half-byte 2nd Half-byte RXD[7:4] RXD[3:0] 2 3 1 4 4 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-86. Timing Requirements for EMAC RGMII Input Receive for 10/100/1000 Mbps (1) (see Figure 7-69 ) -720 -850 A-1000/-1[...]

www.ti.com TXC (at DSP) (B) TXD[3:0] (A) TXCTL (A) 5 6 1st Half-byte TXERR TXEN 2nd Half-byte 1 2 Internal TXC TXC at DSP pins 4 4 2 3 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-88. Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmit (1) (see [...]

www.ti.com 7.14.4 Management Data Input/Output (MDIO) 7.14.4.1 MDIO Device-Specific Information 7.14.4.2 MDIO Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to in[...]

www.ti.com 7.14.4.3 MDIO Electrical Data/Timing 1 3 4 MDCLK MDIO (input) 1 7 MDCLK MDIO (output) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-90. Timing Requirements for MDIO Input (R)(G)MII (see Figure 7-71 ) -720 -850 A-1000/-1000 NO. UNIT -1200 MIN MAX 1 t c(MDCLK) Cycle time, MD[...]

www.ti.com 7.15 Timers 7.15.1 Timers Device-Specific Information 7.15.2 Timers Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The timers can be used to: time events, count events, generate pulses, interrupt the CPU, and send synchronization events to the EDM[...]

www.ti.com 7.15.3 Timers Electrical Data/Timing TINPLx T OUTLx 4 3 2 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-94. Timing Requirements for Timer Inputs (1) (see Figure 7-73 ) -720 -850 A-1000/-1000 NO. UNIT -1200 MIN MAX 1 t w(TINPH) Pulse duration, TINPLx high 12P ns 2 t w(TIN[...]

www.ti.com 7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2) 7.16.1 VCP2 Device-Specific Information 7.16.2 VCP2 Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The C6455 device has a high-performance embedded coprocessor [Viterbi-Decoder Coprocessor (VCP2) th[...]

www.ti.com 7.17 Enhanced Turbo Decoder Coprocessor (TCP2) 7.17.1 TCP2 Device-Specific Information SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-96. VCP2 Registers (continued) EDMA BUS CONFIGURATION BUS ACRONYM REGISTER NAME HEX ADDRESS RANGE HEX ADDRESS RANGE 5800 1000 - BM Branch Me[...]

www.ti.com 7.17.2 TCP2 Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-97. TCP2 Registers EDMA BUS CONFIGURATION BUS ACRONYM REGISTER NAME HEX ADDRESS RANGE HEX ADDRESS RANGE 5000 0000 - TCPIC0 TCP2 Input Configuration Register 0 5000 0004 - TCPIC1 TC[...]

www.ti.com 7.18 Peripheral Component Interconnect (PCI) 7.18.1 PCI Device-Specific Information SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The C6455 DSP supports connections to a PCI backplane via the integrated PCI master/slave bus interface. The PCI port interfaces to DSP internal resour[...]

www.ti.com 7.18.2 PCI Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-99. PCI Configuration Registers PCI HOST ACCESS ACRONYM PCI HOST ACCESS REGISTER NAME HEX ADDRESS OFFSET 0x00 PCIVENDEV Vendor ID/Device ID 0x04 PCICSR Command/Status 0x08 PCICLREV [...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-100. PCI Back End Configuration Registers DSP ACCESS ACRONYM DSP ACCESS REGISTER NAME HEX ADDRESS RANGE 02C0 0000 - 02C0 000F - Reserved 02C0 0010 PCISTATSET PCI Status Set Register 02C0 0014 PCISTATCLR PCI Status Clear Registe[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-100. PCI Back End Configuration Registers (continued) DSP ACCESS ACRONYM DSP ACCESS REGISTER NAME HEX ADDRESS RANGE 02C0 0308 PCIMCFGCMD PCI Master Configuration/IO Access Command Register 02C0 030C - 02C0 030F - Reserved 02C0 [...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-102. PCI Hook Configuration Registers DSP ACCESS ACRONYM DSP ACCESS REGISTER NAME HEX ADDRESS RANGE 02C0 0394 PCIVENDEVPRG PCI Vendor ID and Device ID Program Register 02C0 0398 PCICMDSTATPRG PCI Command and Status Program Regi[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-103. PCI External Memory Space (continued) HEX ADDRESS OFFSET ACRONYM REGISTER NAME 4800 0000 - 487F FFFF - PCI Master Window 16 4880 0000 - 48FF FFFF - PCI Master Window 17 4900 0000 - 497F FFFF - PCI Master Window 18 4980 000[...]

www.ti.com 7.18.3 PCI Electrical Data/Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Texas Instruments (TI) has performed the simulation and system characterization to ensure that the PCI peripheral meets all AC timing specifications as required by the PCI Local Bus Specification (vers[...]

www.ti.com 7.19 UTOPIA 7.19.1 UTOPIA Device-Specific Information 7.19.2 UTOPIA Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The Universal Test and Operations PHY Interface for ATM (UTOPIA) peripheral is a 50 MHz, 8 Bit Slave-only interface. The UTOPIA is m[...]

www.ti.com 7.19.3 UTOPIA Electrical Data/Timing UXCLK 1 2 3 4 4 URCLK 1 2 3 4 4 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-106. Timing Requirements for UXCLK (1) (see Figure 7-74 ) -720 -850 A-1000/-1000 NO. UNIT -1200 MIN MAX 1 t c(UXCK) Cycle time, UXCLK 20 ns 2 t w(UXCKH) Pulse[...]

www.ti.com P47 P48 H1 N 0x1F N 0x1F N + 1 0x1F N N 10 8 4 3 2 1 UXCLK UXDA T A[7:0] UXADDR[4:0] UXCLA V UXENB UXSOC 9 P46 P45 0 x1F A. The UT OPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the UXCLA V and UXSOC signals). 5 6 7 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTE[...]

www.ti.com P48 H1 H2 H3 N 0x1F N+1 0x1F N+2 0x1F N N+1 N+2 12 1 1 9 10 5 4 3 2 1 URCLK URDA T A[7:0] URADDR[4:0] URCLA V URENB URSOC A. The UT OPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the URCLA V and URSOC signals). 8 6 7 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPT[...]

www.ti.com 7.20 Serial RapidIO (SRIO) Port 7.20.1 Serial RapidIO Device-Specific Information 7.20.2 Serial RapidIO Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The SRIO port on the C6455 device is a high-performance, low pin-count interconnect aimed for em[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 0048 RIO_BLK2_EN Block Enable 2 02D0 004C RIO_BLK2_EN_STAT Block Enable Status 2 02D0 0050 RIO_BLK3_EN Block Enable 3 02D0 0054 RIO_BLK3_EN[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 0220 RIO_DOORBELL2_ICSR DOORBELL Interrupt Condition Status Register 2 02D0 0224 - Reserved 02D0 0228 RIO_DOORBELL2_ICCR DOORBELL Interrupt[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 02F0 RIO_ERR_RST_EVNT_ICRR Error, Reset, and Special Event Interrupt Condition Routing Register 02D0 02F4 RIO_ERR_RST_EVNT_ICRR2 Error, Res[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 0460 RIO_LSU4_REG0 LSU4 Control Register 0 02D0 0464 RIO_LSU4_REG1 LSU4 Control Register 1 02D0 0468 RIO_LSU4_REG2 LSU4 Control Register 2 [...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 0610 RIO_QUEUE4_RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 4 02D0 0614 RIO_QUEUE5_RXDMA_HDP Queue Receive DMA Head Descri[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 07F0 - 02D0 07FC - Reserved 02D0 0800 RIO_RXU_MAP_L0 Mailbox-to-Queue Mapping Register L0 02D0 0804 RIO_RXU_MAP_H0 Mailbox-to-Queue Mapping[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 08B8 RIO_RXU_MAP_L23 Mailbox-to-Queue Mapping Register L23 02D0 08BC RIO_RXU_MAP_H23 Mailbox-to-Queue Mapping Register H23 02D0 08C0 RIO_RX[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 1058 RIO_LCL_CFG_HBAR Local Configuration Space Base Address 0 CSR 02D0 105C RIO_LCL_CFG_BAR Local Configuration Space Base Address 1 CSR 0[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 201C RIO_CTRL_CAPT Logical/Transport Layer Control Capture CSR 02D0 2020 - 02D0 2024 - Reserved 02D0 2028 RIO_PW_TGT_ID Port-Write Target D[...]

www.ti.com 7.20.3 Serial RapidIO Electrical Data/Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 2130 - 02D1 0FFC - Reserved Implementation Registers 02D1 1000 - 02D1 1FFC - Reserved 02D1 200[...]

www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 TI only supports designs that follow the board design guidelines outlined in the SPRAAA8 application report. Submit Documentation Feedback C64x+ Peripheral Information and Electrical Specifications 245[...]

www.ti.com 7.21 General-Purpose Input/Output (GPIO) 7.21.1 GPIO Device-Specific Information 7.21.2 GPIO Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 On the C6455 the GPIO peripheral pins GP[15:8] and GP[3:0] are muxed with the UTOPIA, PCI, and McBSP1 perip[...]

www.ti.com 7.21.3 GPIO Electrical Data/Timing GPIx GPOx 4 3 2 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-114. Timing Requirements for GPIO Inputs (1) (2) (see Figure 7-78 ) -720 -850 A-1000/-1000 NO. UNIT -1200 MIN MAX 1 t w(GPIH) Pulse duration, GPIx high 12P ns 2 t w(GPIL) Pul[...]

www.ti.com 7.22 Emulation Features and Capability 7.22.1 Advanced Event Triggering (AET) 7.22.2 Trace SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The C6455 device supports Advanced Event Triggering (AET). This capability can be used to debug complex problems as well as understand performan[...]

www.ti.com 7.22.3 IEEE 1149.1 JTAG 7.22.3.1 JTAG Device-Specific Information 7.22.4 JTAG Peripheral Register Description(s) 7.22.5 JTAG Electrical Data/Timing TCK TDO TDI/TMS/TRST 1 2 3 4 2 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.22.3.1.1 IEEE 1149.1 JTAG Compatibility Statement For [...]

www.ti.com Revision History SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data sheet revision history highlights the technical changes made to the SPRS276G device-specific data sheet to make i[...]

www.ti.com 8 Mechanical Data 8.1 Thermal Data 8.2 Packaging Information SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 8-1 shows the thermal resistance characteristics for the PBGA - ZTZ/GTZ mechanical package. Table 8-1. Thermal Resistance Characteristics (S-PBGA Package) [ZTZ/GTZ] AIR[...]

PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) SM320C6455BGTZEP ACTIVE FCBGA GTZ 697 44 TBD SNPB Level-4-220C-72 HR SM320C6455BGTZSEP ACTIVE FCBGA GTZ 697 44 TBD SNPB Level-4-220C-72 HR V62/07649-01XA ACTIVE FCBGA GTZ 697 44 TBD SNPB Level-4-220C-72 HR [...]

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