Go to page of
Similar user manuals
-
Stereo System
Texas Instruments TMS320C642X
41 pages 0.23 mb -
Stereo System
Texas Instruments TMS320F2801
144 pages 1.4 mb -
Stereo System
Texas Instruments TMS320C6202
74 pages 1 mb -
Stereo System
Texas Instruments ADS8402
31 pages 0.29 mb -
Stereo System
Texas Instruments TMS320C6727
114 pages 1.08 mb -
Stereo System
Texas Instruments TMS320C2801
144 pages 1.4 mb -
Stereo System
Texas Instruments TMS320F28015
144 pages 1.4 mb -
Stereo System
Texas Instruments MSP50C614
414 pages 1.77 mb
A good user manual
The rules should oblige the seller to give the purchaser an operating instrucion of Texas Instruments TMS320C642X, along with an item. The lack of an instruction or false information given to customer shall constitute grounds to apply for a complaint because of nonconformity of goods with the contract. In accordance with the law, a customer can receive an instruction in non-paper form; lately graphic and electronic forms of the manuals, as well as instructional videos have been majorly used. A necessary precondition for this is the unmistakable, legible character of an instruction.
What is an instruction?
The term originates from the Latin word „instructio”, which means organizing. Therefore, in an instruction of Texas Instruments TMS320C642X one could find a process description. An instruction's purpose is to teach, to ease the start-up and an item's use or performance of certain activities. An instruction is a compilation of information about an item/a service, it is a clue.
Unfortunately, only a few customers devote their time to read an instruction of Texas Instruments TMS320C642X. A good user manual introduces us to a number of additional functionalities of the purchased item, and also helps us to avoid the formation of most of the defects.
What should a perfect user manual contain?
First and foremost, an user manual of Texas Instruments TMS320C642X should contain:
- informations concerning technical data of Texas Instruments TMS320C642X
- name of the manufacturer and a year of construction of the Texas Instruments TMS320C642X item
- rules of operation, control and maintenance of the Texas Instruments TMS320C642X item
- safety signs and mark certificates which confirm compatibility with appropriate standards
Why don't we read the manuals?
Usually it results from the lack of time and certainty about functionalities of purchased items. Unfortunately, networking and start-up of Texas Instruments TMS320C642X alone are not enough. An instruction contains a number of clues concerning respective functionalities, safety rules, maintenance methods (what means should be used), eventual defects of Texas Instruments TMS320C642X, and methods of problem resolution. Eventually, when one still can't find the answer to his problems, he will be directed to the Texas Instruments service. Lately animated manuals and instructional videos are quite popular among customers. These kinds of user manuals are effective; they assure that a customer will familiarize himself with the whole material, and won't skip complicated, technical information of Texas Instruments TMS320C642X.
Why one should read the manuals?
It is mostly in the manuals where we will find the details concerning construction and possibility of the Texas Instruments TMS320C642X item, and its use of respective accessory, as well as information concerning all the functions and facilities.
After a successful purchase of an item one should find a moment and get to know with every part of an instruction. Currently the manuals are carefully prearranged and translated, so they could be fully understood by its users. The manuals will serve as an informational aid.
Table of contents for the manual
-
Page 1
TMS320C642x DSP Inter-Integrated Circuit (I2C) Peripheral User's Guide Literature Number: SPRUEN0D March 2011[...]
-
Page 2
2 SPRUEN0D – March 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated[...]
-
Page 3
Preface ....................................................................................................................................... 6 1 Introduction ........................................................................................................................ 7 1.1 Purpose of the Peripheral ....................................[...]
-
Page 4
www.ti.com List of Figures 1 I2C Peripheral Block Diagram ............................................................................................. 8 2 Multiple I2C Modules Connected ......................................................................................... 9 3 Clocking Diagram for the I2C Peripheral .............................[...]
-
Page 5
www.ti.com List of Tables 1 Operating Modes of the I2C Peripheral ................................................................................ 15 2 Ways to Generate a NACK Bit ........................................................................................... 16 3 Descriptions of the I2C Interrupt Events ................................[...]
-
Page 6
Preface SPRUEN0D – March 2011 Read This First About This Manual This document describes the inter-integrated circuit (I2C) peripheral in the TMS320C642x Digital Signal Processor (DSP). The I2C peripheral provides an interface between the DSP and other devices that are compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification vers[...]
-
Page 7
User's Guide SPRUEN0D – March 2011 Inter-Integrated Circuit (I2C) Peripheral 1 Introduction This document describes the operation of the inter-integrated circuit (I2C) peripheral in the TMS320C642x Digital Signal Processor (DSP). The scope of this document assumes that you are familiar with the Philips Semiconductors Inter-IC bus (I2C-bus) s[...]
-
Page 8
ICXSR ICDXR ICRSR ICDRR Clock synchronizer Prescaler Noise filters Arbitrator I2C INT ICREVT Peripheral data bus Interrupt to CPU Sync events to EDMA controller SDA SCL Control/status registers CPU EDMA I2C peripheral ICXEVT Introduction www.ti.com 1.3 Functional Block Diagram A block diagram of the I2C peripheral is shown in Figure 1 . Refer to Se[...]
-
Page 9
TI device I2C I 2 C EPROM I 2 C I2C TI device V DD Pull-up resistors Serial data (SDA) Serial clock (SCL) controll er www.ti.com Peripheral Architecture 2 Peripheral Architecture The I2C peripheral consists of the following primary blocks: • A serial interface: one data pin (SDA) and one clock pin (SCL) • Data registers to temporarily hold rece[...]
-
Page 10
d 7 6 5 PLL1 I2C prescaler Prescaled module clock −−MUST be set to 6.7 to 13.3 MHz I2C input clock External input clock Register bits (ICPSC[IPSC]) I2C clock dividers Register bits (ICCLKL[ICCL]), (ICCLKH[ICCH]) Prescaled module clock frequency = I2C input clock frequency (IPSC + 1) I2C module I2C serial clock on SCL pin T o I2C bus I2C serial [...]
-
Page 11
W ait state Start HIGH period SCL from device #1 SCL from device #2 Bus line SCL www.ti.com Peripheral Architecture The prescaler (IPSC bit in ICPSC) must only be initialized while the I2C module is in the reset state (IRS = 0 in ICMDR). The prescaled frequency only takes effect when the IRS bit in ICMDR is changed to 1. Changing the IPSC bit in IC[...]
-
Page 12
Data line stable data Change of data allowed SDA SCL SDA SCL ST AR T condition (S) condition (P) STOP Peripheral Architecture www.ti.com 2.4.2 Data Validity The data on SDA must be stable during the high period of the clock (see Figure 5 ). The high or low state of the data line, SDA, can change only when the clock signal on SCL is low. Figure 5. B[...]
-
Page 13
SDA SCL MSB Acknowledgement bit from slave (No-)Acknowledgement bit from receiver 1 2 7 8 9 1 2 8 9 Slave address ACK ST AR T condition (S) STOP condition (P) R/W ACK Data S Slave address R/W ACK Data ACK Data ACK P 7 n n 1 1 1 1 1 1 www.ti.com Peripheral Architecture 2.6 Serial Data Formats Figure 7 shows an example of a data transfer on the I2C-b[...]
-
Page 14
S 1 1 1 1 1 0 A A 7 A A A A A A A A ACK 0 1 1 8 ACK 1 Data n ACK 1 P 1 A A = 2 MSBs R/W 8 LSBs of slave address Data Data S 1 Data ACK ACK ACK P 1 n n n 1 1 1 1 7 n 7 n 1 1 1 1 1 1 1 1 S Slave address R/W ACK Data ACK S Slave address R/W ACK Data ACK P 1 Any number 1 Any number Peripheral Architecture www.ti.com 2.6.2 10-Bit Addressing Format The 1[...]
-
Page 15
www.ti.com Peripheral Architecture 2.7 Endianness Considerations When the device is configured for big-endian mode, in order for the data to be placed in the right side of the register being accessed, access to the I2C registers must be performed as follows: • 8-bit accesses: An offset of 3h must be added to the address of the register being acce[...]
-
Page 16
Peripheral Architecture www.ti.com 2.9 NACK Bit Generation When the I2C peripheral is a receiver (master or slave), it can acknowledge or ignore bits sent by the transmitter. To ignore any new bits, the I2C peripheral must send a no-acknowledge (NACK) bit during the acknowledge cycle on the bus. Table 2 summarizes the various ways the I2C periphera[...]
-
Page 17
1 0 0 0 1 0 0 0 1 1 1 1 1 0 Device #1 lost arbitration and switches of f Bus line SCL Data from device #1 Data from device #2 Bus line SDA www.ti.com Peripheral Architecture 2.10 Arbitration If two or more master-transmitters simultaneously start a transmission on the same bus, an arbitration procedure is invoked. The arbitration procedure uses the[...]
-
Page 18
Peripheral Architecture www.ti.com 2.11 Reset Considerations The I2C peripheral has two reset sources: software reset and hardware reset. 2.11.1 Software Reset Considerations To reset the I2C peripheral, write 0 to the I2C reset (IRS) bit in the I2C mode register (ICMDR). All status bits in the I2C interrupt status register (ICSTR) are forced to th[...]
-
Page 19
www.ti.com Peripheral Architecture 2.12.1 Configuring the I2C in Master Receiver Mode and Servicing Receive Data via CPU The following initialization procedure is for the I2C controller configured in Master Receiver mode. The CPU is used to move data from the I2C receive register to CPU memory (memory accessible by the CPU). 1. Enable I2C clock fro[...]
-
Page 20
Peripheral Architecture www.ti.com 4. Enable the desired interrupt you need to receive by setting the desired interrupt bit field within ICIMR to enable the particular Interrupt. • AAS = 1; Expect an interrupt when Master's Address matches yours (ICOAR programmed value). • ICRRDY = 1; Expect a receive interrupt when a byte worth data sent [...]
-
Page 21
www.ti.com Peripheral Architecture 2.13 Interrupt Support The is capable of interrupting the DSP CPU. The CPU can determine which I2C events caused the interrupt by reading the I2C interrupt vector register (ICIVR). ICIVR contains a binary-coded interrupt vector type to indicate which interrupt has occurred. Reading ICIVR clears the interrupt flag;[...]
-
Page 22
Registers www.ti.com 2.16 Emulation Considerations The response of the I2C events to emulation suspend events (such as halts and breakpoints) is controlled by the FREE bit in the I2C mode register (ICMDR). The I2C peripheral either stops exchanging data (FREE = 0) or continues to run (FREE = 1) when an emulation suspend event occurs. How the I2C pe[...]
-
Page 23
www.ti.com Registers 3.1 I2C Own Address Register (ICOAR) The I2C own address register (ICOAR) is used to specify its own slave address, which distinguishes it from other slaves connected to the I2C-bus. If the 7-bit addressing mode is selected (XA = 0 in ICMDR), only bits 6-0 are used; bits 9-7 are ignored. The I2C own address register (ICOAR) is [...]
-
Page 24
Registers www.ti.com 3.2 I2C Interrupt Mask Register (ICIMR) The I2C interrupt mask register (ICIMR) is used to individually enable or disable I2C interrupt requests. The I2C interrupt mask register (ICIMR) is shown in Figure 14 and described Table 6 . Figure 14. I2C Interrupt Mask Register (ICIMR) 31 8 Reserved R-0 76543210 Reserved AAS SCD ICXRDY[...]
-
Page 25
www.ti.com Registers 3.3 I2C Interrupt Status Register (ICSTR) The I2C interrupt status register (ICSTR) is used to determine which interrupt has occurred and to read status information. The I2C interrupt status register (ICSTR) is shown in Figure 15 and described in Table 7 . Figure 15. I2C Interrupt Status Register (ICSTR) 31 16 Reserved R-0 15 1[...]
-
Page 26
Registers www.ti.com Table 7. I2C Interrupt Status Register (ICSTR) Field Descriptions (continued) Bit Field Value Description 10 XSMT Transmit shift register empty bit. XSMT indicates that the transmitter has experienced underflow. Underflow occurs when the transmit shift register (ICXSR) is empty but the data transmit register (ICDXR) has not bee[...]
-
Page 27
www.ti.com Registers Table 7. I2C Interrupt Status Register (ICSTR) Field Descriptions (continued) Bit Field Value Description 1 NACK No-acknowledgment interrupt flag bit. NACK applies when the I2C is a transmitter (master or slave). NACK indicates whether the I2C has detected an acknowledge bit (ACK) or a no-acknowledge bit (NACK) from the receive[...]
-
Page 28
Registers www.ti.com 3.4 I2C Clock Divider Registers (ICCLKL and ICCLKH) When the I2C is a master, the prescaled module clock is divided down for use as the I2C serial clock on the SCL pin. The shape of the I2C serial clock depends on two divide-down values, ICCL and ICCH. For detailed information on how these values are programmed, see Section 2.2[...]
-
Page 29
www.ti.com Registers 3.5 I2C Data Count Register (ICCNT) The I2C data count register (ICCNT) is used to indicate how many data words to transfer when the I2C is configured as a master-transmitter-receiver (MST = 1 and TRX = 1/0 in ICMDR) and the repeat mode is off (RM = 0 in ICMDR). In the repeat mode (RM = 1), ICCNT is not used. The value written [...]
-
Page 30
Registers www.ti.com 3.6 I2C Data Receive Register (ICDRR) The I2C data receive register (ICDRR) is used to read the receive data. The ICDRR can receive a data value of up to 8 bits; data values with fewer than 8 bits are right-aligned in the D bits and the remaining D bits are undefined. The number of data bits is selected by the bit count bits (B[...]
-
Page 31
www.ti.com Registers 3.8 I2C Data Transmit Register (ICDXR) The CPU or EDMA writes transmit data to the I2C data transmit register (ICDXR). The ICDXR can accept a data value of up to 8 bits. When writing a data value with fewer than 8 bits, the written data must be right-aligned in the D bits. The number of data bits is selected by the bit count bi[...]
-
Page 32
Registers www.ti.com 3.9 I2C Mode Register (ICMDR) The I2C mode register (ICMDR) contains the control bits of the I2C. The I2C mode register (ICMDR) is shown in shown in Figure 22 and described in Table 14 . Figure 22. I2C Mode Register (ICMDR) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 NACKMOD FREE STT Reserved STP MST TRX XA R/W-0 R/W-0 R/W-0 R-0 R[...]
-
Page 33
www.ti.com Registers Table 14. I2C Mode Register (ICMDR) Field Descriptions (continued) Bit Field Value Description 10 MST Master mode bit. MST determines whether the I2C is in the slave mode or the master mode. MST is automatically changed from 1 to 0 when the I2C master generates a STOP condition. See Table 16 . 0 Slave mode. The I2C is a slave a[...]
-
Page 34
Registers www.ti.com Table 14. I2C Mode Register (ICMDR) Field Descriptions (continued) Bit Field Value Description 2-0 BC 0-7h Bit count bits. BC defines the number of bits (1 to 8) in the next data word that is to be received or transmitted by the I2C. The number of bits selected with BC must match the data size of the other device. Note that whe[...]
-
Page 35
ICDRR ICRSR 0 1 ICSAR ICOAR 0 1 ICDXR ICXSR 0 1 0 0 DLB SCL_IN SCL_OUT Address/data T o internal I2C logic From internal I2C logic T o internal I2C logic T o ARM CPU or EDMA From ARM CPU or EDMA From ARM CPU or EDMA From ARM CPU or EDMA SCL SDA I2C peripheral DLB DLB www.ti.com Registers Table 16. How the MST and FDF Bits Affect the Role of TRX Bit[...]
-
Page 36
Registers www.ti.com 3.10 I2C Interrupt Vector Register (ICIVR) The I2C interrupt vector register (ICIVR) is used by the CPU to determine which event generated the I2C interrupt. Reading ICIVR clears the interrupt flag; if other interrupts are pending, a new interrupt is generated. If there are more than one interrupt flag, reading ICIVR clears the[...]
-
Page 37
www.ti.com Registers 3.11 I2C Extended Mode Register (ICEMDR) The I2C extended mode register (ICEMDR) is used to indicate which condition generates a transmit data ready interrupt. The I2C extended mode register (ICEMDR) is shown in Figure 25 and described in Table 18 . Figure 25. I2C Extended Mode Register (ICEMDR) 31 16 Reserved R-0 15 1 0 Reserv[...]
-
Page 38
Registers www.ti.com 3.12 I2C Prescaler Register (ICPSC) The I2C prescaler register (ICPSC) is used for dividing down the I2C input clock to obtain the desired prescaled module clock for the operation of the I2C. The IPSC bits must be initialized while the I2C is in reset (IRS = 0 in ICMDR). The prescaled frequency takes effect only when the IRS bi[...]
-
Page 39
www.ti.com Registers 3.13 I2C Peripheral Identification Register (ICPID1) The I2C peripheral identification registers (ICPID1) contain identification data (class, revision, and type) for the peripheral. The I2C peripheral identification register (ICPID1) is shown in Figure 27 and described in Table 20 . Figure 27. I2C Peripheral Identification Regi[...]
-
Page 40
www.ti.com Appendix A Revision History Table 22 lists the changes made since the previous version of this document. Table 22. Document Revision History Reference Additions/Modifications/Deletions Section 1.2 Changed second bullet point. Section 3.5 Changed first sentence in first paragraph. Table 14 Changed Description of RM bit. Table 17 Changed D[...]
-
Page 41
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders[...]