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Texas Instruments TMS320C645x manual

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Table of contents for the manual

  • Page 1

    TMS320C645x DSP General-Purpose Input/Output (GPIO) User ’ s Guide Literature Number: SPRU724 December 2005[...]

  • Page 2

    IMPORT ANT NOTICE T exas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orde[...]

  • Page 3

    3 General-Purpose Input/Output (GPIO) SPRU724 Preface Read This First About This Manual This document describes the general-purpose input/output (GPIO) peripheral in the digital signal processors (DSPs) of the TMS320C645x ™ DSP family . Notational Conventions This document uses the following conventions. - Hexadecimal numbers are shown with the s[...]

  • Page 4

    T rademarks 4 General-Purpose Input/Output (GPIO) SPRU724 TMS320C6000 Programmer ’s Guide (literature number SPRU198) describes ways to optimize C and assembly code for the TMS320C6000 t DSPs and includes application program examples. TMS320C6000 Code Composer Studio Tutorial (literature number SPRU301) introduces the Code Composer Studio t integ[...]

  • Page 5

    Contents 5 General-Purpose Input/Output (GPIO) SPRU724 Contents 1 Overview 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 GPIO Function 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

  • Page 6

    Figures 6 General-Purpose Input/Output (GPIO) SPRU724 Figures 1 TMS320C645x DSP Block Diagram 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 GPIO Peripheral Block Diagram 1 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Interrupt Per-Bank Enab[...]

  • Page 7

    T ables 7 General-Purpose Input/Output (GPIO) SPRU724 T ables 1 GPIO Interrupt and EDMA Event Configuration Options 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 GPIO Registers 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Interrupt Per-Bank Enab[...]

  • Page 8

    8 General-Purpose Input/Output (GPIO) SPRU724 This page is intentionally left blank.[...]

  • Page 9

    9 General-Purpose Input/Output (GPIO) SPRU724 General-PurposeInput/Output(GPIO) This document describes the general-purpose input/output (GPIO) peripheral in the digital signal processors (DSPs) of the TMS320C645x ™ DSP family . 1 Overview The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be[...]

  • Page 10

    Overview General-Purpose Input/Output (GPIO) 10 SPRU724 Figure 1. TMS320C645x DSP Block Diagram L1 S1 M1 D1 Data path A Register file A Register file B D2 Data path B S2 M2 L2 L1 data memory controller Cache control Memory protection Interrupt and exception controller Power control Instruction decode 16/32−bit instruction dispatch Instruction fet[...]

  • Page 11

    Overview 11 General-Purpose Input/Output (GPIO) SPRU724 Figure 2. GPIO Peripheral Block Diagram DIR SET_DA T A OUT_DA T A CLR_DA T A Synchronization logic Peripheral clock (CPU/6) Direction Set data Output data Clear data IN_DA T A Input data Edge detection logic Interrupt and EDMA event (GPINTn ‡ ) SET_RIS_TRIG RIS_TRIG § CLR_RIS_TRIG CLR_F AL_[...]

  • Page 12

    GPIO Function General-Purpose Input/Output (GPIO) 12 SPRU724 2 GPIO Function Y ou can independently configure each GPIO pin (GPn) as either an input or an output using the GPIO direction registers. The GPIO direction register (DIR) specifies the direction of each GPIO signal. Logic 0 indicates the GPIO pin is configured as output, and logic 1 indic[...]

  • Page 13

    Interrupt and Event Generation 13 General-Purpose Input/Output (GPIO) SPRU724 3 Interrupt and Event Generation Each GPIO pin (GPn) can be configured to generat e a CPU interrupt (GPINTn) and a synchronization event to the EDMA controller (GPINTn). The interrupt an d EDMA event can be generated on the rising-edge, falling-edge, or on both edges of t[...]

  • Page 14

    Emulation Halt Operation General-Purpose Input/Output (GPIO) 14 SPRU724 Reading the SET_RIS_TRIG or CLR_RIS_TRIG register returns the value of RIS_TRIG register . Reading from SET_F AL_TRIG and CLR_F AL_TRIG register returns the value of F AL_TRIG register . T o use the GPIO pins as sources for CPU interrupts and EDMA events, bit 0 in the bank inte[...]

  • Page 15

    Registers 15 General-Purpose Input/Output (GPIO) SPRU724 5 Registers The GPIO peripheral is configured through the registers listed in T able 2. S ee the device-specific datasheet for the memory address of these registers. T able 2. GPIO Registers Offsets Acronym Register Name Section 0008 BINTEN Interrupt Per-Bank Enable Register 5.1 0010 DIR Dire[...]

  • Page 16

    Registers General-Purpose Input/Output (GPIO) 16 SPRU724 5.1 Interrupt Per-Bank Enable Register (BINTEN) T o use the GPIO pins as sources for CPU interrupts and EDMA events, bit 0 in the bank interrupt enable register (BINTEN) must be set. BINTEN is shown in Figure 3 and described in T able 3. Figure 3. Interrupt Per-Bank Enable Register (BINTEN) 3[...]

  • Page 17

    Registers 17 General-Purpose Input/Output (GPIO) SPRU724 5.2 Direction Register (DIR) The GPIO direction register (DIR) determines if a given GPIO pin is an input or an output. The GPDIR is shown in Figure 4 and described in T able 4. By default, all the GPIO pins are configured as input pins. When GPIO pins are configured as output pins, the GPIO [...]

  • Page 18

    Registers General-Purpose Input/Output (GPIO) 18 SPRU724 5.3 Output Data Register (OUT_DA T A) The GPIO output data register (OUT_DA T A) indicates the value to be driven on a given GPIO output pin. The OUT_DA T A registers are shown in Figure 5 and described in T able 5. Figure 5. Output Data Register (OUT_DA T A) 31 16 Reserved R-0 15 14 13 12 1 [...]

  • Page 19

    Registers 19 General-Purpose Input/Output (GPIO) SPRU724 5.4 Set Data Register (SET_DA T A) The GPIO set data register (SET_DA T A) is shown in Figure 6 and described in T able 6. SET_DA T A provides an alternate means of driving GPIO outputs high. Writing a 1 to a bit of SET_DA T A sets the corresponding bit in OUT_DA T A. Writing a 0 has no effec[...]

  • Page 20

    Registers General-Purpose Input/Output (GPIO) 20 SPRU724 5.5 Clear Data Register (CLR_DA T A) Th e GPIO clear data register (CLR_DA T A) i s shown in Figure 7 and described in T able 7. CLR_DA T A provides an alternate means of driving GPIO outputs low . Writing a 1 to a bit of CLR_DA T A clears the corresponding bit in OUT_DA T A. Writing a 0 has [...]

  • Page 21

    Registers 21 General-Purpose Input/Output (GPIO) SPRU724 5.6 Input Data Register (IN_DA T A) The GPIO input data register (IN_DA T A) reflects the state of the GPIO pins. The IN_DA T A register is shown in Figure 8 and described in T able 8. When read, IN_DA T A returns the state of the GPIO pins regardless of the state of the corresponding bits in[...]

  • Page 22

    Registers General-Purpose Input/Output (GPIO) 22 SPRU724 5.7 Set Rising Edge Interrupt Register (SET_RIS_TRIG) The GPIO rising trigger register (RIS_TRIG) configures the edge detection logic to trigger GPIO interrupts and EDMA events on the rising edge of GPIO signals. Setting a bit to 1 in RIS_TRIG causes the corresponding GPIO interrupt and EDMA [...]

  • Page 23

    Registers 23 General-Purpose Input/Output (GPIO) SPRU724 5.8 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG) The GPIO rising trigger register (RIS_TRIG) configures the edge detection logic to trigger GPIO interrupts and EDMA events on the rising edge of GPIO signals. Setting a bit to 1 in RIS_TRIG causes the corresponding GPIO interrupt and EDM[...]

  • Page 24

    Registers General-Purpose Input/Output (GPIO) 24 SPRU724 5.9 Set Falling Edge Interrupt Register (SET_F AL_TRIG) The GPIO falling trigger register (F AL_TRIG) configures the edge detection logic to trigger GPIO interrupts and EDMA events on the falling edge of GPIO signals. Setting a bit to 1 in F AL_TRIG causes the corresponding GPIO interrupt and[...]

  • Page 25

    Registers 25 General-Purpose Input/Output (GPIO) SPRU724 5.10 Clear Falling Edge Interrupt Register (CLR_F AL_TRIG) The GPIO falling trigger register (F AL_TRIG) configures the edge detection logic to trigger GPIO interrupts and EDMA events on the falling edge of GPIO signals. Setting a bit to 1 in F AL_TRIG causes the corresponding GPIO interrupt [...]

  • Page 26

    General-Purpose Input/Output (GPIO) 26 SPRU724 This page is intentionally left blank.[...]

  • Page 27

    Index 27 General-Purpose Input/Output (GPIO) SPRU724 Index B block diagram C645x DSP 10 GPIO 1 1 E event generation 13 events 14 F function 12 I interrupt generation 13 interrupts 14 N notational conventions 3 O overview 9 R registers 15 related documentation from T exas Instruments 3 T trademarks 4[...]