Texas Instruments TMS320C645X manual

TMS320C645x Serial Rapid IO (SRIO) User's Guide Literature Number: SPRU976 March 2006[...]

2 SPRU976 – March 2006 Submit Documentation Feedback[...]

Contents Preface .............................................................................................................................. 13 1 Overview .................................................................................................................. 14 1.1 General RapidIO System ...............................................[...]

5.25 Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) .................. 126 5.26 DOORBELL n Interrupt Condition Routing Register (DOORBELL n _ICRR) .............................. 127 5.27 DOORBELL n Interrupt Condition Routing Register 2 (DOORBELL n _ICRR2) .......................... 128 5.28 RX CPPI Interrupt Condition[...]

5.72 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) ................................... 174 5.73 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) ..................................... 175 5.74 Base Device ID CSR (BASE_ID) .............................................................................. 176 5.75 Host Base Device [...]

List of Figures 1 RapidIO Architectural Hierarchy .......................................................................................... 15 2 RapidIO Interconnect Architecture ....................................................................................... 16 3 Serial RapidIO Device to Device Interface Diagrams ..........................[...]

52 Load/Store Module Interrupt Condition Routing Registers ............................................................ 82 53 Error, Reset, and Special Event Interrupt Condition Routing Registers ............................................ 83 54 Sharing of ISDR Bits ..................................................................................[...]

105 Queue Transmit DMA Head Descriptor Pointer Registers (QUEUE n _TXDMA_HDP) .......................... 150 106 Queue Transmit DMA Completion Pointer Registers (QUEUE n _TXDMA_CP) .................................. 151 107 Queue Receive DMA Head Descriptor Pointer Registers (QUEUE n _RXDMA_HDP) ........................... 152 108 Queue Receive DMA[...]

158 Port Error Rate Threshold CSR n (SP n _ERR_THRESH) ........................................................... 206 159 Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) .............................................. 207 160 Port IP Mode CSR (SP_IP_MODE) ...................................................................................[...]

List of Tables 1 RapidIO Documents and Links ........................................................................................... 18 2 Packet Type ................................................................................................................. 23 3 Pin Description .............................................................[...]

50 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) Field Descriptions ......................................... 121 51 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) Field Descriptions .......................................... 122 52 LSU Status Interrupt Register (LSU_ICSR) Field Descriptions .....................................................[...]

99 Source Operations CAR (SRC_OP) Field Descriptions ............................................................. 171 100 Destination Operations CAR (DEST_OP) Field Descriptions ....................................................... 172 101 Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions .............................. [...]

Preface SPRU976 – March 2006 Read This First About This Manual This document describes the Serial Rapid IO (SRIO) on the TMS320C645x devices. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers[...]

1 Overview 1.1 General RapidIO System User's Guide SPRU976 – March 2006 Serial RapidIO (SRIO) The RapidIO peripheral used in the TMS320C645x is called a serial RapidIO (SRIO). This chapter describes the general operation of a RapidIO system, how this module is connected to the outside world, the definitions of terms used within this document[...]

www.ti.com Globally shared memory spec logical Future Message passing system I/O Logical specification Information necessary for the end point to process the transaction (i.e., transaction type, size, physical address) to end in the system (i.e., routing address) Information to transport packet from end T ransport specification spec transport Commo[...]

www.ti.com Host Subsystem I/O Control Subsystem DSP Farm TDM,GMII, Utopia Communications Subsystem PCI Subsystem InfiniBand HCA ™ T o System Area Network Memory Memory Memory Memory RapidIO RapidIO RapidIO RapidIO RapidIO Backplane PCI RapidIO RapidIO RapidIO RapidIO Switch Control Processor IO Processor RapidIO to InfiniBand RapidIO Switch Rapid[...]

www.ti.com Serial RapidIO 1x Device to 1x Device Interface Diagram Serial RapidIO 4x Device to 4x Device Interface Diagram 1x Device TD[0] TD[0] RD[0] RD[0] TD[0] TD[0] 1x Device RD[0] RD[0] RD[0-3] RD[0-3] 4x Device TD[0-3] RD[0-3] RD[0-3] TD[0-3] 4x Device TD[0-3] TD[0-3] 1.2 RapidIO Feature Support in SRIO Overview Figure 3. Serial RapidIO Devic[...]

www.ti.com 1.3 Standards 1.4 External Devices Requirements Overview Features Not Supported: • Compliance with the Global Shared Memory specification (GSM) • 8/16 LP-LVDS compatible • Destination support of RapidIO Atomic Operations • Simultaneous mixing of frequencies between 1X ports (all ports must be the same frequency) • Target atomic[...]

www.ti.com 2 SRIO Functional Description 2.1 Overview SRIO Functional Description 2.1.1 Peripheral Data Flow This peripheral is designed to be an external slave module that is capable of mastering the internal DMA. This means that an external device can push (burst write) data to the DSP as needed, without having to generate an interrupt to the CPU[...]

www.ti.com 1.25-3.125 Gbps differential data Rx Clock recovery S2P 10b Clk 8b/10b decode 8b Clock recovery Rx 8b 8b/10b decode 10b Clk S2P Clock recovery Rx 8b 8b/10b decode 10b Clk S2P Clock recovery Rx 8b 8b/10b decode 10b Clk S2P PLL Tx Tx Tx Tx P2S P2S P2S P2S 8b 8b 8b 8b 10b 8b/10b coding Clk 8b/10b coding 8b/10b coding 8b/10b coding 10b Clk 1[...]

www.ti.com Initiator Request Packet Issued Operation Completed for Master Acknowledge Symbol Acknowledge Symbol Response Packet Forwarded Request Packet Forwarded Acknowledge Symbol Acknowledge Symbol Response Packet Issued Fabric T arget T arget Completes Operation Operation Issued By Master SRIO Functional Description SRIO endpoints are typically[...]

www.ti.com double-word n-1 acklD rsv prio tt ftype destID sourcelD address rsrv xamsbs double-word 0 double-word 1 ... double-word n-2 CRC PHY LOG TRA LOG TRA PHY 5 3 2 2 4 8 8 29 1 2 64 64 (n-4)*64 64 64 16 16 n*64+32 16 4 2 10 LOG PHY 10 TRA 2 4 9 * 6 4 + 32 LOG TRA 16 PHY 16 double-word 0 5 acklD sourcelD rsv 3 prio 2 ftype tt 2 4 destiD 8 1 rsr[...]

www.ti.com SRIO Functional Description The type of received packet determines how the packet routing is handled. Reserved or undefined packet types are destroyed before being processed by the logical layer functional blocks. This prevents erroneous allocation of resources to them. Unsupported packet types are responded to with an error response pac[...]

www.ti.com 2.2 SRIO Pins 2.3 Functional Operation SRIO Functional Description The SRIO device pins are high-speed differential signals based on Current-Mode Logic (CML) switching levels. The transmit and receive buffers are self-contained within the clock recovery blocks. The reference clock input is not incorporated into the SERDES macro. It uses [...]

www.ti.com Port 0 8 x 276 TX 8 x 276 RX 8 x 276 RX 8 x 276 TX Port 1 8 x 276 TX 8 x 276 RX Port 2 8 x 276 RX 8 x 276 TX Port 3 Physical layer buffers SERDES 0 SERDES 1 SERDES 2 SERDES 3 SERDES differential signals 4x mode data path TX buffering 32 x 276B 8 buffers per 1X port - all priorities 32 buffers per 4X port - 8 per priority T ransaction map[...]

www.ti.com SRIO Functional Description 2.3.2 SERDES and its Configurations SRIO offers many benefits to customers by allowing a scalable non-proprietary interface. With the use of TI’s SERDES macros, the peripheral is very adaptable and bandwidth scalable. The same peripheral can be used for all three frequency nodes specified in V1.2 of the Rapi[...]

www.ti.com SRIO Functional Description Table 4. Bits of SERDES_CFG n _CNTL Register (0x120 - 0x12c) (continued) Bit Name Value Description 5:1 MPY PLL multiply. Select PLL multiply factors between 4 and 60. Multiply modes shown below. 0000 4x 0001 5x 0010 6x 0011 Reserved 0100 8x 0101 10x 0110 12x 0111 12.5x 1000 15x 1001 20x 1010 25x 1011 Reserved[...]

www.ti.com SRIO Functional Description Here is the frequency range versus MPY: Table 7. Frequency Range versus MPY MPY RIOCLK and RIOCLK Line Rate Range (Gbps) Range (MHz) Full Half Quarter 4x 250 - 425 2 - 3.4 1 - 1.7 0.5 - 0.85 5x 200 - 425 2 - 4.25 1 - 2.125 0.5 - 1.0625 6x 167 - 354.167 2 - 4.25 1 - 2.125 0.5 - 1.0625 8x 125 - 265.625 2 - 4.25 [...]

www.ti.com SRIO Functional Description Table 8. Bits of SERDES_CFGRX n _CNTL Registers (continued) Bit Field Value Description 15:14 LOS Loss of signal. Enables loss of signal detection with 2 selectable thresholds. 00 Disabled. Loss of signal detection disabled. 01 High threshold. Loss of signal detection threshold in the range 85 to 195mV dfpp . [...]

www.ti.com SRIO Functional Description Table 9. EQ Bits CFGRX[22:19] Low Freq Gain Zero Freq (at e 28 (min)) 0000 Maximum - 0001 Adaptive Adaptive 001x Reserved 01xx Reserved 1000 Adaptive 1084MHz 1001 805MHz 1010 573MHz 1011 402MHz 1100 304MHz 1101 216MHz 1110 156MHz 1111 135MHz 2.3.2.3 Enabling the Transmitter To enable a transmitter for serializ[...]

www.ti.com SRIO Functional Description Table 10. Bits of SERDES_CFGTX n _CNTL Registers (continued) Bit Field Value Description 4:2 BUS- Bus width. Selects the width of the parallel interface (10 or 8 bit). WIDTH 000 10-bit operation. Data is input on TD n [9:0]. TXBCLK n period is 10 bit periods (4 high, 6 low). 001 8-bit operation. Data is input [...]

www.ti.com Configuration/Status Register and T ables (32-bit) Output Buffers (64-bit) RapidIO Endpoint IT Generator ASIC Device RapidIO Endpoint L2 CPU Step 2. IT to CPU for end transfer completion Step 1. ASIC writes through RapidIO to L2 SRIO Functional Description 2.3.2.4 SERDES Configuration Example rdata = SRIO_REGS->SERDES_CFG0_CNTL; wdata[...]

www.ti.com LSU_Reg0 RapidIO Address MSB Control 31 RapidIO Address LSB/Config_offset Control 31 0 LSU_Reg1 DSP Address Control 31 0 LSU_Reg2 RSV Control 31 0 LSU_Reg3 12 1 1 Byte_count OutPortID Control 31 0 LSU_Reg4 1 7 Interrupt Req 30 Priority 29 28 xambs 27 26 ID Size 25 24 DestID 23 8 RSV Drbll Info Command 31 0 LSU_Reg5 8 7 Packet T ype 16 Ho[...]

www.ti.com SRIO Functional Description Table 13. Control/Command Register Field Mapping (continued) Control/Command Register RapidIO Packet Header Field Field Packet Type 4 msb = 4b ftype field for all packets and 4 lsb = 4b trans field for packet types 2,5,8. OutPortID Not available in RapidIO header. Indicates the output port number for the packe[...]

www.ti.com LSU_Reg1 T0 T1 T2 T3 T4 T5 Tn V alid LSU_Reg2 V alid LSU_Reg3 V alid LSU_Reg4 V alid LSU_Reg5 V alid Rdy/BSY Completion V alid V alid After T ransaction Completes SRIO Functional Description Figure 11. LSU Registers Timing The following code illustrates an LSU registers programming example. SRIO_REGS->;LSU1_Reg0 = CSL_FMK( SRIO_LSU1_R[...]

www.ti.com Source Address DMA Read Destination Address Count Byte Count DSP Address RSV Interrupt Req 0 0 1 7 23 8 DestID 25 24 ID Size 27 26 xambs 29 28 Priority OutPortID 31 30 Hop Count Drbll 31 16 15 Packet 8 7 0 RapioIO Address/Config_offset NodeID CRC 16 Count*8 payload 2 xamsbs 1 wr ptr 29 address 32 ext addr 8 srcTID 4 wrsize 4 trans 8 sour[...]

www.ti.com LSU2 LSU4 LSU3 LSU1 MMR command UDI interface Load/store module RapidIO transport and physical layers Port x transmission FIFO queues TX FIFO RX FIFO Peripheral boundary Config bus access Write transfer descriptors CPU I/O pins L2 memory = Shared resource for CPPI and MAU Shared TX data Shared RX data Response timer Control and arbitrato[...]

www.ti.com SRIO Functional Description For posted WRITE operations, which do not require a RapidIO response packet, a core may submit multiple outstanding requests. For instance, a single core may have many streaming write packets buffered at any given time, given outgoing resources. In this application, the control/command registers can be release[...]

www.ti.com SRIO Functional Description Segmentation: The LSU handles two types of segmentation of outbound requests. The first type is when the Byte_Count of Read/Write requests exceeds 256 bytes (up to 4KB). The second type is when Read/Write request RapidIO address is non-64b aligned. In both cases, the outgoing request must be broken up into mul[...]

www.ti.com SRIO Functional Description So the general flow is as follows: • Previously, the control/command registers were written and the request packet was sent • Response Packet Type13, Trans != 0001b arrives at module interface, and is handled sequentially (not based on priority) • targetTID is examined to determine routing of a response [...]

www.ti.com Mailbox 1...64 from RapidIO Packet Header - Received on any input port Mailbox Mapper Q15 Q2 Q1 Q0 Queue assignable to any core Packet Sequence Message n A Packet Manager n+1 B n+2 B n + 3 C n+4 D n+5 B n+6 E Buffer Descriptor Queues: Descriptor per Message All Priorities Dedicated Single Segment Message Descriptor Queue A C E D null nul[...]

www.ti.com msglen msgseg/ xmbox mbox letter 4 4 2 2 Single Segment Mailbox 0 ... 63 Multi-Segment Mailbox 0 ... 4 SOURCEID = SourceID allowed access if secure queue Mailbox = Allowed mailbox for this mapping register (Mask-able) 0b000000 - Mailbox 0 0b000001 - Mailbox 1 0b000010 - Mailbox 2 ... 0b1 1 1 1 1 1 - Mailbox 63 Letter = Allowed letter for[...]

www.ti.com SRIO Functional Description Figure 17. Queue Mapping Register RXU_MAP_L n 31 30 29 24 23 22 21 16 Letter Mask Mailbox Mask Letter Mailbox R/W-11 R/W-111111 R/W-0 R/W-000000 15 0 SOURCEID R/W-0x0000 LEGEND: R = Read, W = Write, n = value at reset Figure 18. Queue Mapping Register RXU_MAP_H n 31 16 Reserved R-0 15 10 9 8 7 6 5 2 1 0 Reserv[...]

www.ti.com 31 0 1 2 15 23 7 27 1 1 19 3 29 O W N E R S H I P T E A R D O W N E O P E O Q S O P 3 RESERVED cc Message Length 13 21 5 25 9 17 1 30 14 22 6 26 10 18 2 28 12 20 4 24 8 16 0 Bit Fields Next Descriptor Pointer Buffer Pointer SRC_ID PRI tt RESERVED Mailbox Word Offset SRIO Functional Description If a multi-segment buffer descriptor queue i[...]

www.ti.com SRIO Functional Description Table 17. RX Buffer Descriptor Field Descriptions Field Description next_descriptor_pointer Next Descriptor Pointer: The 32-bit word aligned memory address of the next buffer descriptor in the RX queue. This references the next buffer descriptor from the current buffer descriptor. If the value of this pointer [...]

www.ti.com SRIO Functional Description Table 17. RX Buffer Descriptor Field Descriptions (continued) Field Description mailbox Destination Mailbox: Specifies the mailbox to which the message was sent. 000000b: Mailbox 0 000001b: Mailbox 1 ... 000100b: Mailbox 4 ... 111111b: Mailbox 63 For multi-segment messages, only the two LSBs of this mailbox ar[...]

www.ti.com Switch Switch Endpoint Endpoint C0 C0 B0 B0 B2 B2 A1 A1 B1 B1 A0 A0 Open Open Open Open Open Open Open Full Open Open Full Full Retry Retry Retry Retry Retry Retry Accept Retry Retry Retry Action Action Retry Retry Scenario A - Default Scenario B - In order mode Data flow destined for the same Rx Queue Rx Queue Status when packet arrives[...]

www.ti.com CPPI block CPU DMA Config bus access L2 memory Bu ffe r de sc ri pto r du al -p ort SR AM (N x2 0B ) Da ta b uff er Peripheral boundary 32 32 32 128 C P P I c o nt r o l r e g i s t e r s SRIO Functional Description Teardown of an Rx queue causes the following actions: • If teardown is issued by software during the time when the RX sta[...]

www.ti.com 31 0 1 2 15 23 7 27 1 1 19 3 29 O W N E R S H I P T E A R D O W N E O P E O Q S O P 3 Reserved Retry_count cc Message Length 13 21 5 25 9 17 1 30 14 22 6 26 10 18 2 28 12 20 4 24 8 16 0 Bit Fields Next Descriptor Pointer Buffer Pointer Dest_ID PRI tt SSIZE Mailbox Port_ID Word Offset SRIO Functional Description 2.3.4.2 TX Operation Outgo[...]

www.ti.com SRIO Functional Description Table 20. TX Buffer Descriptor Field Definitions (continued) Field Description ownership Ownership: Indicates ownership of the message and is valid only on sop. This bit is set by the host and cleared by the port when the message has been transmitted. The host uses this bit to reclaim buffers. 0: The message i[...]

www.ti.com SRIO Functional Description Table 20. TX Buffer Descriptor Field Definitions (continued) Field Description tt RapidIO tt field specifying 8- or 16-bit DeviceIDs 00: 8b deviceIDs 01: 16b deviceIDs 10: reserved 11: reserved PortID Port number for routing outgoing packet. SSIZE RIO standard message payload size. Indicates how the hardware s[...]

www.ti.com SRIO Functional Description Figure 23. Weighted Round Robin Programming Registers (Address Offset 0x7E0 – 0x7EC) TX_QUEUE_CNTL0- Address Offset (0x7E0) 31 24 23 16 TX_Queue_Map3 TX_Queue_Map2 15 8 7 0 TX_Queue_Map1 TX_Queue_Map0 TX_QUEUE_CNTL1- Address Offset (0x7E4) 31 24 23 16 TX_Queue_Map7 TX_Queue_Map6 15 8 7 0 TX_Queue_Map5 TX_Que[...]

www.ti.com SRIO Functional Description Table 21. Weighted Round Robin Programming Registers (Address Offset 0x7E0 – 0x7EC) (continued) Name Bit Access Reset Value Description TX_Queue_Map10 [23:16] R/W 0x0A [23:20] = Number of contiguous messages (descriptors) to process before moving to TX_Queue_Map11 [19:16] = Pointer to a Queue, programmable t[...]

www.ti.com SRIO Functional Description Essentially, instead of the 24-bit value representing the period of the response timer, the period is now defined as P = (2^24 x 16)/F. This means the countdown timer frequency needs to be 44.7 – 89.5Mhz for a 6 – 3 second response timeout. Since the needed timer frequency is derived from the DMA bus clock[...]

www.ti.com SRIO Functional Description The CPPI module can be powered down if the message passing protocol is not being supported in the application. For example, if the direct I/O protocol is being used for data transfers, powering down the CPPI module will save power. In this situation, the buffer descriptor queue SRAMs and mailbox mapper logic s[...]

www.ti.com SRIO Functional Description • This value is compared against the port written value in the TX DMA State CP register, if equal, the interrupt is deasserted. Initialization Example SRIO_REGS->Queue0_RXDMA_HDP = 0 ; SRIO_REGS->Queue1_RXDMA_HDP = 0 ; SRIO_REGS->Queue2_RXDMA_HDP = 0 ; SRIO_REGS->Queue3_RXDMA_HDP = 0 ; SRIO_REGS-[...]

www.ti.com Descriptor Descriptor Buffer Buffer Port Rx DMA State Rx Queue Head Descriptor Pointer SRIO Functional Description Figure 24. RX Buffer Descriptor TX Buffer Descriptor TX_DESCP0_0->TXDESC0 = CSL_FMK( SRIO_TXDESC0_N_POINTER,(int )TX_DESCP0_1 ); //link to TX_DESCP0_1 //NDP TX_DESCP0_0->TXDESC1 = CSL_FMK( SRIO_TXDESC1_B_POINTER,(int )[...]

www.ti.com Descriptor Descriptor Buffer Buffer Port Tx DMA State Tx Queue Head Descriptor Pointer SRIO Functional Description Figure 25. TX Buffer Descriptor Start Message Passing SRIO_REGS->Queue0_RXDMA_HDP = (int )RX_DESCP0_0 ; SRIO_REGS->Queue0_TxDMA_HDP = (int )TX_DESCP0_0 ; 2.3.5 Maintenance The type 8 MAINTENANCE packet format accesses [...]

www.ti.com acklD rsv prio tt 1010 destID sourcelD Reserved srcTID Reserved Doorbell Reg # rsv Doorbell bit CRC PHY LOG TRA LOG TRA PHY 5 3 2 2 4 8 8 8 8 9 2 1 4 16 16 32 16 4 2 10 info (msb) 8 info (lsb) 8 SRIO Functional Description 2.3.6 Doorbell The doorbell operation, consisting of the DOORBELL and RESPONSE transactions (typically a DONE respon[...]

www.ti.com SRIO Functional Description 2.3.7 Congestion Control The RapidIO Flow Control specification is referenced in Table 1 . This section describes the requirements and implementation of congestion control within the peripheral. The peripheral is notified of switch fabric congestion through type 7 RapidIO packets. The packets are referred to a[...]

www.ti.com Reserved RIO_FLOW_CNTL0 31 R, all zeros tt 17 R/W , 0b01 Flow_Cntl_ID0 15 R/W , 0x0000 Reserved RIO_FLOW_CNTL1 31 R, all zeros tt 17 R/W , 0b01 Flow_Cntl_ID1 15 R/W , 0x0000 Reserved RIO_FLOW_CNTL2 31 R, all zeros tt 17 R/W , 0b01 Flow_Cntl_ID2 15 R/W , 0x0000 Reserved RIO_FLOW_CNTL15 31 R, all zeros tt 17 R/W , 0b01 Flow_Cntl_ID15 15 R/[...]

www.ti.com Reserved RIO_LSUn_FLOW_MASKS (Address Offsets: 0x041C, 0x043C, 0x045C, 0x047C) 31-16 R, 0x0000 LSU n Flow Mask 15-0 R/W , 0xFFFF TX Queue1 Flow Mask RIO_TX_CPPI_FLOW_MASKS0 (Address Offsets: 0x0704) 31-16 R/W , 0xFFFF TX Queue0 Flow Mask 15-0 R/W , 0xFFFF TX Queue3 Flow Mask RIO_TX_CPPI_FLOW_MASKS1 (Address Offsets: 0x0708) 31-16 R/W , 0[...]

www.ti.com A0 A0 A2 A2 A1 A1 A3 A3 L2 offset 0x0 DSP defined MMR offset 0x1000 Byte lane 0 31 Byte lane 3 DMA 32b 0 SRIO Functional Description 2.3.8 Endianness RapidIO is based on big endian. This is discussed in detail in section 2.4 of the RapidIO Interconnect specification. Essentially, big endian specifies the address ordering as the most sign[...]

www.ti.com DMA Example The desired operation is to send a T ype 8 maintenance request to an external device. The goal is to read 16B of RapidIO MMR from an external device, starting offset 0x0000. This operation involves the LSU block and utilizes the DMA for transferring the response packet payload. RapidIO defined bit positions A0 A1 A2 A3 31 0 M[...]

www.ti.com SRIO Functional Description 2.3.9.1 Reset Summary After reset, the state of the peripheral depends on the default register values and the BLK n _EN_INIT tieoff values. You can also perform a hard reset using the software of each logical block within the peripheral via the GBL_EN and BLK n _EN bits. The GBL_EN bits reset the peripheral, w[...]

www.ti.com SRIO Functional Description Figure 34. BLK0_EN_STAT (Address 0x003C) 31 1 0 Reserved EN_STAT R-0 R-1 LEGEND: R = Read, W = Write, n = value at reset Figure 35. BLK1_EN (Address 0x0040) 31 1 0 Reserved EN R-0 R/W-1 LEGEND: R = Read, W = Write, n = value at reset Figure 36. BLK1_EN_STAT (Address 0x0044) 31 1 0 Reserved EN_STAT R-0 R-1 LEGE[...]

www.ti.com SRIO Functional Description Table 24. Enable and Enable Status Bit Field Descriptions (continued) Name Bit Access Description BLK1_EN 0 R/W Controls reset to logical block 1, which is the LSU. 0 = Logical block 1 disabled (held in reset, clocks disabled) 1 = Logical block 1 enabled BLK1_EN_STAT 0 R Indicates state of BLK1_EN reset signal[...]

www.ti.com SRIO Functional Description Table 24. Enable and Enable Status Bit Field Descriptions (continued) Name Bit Access Description BLK8_EN_STAT 0 R Indicates state of BLK8_EN reset signal. 0 = Logical block 8 in reset and clock is off 1 = Logical block 8 enabled and clocking The GBL_EN register is implemented with a single ENABLE bit. This bi[...]

www.ti.com SRIO Functional Description Table 25. Emulation Control Signals Name Bit Access Reset Value Description Free 0 R/W 1b FREE = 0, SOFT Bit takes effect FREE = 1, Free run mode (default mode) - Peripheral ignores the EMUSUSP signal and functions normally. Soft 1 R/W 0b SOFT = 0 -> Soft Stop (default mode) SOFT = 1 -> Hard stop – All[...]

www.ti.com SRIO Functional Description 2.3.11.2 PLL, Ports, Device ID and Data Rate Initializations For example, Enable pll, 333MHz, 4p1x, x20. 3.125 Gbps, full rate, ½ rate, ¼ rate: if (srio4p1x_mode){ rdata = SRIO_REGS->PER_SET_CNTL; wdata = 0x0000014F; 4p1x mask = 0x000001FF; mdata = (wdata & mask) | (rdata & ~mask); SRIO_REGS->P[...]

www.ti.com SRIO Functional Description } else{ SRIO_REGS->SP_IP_MODE = 0x04000000; // Jadis mltc/rst/pw enable, clear } SRIO_REGS->IP_PRESCAL = 0x00000021; // srv_clk prescalar=0x21 (333MHz) SRIO_REGS->SP0_SILENCE_TIMER = 0x20000000; // 0, short cycles for sim SRIO_REGS->SP1_SILENCE_TIMER = 0x20000000; // 0, short cycles for sim SRIO_RE[...]

www.ti.com Boot Program Host Controller Optional I2C EEPROM DSP ROM 1x RapidIO SRIO Functional Description 2.3.12 Bootload Capability 2.3.12.1 Configuration It is assumed that an external device will initiate the bootload data transfer and master the DMA interface. Upon reset, the following sequence of events must occur: 1. DSP is placed in SRIO bo[...]

www.ti.com 3 Logical/Transport Error Handling and Logging Logical/Transport Error Handling and Logging Error management registers allow detection and logging of logical/transport layer errors. Figure 41 illustrates the detectable errors. Figure 41. Detectable Errors 31 30 29 28 27 26 25 IO ERR Rspns Msg ERR Rspns GSM ERR Rspns ERR MSG Format ILL Tr[...]

www.ti.com 4 Interrupt Conditions 4.1 CPU Interrupts 4.2 General Description acklD rsv prio tt 1010 destID sourcelD Reserved srcTID Reserved Doorbell Reg # rsv Doorbell bit CRC PHY LOG TRA LOG TRA PHY 5 3 2 2 4 8 8 8 8 9 2 1 4 16 16 32 16 4 2 10 info (msb) 8 info (lsb) 8 Interrupt Conditions This section defines the CPU interrupt capabilities and r[...]

www.ti.com 4.3 Interrupt Condition Control Registers Interrupt Conditions The DOORBELL packet’s 16-bit INFO field indicates which DOORBELL register interrupt bit to set. There are four DOORBELL registers, each currently with 16 bits, allowing 64 interrupt sources or circular buffers. Each bit can be assigned to any core as described by the Interr[...]

www.ti.com Interrupt Conditions Table 26. Interrupt Source Configuration Options Field Access Reset Value Value Function ICSx R 0 0b Condition not present 1b Condition present ICCx W 0 0b No effect 1b Condition status cleared Figure 43. DOORBELL0 Interrupt Registers for Direct I/O Transfers DOORBELL0 Interrupt Condition Status Registers (ICSR) (Add[...]

www.ti.com Interrupt Conditions Where ICS0 - Doorbell1, bit 0, through ICS15 - Doorbell1, bit 15. Figure 45. DOORBELL2 Interrupt Registers for Direct I/O Transfers DOORBELL2 Interrupt Condition Status Registers (ICSR) (Address Offset 0x0220) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 [...]

www.ti.com Interrupt Conditions Figure 47. RX_CPPI Interrupts Using Messaging Mode Data Transfers RX_CPPI Interrupt Condition Status Registers (ICSR) (Address Offset 0x0240) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICS0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W[...]

www.ti.com Interrupt Conditions Where ICS0 - TX CPPI interrupt, buffer descriptor queue 0, through ICS15 - TX CPPI interrupt, buffer descriptor queue 15. Clearing of any ICSR bit is dependent on the CPU writing to the TX DMA State CP. The CPU acknowledges the interrupt after reclaiming all available buffer descriptors by writing the CP value. This [...]

www.ti.com Interrupt Conditions • Bit 21- Transaction was not sent due to DMA data transfer error, LSU3 • Bit 22- Retry Doorbell response received or Atomic Test-and-swap was not allowed (semaphore in use), LSU3 • Bit 23- Packet not sent due to unavailable outbound credit at given priority, LSU3 • Bit 24- Transaction complete, No Errors (Po[...]

www.ti.com Interrupt Conditions The interrupt conditions are programmable to select the interrupt output that will be driven. Each condition is independently programmable to use any of the interrupt destinations supported by the device. For example, a quad core device may support four CPU servicing interrupt destinations, one per core (INTDST0 for [...]

www.ti.com Interrupt Conditions Figure 52. Load/Store Module Interrupt Condition Routing Registers LSU_ICRR0 (Address Offset 0x02E0) 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R/W-0000 R/W-0000 R/W-0000 R/W-0000 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICR0 R/W-0000 R/W-0000 R/W-0000 R/W-0000 LEGEND: R = Read, W = Write, n = value at reset LSU_ICRR1 (Add[...]

www.ti.com 4.4 Interrupt Status Decode Registers Interrupt Conditions Figure 53. Error, Reset, and Special Event Interrupt Condition Routing Registers ERR_RST_EVNT_ICRR (Address Offset 0x02F0) 31 12 11 8 7 4 3 0 Reserved ICR2 ICR1 ICR0 R-0 R/W-0000 R/W-0000 R/W-0000 LEGEND: R = Read, W = Write, n = value at reset ERR_RST_EVNT_ICRR2 (Address Offset [...]

www.ti.com 31 30 29 28 27 26 25 24 23 22 21 20 19 16 18 17 LSU Error , reset and special event Tx CPPI [15:0] Rx CPPI [15:0] ISDR bits: 15 ISDR bits: 14 13 12 1 1 6 8 10 9 7 5 4 3 2 0 1 Doorbell 0 [15:0] Doorbell 1 [15:0] Doorbell 3 [15:0] Doorbell 2 [15:0] 29 29 29 29 29 29 29 29 Interrupt Status Decode Registers INTDST0 INTDST1 INTDST2 INTDST3 IN[...]

www.ti.com 4.5 Interrupt Generation 4.6 Interrupt Pacing Interrupt Conditions LSU bits within the ICSR are logically grouped for a given core and ORd together into a single bit of the decode register. Similarly, the Error/Reset/Special event bits within the ICSR are ORd together into a single bit of the decode register. When either of these bits ar[...]

www.ti.com 4.7 Interrupt Handling Interrupt Conditions Figure 57. INTDST n _RATE_CNTL Interrupt Rate Control Register 31 0 32-bit Count Down Value R/W-0 LEGEND: R = Read, W = Write, n = value at reset Offsets: • INTDST0 – 0x0320 • INTDST1 – 0x0324 • INTDST2 – 0x0328 • INTDST3 – 0x032C • INTDST4 – 0x0330 • INTDST5 – 0x0334 ?[...]

www.ti.com Interrupt Conditions interruptStatus[11] = SRIO_REGS->ERR_RST_EVNT_ICSR; interruptStatus[12] = SRIO_REGS->ERR_RST_EVNT_ICCR; SRIO_REGS->DOORBELL0_ICCR=0xFFFFFFFF; SRIO_REGS->DOORBELL1_ICCR=0xFFFFFFFF; SRIO_REGS->DOORBELL2_ICCR=0xFFFFFFFF; SRIO_REGS->DOORBELL3_ICCR=0xFFFFFFFF; SRIO_REGS->INTDST0_Rate_CNTL=1; SRIO_REGS[...]

www.ti.com 5 SRIO Registers 5.1 Introduction SRIO Registers Table 28 lists the memory-mapped registers for the Serial Rapid IO (SRIO). See the device-specific data manual for the memory address of these registers. Table 28. Serial Rapid IO (SRIO) Registers Offset Acronym Register Description Section 0x0000 PID Peripheral Identification Register Sec[...]

www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x0110 SERDES_CFGTX0_ SERDES Transmit Channel Configuration Register 0 Section 5.14 CNTL 0x0114 SERDES_CFGTX1_ SERDES Transmit Channel Configuration Register 1 Section 5.14 CNTL 0x0118 SERDES_CFGTX2_ SERDES Transmit Channel C[...]

www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x02EC LSU_ICRR3 LSU Interrupt Condition Routing Register 3 Section 5.35 0x02F0 ERR_RST_EVNT_IC Error, Reset, and Special Event Interrupt Condition Routing Register Section 5.36 RR 0x02F4 ERR_RST_EVNT_IC Error, Reset, and Spe[...]

www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x0444 LSU3_REG1 LSU3 Control Register 1 Section 5.42 0x0448 LSU3_REG2 LSU3 Control Register 2 Section 5.43 0x044C LSU3_REG3 LSU3 Control Register 3 Section 5.44 0x0450 LSU3_REG4 LSU3 Control Register 4 Section 5.45 0x0454 LS[...]

www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x0584 QUEUE1_TXDMA_C Queue Transmit DMA Completion Pointer Register 1 Section 5.50 P 0x0588 QUEUE2_TXDMA_C Queue Transmit DMA Completion Pointer Register 2 Section 5.50 P 0x058C QUEUE3_TXDMA_C Queue Transmit DMA Completion P[...]

www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x0630 QUEUE12_RXDMA_ Queue Receive DMA Head Descriptor Pointer Register 12 Section 5.51 HDP 0x0634 QUEUE13_RXDMA_ Queue Receive DMA Head Descriptor Pointer Register 13 Section 5.51 HDP 0x0638 QUEUE14_RXDMA_ Queue Receive DMA[...]

www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x071C TX_CPPI_FLOW_MA Transmit CPPI Supported Flow Mask Register 6 Section 5.54 SKS6 0x0720 TX_CPPI_FLOW_MA Transmit CPPI Supported Flow Mask Register 7 Section 5.54 SKS7 0x0740 RX_QUEUE_TEAR_ Receive Queue Teardown Register[...]

www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x0890 RXU_MAP_L18 MailBox-to-Queue Mapping Register L18 Section 5.61 0x0894 RXU_MAP_H18 MailBox-to-Queue Mapping Register H18 Section 5.62 0x0898 RXU_MAP_L19 MailBox-to-Queue Mapping Register L19 Section 5.61 0x089C RXU_MAP_[...]

www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x1008 ASBLY_ID Assembly Identity CAR Section 5.66 0x100C ASBLY_INFO Assembly Information CAR Section 5.67 0x1010 PE_FEAT Processing Element Features CAR Section 5.68 0x1018 SRC_OP Source Operations CAR Section 5.69 0x101C DE[...]

www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x2048 SP0_ERR_ATTR_CA Port 0 Attributes Error Capture CSR 0 Section 5.96 PT_DBG0 0x204C SP0_ERR_CAPT_DB Port 0 Packet/Control Symbol Error Capture CSR 1 Section 5.97 G1 0x2050 SP0_ERR_CAPT_DB Port 0 Packet/Control Symbol Err[...]

www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x2128 SP3_ERR_RATE Port 3 Error Rate CSR Section 5.101 0x212C SP3_ERR_THRESH Port 3 Error Rate Threshold CSR Section 5.102 0x12000 SP_IP_DISCOVERY Port IP Discovery Timer in 4x mode Section 5.103 _TIMER 0x12004 SP_IP_MODE Po[...]

www.ti.com 5.2 Peripheral Identification Register (PID) SRIO Registers The peripheral identification register (PID) is a constant register that contains the ID and ID revision number for that peripheral. The PID stores version information used to identify the peripheral. All bits within this register are read-only (writes have no effect) meaning th[...]

www.ti.com 5.3 Peripheral Control Register (PCR) SRIO Registers The peripheral control register (PCR) contains a bit that enables or disables the entire peripheral and one bit for every module within the peripheral where this level of control is desired. The module control bits can only be written when the peripheral itself is enabled. In addition,[...]

www.ti.com 5.4 Peripheral Settings Control Register (PER_SET_CNTL) SRIO Registers Figure 60. Peripheral Settings Control Register (PER_SET_CNTL) 31-27 26 25 24 23-21 20-18 17-16 Reserved SW_M LOOP BOOT Reserved TX_PRI2_WM TX_PRI1_WM EM_S BACK _COM LEEP_ PLETE OVER RIDE R-0x00 RW- RW- RW- R-0x00 RW-0x01 RW-0x02 0x01 0x00 0x00 LEGEND: R = Read only; [...]

www.ti.com SRIO Registers Table 31. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions (continued) Bit Field Value Description 17-15 TX_PRI1_WM Transmit credit threshold. Sets the required number of logical layer TX buffers needed to send priority 1 packets across the UDI interface. This is valid for all ports in 1X mode only. R[...]

www.ti.com SRIO Registers Table 31. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions (continued) Bit Field Value Description 2 ENPLL3 Drives SERDES Macro 3 PLL Enable signal 0b Disables macro 3 PLL 1b Enables macro 3 PLL 1 ENPLL2 Drives SERDES Macro 2 PLL Enable signal 0b Disables macro 2 PLL 1b Enables macro 2 PLL 0 ENPLL1 Dr[...]

www.ti.com 5.5 Peripheral Global Enable Register (GBL_EN) SRIO Registers Figure 61. Peripheral Global Enable Register (GBL_EN) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-1 0 Reserved EN R-0x00 RW- 0x00 LEGEND: R = Read only; - n = value after reset Table 32. Peripheral Global Enable Register (GBL_EN) Field Descriptions [...]

www.ti.com 5.6 Peripheral Global Enable Status Register (GBL_EN_STAT) SRIO Registers Figure 62. Peripheral Global Enable Status Register (GBL_EN_STAT) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15 1 0 Reserved GBL_ EN_S TAT R-0x00 R- Undefi ned LEGEND: R = Read only; - n = value after reset Table 33. Peripheral Global Enab[...]

www.ti.com 5.7 Block n Enable Register (BLK n_EN) SRIO Registers There are nine of these registers, one for each of nine logical blocks in the peripheral. Figure 63. Block n Enable Register (BLK n _EN) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-1 0 Reserved EN R-0x00 RW- Undefi ned LEGEND: R = Read only; - n = value aft[...]

www.ti.com 5.8 Block n Enable Status Register (BLK n_EN_STAT) SRIO Registers There are nine of these registers, one for each of nine logical blocks in the peripheral. Figure 64. Block n Enable Status Register (BLK n _EN_STAT) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-1 0 Reserved EN_S TAT R-0x00 R- Undefi ned LEGEND: R[...]

www.ti.com 5.9 RapidIO DEVICEID1 Register (DEVICEID_REG1) SRIO Registers Figure 65. RapidIO DEVICEID1 Register (DEVICEID_REG1) 31-24 23-16 Reserved 8BNODEID R-0x0000 RW-0x00FF LEGEND: R = Read only; - n = value after reset 15-0 16BNODEID RW-0xFFFF LEGEND: R = Read only; - n = value after reset Table 36. RapidIO DEVICEID1 Register (DEVICEID_REG1) Fi[...]

www.ti.com 5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2) SRIO Registers Figure 66. RapidIO DEVICEID2 Register (DEVICEID_REG2) 31-24 23-16 Reserved 8BNODEID R-0x0000 RW-0x00FF LEGEND: R = Read only; - n = value after reset 15-0 16BNODEID RW-0xFFFF LEGEND: R = Read only; - n = value after reset Table 37. RapidIO DEVICEID2 Register (DEVICEID_REG2) F[...]

www.ti.com 5.11 Packet Forwarding Register n for 16b DeviceIDs (PF_16B_CNTL n) SRIO Registers There are four of these registers, to support four ports. Figure 67. Packet Forwarding Register n for 16b DeviceIDs (PF_16B_CNTL n ) 31-16 16BIT_DEVID_UP_BOUND RW-0xFFFF LEGEND: R = Read only; - n = value after reset 15-0 16BIT_DEVID_LOW_BOUND RW-0xFFFF LE[...]

www.ti.com 5.12 Packet Forwarding Register n for 8b DeviceIDs (PF_8B_CNTL n) SRIO Registers There are four of these registers, to support four ports. Figure 68. Packet Forwarding Register n for 8b DeviceIDs (PF_8B_CNTL n ) 31-18 17-16 Reserved OUT_BOUND_ PORT R-0x00 RW-0x03 LEGEND: R = Read only; - n = value after reset 15-8 7-0 8BIT_DEVID_UP_BOUND[...]

www.ti.com 5.13 SERDES Receive Channel Configuration Registers n (SERDES_CFGRX n_CNTL) SRIO Registers There are four of these registers, to support four ports. Figure 69. SERDES Receive Channel Configuration Registers n (SERDES_CFGRX n _CNTL) 31 26 25 24 23 22 19 18 16 Reserved Reserv Reserv Reserv EQ CDR ed ed ed R-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15[...]

www.ti.com SRIO Registers Table 40. SERDES Receive Channel Configuration Registers n (SERDES_CFGRX n _CNTL) Field Descriptions (continued) Bit Field Value Description 11 Reserved Reserved. 10:8 TERM Termination. Selects input termination options suitable for a variety of AC or DC coupled scenarios. 000 Common point connected to VDDT. This configura[...]

www.ti.com 5.14 SERDES Transmit Channel Configuration Registers n (SERDES_CFGTX n_CNTL) SRIO Registers There are four of these registers, to support four ports. Figure 70. SERDES Transmit Channel Configuration Registers n (SERDES_CFGTX n _CNTL) 31 17 16 Reserved ENFT P R-0 R/W-0 15 12 11 9 8 7 6 5 4 2 1 0 DE SWING CM INVPA RATE BUSWIDTH Reserv ENTX[...]

www.ti.com SRIO Registers Table 43. SWING Bits CFGTX[11:9] Amplitude (mV dfpp ) 000 125 001 250 010 500 011 625 100 750 101 1000 110 1125 111 1250 Table 44. DE Bits CFGTX[15:12] Amplitude Reduction % dB 0000 0 0 0001 4.76 -0.42 0010 9.52 -0.87 0011 14.28 -1.34 0100 19.04 -1.83 0101 23.8 -2.36 0110 28.56 -2.92 0111 33.32 -3.52 1000 38.08 -4.16 1001 [...]

www.ti.com 5.15 SERDES Macro Configuration Register n (SERDES_CFG n_CNTL) SRIO Registers There are four of these registers, to support four ports. Figure 71. SERDES Macros CFG (0-3) Registers (SERDES_CFG n _CNTL) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LB Reserved MPY ENPLL R-0 R/W-0 R-0 R/W-0 R/W-0 LEGEND: R = Read, W = W[...]

www.ti.com 5.16 DOORBELL n Interrupt Status Register (DOORBELL n_ICSR) SRIO Registers Each of the four doorbells is supported by a register of this type. Figure 72. DOORBELL n Interrupt Status Register (DOORBELL n _ICSR) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ICS (0-15) R-0x00 LEGEND: R = Read only; - n = value af[...]

www.ti.com 5.17 DOORBELL n Interrupt Clear Register (DOORBELL n_ICCR) SRIO Registers Each of the four doorbells is supported by a register of this type. Figure 73. DOORBELL n Interrupt Clear Register (DOORBELL n _ICCR) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ICC (0-15) W-0x00 LEGEND: R = Read only; - n = value afte[...]

www.ti.com 5.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR) SRIO Registers Figure 74. RX CPPI Interrupt Status Register (RX_CPPI_ICSR) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ICS (0-15) R-0x00 LEGEND: R = Read only; - n = value after reset Table 48. RX CPPI Interrupt Status Register (RX_CPPI_ICSR) Field Descri[...]

www.ti.com 5.19 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) SRIO Registers Figure 75. RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ICC (0-15) W-0x00 LEGEND: R = Read only; - n = value after reset Table 49. RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) Field Descripti[...]

www.ti.com 5.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) SRIO Registers Figure 76. TX CPPI Interrupt Status Register (TX_CPPI_ICSR) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ICS (0-15) R-0x00 LEGEND: R = Read only; - n = value after reset Table 50. TX CPPI Interrupt Status Register (TX_CPPI_ICSR) Field Descri[...]

www.ti.com 5.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) SRIO Registers Figure 77. TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ICC (0-15) W-0x00 LEGEND: R = Read only; - n = value after reset Table 51. TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) Field Descripti[...]

www.ti.com 5.22 LSU Status Interrupt Register (LSU_ICSR) SRIO Registers Figure 78. LSU Status Interrupt Register (LSU_ICSR) 31-16 ICS(31-16) R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ICS(15-0) R-0x00 LEGEND: R = Read only; - n = value after reset Table 52. LSU Status Interrupt Register (LSU_ICSR) Field Descriptions Bit Field Value [...]

www.ti.com 5.23 LSU Clear Interrupt Register (LSU _ICCR) SRIO Registers Figure 79. LSU Clear Interrupt Register (LSU _ICCR) 31-16 ICC(31-16) W-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ICC(15-0) W-0x00 LEGEND: R = Read only; - n = value after reset Table 53. LSU Clear Interrupt Register (LSU _ICCR) Field Descriptions Bit Field Value [...]

www.ti.com 5.24 Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR) SRIO Registers Figure 80. Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR) 31-17 16 Reserved ICS16 R-0x00 R/W- 0x00 LEGEND: R = Read only; - n = value after reset 15-12 11 10 9 8 7-3 2 1 0 Reserved ICS11 ICS10 ICS9 ICS8 Reserve[...]

www.ti.com 5.25 Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) SRIO Registers Figure 81. Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) 31-17 16 Reserved ICC16 R-0x00 W- 0x00 LEGEND: R = Read only; - n = value after reset 15-12 11 10 9 8 7-3 2 1 0 Reserved ICC11 ICC10 ICC9 ICC8 Reserved IC[...]

www.ti.com 5.26 DOORBELL n Interrupt Condition Routing Register (DOORBELL n_ICRR) SRIO Registers Each of the four doorbells is supported by a register of this type. Figure 82. DOORBELL n Interrupt Condition Routing Register (DOORBELL n _ICRR) 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 15 12 11 8 7 4 3 0 ICR3 ICR[...]

www.ti.com 5.27 DOORBELL n Interrupt Condition Routing Register 2 (DOORBELL n_ICRR2) SRIO Registers Each of the four doorbells is supported by a register of this type. Figure 83. DOORBELL n Interrupt Condition Routing Register 2 (DOORBELL n _ICRR2) 31 28 27 24 23 20 19 16 ICR15 ICR14 ICR13 ICR12 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 15 12 11 8 7 4 3 [...]

www.ti.com 5.28 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) SRIO Registers Figure 84. RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICR0 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 LEGEND: R = Read, W = Write, n [...]

www.ti.com 5.29 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2) SRIO Registers Figure 85. RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2) 31 28 27 24 23 20 19 16 ICR15 ICR14 ICR13 ICR12 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 15 12 11 8 7 4 3 0 ICR11 ICR10 ICR9 ICR8 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 LEGEND: R = Read, W = W[...]

www.ti.com 5.30 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) SRIO Registers Figure 86. TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICR0 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 LEGEND: R = Read, W = Write, n [...]

www.ti.com 5.31 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) SRIO Registers Figure 87. TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) 31 28 27 24 23 20 19 16 ICR15 ICR14 ICR13 ICR12 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 15 12 11 8 7 4 3 0 ICR11 ICR10 ICR9 ICR8 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 LEGEND: R = Read, W = W[...]

www.ti.com 5.32 LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0) SRIO Registers Figure 88. LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0) 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R/W-0000 R/W-0000 R/W-0000 R/W-0000 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICR0 R/W-0000 R/W-0000 R/W-0000 R/W-0000 LEGEND: R = Read, W = Write, [...]

www.ti.com 5.33 LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) SRIO Registers Figure 89. LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) 31 28 27 24 23 20 19 16 ICR15 ICR14 ICR13 ICR12 R/W-0000 R/W-0000 R/W-0000 R/W-0000 15 12 11 8 7 4 3 0 ICR11 ICR10 ICR9 ICR8 R/W-0000 R/W-0000 R/W-0000 R/W-0000 LEGEND: R = Read, W = W[...]

www.ti.com 5.34 LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) SRIO Registers Figure 90. LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) 31 28 27 24 23 20 19 16 ICR23 ICR22 ICR21 ICR20 R/W-0000 R/W-0000 R/W-0000 R/W-0000 15 12 11 8 7 4 3 0 ICR19 ICR18 ICR17 ICR16 R/W-0000 R/W-0000 R/W-0000 R/W-0000 LEGEND: R = Read, W =[...]

www.ti.com 5.35 LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3) SRIO Registers Figure 91. LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3) 31 28 27 24 23 20 19 16 ICR31 ICR30 ICR29 ICR28 R/W-0000 R/W-0000 R/W-0000 R/W-0000 15 12 11 8 7 4 3 0 ICR27 ICR26 ICR25 ICR24 R/W-0000 R/W-0000 R/W-0000 R/W-0000 LEGEND: R = Read, W =[...]

www.ti.com 5.36 Error, Reset, and Special Event Interrupt Condition Routing Register SRIO Registers (ERR_RST_EVNT_ICRR) Figure 92. Error, Reset, and Special Event Interrupt Condition Routing Register (ERR_RST_EVNT_ICRR) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-12 11-8 7-4 3-0 Reserved ICR2 ICR1 ICR0 R-0x00 RW-0x00 RW-[...]

www.ti.com 5.37 Error, Reset, and Special Event Interrupt Condition Routing Register 2 SRIO Registers (ERR_RST_EVNT_ICRR2) Figure 93. Error, Reset, and Special Event Interrupt Condition Routing Register 2 (ERR_RST_EVNT_ICRR2) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-12 11-8 7-4 3-0 ICR11 ICR10 ICR9 ICR8 RW-0x00 RW-0x0[...]

www.ti.com 5.38 Error, Reset, and Special Event Interrupt Condition Routing Register 3 SRIO Registers (ERR_RST_EVNT_ICRR3) Figure 94. Error, Reset, and Special Event Interrupt Condition Routing Register 3 (ERR_RST_EVNT_ICRR3) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-4 3-0 Reserved ICR16 R-0x00 RW-0x00 LEGEND: R = Read[...]

www.ti.com 5.39 INTDST n Interrupt Status Decode Registers (INTDST n_DECODE) SRIO Registers There are eight of these registers. Figure 95. INTDST n Interrupt Status Decode Registers (INTDST n _DECODE) 31-16 ISDR[31-16] R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ISDR[15-0] R-0x00 LEGEND: R = Read only; - n = value after reset Table 6[...]

www.ti.com 5.40 INTDST n Interrupt Rate Control Registers (INTDST n_RATE_CNTL) SRIO Registers There are eight of these registers. Figure 96. INTDST n Interrupt Rate Control Registers (INTDST n _RATE_CNTL) 31-16 COUNT_DOWN_VALUE RW-0x00 LEGEND: R = Read only; - n = value after reset 15-0 COUNT_DOWN_VALUE RW-0x00 LEGEND: R = Read only; - n = value af[...]

www.ti.com 5.41 LSU n Control Register 0 (LSU n_REG0) SRIO Registers There are four of these registers, one for each LSU. Figure 97. LSU n Control Register 0 (LSU n _REG0) 31-16 ADDRESS_MSB RW-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ADDRESS_MSB RW-0x00 LEGEND: R = Read only; - n = value after reset Table 71. LSU n Control Register [...]

www.ti.com 5.42 LSU n Control Register 1 (LSU n_REG1) SRIO Registers There are four of these registers, one for each LSU. Figure 98. LSU n Control Register 1 (LSU n _REG1) 31-16 ADDRESS_LSB_CONFIG_OFFSET RW-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ADDRESS_LSB_CONFIG_OFFSET RW-0x00 LEGEND: R = Read only; - n = value after reset Table[...]

www.ti.com 5.43 LSU n Control Register 2 (LSU n_REG2) SRIO Registers There are four of these registers, one for each LSU. Figure 99. LSU n Control Register 2 (LSU n _REG2) 31-16 DSP_ADDRESS RW-0x00 LEGEND: R = Read only; - n = value after reset 15-0 DSP_ADDRESS RW-0x00 LEGEND: R = Read only; - n = value after reset Table 73. LSU n Control Register [...]

www.ti.com 5.44 LSU n Control Register 3 (LSU n_REG3) SRIO Registers There are four of these registers, one for each LSU. Figure 100. LSU n Control Register 3 (LSU n _REG3) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-12 11-0 Reserved BYTE_COUNT R-0x00 RW-0x00 LEGEND: R = Read only; - n = value after reset Table 74. LSU n[...]

www.ti.com 5.45 LSU n Control Register 4 (LSU n_REG4) SRIO Registers There are four of these registers, one for each LSU. Figure 101. LSU n Control Register 4 (LSU n _REG4) 31-30 29-28 27-26 25-24 23-16 OUTPORTID PRIORITY XAMBS ID_SIZE DESTID RW-0x00 RW-0x00 RW-0x00 RW-0x00 RW-0x00 LEGEND: R = Read only; - n = value after reset 15-8 7-1 0 DESTID Re[...]

www.ti.com 5.46 LSU n Control Register 5 (LSU n_REG5) SRIO Registers There are four of these registers, one for each LSU. Figure 102. LSU n Control Register 5 (LSU n _REG5) 31-16 DRBLL_INFO RW-0x00 LEGEND: R = Read only; - n = value after reset 15-8 7-0 HOP_COUNT PACKET_TYPE RW-0x00 RW-0x00 LEGEND: R = Read only; - n = value after reset Table 76. L[...]

www.ti.com 5.47 LSU n Control Register 6 (LSU n_REG6) SRIO Registers There are four of these registers, one for each LSU. Figure 103. LSU n Control Register 6 (LSU n _REG6) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-5 4-1 0 Reserved COMPLETION_CODE BSY R-0x00 R-0x00 R- 0x00 LEGEND: R = Read only; - n = value after reset[...]

www.ti.com 5.48 LSU Congestion Control Flow Mask n (LSU_FLOW_MASKS n) SRIO Registers Figure 104. LSU Congestion Control Flow Mask n (LSU_FLOW_MASKS n ) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 FLOW_MASK (0-15) RW-0x01 LEGEND: R = Read only; - n = value after reset Table 78. LSU Congestion Control Flow Mask n (LSU_FL[...]

www.ti.com 5.49 Queue Transmit DMA Head Descriptor Pointer Registers (QUEUE n_TXDMA_HDP) SRIO Registers There are sixteen of these registers. Figure 105. Queue Transmit DMA Head Descriptor Pointer Registers (QUEUE n _TXDMA_HDP) 31-16 TX_HDP RW-0x00 LEGEND: R = Read only; - n = value after reset 15-0 TX_HDP RW-0x00 LEGEND: R = Read only; - n = value[...]

www.ti.com 5.50 Queue Transmit DMA Completion Pointer Registers (QUEUE n_TXDMA_CP) SRIO Registers There are sixteen of these registers. Figure 106. Queue Transmit DMA Completion Pointer Registers (QUEUE n _TXDMA_CP) 31-16 TX_CP RW-0x00 LEGEND: R = Read only; - n = value after reset 15-0 TX_CP RW-0x00 LEGEND: R = Read only; - n = value after reset T[...]

www.ti.com 5.51 Queue Receive DMA Head Descriptor Pointer Registers (QUEUE n_RXDMA_HDP) SRIO Registers There are sixteen of these registers. Figure 107. Queue Receive DMA Head Descriptor Pointer Registers (QUEUE n _RXDMA_HDP) 31-16 RX_HDP RW-0x00 LEGEND: R = Read only; - n = value after reset 15-0 RX_HDP RW-0x00 LEGEND: R = Read only; - n = value a[...]

www.ti.com 5.52 Queue Receive DMA Completion Pointer Registers (QUEUE n_RXDMA_CP) SRIO Registers There are sixteen of these registers. Figure 108. Queue Receive DMA Completion Pointer Registers (QUEUE n _RXDMA_CP) 31-16 RX_CP RW-0x00 LEGEND: R = Read only; - n = value after reset 15-0 RX_CP RW-0x00 LEGEND: R = Read only; - n = value after reset Tab[...]

www.ti.com 5.53 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) SRIO Registers Figure 109. Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU E15_T E14_T [...]

www.ti.com 5.54 Transmit CPPI Supported Flow Mask Registers n (TX_CPPI_FLOW_MASKS n) SRIO Registers There are eight registers of this type. See Figure 28 for more information on this register. Figure 110. Transmit CPPI Supported Flow Mask Registers n (TX_CPPI_FLOW_MASKS n ) Transmit CPPI Supported Flow Mask Register 0 (TX_CPPI_FLOW_MASKS0) 31-16 15[...]

www.ti.com SRIO Registers Transmit CPPI Supported Flow Mask Register 7 (TX_CPPI_FLOW_MASKS7) 31-16 15-0 QUEUE15_FLOW_MASK QUEUE14_FLOW_MASK RW-0x01 RW-0x01 LEGEND: R = Read only; - n = value after reset Table 84. Transmit CPPI Supported Flow Mask Registers n (TX_CPPI_FLOW_MASKS n ) Field Descriptions Field Value Description QUEUE n _FLOW_ Flow mask[...]

www.ti.com 5.55 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) SRIO Registers Figure 111. Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU E15_T E14_T E1[...]

www.ti.com 5.56 Receive CPPI Control Register (RX_CPPI_CNTL) SRIO Registers Figure 112. Receive CPPI Control Register (RX_CPPI_CNTL) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU E15_I E14_I E13_I E12_I E11_I [...]

www.ti.com 5.57 Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0) SRIO Registers Figure 113. Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0) 31-28 27-24 23-20 19-16 TX_QUEUE_MAP3_NUM_MSG TX_QUEUE_MAP3_QUEUE_PT TX_QUEUE_MAP2_NUM_MSG TX_QUEUE_MAP2_QUEUE_PT S R S R RW-0x00 RW-0x03 RW-0x00 RW-0x02 LEGEND: R =[...]

www.ti.com 5.58 Transmit CPPI Weighted Round Robin Control Register 1 (TX_QUEUE_CNTL1) SRIO Registers Figure 114. Transmit CPPI Weighted Round Robin Control Register 1 (TX_QUEUE_CNTL1) 31-28 27-24 23-20 19-16 TX_QUEUE_MAP7_NUM_MSG TX_QUEUE_MAP7_QUEUE_PT TX_QUEUE_MAP6_NUM_MSG TX_QUEUE_MAP6_QUEUE_PT S R S R RW-0x00 RW-0x07 RW-0x00 RW-0x06 LEGEND: R =[...]

www.ti.com 5.59 Transmit CPPI Weighted Round Robin Control Register 2 (TX_QUEUE_CNTL2) SRIO Registers Figure 115. Transmit CPPI Weighted Round Robin Control Register 2 (TX_QUEUE_CNTL2) 31-28 27-24 23-20 19-16 TX_QUEUE_MAP11_NUM_MSG TX_QUEUE_MAP11_QUEUE_P TX_QUEUE_MAP10_NUM_MSG TX_QUEUE_MAP10_QUEUE_P S TR S TR RW-0x00 RW-0x0B RW-0x00 RW-0x0A LEGEND:[...]

www.ti.com 5.60 Transmit CPPI Weighted Round Robin Control Register 3 (TX_QUEUE_CNTL3) SRIO Registers Figure 116. Transmit CPPI Weighted Round Robin Control Register 3 (TX_QUEUE_CNTL3) 31-28 27-24 23-20 19-16 TX_QUEUE_MAP15_NUM_MSG TX_QUEUE_MAP15_QUEUE_P TX_QUEUE_MAP14_NUM_MSG TX_QUEUE_MAP14_QUEUE_P S TR S TR RW-0x00 RW-0x0F RW-0x00 RW-0x0E LEGEND:[...]

www.ti.com 5.61 Mailbox-to-Queue Mapping Register L n (RXU_MAP_L n) SRIO Registers Figure 117. Mailbox-to-Queue Mapping Register L n (RXU_MAP_L n ) 31-30 29-24 23-22 21-16 LETTER_MAS MAILBOX_MASK LETTER MAILBOX K RW-0x03 RW-0x3F RW-0x00 RW-0x00 LEGEND: R = Read only; - n = value after reset 15-0 SOURCEID RW-0x00 LEGEND: R = Read only; - n = value a[...]

www.ti.com 5.62 Mailbox-to-Queue Mapping Register H n (RXU_MAP_H n) SRIO Registers Figure 118. Mailbox-to-Queue Mapping Register H n (RXU_MAP_H n ) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-10 9-8 7-6 5-2 1 0 Reserved TT Reserved QUEUE_ID PROM SEGM ISCUO ENT_ US MAPPI NG R-0x00 RW-0x01 R-0x00 RW-0x00 RW- RW- 0x00 0x00 [...]

www.ti.com 5.63 Flow Control Table Entry Registers (FLOW_CNTL n) SRIO Registers There are sixteen of these registers. Figure 119. Flow Control Table Entry Registers (FLOW_CNTL n ) 31-18 17-16 Reserved TT R-0x00 RW-0x01 LEGEND: R = Read only; - n = value after reset 15-0 FLOW_CNTL_ID RW-0x00 LEGEND: R = Read only; - n = value after reset Table 93. F[...]

www.ti.com 5.64 Device Identity CAR (DEV_ID) SRIO Registers Figure 120. Device Identity CAR (DEV_ID) 31-16 DEVICEIDENTITY R-0x0000 LEGEND: R = Read only; - n = value after reset 15-0 DEVICE_VENDORIDENTITY R-0x0030 LEGEND: R = Read only; - n = value after reset Table 94. Device Identity CAR (DEV_ID) Field Descriptions Bit Field Value Description 31-[...]

www.ti.com 5.65 Device Information CAR (DEV_INFO) SRIO Registers Figure 121. Device Information CAR (DEV_INFO) 31-16 DEVICEREV R-0x0000 LEGEND: R = Read only; - n = value after reset 15-0 DEVICEREV R-0x0000 LEGEND: R = Read only; - n = value after reset Table 95. Device Information CAR (DEV_INFO) Field Descriptions Bit Field Value Description 31-0 [...]

www.ti.com 5.66 Assembly Identity CAR (ASBLY_ID) SRIO Registers Figure 122. Assembly Identity CAR (ASBLY_ID) 31-16 ASSY_IDENTITY R-0x0000 LEGEND: R = Read only; - n = value after reset 15-0 ASSY_VENDORIDENTITY R-0x0030 LEGEND: R = Read only; - n = value after reset Table 96. Assembly Identity CAR (ASBLY_ID) Field Descriptions Bit Field Value Descri[...]

www.ti.com 5.67 Assembly Information CAR (ASBLY_INFO) SRIO Registers Figure 123. Assembly Information CAR (ASBLY_INFO) 31-16 ASSYREV R-0x0000 LEGEND: R = Read only; - n = value after reset 15-0 EXTENDEDFEATURESPTR R-0x0100 LEGEND: R = Read only; - n = value after reset Table 97. Assembly Information CAR (ASBLY_INFO) Field Descriptions Bit Field Val[...]

www.ti.com 5.68 Processing Element Features CAR (PE_FEAT) SRIO Registers Figure 124. Processing Element Features CAR (PE_FEAT) 31 30 29 28 27-16 BRIDG MEMO PROC SWIT Reserved E RY ESSO CH R R- R- R- R- R-0x00 0x00 0x00 0x01 0x00 LEGEND: R = Read only; - n = value after reset 15-8 7 6 5 4 3 2-0 Reserved FLOW RETR CRF_ LARG EXTE EXTENDED_ADDRESS _CON[...]

www.ti.com 5.69 Source Operations CAR (SRC_OP) SRIO Registers Figure 125. Source Operations CAR (SRC_OP) 31-18 17-16 Reserved IMPLMNT_DEF INED_2 R-0x00 R-0x00 LEGEND: R = Read only; - n = value after reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1-0 READ WRIT STRE WRIT DATA DOOR Reserv ATOMI ATOMI ATOMI ATOMI ATOMI Reserv PORT IMPLMNT_DEF E AM_W E_WIT _M[...]

www.ti.com 5.70 Destination Operations CAR (DEST_OP) SRIO Registers Figure 126. Destination Operations CAR (DEST_OP) 31-18 17-16 Reserved IMPLMNT_DEF INED_2 R-0x00 R-0x00 LEGEND: R = Read only; - n = value after reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1-0 READ WRIT STRE WRIT DATA DOOR Reserv ATOMI ATOMI ATOMI ATOMI ATOMI Reserv PORT IMPLMNT_DEF E A[...]

www.ti.com 5.71 Processing Element Logical Layer Control CSR (PE_LL_CTL) SRIO Registers Figure 127. Processing Element Logical Layer Control CSR (PE_LL_CTL) 31-16 Reserved R-0x0000 LEGEND: R = Read only; - n = value after reset 15-3 2-0 Reserved EXTENDED_ADDRESS ING_CONTROL R-0x0000 RW-0x0001 LEGEND: R = Read only; - n = value after reset Table 101[...]

www.ti.com 5.72 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) SRIO Registers Figure 128. Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) 31 30-16 Reserv LCSBA ed R- R-0x00 0x00 LEGEND: R = Read only; - n = value after reset 15-0 LCSBA R-0x00 LEGEND: R = Read only; - n = value after reset Table 102. Local Configuration Spac[...]

www.ti.com 5.73 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) SRIO Registers Figure 129. Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) 31-16 LCSBA R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 LCSBA R-0x00 LEGEND: R = Read only; - n = value after reset Table 103. Local Configuration Space Base Address 1 CSR (L[...]

www.ti.com 5.74 Base Device ID CSR (BASE_ID) SRIO Registers Figure 130. Base Device ID CSR (BASE_ID) 31-24 23-16 Reserved BASE_DEVICEID R-0x00 RW-0x00FF LEGEND: R = Read only; - n = value after reset 15-0 LARGE_BASE_DEVICEID RW-0xFFFF LEGEND: R = Read only; - n = value after reset Table 104. Base Device ID CSR (BASE_ID) Field Descriptions Bit Field[...]

www.ti.com 5.75 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) SRIO Registers See Section 2.4.2 of the RapidIO Specification for description of this register. It provides a lock function that is write-once/reset-able. Figure 131. Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset [...]

www.ti.com 5.76 Component Tag CSR (COMP_TAG) SRIO Registers Figure 132. Component Tag CSR (COMP_TAG) 31-16 COMPONENT_TAG RW-0x00 LEGEND: R = Read only; - n = value after reset 15-0 COMPONENT_TAG RW-0x00 LEGEND: R = Read only; - n = value after reset Table 106. Component Tag CSR (COMP_TAG) Field Descriptions Bit Field Value Description 31-0 COMPONEN[...]

www.ti.com 5.77 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) SRIO Registers Figure 133. 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) 31-16 EF_PTR R-0x1000 LEGEND: R = Read only; - n = value after reset 15-0 EF_ID R-0x0001 LEGEND: R = Read only; - n = value after reset Table 107. 1x/4x LP_Serial Port Mai[...]

www.ti.com 5.78 Port Link Time-Out Control CSR (SP_LT_CTL) SRIO Registers Figure 134. Port Link Time-Out Control CSR (SP_LT_CTL) 31-16 TIMEOUT_VALUE RW-0xFFFFFF LEGEND: R = Read only; - n = value after reset 15-8 7-0 TIMEOUT_VALUE Reserved RW-0xFFFFFF R-0x00 LEGEND: R = Read only; - n = value after reset Table 108. Port Link Timeout Control CSR (SP[...]

www.ti.com 5.79 Port Response Time-Out Control CSR (SP_RT_CTL) SRIO Registers Figure 135. Port Response Time-Out Control CSR (SP_RT_CTL) 31-16 TIMEOUT_VALUE RW-0xFFFFFF LEGEND: R = Read only; - n = value after reset 15-8 7-0 TIMEOUT_VALUE Reserved RW-0xFFFFFF R-0x00 LEGEND: R = Read only; - n = value after reset Table 109. Port Response Time-Out Co[...]

www.ti.com 5.80 Port General Control CSR (SP_GEN_CTL) SRIO Registers Figure 136. Port General Control CSR (SP_GEN_CTL) 31 30 29 28-16 HOST MAST DISCO Reserved ER_E VERE NABL D E RW- RW- RW- R-0x00 0x00 0x00 0x00 LEGEND: R = Read only; - n = value after reset 15-0 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset Table 110. Port General[...]

www.ti.com 5.81 Port Link Maintenance Request CSR n (SP n_LM_REQ) SRIO Registers Each of the four ports is supported by a register of this type. Figure 137. Port Link Maintenance Request CSR n (SP n _LM_REQ) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-3 2-0 Reserved COMMAND R-0x00 RW-0x00 LEGEND: R = Read only; - n = val[...]

www.ti.com 5.82 Port Link Maintenance Response CSR n (SP n_LM_RESP) SRIO Registers Each of the four ports is supported by a register of this type. Figure 138. Port Link Maintenance Response CSR n (SP n _LM_RESP) 31 30-16 RESP Reserved ONSE _VALI D R- R-0x00 0x00 LEGEND: R = Read only; - n = value after reset 15-10 9-5 4-0 Reserved ACKID_STATUS LINK[...]

www.ti.com 5.83 Port Local AckID Status CSR n (SP n_ACKID_STAT) SRIO Registers Each of the four ports is supported by a register of this type. Figure 139. Port Local AckID Status CSR n (SP n _ACKID_STAT) 31-29 28-24 23-16 Reserved INBOUND_ACKID Reserved R-0x00 RW-0x00 R-0x00 LEGEND: R = Read only; - n = value after reset 15-13 12-8 7-5 4-0 Reserved[...]

www.ti.com 5.84 Port Error and Status CSR n (SP n_ERR_STAT) SRIO Registers Each of the four ports is supported by a register of this type. Figure 140. Port Error and Status CSR n (SP n _ERR_STAT) 31-27 26 25 24 23-21 20 19 18 17 16 Reserved OUTP OUTP OUTP Reserved OUTP OUTP OUTP OUTP OUTP UT_P UT_FL UT_D UT_R UT_R UT_R UT_E UT_E KT_D D_EN EGRD ETRY[...]

www.ti.com SRIO Registers Table 114. Port Error and Status CSR n (SP n _ERR_STAT) Field Descriptions (continued) Bit Field Value Description 1 PORT_OK The input and output ports are initialized and the port is exchanging error-free control symbols with the attached device (read-only). 0 PORT_UNINITIA Input and output ports are not initialized. This[...]

www.ti.com 5.85 Port Control CSR n (SP n_CTL) SRIO Registers Each of the four ports is supported by a register of this type. Figure 141. Port Control CSR n (SP n _CTL) 31-30 29-27 26-24 23 22 21 20 19 18-16 PORT_WIDTH INITIALIZED_PORT_WI PORT_WIDTH_OVERRI PORT OUTP INPUT ERRO MULTI Reserved DTH DE _DISA UT_P _POR R_CH CAST BLE ORT_ T_EN ECK_ _PAR E[...]

www.ti.com SRIO Registers Table 115. Port Control CSR n (SP n _CTL) Field Descriptions (continued) Bit Field Value Description 21 INPUT_PORT_E Input port receive enable NABLE 0b Port is stopped and only enabled to route or respond I/O logical MAINTENANCE packets, depending upon the functionality of the processing element. Other packets generate pac[...]

www.ti.com 5.86 Error Reporting Block Header (ERR_RPT_BH) SRIO Registers Figure 142. Error Reporting Block Header (ERR_RPT_BH) 31-16 EF_PTR R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 EF_ID R-0x0007 LEGEND: R = Read only; - n = value after reset Table 116. Error Reporting Block Header (ERR_RPT_BH) Field Descriptions Bit Field Value D[...]

www.ti.com 5.87 Logical/Transport Layer Error Detect CSR (ERR_DET) SRIO Registers Figure 143. Logical/Transport Layer Error Detect CSR (ERR_DET) 31 30 29 28 27 26 25 24 23 22 21-16 IO_ER MSG_ GSM_ ERR_ ILL_T ILL_T MSG_ PKT_ UNSO UNSU Reserved R_RS ERR_ ERR_ MSG_ RANS RANS REQ_ RSPN LICITE PPOR PNS RSPN RSPN FORM _DEC _TRG TIMEO S_TIM D_RS TED_T S S[...]

www.ti.com 5.88 Logical/Transport Layer Error Enable CSR (ERR_EN) SRIO Registers Figure 144. Logical/Transport Layer Error Enable CSR (ERR_EN) 31 30 29 28 27 26 25 24 23 22 21-16 IO_ERR_ MSG_E GSM_E ERR_MS ILL_TR ILL_TR MSG_RE PKT_R UNSOLICI UNSUP Reserved RESP_EN RR_RE RR_RE G_FORM ANS_D ANS_T Q_TIMEO ESP_TI TED_RES PORTE ABLE SP_EN SP_EN AT_ENAB [...]

www.ti.com 5.89 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) SRIO Registers Figure 145. Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) 31-16 ADDRESS_63_32 R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ADDRESS_63_32 R-0x00 LEGEND: R = Read only; - n = value after reset Table 119. Logical/Transport Layer[...]

www.ti.com 5.90 Logical/Transport Layer Address Capture CSR (ADDR_CAPT) SRIO Registers Figure 146. Logical/Transport Layer Address Capture CSR (ADDR_CAPT) 31-16 ADDRESS_31_3 R-0x00 LEGEND: R = Read only; - n = value after reset 15-3 2 1-0 ADDRESS_31_3 Reserv XAMSBS ed R-0x00 R- R-0x00 0x00 LEGEND: R = Read only; - n = value after reset Table 120. L[...]

www.ti.com 5.91 Logical/Transport Layer Device ID Capture CSR (ID_CAPT) SRIO Registers Figure 147. Logical/Transport Layer Device ID Capture CSR (ID_CAPT) 31-24 23-16 MSB_DESTID DESTID R-0x00 R-0x00 LEGEND: R = Read only; - n = value after reset 15-8 7-0 MSB_SOURCEID SOURCEID R-0x00 R-0x00 LEGEND: R = Read only; - n = value after reset Table 121. L[...]

www.ti.com 5.92 Logical/Transport Layer Control Capture CSR (CTRL_CAPT) SRIO Registers Figure 148. Logical/Transport Layer Control Capture CSR (CTRL_CAPT) 31-28 27-24 23-16 FTYPE TTYPE MSGINFO R-0x00 R-0x00 R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 IMP_SPECIFIC R-0x00 LEGEND: R = Read only; - n = value after reset Table 122. Logica[...]

www.ti.com 5.93 Port-Write Target Device ID CSR (PW_TGT_ID) SRIO Registers Figure 149. Port-Write Target Device ID CSR (PW_TGT_ID) 31-24 23-16 DEVICEID_MSB DEVICEID RW-0x00 RW-0x00 LEGEND: R = Read only; - n = value after reset 15-0 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset Table 123. Port-Write Target Device ID CSR (PW_TGT_ID)[...]

www.ti.com 5.94 Port Error Detect CSR n (SP n_ERR_DET) SRIO Registers Each of the four ports is supported by a register of this type. Figure 150. Port Error Detect CSR n (SP n _ERR_DET) 31 30-24 23 22 21 20 19 18 17 16 ERR_I Reserved Invalid CORR CNTL_ RCVD PKT_ RCVD RCVD Reserv MP_S UPT_ SYM_ _PKT_ UNEX _PKT_ _PKT_ ed PECIF CNTL_ UNEX NOT_ PECT WI[...]

www.ti.com 5.95 Port Error Rate Enable CSR n (SP n_RATE_EN) SRIO Registers Each of the four ports is supported by a register of this type. Figure 151. Port Error Rate Enable CSR n (SP n _RATE_EN) 31 30-24 23 22 21 20 19 18 17 16 EN_IM Reserved Reserv CORRU CNTL_S RCVED_ PKT_U RCVED RCVED Reserv P_SPE ed PT_CNT YM_UN PKT_NO NEXPE _PKT_ _PKT_ ed CIFI[...]

www.ti.com 5.96 Port n Attributes Error Capture CSR 0 (SP n_ERR_ATTR_CAPT_DBG0) SRIO Registers Each of the four ports is supported by a register of this type. Figure 152. Port n Attributes Error Capture CSR 0 (SP n _ERR_ATTR_CAPT_DBG0) 31-30 29 28-24 23-16 INFO_TYPE Reserv ERROR_TYPE IMP_SPECIFIC ed R-0x00 R- R-0x00 R-0x00 0x00 LEGEND: R = Read onl[...]

www.ti.com 5.97 Port n Packet/Control Symbol Error Capture CSR 1 (SP n_ERR_CAPT_DBG1) SRIO Registers Each of the four ports is supported by a register of this type. Figure 153. Port n Packet/Control Symbol Error Capture CSR 1 (SP n _ERR_CAPT_DBG1) 31-16 CAPTURE0 R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 CAPTURE0 R-0x00 LEGEND: R = [...]

www.ti.com 5.98 Port n Packet/Control Symbol Error Capture CSR 2 (SP n_ERR_CAPT_DBG2) SRIO Registers Each of the four ports is supported by a register of this type. Figure 154. Port n Packet/Control Symbol Error Capture CSR 2 (SP n _ERR_CAPT_DBG2) 31-16 CAPTURE1 R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 CAPTURE1 R-0x00 LEGEND: R = [...]

www.ti.com 5.99 Port n Packet/Control Symbol Error Capture CSR 3 (SP n_ERR_CAPT_DBG3) SRIO Registers Each of the four ports is supported by a register of this type. Figure 155. Port n Packet/Control Symbol Error Capture CSR 3 (SP n _ERR_CAPT_DBG3) 31-16 CAPTURE2 R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 CAPTURE2 R-0x00 LEGEND: R = [...]

www.ti.com 5.100 Port n Packet/Control Symbol Error Capture CSR 4 (SP n_ERR_CAPT_DBG4) SRIO Registers Each of the four ports is supported by a register of this type. Figure 156. Port n Packet/Control Symbol Error Capture CSR 4 (SP n _ERR_CAPT_DBG4) 31-16 CAPTURE3 R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 CAPTURE3 R-0x00 LEGEND: R =[...]

www.ti.com 5.101 Port Error Rate CSR n (SP n_ERR_RATE) SRIO Registers Each of the four ports is supported by a register of this type. Figure 157. Port Error Rate CSR n (SP n _ERR_RATE) 31-24 23-18 17-16 ERROR_RATE_BIAS Reserved ERROR_RATE _RECOVERY RW-0xFF R-0x00 RW-0x00 LEGEND: R = Read only; - n = value after reset 15-8 7-0 PEAK_ERROR_RATE ERROR_[...]

www.ti.com 5.102 Port Error Rate Threshold CSR n (SP n_ERR_THRESH) SRIO Registers Each of the four ports is supported by a register of this type. Figure 158. Port Error Rate Threshold CSR n (SP n _ERR_THRESH) 31-24 23-16 ERROR_RATE_FAILED_THRESHOLD ERROR_RATE_DEGRADED_THRES RW-0xFF RW-0xFF LEGEND: R = Read only; - n = value after reset 15-0 Reserve[...]

www.ti.com 5.103 Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) SRIO Registers Figure 159. Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) 31-28 27-24 23-20 19-16 DISCOVERY_TIMER Reserved PW_TIMER Reserved RW-0x09 R-0x00 RW-0x08 R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 Reserved R-0x00 LEGEND: R = Read only; [...]

www.ti.com 5.104 Port IP Mode CSR (SP_IP_MODE) SRIO Registers Figure 160. Port IP Mode CSR (SP_IP_MODE) 31-30 29 28 27 26 25 24-16 SP_MODE IDLE_ TX_FI PW_DI TGT_I SELF_ Reserved ERR_ FO_B S D_DIS RST DIS YPAS S R-0x00 RW- RW- RW- R- RW- R-0x00 0x00 0x00 0x00 0x00 0x00 LEGEND: R = Read only; - n = value after reset 15-6 5 4 3 2 1 0 Reserved MLTC MLT[...]

www.ti.com SRIO Registers Table 134. Port IP Mode CSR (SP_IP_MODE) Field Descriptions (continued) Bit Field Value Description 3 RST_EN Reset Interrupt Enable. If enabled, the interrupt signal is High when the 4 reset control symbols are received in a sequence 0b Reset interrupt disable 1b Reset interrupt enable 2 RST_CS Reset received status bit. I[...]

www.ti.com 5.105 Serial Port IP Prescalar (IP_PRESCAL) SRIO Registers Figure 161. Serial Port IP Prescalar (IP_PRESCAL) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-8 7-0 Reserved PRESCALE R-0x00 RW-0x0F LEGEND: R = Read only; - n = value after reset Table 135. Serial Port IP Prescalar (IP_PRESCAL) Field Descriptions Bit [...]

www.ti.com 5.106 Port-Write-In Capture CSR n (SP_IP_PW_IN_CAPT n) SRIO Registers Each of the four ports is supported by a register of this type. Figure 162. Port-Write-In Capture CSR n (SP_IP_PW_IN_CAPT n ) 31-16 PW_CAPT n R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 PW_CAPT n R-0x00 LEGEND: R = Read only; - n = value after reset Tabl[...]

www.ti.com 5.107 Port Reset Option CSR n (SP n_RST_OPT) SRIO Registers Each of the four ports is supported by a register of this type. Figure 163. Port Reset Option CSR n (SP n _RST_OPT) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-8 7-0 Reserved PORT_ID R-0x00 R-Undefined LEGEND: R = Read only; - n = value after reset Ta[...]

www.ti.com 5.108 Port Control Independent Register n (SP n_CTL_INDEP) SRIO Registers Each of the four ports is supported by a register of this type. Figure 164. Port Control Independent Register n (SP n _CTL_INDEP) 31 30 29 28-27 26 25-24 23 22 21 20 19-18 17 16 Reserv TX_FL SOFT Reserved FORC TRANS_MODE DEBU SEND ILL_T ILL_T Reserved MAX_ MAX_ ed [...]

www.ti.com SRIO Registers Table 138. Port Control Independent Register n (SP n _CTL_INDEP) Field Descriptions (continued) Bit Field Value Description 17 MAX_RETRY_EN Max_retry_error report enable. If enabled, the Port-Write and interrupt are reported as errors. 1b Max retry error report enable 0b Max retry error report disable 16 MAX_RETRY_ER Max_r[...]

www.ti.com 5.109 Port Silence Timer n (SP n_SILENCE_TIMER) SRIO Registers Each of the four ports is supported by a register of this type. Figure 165. Port Silence Timer n (SP n _SILENCE_TIMER) 31-28 27-16 SILENCE_TIMER Reserved RW-0x0B R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 Reserved R-0x00 LEGEND: R = Read only; - n = value afte[...]

www.ti.com 5.110 Port Multicast-Event Control Symbol Request Register n (SP n_MULT_EVNT_CS) SRIO Registers Each of the four ports is supported by a register of this type. Figure 166. Port Multicast-Event Control Symbol Request Register n (SP n _MULT_EVNT_CS) 31-16 MULT_EVNT_CS W-0x00 LEGEND: R = Read only; - n = value after reset 15-0 MULT_EVNT_CS [...]

www.ti.com 5.111 Port Control Symbol Transmit n (SP n_CS_TX) SRIO Registers Each of the four ports is supported by a register of this type. Figure 167. Port Control Symbol Transmit n (SP n _CS_TX) 31-29 28-24 23-19 18-16 STYPE_0 PAR_0 PAR_1 STYPE_1 RW-0x00 RW-0x00 RW-0x00 RW-0x00 LEGEND: R = Read only; - n = value after reset 15-13 12 11-0 CMD CS_E[...]

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