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Vodafone SS 08 manual

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  • Page 1

    Vodafone Chair Mobile Co mmunications Systems, Pr of. Dr.-Ing. G. Fettweis chair Digital Signal Transmission Lab SS 08 Oliver Arnold Steffen Kunze[...]

  • Page 2

    TU Dresden, 4/29/2008 Slide 2 chair Introduction  Hardware  Why to use digital signal processing?  General introduction to DSPs  The TMS320C6711 DSP  Architecture Overview  Peripherals  DSK6711 evaluation board - Software  Code Composer Studio  DSP/BIOS  Multi-channel Buffered Serial Port (McBSP)[...]

  • Page 3

    TU Dresden, 4/29/2008 Slide 3 chair Hardware[...]

  • Page 4

    TU Dresden, 4/29/2008 Slide 4 chair Digital Signal Processing (DSP) Consumer Audio  Stereo A/D, D/A  PLL  Mixers Multimedia  Stereo audio  Imaging  Graphics palette  Voltage regulation Wireless / Cellular  Voice-band audio  RF codecs  Voltage regulation HDD  PRML read channel  MR pre-amp  Servo control  SCS[...]

  • Page 5

    TU Dresden, 4/29/2008 Slide 5 chair System Considerations Performance Performance Interfacing Interfacing Power Power Size Size Ease Ease - - of Use of Use • • Programming Programming • • Interfacing Interfacing • • Debugging Debugging Integration Integration • • Memory Memory • • Peripherals Peripherals Cost Cost • • Device[...]

  • Page 6

    TU Dresden, 4/29/2008 Slide 6 chair Why Go Digital?  Digital signal processing techniques are now so powerful that sometimes it is extremely difficult, if not impossible, for analogue signal processing to achieve similar performance.  Examples :  FIR filter with linear phase  Adaptive filters[...]

  • Page 7

    TU Dresden, 4/29/2008 Slide 7 chair Why Go Digital?  Analogue signal processing is achieved by using analogue components such as:  Resistors  Capacitors  Inductors  The inherent tolerances associated with these components, temperature, voltage changes and mechanical vibrations can dramatically affect the effectiveness of the analogue[...]

  • Page 8

    TU Dresden, 4/29/2008 Slide 8 chair Why Go Digital?  With DSP? - It is easy to:  Change applications  Correct applications  Update applications  Additionally DSPs reduce:  Noise susceptibility  Chip count  Development time  Cost  Power consumption[...]

  • Page 9

    TU Dresden, 4/29/2008 Slide 9 chair General Introduction to DSPs[...]

  • Page 10

    TU Dresden, 4/29/2008 Slide 10 chair What Problem Are We Trying To Solve? Digital sampling of an analog signal: A t Most DSP algorithms can be expressed as: count i = 1 Y = Σ a i * x i for (i = 1; i < count; i++){ sum += m[i] * n[i]; } DAC xY ADC DSP[...]

  • Page 11

    TU Dresden, 4/29/2008 Slide 11 chair What are the typical DSP algorithms?  The Sum of Products (SOP) is the key element in most DSP algorithms: 0 () ( ) M k k yn a xn k = = − ∑ ∑ ∑ = = − + − = N k k M k k k n y b k n x a n y 1 0 ) ( ) ( ) ( ∑ = − = N k k n h k x n y 0 ) ( ) ( ) ( ∑ − = − = 1 0 ] ) / 2 ( exp[ ) ( ) ( N n nk [...]

  • Page 12

    TU Dresden, 4/29/2008 Slide 12 chair  Use a DSP processor when the following are required:  Cost saving  Smaller size  Low power consumption  Processing of many “high” frequency signals in real-time  Use a GPP processor when the following are required:  Large memory  Advanced operating systems Why do we need DSP processo[...]

  • Page 13

    TU Dresden, 4/29/2008 Slide 13 chair Hardware vs. Microcode multiplication  DSP processors are optimized to perform multiplication and addition operations.  Multiplication and addition are done in hardware and in one cycle.  Example: 4-bit multiply (unsigned). 1011 1011 x 1110 x 1110 1011 1011 x 1110 x 1110 Hardware Hardware Microcode Micr[...]

  • Page 14

    TU Dresden, 4/29/2008 Slide 14 chair General Purpose DSP vs. DSP in ASIC  Application Specific Integrated Circuits ( ASIC s) are semiconductors designed for dedicated functions .  The advantages and disadvantages of using ASIC s are listed below: Advantages Advantages • • High throughput High throughput • • Lower silicon area Lower si[...]

  • Page 15

    TU Dresden, 4/29/2008 Slide 15 chair Floating vs. Fixed point processors  Applications which require:  High precision  Wide dynamic range  High signal-to-noise ratio  Ease of use Î Need a floating point processor  Drawback of floating point processors:  Higher power consumption  Usually higher cost  Usually slower than f[...]

  • Page 16

    TU Dresden, 4/29/2008 Slide 16 chair TMS320C6711 Architectural Overview[...]

  • Page 17

    TU Dresden, 4/29/2008 Slide 17 chair General DSP System Block Diagram P E R I P H E R A L S Central Processing Unit Internal Memory Internal Buses External Memory[...]

  • Page 18

    TU Dresden, 4/29/2008 Slide 18 chair ‘6711 CPU Overview  Specification  Clock Rate: 100/150 MHz Î 600/900 MFLOPS  0.18- μ m/5-Level Metal Process – CMOS Technology  CPU has got two Datapaths , altogether:  Four ALUs (Floating- and Fixed-Point)  Two ALUs (Fixed-Point)  Two Multipliers (Floating- and Fixed-Point)  Load-S[...]

  • Page 19

    TU Dresden, 4/29/2008 Slide 19 chair ‘6711 CPU Overview  VelociTI Î advanced very-long instruction words ( VLIW )  Program Memory Width is 256 Bit  Up to 8 32-Bit instructions c an be executed in parallel/Cycle  16, 32 and 40 bit fixed point operands  32 and 64 bit floating point operands  Instruction parallelism is detected at[...]

  • Page 20

    TU Dresden, 4/29/2008 Slide 20 chair Functional Block and CPU Diagram[...]

  • Page 21

    TU Dresden, 4/29/2008 Slide 21 chair A ‘6711 Datapath  .S & .L  Arithmetic, Logical & Branch functions  .M  Multiply, Rotation, Bit expansion  .D  Data-addressing  Only way to access memory  Cross path[...]

  • Page 22

    TU Dresden, 4/29/2008 Slide 22 chair Functional Units and Operations Performed[...]

  • Page 23

    TU Dresden, 4/29/2008 Slide 23 chair C6700: Instruction Set .L .L .L .D .D .D .S .S .S .M .M .M No Unit Used IDLE IDLE NOP NOP .S Unit .S Unit NEG NEG NOT NOT OR OR SET SET SHL SHL SHR SHR SSHL SSHL SUB SUB SUB2 SUB2 XOR XOR ZERO ZERO ADD ADD ADDK ADDK ADD2 ADD2 AND AND B B CLR CLR EXT EXT MV MV MVC MVC MVK MVK MVKH MVKH ABSSP ABSSP ABSDP ABSDP CMP[...]

  • Page 24

    TU Dresden, 4/29/2008 Slide 24 chair 'C6x System Block Diagram Internal Buses Internal Buses CPU CPU .D1 .D1 .M1 .M1 .L1 .L1 .S1 .S1 .D2 .D2 .M2 .M2 .L2 .L2 .S2 .S2 Regs (B0 Regs (B0 - - B15) B15) Regs (A0 Regs (A0 - - A15) A15) Control Regs Control Regs EMIF EMIF Ext Ext ’ ’ l l Memory Memory - - Sync Sync - - Async Async Program Program [...]

  • Page 25

    TU Dresden, 4/29/2008 Slide 25 chair ‘C6000 Internal Buses PC Program Addr x32 Program Data x256 DMA DMA Addr - Read x32 DMA Data - Read x32 DMA Addr - Write x32 DMA Data - Write x32 A regs B regs Data Addr - T1 x32 Data Data - T1 x32/64 Data Addr - T2 x32 Data Data - T2 x32/64 Internal Memory External Memory Peripherals[...]

  • Page 26

    TU Dresden, 4/29/2008 Slide 26 chair How are Peripherals Controlled?  Control and configuration of internal peripherals is done by memory mapped control registers  There is a separate memory mapped register file of control registers Example of Timer mode control register: C/P Func INVOUT DATOUT DATIN PWID Rsvd GO HLD CLKSRC INVIMP TSAT Rsvd 0[...]

  • Page 27

    TU Dresden, 4/29/2008 Slide 27 chair ‘C6711 Memory Map Byte Address FFFF_FFFF 0000_0000 64K x 8 Internal (L2 cache) Internal Memory  Unified (data or prog)  4 blocks - each can be RAM or cache On-chip Peripherals 0180_0000 External Memory  Async (SRAM, ROM, etc.)  Sync (SBSRAM, SDRAM) 256M x 8 External 2 256M x 8 External 3 8000_0000 [...]

  • Page 28

    TU Dresden, 4/29/2008 Slide 28 chair Memory Map FFFF_FFFF 0000_0000 64KB Internal (Progam or Data) On-chip Periph 0180_0000 256MB External 256MB External 8000_0000 9000_0000 A000_0000 B000_0000 256MB External 256MB External 9008_0000 Available via Daughter Card Connector 16MB SDRAM 128K byte FLASH 4 byte I/O Port  LED’s  Switches  DSK st[...]

  • Page 29

    TU Dresden, 4/29/2008 Slide 29 chair Operands  Operands can be  5-bit constants (or 16-bit in some special instruct.)  32-bit Registers  40-bit Registers  64-bit Registers  A 40-bit or a 64-bit register can be obtained by concatenating two registers  The registers must be from the same side  The first register must be even a[...]

  • Page 30

    TU Dresden, 4/29/2008 Slide 30 chair Conditional execution  All instructions in each Functional Unit of both Data paths can be executed conditionally  Only the Registers A1, A2, B0, B1, B2 can hold the condition  Conditional Execution uses the Syntax [!condition] Instruction e.g [!B0] ADD.L1 A1,A2,A3 ; add if B0 ==0 [B0] ADD.L1 A1,A2,A3 ; [...]

  • Page 31

    TU Dresden, 4/29/2008 Slide 31 chair Branches  Branches are required to realize loops and change the program flow  Branches are very useful in conjunction with conditional execution  There are two branch types supported:  Relative Branching  Absolute Branching[...]

  • Page 32

    TU Dresden, 4/29/2008 Slide 32 chair  Case 1: B .S1 label  Relative branch.  Label limited to +/- 2 20 offset . More on the Branch Instruction (1)  With this processor all the instructions are encoded in a 32-bit.  Therefore the label must have a dynamic range of less than 32-bit as the instruction B has to be coded. 21 21 - - bit re[...]

  • Page 33

    TU Dresden, 4/29/2008 Slide 33 chair More on the Branch Instruction (2)  By specifying a register as an operand instead of a label, it is possible to have an absolute branch.  This will allow a dynamic range of 2 32 .   Case 2: Case 2: B .S B .S 2 2 register register   Absolute branch. Absolute branch.   Operates on .S2 ONLY[...]

  • Page 34

    TU Dresden, 4/29/2008 Slide 34 chair Getting Data from the Memory  All Instructions work exclusively on Registers  The .D Units in the Data-Paths are used to load and store the required Data from and to the Memory  Load and Store Instructions use an Address operator X:[...]

  • Page 35

    TU Dresden, 4/29/2008 Slide 35 chair Addressing Modes  There are two addressing modes supported:  Linear Addressing  Circular Addressing (e.g. Convolution)  Circular Addressing supports block sizes 2 N  Only the lower N bits of the Address are modified by address arithmetic. This equals mod(2 N ) operations.  The addressing mode i[...]

  • Page 36

    TU Dresden, 4/29/2008 Slide 36 chair Floating vs. Fixed point processors  Fixed point arithmetic  16-bit (integer or fractional)  Signed or unsigned  Floating point arithmetic  32-bit single precision  64-bit single precision  Using signed and unsigned integers:  Multiplication overflow.  Addition overflow Î Saturate the[...]

  • Page 37

    TU Dresden, 4/29/2008 Slide 37 chair C6000 C Data Types Type Type Size Size Representation Representation char, signed char char, signed char 8 bits 8 bits ASCII ASCII unsigned char unsigned char 8 bits 8 bits ASCII ASCII short short 16 bits 16 bits 2 2 ’ ’ s complement s complement unsigned short unsigned short 16 bits 16 bits binary binary in[...]

  • Page 38

    TU Dresden, 4/29/2008 Slide 38 chair Numerical Issues - Useful Tips  Multiply by 2: Use shift left  Divide by 2: Use shift right  Log 2 N: Use shift  Sine, Cosine, Log: Use look up tables  To convert a fractional number to hex:  Num x 2 15  Then convert to hex e.g: convert 0.5 to hex  0.5 x 2 15 = 16384  (16384) dec = (0x[...]

  • Page 39

    TU Dresden, 4/29/2008 Slide 39 chair Numerical Issues - 32-bit Multiplication  It is possible to perform 32-bit multiplication using 16-bit multipliers.  Example: c = a x b (with 32-bit values). a a h h a a l l b b h h b b l l a = a = b = b = 32 32 - - bits bits a * b = (a h << 16 + a l )* (b h << 16 + b l ) = [(a h * b h ) <&l[...]

  • Page 40

    TU Dresden, 4/29/2008 Slide 40 chair Selected ‘6711 Peripherals[...]

  • Page 41

    TU Dresden, 4/29/2008 Slide 41 chair C6000 Peripherals .D1 .D1 .M1 .M1 .L1 .L1 .S1 .S1 .D2 .D2 .M2 .M2 .L2 .L2 .S2 .S2 Regs Regs (B0 (B0 - - B15/31) B15/31) Regs Regs (A0 (A0 - - A15/31) A15/31) CPU CPU External External Memory Memory Internal Buses Internal Buses 16/32 16/32 EMIF EMIF Timer/Count Timer/Count DMA DMA Boot Loader Boot Loader EDMA ED[...]

  • Page 42

    TU Dresden, 4/29/2008 Slide 42 chair The McBSP  Multichannel Buffered Serial Port  Up to 100 Mb/sec performance  2 (or 3) full-duplex, synchronous serial-ports  Enables direct interfacing to industry standard Codecs, Analog interface Chips and other serially connected devices  Supports a wide range of data-sizes , including 8, 12, 16[...]

  • Page 43

    TU Dresden, 4/29/2008 Slide 43 chair PCM3003  MONOLITHIC 20-BIT DS ADC AND DAC  16-/20-BIT INPUT/OUTPUT DATA  HARDWARE CONTROL: PCM3003  STEREO ADC: SNR: 90dB & DynamicRange: 90dB  STEREO DAC: SNR: 94dB & Dynamic Range: 94dB  Digital Attenuation (256 Steps), Soft Mute, Digital Loop Back  SAMPLING RATE: Up to 48kHz  S[...]

  • Page 44

    TU Dresden, 4/29/2008 Slide 44 chair What is the bootloader?  When the DSP is NOT powered or under reset the internal program memory is in a random state. DMA DMA L2 Cache L2 Cache L1P Cache L1P Cache L1D Cache L1D Cache CPU CPU Boot Boot Config Config EMIF EMIF EPROM EPROM C6211/C6711 C6211/C6711 VCC VCC VCC VCC Addr Addr 0000 0000 0001 0001 00[...]

  • Page 45

    TU Dresden, 4/29/2008 Slide 45 chair What is the bootloader?  When the DSP is powered and the CPU is taken out of reset the internal memory is still in a random state and the program will start running for address zero. DMA DMA L2 Cache L2 Cache L1P Cache L1P Cache L1D Cache L1D Cache CPU CPU Boot Boot Config Config EMIF EMIF EPROM EPROM C6211/C[...]

  • Page 46

    TU Dresden, 4/29/2008 Slide 46 chair What is the bootloader?  With the boot, a portion of code can be automatically copied from external to internal memory. DMA DMA L2 Cache L2 Cache L1D Cache L1D Cache CPU CPU Boot Boot Config Config EMIF EMIF EPROM EPROM C6211/C6711 C6211/C6711 VCC VCC VCC VCC L1P Cache L1P Cache[...]

  • Page 47

    TU Dresden, 4/29/2008 Slide 47 chair Interrupts  DSPs must be able to execute tasks on asynchronous events  Interrupts suspend the current processor task and save its context  A interrupt service routine (ISR) is executed  After completion of the ISR, the context of the former task is restored and the execution continues  Interrupts [...]

  • Page 48

    TU Dresden, 4/29/2008 Slide 48 chair Interrupt Interrupt- and Thread Types  HWI priorities set by hardware Î One ISR per interrupt  14 SWI priority levels Î Multiple SWIs at each level  15 TSK priority levels Î Multiple TSKs at each level  Multiple IDL functions Î Continuous loop Î HWI triggered by hardware interrupt Î IDL runs as[...]

  • Page 49

    TU Dresden, 4/29/2008 Slide 49 chair The DSK6711 Development Kit[...]

  • Page 50

    TU Dresden, 4/29/2008 Slide 50 chair DSK Contents Hardware  150 MHz ‘C6711 DSP  TI 16-bit A/D Converter (‘AD535)  External Memory  16M Bytes SDRAM  128K Bytes Flash ROM  LED’s  Daughter card expansion  Power Supply & Parallel Port Cable Software  Code Generation Tools (C Compiler, Assembler & Linker)  Cod[...]

  • Page 51

    TU Dresden, 4/29/2008 Slide 51 chair C6711 DSK Overview 1.8V Power Supply 16M SDRAM 128K FLASH Daughter Card I/F (EMIF Connector) Parallel Port I/F Power Jack Power LED 3.3V Power Supply JTAG Header Emulation JTAG Header Reset Line Level Out p ut ( s p eakers ) Line Level Input (microphone) 16-bit codec (A/D & D/A) Three User LEDs User DIP swit[...]

  • Page 52

    TU Dresden, 4/29/2008 Slide 52 chair Software: (4) PC Æ DSK Communications DSP DSP JTAG JTAG ....... ....... ....... ....... JTAG JTAG Emulation Emulation Port Port CCS uses parallel port to control DSP via JTAG port CCS uses parallel port to control DSP via JTAG port You can use full TI eXtended D ev System (XDS) via 14 pin You can use full TI eX[...]

  • Page 53

    TU Dresden, 4/29/2008 Slide 53 chair What happens to the Source-Code?[...]