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Xilinx DS610 manual

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Table of contents for the manual

  • Page 1

    DS610 J uly 16, 20 07 www .xil inx.com 1 Pr oduct Specific ation © 2007 Xilinx, Inc. All ri ghts reser ved. All Xilinx trademarks, registe red trademarks, paten ts, and disclaimers are as listed a t h ttp://www.xilinx.com/legal.htm . All ot her tradem ark s are th e pro per ty of th eir re spective owners. All specifica tion s are subj ect to chan[...]

  • Page 2

    Data Sheet 2 www .xilinx. com DS610 J uly 16, 2007 Produ ct Specificati on R This page intentionally left b lank.[...]

  • Page 3

    DS610-1 (v2.0) July 16, 2007 www .xil inx.com 3 Pr oduct Specific ation © 2007 Xilinx, Inc. All ri ghts reser ved. All Xilinx trademarks, registe red trademarks, paten ts, and disclaimers are as listed a t h ttp://www.xilinx.com/legal.htm . All ot her tradem ark s are th e pro per ty of th eir re spective owners. All specifica tion s are subj ect [...]

  • Page 4

    Intr oduction and Ordering Inf ormation 4 www .xilinx. com DS610-1 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Ar chitectural Ov er view The S par tan-3A DSP f a mily ar chitectu re cons ists of five fundamenta l pro grammable functional elemen ts: • XtremeDSP DSP48A Slice provides an 18-bit x 18-bit multiplier , 18-bit pre-add er , 48 -bit [...]

  • Page 5

    Intr oduction and Ordering Inf ormation DS610-1 (v2.0) July 16, 2007 www .xil inx.com 5 Pr oduct Specific ation R Figure 1 : Spar tan-3A DS P Family Ar chitecture CLB Block RAM DCM IOBs IOBs DS610-1_01_031207 IOBs IOBs DCM Block RAM / DSP48A Slice DCM CLBs IOBs DSP48A Slice Notes: 1 . The XC3SD18 00A and XC3 SD3400 A have two DCMs on both th e left[...]

  • Page 6

    Intr oduction and Ordering Inf ormation 6 www .xilinx. com DS610-1 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Pa c k a g e M a r k i n g Figure 2 shows the to p mar king f or Sp ar tan -3A D SP FPGAs. Use the sev e n digits of t he Lot Co de to ac cess additiona l infor matio n for a speci fic d e v ice us ing the Xili nx we b-based G enealog[...]

  • Page 7

    Intr oduction and Ordering Inf ormation DS610-1 (v2.0) July 16, 2007 www .xil inx.com 7 Pr oduct Specific ation R Revi sion H istory The f ollo wing tab le sho ws the re vi sion hi stor y f or this docum ent. Date V ers ion Revision 04/02/07 1.0 Initial Xili nx release. 05/25/ 07 1.0.1 Minor ed its. 06/18/ 07 1.2 Update d f or Production rele ase. [...]

  • Page 8

    Intr oduction and Ordering Inf ormation 8 www .xilinx. com DS610-1 (v 2.0) J uly 16, 2007 Produ ct Specificati on R This page intentionally left b lank.[...]

  • Page 9

    DS610-2 (v2.0) July 16, 2007 www .xil inx.com 9 Pr oduct Specific ation © 2007 Xilinx, Inc. All ri ghts reser ved. All Xilinx trademarks, registe red trademarks, paten ts, and disclaimers are as listed a t h ttp://www.xilinx.com/legal.htm . All ot her tradem ark s are th e pro per ty of th eir re spective owners. All specifica tion s are subj ect [...]

  • Page 10

    Functional Description 10 www .xilinx. com DS610-2 (v 2.0) J uly 16, 2007 Produ ct Specificati on R This page intentionally left b lank.[...]

  • Page 11

    DS610-3 (v2.0) July 16, 2007 www .xil inx.com 11 Pr oduct Specific ation © 2007 Xilinx, Inc. All ri ghts reser ved. All Xilinx trademarks, registe red trademarks, paten ts, and disclaimers are as listed a t h ttp://www.xilinx.com/legal.htm . All ot her tradem ark s are th e pro per ty of th eir re spective owners. All specifica tion s are subj ect[...]

  • Page 12

    DC and Switching Characteristics 12 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R P ower S upply Specifica tions General Recomm ended Operating Conditions T able 4: Supply V oltage Thresholds for P ower -On Reset Symbol Description Min Max Units V CCINTT Threshold f or the V CCINT supply 0.4 1.0 V V CCAU XT Threshol d fo[...]

  • Page 13

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 13 Pr oduct Specific ation R General DC Characteristic s for I/O Pins T able 8: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins Symbol Description T est Conditions Min T yp Max Units I L Leakage current at User I/O , Inpu t-o nly , Dual- Pur pos[...]

  • Page 14

    DC and Switching Characteristics 14 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Quiescent Curr ent Requiremen ts T able 9: Quiescent Suppl y Current Characteristics Symb ol Desc rip tio n Device Po w er T y pi cal (2) Commer cial Maxim um (2) Industrial Maxim um (2) Units I CCINTQ Qu iescen t V CCI NT supply current XC[...]

  • Page 15

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 15 Pr oduct Specific ation R Single-Ended I/O Stand ards T able 10: Recommended Operating Conditions for User I/Os Using Single-Ended Standar ds IOST A ND ARD Attribute V CCO for Driver s (2) V REF V IL V IH Min (V) Nom (V) Max (V) Min (V) N om (V) Max (V) Max (V) Min ([...]

  • Page 16

    DC and Switching Characteristics 16 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R T able 11: DC Characteristic s of User I/Os Using Single-Ended St andards IOST ANDARD Attribute Te s t Conditions Logic Le vel Character istics I OL (mA) I OH (mA) V OL Max (V) V OH Min (V) L VTTL (3) 22 – 2 0 . 4 2 . 4 44 – 4 66 – 6 [...]

  • Page 17

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 17 Pr oduct Specific ation R Differen tial I/O Standards Figure 3 : Differential Input V olt ages T able 12: Reco mmende d Ope ratin g Con ditions f or U ser I/Os Using Di ffer ent ial S ignal St andar ds IOST AN D ARD Attribute V CCO for Dr ive rs (1) V ID V ICM (2) Mi[...]

  • Page 18

    DC and Switching Characteristics 18 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Figure 4: Diff erential Output V oltages T able 13: DC Characteristics of User I/Os Using D ifferential Signal Standar ds IOST ANDARD Attribute V OD V OC M V OH V OL Min (mV) T yp (mV) Max (mV) Min (V) T yp (V) Max (V) Min (V) Max (V) L VDS[...]

  • Page 19

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 19 Pr oduct Specific ation R External T ermination Requirements f or Differential I/O L VDS , RSDS, MINI_L VDS, and P PDS I/O Standards BL VDS _25 I/O S tandard TMDS_33 I/O Standard Device DNA Data Retention, Read Endurance Figu re 5: External Input T erminatio n for L [...]

  • Page 20

    DC and Switching Characteristics 20 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Switc hing Characteristics All Spa r tan- 3A DSP FPGAs s hip in two s peed grades: – 4 and the hig her pe rformanc e –5. Sw itching c haracter isti cs in this docume nt are designa ted as Preview , A dvance, Prelim inar y , or Productio[...]

  • Page 21

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 21 Pr oduct Specific ation R T o c reate a X ilinx M ySuppor t use r acco unt and sign up for automa tic E-m ail notif ication w henev er this data shee t is updated: • Sign Up for Ale rts on Xilinx MySupport www .xilinx.com / xlnx/xil_an s_disp lay .jsp?g etPageP at [...]

  • Page 22

    DC and Switching Characteristics 22 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R I/O Timing T able 17: Pin-to-Pi n Clock -to-Output Times for the IOB Output P ath Symbol Descriptio n Con ditions Device Speed Gra de Units -5 -4 Max Max Cloc k-to-Outpu t Times T ICKO F DCM When rea d ing f rom the O utput Flip-Flo p (OFF)[...]

  • Page 23

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 23 Pr oduct Specific ation R T able 18: Pin-to-Pin Setup a nd Hold Times for the IOB Input Pa th (System Sync hronous) Symbol Descr iption Conditions Device Speed Grade Units -5 -4 Min Min Setup Times T PSDCM When w riting to th e Input Flip-Flo p (IFF), the time fro m [...]

  • Page 24

    DC and Switching Characteristics 24 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R T able 19: Setup and Hold Times for the IOB Input Path Symbol Descr iption Conditions IFD_DELA Y_ VA L U E Device Speed Grade Units -5 -4 Min Min Setup Ti mes T IOPI CK Time f rom the setup of data at the Input pin to the activ e tran sitio[...]

  • Page 25

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 25 Pr oduct Specific ation R T able 20: Propa gation Times for the IOB Input P ath Symbol Descrip tion Conditions IFD_De lay_V alue De vice Speed Grade Uni ts -5 -4 Max Max Propaga tion Tim es T IOPLI The time it tak es for da ta to tra vel from th e Input pin through t[...]

  • Page 26

    DC and Switching Characteristics 26 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R T able 21: Input Timin g Adjustments by IOST AND ARD Con vert Input Time fr om L VCMOS25 to the Follow ing Signal S tandar d (IOST AND ARD) Add the Adjustment Be low Units Speed Grade -5 -4 Single- Ended Standar ds L VTTL 0.62 0.62 ns L VCM[...]

  • Page 27

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 27 Pr oduct Specific ation R T able 22: Timing for the IOB Output P ath Symbol Description Con d itions De vice Speed Grade Uni ts -5 -4 Max Max Cloc k-to-Outpu t Times T IOCKP Whe n reading from th e Output Flip-Flop (OFF), the time fro m the activ e transitio n at the[...]

  • Page 28

    DC and Switching Characteristics 28 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R T able 24: Output Tim ing Adjustmen ts for IOB Con vert Output Time from L VCMOS25 with 12m A Drive and Fast Slew Rate to the F ollowing Signal Standar d (IOST AND ARD) Add th e Adjustment Below Units Speed G r ade -5 -4 Sing le -E nde d S [...]

  • Page 29

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 29 Pr oduct Specific ation R LV C M O S 2 5 Slow 2 mA 5. 33 5.33 ns 4 mA 2.81 2.81 ns 6 mA 2.82 2.82 ns 8 mA 1.14 1.14 ns 12 mA 1.10 1.10 ns 16 mA 0.83 0.83 ns 24 mA 2.26 2.26 ns F ast 2 mA 4.36 4.36 ns 4 mA 1.76 1.76 ns 6 mA 1.25 1.25 ns 8 mA 0.38 0.38 ns 12 mA 0.00 0.[...]

  • Page 30

    DC and Switching Characteristics 30 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Differe ntial Standard s L VDS_25 1.16 1 .16 ns L VDS_33 0.46 0 .46 ns BL VDS_25 0.11 0 .11 ns MINI_L VDS_25 0.75 0.75 ns MINI_L VDS_33 0.40 0.40 ns L VPECL_25 Inputs O nly L VPECL_33 RSDS_25 1.42 1 .42 ns RSDS_33 0.58 0 .58 ns TMDS_33 0 .4[...]

  • Page 31

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 31 Pr oduct Specific ation R Timing Measu rement Methodolog y When meas uri ng tim ing pa rameters at th e programmable I/Os, different signal stand ards ca ll for diff e rent te st conditio ns. Ta b l e 2 5 lis ts the c onditions to use for each standa rd. The meth od [...]

  • Page 32

    DC and Switching Characteristics 32 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R The cap acitive load (C L ) is connec ted be tween the ou tput and GND . The Ou tput tim ing for all standa rds, as published in the spe ed file s and th e data s heet, is a lwa ys base d on a C L val u e o f ze ro. High-imp edance pr obes [...]

  • Page 33

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 33 Pr oduct Specific ation R Using IBIS Mode ls to Sim u late Load Cond itions in Application IBIS mode ls pe rm it the m ost ac curate pred ictio n of tim ing delays f or a gi ven applicatio n. The parame ters found in the IBIS m odel (V REF , R RE F , and V MEA S ) co[...]

  • Page 34

    DC and Switching Characteristics 34 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R T able 27: Recommended Number of Simult a neously Switchin g Outputs per V CCO -GND P air (V CCAUX =3 .3V) Signal Standar d (IOST ANDARD) Pa c k a g e Ty p e CS48 4, FG 676 T op , Bottom (Ba nks 0, 2) Left, Right (Banks 1,3) Single-Ende d S[...]

  • Page 35

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 35 Pr oduct Specific ation R L VCM OS15 Slow 2 55 55 4 31 31 6 18 18 8 –1 5 12 –1 0 Fa s t 2 25 25 4 10 10 6 66 8 –4 12 –3 QuietIO 2 70 70 4 40 40 6 31 31 8 –3 1 12 –2 0 L VCM OS12 Slow 2 40 40 4 –2 5 6 –1 8 Fa s t 2 31 31 4 –1 3 6 –9 QuietIO 2 55 55[...]

  • Page 36

    DC and Switching Characteristics 36 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Configurab le Logic Bloc k (CLB) Timing T able 28: CLB (SLICEM) Timing Symbol D escription Speed Grade Units -5 -4 Min Max Min Max Cloc k-to-Outpu t Times T CK O When reading from the FFX (FF Y) Flip-Flo p , the time from the a c tiv e tran[...]

  • Page 37

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 37 Pr oduct Specific ation R Cloc k Buffer/Multipl ex er Switching Charact eristics T able 29: CLB Distributed RAM Switching Characteristics Symbol Des cription Speed Grade Units -5 -4 Min Max Min Max Cloc k-to-Outpu t Times T SHCK O Time from the activ e edge at the C [...]

  • Page 38

    DC and Switching Characteristics 38 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Bloc k RAM Timing T able 32: Block RAM Timing Symbol Description Speed Grade Units -5 -4 Min Max Min M ax Cloc k-to-Outpu t Times T RCK O _DOA_NC When reading f rom bloc k RAM, the d elay from the ac tive tra nsition at the CL K input to d [...]

  • Page 39

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 39 Pr oduct Specific ation R DSP48A Timing T o reference the DSP48A block diagram, see th e XtremeDSP DSP48A f or Spar tan-3 A DSP FPGA User Guide ( UG431 ). T able 33: Setup Times f or the DSP48A Symbol Description Preadder Multiplier P ostadder Speed G rade Units -5 -[...]

  • Page 40

    DC and Switching Characteristics 40 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R T able 34: Clock to Out , Propa gation Delays, and Maximum Frequenc y for the DSP48A Symbol Description Preadder Multiplier P ostadder Speed G rade Units -5 -4 Max Max Cloc k to Out from O utput Regis ter Cloc k to Ou tput Pin T DSPCK O _PP[...]

  • Page 41

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 41 Pr oduct Specific ation R Digital C lock Mana ger (DCM) Timing F or spe cificat ion pur poses, the DCM cons ists of th ree key componen ts: the Delay-Lock e d Loop (DLL), th e Digit al F requ ency Sy nthes izer (DFS), an d the P hase Shi fter (PS ). Aspects of DLL op[...]

  • Page 42

    DC and Switching Characteristics 42 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R T able 36: Switching Charact eristics for the DL L Symbol Description Device Speed Grade Units -5 -4 Min Max Min M ax Output Frequency Ranges CLK OUT_FRE Q_CLK0 F r equency for the CLK0 and CLK 180 outputs All 5 280 5 250 MHz CLK OUT_FRE Q_[...]

  • Page 43

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 43 Pr oduct Specific ation R Digital Frequency Synthesizer (D FS) T able 37: Recommended Operating Conditions for the DFS Symbol Des c ription Speed G r ade Units -5 -4 Min Max Mi n Max Input Frequency Ran ges (2) F CLKIN CLKIN_FREQ_ FX F requ ency for the CLKIN inpu t [...]

  • Page 44

    DC and Switching Characteristics 44 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Phase Shift er (PS) Miscellaneous DCM Timing T able 39: Recommend ed Opera ting Condit ions for the P S in V ariable P hase Mo de Symbol Descripti on Speed Grade Units -5 -4 Min Max Min Max Operating Frequ ency Ranges PSCLK_FREQ (F PSCLK ) [...]

  • Page 45

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 45 Pr oduct Specific ation R DNA P or t Timing T able 42: DNA_PORT Interface Timing Symbol Description Min Max Units T DNASSU Setup time on SHIFT bef ore the rising edge of C LK 1 .0 –n s T DNASH Hold time o n SHIFT after the rising edge o f CLK 0.5 –n s T DNADSU Se[...]

  • Page 46

    DC and Switching Characteristics 46 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Suspend M ode Timin g Figure 9: Suspend Mode Timing DS610-3_08_061207 Bl o cke d t SUSPEND_DISABLE t SUSPEND_GWE t SUSPENDHIGH_AWAKE t AWAKE_GWE t AWAKE_GTS t SUSPEND_GTS SUSPEND Input AWAKE Output Flip-Flops, Block RAM, Distributed RAM FPG[...]

  • Page 47

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 47 Pr oduct Specific ation R Confi gur atio n and JT A G Ti ming General Configurat ion P ower -On/Reconfig ure Timing Figure 10 : W aveforms for P ower-On and t he Beginni ng of Conf iguration T able 44: P ower- On Timing a nd the Beginning of Configuration Symb ol Des[...]

  • Page 48

    DC and Switching Characteristics 48 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Configurati on Cloc k (CCLK) Characterist ics T able 45: Master Mode CCLK Output P eriod by ConfigRate Option Setting Symbol D escription ConfigRate Setting T empera ture Range Minimum Maxim um Units T CCLK1 CCLK cloc k period b y Con figRa[...]

  • Page 49

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 49 Pr oduct Specific ation R T able 46: Master Mode CCLK Output Frequency by ConfigRate Option Setting Symbol D escription ConfigRate Setting T empera ture Range Minimum Maxim um Units F CCLK1 Equiv alent CCLK c lock fre quency by ConfigRate setting 1 (pow er-on v alue)[...]

  • Page 50

    DC and Switching Characteristics 50 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Master Serial and Sla ve Serial Mode Timing Figure 11: W aveforms for Master Seria l and Sl ave Serial Co nfigurat ion T able 49: Timing for the Master Serial and Sla v e Serial Configuration Mo des Symbol Descripti on Slave / Maste r All S[...]

  • Page 51

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 51 Pr oduct Specific ation R Slave P arallel Mode Timing Figure 12: W aveforms for Slave Parallel Con figurat ion T able 50: Timing for the Slave P a rallel Configuration Mode Symbol Description All Spee d Grades Units Min Max Setu p Ti mes T SMD CC (2) The time from th[...]

  • Page 52

    DC and Switching Characteristics 52 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Serial P eripheral Interf ace (SPI) Configurat ion Timing Figure 1 3: W aveforms f or Serial Peripher a l Interface (SPI) Configuration T able 51: Timing for Serial Pe ripheral Interface (SPI) Conf iguration Mode Symb ol Desc rip tio n Mini[...]

  • Page 53

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 53 Pr oduct Specific ation R T able 52: Configuration Timing Requirements for Atta ched SPI Serial Flash Symbol Description Requirement Units T CCS SPI serial Flash PR OM chip-se lect time ns T DSU SPI serial Fl ash PROM da ta input setup ti me ns T DH SPI serial Fl ash[...]

  • Page 54

    DC and Switching Characteristics 54 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Byte P eripheral Interface (BPI ) Configuration Timing Figure 14: W ave for ms f or Byt e-wi de Pe ripher al In ter face (BPI ) Con fi gura tion T able 53: Timing for Byte-wide P eripheral Interface (BPI) Configuration Mode Symbol Descripti[...]

  • Page 55

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 55 Pr oduct Specific ation R T able 54: Configuration Timing Requirements for Attach e d Pa rallel NOR Flash Symbol Description Requirement Unit s T CE (t ELQV ) P arall el N OR F las h PROM chi p-s ele ct t ime ns T OE (t GLQV ) P arallel NO R Flash PROM output-enab le[...]

  • Page 56

    DC and Switching Characteristics 56 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R IEEE 1149.1/1553 JT A G T est Access P or t Timing Figure 15 : JT AG W aveforms TCK T TMSTCK TMS TDI TDO (Inp u t) (Inp u t) (Inp u t) (O u tp u t) T TCKTMS T TCKTDI T TCKTDO T TDITCK DS099_06_040703 T CCH T CCL 1/F TCK T able 55: Timing fo[...]

  • Page 57

    DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 57 Pr oduct Specific ation R Revi sion H istory The f ollo wing tab le sho ws the re vi sion hi stor y f or this docum ent. Date V ersion Revis ion 04/02/07 1.0 Initial Xili nx release . 05/25/ 07 1.0.1 Minor ed its. 06/18/ 07 1.2 Updated f or v1.29 produ ction speed fi[...]

  • Page 58

    DC and Switching Characteristics 58 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R This page intentionally left b lank.[...]

  • Page 59

    DS610-4 (v2.0) July 16, 2007 www .xil inx.com 59 Pr oduct Specific ation © 2007 Xilinx, Inc. All ri ghts reser ved. All Xilinx trademarks, registe red trademarks, paten ts, and disclaimers are as listed a t h ttp://www.xilinx.com/legal.htm . All ot her tradem ark s are th e pro per ty of th eir re spective owners. All specifica tion s are subj ect[...]

  • Page 60

    Pinout Descriptions 60 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Pa c k a g e P i n s by Typ e Each package has t hree sep arate voltage s uppl y inputs—V CCINT , VCCA UX , and VC CO—and a c ommon ground ret ur n, GND . The numbers of p ins dedi cated to these func tions var y by package, as shown in Ta b l e 5 7[...]

  • Page 61

    Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 61 Pr oduct Specific ation R P ac kage Thermal Characteri stics The power dissi pated by an FPGA applicat ion ha s implic ations on package s elect ion and system desi gn. The power consume d by a Spar tan-3A DSP FPGA is rep or te d using ei ther the XP owe r P o wer Estimator or the[...]

  • Page 62

    Pinout Descriptions 62 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R CS484: 484-Ball Chip-Sca le Ball Grid Array The 484- ball ch ip-s cale ba ll gr id array , C S484, suppor ts both the XC3SD 1800A and XC3 SD3400A F PGAs. Ther e are no pi nout differences be tween the two devices. Ta b l e 6 0 l ists al l the CS48 4 pac[...]

  • Page 63

    Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 63 Pr oduct Specific ation R 0 IO_L1 7N_0/GCL K5 F11 G CLK 0 IP_0 F12 INPUT 0 IO_L1 3N_0 F1 3 I/O 0 IO_L1 3P_0 F14 I/O 0 IO_L0 5N_0 F1 5 I/O 0 IO_L0 4N_0 F1 6 I/O 0 IO_L2 3P_0 G8 I/O 0 VCCO_0 B5 VCCO 0 VCCO_0 B10 VCCO 0 VCCO_0 B14 VCCO 0 VCCO_0 B18 VCCO 0 VCCO_0 E9 VCCO 0 VCCO_0 E14 [...]

  • Page 64

    Pinout Descriptions 64 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R 1 IO_L03N _1/A1 V20 DUAL 1 IP_L08P_1 V22 INPUT 1 IO_L03P_1/A0 W19 D UAL 1 IP_L04N_1/VREF_1 W20 VREF 1 IP_L04P_1 W21 IN PUT 1 IO_L06P_1 W22 I/O 1 IO_L0 2P_1/LDC1 Y21 DU AL 1 IO_L0 6N_1 Y22 I/O 1 VCCO_1 E21 VCCO 1 VCCO_1 J18 VCCO 1 VCCO_1 K21 VCCO 1 VCCO_[...]

  • Page 65

    Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 65 Pr oduct Specific ation R 2 IP_2/VREF_2 Y14 VREF 2 IO_L2 4N_2/D3 Y15 DU AL 2 IO_L2 9N_2 Y16 I/O 2 IO_L29P_2 Y17 I/O 2 IO_L26P_2 /D2 Y18 DUAL 2 IO_L2 6N_2/D1 Y19 DU AL 2 VCC O_2 AA5 VCCO 2 VCC O_2 AA9 VCCO 2 VCC O_2 AA13 VCCO 2 VCC O_2 AA18 VCCO 2 VCCO_2 V9 VCCO 2 VCCO_2 V14 VCCO 3[...]

  • Page 66

    Pinout Descriptions 66 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R 3 IO_L36P_3 V4 I/O 3 IO_L3 5N_3 W1 I/O 3 IO_L3 7N_3 W2 I/O 3 IO_L3 7P_3 W3 I/O 3 IO_L35P_3 Y1 I/O 3 IP_L39P_3 Y2 INPUT 3 VCCO_3 E2 VCCO 3 VCCO_3 J2 VCCO 3 VCCO_3 J5 VCCO 3 VCCO_3 N2 VCCO 3 VCCO_3 P5 VCCO 3 VCCO_3 V2 VCCO GND GND A1 GND GND GND A22 GND G[...]

  • Page 67

    Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 67 Pr oduct Specific ation R GND GND T14 GND GND GND T15 GND GND GND T19 GND GND GND T21 GND GND GND U6 GND GND GND U11 GND GND GND U17 GND GND GND W7 GND GND GND W12 GND GND GND W16 GND GND GND Y3 GND GND GND Y20 GND VCCA UX PROG_B A2 CONFIG VCCA UX DONE AB21 CONFIG VCCA UX TCK A2 1[...]

  • Page 68

    Pinout Descriptions 68 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R User I/Os b y Bank T able 61 and Ta b l e 6 2 i ndic ates h ow the user-I /O pins ar e distr ibuted between the f our I/O b anks on the CS 484 package. The A WAKE pin is c ounted a s a Dual- Pur po se I/O . Footpr int Migration Di fferences There ar e n[...]

  • Page 69

    Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 69 Pr oduct Specific ation R CS484 Footpr int Left Half of P acka ge (top vie w) 156 I/O: Unrestricted, general-purpos e user I/O. 41 INPUT : Unr estricted, general-purpos e input pin. 52 DU AL: Configuration, A WAKE pins, then possible user I/O. 28 VREF: User I/O or input voltage re[...]

  • Page 70

    Pinout Descriptions 70 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Right Half of CS484 P acka ge (top view) 12 13 14 15 16 17 18 19 20 21 22 INPU T I/O L11P_0 I/O L10P_0 INPU T I/O L06P_0 VREF_0 I/O L06N_0 INPU T I/O L07N_0 I/O 0 TCK GND A GND I/O L11N_0 VCCO_0 I/O L10N_0 GND I/O L03P_0 VCCO_0 I/O L02N_0 I/O L07P_0 VCC[...]

  • Page 71

    Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 71 Pr oduct Specific ation R FG676: 676-Ball Fine-P itch Ball Gr id Arra y The 676 -ball fi ne-pitc h ball gr id array , FG67 6, sup por t s both the XC3S D1800A and th e XC3SD34 00A F PGAs. The re are multiple pinou t differences be tween the two devices. F or a list of d ifferences[...]

  • Page 72

    Pinout Descriptions 72 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R 0 IO_L22P _0 D16 I/O 0 IO_L21P _0 D17 I/O 0 IO_L17P _0 D18 I/O 0 IO_L11P _0 D20 I/O 0 IO_L10N_ 0 D21 I/O 0 IO_L05P _0 D22 I/O 0 IO_L06P _0 D23 I/O 0 IO_L44P _0 C5 I/O 0 IO_L41N_ 0 C6 I/O 0 IO_L42N_ 0 C7 I/O 0 IO_L40P _0 C8 I/O 0 IO_L34P _0 C10 I/O 0 IO_[...]

  • Page 73

    Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 73 Pr oduct Specific ation R 0 VCCO_0 B16 VCCO 0 VCCO_0 B22 VCCO 1 IO_L01P _1/HDC Y20 DU AL 1 IO_L0 1N_1 /LDC 2 Y21 DUAL 1 IO_L13P _1 Y22 I/O 1 IO_L13N_ 1 Y23 I/O 1 IO_L15P _1 Y24 I/O 1 IO_L15N_ 1 Y25 I/O 1 IP_L16N _1 Y26 INPUT 1 IO_L04P _1 W20 I/O 1 IO_L04N_ 1 W21 I/O 1 IO_L18P _1 W[...]

  • Page 74

    Pinout Descriptions 74 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R 1 IO_L50N_ 1 K21 I/O 1 IO_L46N_ 1 K22 I/O 1 IO_L46P _1 K23 I/O 1 IP_L40P_1 K24 INPUT 1 IO_L41P _1 K25 I/O 1 IO_L41N_ 1 K26 I/O 1 IO_L59P _1 J19 I/O 1 IO_L59N_ 1 J20 I/O 1 IO_L62P _1/A20 J 21 DU AL 1 IO_L49N_ 1 J22 I/O 1 IO_L49P _1 J23 I/O 1 IO_L4 3N_1 /[...]

  • Page 75

    Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 75 Pr oduct Specific ation R 2 IO_L46P _2 W17 I/O 2 IO_L09P _2 V10 I/O 2 IO_L13P _2 V11 I/O 2 IO_L16P _2 V12 I/O 2 IO_L20P _2 V13 I/O 2 IO_L31P _2 V14 I/O 2 IO_L35P _2 V15 I/O 2 IO_L42P _2 V16 I/O 2 IO_L46N_ 2 V17 I/O 2 IO_L13N_ 2 U11 I/O 2 IO_L35N_ 2 U15 I/O 2 IO_L42N_ 2 U16 I/O 2 I[...]

  • Page 76

    Pinout Descriptions 76 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R 2 IO_L4 1N_2 AC20 I /O 2 IO_L4 5N_2 AC21 I /O 2 IO_2 A C22 I/O 2 IP_2/VREF_2 AB6 VREF 2 IO_L14N_ 2 AB7 I/O 2 IO_L15P _2 AB9 I/O 2 IO_L21P _2 AB12 I/O 2 IP_2 AB13 INPUT 2 IO_L30N_2/MOSI/CSI_ B AB15 DU AL 2 IO_L38N_ 2 AB16 I/O 2 IO_L47P _2 AB18 I/O 2 IO_L[...]

  • Page 77

    Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 77 Pr oduct Specific ation R 3 IO_L48P _3 T10 I/O 3 IO_L36P _3/VREF_3 R1 VREF 3 IO_L36N_ 3 R2 I/O 3 IO_L37P _3 R3 I/O 3 IO_L37N_ 3 R4 I/O 3 IO_L40P _3 R5 I/O 3 IO_L40N_ 3 R6 I/O 3 IO_L45N_ 3 R7 I/O 3 IO_L45P _3 R8 I/O 3 IO_L43N_ 3 R9 I/O 3 IO_L43P_3/VREF_3 R10 V REF 3 IO_L33P_3/L HCL[...]

  • Page 78

    Pinout Descriptions 78 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R 3 IP_L04P_3 C2 INPUT 3 IO_L02N_ 3 B1 I/O 3 IO_L02P _3 B2 I/O 3 IP_L66P_3 AE1 INPUT 3 IP_L66N_3/VREF_3 AE2 V R EF 3 IO_L65P _3 AD1 I/O 3 IO_L65N_ 3 AD2 I/O 3 IO_L60N_ 3 A C1 I/O 3 IO_L64P _3 AC 2 I/O 3 IO_L64N_ 3 A C3 I/O 3 IO_L60P _3 AB1 I/O 3 IO_L55P _[...]

  • Page 79

    Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 79 Pr oduct Specific ation R GND GND F21 GND GND GND F26 GND GND GND C3 GND GND GND C9 GND GND GND C14 GND GND GND C19 GND GND GND C24 GND GND GND AF1 GND GND GND AF6 GND GND GND AF11 GN D GND GND AF16 GN D GND GND AF21 GN D GND GND AF26 GN D GND GND AD3 GND GND GND AD8 GND GND GND A[...]

  • Page 80

    Pinout Descriptions 80 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R User I/Os by Bank T able 64 indi cates how the av ai lable user-I/O pi ns are distr ibuted between the four I/O banks o n the F G676 pa ckage. The A W AK E pin is coun ted as a Du al-P ur pose I/O. T able 64: User I/Os P er Bank for the X C3SD180 0A in [...]

  • Page 81

    Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 81 Pr oduct Specific ation R FG676 Footprint - XC3SD18 00A FPGA Left Half of Pac kage (top vie w) 314 I/O: Unrestricted, general-purpos e user I/O. 82 INPUT : Unr estricted, general-purpos e input pin. 52 DU AL: Configuration, A WAKE pins, then possible user I/O. 39 VREF: User I/O or[...]

  • Page 82

    Pinout Descriptions 82 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Right Half of FG676 P ackage (top view) 14 15 16 17 18 19 20 21 22 23 24 25 2 6 I/O L26N_0 GCL K7 I/O L23N_ 0 GND INPUT I/O L18N_0 I/O L15N_0 I/O L14N_0 GND I/O L07N_0 INPUT ∇ INP U T ∇ TCK GND A I/O L26P_0 GCL K6 I/O L23P_0 VCCO_0 I/ O L19N_0 I/O L[...]

  • Page 83

    Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 83 Pr oduct Specific ation R XC3SD3400A FPGA Ta b l e 6 5 l ists al l the FG 676 pa ckage pins for the XC3SD3400 A FPG A. They are sor ted by bank numb er and then by pin nam e. P air s of pins that form a differential I/O pair app ear togeth er in the table. Ta b l e 6 5 also sho ws[...]

  • Page 84

    Pinout Descriptions 84 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R 0 IO_L05P _0 D2 2 I/O 0 IO_L06P _0 D2 3 I/O 0 IO_L44P _0 C5 I/O 0 IO_L41N_ 0 C6 I/O 0 IO_L42N_ 0 C7 I/O 0 IO_L40P _0 C8 I/O 0 IO_L34P _0 C1 0 I/O 0 IO_L32P _0 C1 1 I/O 0 IO_L30N_ 0 C12 I/O 0 I O_L28 N_0/ GCL K11 C13 GCLK 0 IO_L22N_ 0 C15 I/O 0 IO_L21N_ [...]

  • Page 85

    Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 85 Pr oduct Specific ation R 1 IO_L12N_ 1 U18 I/O 1 IO_L12P _1 U1 9 I/O 1 IO_L10N_ 1 U20 I/O 1 IO_L14P _1 U2 1 I/O 1 IO_L21N_ 1 U22 I/O 1 IO_L23P _1 U2 3 I/O 1 I O_L23 N_1 /VRE F_1 U24 VR EF 1 IP_1/VREF_1 U26 VREF 1 IO_L17N_ 1 T17 I/O 1 IO_L17P _1 T18 I/O 1 IO_L14N_ 1 T20 I/O 1 IO_L2[...]

  • Page 86

    Pinout Descriptions 86 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R 1 IP_1/VREF_1 G2 5 VREF 1 IO_L58P_1/VR EF_1 F22 VREF 1 IO_L56N_ 1 F23 I/O 1 IO_L54N_ 1 F24 I/O 1 IO_L54P _1 F25 I/O 1 IO_L56P_1 E24 I/O 1 IO_L60P_1 E26 I/O 1 IO_L61N_ 1 D24 I/O 1 IO_L61P _1 D2 5 I/O 1 IO_L60N_ 1 D26 I/O 1 I O_L63 N_1/ A23 C25 D UAL 1 IO[...]

  • Page 87

    Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 87 Pr oduct Specific ation R 2 IO_L48P_2 AF23 I/O 2 IO_L52P_2/D0 /DIN/MISO AF24 DUA L 2 IO_L51P_2 AF25 I/O 2 IO_L06P_2 AE3 I/O 2 IO_L07P_2 AE4 I/O 2 IO_L10N_2 AE6 I/O 2 IO_L11N_2 AE7 I/O 2 IO_L18P_2 AE8 I/O 2 IO_L19P_2/VS1 AE9 DUA L 2 IO_L22P_2/D 7 AE10 DU AL 2 IO_L24N_2/D4 AE12 DUA [...]

  • Page 88

    Pinout Descriptions 88 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R 2 VCCO_2 AB8 VCCO 2 VCCO_2 AB1 4 VCCO 2 VCCO_2 AB1 9 VCCO 3 IO_L53P_3 Y1 I/O 3 IO_L53N_3 Y2 I/O 3 IP_3 Y3 INPUT 3 IO_L57P_3 Y5 I/O 3 IO_L57N_3 Y6 I/O 3 IP_L50P_3 W1 INPUT 3 IP_L50N_3/VREF_3 W2 VREF 3 IO_L52P _3 W3 I/O 3 IO_L52N_ 3 W4 I/O 3 IO_L63N_ 3 W6[...]

  • Page 89

    Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 89 Pr oduct Specific ation R 3 IO_L23N_3 K2 I/O 3 IO_L23P_3 K3 I/O 3 IO_L22N_3 K4 I/O 3 IO_L22P_3 K5 I/O 3 IO_L18P_3 K6 I/O 3 IO_L13P_3 K7 I/O 3 IO_L05N_3 K8 I/O 3 IO_L05P_3 K9 I/O 3 IP_L24P_3 J1 INPUT 3 IP_L20N_3/VREF_3 J2 VREF 3 IP_L20P_3 J3 INPUT 3 IO_L19N_ 3 J4 I/O 3 IO_L19P _3 J[...]

  • Page 90

    Pinout Descriptions 90 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R GND GND P12 GND GND GND P16 GND GND GND P19 GND GND GND P24 GND GND GND N3 G ND GND GND N8 G ND GND GND N11 GND GND GND N15 GND GND GND M12 GND GND GND M14 GND GND GND M16 GND GND GND L1 GND GND GND L6 GND GND GND L11 GND GND GND L13 GND GND GND L15 GND[...]

  • Page 91

    Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 91 Pr oduct Specific ation R GND GND A23 GND GND GND A26 GND VCCA UX DONE AB21 CONFIG VCCA UX PROG_B A2 CONFIG VCCA UX TDI G7 JT AG VCCA UX TDO E23 J T A G VCCA UX TMS D4 JT AG VCCA UX TCK A25 JT A G VCCA UX VCCA UX W26 VCCA UX VCCA UX VCCA UX V9 VCCAUX VCCA UX VCCA UX U14 VCCAUX VCC[...]

  • Page 92

    Pinout Descriptions 92 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R User I/Os by Bank T able 66 indi cates how the av ai lable user-I/O pi ns are distr ibuted between the f our I/O banks on the FG 676 package. The A WAKE pin is c ounted a s a Dual- Pur po se I/O . T able 66: User I/Os P er Bank for the X C3SD340 0A in t[...]

  • Page 93

    Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 93 Pr oduct Specific ation R FG676 Footprint - XC3SD34 00A FPGA Left Half of Pac kage (top vie w) 314 I/O: Unrestricted, general-purpos e user I/O. 34 INPUT : Unr estricted, general-purpos e input pin. 52 DU AL: Configuration, A WAKE pins, then possible user I/O. 37 VREF: User I/O or[...]

  • Page 94

    Pinout Descriptions 94 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Right Half of FG676 P ackage (top view) 14 15 16 17 18 19 20 21 22 23 24 25 2 6 I/O L26N_0 GCL K7 I/O L23N_ 0 GND INPUT I/O L18N_0 I/O L15N_0 I/O L14N_0 GND I/O L07N_0 GND ∇ VCCAUX ∇ TCK GND A I/O L26P_0 GCL K6 I/O L23P_0 VCCO_0 I/ O L19N_0 I/O L18P[...]

  • Page 95

    Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 95 Pr oduct Specific ation R Footpr int Migration Di fferences There ar e multiple m igration footprin t differences be tween the XC3SD1 800A a nd the X C3SD34 00A in the FG676 package. These mi gration footprin t differences a re shown in Ta b l e 6 7 . M igration fro m the XC 3S140[...]

  • Page 96

    Pinout Descriptions 96 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Migrat ion Recomm endations There ar e multiple p inout d ifferences be tween the XC3SD1800 A and the X C3SD3400A FPG As in the FG676 package. Please not e the di fferences between th e two de vices from Ta b l e 6 7 an d take the ne cess ar y p recauti[...]

  • Page 97

    Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 97 Pr oduct Specific ation R Revi sion H istory The f ollo wing tab le sho ws the re vi sion hi stor y f or this docum ent. w ww . x ilinx.com/spartan3adsp Date V ers ion Revision 04/02/ 07 1.0 Initial Xili nx release. 05/25/ 07 1.1 Update s to Ta b l e 5 8 , T abl e 6 0 , T able 61 [...]

  • Page 98

    Pinout Descriptions 98 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R This page intentionally left b lank.[...]