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Xilinx EDK 8.2i manual

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Table of contents for the manual

  • Page 1

    R Micr oBlaz e Pr ocessor Ref erence Guide Embed ded De velopment Kit EDK 8.2i UG081 (v6.0) June 1, 2006[...]

  • Page 2

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com UG081 (v6.0) June 1, 2006 1-800-255-7778 © 2006 Xilinx, Inc. All Rights Reser v ed. XILINX, the Xilinx logo , and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the proper ty of their respective o wners. NO TICE OF DISCLAIMER: Xilinx is providing[...]

  • Page 3

    UG081 (v6.0) June 1, 2006 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 Micr oBlaze Processor Reference Guide UG081 (v6.0) J une 1, 2006 The following table shows the revision history for this document. Date V ersion Revision 10/01/02 1.0 Xilinx EDK 3.1 release 03/1 1/03 2.0 Xilinx EDK 3.2 release 09/24/03 3.0 Xilinx EDK 6.1 [...]

  • Page 4

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com UG081 (v6.0) June 1, 2006 1-800-255-7778[...]

  • Page 5

    UG081 (v6.0) June 1, 2006 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 Preface: About This Guide Manual Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

  • Page 6

    UG081 (v6.0) June 1, 2006 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 MicroBlaze I/O Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

  • Page 7

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 7 UG081 (v6.0) June 1, 2006 1-800-255-7778 R Pr eface About This Guide W elcome to the MicroBlaze Pr ocessor Reference Guide. This document provides information about the 32-bit soft processor Micr oBlaze, which is part of the Embedded Processor Development Kit (EDK). The document is intended as[...]

  • Page 8

    8 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Pref ace: About This Guide R Con ventions This document uses the following conventions. An example illustrates each convention. T ypogr aphical The following typographical conventions are used in this document: Problem Solvers Interactive tools that all[...]

  • Page 9

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 9 UG081 (v6.0) June 1, 2006 1-800-255-7778 Con ventions R Online Document The following conventions are used in this document: V ertical ellipsis . . . Repetitive material that has been omitted IOB #1: Name = QOUT’ IOB #2: Name = CLKIN’ . . . Horizontal ellipsis ... Repetitive material that [...]

  • Page 10

    10 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Pref ace: About This Guide R[...]

  • Page 11

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 11 UG081 (v6.0) June 1, 2006 1-800-255-7778 R Chapter 1 Micr oBlaze Ar chitectur e Overview The MicroBlaze embedded processor soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx field programmable gate arrays (FPGAs). Figure 1- 1 shows a functional bloc[...]

  • Page 12

    12 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R In addition to these fixed features the Micr oBlaze processor is parametrized to allow selective enabling of additional functionality . Older (depr ecated) versions of MicroBlaze support a subset of the optional fe[...]

  • Page 13

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 13 UG081 (v6.0) June 1, 2006 1-800-255-7778 Data T ypes and Endianness R Data T ypes and Endianness MicroBlaze uses Big-Endian, bit-r eversed format to repr esent data. The hardwar e supported data types for MicroBlaze ar e word, half wor d, and byte. The bit and byte organization for each type [...]

  • Page 14

    14 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R T able 1-5: Instruction Set Nomenc lature Symbol Description Ra R0 - R31, General Purpose Register , source operand a Rb R0 - R31, General Purpose Register , source operand b Rd R0 - R31, General Purpose Register , [...]

  • Page 15

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 15 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R << x Bit shift left x bits and Logic AND or Logic OR xor Logic exclusive OR op1 if cond else op2 Perform op1 if condition cond is true, else perform op2 & Concatenate. E.g. “0000100 & Imm7” is the concatenation of the ?[...]

  • Page 16

    16 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R ADDIKC Rd,Ra,Imm 001 1 10 Rd Ra Imm Rd := s(Imm) + Ra + C RSUBIKC Rd,Ra,Imm 001 1 1 1 Rd Ra Imm Rd := s(Imm) + Ra + C MUL Rd,Ra,Rb 010000 Rd Ra Rb 00000000000 Rd := Ra * Rb BSRL Rd,Ra,Rb 010001 Rd Ra Rb 00000000000 [...]

  • Page 17

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 17 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R PUT Ra,FSLx 01 101 1 00000 Ra 1000000000000 & FSLx FSLx := Ra (blocking data write) NGET Rd,FSLx 01 101 1 Rd 00000 0100000000000 & FSLx Rd := FSLx (non-blocking data read) MSR[FSL] := 1 if (FSL x _S_Control = 1) MSR[C] := not FSL[...]

  • Page 18

    18 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R MTS Sd,Ra 100101 00000 Ra 1 1 & Sd SPR[Sd] := Ra, where: • SPR[0x0001] is MSR • SPR[0x0007] is FSR MFS Rd,Sa 100101 Rd 00000 10 & Sa Rd := SPR[Sa], where: • SPR[0x0000] is PC • SPR[0x0001] is MSR •[...]

  • Page 19

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 19 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R BGTD Ra,Rb 1001 1 1 10100 Ra Rb 00000000000 PC := PC + Rb if Ra > 0 BGED Ra,Rb 1001 1 1 10101 Ra Rb 00000000000 PC := PC + Rb if Ra >= 0 ORI Rd,Ra,Imm 101000 Rd Ra Imm Rd := Ra or s(Imm) ANDI Rd,Ra,Imm 101001 Rd Ra Imm Rd := Ra and[...]

  • Page 20

    20 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R Registers MicroBlaze has an orthogonal instr uction set architecture. It has thirty-two 32-bit general purpose registers and up to seven 32-bit special purpose r egisters, depending on configured options. BLEID Ra,[...]

  • Page 21

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 21 UG081 (v6.0) June 1, 2006 1-800-255-7778 Registers R General Pur pose Registers The thirty-two 32-bit General Purpose Registers are number ed R0 through R31. The register file is r eset on bit stream download (r eset value is 0x00000000). Note: The register file is not reset by the external[...]

  • Page 22

    22 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R Machine Status Register (MSR) The Machine Status Register contains control and status bits for the pr ocessor . It can be read with an MFS instr uction. When reading the MSR, bit 29 is replicated in bit 0 as the car[...]

  • Page 23

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 23 UG081 (v6.0) June 1, 2006 1-800-255-7778 Registers R 22 EIP Exception In Progress 0 No hardwar e exception in progr ess 1 Hardwar e exception in progr ess Read/W rite 0 23 EE Exception Enable 0 Hardwar e exceptions disabled 1 Hardwar e exceptions enabled Read/W rite 0 24 DCE Data Cache Enable[...]

  • Page 24

    24 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R Exception Address Register (EAR) The Exception Address Register stor es the full load/store addr ess that caused the exception. For an unaligned access exception that means the unaligned access address, and for an D[...]

  • Page 25

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 25 UG081 (v6.0) June 1, 2006 1-800-255-7778 Registers R Exception Status Register (ESR) The Exception Status Register contains status bits for the processor . When read with the MFS instruction the ESR is specified by setting Sa = 0x0005. 19 20 26 27 31 ↑↑ ↑ ↑ RESER VED DS ESS EC Figure[...]

  • Page 26

    26 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R Branch T arget Register (BTR) The Branch T arget Register only exists if the Micr oBlaze processor is configured to use exceptions. The register stor es the branch target addr ess for all delay slot branch instruct[...]

  • Page 27

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 27 UG081 (v6.0) June 1, 2006 1-800-255-7778 Registers R Floating P oint Status Register (FSR) The Floating Point Status Register contains status bits for the floating point unit. It can be read with an MFS, and written with an MTS instruction. When read or written, the register is specified by[...]

  • Page 28

    28 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R T able 1-15: Pr ocessor V ersion Register 0 (PVR0) Bits Name Description V alue 0 CFG PVR implementation: 0=basic, 1=full Based on C_PVR 1 BS Use barrel shifter C_USE_BARREL 2 DIV Use divider C_USE_DIV 3 MUL Use har[...]

  • Page 29

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 29 UG081 (v6.0) June 1, 2006 1-800-255-7778 Registers R 25 OP0EXEC Generate exception for 0x0 illegal opcode C_OPCODE_0x0_ILLEGAL 26 UNEXEC Generate exception for unaligned data access C_UNALIGNED_EXCEPTION 27 OPEXEC Generate exception for any illegal opcode C_ILL_OPCODE_EXCEPTION 28 IOPBEXEC Ge[...]

  • Page 30

    30 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R 8:10 ICLL Instruction cache line length 2^n C_ICACHE_LINE_LEN 1 1:15 ICBS Instr uction cache byte size 2^n C_CACHE_BYTE_SIZE 16:31 Reserved 0 T able 1-20: Pr ocessor V ersion Register 5 (PVR5) Bits Name Description [...]

  • Page 31

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 31 UG081 (v6.0) June 1, 2006 1-800-255-7778 Pipeline Arc hitecture R Pipeline Ar chitecture MicroBlaze instr uction execution is pipelined. The pipeline is divided into five stages: Fetch (IF), Decode (OF), Execute (EX), Access Memory (MEM), and W riteback (WB). For most instructions, each stag[...]

  • Page 32

    32 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R Branches Normally the instructions in the fetch and decode stages (as well as prefetch buf fer) are flushed when executing a taken branch. The fetch pipeline stage is then reloaded with a new instruction fr om the [...]

  • Page 33

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 33 UG081 (v6.0) June 1, 2006 1-800-255-7778 Reset, Interrupts, Exceptions, and Break R Reset, Interrupts, Exceptions, and Break MicroBlaze supports r eset, interrupt, user exception, break, and har dware exceptions. The following section describes the execution flow associated with each of thes[...]

  • Page 34

    34 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R Reset When a Reset or Debug_Rst (1) occurs, MicroBlaze will flush the pipeline and start fetching instructions fr om the reset vector (addr ess 0x0). Both external reset signals are active high, and should be asser[...]

  • Page 35

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 35 UG081 (v6.0) June 1, 2006 1-800-255-7778 Reset, Interrupts, Exceptions, and Break R • Unaligned Exception The unaligned exception is caused by a word access wher e the address to the data bus has bits 30 or 31 set, or a half-word access with bit 31 set. • Divide by Zero Exception The divi[...]

  • Page 36

    36 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R Software Breaks T o perform a software br eak, use the brk and brki instructions. Refer to Chapter 4, “MicroBlaze Instr uction Set Architectur e” for detailed information on software br eaks. Latency The time it[...]

  • Page 37

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 37 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instruction Cache R PC ← 0x00000008 Instruction Cache Ov er view MicroBlaze may be used with an optional instruction cache for impr oved performance when executing code that resides outside the LMB addr ess range. The instruction cache has the follow[...]

  • Page 38

    38 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R For example: in a MicroBlaze configur ed with C_ICACHE_BASEADDR= 0x00300000, C_ICACHE_HIGHADDR=0x0030ff ff, C_CACHE_BYTE_SIZE=4096, and C_ICACHE_LINELEN=8; the cacheable memory of 64 kB uses 16 bits of byte address[...]

  • Page 39

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 39 UG081 (v6.0) June 1, 2006 1-800-255-7778 Data Cache R • Cache on and off contr olled using a bit in the MSR • Optional WDC instruction to invalidate data cache lines General Data Cache Functionality When the data cache is used, the memory address space in split into two segments: a cachea[...]

  • Page 40

    40 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R A load from an address within the cacheable range will, provided that the cache is enabled, trigger a check to determine if the requested data is curr ently cached. If it is (i.e. on a cache- hit) the requested data[...]

  • Page 41

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 41 UG081 (v6.0) June 1, 2006 1-800-255-7778 Floating P oint Unit (FPU) R F or mat An IEEE 754 single precision floating point number is composed of the following thr ee fields: 1. 1-bit sign 2. 8-bit biased exponent 3. 23-bit fraction (a.k.a. mantissa or significand) The fields are stor ed i[...]

  • Page 42

    42 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R Comparison The FPU implements the following floating point comparisons: • compare less-than, fcmp.lt • compare equal, fcmp.eq • compare less-or -equal, fcmp.le • compare gr eater-than, fcmp.gt • compare n[...]

  • Page 43

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 43 UG081 (v6.0) June 1, 2006 1-800-255-7778 Debug and T race R Figure 1-12: FSL used with HW accelerated function f x This method is similar to extending the ISA with custom instructions, but has the benefit of not making the overall speed of the processor pipeline dependent on the custom funct[...]

  • Page 44

    44 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R[...]

  • Page 45

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 45 UG081 (v6.0) June 1, 2006 1-800-255-7778 R Chapter 2 Micr oBlaze Signal Interface Description Overview The MicroBlaze cor e is organized as a Harvar d architectur e with separate bus interface units for data accesses and instruction accesses. The following three memory interfaces are supporte[...]

  • Page 46

    46 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R Figure 2-1: MicroBlaze Core Bloc k Diagram DXCL_M DXCL_S Data-side Instruction-side DOPB DLMB IOPB ILMB bus interf ace bus interf ace Instruction Buff er Program Counter Register File 32 X 32b ALU In[...]

  • Page 47

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 47 UG081 (v6.0) June 1, 2006 1-800-255-7778 MicroBlaze I/O Overview R IM_BE[0:3] IOPB O Instruction interface OPB byte enables IM_busLock IOPB O Instruction interface OPB bus lock IM_DBus[0:31] IOPB O Instruction interface OPB write data bus (always 0x00000000) IM_request IOPB O Instruction inte[...]

  • Page 48

    48 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R On-Chip P eripheral Bus (OPB) Interface Description The MicroBlaze OPB interfaces ar e implemented as byte-enable capable masters. Please refer to the Xilinx OPB design document: “OPB Usage in Xili[...]

  • Page 49

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 49 UG081 (v6.0) June 1, 2006 1-800-255-7778 Local Memory Bus (LMB) Interface Description R Local Memory Bus (LMB) Interface Description The LMB is a synchronous bus used primarily to access on-chip block RAM. It uses a minimum number of control signals and a simple pr otocol to ensure that local[...]

  • Page 50

    50 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R Data_Write[0:31] The write data bus is an output from the cor e and contains the data that is written to memory . It becomes valid when AS is high and goes invalid in the clock cycle after Ready is s[...]

  • Page 51

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 51 UG081 (v6.0) June 1, 2006 1-800-255-7778 Local Memory Bus (LMB) Interface Description R LMB T ransactions The following diagrams provide examples of LMB bus operations. Generic Wr ite Operation Generic Read Operation Figure 2-2: LMB Generic Write Operation Clk Addr Byte_Enable Data_W rite AS [...]

  • Page 52

    52 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R Back-to-Bac k Wr ite Operation Single Cycle Back-to-Bac k Read Operation Back-to-Bac k Mixed Read/Write Operation Figure 2-4: LMB Back-to-Bac k Write Operation Figure 2-5: LMB Single Cycle Bac k-to-B[...]

  • Page 53

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 53 UG081 (v6.0) June 1, 2006 1-800-255-7778 Local Memory Bus (LMB) Interface Description R Read and Write Data Steer ing The MicroBlaze data-side bus interface performs the r ead steering and write steering requir ed to support the following transfers: • byte, halfword, and wor d transfers to [...]

  • Page 54

    54 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R F ast Simplex Link (FSL) Interface Description The Fast Simplex Link bus provides a point-to-point communication channel between an output FIFO and an input FIFO. For details on the generic FSL proto[...]

  • Page 55

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 55 UG081 (v6.0) June 1, 2006 1-800-255-7778 Xilinx CacheLink (XCL) Interface Description R FSL T ransactions FSL BUS Write Operation A write to the FSL bus is performed by MicroBlaze using one of the flavors of the put instruction. A write operations transfers the register contents to an output[...]

  • Page 56

    56 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R The MicroBlaze CacheLink interface can also connect to an Fast Simplex Link (FSL) interfaced memory controller via explicitly instantiated FSL master/slave pair , however this topology is considered [...]

  • Page 57

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 57 UG081 (v6.0) June 1, 2006 1-800-255-7778 Xilinx CacheLink (XCL) Interface Description R CacheLink T ransactions All individual CacheLink accesses follow the FSL FIFO based transaction protocol: • Access information is encoded over the FSL data and control signals (e.g. DCACHE_FSL_OUT_Data, [...]

  • Page 58

    58 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R The CacheLink solution uses one incoming (slave) and one outgoing (master) FSL per cache controller . The outgoing FSL is used to send access requests, while the incoming FSL is used for receiving th[...]

  • Page 59

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 59 UG081 (v6.0) June 1, 2006 1-800-255-7778 Debug Interface Description R 0b01=byte1 or halfword0, 0x10=byte2, and 0x1 1=byte3 or halfword1. The selection of half-word or byte access is based on the contr ol bit for the data word in step 4. 3. If DCACHE_FSL_OUT_Full = 1 then stall until it goes [...]

  • Page 60

    60 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R T race_Reg_W rite 1 Instruction writes to the register file std_logic output T race_Reg_Addr 1 Destination register address std_logic_vector (0 to 4) output T race_MSR_Reg 1 Machine status register [...]

  • Page 61

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 61 UG081 (v6.0) June 1, 2006 1-800-255-7778 MicroBlaze Core Con fi gurability R Micr oBlaze Core Con fi gurability The MicroBlaze cor e has been developed to support a high degree of user configurability . This allows tailoring of the processor to meet specific cost/performance r equirements[...]

  • Page 62

    62 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R Parameters valid for MicroBlaze v5.00a ar e listed in T able 2-12 . Note that not all of these are r ecognized by older versions of MicroBlaze, however the configurability is fully backward compatib[...]

  • Page 63

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 63 UG081 (v6.0) June 1, 2006 1-800-255-7778 MicroBlaze Core Con fi gurability R C_USE_FPU Include hardware floating point unit (V irtex2 and later) 0, 1 0 integer C_USE_MSR_INSTR Enable use of instructions: MSRSET and MSRCLR 1 1 integer C_USE_PCMP_INSTR Enable use of instructions: PCMPBF , PCM[...]

  • Page 64

    64 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R C_ICACHE_HIGHADDR Instruction cache high address 0x00000000 - 0xFFFFFFFF 0x3FFF FFFF std_logi c_vector C_USE_ICACHE Instruction cache 0, 1 0 integer C_ALLOW_ICACHE_WR Instruction cache write enable 0[...]

  • Page 65

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 65 UG081 (v6.0) June 1, 2006 1-800-255-7778 R Chapter 3 Micr oBlaze Application Binary Interface Scope This document describes MicroBlaze Application Binary Interface (ABI), which is important for developing software in assembly language for the soft pr ocessor . The MicroBlaze GNU compiler foll[...]

  • Page 66

    66 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 3: MicroBlaze Application Binary Interface R Register Usage Con ventions The register usage convention for Micr oBlaze is given in T able 3-2 . The architectur e for MicroBlaze defines 32 general purpose r egisters (GPRs). These registers ar e[...]

  • Page 67

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 67 UG081 (v6.0) June 1, 2006 1-800-255-7778 Stack Con vention R • Certain registers ar e used as dedicated registers and pr ogrammers are not expected to use them for any other purpose. ♦ Registers R14 through R17 ar e used for storing the return addr ess from interr upts, sub-routines, trap[...]

  • Page 68

    68 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 3: MicroBlaze Application Binary Interface R Consider an example where Func1 calls Func2, which in turn calls Func3. The stack repr esentation at differ ent instances is depicted in Figure 3-2 . After the call fr om Func 1 to Func 2, the value [...]

  • Page 69

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 69 UG081 (v6.0) June 1, 2006 1-800-255-7778 Memory Model R Figure 3-2: Stack Frame Calling Con v ention The caller function passes parameters to the callee function using either the registers (R5 through R10) or on its own stack frame. The callee uses the caller ’s stack area to store the para[...]

  • Page 70

    70 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 3: MicroBlaze Application Binary Interface R Interrupt and Exception Handling MicroBlaze assumes certain addr ess locations for handling interrupts and exceptions as indicated in T able 3-3 . At these locations, code is written to jump to the a[...]

  • Page 71

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 71 UG081 (v6.0) June 1, 2006 1-800-255-7778 R Chapter 4 Micr oBlaze Instruction Set Ar chitectur e Summary This chapter provides a detailed guide to the Instr uction Set Architectur e of MicroBlaze™. Notation The symbols used throughout this document ar e defined in T able 4-1 . T able 4-1: S[...]

  • Page 72

    72 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R Formats MicroBlaze uses two instr uction formats: T ype A and T ype B. T ype A T ype A is used for register-r egister instructions. It contains the opcode, one destination and two source r egisters.[...]

  • Page 73

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 73 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R add Arithmetic Ad d Description The sum of the contents of registers rA and rB, is placed into r egister rD. Bit 3 of the instruction (labeled as K in the figure) is set to a one for the mnemonic addk. Bit 4 of the instruction (labeled [...]

  • Page 74

    74 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R addi Arithmetic Ad d Immediate Description The sum of the contents of registers rA and the value in the IMM field, sign-extended to 32 bits, is placed into register rD. Bit 3 of the instruction (la[...]

  • Page 75

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 75 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R and Logical AND Description The contents of register rA ar e ANDed with the contents of register rB; the r esult is placed into register rD. Pseudocode (rD) ← (rA) ∧ (rB) Registers Altered • rD Latency 1 cycle and rD , rA, rB 1 0 0[...]

  • Page 76

    76 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R andi Logial AND with Immediate Description The contents of register rA are ANDed with the value of the IMM field, sign-extended to 32 bits; the result is placed into r egister rD. Pseudocode (rD) ?[...]

  • Page 77

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 77 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R andn Logical AND NO T Description The contents of register rA ar e ANDed with the logical complement of the contents of register rB; the r esult is placed into register rD. Pseudocode (rD) ← (rA) ∧ (rB) Registers Altered • rD Laten[...]

  • Page 78

    78 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R andni Logical AND NO T with Immediate Description The IMM field is sign-extended to 32 bits. The contents of register rA ar e ANDed with the logical complement of the extended IMM field; the resul[...]

  • Page 79

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 79 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R beq Branch if Equal Description Branch if rA is equal to 0, to the instruction located in the offset value of rB. The tar get of the branch will be the instruction at address PC + rB. The mnemonic beqd will set the D bit. The D bit deter[...]

  • Page 80

    80 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R beqi Branch Immediate if Equal Description Branch if rA is equal to 0, to the instruction located in the offset value of IMM. The tar get of the branch will be the instruction at address PC + IMM. T[...]

  • Page 81

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 81 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R bge Branch if Greater or Equal Description Branch if rA is greater or equal to 0, to the instr uction located in the offset value of rB. The target of the branch will be the instr uction at address PC + rB. The mnemonic bged will set the[...]

  • Page 82

    82 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R bgei Branch Immediate if Greater or Equal Description Branch if rA is greater or equal to 0, to the instruction located in the of fset value of IMM. The target of the branch will be the instruction [...]

  • Page 83

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 83 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R bgt Branch if Greater Than Description Branch if rA is greater than 0, to the instr uction located in the offset value of rB. The tar get of the branch will be the instruction at address PC + rB. The mnemonic bgtd will set the D bit. The[...]

  • Page 84

    84 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R bgti Branch Immediate if Greater Than Description Branch if rA is greater than 0, to the instr uction located in the offset value of IMM. The target of the branch will be the instr uction at address[...]

  • Page 85

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 85 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R ble Branch if Less or Equal Description Branch if rA is less or equal to 0, to the instruction located in the offset value of rB. The target of the branch will be the instr uction at address PC + rB. The mnemonic bled will set the D bit.[...]

  • Page 86

    86 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R blei Branc h Immediate if Less or Equal Description Branch if rA is less or equal to 0, to the instruction located in the offset value of IMM. The target of the branch will be the instr uction at ad[...]

  • Page 87

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 87 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R blt Branch if Less Than Description Branch if rA is less than 0, to the instruction located in the offset value of rB. The tar get of the branch will be the instruction at address PC + rB. The mnemonic bltd will set the D bit. The D bit [...]

  • Page 88

    88 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R blti Branc h Immediate if Less Than Description Branch if rA is less than 0, to the instruction located in the offset value of IMM. The tar get of the branch will be the instruction at address PC + [...]

  • Page 89

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 89 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R bne Branch if Not Equal Description Branch if rA not equal to 0, to the instruction located in the offset value of rB. The tar get of the branch will be the instruction at address PC + rB. The mnemonic bned will set the D bit. The D bit [...]

  • Page 90

    90 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R bnei Branch Immediate if Not Equal Description Branch if rA not equal to 0, to the instruction located in the offset value of IMM. The tar get of the branch will be the instruction at address PC + I[...]

  • Page 91

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 91 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R br Unconditional Branch Description Branch to the instruction located at address determined by rB. The mnemonics brld and brald will set the L bit. If the L bit is set, linking will be performed. The current value of PC will be stor ed i[...]

  • Page 92

    92 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R Note The instructions brl and bral ar e not available. A delay slot must not be used by the following: IMM, branch, or break instructions. This also applies to instructions causing r ecoverable exce[...]

  • Page 93

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 93 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R bri Unconditional Branch Immediate Description Branch to the instruction located at address determined by IMM, sign-extended to 32 bits. The mnemonics brlid and bralid will set the L bit. If the L bit is set, linking will be performed. T[...]

  • Page 94

    94 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R Notes The instructions brli and brali ar e not available. By default, T ype B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to use as the immediate operand. This b[...]

  • Page 95

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 95 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R brk Break Description Branch and link to the instruction located at address value in rB. The curr ent value of PC will be stored in rD. The BIP flag in the MSR will be set. Pseudocode (rD) ← PC PC ← (rB) MSR[BIP] ← 1 Registers Alt[...]

  • Page 96

    96 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R brki Break Immediate Description Branch and link to the instruction located at address value in IMM, sign-extended to 32 bits. The current value of PC will be stor ed in rD. The BIP flag in the MSR[...]

  • Page 97

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 97 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R bs Barrel Shift Description Shifts the contents of register rA by the amount specified in r egister rB and puts the result in register rD. The mnemonic bsll sets the S bit (Side bit). If the S bit is set, the barrel shift is done to the[...]

  • Page 98

    98 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R bsi Barrel Shift Immediate Description Shifts the contents of register rA by the amount specified by IMM and puts the r esult in register rD. The mnemonic bsll sets the S bit (Side bit). If the S b[...]

  • Page 99

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 99 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R cmp Integer Compare Description The contents of register rA is subtracted fr om the contents of register rB and the r esult is placed into register rD. The MSB bit of rD is adjusted to shown true r elation between rA and rB. If the U bit[...]

  • Page 100

    100 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R fadd Floating P oint Arithmetic Add Description The floating point sum of registers rA and rB, is placed into r egister rD. Pseudocode if isDnz(rA) or isDnz(rB) then (rD) ← 0xFFC00000 FSR[DO] ?[...]

  • Page 101

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 101 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R fr sub Reverse Floating P oint Arithmetic Subtraction Description The floating point value in rA is subtracted from the floating point value in rB and the result is placed into r egister rD. Pseudocode if isDnz(rA) or isDnz(rB) then ([...]

  • Page 102

    102 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R fm ul Floating P oint Arithmetic Multiplication Description The floating point value in rA is multiplied with the floating point value in rB and the result is placed into r egister rD. Pseudocode[...]

  • Page 103

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 103 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R fdiv Floating P oint Arithmetic Division Description The floating point value in rB is divided by the floating point value in rA and the result is placed into register rD. Pseudocode if isDnz(rA) or isDnz(rB) then (rD) ← 0xFFC00000 [...]

  • Page 104

    104 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R fcmp Floating P oint Number Comparison Description The floating point value in rB is compared with the floating point value in rA and the comparison result is placed into r egister rD. The OpSel [...]

  • Page 105

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 105 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R Registers Altered • rD, unless an FP exception is generated, in which case the register is unchanged • ESR[EC] • FSR[IO,DO] Latency 1 cycle Note These instructions are only available when the MicroBlaze parameter C_USE_FPU is set [...]

  • Page 106

    106 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R get get fr om fsl interface Description MicroBlaze will r ead from the FSLx interface and place the r esult in register rD. The get instruction has four variants. The blocking versions (when ‘n?[...]

  • Page 107

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 107 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R idiv Integer Divide Description The contents of register rB is divided by the contents of r egister rA and the result is placed into register rD. If the U bit is set, rA and rB is considered unsigned values. If the U bit is clear , rA a[...]

  • Page 108

    108 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R imm Immediate Description The instruction imm loads the IMM value into a temporary r egister . It also locks this value so it can be used by the following instruction and form a 32-bit immediate va[...]

  • Page 109

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 109 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R lb u Load Byte Unsigned Description Loads a byte (8 bits) from the memory location that r esults from adding the contents of registers rA and rB. The data is placed in the least significant byte of r egister rD and the other three byte[...]

  • Page 110

    110 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R lb ui Load Byte Unsigned Immediate Description Loads a byte (8 bits) from the memory location that r esults from adding the contents of register rA with the value in IMM, sign-extended to 32 bits. [...]

  • Page 111

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 111 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R lhu Load Halfwor d Unsigned Description Loads a halfword (16 bits) fr om the halfword aligned memory location that r esults from adding the contents of registers rA and rB. The data is placed in the least significant halfword of r egis[...]

  • Page 112

    112 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R lhui Load Halfwor d Unsigned Immediate Description Loads a halfword (16 bits) fr om the halfword aligned memory location that r esults from adding the contents of register rA and the value in IMM, [...]

  • Page 113

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 113 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R lw Load W ord Description Loads a word (32 bits) fr om the word aligned memory location that r esults from adding the contents of registers rA and rB. The data is placed in r egister rD. Pseudocode Addr ← (rA) + (rB) Addr[30:31] ← 0[...]

  • Page 114

    114 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R lw i Load W ord Immediate Description Loads a word (32 bits) fr om the word aligned memory location that r esults from adding the contents of register rA and the value IMM, sign-extended to 32 bits[...]

  • Page 115

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 115 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R mfs Move Fr om Special Purpose Register Description Copies the contents of the special purpose register rS into r egister rD. Pseudocode switch (rS): case 0x0000 : (rD) ← PC case 0x0001 : (rD) ← MSR case 0x0003 : (rD) ← EAR case 0[...]

  • Page 116

    116 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R msr c lr Read MSR and clear bits in MSR Description Copies the contents of the special purpose register MSR into r egister rD. Bit positions in the IMM value that are 1 ar e cleared in the MSR. Bit[...]

  • Page 117

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 117 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R msr set Read MSR and set bits in MSR Description Copies the contents of the special purpose register MSR into r egister rD. Bit positions in the IMM value that are 1 ar e set in the MSR. Bit positions that are 0 in the IMM value are lef[...]

  • Page 118

    118 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R mts Move T o Special Purpose Register Description Copies the contents of register rD into the MSR or FSR. Pseudocode (rS) ← (rA) Registers Altered • rS Latency 1 cycle Notes When writing MSR us[...]

  • Page 119

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 119 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R mu l Multiply Description Multiplies the contents of registers rA and rB and puts the r esult in register rD. This is a 32- bit by 32-bit multiplication that will produce a 64-bit r esult. The least significant word of this value is pl[...]

  • Page 120

    120 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R m uli Multiply Immediate Description Multiplies the contents of registers rA and the value IMM, sign-extended to 32 bits; and puts the result in r egister rD. This is a 32-bit by 32-bit multiplicat[...]

  • Page 121

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 121 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R or Logical OR Description The contents of register rA ar e ORed with the contents of register rB; the r esult is placed into register rD. Pseudocode (rD) ← (rA) ∨ (rB) Registers Altered • rD Latency 1 cycle or rD , rA, rB 1 0 0 0 [...]

  • Page 122

    122 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R ori Logical OR with Immediate Description The contents of register rA ar e ORed with the extended IMM field, sign-extended to 32 bits; the result is placed into r egister rD. Pseudocode (rD) ← ([...]

  • Page 123

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 123 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R pcmpbf P attern Compare Byte Find Description The contents of register rA is bytewise compar ed with the contents in register rB. • rD is loaded with the position of the first matching byte pair , starting with MSB as position 1, and[...]

  • Page 124

    124 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R pcmpeq P attern Compare Equal Description The contents of register rA is compar ed with the contents in register rB. • rD is loaded with 1 if they match, and 0 if not Pseudocode if (rB) = (rA) th[...]

  • Page 125

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 125 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R pcmpne P attern Compare Not Equal Description The contents of register rA is compar ed with the contents in register rB. • rD is loaded with 0 if they match, and 1 if not Pseudocode if (rB) = (rA) then (rD) ← 0 else (rD) ← 1 Regis[...]

  • Page 126

    126 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R put put to fsl interface Description MicroBlaze will write the value fr om register rA to the FSLx interface. The put instruction has four variants. The blocking versions (when ‘n’ is ‘0’) [...]

  • Page 127

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 127 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R r sub Arithmetic Reverse Subtract Description The contents of register rA is subtracted fr om the contents of register rB and the r esult is placed into register rD. Bit 3 of the instruction (labeled as K in the figur e) is set to a on[...]

  • Page 128

    128 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R r subi Arithmetic Reverse Subtract Immediate Description The contents of register rA is subtracted fr om the value of IMM, sign-extended to 32 bits, and the result is placed into r egister rD. Bit [...]

  • Page 129

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 129 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R r tbd Return from Break rn from Interrupt Description Return from br eak will branch to the location specified by the contents of rA plus the IMM field, sign-extended to 32 bits. It will also enable breaks after execution by clearing [...]

  • Page 130

    130 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R r tid Return from Interrupt rn from Interrupt Description Return from interr upt will branch to the location specified by the contents of rA plus the IMM field, sign-extended to 32 bits. It will [...]

  • Page 131

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 131 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R r ted Return from Exception Description Return from exception will branch to the location specified by the contents of rA plus the IMM field, sign-extended to 32 bits. The instruction will also enable exceptions after execution. This [...]

  • Page 132

    132 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R r tsd Return from Subr outine Description Return from subr outine will branch to the location specified by the contents of rA plus the IMM field, sign-extended to 32 bits. This instruction always[...]

  • Page 133

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 133 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R sb Store Byte Description Stores the contents of the least significant byte of register rD, into the memory location that results fr om adding the contents of registers rA and rB. Pseudocode Addr ← (rA) + (rB) Mem(Addr) ← ( rD)[24:[...]

  • Page 134

    134 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R sbi Store Byte Immediate Description Stores the contents of the least significant byte of register rD, into the memory location that results fr om adding the contents of register rA and the value [...]

  • Page 135

    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 135 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R se xt16 Sign Extend Halfwor d Description This instruction sign-extends a halfwor d (16 bits) into a word (32 bits). Bit 16 in rA will be copied into bits 0-15 of rD. Bits 16-31 in rA will be copied into bits 16-31 of rD. Pseudocode (rD[...]

  • Page 136

    136 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R se xt8 Sign Extend Byte Description This instruction sign-extends a byte (8 bits) into a word (32 bits). Bit 24 in rA will be copied into bits 0-23 of rD. Bits 24-31 in rA will be copied into bits [...]

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    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 137 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R sh Store Halfwor d Description Stores the contents of the least significant halfwor d of register rD, into the halfwor d aligned memory location that results fr om adding the contents of registers rA and rB. Pseudocode Addr ← (rA) + [...]

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    138 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R shi Store Halfwor d Immediate Description Stores the contents of the least significant halfwor d of register rD, into the halfwor d aligned memory location that results from adding the contents of[...]

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    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 139 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R sra Shift Right Arithmetic Description Shifts arithmetically the contents of register rA, one bit to the right, and places the r esult in rD. The most significant bit of rA (i.e. the sign bit) placed in the most significant bit of rD.[...]

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    140 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R sr c Shift Right with Carry Description Shifts the contents of register rA, one bit to the right, and places the r esult in rD. The Carry flag is shifted in the shift chain and placed in the most [...]

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    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 141 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R srl Shift Right Logical Description Shifts logically the contents of register rA, one bit to the right, and places the r esult in rD. A zero is shifted in the shift chain and placed in the most significant bit of rD. The least signifi[...]

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    142 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R sw Store W ord Description Stores the contents of r egister rD, into the word aligned memory location that r esults from adding the contents of registers rA and rB. Pseudocode Addr ← (rA) + (rB) [...]

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    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 143 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R sw i Store W ord Immediate Description Stores the contents of r egister rD, into the word aligned memory location that r esults from adding the contents of registers rA and the value IMM, sign-extended to 32 bits. Pseudocode Addr ← (r[...]

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    144 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R wdc Write to Data Cache Description W rite into the data cache tag. The register rB value is not used. Register rA contains the instruction addr ess. Bit 30 in rA is the new valid bit. The WDC inst[...]

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    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 145 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R wic Write to Instruction Cache Description W rite into the instruction cache tag. The r egister rB value is not used. Register rA contains the instruction addr ess. Bit 30 in rA is the new valid bit. The WIC instruction should only be u[...]

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    146 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R xor Logical Exclusive OR Description The contents of register rA ar e XORed with the contents of register rB; the r esult is placed into register rD. Pseudocode (rD) ← (rA) ⊕ (rB) Registers Alt[...]

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    MicroBlaze Pr ocessor Reference Guide www .xilinx.com 147 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R xori Logical Exclusive OR with Immediate Description The IMM field is extended to 32 bits by concatenating 16 0-bits on the left. The contents of register rA ar e XORed with the extended IMM field; the result is placed into r egister [...]

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    148 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R[...]