English dropdown-ico

Xilinx ML605 manual

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92

Go to page of

Similar user manuals

A good user manual

The rules should oblige the seller to give the purchaser an operating instrucion of Xilinx ML605, along with an item. The lack of an instruction or false information given to customer shall constitute grounds to apply for a complaint because of nonconformity of goods with the contract. In accordance with the law, a customer can receive an instruction in non-paper form; lately graphic and electronic forms of the manuals, as well as instructional videos have been majorly used. A necessary precondition for this is the unmistakable, legible character of an instruction.

What is an instruction?

The term originates from the Latin word „instructio”, which means organizing. Therefore, in an instruction of Xilinx ML605 one could find a process description. An instruction's purpose is to teach, to ease the start-up and an item's use or performance of certain activities. An instruction is a compilation of information about an item/a service, it is a clue.

Unfortunately, only a few customers devote their time to read an instruction of Xilinx ML605. A good user manual introduces us to a number of additional functionalities of the purchased item, and also helps us to avoid the formation of most of the defects.

What should a perfect user manual contain?

First and foremost, an user manual of Xilinx ML605 should contain:
- informations concerning technical data of Xilinx ML605
- name of the manufacturer and a year of construction of the Xilinx ML605 item
- rules of operation, control and maintenance of the Xilinx ML605 item
- safety signs and mark certificates which confirm compatibility with appropriate standards

Why don't we read the manuals?

Usually it results from the lack of time and certainty about functionalities of purchased items. Unfortunately, networking and start-up of Xilinx ML605 alone are not enough. An instruction contains a number of clues concerning respective functionalities, safety rules, maintenance methods (what means should be used), eventual defects of Xilinx ML605, and methods of problem resolution. Eventually, when one still can't find the answer to his problems, he will be directed to the Xilinx service. Lately animated manuals and instructional videos are quite popular among customers. These kinds of user manuals are effective; they assure that a customer will familiarize himself with the whole material, and won't skip complicated, technical information of Xilinx ML605.

Why one should read the manuals?

It is mostly in the manuals where we will find the details concerning construction and possibility of the Xilinx ML605 item, and its use of respective accessory, as well as information concerning all the functions and facilities.

After a successful purchase of an item one should find a moment and get to know with every part of an instruction. Currently the manuals are carefully prearranged and translated, so they could be fully understood by its users. The manuals will serve as an informational aid.

Table of contents for the manual

  • Page 1

    User Guide [optional] UG534 (v1.2.1 ) January 21, 20 10 [option al] ML605 Har d ware User Guide UG534 (v1.2.1 ) January 21, 20 10[...]

  • Page 2

    ML605 Hardware User Guide www .xilinx.com UG534 (v1.2.1) January 21, 2010 Xilinx is disclosing this user gui de, manual, rel ease note, and/or sp ecification (the "Documentation") to y ou solely f or use in the de velopment of designs to operate with Xilinx hardw are de vices. Y ou may not re produce, distribu te, repub lish, download, di[...]

  • Page 3

    ML605 Hardware User Guide www .xilinx.com 3 UG534 (v1.2.1) January 21, 2010 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

  • Page 4

    4 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 FPGA_PROG_B Pushbutton SW4 (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SYSACE_RESET_B Pu shbutton SW3 (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 System ACE CF CompactFlash Im age Select DIP Switch S1 . . . .[...]

  • Page 5

    ML605 Hardware User Guide www .xilinx.com 5 UG534 (v1.2.1) January 21, 2010 Pr eface About This Guide This manual accompan ies the V irtex®-6 FPGA M L605 Evaluation Boa rd and contains information about the ML605 hardwar e and software tools. Guide Contents This manual contains the following chapters: • Chapter 1, “ML605 Evalu ation Board,” [...]

  • Page 6

    6 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Pref ace: About This Guide • V irtex-6 FPGA Memory Resource s User Guide The functionality of the b lock RAM and FIFO are described in this u ser guide. • V irtex-6 FPGA SelectIO Resources User Guide This guide describes the SelectIO™ resour ces available in all V[...]

  • Page 7

    ML605 Hardware User Guide www .xilinx.com 7 UG534 (v1.2.1) January 21, 2010 Chapter 1 ML605 Evaluation Board Overview The ML605 boar d enables har dwar e and softwar e developers to cr eate or evaluat e designs targeting the V irtex®-6 XC6VLX240T -1FFG1 156 FPGA. The ML605 provides boar d featur es common to many embedded processing systems. Some [...]

  • Page 8

    8 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board F eatures The ML605 provides the following featur es: • 1. V irtex-6 XC 6VLX240T -1 FFG1 156 FPGA • 2. 512 MB DDR3 Memory SODIMM • 3. 128 Mb Platform Flash XL • 4. 32 MB Linear BPI Flash • 5. System ACE CF and CompactFlash Co[...]

  • Page 9

    ML605 Hardware User Guide www .xilinx.com 9 UG534 (v1.2.1) January 21, 2010 Overvie w • 16. Status LEDs ♦ Ethernet status ♦ FPGA INIT ♦ FPGA DONE ♦ System ACE CF Status • 17. User I/O ♦ USER LED Group 1 - GPIO (8) ♦ USER LED Group 2 - di rectional (5) ♦ User pushbuttons - directional (5 ) ♦ CPU reset pushbutton ♦ User DIP swit[...]

  • Page 10

    10 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board Bloc k Diagra m Figur e 1- 1 shows a high-level block diagram of the ML605 and its peripherals. Related Xilinx Documents Prior to using the ML605 Evaluation Board, user s should be famil iar with Xilinx re sources. See Appendix D, “[...]

  • Page 11

    ML605 Hardware User Guide www .xilinx.com 11 UG534 (v1.2.1) January 21, 2010 Detailed Des cription Detailed Description Figur e 1-2 shows a board photo with numbered featur es corresponding to Ta b l e 1 - 1 and the section headings in this document. The numbere d features in Fi gure 1-2 corr elate to the features and notes list ed in Ta b l e 1 - [...]

  • Page 12

    12 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 7 Clock generation 200 MHz OSC, oscillator socket, SMA connectors 30 a. 200 MHz oscillator (on backside) Epson 200 MHz 2.5V L VDS OSC 30 b. Oscillator socket, single- ended MMD Components 66 MHz 2.5V 30 c. SMA connectors SMA pair 30 d[...]

  • Page 13

    ML605 Hardware User Guide www .xilinx.com 13 UG534 (v1.2.1) January 21, 2010 Detailed Des cription 1. Vir te x-6 XC6VLX 240T -1FFG1156 FPGA A V irtex-6 XC6V LX240T -1FFG1 156 FPGA is installed on the embedded development board. Keep-Out ar eas and drill holes ar e define d ar ound the FPGA to support an Ir onwood Electronics SG-BGA-6046 FPGA socket[...]

  • Page 14

    14 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board The ML605 supports Mas ter BPI-Up, JT AG, an d Slave SelectMAP . These are selected by setting M[2:0] options 010 , 101 and 110 shown in Ta b l e 1 - 2 . For an overview on conf iguring the FP GA, see “Configuration Options,” page[...]

  • Page 15

    ML605 Hardware User Guide www .xilinx.com 15 UG534 (v1.2.1) January 21, 2010 Detailed Des cription Ref erences See the Xilinx V irtex-6 FPG A docu mentation for more information at http://www .xilinx.com/support/documentation/virtex-6.htm . 2. 512 MB DDR3 Memor y SODIMM A 512MB DDR3 SODIMM is provided as a flex i ble and effi cient form-factor vola[...]

  • Page 16

    16 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board A15 DDR3_A6 90 A6 B15 DDR3_A7 86 A7 G15 DDR3_A8 89 A8 F15 DDR3_A9 85 A9 M16 DDR3_A10 107 A10/AP M15 DDR3_A1 1 84 A1 1 H15 DDR3_A12 83 A12_BC_N J15 DDR3_A1 3 1 19 A13 D15 DDR3_A14 80 A14 C15 DDR3_A 15 78 A15 K19 DDR3_BA0 109 BA0 J19 DD[...]

  • Page 17

    ML605 Hardware User Guide www .xilinx.com 17 UG534 (v1.2.1) January 21, 2010 Detailed Des cription G12 DDR3_D20 40 DQ20 G13 DDR3_D21 42 DQ21 F14 DDR3_D22 50 DQ22 H14 DDR3_D23 52 DQ23 C19 DDR3_D24 57 DQ24 G20 DDR3_D25 59 DQ25 E19 DDR3_D26 67 DQ26 F20 DDR3_D27 69 DQ27 A20 DDR3_D28 56 DQ28 A21 DDR3_D29 58 DQ29 E22 DDR3_D30 68 DQ30 E23 DDR3_D31 70 DQ31[...]

  • Page 18

    18 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board E24 DDR3_D54 174 DQ54 G25 DDR3_D55 176 DQ55 F28 DDR3_D56 181 DQ56 B31 DDR3_D57 183 DQ57 H29 DDR3_D58 191 DQ58 H28 DDR3_D59 193 DQ59 B30 DDR3_D60 180 DQ60 A30 DDR3_D61 182 DQ61 E29 DDR3_D62 192 DQ62 F29 DDR3_D63 194 DQ63 E1 1 DDR3_DM0 [...]

  • Page 19

    ML605 Hardware User Guide www .xilinx.com 19 UG534 (v1.2.1) January 21, 2010 Detailed Des cription The Memory Interface Generator (MIG) tool guidelines specify a set of U1 FPGA “No Connect” pins. These should be added to the UCF as CONFIG PROHIB IT pins as follows: CONFIG PROHIBIT = H22; CONFIG PROHIBIT = F21; CONFIG PROHIBIT = B20; CONFIG PROH[...]

  • Page 20

    20 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 3. 12 8 Mb Platf or m Flash XL A 128 Mb Xilinx XCF128X-FTG64C Platform Fl ash XL device is used with an onboard 47 MHz oscillator (X4) to configure the FPGA in less than 100 ms from power valid as requir ed by the PCI Express Card Ele[...]

  • Page 21

    ML605 Hardware User Guide www .xilinx.com 21 UG534 (v1.2.1) January 21, 2010 Detailed Des cription ML605 Flash Boot Options The ML605 has two parallel wired fl ash memory devices as shown in Figur e 1-3 . At ML605 power-up, bef ore FPGA configuration, DIP switch S2 s witch 2 selects which f lash device, U4 (BPI) or U27 (Platform Flas h), provides t[...]

  • Page 22

    22 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board AF24 FLASH_D0 34 DQ0 F2 DQ00 AF25 FLASH_D1 36 DQ1 E2 DQ01 W24 FLASH_D2 39 DQ2 G3 DQ02 V24 F LASH_D3 41 DQ3 E4 DQ03 H24 FLASH_D4 47 DQ 4 E5 DQ04 H25 FLASH_D5 49 DQ 5 G5 DQ05 P24 F LASH_D6 51 DQ6 G6 DQ06 R24 FLASH_D7 53 DQ7 H7 DQ07 G23 [...]

  • Page 23

    ML605 Hardware User Guide www .xilinx.com 23 UG534 (v1.2.1) January 21, 2010 Detailed Des cription FPGA Design Considerations f or the Configuration Flash After FPGA configuration, the FPGA design can disable the configuration flash or access the configuration flash to r ead/write code or data. When the FPGA design does not use the config uration f[...]

  • Page 24

    24 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 5. System A CE CF and CompactFlash Connector The Xilinx System ACE CompactFlash (CF) configuration controller allows a T ype I or T ype II CompactFlash ca rd to pr ogram the FPGA through the JT AG port. Both hardware and software data[...]

  • Page 25

    ML605 Hardware User Guide www .xilinx.com 25 UG534 (v1.2.1) January 21, 2010 Detailed Des cription Ta b l e 1 - 6 list s the System ACE CF conne ctions. Ref erences See the System ACE CF product page and the System ACE CompactFlash Solu tion Data Sheet . [Ref 18] T able 1-6: System ACE CF Connections U1 FPGA Pin Schematic Net Name U19 XCCA CETQ144I[...]

  • Page 26

    26 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 6. USB JT A G JT AG configuration is pr ovided through on boar d USB-to-JT AG configuration logic wher e a computer host accesses the ML605 JT AG chai n through a T ype-A (computer host side) to T ype-Mini-B (ML605 side) USB cable. Th[...]

  • Page 27

    ML605 Hardware User Guide www .xilinx.com 27 UG534 (v1.2.1) January 21, 2010 Detailed Des cription Th e J T A G c h a in c a n b e u s e d t o p ro g r a m t h e F P GA a n d a cc e s s t he F P G A f o r h a rdw a re a n d software debug. The JT AG connector (USB Mini-B J22) allows a host computer to download bitstreams to the FPGA using the Xilin[...]

  • Page 28

    28 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board X-Ref Target - Figure 1-7 Figure 1-7: ML605 Oscillator Soc ket Pin 1 Location Identifier s S ilk s creened o u tline h as b e v eled corner UG5 3 4_07_092109 S ock et h as notch in cro ssba r[...]

  • Page 29

    ML605 Hardware User Guide www .xilinx.com 29 UG534 (v1.2.1) January 21, 2010 Detailed Des cription SMA Connectors (Diff erential) A high-pr ecision clock signal can be provide d to the FPGA using dif fer ential clock signals through the onboar d 50-ohm SMA connectors J58(P)/J55(N). X-Ref Target - Figure 1- 8 Figure 1- 8: ML605 Os cillator Pin 1 Loc[...]

  • Page 30

    30 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board GTX SMA Clock The ML605 includes a pair of SMA connector s for a GTX (MGT) Clock as described in Figur e 1-9 and Ta b l e 1 - 7 . X-Ref Target - Figure 1-9 Figure 1- 9: GTX SMA Clock UG5 3 4_09_081 3 09 S MA_REFCLK_C_N1 J 3 0 3 2K10K-[...]

  • Page 31

    ML605 Hardware User Guide www .xilinx.com 31 UG534 (v1.2.1) January 21, 2010 Detailed Des cription 8 . Multi-Gigabit T ransceiv e rs (GTX MGTs) The ML605 provides access to 20 MGT s. • Eight (8) of the MGT s are w ired to the PCIe x8 Endpoint (P1) edge connector fingers • Eight (8) of the MGT s are wir ed to the FMC HPC connector (J64) • One [...]

  • Page 32

    32 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 9. PCI Express Endpoint Connectivity The 8-lane PCIe edge connector pe rforms data transfe rs at the rate of 2.5 GT/s for a Gen1 application and 5.0 GT/s for a Gen2 applica tio n. The V irtex FPGA GTX MGT s are used for the multi-giga[...]

  • Page 33

    ML605 Hardware User Guide www .xilinx.com 33 UG534 (v1.2.1) January 21, 2010 Detailed Des cription Ta b l e 1 - 8 s h o w s t h e P C I e c o n ne c t o r ( P1 ) t h a t p r o vi d e s up t o 8 -l a n e ac c e s s t h r o u g h t he G T X transceivers to the V irtex-6 FPGA inte grated Endpoint block for PCIe designs. T able 1- 8: PCIe Edge Connecto[...]

  • Page 34

    34 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board The PCIe interface obtains its power from th e DC power s upply provided with the ML605 or thro ugh the 12V A TX power supply connector . The PCIe edge connector is not used for any power connections. The board can be powered by one o[...]

  • Page 35

    ML605 Hardware User Guide www .xilinx.com 35 UG534 (v1.2.1) January 21, 2010 Detailed Des cription Ref erences See the following websites for more V irtex-6 FPGA Integrated Endpoint Block for PCI Express inf ormation: • http://www .xilinx.com/pr oducts/ipcenter/V6_PCI_Express_Block.htm • http://www .xilinx.com/support/docum entation/ipbusinterf[...]

  • Page 36

    36 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 11. 10/100/1000 T r i-Speed Ether net PHY T h e M L 6 0 5 u t i l i z e s t h e o n b o a r d M a r v e l l A l a s k a P H Y d e v i c e ( 8 8 E 1111 ) f o r E t h e r n e t communications at 10, 100, or 1000 Mb/s. Th e board support[...]

  • Page 37

    ML605 Hardware User Guide www .xilinx.com 37 UG534 (v1.2.1) January 21, 2010 Detailed Des cription SGMII GTX T ransceiver Cloc k Generation An Integrated Circuit System s ICS844021I chip generates a high-quality , low-jitter , 125- MHz L VDS clock from an inexpensive 25-MHz crys tal oscillator . This clock is sent to the GTX driving the SGMII inter[...]

  • Page 38

    38 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board Ref erences See the Marvell Alaska Gigabit Ethernet T ransceivers product page for more information. [Ref 28] Also, see the LogiCORE™ IP T ri-Mode Et hernet MAC User Guide . [Ref 19] AM12 PHY_RXD4 124 RXD4 AD1 1 PHY_RXD5 123 RXD5 AC[...]

  • Page 39

    ML605 Hardware User Guide www .xilinx.com 39 UG534 (v1.2.1) January 21, 2010 Detailed Des cription 12. USB-to-U AR T Bridge The ML605 contains a Silicon Labs CP2103G M USB-to-UAR T bridg e device (U34) whi ch allows connection to a host computer with a US B cable. The USB cable is supplied in this evaluation kit (T ype A end to host computer , T yp[...]

  • Page 40

    40 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 13. USB Controller The ML605 provides USB support via a Cypr ess CY7C67300 EZ-Host™ Programmable Embedded USB Host and Peri pheral Contr olle r (U81). The host port is a USB T ype-A connector (J5). A USB keyboard (without an inte rn[...]

  • Page 41

    ML605 Hardware User Guide www .xilinx.com 41 UG534 (v1.2.1) January 21, 2010 Detailed Des cription 14. D VI Codec The ML605 features a DVI connector (P3) to support an external video monitor . The DVI circuitry utilizes a Chr ontel CH7301C (U38) ca pable of 1600 X 1200 resolution with 24-bit color . The video interface chip dr ives both the digital[...]

  • Page 42

    42 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 15. IIC Bus The ML605 implements four IIC bus interfaces at the FPGA. The "MAIN" IIC bus hosts four items: • FPGA U1 Bank 34 "MAIN" IIC interface • 8Kb NV Memory U6 • FMC HPC connector J64 • DDR3 SODIMM Soc[...]

  • Page 43

    ML605 Hardware User Guide www .xilinx.com 43 UG534 (v1.2.1) January 21, 2010 Detailed Des cription X-Ref Target - Figure 1-14 Figure 1- 14: IIC Bus T opolog y U1 J6 3 P 3 U 3 8 BANK 3 4 IIC_ S D A_MAIN_L S IIC_ S CL_MAIN_L S IIC_ S DA _ S FP IIC_ S CL_ S FP IIC_ S DA _ DVI IIC_ S CL_D VI FMC_LPC_IIC_ S DA _ L S FMC_LPC_IIC_ S CL_L S FMC_LPC_IIC_ S [...]

  • Page 44

    44 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 8 Kb NV Memory The ML605 hosts an 8 Kb ST Micr oelectr onics M24C08 -WDW6TP IIC parameter s torage memory device (U6) . The IIC addres s of U7 is 0b1010100, and U6 is not write protected (WP pin 7 is tied to GND). The IIC memory is sh[...]

  • Page 45

    ML605 Hardware User Guide www .xilinx.com 45 UG534 (v1.2.1) January 21, 2010 Detailed Des cription 16. Status LEDs Ta b l e 1 - 1 9 defines the status LEDs. T able 1- 19: Status LEDs Designator Signal Name Color Label Description DS1 SYSACE_ST A T_LED GREEN Syst em ACE CF Status LED System ACE CF Status DS2 TI_PWRGOOD and MGT_TI_PWRGOOD GREEN P OWE[...]

  • Page 46

    46 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board Ether net PHY Status LEDs The Ethernet PHY status LEDs ar e mounted to be visible when the ML605 boar d is installed into a PC motherboa rd. They ar e mo unted in right-angle, plastic housings and c a n b e se e n o n t h e c o nn e c[...]

  • Page 47

    ML605 Hardware User Guide www .xilinx.com 47 UG534 (v1.2.1) January 21, 2010 Detailed Des cription FPGA INIT and DONE LEDs The typical Xilinx FPGA power up and conf iguration status LEDs are pr esent on the ML605. The red INIT LED DS31 comes on momentarily after the FPGA powers up and during its internal power -on process. The DONE LED DS13 comes o[...]

  • Page 48

    48 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board User LEDs The ML605 provides two gr oups of active-High LEDs as described in Figure 1- 18 and Ta b l e 1 - 2 1 . Note: See “User Pushbutton Switches, ” page 49 for more details about the LEDs. X-Ref Target - Figure 1-1 8 Figure 1-[...]

  • Page 49

    ML605 Hardware User Guide www .xilinx.com 49 UG534 (v1.2.1) January 21, 2010 Detailed Des cription User Pushb utton Switches The ML605 provides six active -High pushbutton sw itches: • SW5, SW6, SW7, SW8 and SW9, arranged in a diamond configur ation to depict “directional” headings North, South, East, W est and Center respectively • SW10 CP[...]

  • Page 50

    50 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board User DIP Switch The ML605 includes an active-High eigh t pole DIP swit ch as described in Figure 1-20 and Ta b l e 1 - 2 3 . T able 1-22 : User Pushb utton Switch Connections U1 FPGA Pin Schematic Net Name Pushb utton Switch Pin A19 G[...]

  • Page 51

    ML605 Hardware User Guide www .xilinx.com 51 UG534 (v1.2.1) January 21, 2010 Detailed Des cription User SMA GPIO The ML605 includes an pair of SMA connectors for GPIO as described in Figure 1-21 and Ta b l e 1 - 2 4 . X-Ref Target - Figure 1-21 Figure 1-21: User SMA GPIO UG5 3 4_21_072109 U S ER S MA GPIO N J56 3 2K10K-400E 3 J76 3 2K10K-400E 3 GND[...]

  • Page 52

    52 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board LCD Displa y (16 C haracter x 2 Lines) The ML605 board has a 16-character x 2-line LCD (Display T e ch S162D BA BC, installed onto J41 2x7 header) on the board to display text information. Potent iometer R270 adjusts the contrast of t[...]

  • Page 53

    ML605 Hardware User Guide www .xilinx.com 53 UG534 (v1.2.1) January 21, 2010 Detailed Des cription 1 8 . Switches The ML605 Evalua tion board includes the foll owing switches: • Power On/Off Slide Switch SW2 • FPGA_PROG_B SW 4 (active-Low) • SYSACE_RESET_B SW3 (active-Low) • System ACE CF CompactFlash Image Se lect DIP Switch S1 (active-Hig[...]

  • Page 54

    54 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board FPGA_PROG_B Pushbut ton SW4 (Activ e-Low) This switch grounds the FPGA's PR OG_B pin wh en pressed. This action clears the FPGA. See the V irtex-6 FPGA Data Sheet for mor e information on clearing the contents of the FPGA. [Ref 4[...]

  • Page 55

    ML605 Hardware User Guide www .xilinx.com 55 UG534 (v1.2.1) January 21, 2010 Detailed Des cription System A CE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash (CF) image select DIP switch S1, switch es 1–3, select which CF resident bitstream image is downloaded to the FPGA ( Figure 1-26 ). S1 switches 1–3 offer eight binar[...]

  • Page 56

    56 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board Mode, Osc Enab le, Boot EEPROM Select, and Addr Select D IP Switch S2 DIP switch S2 is a multi-purpose selector switch ( Figure 1-27 and T able 1-27, p age 57 ). FPGA M ode: S2 switches 3, 4, and 5 control the FPGA mode ( Ta b l e 1 -[...]

  • Page 57

    ML605 Hardware User Guide www .xilinx.com 57 UG534 (v1.2.1) January 21, 2010 Detailed Des cription See “3. 128 Mb Platform Flash XL,” page 20 and “4. 32 MB Linear BPI Fla sh,” page 20 for details. 19. VIT A 57.1 FMC HPC Connector The ML605 implements both the High Pin Coun t (HPC, J64) and Low Pin Count (LPC, J63) connector options of VIT A[...]

  • Page 58

    58 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board Note: The ML605 board V ADJ voltage for the FMC HPC and LPC connectors (J64 and J63) is fixed at 2.5V (non-adjusta ble). The 2.5V rail cannot b e tur ned off. The ML605 VIT A 57.1 FMC interfaces are compatible with 2.5V mezzanine card[...]

  • Page 59

    ML605 Hardware User Guide www .xilinx.com 59 UG534 (v1.2.1) January 21, 2010 Detailed Des cription C14 FMC_HPC_LA10_P AM20 D14 FMC_HPC_LA09_P AM18 C15 FMC_HPC_LA10_N AL20 D15 FMC_HPC_LA09_N AL18 C18 FMC_HPC_LA14_P AN19 D17 FMC_HPC_LA13_P AP19 C19 FMC_HPC_LA14_N AN20 D18 FMC_HPC_LA13_N AN18 C22 FMC_HPC_LA18_CC_P AH25 D20 FMC_HPC_LA17_CC_P AN27 C23 F[...]

  • Page 60

    60 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board E28 FMC_HPC_HB09_N AK34 F28 FMC_HPC_HB08_P AK33 E30 FMC_HPC_HB13_P AH33 F29 FMC_HPC_HB08_N AK32 E31 FMC_HPC_HB13_N AH32 F31 FMC_HPC_HB12_P AJ31 E33 FMC_HPC_HB19_P AL31 F32 FMC_HPC_HB12_N AJ32 E34 FMC_HPC_HB19_N AK31 F34 FMC_HPC_HB16_P[...]

  • Page 61

    ML605 Hardware User Guide www .xilinx.com 61 UG534 (v1.2.1) January 21, 2010 Detailed Des cription J2 FMC_HPC_CLK3_M2C_P (2) U84.6 K4 FMC_HPC_CLK2_M2C _P (2) U83.6 J3 FMC_HPC_CLK3_M2C_N (2) U84.7 K5 FMC_HPC_CLK2_M2C _N (2) U83.7 J6 FMC_HPC_HA03_P AA25 K7 FMC_HPC_HA02_P AB25 J7 FMC_HPC_HA03_N Y26 K8 FMC_HPC_HA02_N AC25 J9 FMC_HPC_HA07_P AA26 K10 FMC[...]

  • Page 62

    62 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board T able 1-29 : P o wer Supply V oltages for HPC Connector Vo l t a g e S u p p l y Allowable Vo l t a g e R a n g e No Pins Max Amps T olerance Max Capacitive Load V ADJ Fixed 2.5V 4 4 +/- 5% 1000 uF VIO_B_M2C 0-V ADJ 2 1.15 +/- 5% 500[...]

  • Page 63

    ML605 Hardware User Guide www .xilinx.com 63 UG534 (v1.2.1) January 21, 2010 Detailed Des cription 20. VIT A 57.1 FMC LPC Connector The ML605 implements both the High Pin Coun t (HPC, J64) and Low Pin Count (LPC, J63) connector options of VIT A 57.1.1 FMC specific ation. This secti on discusses the FMC LP C J63 connector . The FMC standar d calls f[...]

  • Page 64

    64 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board Ta b l e 1 - 3 0 shows the VIT A 57.1 FMC LPC connections. The connector pinout is in Appendix B, “VIT A 57 .1 FMC LPC (J6 3 ) and HPC (J64) Connector Pinout.” Any signal named FMC_LPC_xxxx that is wired between a U1 FPGA pin and [...]

  • Page 65

    ML605 Hardware User Guide www .xilinx.com 65 UG534 (v1.2.1) January 21, 2010 Detailed Des cription Ref erences See the data sheet for the ROHS compliant FMC HPC Samtec SEARA Y connector (carrier side socket ASP-134486-01; module side plug ASP-134488-01), and the high-speed characterization report for this conne ctor system on the Samtec website. [R[...]

  • Page 66

    66 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board Onboard P ow er Regulation Figure 1- 28 shows the ML605 onboar d power supply architectur e. The ML605 uses power solutions fr om T exas Instruments. X-Ref Target - Figure 1-2 8 Figure 1-28: ML605 Onboard P ower Regulator s Line a r R[...]

  • Page 67

    ML605 Hardware User Guide www .xilinx.com 67 UG534 (v1.2.1) January 21, 2010 Detailed Des cription V o ltage and current monitoring and contr ol ar e available for selected power rails through T exas Instruments’ Fusion Digital Power™ gr aphical user interface (GUI). Both onboard TI power controller s are wir ed to the same PMBus. The PMB us co[...]

  • Page 68

    68 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board 22. System Monitor The System Monitor provides information r egarding the FPGA on-chip temperature and power supply conditions via JT AG and an inte rnal FPGA interface. The System Monitor can also be used to monitor ex ternal analog [...]

  • Page 69

    ML605 Hardware User Guide www .xilinx.com 69 UG534 (v1.2.1) January 21, 2010 Detailed Des cription System Monitor Header (J35) Figure 1- 30 shows the pinout for the System Monitor 12-pin he ader . The header pr ovides user access to the analog power supply (A Vdd ) and the 1.25V refer ence shown in Figure 1-29, page 68 . Access to the FPGA ther mal[...]

  • Page 70

    70 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board ML605 Board P ower Mo nitor In addition to monitoring the FPGA core supply power consumption, two a uxiliary analog input channels (of the 16 that are available) are used to implement a power monitor for the entire ML605 boar d. The b[...]

  • Page 71

    ML605 Hardware User Guide www .xilinx.com 71 UG534 (v1.2.1) January 21, 2010 Detailed Des cription F an Controller In highly demanding situations , active thermal management in the form of a heat sink and fan may be requi red. In or der to support this, drive cir cuitry for an external fan has been provided on the ML605. A fan with tach output can [...]

  • Page 72

    72 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board FPGA P ower Supply Mar gining The PMBus (IIC), which provides access to th e 2 x UDC9240 power controllers, can also be accessed via FPGA I/O in addition to a dedicated header (J3), see Fi gure 1-33 . A full description of the UDC9240[...]

  • Page 73

    ML605 Hardware User Guide www .xilinx.com 73 UG534 (v1.2.1) January 21, 2010 Configuration Options Configuration Options The FPGA on the ML605 Evaluation Board can be configur ed by the following methods: • “3. 128 Mb Platform Flash XL,” page 20 • “4. 32 MB Linear BPI Flash,” page 20 • “5. System ACE CF and C ompactFlash Connector?[...]

  • Page 74

    74 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Chapter 1: ML605 Ev aluation Board[...]

  • Page 75

    ML605 Hardware User Guide www .xilinx.com 75 UG534 (v1.2.1) January 21, 2010 Appendix A Default Switch and Jumper Settings Ta b l e A - 1 : Def ault Switch Settings REFDES Function/T ype Default SW2 Boar d power slide-switch off SW1 User GPIO 8-pole DIP switch 8 o f f 7 o f f 6 o f f 5 o f f 4 o f f 3 o f f 2 o f f 1 o f f S1 System ACE CF configur[...]

  • Page 76

    76 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Appendix A: Default Switc h and J umper Settings Ta b l e A - 2 : Def ault Jumper Setting s J umper REFDES Function Default J69 System ACE CF Error LED Enable Jump 1-2 GMII: J66 pins 1-2: GMII/M II to Cu pins 2-3: SGMI I to Cu, no clk Jump 1 - 2 J67 pins 1-2: GMII/M II[...]

  • Page 77

    ML605 Hardware User Guide www .xilinx.com 77 UG534 (v1.2.1) January 21, 2010 Appendix B VIT A 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout Figure B-1 shows the pinout of the FMC LPC co nnector . Pins marked NC are not connected. X-Ref Target - Figure B-1 Figure B-1: FMC LPC Connector Pinout KJ H G F E D C B A 1 N C N C V R E F _ A_ M2 C G ND N[...]

  • Page 78

    78 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Appendix B: VIT A 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout Figure B-2 shows the pinout of the FMC HPC connector . X-Ref Target - Figure B-2 Figure B-2: FMC HPC Connector Pinout KJH G F E D C B A 1 V R E F_ B_ M 2 C G ND V R EF _ A _ M 2 C GN D P G_ M 2 C G N D[...]

  • Page 79

    ML605 Hardware User Guide www .xilinx.com 79 UG534 (v1.2.1) January 21, 2010 Appendix C ML605 Master UCF The UCF template is provided for design s that target the ML605. Net names pr ovided in the constraints below correlate with net names on the ML605 Rev . D schematic. On identifying the appropriate pins, the net name s below should be r eplaced [...]

  • Page 80

    80 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Appendix C: ML605 Maste r UCF NET "DDR3_D8" LOC = "M13"; ## 21 on J1 NET "DDR3_D9" LOC = "J14"; ## 23 on J1 NET "DDR3_D10" LOC = "B13"; ## 33 on J1 NET "DDR3_D11" LOC = "B12"; ## 35 on J1 N[...]

  • Page 81

    ML605 Hardware User Guide www .xilinx.com 81 UG534 (v1.2.1) January 21, 2010 NET "DDR3_DQS0_P" LOC = "D12"; ## 12 on J1 NET "DDR3_DQS1_N" LOC = "J12"; ## 27 on J1 NET "DDR3_DQS1_P" LOC = "H12"; ## 29 on J1 NET "DDR3_DQS2_N" LOC = "A14"; ## 45 on J1 NET "DDR3_DQS2_P[...]

  • Page 82

    82 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Appendix C: ML605 Maste r UCF NET "FLASH_A21" LOC = "AF9"; ## 10 on U4, A8 on U27 NET "FLASH_A22" LOC = "AL9"; ## 9 on U4, G1 on U27 NET "FLASH_A23" LOC = "AA23"; ## 26 on U4 NET "FLASH_D0" LOC = &qu[...]

  • Page 83

    ML605 Hardware User Guide www .xilinx.com 83 UG534 (v1.2.1) January 21, 2010 NET "FMC_HPC_DP6_M2C_N" LOC = "AM6"; ## B17 on J64 NET "FMC_HPC_DP6_M2C_P" LOC = "AM5"; ## B16 on J64 NET "FMC_HPC_DP7_C2M_N" LOC = "AP2"; ## B33 on J64 NET "FMC_HPC_DP7_C2M_P" LOC = "AP1"; ## [...]

  • Page 84

    84 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Appendix C: ML605 Maste r UCF NET "FMC_HPC_HB03_P" LOC = "AL30"; ## E21 on J64 NET "FMC_HPC_HB04_N" LOC = "AL33"; ## F26 on J64 NET "FMC_HPC_HB04_P" LOC = "AM33"; ## F25 on J64 NET "FMC_HPC_HB05_N" L[...]

  • Page 85

    ML605 Hardware User Guide www .xilinx.com 85 UG534 (v1.2.1) January 21, 2010 NET "FMC_HPC_LA16_N" LOC = "AN23"; ## G19 on J64 NET "FMC_HPC_LA16_P" LOC = "AP22"; ## G18 on J64 NET "FMC_HPC_LA17_CC_N" LOC = "AM27"; ## D21 on J64 NET "FMC_HPC_LA17_CC_P" LOC = "AN27"; ## D2[...]

  • Page 86

    86 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Appendix C: ML605 Maste r UCF NET "FMC_LPC_LA07_N" LOC = "H32"; ## H14 on J63 NET "FMC_LPC_LA07_P" LOC = "G32"; ## H13 on J63 NET "FMC_LPC_LA08_N" LOC = "K29"; ## G13 on J63 NET "FMC_LPC_LA08_P" LOC [...]

  • Page 87

    ML605 Hardware User Guide www .xilinx.com 87 UG534 (v1.2.1) January 21, 2010 NET "FPGA_M0" LOC = "U8"; ## 3 on S2 DIP switch (active-High) NET "FPGA_M1" LOC = "W8"; ## 4 on S2 DIP switch (active-High) NET "FPGA_M2" LOC = "V8"; ## 4 on S2 DIP switch (active-High) NET "FPGA_PROG_B"[...]

  • Page 88

    88 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Appendix C: ML605 Maste r UCF NET "PCIE_RX2_N" LOC = "L4"; ## B24 on P1 NET "PCIE_RX2_P" LOC = "L3"; ## B23 on P1 NET "PCIE_RX3_N" LOC = "N4"; ## B28 on P1 NET "PCIE_RX3_P" LOC = "N3"; ## B[...]

  • Page 89

    ML605 Hardware User Guide www .xilinx.com 89 UG534 (v1.2.1) January 21, 2010 NET "PMBUS_DATA_LS" LOC = "AB10"; ## 2 on Q17 ## NET "SFP_LOS" LOC = "V23"; ## 8 on P4 NET "SFP_RX_N" LOC = "E4"; ## 12 on P4 NET "SFP_RX_P" LOC = "E3"; ## 13 on P4 NET "SFP_TX_DISABLE_FPG[...]

  • Page 90

    90 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Appendix C: ML605 Maste r UCF NET "USB_D6_LS" LOC = "V27"; ## 2 on U31 NET "USB_D7_LS" LOC = "U25"; ## 12 on U30 NET "USB_D8_LS" LOC = "Y28"; ## 14 on U29 NET "USB_D9_LS" LOC = "W32"; ## 8 [...]

  • Page 91

    ML605 Hardware User Guide www .xilinx.com 91 UG534 (v1.2.1) January 21, 2010 Appendix D Refer ences This section provide s refer e nces to document ation supporting V irt ex-6 FPGAs, tools, and IP . For additional informa tion, see www .xilinx.com/support/d ocumentation/index.htm . Documents supporting the ML605 Evaluation Board: 1. UG535 , ML605 R[...]

  • Page 92

    92 www .xilinx.com ML6 05 Hard ware User Guid e UG534 (v1.2.1) January 21 , 2010 Appendix D: Ref erences Additional documentation: 22. Micron T echnology , Inc. , DDR3 SODIMM Specification (M T4JSF6464HY - 1G1) 23. Wi n b o n d , Serial Flash Memory Data Sheet ( W25Q64VSF IG) 24. Numonyx , Embedded Flash Memory Data Sh eet (TE28F128J3D-75 ) 25. Eps[...]