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Yamaha YMF744B (DS-1S) manual

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  • Page 1

    YMF744B DS-1S YAMAHA CORPORATION Decem ber 18, 1998 Prelimina ry YMF744B CATALOG CATALOG No.: LSI-4MF744B00 February 3, 1999 OVERVIEW YMF744B (DS-1S ) is a high perform ance audio con troller for th e PCI Bus. DS- 1S cons ists of t wo separat ed fun ction al block s. One is the PCI A udio block and the oth er is th e Leg acy A udio block . PCI Au d[...]

  • Page 2

    YMF744B February 3, 1999 -2- LOGOS 1. GM sy stem lev el 1 GM sy stem lev el 1 is a w orld standard form at about MIDI synth esizer wh ich provides voice arran gem ents and MI D I functions. 2. XG XG is a format abou t MIDI synth esizer that is proposed by YA MAHA, and keeps the upper com p atibility of GM sy stem level 1. T he good poin ts are the [...]

  • Page 3

    YMF744B February 3, 1999 -3- PIN CONFIGURA TION YMF744B-V (0.5m m pin pitch ) 128 Pin L QFP Top View AD7 AD6 AD5 PVDD 0 AD4 AD3 AD2 AD1 PVSS 0 AD0 SER IRQ # PC GN T # PC RE Q # CLK RUN # CVDD 0 ROMD I ROMC S VSS0 FRAM E# 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95[...]

  • Page 4

    YMF744B February 3, 1999 -4- YMF744B-R (0.4mm pin pitch ) 128 Pin L QFP Top View 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 33 34 35 36 37 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 ZVLR CK VDD1 CMCL K CSDO IRQ1 0 IRQ9 IRQ7 IRQ5 GPIO 2 GPIO 1 GPIO 0 RESERVE3 [...]

  • Page 5

    YMF744B February 3, 1999 -5- PIN DESCRIPTION 1. PCI Bus Interface (54-pin) Name I/O Type Size Function PCIC LK I P PCI C lock RST# I P Reset AD[31: 0] IO Ptr Address / Data C/BE[3:0]# IO Ptr Co mmand / Byte Enable PAR IO P tr Parity FRAME# IO Pstr Frame IRDY# IO Pstr Initiator Ready TRDY# IO Pstr Target Ready STOP # IO Pstr Stop IDSEL I P ID Select[...]

  • Page 6

    YMF744B February 3, 1999 -6- 3. External Audio Interface (5-pin) Name I/O Type Size Function SPDIFOUT O T 2m A Digital Au dio Interface ou tput SPDIFIN I Tup - Digital Au dio Interface inpu t ZVBC LK I Tup - Zoom ed Video Port Bi t Cl ock ZVL RCK I Tup - Zoom ed Video Port L /R Clock ZVSDI I Tup - Zoom ed Video Port Serial Data 4. Legacy Device Int[...]

  • Page 7

    YMF744B February 3, 1999 -7- 6. Power Supply ( 22-pin) Name I/O Type Size Function PVDD[3:0] - - - 3.3V P o wer supply for PCI Bus Interface PVSS[6:0] - - - Ground for PCI Bus Interface CVDD[2:0] - - - 3.3V Po wer supply for Core logic VDD[2:0] - - - 3.3V Power supply VSS[3:0] - - - Grou nd LVDD - - - 3.3V Power supply for PLL Filter 7. Reserv e Pi[...]

  • Page 8

    YMF744B February 3, 1999 -8- BLOCK DIA G RAM PCI Side Ban d PC / PCI S-IRQ Aud io Func tion Confi g Re g iste r PC I In t e rf a c e Le g ac y Audio FM S y nt he s iz er SB Pro D-DM A En g ine MPU 40 1 Jo y stick PCI Bu s Master D MA Cont r olle r PCI N ati v e A udi o XG S y nthe s izer Dire ctSoun d A cc. Wa v e I n / O u t ZV Port SRC Sa mp lin [...]

  • Page 9

    YMF744B February 3, 1999 -9- FUNCTION OVERVIEW 1. PCI INTERFACE DS-1S su pports the PCI bu s interface an d complies to PCI revision 2.2. 1-1. PCI Bus Com mand DS-1S supports the f ollow ing PCI Bu s com man ds. 1-1-1. T arget Device Mode C/BE[3:0]# Com mand 0000 I n t e r r u p t A c k n o w l e d g e ( n o t s u pport) 0001 S p e c i a l C y c l [...]

  • Page 10

    YMF744B February 3, 1999 -10- 1-2. PCI Config uration Regist er In addition to the Co nfiguration Register defined by P CI Revision 2.2 , DS-1S pro vides prop rietary PCI Configuratio n Registers in ord er to c o ntrol legacy audio function, such as FM Synthesizer, So und Bla ster P ro, MPU401 and Joystick . These additional registers are configu r[...]

  • Page 11

    YMF744B February 3, 1999 -11- 00-01h: Vendor ID Read Only Default: 1073h Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Vendor ID b[15:0] ........Vendor ID This regis ter contain s the YAMA HA Vendor ID regis tered in Re vision 2.2. This register is h ardw ired to 1073h . 02-03h: Device ID Read Only Default: [...]

  • Page 12

    YMF744B February 3, 1999 -12- b6 ................ PER: Parity Error Response This bit enables DS-1S respo nses to Parity Error. “0”: DS-1S ig nores all parity errors. “1”: DS- 1S perform s error operation w hen DS-1S detects a parity error. b8 ................ SER: SERR# Enable This bit enables DS-1S to drive SERR#. “0”: Do not drive SE[...]

  • Page 13

    YMF744B February 3, 1999 -13- 08h: Revision ID Read Only Default: 02h Access Bus W idth: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Revision I D b[7:0] ..........Revision ID This re giste r contains the revision number o f DS-1S. T his register is har dwired to 02h . 09h: Programming Interf ace Read Only Default: 00h Access Bus W idth: 8, 16, 32-bit b7 [...]

  • Page 14

    YMF744B February 3, 1999 -14- 0Dh: Latency Timer Read / W rite Default: 00h Access Bus W idth: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Latency Tim er b[7:0] ..........Latency Timer When DS-1S becomes a Bus Master device, this register indicates the initial value of the Master Latency Tim er. 0Eh: Header Ty pe Read Only Default: 00h Access Bus W idth:[...]

  • Page 15

    YMF744B February 3, 1999 -15- 14-17h: Legacy A udio I/O Base A ddress (Dummy for SB, FM, MPU , D-DMA ) Read / W rite Default: 00000001h Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 IOBASE0 ----- I/O b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 ---------- ------ b0 ................ IO (Rea[...]

  • Page 16

    YMF744B February 3, 1999 -16- 2C-2Dh: Subsystem Vendor ID Read Only Default: 1073h Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Subsys t em V endor I D b[15:0] ........Subsystem Vendor ID This register contains the Sub system Vendo r ID. In gener al, this ID is used to distinguish ada pters o r sy stem s m [...]

  • Page 17

    YMF744B February 3, 1999 -17- 34h: Capability Register Pointer Read Only Default: 50h Access Bus W idth: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Capability Register Point er b[7:0] ..........Capability Register Pointer This register indicates the offset address of the Capa bilities register in the PCI Configuration register wh en 58- 59h: AC PI Mode [...]

  • Page 18

    YMF744B February 3, 1999 -18- 3Fh: Maximum Latency Read Only Default: 19h Access Bus W idth: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Maximum Lat enc y b[7:0] ..........Maximum Latency This register indicates how often DS-1S generates the Bus Master Requ est. This regist er is hardw ired to 19h . 40-41h: Legacy A udio Control Read / W rite Default: 90[...]

  • Page 19

    YMF744B February 3, 1999 -19- b4 ................ MIEN: M PU401 IRQ Enable This bit enables the int errupt s ervice of MPU401, w hen LAD is set to “0” and MEN is set to “1”. MPU401 generates an in terrupt sign al w hen it receives an y k ind of MIDI data f rom the R XD pin. “0”: The MPU401 block can not u se the interru pt servi ce. “[...]

  • Page 20

    YMF744B February 3, 1999 -20- b14 .............. SIEN: Serialized IRQ enable DS-1S s upports 3 t ypes of interru pt protocols: PCI inte rrupt (INTA#), Leg acy i nterrupt (IRQs) and Serialized IRQ. The interrupt protocol is selected w ith IMOD and SIEN as follow s. The interrupt channels f or IRQs and Serialized IRQ are determined by SBIRQ and MPUIR[...]

  • Page 21

    YMF744B February 3, 1999 -21- b[14:13] ......SBVER: SB Version Select These bits set the version o f the SB Pro DSP . T he value set in these bits is returned by sending the E1h DS P co mma nd . “0”: ver 3.01 (default) “1”: ver 2.01 “2”: ver 1.05 “3”: reserved b15 .............. IMOD: Legacy IRQ mode The legacy interrupt protocol is[...]

  • Page 22

    YMF744B February 3, 1999 -22- 48-49h: DS-1S Cont rol Read / W rite Default: 0001h Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 B1 b0 ---------- -- ACLS WRST - CRST b0 ................ CRST: AC’97 Software Reset Signal Control This bit contro ls the CRST# signal. “0”: Inactive (CR ST#=High) “1”: Activ e [...]

  • Page 23

    YMF744B February 3, 1999 -23- 4A -4Bh: D S-1S P ower Control 1 Read / W rite Default: 0000h Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PR7 PR6 PR5 PR4 PR 3 PR2 PR1 PR0 - JSR --- DPLL - DMC b0 ................ DMC: Disable M aster Clock Oscillation Setting this bit to “1” disables the os cillation of t[...]

  • Page 24

    YMF744B February 3, 1999 -24- b12 .............. PR4: A C’97 Pow er Down Control 4 This bit contro ls the p ower state of the AC-link in the Primary A C’97. “0”: Normal (default) “1”: Pow er down b13 .............. PR5: A C’97 Pow er Down Control 5 Setting this bit to “1” disables the internal clock of the Pr imary AC’97. In cas[...]

  • Page 25

    YMF744B February 3, 1999 -25- 4E-4Fh: DS-1S Pow er Cont rol 2 Read / W rite Default: 0000h Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 - - - PSHW V PSIO PSACL PSDIR PSDIT PSZV PSSRC PSPCA PSJOY PSMPU PSSB PSFM CMCD b0 ................ CMCD: CODEC M aster Clock Disable Setting this bit to “1” disables t[...]

  • Page 26

    YMF744B February 3, 1999 -26- b7 ................ PSZV: Power Save Zoomed Video port Settin g th is bit to “ 1” stops a clock su pplied to th e Zoom ed Video port block . “0”: Normal (default) “1” : D isa ble b8 ................ PSDIT: Pow er Save Digital Audio Interface Transmitter Setting this bit to “1” stop s a clo c k sup plied[...]

  • Page 27

    YMF744B February 3, 1999 -27- PCI Clock (33MHz) PCI I/F PC/PCI S-IRQ EEPROM I/F I/O P ad PSIO External Input Master Clock (24.576MHz) PLL DMC DPLL FM Synthesizer SB Pro A C-link ZVpor t H/W V ol. PCI A udio SRC SPDIF out SPDIF in A C97 Master Clock MPU401 Jo ystick CMCD PSFM PSSB PSMPU PSJO Y PSPCA PSSRC PSZV PSDIT PSDIR PSA CL PSHWV Power Manag em[...]

  • Page 28

    YMF744B February 3, 1999 -28- 51h: Next It em Poi nt er Read Only Default: 00h Access Bus W idth: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Nex t Item Pointer b[7:0] ..........Next Item Pointer DS-1S does not pr ovide other new capability besid es Pow er Management. This register is hardwired to 00h . 52-53h: Power Management Capabilities Read Only Def[...]

  • Page 29

    YMF744B February 3, 1999 -29- 58-59h: A CPI Mode Read / W rite Default: 0000h Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ---------- ----- ACPI b0 ................ A CPI: ACPI Mode Select This bit select either PCI Bus Power Manag emen t or ACPI Mode for pow er managem ent of DS-1S. “ 0”: PCI Bus Power[...]

  • Page 30

    YMF744B February 3, 1999 -30- b4 ................ SPR4: Secondary A C’97 Power Dow n Control 4 This bit contro ls the p ower state of the AC-link in the Secondary AC’97. “0”: Normal (default) “1”: Pow er down b5 ................ SPR5: Secondary A C’97 Power Dow n Control 5 Setting this bit to “1” disab les the internal clock of th[...]

  • Page 31

    YMF744B February 3, 1999 -31- 64-65h: MPU401 Base Address Read / W rite Default: 0000h Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 MPU401 Base Addres s - b[15:1] ........M PU401 Base A ddress This regi ster sets the base address of the MPU401. If b5: I/O bit of 40h regi ster is s et to “1”, b[9:1] bits[...]

  • Page 32

    YMF744B February 3, 1999 -32- 2. ISA Comp atible Device DS-1S contains the following functions to m aintain the compatibility w ith the past ISA Sound Devices. These devices are considered L egacy devices an d the fu nctions are ref erred to as Legacy A udio. Legacy Audio is independen t from PCI Audio an d can be us ed sim ultaneous ly. The config[...]

  • Page 33

    YMF744B February 3, 1999 -33- DS-1S su pports PC/PCI and D-DMA protocols to em ulate the DMA of SB Pr o on the PCI. In addition, DS- 1S support s the old t ype of interrupts u sed by ISA an d the Seri alized IRQ protocol. Yamah a recomm ends the combination of PC/PCI and Serialized IRQ. The system block diagram w hen using Intel chip set is sho wn [...]

  • Page 34

    YMF744B February 3, 1999 -34- 2-1. FM Synthesizer Block FM S yn thesi zer Block is reg ister compatibl e wi th YMF289B. Howev er, Pow er Managem ent regis ter has been deleted because it is n ow con trolled by th e PCI Config uration Reg ister. The follo wing show s the FMB ase I/O map of FM Synthesizer. FMBase (R) Status Register por t FMBase (W) [...]

  • Page 35

    YMF744B February 3, 1999 -35- 2-1-2. FM Synthesizer Data Register FM Synthesizer Dat a Register A rray 0 (R/W ): A d d r e s s D 7D 6D 5D 4D 3D 2D 1D 0 00-01h LSI TES T 02h TIMER 1 03h TIMER 2 04h RST MT1 MT2 - - - ST2 ST1 0 8 h - N T S ---- -- 20-35h (*1) AM VIB EGT KSR M ULT 40-55h (*2) KSL TL 60-75h (*3) AR DR 80-95h (*4) SL RR A0-A8h F-NUM (L) [...]

  • Page 36

    YMF744B February 3, 1999 -36- 2-2. Sound Blast er Pro Block This block emu lates the DSP comm ands of Sound Blaster and Sound Blaster Pro. Only play back fun ctions are s upported (record fun ctions are n ot supported). However, to m aintain compatibility for gam es, it is designed so that ev ery DSP com mand receives a correct response. The DMA tr[...]

  • Page 37

    YMF744B February 3, 1999 -37- 2-2-1. DSP Com m and The follow ing sh ows the li st of DS P Comm ands that are supported by the SB Pro engin e. Both SB and SB Pro com man ds are supported. CMD Support F unction 10h o 8bit direct mode single byte digitized sound output 14h o 8bit single-cycle DMA mode digitiz ed sound output 16h 8bit to 2bit ADPCM si[...]

  • Page 38

    YMF744B February 3, 1999 -38- 2-2-2. Sound Blaster Pro Mixer The follow ing show s the register m ap of the Mixer section of Soun d Blaster Pro. A d d r e s s b 7b 6b 5b 4b 3b 2b 1b 0 R e m a r k 00h Reset 04h Voice V ol um e L "1" Voice Volum e R "1" 0Ah - - - "1" - MIC Vol u m e* 0Ch - - Ifilte r* "1" Input[...]

  • Page 39

    YMF744B February 3, 1999 -39- (1) Volum e for MIDI MID I Vol. (26h) 01234567 mut e mute mu te mute mu te mute mu te mute 0 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h mut e -52dB -42dB -36dB -32dB -30dB -28dB -26dB 1 0000h 0029h 0082h 0103h 019Bh 0206h 028C h 0335h mut e -42dB -32dB -26dB -22dB -20dB -18dB -16dB 2 0000h 0082h 019Bh 0335h 0515h [...]

  • Page 40

    YMF744B February 3, 1999 -40- 2-2-3. SB Suspend / Res ume The SB block can read the internal state as to su pport Su spend and R esum e functions . The internal state is m ade up of 268 flip flops. To read the state, these states are shifted in order and read 8 bits at a time from the SCA N DATA register. These registers are mapped to th e SB Mixer[...]

  • Page 41

    YMF744B February 3, 1999 -41- F1h: Scan In/ O ut Data Read / W rite Default: 00h b7 b6 b5 b4 b3 b2 b1 b0 SCAN DATA b[7:0] ..........SCAN DA TA This is the data p o rt for reading and writing the internal state. F2h: Current FM Synthesizer Index Read Only Default: 00h b7 b6 b5 b4 b3 b2 b1 b0 Current FM Synthesi zer I ndex b[7:0] ..........Current FM[...]

  • Page 42

    YMF744B February 3, 1999 -42- b7 ................ FFEMP: FM Synthesizer Empty This bit indicates whether or not FIFO followed by the FM Sy nthesizer is empty. “0”: not Em pty “1”: Em pty (defaul t) i) Scan Out SBPDA=0 SBPDR=1 SBPDA=1 SM=1 SS=1 SE=1 -> 0 SE=1 -> 0 : not re ady f or scanning internal state data : inhibit further DMA, in[...]

  • Page 43

    YMF744B February 3, 1999 -43- 2-2-4. SB IRQ Status F8h: Interrupt Fl ag Regi ster Read Only Default: 00h b7 b6 b5 b4 b3 b2 b1 b0 ------- SBI b0 ................ SBI: SB Interrupt Flag This bit indicates that the SB DSP occurs the interrupt. T his bit is read only . Thus, read the SB DSP read port to clearing the interrup t and this bit. Then, the v[...]

  • Page 44

    YMF744B February 3, 1999 -44- 3. DMA Emulati on Protocol The form er sy nth esizer LSI f or the ISA bu s such as the Soun d Blaster used th e DMA controller (8237: ISA DMAC) on the sy stem to transfer the sound data from/to the host. For DS-1S, however, ISA DMAC m ust be used to transfer the sound da ta to the Sound Blaster Pro Block of the L egacy[...]

  • Page 45

    YMF744B February 3, 1999 -45- 3-2. D- DMA DS-1S prov ides the f ollow ing reg isters to su pport D-DMA . D-DMA S lave Conf igurat ion Regi ster (4C- 4Dh) of the PCI C onfigu ration register is us ed to set the Base address of the Slav e Address. Slave Address R/W Register Name Base + 0h W B ase Address 0-7 Base + 0h R Curren t Address 0-7 Base + 1h[...]

  • Page 46

    YMF744B February 3, 1999 -46- 4. Interrupt Routi ng DS-1S s upports t hree types of interru pts, in terrupt s ignal on the PCI bus (INTA #), interrupt s ign al on the ISA bus (IRQ[5,7,9,10,11]), an d Serialized IRQ. The IRQs on DS-1S are rout ed as show n below . Sound Blaster Pro MPU401 IRQ Selector Selector IRQ SBIRQ[2:0] ISA IRQ SERIRQ MPUIRQ[2:[...]

  • Page 47

    YMF744B February 3, 1999 -47- 5. Hard ware Volu me Co ntrol The hardware volume control de term ines the AC’97 master volume w itho ut using any softw are co ntrol using the external circuit listed below. Two pins, VOL UP # for increasing the volum e and VOLDW# for decreasing th e volum e, are used. 1k VOLDW# VOLUP# 1k 1000p 1000p Push SW Push SW[...]

  • Page 48

    YMF744B February 3, 1999 -48- 6. Digi tal Audio Interface DS-1S su pports each sy stem of the S PDIF input/outpu t port compliant with the IEC958 specifi cation. 6-1. SPDI F IN DS-1S provides the SP DIF input capab ility by switch- over operatio n of the zoomed video port. SPDIF input sam pling frequen cy is 32.0kHz, 44.1k Hz or 48.0kHz. In DS-1S, [...]

  • Page 49

    YMF744B February 3, 1999 -49- 7. Zoomed Video Port Zoom ed Video Port is defin ed in the PC C ard Stan dard (PCMCIA ) applicable to the n otebook PC or other sy stem s. T his port is us ed to directly output vi deo and/or audi o sign als ont o the PCMC IA bus for D/A conversion process, an d connect them directly to the video and/or audio signal pr[...]

  • Page 50

    YMF744B February 3, 1999 -50- 8. Multi ple AC’97 & M ulti-C hannel DS-1S allow s connection with up to two A C’97s, and play s back up to 4-channel PCM data. Therefore, the follow ing application s can be realized. 8-1. AC’97 Dig ital Docking AC’ 97 digital dockin g can be real ized by m ountin g the s econdary AC’ 97 on th e docking [...]

  • Page 51

    YMF744B February 3, 1999 -51- ELECTRICA L CHARA CTERISTICS 1. Absolute Maximum Rating s Item Sym bol Min. Max. Unit Pow er Supply Voltage (PVDD, VDD, CVDD, LVDD) V DD3 -0.3 4. 6 V Input Vo ltage V IN -0. 3 7.0 V Operating Am bient Temperature T OP 07 0 ° C Storage Temperature T STG -50 125 °C Note : PVSS=VSS=0[ V] 2. Recommended Operating Conditi[...]

  • Page 52

    YMF744B February 3, 1999 -52- 3. DC Char acteristics Item Symbol Conditio n Min. T yp. Max. Unit High Level Input Voltage 1 V IN -0.5 - 5.75 V High Level Input Voltage 1 V IH1 *1 0.5V DD3 -5 . 7 5 V Low L evel Input Voltage 1 V IL1 *1 -0.5 - 0.3V DD3 V High Level Input Voltage 2 V IH2 *2 0.7V DD3 -5 . 7 5 V Low L evel Input Voltage 2 V IL2 *2 -0.5 [...]

  • Page 53

    YMF744B February 3, 1999 -53- 4. AC Character istics 4-1. Master Clock (Fig.1) Item Sym bol Min. Typ. Max. Unit XI24 Cy cle Time t XICYC - 40.69 - ns XI24 High Tim e t XI HIGH 13 - 24 ns XI24 Low T ime t XILOW 13 - 24 ns Note : T op = 0-70° C, PVDD=3.3 ± 0.3 V, VDD=3.3 ± 0.3 V, C VDD=3.3 ± 0.3 V, L VDD=3.3 ± 0.3 V t XI24 XICYC t XIHIGH 1.0 V 1[...]

  • Page 54

    YMF744B February 3, 1999 -54- 4-3. PCI Interface (Fig.3, 4) Item Sym bol Condition Min. Typ. Max. Unit PCICLK Cy cle T im e t PCYC 30 - - ns PCI CLK High T ime t PHIGH 11 - - ns PCI CLK Lo w Time t PLOW 11 - - ns PCIC LK Sl ew Rate - 1 - 4 V/n s t PVAL (Bused signa l) 2 - 11 ns PCICLK to Signal Valid Delay t PVAL ( PTP ) (Point to P oint) 2 - 1 2 n[...]

  • Page 55

    YMF744B February 3, 1999 -55- 4-4. AC’97 Master Cloc k (F ig.5) Item Sym bol Min. Typ. Max. Unit CMCLK Cycle Time t CMCYC - 40.69 - ns CMCLK High Time t CMHIGH 8- - n s CMCLK Low Time t CMLOW 8- n s CMCLK Rising Ti me t CMR -4 . 6 - n s CMCLK Falling T i me t CMF -2 . 1 - n s Note : T op = 0-70° C, PVDD=3.3 ± 0.3 V, VDD= 3.3 ± 0.3 V, CVDD=3.3 [...]

  • Page 56

    YMF744B February 3, 1999 -56- 4-5. AC-link (Fig.6) Item Sym bol Conditio n Min. Typ. Max. Unit CBCLK Cycle T ime t CBICYC - 81.4 - ns CBCLK High T ime t CBIHIGH 35 40.7 45 ns CBCLK Low T i me t C BILOW 35 40.7 45 n s CSYNC Cycle Time t CSYCYC - 20.8 - ns CSYNC High Time t CSYHIGH -1 . 3- µ s CSYNC Low Time t CSYLOW - 19.5 - µ s CBCLK to Signal Va[...]

  • Page 57

    YMF744B February 3, 1999 -57- 4-6. Zoom ed Video Port (Fig.7) Item Sym bol Min. Typ. Max. Unit ZVLRCK De lay T i me t SLR D 2- - n s ZVLRCK Se tup T ime t SLR S 32 - - ns ZVB C LK Low T ime t SC LKL 22 - - ns ZVBC LK High T ime t SC LKH 22 - - ns ZVSDI Setup Time t SDS 32 - - ns ZVSD I Ho ld T ime t SDH 2- - n s Note : T op = 0-70° C, PVDD=3.3 ± [...]

  • Page 58

    YMF744B February 3, 1999 -58- EXTERNA L DIMENSIONS YMF744B-V 102 65 103 128 13 8 39 64 P-0.50T yp. 0.15T yp. or 0.17T yp . (LEAD THICKNESS) 1.70MAX. 0 Min. (ST AND OFF) Unit : mm 22.00±0.40 20.00±0.30 14.00±0.30 0.20±0.10 16.00±0.40 (1.00) 0-15˚ 0.50±0.30 1.40±0.20 The shape of the m olded corner may slightly different from the shape in thi[...]

  • Page 59

    YMF744B February 3, 1999 -59- YMF744B-R 96 97 128 13 2 33 64 65 P-0.40T yp. Unit : mm 16.00±0.40 14.00±0.30 14.00±0.30 0.16±0.10 16.00±0.40 (1.0) 0-10˚ 0.50±0.20 1.40±0.20 1.70MAX. 0 Min. (STAND OFF) LEAD THICKNESS : 0.125Typ. or 0.15Typ. The shape of the m olded corner may slightly different from the shape in this diagram . The figure in t[...]

  • Page 60

    YMF744B February 3, 1999 -60- IMPORTANT NOT ICE 1. Yamaha reserv es the ri g ht to make chan g es to its Products and to this document without notice. The information cont ained in this document has been carefull y checked and is believed to be reliable. How ever, Yamaha assumes no responsibilities for inaccur acies and makes no com mitment to upda[...]