AMD SB600 manual

AMD SB600 Register Reference Manual (Public Version) Technical Reference Manual Rev. 3.03 P/N: 46155_sb600 _rrg_pub_3.03 ©2008 Advanced Micro De vices, Inc.[...]

Trademarks AMD, the AMD A rrow logo, Athl on, and com binations th ereof, AT I, ATI logo, Radeon, and Crossfir e are tradem arks of A dvanced Micr o Devices, Inc. HyperTransport is a licen sed trademark of the HyperTransport Technolog y Consortium. Microsoft and Windows are registered trade marks and Windows Vista is trad emark of Microsoft Corpora[...]

© 2008 Advanced Micro De vices, Inc. Table of Contents AMD SB600 Register Referen ce Manual Proprietary Page 3 Table of Contents 1 Introducti on ............................................................................................................. 7 1.1 About this Manual.......................................................................[...]

© 2008 Advanced Micro De vices, Inc. List of Figures AMD SB600 Register Referen ce Manual Proprietary Page 4 2.5 AC ’97 Controller Func tional Descriptions ................................................................................. 198 2.5.1 Audio Registers (Device 20, Func tion 5) ..........................................................[...]

© 2008 Advanced Micro De vices, Inc. List of Figures AMD SB600 Register Referen ce Manual Proprietary Page 5 List of Figures Figure 1 SB600 PCI In ternal De vices ............................................................................................ .............................. 11 Figure 2 SB600 PCI Internal De vices and Major F unction Bl[...]

© 2008 Advanced Micro De vices, Inc. List of Tables AMD SB600 Register Referen ce Manual Proprietary Page 6 List of Tables Table 1-1: Register Descripti on Table Nota tion—Exa mple ......................................................................... ................... 7 Table 2-1 HcRevi sion Register .......................................[...]

© 2008 Advanced Micro De vices, Inc. About this Manual AMD SB600 Register Referen ce Manual Proprietary Page 7 1 Introduction 1.1 About this Manual This manual is a register referen ce guide for the AMD SB600 Southbridge. It integrates the key I/O, communications, an d audio features required in a st ate-of-t he-art PC into a single device. It is [...]

© 2008 Advanced Micro De vices, Inc. Nomenclature and Conventions AMD SB600 Register Referen ce Manual Proprietary Page 8 Register Information Value/Content in the Example Register name Latency Timer Read / Write capabilit y R = Readable W = Writable RW = Readable and Writable RW Register size 8 bits Register address(es)* Offset: 0Dh Field name La[...]

© 2008 Advanced Micro De vices, Inc. Features of the SB600 AMD SB600 Register Referen ce Manual Proprietary Page 9 1.3 Features of the SB600 CPU Interface  Supports both Single and Dual core AMD CPUs  Desktop: Athlon 64, Athlon 64 FX, Athlon 64 X2, Sempron, Opteron, dual-core Opteron  Mobile: Athlon XP-M, Mobile Athlon 64, Turion 64, Mobi[...]

© 2008 Advanced Micro De vices, Inc. Features of the SB600 AMD SB600 Register Referen ce Manual Proprietary Page 10 AC Link interface  Supports for both audio an d modem codecs  Compliant with AC-97 co dec Rev. 2.3  6/8 channel support on audio co dec  Multiple functions for audio and modem Codec operations  Bus master logic  Sup[...]

© 2008 Advanced Micro De vices, Inc. Block Diagram s AMD SB600 Register Referen ce Manual Proprietary Page 11 1.4 Block Diagrams This section contains two block diag rams for the SB600. Figure 1 shows the SB600 intern al PCI devices with their assigned bus, device, and function numbers. Figure 2 shows the SB600 internal PCI devices and the major f[...]

© 2008 Advanced Micro De vices, Inc. Block Diagram s AMD SB600 Register Referen ce Manual Proprietary Page 12 SATA Controller AC97 Audio IDE LPC PCI Bridge SMBUS /ACPI AB AC97 Modem HD Audio PORT 1 PORT 0 USB:OHCI USB:EHCI 8250 TIMER GPIO BM RTC ACPI / HW Monitor SMBUS ROM BUS Controler PIC APIC INTERRUPT controller SMI SIRQ PM SPEAKER GEVENT[7:0][...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 13 2 Register Descriptions: PCI Devices 2.1 SATA Registers (Device 18, Function 0) Note: Some SATA functions are controlled by, and associ at ed with, certain PCI configuration registe rs in the SMBus/ACPI device. For [...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 14 Register Name Offset A ddress Serial ATA Capability Re gister 0 70h Serial ATA Capability Re gister 1 74h IDP Index 78h IDP Data 7Ch PHY Port0 Control 88h PHY Port1 Control 8Ch PHY Port2 Control 90h PHY Port3 Contro[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 15 Status - RW - 16 bits - [PCI_Reg:06h] Field Name Bits Default Description Reserved 2:0 Reserved. Interrupt Status 3 0b Interrupt status bit. Complies with the PCI 2.3 specific ation. Capabilities List 4 1b Rea d Onl[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 16 Revision ID/Class Code - R - 32 bits - [PCI_Reg:08h] Field Name Bits Default Description Note: This field is only writeable when PCI_Reg:40h[0] is set. Sub-Class Code Program Interface Controller T ype 01 8F IDE 06 [...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 17 Base Address 2 - RW - 32 bits - [PCI_ Reg:18h] Field Name Bits Default Description Resource Type Indicator 0 1b T his bit is wired to 1 to indicate that the base address field in this register maps to I/O space. Res[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 18 Min_gnt - R - 8 bits - [PCI_Reg :3Eh ] Field Name Bits Default Description Minimum Grant 7:0 00h This register specif ies the de sired settings for how long of a burst the SATA controller needs . T he value specifie[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 19 MSI Control - RW- 32 bits - [PCI_ Reg : 50h] Field Name Bits Default Description Capability ID 7:0 05h Read-Only. Capability ID. It indicates that th is is and MSI capability ID. Capability Next Pointer 15:8 70h Rea[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 20 PCI Power Management Control And St atus - RW- 16 bits - [P CI_Reg :64h] Field Name Bits Default Description Power State 1:0 00b This field is used both to determine the curre nt power state of the HBA and to set a [...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 21 PHY Port0 Control - RW- 32 bits - [PCI _Reg:88h] Field Name Bits Default Description Port0 PHY 23:0 B40014h PHY port0 fine-tune register. TX main driver swing 4:0 10100b Port0 Tx drivin g swing[4:0] is valid for SAT[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 22 PHY Port1 Control - RW- 32 bits - [PCI _Reg:8Ch] Field Name Bits Default Description TX pre-emphasis driver swing 7:5 000b Port1 Tx driving swing[7:5] is valid for b oth SATA 3G and 1.5G. It sets the TX pre-emphasis[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 23 PHY Port3 Control - RW- 32 bits - [PCI _Reg:94h] Field Name Bits Default Description Port3 PHY 23:0 B40014h PHY port3 fine-tune register. TX main swing 4:0 10100b Port3 Tx driv ing swing[4:0] is valid at SATA 1.5G. [...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 24 2.1.2 BAR0/BAR2/BAR1/BAR3 Registers (SATA I/O Register for IDE mode) BAR0/BAR2 uses 8 bytes of I/O spac e. BAR0 is used for Primary chann el and BAR2 is used for Second ary channel during IDE native mode. BAR1/BAR3 [...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 25 Bus-master IDE Status - RW - 8 bits - [IO_Reg: BAR4 + 0 2/0Ah ] Field Name Bits Default Description Bus Master Active 0 0b Bus Master IDE active. T his bit is set to 1 when bit 0 in the Bus Master IDE command addres[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 26 HBA Capabilities – R - 32bi ts [Mem _reg: ABAR + 00h] Field Name Bits Default De scription Number of Ports(NP) 4:0 00011b 0’s based valu e indicating the maximum number of ports supported by the HBA silicon. A m[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 27 HBA Capabilities – R - 32bi ts [Mem _reg: ABAR + 00h] Field Name Bits Default De scription Supports Port Multiplier (SPM) 17 1b Indicates whether the HBA ca n support a Port Multiplier. When set, a Port Multiplier[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 28 HBA Capabilities – R - 32bi ts [Mem _reg: ABAR + 00h] Field Name Bits Default De scription Supports Native Command Queu ing (SNCQ) 30 1b Indicates whether the HBA su pports Serial ATA native command queuing. If se[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 29 Global HBA Control – RW - 32bits [Mem_reg: ABAR + 0 4h] Field Name Bits Default De scription AHCI Enable (AE) 31 0b When set, indicates that communication to the HBA shall b e via AHCI mechanisms. This can be used[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 30 Command Completion Coalescing Control(CCC_CTL) - RW – 32 bits [M em_reg: ABAR + 14h] Field Name Bits Default De scription CCC Interrupt (INT) 7:3 1Fh Read Only Specifies the interrupt used by the CCC featur e. Thi[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 31 2.1.4.2 Port Registers (On e Set Per Port) The algorithm for the software to det ermine the offset is as follo ws: • Port offset = 100h + (PI Asserted Bit Position * 80h) Register Name Offset Address Port-N Comman[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 32 Port-N FIS Base Address Upper –RW – 32 bi ts [Mem_reg : ABAR + port offset + 0Ch] Field Name Bits Default De scription FIS Base Address Upper (FBU) 31:0 0000_ 0000h Indicates the upper 32-bits for the receive d [...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 33 Port–N Interrupt Status - RW - 32 bits [Mem_reg: ABA R + po rt offset + 10h ] Field Name Bits Default De scription Host Bus Data Error Status (HBDS) 28 0b Indicates that the HBA encountered a d ata error (uncorrec[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 34 Port-N Interrupt Enable - RW -32 bits [Mem_reg: ABAR + port offset + 14h ] Field Name Bits Default De scription Cold Presence Detect Enable (CPDE) 31 0b When set, GHC.IE is set, and P0S.CPDS is set, the HBA shall ge[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 35 Port-N Command and Status - R - 32 bits [Mem _r eg: ABAR + port offs et + 18h] Field Name Bits Default De scription Current Command Slot (CCS) 12:8 00h T his field is valid when P0CMD.ST is set to ‘1’ and shall [...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 36 Port-N Command and Status - R - 32 bits [Mem _r eg: ABAR + port offs et + 18h] Field Name Bits Default De scription Device is ATAPI (ATAPI) 24 0b RW When set to ‘1’, the connected device is an ATAPI device. This[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 37 Port-N Command and Status - R - 32 bits [Mem _r eg: ABAR + port offs et + 18h] Field Name Bits Default De scription Interface Communication Control (ICC) 31:28 0h RW This field is used to control power management st[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 38 Port-N Task Fike Data – R – 32 bits [Mem_reg : ABAR + port offset + 20h ] Field Name Bits Default De scription Status (STS) 7:0 7Fh Contains the latest copy of the ta sk file status register. Fields of note in t[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 39 Port-N Serial ATA Status – R – 32 bits [Mem_r eg: ABAR + port offset + 28h ] Field Name Bits Default De scription Interface Power Management (IPM) 11:8 0h Indicates the current interface state: 0h Device not pre[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 40 Port-N Serial ATA Control – RW – 32 bi ts [Mem _reg: ABAR + port of fset + 2Ch] Field Name Bits Default De scription Interface Power Management Transitions Allowed (IPM) 11:8 0h Indicates which power states t he[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 41 Port-N Serial ATA Error – RW – 32 bits [Mem_reg: ABAR + por t offset + 30h] Field Name Bits Default De scription ERROR 15:0 0000h T he ERR field contains error information for use by host software in determining[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 42 Port-N Serial ATA Error – RW – 32 bits [Mem_reg: ABAR + por t offset + 30h] Field Name Bits Default De scription Diagnostics (DIAG) 31:16 0000h Contains diagn ostic error information for use by diagnostic softwa[...]

© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 43 Port-N Serial ATA Activ e – RW – 32 bits [Mem _reg: ABAR + port offset + 34 h] Field Name Bits Default De scription Device Status (DS) 31:0 00000000h This field is bit significant. Each bit corresponds to the TA[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 44 2.2 OCHI USB 1.1 and EH CI USB 2.0 Controllers Note: Some USB functions are cont rolled by, and associat ed with, certain PCI confi guration registers in the SMBus/ACPI device. For more information refer to sectio[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 45 Register Name Offset Address Device / Vendor ID 00h Command 04h Status 06h Revision ID / Class Cod e 08h Miscellaneous 0Ch BAR_OHCI 10h Subsystem Vendor ID / Subsystem ID 2Ch Capability Pointer 34h Interrupt Line [...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 46 Device / Vendor ID – R - 32 bits - [PCI _Reg : 00h] Field Name Bits Default Description DEV_ID 31:16 Function 0: 4387h Function 1: 4388h Function 2: 4389h Function 3: 438Ah Function 4: 438Bh Device ID Command ?[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 47 Status – R - 16 bits - [PCI _Reg : 06h] Field Name Bits Default Description Master Data Parity Error 8 0b T his bit is set only when three conditions are met: 1) the bus agent asserted PERR# itself (on a read) o[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 48 Bar_OHCI – RW - 32 bits - [PCI_ Reg : 10h] Field Name Bits Default Description PM 3 0b Prefetch memor y. A constant va lue of ‘0’ indicates that there is no support for “prefetchable memory”. Read Only. [...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 49 Config Timers / MSI Disable (OHCI0 only ) – RW - 16 bits - [PCI_Reg : 40h] Field Name Bits Default Description MSI Disable 12:8 00h W hen these bits are set MSI capabilit y will be disabled for the corresponding[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 50 Over Current Control 1 (OHCI0 only ) – R - 32 bits - [PCI_Reg : 58h] Field Name Bits Default Description Port5 OverCurrent Control 23:20 Fh The register is to control the OverCurrent pin mapp ing for Port-5. The[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 51 Target Timeout Control (OHCI0 only ) – RW - 32 bits - [PCI_ Reg : 74h] Field Name Bits Default Description Retry counter 7:0 FFh Counter to control the purge of the delay queue when the host controller does not [...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 52 Register Name Offset Address HcBulkCurrentED 2Ch HcDoneHead 30h HcFmInterval 34h HcFmRemaining 38h HcFmNumber 3Ch HcPeriodicStart 40h HcLSThreshold 44h HcRhDescriptorA 48h HcRhDescrip torB 4Ch HCRhStatus 50h HcRhP[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 53 HcControl - 32 bits - [MEM_Reg : 04h ] Field Name Bits Default HCD HC Description IE 3 0b RW R IsochronousEnable This bit is used by HCD to enable/disabl e processing of isochronous Eds. While processing the perio[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 54 HcControl - 32 bits - [MEM_Reg : 04h ] Field Name Bits Default HCD HC Description IR 8 0b RW R InterruptRouting This bit determines the rout ing of interrupts generate d by events registered in HcInterruptStatu s.[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 55 HcCommandStatus - 32 bits - [MEM_Reg : 08h] Field Name Bits Default HCD HC Description CLF 1 0b RW RW ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. It is set by HCD [...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 56 HcInterruptStatus – RW - 32 bits - [MEM_Reg : 0Ch ] Field Name Bits Default HCD HC Description SO 0 0b RW RW SchedulingOve rrun This bit is set when the USB schedule for the current Frame overruns and after the [...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 57 HcInterruptEnable - 32 bits - [MEM_ Re g : 10h] Field Name Bits Default HCD HC Description RD 3 0b RW W 0 - Ignore 1 - Enable interrupt generati on due to Resume Detect. UE 4 0b RW RW 0 - Ignore 1 - Enable interru[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 58 HcPeriodCurrentED - 32 bits - [MEM_Reg : 1Ch] Field Name Bits Default HCD HC Description Reserved 3:0 Reserved PCED 31:4 0000000 h R RW PeriodCurrentED This is used by HC to point to the head of one of the Periodi[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 59 HcBulkCurrentED - 32 bit s - [MEM_ Reg : 2Ch] Field Name Bits Default HCD HC Description BCED 31:4 0000000 h RW RW BulkCurrentED This is advanced to the next ED after the HC has served the present one. HC continue[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 60 HcFmRemaining - 32 bit s - [MEM_ Reg : 38h] Field Name Bits Default HCD HC Description FR 13:0 0000h R RW FrameRemaining This counter is decremented at each bit time. W hen it reaches zero, it is reset by loading [...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 61 HcRhDescriptorA - 32 bi ts - [MEM _Reg : 48h] Field Name Bits Default HCD HC Description NDP 7:0 02h R R NumberDownstreamPorts These bits specify the number of downstream ports supported by the Root Hub. PSM 8 0b [...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 62 HcRhDescriptorB - 32 bi ts - [MEM _Reg : 4Ch] Field Name Bits Default HCD HC Description DR 15:0 0000h RW R DeviceRemovable Each bit is dedicated to a port of the Root Hub. When cleared, the attached device is rem[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 63 HcRhStatus - 32 bits - [M EM_Reg : 50h] Field Name Bits Default HCD HC Description LPSC 16 0b RW R (Read) LocalPow erStatusChange The Root Hub does not support the local po wer status feature; thus, this bit is al[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 64 HcRhPortStatus - 32 bits - [MEM_Reg : 50h+4*(1:N DP)] Field Name Bits Default HCD HC Description PES 1 0b RW RW (Read) PortEnableStatus This bit indicates whether the port is enable d or disabled. The Root Hub may[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 65 HcRhPortStatus - 32 bits - [MEM_Reg : 50h+4*(1:N DP)] Field Name Bits Default HCD HC Description PRS 4 0b RW RW (Read) PortResetStatus When this bit is set by a write to SetPortRese t, port reset signaling is asse[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 66 HcRhPortStatus - 32 bits - [MEM_Reg : 50h+4*(1:N DP)] Field Name Bits Default HCD HC Description CSC 16 0b RW RW ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. The HCD writes a [...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 67 standard OpenHCI descriptor-ba sed accesses. The em ulation code sets up the appropriate Endpoi nt Descriptors and Transfe r Descriptors that cause data to be sent to or re ceived from a USB keyboard/mouse using t[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 68 2.2.2.3 Programming Interface The following modification is needed for t he HcRevision register: Table 2-1 HcRevision Register HcRevision - 32 bits Field Name Bits Res et HCD HC De scription Revision 7:0 10h R R T[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 69 Table 2-4 HceInput Registers HceInput – RW - 32 bits Field Name Bits Default Description InputData 7:0 00h This register holds data that is written to I/O ports 60h and 64h. Reserved 31:8 Reserved I/O data that [...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 70 HceControl Register Table 2-7 HceControl Register HceControl - 32 bits Field Name Bits Reset Description EmulationEnable 0 0b When set to 1, t he HC is enabled for legac y emulation. The HC decodes accesses to I/O[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 71 Base Address – BAR_EHCI 10h Subsystem ID / Subsystem Vendor ID 2Ch Capability Poin ter 34h Interrupt Line 3Ch EHCI Misc Control 50h Serial Bus Release Number – SBRN 60h Frame Length Adjustment – FLADJ 61h PM[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 72 Status – R - 16 bits - [PCI _Reg : 06h] Field Name Bits Default Description Reserved 2:0 Reserv ed Interrupt Status 3 0b This bit reflects the state of the interrupt in the device/function. Only when the Interru[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 73 Miscellaneous – RW - 32 bits - [PCI_Reg : 0Ch] Field Name Bits Default Description Header Type 23:16 00h T his field identifies the layout of the second part of the predefined header (begin ning at byte 10h in C[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 74 Interrupt Line - RW - 32 bits - [PCI_ Reg : 3Ch] Field Name Bits Default Description Interrupt Line 7:0 00h The Interrupt Line is a fiel d used to communicate interrupt line routing information. T he register is r[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 75 EHCI Misc Control – RW - 32 bits - [PCI_Reg : 50h ] Field Name Bits Default Description Disable Async QH Cache on OUT xfer 25 0b Set to 1 to disable async QH/QT D cache during OUT xfer. Disable Async Data Cache [...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 76 PME Control – RW - 32 bits - [PCI_R eg : C0h] Field Name Bits Default Description DSI 21 0b Read only. The Device Specific Initialization bit in dicates whether special initialization of this function is req uir[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 77 PME Data / Status – RW - 32 bits - [PCI _Reg : C4h] Field Name Bits Default Description B2_B3# 22 1b Read only. The state of this bit determines the action that is to occur as a direct result of programming the [...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 78 DBUG_PRT Control – R - 32 bits - [PCI_Reg : E4h ] Field Name Bits Default Description Bar # 31:29 1h A 3-bit field, which indicates which one of the possible 6 Base Address Register offsets, contains the Deb ug [...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 79 USBLEGCTLS TS – RW - 32 bits - [PCI_Reg : EECP + 04h] Field Name Bits Default Description SMI on OS Ownership Enable 13 0b When this bit is a one AND the OS Ownership Change bit is one, the host controller will [...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 80 CAPLENGTH – R - 8 bits - [MEM_ Reg : 00h] Description This register is used as an offset to add to register base to find the beginning of the Operational Re gister Space. Default value = 20h. HCIVERSION – R - [...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 81 HCSPARAMS – R - 32 bits - [MEM_ Reg : 04h] Field Name Bits Default Description Reserved 19:17 These bits are reserve d and should be set to zero. Debug Port Number 23:20 1h Optional. This register identifies wh [...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 82 HCSP-PORTROUTE – R - 60 bits - [M EM_Reg : 0Ch] Description This optional field is valid only if Port Routing Rules field in the HCSPA RAMS register is set to a one. This field is a 15-element nibble array (each[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 83 USBCMD – RW - 32 bits - [EOR_ Reg : EHCI_EOR + 00h ] Field Name Bits Default Description Host Controller Reset (HCRESET) 1 0b T his control bit is used by software to reset the host controller. The effects of th[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 84 USBCMD – RW - 32 bits - [EOR_ Reg : EHCI_EOR + 00h ] Field Name Bits Default Description Asynchronous Schedule Park Mode Count (Optional) 9:8 00b If the Asynchronous Park Capabil ity bit in the HCCPARAMS registe[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 85 USBSTS - RW - 32 bits - [E OR_Reg : EHCI_EO R + 04h] Field Name Bits Default Description Port Change Detect 2 0b Port Change Detect. The Host Controller sets this bit to a one when any port for which the Port Owne[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 86 USBINTR –RW - 32 bits - [E OR_Reg : EHCI_EOR + 08h] Field Name Bits Default Description USB Interrupt Enable 0 0b When this bit is a one, and the USBINT bit in the USBSTS register is a one, the host controller w[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 87 ASYNCLISTADDR –RW - 32 bits - [EOR_ Reg : EHCI_EOR + 18h] Field Name Bits Default Description Reserved 4:0 These bits are reserved an d their value h as no effect on operation. Link Pointer Low (LPL) 31:5 00h Th[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 88 PORTSC (1-N_PORTS) – RW - 32 bits - [EOR_Reg : EHCI_E OR + (44h~68h )] Field Name Bits Default Description Force Port Resume 6 0b 1 = Resume detected/driven on port. 0 = No resume (K-state) detected/driven on po[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 89 PORTSC (1-N_PORTS) – RW - 32 bits - [EOR_Reg : EHCI_E OR + (44h~68h )] Field Name Bits Default Description Port Reset 8 0b 1 = Port is in Reset. 0 = Port is not in Reset. When software writes a one to this bit ([...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 90 PORTSC (1-N_PORTS) – RW - 32 bits - [EOR_Reg : EHCI_E OR + (44h~68h )] Field Name Bits Default Description Port Owner 13 1b This bit unconditionally g oes to a 0b when the Configured bit in the CONFIGFLAG regist[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 91 USB PHY Status 0 – RW - 32 bits - [EOR_Reg : EHCI_EOR + 88h] Field Name Bits Default Description PORT0_PHYStatus 7:0 00h Read only. PHY Status of Port0 PORT1_PHYStatus 15:8 00h Read only. PHY Status of Port1 POR[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 92 UTMI Control – RW - 32 bits - [EO R_ Reg: EHCI_EOR + 94h] Field Name Bits Default Description VBusy 17 0b RO – T o block software write to [16:8] when port r outer is updating the field. Reserved 31:18 Reserv [...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 93 Control register (EHCI_PCI_CF G xE4[28:16], default = 0E0h) , regardless of the value in register (MEM_Reg: 00h). Registers Name Offset Address Control / Status DBase + 00h USB PIDs DBase + 04h Data Buffer DBase +[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 94 Control / Status – RW - 32 bits - [DBUG_Reg : DBase + 00h] Field Name Bits Default Description Enabled 28 0b This bit is a one if t he debug port is enabled for operation. Software can clear this by writing a ze[...]

© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 95 Data Buffer – RW - 64 bits - [DBug_Reg : DBase + 08h/0Ch ] Field Name Bits Default Description Data Buffer 63:0 00000 000 _ 00000000 h The least significant byte is accessed at offse t 08h and the most significa[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 96 2.3 SMBus Module and ACPI Block (Device 20, Function 0) Some registers in the SMBus/ACPI PC I configuration space (PCI_reg, see section 2.3.1 ) contain control s and settings for a number of blocks withi[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 97 2.3.1 PCI Configuration Registers and Extended Registers 2.3.1.1 PCIE Configuration Registers Register Name Configuration Offset VendorID 00h DeviceID 02h Command 04h STATUS 06h Revision ID/Class Code 08[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 98 Register Name Configuration Offset IDE_GPIO_In A4h GPIO_48_47_46_37_Cntrl A6h GPIO_12_to_4_Cntrl A8h SATA_Cntrl ACh SataIntMap AFh MSI_Mapping_Capabi lity B0h PcilntGpio BCh UsbIntMap BEh IoDrvSth C0h I2[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 99 Command- RW - 16 bits - [PCI_Reg: 04h] Field Name Bits Default Description Parity Error Response 6 0b This bit controls the device’s response to parit y errors. When the bit is set, the device must tak[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 100 Revision ID/Class Code - R - 32 bits - [PCI_Reg: 08h] Field Name Bits Default Description RevisionID 7:0 11h / 12h / 13h This field reflects the ASIC revision. 11h : For ASIC revision A11 12h : For ASIC[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 101 Base Address 2- R - 3 2 bits - [P CI_Reg: 18h] Field Name Bits Default Description Base Address 2 register Base Address 3- R - 3 2 bits - [P CI_Reg: 1Ch] Field Name Bits Default Description Base Address[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 102 Interrupt Line - R - 8 bits - [PCI_Reg : 3Ch] Field Name Bits Default Description Interrupt Line 7:0 00h This module does not generate interrupt. T his register is hardcoded to 0. Interrupt Line registe[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 103 DmaLimit- RW - 8 bits - [ P CI_Reg: 42h] Field Name Bits Default Description DmaBurstLimit 6:0 00h Enables the amount of burst data the legacy DMA engine c an sustain before it should give up the intern[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 104 GPIO_52_to_49_Cn trl - RW – 1 6 bits - [PCI_Reg: 50h] Field Name Bits Default Description GPIO_Out 3:0 0h Write 1 to set and 0 to clear each of the GPIO port; providing the corresponding enable bits ([...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 105 GPIO_64_to_61_Cn trl - RW – 1 6 bits - [PCI_Reg: 56h] Field Name Bits Default Description GPIO_64_to_61_Cntrl register ASFSMbusIoBase- RW - 16 bits - [PCI_Reg : 58h] Field Name Bits Default Descriptio[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 106 SmartPowerControl1B - RW – 8 bits - [PCI_Reg: 5Dh] Field Name Bits Default Description CheckVIN0 0 0b If SmartVoltEnable is set and this bit is also set, the SmartPower function will only assert Smart[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 107 MiscEnable- RW - 8 bits - [PCI_Reg : 6 2h] Field Name Bits Default Description USB_Fast_SMI_Disable 5 0b For K8 s ystem, legacy USB can request SMI# to be sent out early before IO completion. Some appli[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 108 Features Enable- RW - 32 bits - [P CI_Reg: 64h] Field Name Bits Default Description Smi_Gevent_En 12 0b Enable all the events with the capability of doing both SMI# and SCI to SMI# assertion. If enabled[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 109 UsbEnable - RW - 8 bits - [PCI_ Reg: 68h] Field Name Bits Default Description OHCI_2_enable 3 1b Set to 1 to enable OHCI_2 OHCI_3_enable 4 1b Set to 1 to enable OHCI_3 OHCI_4_enable 5 1b Set to 1 to ena[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 110 TestMode- RW - 16 bits - [PCI_ Reg: 6C] Field Name Bits Default Description DMA_Timing 0 0b To be used by BIOS only; when set, legac y DMA will insert 1 extra idle clock in bet ween requests. Software s[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 111 GPIO_69_68_66_65_Cn trl - RW – 16 bits - [PCI_Re g: 7Eh] Field Name Bits Default Description GPIO_Out_En# 7:4 Fh GPIO output port enable for each of the GPIO port 0: Output = GPIO_Out 1: Output = tris[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 112 SmartPowerControl2A - RW – 8 bits - [PCI_Reg: 98h] Field Name Bits Default Description CheckLpc 0 0b If SmartVoltEnable2 is set and this bit is also set, the SmartPower2 function will only assert Smar[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 113 SmartPowerControl2C - RW – 8 bits - [PCI_Reg: 9Ah] Field Name Bits Default Description SmartVoltEnable2 7 0b Enab le bit for the Sm artPower2 function. When set, the logic will monitor the logic (defi[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 114 GPIO_12_to_4_Cntrl – RW – 32 bits - [PCI_ Reg: A8h] Field Name Bits Default Description GPIO_Out 7:0 00h Write 1 to set and 0 to clear each of the GPIO port providing the corresponding bits [15:8 ],[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 115 SATA_Cntrl - RW – 16 bits - [PCI_Reg: ACh] Field Name Bits Default Description ExtendIntrToWakeTime 18:16 000b This is used in K8 system to extend the interrupt break event status. Whenever there is a[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 116 UsbIntMap - RW - 16 bits - [PCI_ Reg: BEh] Field Name Bits Default Description Reserved 15:14 00b UsbIntMap register Encoding: 000 - INTA#, 001 - INTB#, 010 - INTC#, 011 - INTD#, 100 - INTE#, 101 - INTF[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 117 IoDrvSth - RW - 32 bits - [PCI_ Reg: C0h] Field Name Bits Default Description For control with only t wo bits, one can assume the four drive strength settings (correspo nding to 25, 50, 75, and 100% res[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 118 I2CShadow1- RW - 8 bits - [PCI_ Reg: D4h] Field Name Bits Default Description I2CShadow1 register I2Cshadow2- RW - 8 bits - [PCI_Reg: D5h] Field Name Bits Default Description Read/Write ShadowPort2 0 0b[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 119 MwaitSts- R - 8 bits - [P CI_Reg : F7h] Field Name Bits Default Description Mwait_cpu1_sts 1 0b Set to 1 b y MWAIT wi th addr[19:18] = Mwai t_physical _ID[3:2] and addr[17:16] = Mwait_logical_ID[1:0]. C[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 120 2.3.1.2 Extended Registers Register Name Configuration Offset AudioPortConfig 00h AudioGpioControl 04h AudioPortConfig- RW - 32 bits - [E xtend_ Reg: 00h] Field Name Bits Default Description AzPort0Conf[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 121 AudioGpioControl – RW - 32 bits - [Exten d_Reg: 04h] Field Name Bits Default Description AudioGpioOut0OeB 0 1b When ACZ_SDIN0 is configured as GPIO, this bit represents the output enable. 1 – Trista[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 122 AudioGpioControl – RW - 32 bits - [Exten d_Reg: 04h] Field Name Bits Default Description AzRstGpioOut 20 0b When AZ_RST # is configured as GPIO, this bit represents the output value if the output is e[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 123 2.3.2 SMBus Registers Register Name Offset Address SMBusStatus 00h SMBusSlaveStatus 01h SMBusControl 02h SMBusHostCmd 03h SMBusAddress 04h SMBusData0 05h SMBusData1 06h SMBusBlockData 07h SMBusSlaveCont[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 124 SMBusSlaveStatus - RW - 8 bits - [SM BUS:01h] Field Name Bits Default Description Reserved 7:6 00b SMBusControl - RW - 8 bi ts - [SM BUS:02h] Field Name Bits Default Description InterruptEnable 0 0b Ena[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 125 SMBusSlaveControl - RW - 8 bits - [S MBUS:08h] Field Name Bits Default Description SlaveEnable 0 0b Enable the gen eration of an interrupt or resume event upon an external SMBus master generating a tran[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 126 2.3.3 Legacy ISA and ACPI Controller 2.3.3.1 Legacy Block Regis ters There are two sets of registers in the ACPI/SMBus module. The first set is in the PCI configuration space and the registers cont rol [...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 127 Register Name Offset A d dress Dma2_Ch6Cnt CAh Dma2_Ch7Addr CCh Dma2_Ch7Cnt CEh Dma_Status D0h Dma_WriteRequest D2h Dma_WriteMask D4h Dma_WriteMode D6h Dma_Clear D8h Dma_Clear DAh Dma_ClrMask DCh Dma_Cl[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 128 Dma_Status- RW – 8 bits - [IO_Reg: 0 8h] Field Name Bits Default Description Dma_Status 7:0 00h Returns status when read; command for write Dma_Status register Dma_WriteReques t- RW – 8 bits - [IO_R[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 129 IntrCntrl1Reg2- RW – 8 b its - [IO_Reg: 21h] Field Name Bits Default Description IntrCntrl1Reg2 7:0 00h IRQ0 – IRQ7: Read IMR Write ICW2, ICW3, ICW4, OCW1 IntrCntrl1Reg2 register IMCR_Index- RW – [...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 130 Tmr1CntrlWord - RW – 8 bits - [IO_Re g: 43h] Field Name Bits Default Description CntDownSelect 0 0b 0 – Binary countdo wn 1 – BCD countdown ModeSelect 3:1 000 b 000 – Assert s OUT signal at end [...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 131 RtcDataPort - RW – 8 bits - [IO_Reg: 71h ] Field Name Bits Default Description RtcDataPort AlternatRtcAddrPort - RW – 8 bits - [IO_Reg: 72h] Field Name Bits Default Description AlternatRTCAddrPort 7[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 132 Dma_Page_Reserv ed4- RW – 8 bits - [IO_Reg: 8 8h] Field Name Bits Default Description Dma_Page_Reserved4 7:0 00h Dma Pag e Reserved4 register Dma_Page_Reserved4 re gister Dma_PageCh6 - RW – 8 bits -[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 133 IntrCntrl2Reg1- RW – 8 b its - [IO_Reg: A0h] Field Name Bits Default Description IntrCntrl2Reg1 7:0 00h IRQ8 – IRQ15: Read IRR, ISR Write ICW1, OCW2, OCW3 IntrCntrl2Reg1 register IntrCntrl2Reg2- RW [...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 134 Dma_Ch7Cnt - RW – 8 bits - [IO_ Reg: CEh] Field Name Bits Default Description Dma2_Ch7Cnt 7:0 00h Channel 7 DM A base and current count Dma2_Ch7Cnt register Dma_Status - RW – 8 bits - [IO_R eg: D0h][...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 135 NCP_Error - RW – 8 bits - [IO_Reg: F0h] Field Name Bits Default Description NCP_Error register: In addition to the WarmBoot function, writing to this port will assert IGNNE# if FERR# is true. If FERR#[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 136 Pci_Intr_Data - RW – 8 bits - [IO_Reg: C01h ] Field Name Bits Default Description Pci_Intr_Data 7:0 00h PCI redirecti on regi ster; map PCI interrupt addressed by Pci_Intr_Index to a PIC IRQ [7:4] –[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 137 GpmPort - RW – 8 bits - [ I O_Re g: C52h] Field Name Bits Default Description GpmPort register Isa_Misc - RW – 8 bits - [IO_Reg: C6Fh] Field Name Bits Default Description Reserved 5:0 00h FlashRomEn[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 138 IdRegister - R – 8 bits - [IO_Reg: 0 0h] Field Name Bits Default Description IdRegister 7:0 00h IdRegister register TempStatus - R – 8 bits - [IO_ Reg : 02h] Field Name Bits Default Description TALE[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 139 2.3.3.1.3 System Reset Registe r (IO CF9) Note: Refer to PM IO reg x85 for a detailed description. This re gister has been desig ned to be dual-port accessible. 2.3.3.2 Power Management (PM) Registers T[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 140 Register Name Offset Address AcpiPmaCntBlkLo 2Ch AcpiPmaCntBlkHi 2Dh AcpiSsCntBlkLo 2Eh AcpiSsCntBlkHi 2Fh GEvtConfig0 30h GEvtConfig1 31h GPMConfig0 32h GPMConfig1 33h GPMConfig2 34h GPMConfig3 35h GEv[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 141 Register Name Offset Address SOS3ToS5Enable2 78h SOS3ToS5Enable3 79h NoStatusControl0 7Ah NoStatusControl1 7Bh MiscEnable7C 7Ch DprSlpVrMinTime 7Dh SMAF0 80h SMAF1 81h SMAF2 82h SMAF3 83h WakePinCntl 84[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 142 MiscControl - RW – 8 bits - [PM_R eg: 00h] Field Name Bits Default Description Reserved 3 0b SmiReq 4 0b Software initiated SMI#. When set, SB will update bit [4] of the MiscStatus and issue SMI#. Res[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 143 SmiWakeUpEv entStatus2 - RW – 8 bits - [PM_Re g : 06h] Field Name Bits Default Description SmiWakeUpEventStatus2 register. SmiWakeUpEv entStatus3 - RW – 8 bits - [PM_Re g : 07h] Field Name Bits Defa[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 144 PmTmr1CurValue - R – 8 bits - [PM_Reg: 0Ch] Field Name Bits Default Description PmTmr1CurValue 5:0 - Current va lue of decrementin g counter Reserved 7:6 00b PwrLedExtEv ent - RW – 8 bits - [PM_Reg:[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 145 AcpiEn - RW – 8 bits - [PM_Reg: 10 h] Field Name Bits Default Description EOSEnale 0 0b Set 1 by software and clear by hardware. This bit needs to be set in order to generate SMI#/SCI RTC_En_En 1 0b R[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 146 Programlo0RangeLo - RW – 8 bits - [PM_Reg : 14 h] Field Name Bits Default Description ProgramIo0Mask 3:0 0h These four bits are us ed to m ask the least 4 bits of the 16 bit I/O. If bit [3] is set, th[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 147 ProgramIo2RangeLo - RW – 8 bits - [PM_Reg: 18h] Field Name Bits Default Description ProgramIo2RangeLo register. ProgramIo2RangeHi - RW – 8 bits - [PM_Reg: 19h] Field Name Bits Default Description Pr[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 148 IOMonitorStatus - RW – 8 bits - [PM_Reg: 1Dh] Field Name Bits Default Description MouseKbMonito rStatus 3 - Mouse/keyboard statu s bit; write 1’ b1 to clear the sta tus bit ProgramIo3Status 4 - Prog[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 149 AcpiPm1CntBlkHi - RW – 8 bits - [PM _Reg: 23h] Field Name Bits Default Description AcpiPm1CntBlkHi register. AcpiPmTmrBlkLo - RW – 8 bits - [PM_Re g: 24h] Field Name Bits Default Description Reserve[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 150 AcpiSmiCmdLo - RW – 8 bits - [PM_Reg: 2Ah] Field Name Bits Default Description AcpiSmiCmdLo 7:0 00h These bits define the least significant byte of the 16 bit I/O base address of the ACPI SMI Command [...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 151 GPMConfig0 – RW – 8 bits - [PM_Reg: 32h] Field Name Bits Default Description ExtEvent0Config 1:0 00b These tw o bits config ure ExtEvent0 00 ACPI Event (trigger SCIOUT or SMI# depending on SCI_EN bi[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 152 GPMConfig2- RW – 8 bits - [PM_Reg: 34h] Field Name Bits Default Description Gpio0Config 1:0 00b These two bits configure Gpio0 or WAKE# 00 ACPI Event (trigger SCIOUT or SMI# depending on SCI_EN bit) 0[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 153 GEvtLevelConfig - RW – 8 bits - [PM_ Reg : 36h] Field Name Bits Default Description GEvtLevelConfig 7:0 00h GEVENT input level configuration 1 - Rising edge trigger 0 - Falling edge trigger GEvtLevelC[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 154 GPMLevelConfig1 - RW – 8 bits - [P M_Reg: 38h] Field Name Bits Default Description SataSciLevelConfig 7 0b SataSci input level configuration 1 – Rising edge trigger 0 – Falling edge trigger GEvtSt[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 155 OthersConfig- RW – 8 bits - [PM_Reg : 3Ch] Field Name Bits Default Description Ac97Config 7:6 00b These two bits config ure AC97 PME 00 ACPI Event (trigger SCIOUT or SMI# depending on SCI_EN bit) 01 A[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 156 AD23_Pull_UpB - RW – 8 bits - [PM_Reg: 41h ] Field Name Bits Default Description AD23_Pull_UpB 0 0b This bit controls integrated pull-up for AD[23]. 0: Enable 1: Disable Reserved 7:1 0000_000b AD23_Pu[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 157 TPRESET2 - RW – 8 bits - [PM_Reg: 52h] Field Name Bits Default Description PopUpReqHoldEn (Applicable to ASIC revision A21 and above) 7 0b Setting this bit to 1 will cause the pop-up request from the [...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 158 Reserved – 8 bits - [PM_Reg: 57h ] Field Name Bits Default Description Reserved 7:0 00h Reserved Reserved – 8 bits - [PM_Reg: 58h ] Field Name Bits Default Description Reserved 7:0 00h Reserved Misc[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 159 SmiSciSts2 - RW – 8 bits - [PM_Reg: 5Ch] Field Name Bits Default Description ExtEvent0Status 0 0b This bit indicat e s the SMI# status of ExtEvent0 to SCI/Wakeup if it is configured to generate S MI# [...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 160 MwaitEnable - RW – 8 bits - [PM_Reg : 5Eh] Field Name Bits Default Description MwaitEnable register This register is used only in the P4 system. MwaitSmiSts - RW – 8 bits - [PM_Re g : 5Fh] Field Nam[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 161 SwitchVoltageTime - RW – 8 bits - [PM_Reg: 63 h] Field Name Bits Default Description SwitchVoltageTime 5:0 05h Programmabl e value (in 2us increment with 2us uncertainty) Reserved 7:6 00b SwitchVoltag[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 162 MiscEnable67 – RW – 8 bits – [PM_Re g:67 h] Field Name Bits Default Description TempPolarity 6:5 00b T emperature polarity control for THRMT RIP and TALERT respectively. 0: active low; 1; active h[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 163 WatchDogTimerBase2 – RW – 8 bits – [PM_Reg:6Eh] Field Name Bits Default Description WatchDogTimerBase2 7:0 00h WatchD ogTimer Base address [23:16] WatchDogTimerBase2 regist er WatchDogTimerBase3 ?[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 164 C4Control – RW – 8 bits – [PM_Reg:72h] Field Name Bits Default Description DPRSLPVR_delay 6:0 000_0000b This defines the delay bet ween CPU_STP# de-assertion and DPRSLPVR de-assertion in C4 state,[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 165 S0S3ToS5Enable0 – RW – 8 bits – [PM_Reg:76h] Field Name Bits Default Description S0S3ToS5Enable0 register S0S3ToS5Enable1 – RW – 8 bits – [PM_Reg:77h] Field Name Bits Default Description S0S[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 166 NoStatusControl0 – RW – 8 bits – [P M_Reg:7Ah] Field Name Bits Default Description NoStatusControl0 7:0 00h For GEVENT#[7:0] configured as PME# (wakeup function), additional setting of these bits [...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 167 SMAF1 – RW – 8 bits – [PM_Reg:81h] Field Name Bits Default Description SMAF1 register SMAF2 – RW – 8 bits – [PM_Reg:82h] Field Name Bits Default Description S1SMAF 2:0 011 b System managemen[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 168 ThermThrotCntl – RW – 8 bits – [PM_Reg :86h] Field Name Bits Default Description ThrottleControl 4:1 0000b Bit[4] Enable thermal clock throttle Bit[3:1] Throttle interval for STPCLK# de-ass ertion[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 169 LdtAgpTimeCntl – RW – 8 bits – [PM_Reg:8Ah] Field Name Bits Default Description LdtAgpTimeCntl register for ACPI C state in the K8 s ystem. StutterTime – RW – 8 bits – [PM_Reg:8Bh] Field Nam[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 170 FakeAsrEn– RW – 8 bits – [PM_Reg:8Fh] Field Name Bits Default Description MaskNbBmStsSet 5 0b When set, BmStsSet message from NB will not cause wake up from C state. MemRstDisable 6 0b When set, t[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 171 K8C1ePort - RW - 16 bits - [PM_Reg: 99:98 h] Field Name Bits Default Description K8C1ePort 15:0 0000h This register defines the 16 bit IO address fo r the K8 C1e support. In AMD K8 dual core system, whe[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 172 AutoArbDisWaitTime - R W - 8 bits - [PM_Reg: 9Fh] Field Name Bits Default Description AutoArbDisWaitTime 3:0 0h This defines the am ount of time (in 2us increment) that SB will hold ARB_DIS set after br[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 173 ProgramIo5RangeHi - RW – 8 bits - [PM_Reg: A3 h] Field Name Bits Default Description ProgramIo5RangeHi register Programlo6RangeLo - RW – 8 bits - [PM_Reg: A4 h] Field Name Bits Default Description P[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 174 PIO7654Enable - RW – 8 bits - [PM_Reg: A8h] Field Name Bits Default Description ProgramIo5Enable 1 0b Enables IO monitoring for ProgramIO5 (defined by index A2 , A3). 1 = On 0 = Off ProgramIo6Enable 2[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 175 C3Count - R – 8 bits - [PM_Reg: B4h] Field Name Bits Default Description C3Count 7:0 00h T he value shows the amount of time the CPU spends in C 3. Each increment represents approximat ely 0.39% (1/25[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 176 2.3.3.3 ACPI Registers Register Name Offset Address* Pm1Status 00h Pm1Enable 02h PmControl 00h PmaControl 00h TmrValue/ETmrValu e 00h CLKVALUE 00h PLvl2 04h PLvl3 05h PLvl4 06h AcpiSsCnt 00h EVENT_STATU[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 177 Pm1Enable - RW - 16 bits - [AcpiPm E vtBlk:02h] Field Name Bits Default Description Reserved 13:11 000b PciExpWakeDis 14 1b T his bit disables t he inputs to the PciExpWakeStatus from waking the system.[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 178 CLKVALUE - RW - 3 2 bits - [CpuControl:00h ] Field Name Bits Default Description This register is located at t he base address defined by Cpu Control PLvl2 - R - 8 bits - [CpuC ontrol:04h] Field Name Bi[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 179 EVENT_STATUS - RW - 32 bits - [AcpiGpe0Blk:00h] Field Name Bits Default Description AzaliaStatus 27 0b This bit indicat es the status from the internal HD Audio controller GPM6Status 28 0b This bit indi[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 180 SmiCmdStatus - RW - 8 bits – [Sm i Cm dBlk: 01h] Field Name Bits Default Description This register is located at the base a ddress defined by AcpiSmiCmd + offset 1.[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 181 2.3.4 WatchDogTimer Registers WatchDogTimer base address is defined in PM_Reg 6F:6Ch. Register Name Offset A d dress WatchDogControl 00h WatchDogCount 04h WatchDogControl - RW - 32 bits - [WD_Mem_Reg : [...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 182 2.3.5 ASF SM bus Host Interface Registers The ASF SM bus host register block is resid ent in the Io space whose base defined at offset 58h/59h of config space. Register Name Offset Address HostStatus 00[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 183 HostControl – RW - 8 bits - [ASF_IO: 02h] Field Name Bits Default Description PECEnable 7 0b 0: PEC disable 1: PEC enable, enable CRC checki ng when ASF HC presents as SM master and SM slave. HostComm[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 184 StatusMask0– RW - 8 bits - [ASF_IO: 0Bh] Field Name Bits Default Description Temp0StatusEnable 0 0b 1: Report T emp0 status to ASF 0: No report Temp1StatusEnable 1 0b 1: Report T emp1 status to ASF 0:[...]

© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 185 SlaveMisc- RW - 8 bits - [ASF_I O: 0 Dh] Field Name Bits Default Description KillSlave 6 0b RW Write 1 to reset Slave ASF Slave state machine LegacySensor En 7 0b RW 0: Disable Legacy Sensor 1: Enable L[...]

© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 186 2.4 IDE Controller (Device 20, Function 1) 2.4.1 PCI Configuration Registers Register Name Offset A ddress Vendor ID 00h Device ID 02h Command 04h Status 06h Revision ID/Class Code 08h Cache Line Size 0Ch Master Lat[...]

© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 187 Device ID - R - 16 bits - [PCI_Reg:02h ] Field Name Bits Default Description Device ID Register: This register holds a u nique 16-bit value assigned to a device, and combin ed with the vendor ID it identifies any PC[...]

© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 188 Status - RW - 16 bits - [PCI_Reg:06h] Field Name Bits Default Description DEVSEL- Timing 10:9 01b DEVSEL- timing – Read only bits indicating DEVSEL- timing when performing a positive decode. Since DEVSEL- is asser[...]

© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 189 Master Latency Timer - RW - 8 bits - [PCI_Reg:0Dh] Field Name Bits Default Description Reserved 2:0 0h They are not used and wired to 0. Master Latency Timer 7:3 00h Master Latency Timer. T his num ber represents th[...]

© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 190 Base Address 2 - RW - 32 bits - [PCI_ Reg:18h] Field Name Bits Default Description Reserved 31:16 0000h Reserved. Al ways read as 0’s. Base Address 2 Register (Secondar y CS0): This register identifies the base ad[...]

© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 191 Interrupt Pin - R - 8 bits - [PCI_Reg:3 Dh] Field Name Bits Default Description Interrupt Pin 7:0 01h Hard-wired to 01h. Interrupt Pin Register: This register identifies the interrupt pin a devic e uses . Since the [...]

© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 192 IDE Legacy DMA (Multi-words DMA) Timi ng Modes - RW - 32 bits - [PCI_Reg:44h] Field Name Bits Default Description IDE Legacy DMA (Multi- words DMA) Timing Modes Register: Th is register controls the IDE interface an[...]

© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 193 IDE Ultra DMA Status - R W- 8 bits - [PCI_Reg:55h] Field Name Bits Default Description IDE Ultra DMA Status Register: This register s pecifies the Ultra DMA status for primary channel. IDE Ultra DMA Mode - RW- 1 6 b[...]

© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 194 IDE Internal Control - RW- 16 bits - [PCI_R eg:62h] Field Name Bits Default Description IDE Internal PCI master request selection 0 0b Select num ber of delay cycles on internal PC I master request 0: delay two PCI [...]

© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 195 IDE Dynamic Clocking - RW- 2 0 bits - [PCI_Reg:6Ch ] Field Name Bits Default Description IDE Power Down Counter 19:0 FFFFFh The IDE po wer down counter can be programmed to shut down the IDE clock. The counter is ru[...]

© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 196 Bus-master IDE Command - RW - 8 bits - [IDE:00h] Field Name Bits Default Description Bus Master IDE Start/Stop 0 0b Bus Master IDE Start (1)/Stop (0). This bit will not be reset by interrupt from IDE device. T his m[...]

© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 197 Address (hex) Name and Function Compatibility Mode Native Mode (Offset) Read Function Write Function 1F1 Base Address 0 + 1 Error register Features register 1F2 Base Address 0 + 2 Sector Count Sector Count 1F3 Base [...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 198 2.5 AC ’97 Controller Functional Descriptions 2.5.1 Audio Registers (Device 20, Function 5) The PCI based registers for Audio are de fined accord ing to the PCI 2.1 specification and Windows 2000 requirement[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 199 CMD- RW - 16 bits - [PCI_ Reg : 04h] Field Name Bits Default Description IO Space 0 0b I/O Access Enable. Memory Space 1 0b Memor y Access Enable. Bus Master 2 0b Master Enable. Special Cycles 3 0b Hardwired t[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 200 Revision ID/Class Code - R - 32 bits - [PCI_Reg: 08h] Field Name Bits Default Description Revision ID 7:0 00h Revision ID. Class Code 31:8 04010 0h Class Co de. Revision ID/Class Code Register: This read onl y[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 201 Base Address Reg 1- RW - 32 bits – [P CI_Reg: 14h] Field Name Bits Default Description Reserved 7:4 0h Always 0; meaning t hat the IO mapped registers occupy 256 bytes. BAR1 31:8 0000_00h Base address regist[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 202 MSI Capability Register Set IDs- R – 16 bits – [PCI_Reg: 40h] Field Name Bits Default Description Capability ID 7:0 05h Rea d only. 05h indicates it is an MSI capabilit y register set. Pointer to Next ID 1[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 203 UnMask Latency Timer Expiration W - 32 bits - [PCI_Reg: 5 0h] Field Name Bits Default Description UnMask Latency Timer Expiration 0 0b W hen this bit is set to 0, latency timer register will be ignored , and A[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 204 Interrupt - RW - 32 bits - [MEM_Reg : 00h] Field Name Bits Default Description in DMA Overflow 0 0b Input Channel overflow on the next AC'97 clock - out of FIFO space. in DMA Status 1 0b Set to “1” af[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 205 Interrupt Enable- RW - 32 bits - [ME M _Re g: 04h] Field Name Bits Default Description Reserved 31:16 0000h Interrupt Enable Register: If a bit in this register is set to “1”, the corresponding interrupt i[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 206 Audio Command- RW - 32 bits - [MEM_Reg: 08 h] Field Name Bits Default Description Packed format disable 24 0b 1 - Disable packed forma t for sending data: data is sent to memory including data from Slot1 and 2[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 207 Slot Request- R - 32 bits - [MEM_Reg: 14h] Field Name Bits Default Description SLOTREQ 9:0 000h The read only bits [0:9] of this field respectively come from slot1[11:2] of AC link’s SDATA_IN 0/1/2 OR’ed t[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 208 Input DMA DT Current- R - 32 bits - [M EM_Reg: 2Ch] Field Name Bits Default Description in DMA DT current 31:0 0000_ 0 000h Pointer to the currently accessing memor y address for the input DMA. Input DMA DT Cu[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 209 Output DMA DT Size and State - R - 32 bits - [MEM_ Reg : 48h] Field Name Bits Default Description Out DMA DT size 15:0 0000h Data size of DT for Output DMA. Reserved 25:16 000h out DMA state 28:26 0h Current s[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 210 SPDIF Channel DT Current- R - 32 bit s - [MEM_ Reg: 5Ch] Field Name Bits Default Description SPDIF DT current 31:0 0000_0 000h SPDIF Channel currently accessed memor y address. SPDIF DT Current Pointer Registe[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 211 Output DMA Fifo info- R - 32 bits - [MEM_Reg: 8C h] Field Name Bits Default Description Out FIFO Used 6:0 00h Number of filled FIFO entries of output DMA. Reserved 7 0b Out FIFO Free 14:8 5Ah Number of free FI[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 212 Audio Phy Semaphore Reg- RW - 8 bi ts - [MEM _Reg: A8h] Field Name Bits Default Description Audio Phy semaphore 0 0b PHY is ready for Audio to acc ess: 0 = PHY is not ready for Audio to access. 1 = PHY is read[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 213 2.5.2 Modem Registers (Device 20, Function 6) The PCI based registers for Modem are defined ac cording to the PCI 2.1 spec and Windows 2000 requirements. 2.5.2.1 PCI Configuration Registers Register Name Offse[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 214 CMD- RW - 16 bits - [PCI_ Reg : 04h] Field Name Bits Default Description IO Space 0 0b I/O Access Enable. Memory Space 1 0b Memor y Access Enable. Bus Master 2 0b Master Enable Special Cycles 3 0b Hardwired to[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 215 Cache Line Size - RW - 8 bits - [PCI_ Reg : 0Ch] Field Name Bits Default Description Cache Line Size 7:0 00h Cach e Lien Size. Cache Line Size Register: This register speci fies the system cache line size. Lat[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 216 Subsystem ID & Subsy stem Vendor ID - W/R - 32 bits - [PCI_Reg: 2Ch] Field Name Bits Default Description Subsystem Vendor ID 15:0 0000h Subsystem Vendor ID. Subsystem ID 31:16 0000h Subsystem ID. This 4-by[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 217 MSI Message Control Register- RW - 16 bits - [PCI_Reg : 42h ] Field Name Bits Default Description Multiple Message Enable 6:4 0b Soft ware programs a 3-bit value into this field indicating the actual number of[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 218 2.5.2.2 Modem M emory M apped Registers All the AC’97 Controller modem registers are mapped to memory. Register Name Offset A ddress Interrupt 00h Interrupt Enable 04h Modem Command 08h Output Phy Status And[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 219 Interrupt - RW - 32 bits - [MEM_Reg : 00h] Field Name Bits Default Description Phy Addr mismatch 9 0b There is mismatch bet ween in Phy and out Phy address values Codec0 Not Ready 10 0b The Ac97_Phy r egisters[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 220 Modem Command - RW - 32 bits - [ M EM_Re g: 08h] Field Name Bits Default Description Modem send out through DMA2 enable 3 0b Enables sending of modem data to slot 10 on AC link using out DMA2 Modem send out th[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 221 Modem Command - RW - 32 bits - [ M EM_Re g: 08h] Field Name Bits Default Description Modem Command Register: Controls the operatio n of Audio Controller. Valu e of "1" in bit position e nables corres[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 222 Counter - R - 32 bits - [M EM_Reg : 18h] Field Name Bits Default Description Slot Counter 3:0 0h The current sl ot number (0-12) which the AC97 controller handling. Reserved 7:4 0h Bit Clock Counter 12:8 00h F[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 223 Output DMA 1/2/3 Threshold – RW - 3 2 bits - [MEM_Reg: 34h] Field Name Bits Default Description out DMA #1 State 2:0 0h Curr ent state of out DMA # 1 (Modem 1 for slot 5) [Read-only] out DMA #2 State 5:3 0h [...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 224 Output DMA2 DT Start– R - 32 bits - [MEM_Reg: 50h] Field Name Bits Default Description out DMA2 DT start 31:0 0000_0000h Pointer to t he start of data associated with current DT for the Output DMA2. Output D[...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 225 Output DMA 1/2/3 FIFO Info– R - 32 bits - [MEM_ Reg: 70h] Field Name Bits Default Description out DMA3 Used 14:10 00h Number of filled FIFO entries of Output DMA3 (FIFO size 6). Reserved 15 0b out DMA1 Free [...]

© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 226 Modem Fifo Flush– W - 32 bits - [ME M_Re g: 88h] Field Name Bits Default Description Output DMA3 Fifo Flush 2 0b Writing to this bit flushes modem output DMA3 fifo, i.e., the indexes and Used/Free counts are[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 227 2.6 HD Audio Controllers Registers Note: Some HD Audio functions are controlled by, and asso ciated with, certain PCI c onfiguration registers in the SMBus/ACPI device. For more information refer to section 2.3: SMBus Modu[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 228 PCI Command – RW – 16 bits – [PCI_Reg : 04h ] Field Name Bits Default Description Reserved 0 0b Reserved. Memory Space Enable 1 0b Enables the H D Audio controller to respond to PCI memory space access. Bus Master En[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 229 Latency Timer – R – 8 bits – [PCI_Reg : 0Dh] Field Name Bits Default Description Latency Timer 7:0 00h Hardwired to “0”. Header Type – R – 8 bits – [PCI_Reg : 0Eh] Field Name Bits Default Description Header[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 230 Interrupt Line – RW – 8 bits – [PCI_Re g: 3Ch] Field Name Bits Default Description Interrupt Line 7:0 00h This register is used to communic ate to software the interrupt line that the interrupt pin is connected to. I[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 231 Power Management Capabilities – R – 16 bits – [PCI_Reg: 52h] Field Name Bits Default Description Version 2:0 010 b Hardwired to 010b. Indicates this function complies with Revision 1.1 of the PCI Power Manageme nt In[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 232 MSI Message Lower Address – RW - 32 bits – [P CI_Reg: 64h] Field Name Bits Default Description MSI Message Lower Address 31:2 00000000 h Lower Address used for MSI Message. Reserved 01:0 0h Reserved MSI Message Upper A[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 233 Register Name Address Offset Immediate Command Input Interface 64h Immediate Command Input Interface 68h DMA Position Buffer Lower Base Address 70h DMA Position Buffer Upper Base Address 74h Control 80h Status 83h Link Pos[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 234 Register Name Address Offset Control 140h Status 143h Link Position in Current Buffer 144h Cyclic Buffer Length 148h Last Valid Index 14Ch FIFO Size 150 h Stream Format 152h Buffer Descriptor Lower Base Address 158h Buffer[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 235 Output Payload Capability – R – 16 bits - [Mem _Reg: Base + 04h] Field Name Bits Default Description Output Payload Capabilit y 15:0 003Ch Hardwired to 3Ch. Indicates the total o utput payload on the link. This does no[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 236 Wake Enable – RW – 16 bits - [Mem_ Reg : Base + 0Ch] Field Name Bits Default Description Wake Enable 3:0 0h This field controls which SDIN signals may generate a wake event in response to a codec State Ch ange event. B[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 237 Input Stream Payload Capability – R – 16 bits - [Mem_Reg: Base + 1Ah] Field Name Bits Default Description Input Stream Payload Capability 15:0 0000h T his field indicates the maximum number of words per frame for any s[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 238 Interrupt Status – RW – 32 bits - [Mem_Reg : Base + 24h] Field Name Bits Default Description Stream Interrupt Status 7:0 00h A “1” indicate s that an interrupt condition occ urred on the corresponding stream. These[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 239 CORB Upper Base Addre ss – RW – 32 bits – [Mem_Reg : Base + 44h] Field Name Bits Default Description CORB Upper Base Address 31:0 00000000 h Upper 32 bits address of the CORB. This register must not be written when t[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 240 CORB Status – RW – 8 bits – [Mem_ Reg: Base + 4Dh ] Field Name Bits Default Description CORB Memory error Indication 0 0b If this status bit is set, t he controller has detected an error in the pathway bet ween the c[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 241 RIRB Response Interrupt Count – RW – 16 bits – [Mem_Reg: Base + 5 Ah] Field Name Bits Default Description N Response Interrupt Count 7:0 00h 01h = 1 Response sent to RIRB : FFh = 255 Responses sent to RIRB 00h = 256 [...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 242 Immediate Command Output Interface – RW – 32 bits – [Mem _ Reg: Base + 60h] Field Name Bits Default Description Immediate Command Write 31:0 00000000 h The value written into this register is used as the verb to be s[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 243 DMA Position Lo wer Base Address – RW – 32 bits – [Mem_Reg: Base + 7 0h] Field Name Bits Default Description DMA Position Lower Base Address 31:7 0000000h Conta ins the upper 25 bits of the lower 32 bits of the DMA P[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 244 Stream Descriptor Control – RW – 24 bits Input Stream 0 - [Mem_Reg: Base + 8 0h] Input Stream 1 - [Mem_Reg: Base + A0h] Input Stream 2 - [Mem_Reg: Base + C0h] Input Stream 3 - [Mem_Reg: Base + E0h] Output Stream 0 - [M[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 245 Stream Descriptor Status – RW – 8 bits Input Stream 0 - [Mem_Reg: Base + 8 3h] Input Stream 1 - [Mem_Reg: Base + A3h] Input Stream 2 - [Mem_Reg: Base + C3h] Input Stream 3 - [Mem_Reg: Base + E3h] Output Stream 0 - [Mem[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 246 Stream Descriptor Cyclic Buffer Length – RW – 3 2 bits Input Stream 0 - [Mem_Reg: Base + 8 8h] Input Stream 1 - [Mem_Reg: Base + A8h] Input Stream 2 - [Mem_Reg: Base + C8h] Input Stream 3 - [Mem_Reg: Base + E8h] Output[...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 247 Stream Descriptor FIFO Size – R – 16 bits Input Stream 0 - [Mem_Reg: Base + 9 0h] Input Stream 1 - [Mem_Reg: Base + B0h] Input Stream 2 - [Mem_Reg: Base + D0h] Input Stream 3 - [Mem_Reg: Base + F 0h] Output Stream 0 - [...]

© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 248 Stream Descriptor BDL Pointer Lo wer Base Address – RW – 32 bits Input Stream 0 - [Mem_Reg: Base + 9 8h] Input Stream 1 - [Mem_Reg: Base + B8h] Input Stream 2 - [Mem_Reg: Base + D8h] Input Stream 3 - [Mem_Reg: Base + F[...]

© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 249 3 Register Descriptions: PCI Bridges 3.1 LPC ISA Bridge (Device 20, Function 3) Note: Some LPC functions are controlled by, and asso ciat ed with, certain PCI configuration registers in the SMBus/ACPI device. For mo[...]

© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 250 Register Name Offset Address Rom Protect 1 54h Rom Protect 2 58h Rom Protect 3 5Ch PCI Memory Start Address for LPC Target Cycles 60h PCI Memory End Address for LPC Target Cycles 62h PCI IO base Address for Wide Gen[...]

© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 251 CMD- RW - 16 bits - [PCI_ Reg : 04h] Field Name Bits Default Description SERR# Enable 8 0b SERR# enable - If set to 1, the LPC bridge asserts SERR# when it detects as address parity error. SERR# is not asserted if t[...]

© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 252 Latency Timer - R - 8 bit s - [PCI_Reg: 0Dh ] Field Name Bits Default Description Latency Timer 7:0 00h Latency Timer. Latency Timer Register: T his register specifies the value of the Latency Timer in units of PCIC[...]

© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 253 IO Port Decode Enable Register 1- RW - 8 bits - [PCI_Re g: 44 h] Field Name Bits Default Description Parallel Port Enable 5 5 0b Port enab le for parallel port, 7bc-7bfh Serial Port Enable 0 6 0b Port enable for ser[...]

© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 254 IO/Mem Port Decode Enable Register 5- RW - 8 bits - [PCI_Reg : 48h] Field Name Bits Default Description Rom Range 1 Port Enable 3 0b Port enab le for LPC ROM address range 1 (memory), see register 68-6bh Rom Range 2[...]

© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 255 Rom Protect 0 - RW - 32 bits - [P CI_Reg: 50h] Field Name Bits Default Description Write Protect 0 0b W hen this bit is set, the memory range defined by this register is write-protected. Writing to the rang e has no[...]

© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 256 LPC ROM Address Range 1 (Star t Address ) - RW - 16 bits - [PCI_Reg: 6 8h] Field Name Bits Default Description Rom Start Address 1 15:0 0eh (if iLpc_Rom strap is enabled), 00h (if the strap is disabled) 16-bit start[...]

© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 257 Firmware Hub Select – RW* - 32 bits - [PCI_Reg: 70h] Field Name Bits Default Description FWH_D8_IDSEL 15:12 4h IDSEL for two 512 KB FWH memory ranges. The IDSEL programmed in this field addre sses the following me[...]

© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 258 Miscellaneous Control Bits- RW - 8 bi ts - [PCI_Reg: 78h ] Field Name Bits Default Description Msi On 1 0b W hen this bit is set to 1, it turns on LPC MSI capability. The following will be true: * Reg0x04[20] (capab[...]

© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 259 MSI Capability Register- R - 32 bits - [PCI_Reg: 80h] Field Name Bits Default Description CAP Fixed 17 1b CAP F ixed. Reserved 26:18 000h CAP Type 31:27 15h CAP Type. TMKBC_BaseAddrLo w Register- RW - 32 bits - [PCI[...]

© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 260 TMKBC_Remap Regis ter- RW - 16 bits - [P CI_R eg: 8Ch] Field Name Bits Default Description TMKBC_Remap 15:8 00h This register defines the remap address [15: 8] on the LPC bus. There are actually four sets of such ma[...]

© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 261 Register Name Offset Address SPI_FakeID 1Ch SPI_Cntrl0 Register- RW - 32 bits - [M em_Reg 00h] Field Name Bits Default Description SPI_OpCode 7:0 00h When soft ware uses the alternate program method to communicate w[...]

© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 262 SPI_RestrictedCmd2 Register- RW - 32 bits - [Mem_Reg 08h] Field Name Bits Default Description RestrictedCmdWoAddr 1 23:16 00h Same as RestrictedCmd0 e xc ept this command does not have address RestrictedCmdWoAddr 2 [...]

© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 263 SPI_CmdValue1 Register- RW - 32 bits - [Mem_Re g 14h] Field Name Bits Default Description WREN 7:0 06h T his is used to compare against the opcode sent out by the MAC. This is a predefined value to decode f or the W[...]

© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 264 3.1.4 Features of the LPC Block Bus Speed: LPC bus—33MHz Supported peripherals and address: • I/O address devices: • Parallel Ports: 378~37fh, 778~77fh, 278~27fh, 678~67fh, 3bc~3 bfh, 7bc~7bfh • Serial Ports[...]

© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 265 3.2 Host PCI Bridge Registers (Device 20, Function 4) Note: Some PCI functions are controlle d by, and associat ed with, certain PCI configuration registers in the SMBus/ACPI device. For more information[...]

© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 266 Register Name Offset A ddress Additional Priorit y 49h PCICLK Enable Bits 4Ah Misc Control 4Bh AutoClockRun Control 4Ch Dual Address Cycle Enable a nd PCIB_SCLK_Stop Override 50h MSI Mapping Capabilit y [...]

© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 267 Status- RW - 16 bits - [PCI_Reg : 06h] Field Name Bits Default Description Capabilities List 4 0b Read only. This bi t is 1 when Offset 40h [3] = 1. At other time this bit is 0. 0 – Bridge does not sup[...]

© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 268 Primary Bus Number- RW - 8 bits - [PCI_Reg: 18 h] Field Name Bits Default Description Primary Bus Number 7:0 00h Bus number of the PCI bus to which the primary interface is connected. Primary Bus Number [...]

© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 269 Secondary Status- RW - 1 6 bits - [PCI_Reg: 1Eh] Field Name Bits Default Description Received Secondar y Target Abort 12 0b Received Target Abort on the secondar y bus, write clears it. Received Secondar[...]

© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 270 IO Limit Upper 16 bits- RW - 16 bits - [PCI_ Reg: 32h] Field Name Bits Default Description IO limit upper 16 bits Capabilities Pointer- R - 8 bits - [P CI_Reg: 34h] Field Name Bits Default Description Ca[...]

© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 271 Bridge Control- RW - 16 b its - [PCI_Reg: 3Eh] Field Name Bits Default Description Secondary Discard Timer 9 0b Secondary Discard T imer conf iguration, ‘0’ configures the timer to 15-bit, ‘1’ co[...]

© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 272 CLKCTRL- RW - 8 bits - [ P CI_Reg: 42h] Field Name Bits Default Description PCICLKStopEnable 0 0b 33MHz PCICLKs request bit; when ‘1,’ 33 MHz PCI Clocks are requested to stop. PCICLKStopStatus 1 0b R[...]

© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 273 PCICLK Enable Bits- RW - 8 bits - [PC I _Reg: 4Ah] Field Name Bits Default Description PCICLK4Enable 0 1b 33MHz PCICLK4 enable. PCICLK5Enable 1 1b 33MHz PCICLK 5 enable. PCICLK6Enable 2 1b 33MHz PCICLK 6[...]

© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 274 Dual Address Cycle Enable and PCIB_CLK_Stop Ov erride - RW - 16 bits - [PCI_Reg: 50h] Field Name Bits Default Description ClkrunOvrridePCICLK 6 0b When set, overrides the CLKRUN# and 33MHz PCICLK continu[...]

© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 275 Prefetch Size Control - 32 bits - [PCI_ Reg: 60h] Field Name Bits Default Description Read Size 2:0 2h If prefetch function is enabled, this defines the numb er of initial prefetch cachelines for a PCI R[...]

© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 276 Misc Control Register - 32 bits - [P CI_Reg: 64h] Field Name Bits Default Description Prefetch Enable For Upstream Read Line and Read Multiple 7 1h 0: Prefetch is disabled fo r upstream memory read line [...]

© 2008 Advanced Micro De vices, Inc. GPIO/GPOC AMD SB600 Register Referen ce Manual Proprietary Page 277 4 Register Descriptions: General Purpose Functions/Interrupt Controllers/Support Function Pins 4.1 GPIO/GPOC Note: Some GPIO functions are controlled by, and a ssoci ated with, certain PCI configuration registers in the SMBus/ACPI device. For m[...]

© 2008 Advanced Micro De vices, Inc. GPIO/GPOC AMD SB600 Register Referen ce Manual Proprietary Page 278 Pin Name (Note 1) Multi-function Selection Output Enable (On SMBus Controller) Bus 00h/ Dev14h/ Fun00 Input if GPI (On SMBus Controller) Bus 00h/ Dev14h/ Fun00 Output if GPO (On SMBus Controller) Bus 00h/ Dev14h/ Fun00 Power Domain GPIO4/ SMART[...]

© 2008 Advanced Micro De vices, Inc. GPIO/GPOC AMD SB600 Register Referen ce Manual Proprietary Page 279 Pin Name (Note 1) Multi-function Selection Output Enable (On SMBus Controller) Bus 00h/ Dev14h/ Fun00 Input if GPI (On SMBus Controller) Bus 00h/ Dev14h/ Fun00 Output if GPO (On SMBus Controller) Bus 00h/ Dev14h/ Fun00 Power Domain GPIO[30:15]/[...]

© 2008 Advanced Micro De vices, Inc. GPIO/GPOC AMD SB600 Register Referen ce Manual Proprietary Page 280 Pin Name (Note 1) Multi-function Selection Output Enable (On SMBus Controller) Bus 00h/ Dev14h/ Fun00 Input if GPI (On SMBus Controller) Bus 00h/ Dev14h/ Fun00 Output if GPO (On SMBus Controller) Bus 00h/ Dev14h/ Fun00 Power Domain GPIO42/ ACZ_[...]

© 2008 Advanced Micro De vices, Inc. GPIO/GPOC AMD SB600 Register Referen ce Manual Proprietary Page 281 Pin Name (Note 1) Multi-function Selection Output Enable (On SMBus Controller) Bus 00h/ Dev14h/ Fun00 Input if GPI (On SMBus Controller) Bus 00h/ Dev14h/ Fun00 Output if GPO (On SMBus Controller) Bus 00h/ Dev14h/ Fun00 Power Domain GPIO[60:53]/[...]

© 2008 Advanced Micro De vices, Inc. GPIO/GPOC AMD SB600 Register Referen ce Manual Proprietary Page 282 Pin Name (Note 1) Multi-function Selection Output Enable (On SMBus Controller) Bus 00h/ Dev14h/ Fun00 Input if GPI (On SMBus Controller) Bus 00h/ Dev14h/ Fun00 Output if GPO (On SMBus Controller) Bus 00h/ Dev14h/ Fun00 Power Domain Notes: 1– [...]

© 2008 Advanced Micro De vices, Inc. GEVENT/GPE/GPM/ExtEvent AMD SB600 Register Referen ce Manual Proprietary Page 283 4.2 GEVENT/GPE/GPM/ExtEvent 4.2.1 GEVENT as GPIO GEVENT[1:0] are inputs only. Their status ca n be read from PM I/O Reg 92h Bit[1:0]. GEVENT[7:2] can be programmed either as GPIO lines or as GPE lines (s ee section 4.2.2 ).  PM[...]

© 2008 Advanced Micro De vices, Inc. GEVENT/GPE/GPM/ExtEvent AMD SB600 Register Referen ce Manual Proprietary Page 284 Pin Name (*Note 1) Multi-Function Selection Configure Bit 00 – SCI or SMI# 01 – SMI# 10 – SMI# followed by S CI 11 - IRQ13 Trigger Configure 0–Falling edge 1–Rising edge Enable ACP I E ve n t Status (Write 1 to ACPI GPE0[...]

© 2008 Advanced Micro De vices, Inc. GEVENT/GPE/GPM/ExtEvent AMD SB600 Register Referen ce Manual Proprietary Page 285 Pin Name (*Note 1) Multi-Function Selection Configure Bit 00 – SCI or SMI# 01 – SMI# 10 – SMI# followed by S CI 11 - IRQ13 Trigger Configure 0–Falling edge 1–Rising edge Enable ACP I E ve n t Status (Write 1 to ACPI GPE0[...]

© 2008 Advanced Micro De vices, Inc. GEVENT/GPE/GPM/ExtEvent AMD SB600 Register Referen ce Manual Proprietary Page 286 Pin Name (*Note 1) Multi-Function Selection Configure Bit 00 – SCI or SMI# 01 – SMI# 10 – SMI# followed by S CI 11 - IRQ13 Trigger Configure 0–Falling edge 1–Rising edge Enable ACP I E ve n t Status (Write 1 to ACPI GPE0[...]

© 2008 Advanced Micro De vices, Inc. GEVENT/GPE/GPM/ExtEvent AMD SB600 Register Referen ce Manual Proprietary Page 287 4.2.3.2 GPM pins as Outpu t For GPM[7:0], follow this sequence - 1. Set index register 0C50h to 13h (Misc. Control ). 2. Set CM Data register 0C51h Bits [7:6] = 01b to set Input/Out control. 3. Set GPM port 0C52h appropriate bits [...]

© 2008 Advanced Micro De vices, Inc. THRMTRIP/TALERT AMD SB600 Register Referen ce Manual Proprietary Page 288 4.3 THRMTRIP/TALERT 4.3.1 Thermal Trip – THRMTRIP The thermal trip function is multiplexed on the G EVENT2 pin. The THRMTRIP status cannot be used to generate SCI or SMI#. Table 4-6: THRMTRIP Pin Pin Name Enable THRMTRIP THRMTRIP Polari[...]

© 2008 Advanced Micro De vices, Inc. Real Time Clock (RTC) AMD SB600 Register Referen ce Manual Proprietary Page 289 4.4 Real Time Clock (RTC) Note: Some RTC functions are cont rolled by, and associat ed with, certain P CI confi guration registers in the SMBus/ACPI device. For more information refer to se ct ion 2.3: SMBus Module and ACPI Block (D[...]

© 2008 Advanced Micro De vices, Inc. Real Time Clock (RTC) AMD SB600 Register Referen ce Manual Proprietary Page 290 . Figure 5 Register Bank Definition and Memory Address Ma pping The analog portion consists of two majo r parts: one is a 256-byte CMOS RAM and the other a 44-bit ripple counter. Register Name Offset A ddress Seconds 00h Seconds Ala[...]

© 2008 Advanced Micro De vices, Inc. Real Time Clock (RTC) AMD SB600 Register Referen ce Manual Proprietary Page 291 Register Name Offset A ddress Register A 0Ah Register B 0Bh Register C 0Ch Register D 0Dh AltCentury (when DV0= 0) 32h Century (when DV0= 1) 48h Extended RAM Address Port 50h Extended RAM Data Port 53h RTC Time Clear 7Eh RTC RAM Ena[...]

© 2008 Advanced Micro De vices, Inc. Real Time Clock (RTC) AMD SB600 Register Referen ce Manual Proprietary Page 292 Hours - RW – 8 bits - [RTC_Reg: 04h ] Field Name Bits Default Description Hours register Hours Alarm- RW – 8 bits - [RT C_ Reg : 05h] Field Name Bits Default Description Hours Alarm 7:0 00h Binary-C ode-Decimal format. If SET bi[...]

© 2008 Advanced Micro De vices, Inc. Real Time Clock (RTC) AMD SB600 Register Referen ce Manual Proprietary Page 293 Register A - RW – 8 bits - [RTC_Reg: 0Ah ] Field Name Bits Default Description Rate Selection(RS1) 1 0b Rate Selection(RS2) 2 0b Rate Selection(RS3) 3 0b 15-stage frequency divider or disable the divider output (flat output signal[...]

© 2008 Advanced Micro De vices, Inc. Real Time Clock (RTC) AMD SB600 Register Referen ce Manual Proprietary Page 294 Register C - R – 8 bits - [RTC_Reg: 0Ch] Field Name Bits Default Description Update Ended Interrupt Flag(UF ) 4 0b T his bit is set to one after each update cycle. Reading Register C clears UF. Alarm Interrupt Flag (AF) 5 0b This [...]

© 2008 Advanced Micro De vices, Inc. Real Time Clock (RTC) AMD SB600 Register Referen ce Manual Proprietary Page 295 Extended RAM Address Port - RW – 8 bits - [RT C_Reg: 50h] Field Name Bits Default Description ExtendedRAMAddr 6:0 00h Becaus e only 7 address bits are used in por t x70, only lower 128 bytes are accessibl e through port x71. The E[...]

© 2008 Advanced Micro De vices, Inc. IOXAPIC Registers AMD SB600 Register Referen ce Manual Proprietary Page 296 4.5 IOXAPIC Registers Note: Some IOXAPIC functions are controlled by, and associated with, certain PCI c onfiguration registers in the SMBus/ACPI device. For more information refer to section 2.3: SMBus Module and ACPI Block (De vi ce 2[...]

© 2008 Advanced Micro De vices, Inc. IOXAPIC Registers AMD SB600 Register Referen ce Manual Proprietary Page 297 4.5.2 Indirect Access Registers Software needs to first select the regist er to access using the IO Register Sele ct Register, and then read or write using the IO Window Regi ster. IOAPIC ID Register [Indirect Address Offset = 00H] RW F[...]

© 2008 Advanced Micro De vices, Inc. IOXAPIC Registers AMD SB600 Register Referen ce Manual Proprietary Page 298 Redirection Table Entry [0–23 ] [Indirect Address Offset = 11/1 0H–3F/3EH] RW Field Name Bits Default Description Destination ID 63:56 0 Bits [19:12] of the address field of the interrupt message[...]

© 2008 Advanced Micro De vices, Inc. Appendix A: AC97 Audio FAQs AMD SB600 Register Referen ce Manual Proprietary Page 299 Appendix A: AC97 Audio FAQs Q: What is the descriptor table (DT) data stru cture in memory? A: Data Pointer (first dword); Size, Status (2nd dwor d) ; Next descriptor pointer (3rd dword). The Data pointer points to the beginni[...]

© 2008 Advanced Micro De vices, Inc. Appendix B: Revision History AMD SB600 Register Referen ce Manual Proprietary Page 300 Appendix B: Revision History Date Rev. Comment September, 2008 3.03 First rel ease of the public version.[...]