Compaq 21264 manual

Compaq Computer Corporation Shrewsbury , Massachuset t s Alpha 21264/EV67 Microprocessor Hardware Reference Manual Orde r Number: DS–0 028B –TE This manu al is di rect ly derive d from the internal 21264 /EV67 Spe cificat ions, Revi- sion 1.4. Y ou can ac cess th is ha rdware ref erence m anual in PDF form at from th e following site: ftp://f t[...]

September 2000 The infor mat ion in this pub li cat ion is subj ec t to cha nge witho ut noti ce . COMP AQ COMPUTER CORPORA TION SHALL NOT BE LIABLE FOR TECHNICAL OR EDITORIAL ERRORS OR OMISS IONS CONT AINED HEREIN, NOR FOR INCIDEN T AL OR CONSEQUENTIAL DAM- AGES RESUL TING FROM THE FURNISHING , PERFORMANCE, OR USE OF THIS MA TERIAL. T H IS INFORMA[...]

Alpha 21264/E V67 Hard ware Ref erence Manual iii T able of Content s Pref ace 1 Introduction 1.1 The Archi tecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 1.1.1 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

iv Alpha 212 64/EV 67 Hardwar e Referenc e Manual 2.3.1 Instruct ion Group Definit ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17 2.3.2 Ebox Slot ting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18 2.3.3 Instruct ion Late[...]

Alpha 21264/E V67 Hard ware Ref erence Manual v 4.3.2 System Duplicate Tag Store s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7 4.4 Victim D ata Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8 4.5 Cache Coh erency . . . [...]

vi Alpha 212 64/EV 67 Hardwar e Referenc e Manual 5.1. 3 Virtual Ad dress Register – VA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4 5.1.4 Virtual Ad dress Control Re gister – VA_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4 5.1.5 Virtual Ad dress Format Re gister ?[...]

Alpha 21264/E V67 Hard ware Ref erence Manual vii 6.5.2 Hardware Structure of Explic itly Written IPRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 6.5.3 Hardware Structure of Impli citly Written IPRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9 6.5.4 IPR Acces s Ordering . . . . . . . . . . . . . .[...]

viii Alpha 212 64/EV 67 Hardwar e Referenc e Manual 7.11.2 PLL Output Cl ocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–19 7.11.2.1 GCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–19 7.11.2.2 Differe nti[...]

Alpha 21264/E V67 Hard ware Ref erence Manual ix 11.5.2 SROM Initial ization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–5 11.5.2.1 Serial Instru ction Cache L oad Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–6 11.6 Notes on IEEE 1149.1 Operation an[...]

x Alpha 212 64/EV 67 Hardwar e Referenc e Manual D.26 Restricti on 30 : HW_MTPR and HW_MFPR to the Cbox CSR . . . . . . . . . . . . . . . . . . . . . . . D–15 D.27 Restricti on 31 : I_CTL[VA_ 48] Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–17 D.28 Restricti on 32 : PCTR_CTL Upd ate . . . . . . . . [...]

Alpha 21264/E V67 Hard ware Ref erence Manual xi Figures 2–1 21264/EV67 Bl ock Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 –3 2–2 Branch Predic tor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 2–3 Loca[...]

xii Alpha 212 64/EV 67 Hardwar e Referenc e Manual 5–34 Dcache S tatus Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–32 5–35 Cbox Da ta Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–33 5–36 Cbo[...]

Alpha 21264/E V67 Hard ware Ref erence Manual xiii Tables 1–1 Integer Dat a Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 2–1 Pipeline Abort Delay (GCLK Cycl es) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16 2–2 Instruc[...]

xiv Alpha 212 64/EV 67 Hardwar e Referenc e Manual 4–34 Rules for System Control of Cache Status Up date Order . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–42 4–35 Range of Maximum Bcache Cl ock Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–43 4–36 Bcache Port Pins . . . . . . . . . . . [...]

Alpha 21264/E V67 Hard ware Ref erence Manual xv 7–6 Effect on IPRs After Transition Through Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10 7–7 Signals and Constraints f or the Sleep M ode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11 7–8 Effect on IPRs After Warm Reset . . . . . . . . [...]

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Alpha 21264/E V67 Hard ware Ref erence Manual xvii Preface Audience This manua l is for syste m designers and pr ogrammers who use t he Alpha 21264/E V 67 micropro cessor (ref erred to as the 21264/EV67). Content This manual contains t he following ch apters and appen dixes: Chapter 1 , Introducti on, introduces the 2 1264/EV67 and prov ides an ove[...]

xviii Alpha 212 64/EV 67 Hardwar e Referenc e Manual Appendix C, S erial Icache Lo ad Predecode V alues, provi des a pointer t o the Alpha Mothe rboa rds So ft wa re Deve lope r ’ s K it (SD K), wh ich co ntai ns th is inf orma ti on. Appendix D, P ALcode Restric tions and Guid elines, lists restrictions and guideli nes that must be adhered t o w[...]

Alpha 21264/E V67 Hard ware Ref erence Manual xix T erminology and Conven tions This sec tion defines the abbrevi ations, terminol ogy , and other conv entions used througho ut this document. Abbreviations • Binary Multip les The abbre viations K, M, and G (kilo, mega , and giga) rep resent bina ry multiples and have t he following values. For ex[...]

xx Alpha 212 64/EV 67 Hardwar e Referenc e Manual • Sign ext ension SEXT(x) means x i s sign-extended to the requi red size. Addresses Unless ot herwise note d, all addres ses and of fsets are hex adecimal. Aligned and Unaligned The term s aligned an d naturally a ligned are i nterchangeab le and refer to data objects that ar e powers of two in s[...]

Alpha 21264/E V67 Hard ware Ref erence Manual xxi Data Unit s The foll owing data uni t terminology is used thro ughout this manu al. Do Not Care (X) A capital X represents any valid value. Exte rnal Unless ot herwise sta ted, external mea ns not contai ned in the chi p. Field Nota tion The name s of single-bi t and multiple-b it fields c an be use[...]

xxii Alpha 212 64/EV 67 Hardwar e Referenc e Manual AlphaSignal[n: n] Boldface, mixed-c ase type denotes signal names tha t are assigne d internal a nd external to the 21264/EV67 (that is, the sig nal travers es a chip inter face pin). AlphaSignal_ x [n:n] When a signa l has high and low asserti on states, a l ower- case it alic x repr esents the a[...]

Alpha 21264/E V67 Hard ware Ref erence Manual xxiii X Do not car e. A capital X r epresents any v alid value.[...]

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Alpha 21264/E V67 Hard ware Ref erence Manual Introductio n 1–1 1 Introduction This chap ter provides a brief intr oduction to t he Alpha archite cture, Compaq’ s RISC (reduce d instruction set computing) archi tecture designed f or high performa nce. The chapter then summarize s the specif ic features of the Alpha 21264 /EV67 microproce s- sor[...]

1–2 Introduc tion Alpha 212 64/EV 67 Hardwar e Referenc e Manual The Architec tu re direct access to low- level hardwar e funct ions. P ALcode suppor ts opti mizat ions fo r mul- tiple opera tin g syst ems, flexi ble mem ory -man ag eme nt im plem ent at ion s, a nd mu l ti- instru ction atomic sequ enc es. The Alpha a rchitectur e performs byt e[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Introductio n 1–3 21264/ EV67 Microprocessor Features 1.2 21264/EV67 Microprocessor Features The 21264/EV67 microprocessor is a sup er sca lar pipeline d pro ces sor . It is package d in a 587-pi n PGA carrier a nd has removable app lication-s pecific hea t sinks. A number of configur ation opt ions a[...]

1–4 Introduc tion Alpha 212 64/EV 67 Hardwar e Referenc e Manual 21264/ EV67 Microprocessor Features • An onchip, d uplicate ta g array used t o maintain level 2 cache coher ency . • A 64-bit data bus with o nchip parity and error co rrection code ( ECC) support. • Support f or an extern al second-le vel (Bcache) cache. The siz e and some t[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–1 2 Internal Architecture This chapte r pr ovid es both an overview of the 21264/EV67 microarchit ect ure and a sys- tem designer’ s view of the 2 1264/EV67 implementat io n of t he Alp ha architectur e. The combinat ion of the 21264/EV67 mic roar chi te ctur e and privileg[...]

2–2 Intern al Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual 21264/ EV67 Microarchitect ure • Floatin g-point exec ution unit ( Fbox) • Onchip cac hes (Icache and Dcache) • Memory re ference uni t (Mbox) • External cache and sys tem interface u nit (Cbox) • Pipelin e operation sequenc e 2.1.1 Instruction Fetch, Issue, and [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–3 21264/EV 67 Microarchit ecture Figure 2–1 21264/EV 67 Block Diagram 2.1.1.2 Branch Predictor The branc h predictor is composed of t hree units: th e local, glob al, and choice predic- tors. Fi gure 2–2 shows ho w the branch pr edictor gene rates the predi cted branch ad[...]

2–4 Intern al Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual 21264/ EV67 Microarchitect ure Figure 2–2 Branch Predictor Local Predictor The local predictor uses a 2-level t able that h olds the hist ory of individu al branches. The 2-le vel table des ign approache s the predic tion accuracy of a lar ger single-l evel table whi le [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–5 21264/EV 67 Microarchit ecture Figure 2–4 Global Predictor Choice Predictor The choice predicto r monitors the histor y of the lo cal and glob al predic tors and ch ooses the best of the two pr edictors f or a particul ar branch. Figure 2–5 sho w s how the choic e predi[...]

2–6 Intern al Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual 21264/ EV67 Microarchitect ure 2.1.1.4 Instruction Fetch Logic The inst ruction pref etcher (prede code) reads a n octaword, contai ning up to four natu- rally ali gned instructions per cycle, f rom the Icache. Branch prediction and l ine predic- tion bi ts accompany the f[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–7 21264/EV 67 Microarchit ecture • Inte ger operate • Integer conditional branch • Unconditi onal branch – bot h displacement an d memory format • Integer and floati ng-point load and store • P AL-reserv ed instruction s: HW_MTPR, HW_MFPR, HW_LD, HW_ST , HW_RET ?[...]

2–8 Intern al Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual 21264/ EV67 Microarchitect ure The FQ arbiter s pick bet ween simul taneou s reques ters of a pipelin e based on the age of the requ est —ol de r r eque st s are given pri or it y ove r newer request s. Fl oat ing-point s tore instru ctions and FT OI x instr uctions in e[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–9 21264/EV 67 Microarchit ecture Figure 2–6 Integer Execution Unit—Cl usters 0 and 1 Most i nstru ctions have 1- cycle late ncy for consumer s tha t execu te wit hin th e sa me clus - ter . Also, t here is anoth er 1- cycle dela y ass ociat ed wit h prod ucing a value in [...]

2–10 Internal Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual 21264/ EV67 Microarchitect ure The Ebox has 80 register -file entr ies that cont ai n st orage for the va lue s of the 31 Alpha integer registers (t he value of R3 1 is not stor ed), the valu es of 8 P ALshadow regist ers, and 41 re sults written b y instructi ons that hav[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–1 1 21264/EV 67 Microarchit ecture The Fbox re gister file c ontains six reads ports and four write por ts. Four read ports are used to s ource operand s to the add an d multiply pipel ines, and two r ead ports are used to sour ce data f or store instructions. T wo write port[...]

2–12 Internal Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual 21264/ EV67 Microarchitect ure • V irtual tag bits [47:15] • 8-bit a ddress space number (ASN) field • 1-bit a ddress space m atch (ASM) bit • 1-bit P ALcode bit to i ndicate phys ical addres sing • V alid bit • Data and t ag parity bits • Four acce ss-check [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–13 Pipeline Organization • Miss addr ess file (M AF) • Dstre am tr ans lati on bu ffer (D TB) 2.1.6.1 Load Queue The load q ueue (LQ) is a r eorder buf fer for loa d instructi ons. It contain s 32 entries and maintai ns t he state asso ci ate d with load instructio ns tha[...]

2–14 Internal Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual Pipeline Organization Figure 2–8 Pipeline Organization St age 0 — Instruction Fetch The branch pre dictor uses a br anch history a lgo ri thm t o pr edi ct a br anc h in struction t ar - get addr ess. Up to four aligned instruct ions are fet ched from the Icache , in p[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–15 Pipeline Organization In th e sl ot s tag e, th e bra nch pred ict or c omp ares the n ex t Ic ache ind ex th at i t ge nerat es t o the inde x that was gene rated by the line predictor . If there is a mismatch, the br anch predict or wins—the ins tructions f etched duri[...]

2–16 Internal Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual Instruction Is sue Rules St age 4 — Regi ster R ead Instru cti ons issued fr om t he issue que ues read th eir operands f rom the integer a nd f loat- ing-poi nt register f iles and rec eive bypass data . St age 5 — Execute The Ebox and Fbox pipeline s begin execut ion[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–17 Instruction Issu e Rules 2.3.1 Instruction Group Definitions T able 2– 2 lists the in struction c lass, the pipel ine assignment s, and the instr uctions include d in the clas s. Table 2–2 Instruction Name, Pipeline, and Types Class Name Pipelin e Instruction T ype ild[...]

2–18 Internal Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual Instruction Is sue Rules 2.3.2 Ebox Slotting Instru ctions that are issued fro m the IQ, and coul d execute in e ither upper or lower Ebox su bclusters, are slotted to one pair or the ot her during t he pipeline ma pping stage based on t he instruct ion mixture in the fetc[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–19 Instruction Issu e Rules E L U U L L U U U E L E U L L U E U E E L U L U U E L L U U L L E U E L L U U L U E L U U L L U E U E U L U L U U E U E U L U L E U L E L U L U U E U L U L U L E U L L U U L L U E U U U L U U E U L U L U L U U L E E U L U L E U U E L U U L U L E L [...]

2–20 Internal Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual Instruction Is sue Rules 2.3.3 Instruction Latencies Afte r an i nstr uct io n is pl ace d in th e IQ o r FQ, its i ssu e p oin t is de term ine d by th e av ai l- abilit y of its re gister operands , functional unit(s), and re lationship to other ins tructions in the q ue[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–21 Instruct ion Retire Rules 2.4 Instruction Retir e Rules An instr uction is re tired when it has been execute d to complet ion, and all pre vious instru ctions have be en retired. The execution pipeline stage in which an ins truction becomes el igible to be retired de pends[...]

2–22 Internal Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual Retire of Operate Instructions into R31/F31 2.4.1 Floating-Point Divide/Square Root Earl y Ret ire The floa ting-point d ivider and squar e root unit can detect that , for many comb inations of sourc e operand val ues, no excepti on can be gener ated. Instruct ions with th[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–23 Load Instructions to R31 and F31 2.6 Load Instructions to R31 and F31 This sect io n des cribes how the 2126 4/EV6 7 processes sof twar e- di rec te d pre fe tc h tr ans- actions and load instru ctions with a des tination of R31 and F3 1. Prefet ches al l ocate a MAF en tr[...]

2–24 Internal Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual Special Cases of Alpha Instruction Execution 2.6.3 Pr efe tch, Evi ct Next: LDQ and HW _LDQ Inst ructions The 21264/ EV67 processes t his instruct ion like a nor mal prefetch transaction ( Read- BlkSpec co mmand), with one exception—i f the load mi sses the Dcache, t he [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–25 Special Cases of Alpha Instruction Execution Figure 2–9 Pipeline Timing for Integer Load Instructions There are t wo cycl es in which the IQ may speculati ve ly is sue instruction s tha t use load data bef ore Dca che hit infor mat ion is known. An y inst ructions th at [...]

2–26 Internal Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual Special Cases of Alpha Instruction Execution Figure 2–10 Pipeline Timing for Floating-Po in t Load I nstructions The specul ative window fo r floating-p oint load ins tructions i s one cycle wide. FQ-issue d instruction s that are is sued within th e speculat ive window [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–27 Memory and I/O Address S pace Instructions The firs t in struction, CMOV1 , te sts the value of Ra and r eco rds the resul t of thi s te st in a 65th bit of its de stina tion r egister , newRc1. It also co pie s the val ue of th e old phys ical destina tion register , oldR[...]

2–28 Internal Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual Memory and I/O Address Space Instructions If the requested phys ical locat ion is found i n the Dcache ( a hit), the d ata is formatt ed and writ ten in to the appro priate i nteger or float ing-po int re gister . If t he loc ation i s not in the D cac he (a m i ss), the p[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–29 Memory and I/O Address S pace Instructions 2.8.3 Memory Address Sp ace S tore Instruct ions The Mbox begi ns execution of a store in struction by tr anslating i ts virtual ad dress to a physical address usi ng the DTB and by pr obing the Dcac he. The Mbox puts in forma- ti[...]

2–30 Internal Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual MAF Memory Address Space Merging Rules • Byte/word store inst ructions and different size stor e instructions are not allo wed to merg e. • A stream of as cen din g non-overlappi ng, bu t not necessar il y cons ecutive, longwo rd store i nstruction s are allo wed to me[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–31 Replay Traps The 21264/ EV67 maintains t he default memor y data instru ction orderi ng as shown in T able 2– 10 (assume address X and address Y a re dif ferent). The 21264/EV67 maint ains t he defa ult I/ O instr uctio n order ing as sho wn in T able 2–1 1 (assume a d[...]

2–32 Internal Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual I/O Write Buffer a nd the WMB Instruction 2.1 1.1.1 Load-Load Order T rap The Mbox ensur es that loa d instructi ons that re ad the same physica l byte(s) ul timately issue i n correct or der by using the load-load o rder trap. The Mbox c ompares the address of each load i[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–33 I/O Write Buffer and the WMB Instruction • RdBlkSpec ( valid), RdBlkModSpec ( valid), RdBlkSpecI (valid) • RdBlkV ic, RdBlkModV ic, RdBlkV icI • CleanT oDirty , SharedT oDirty , STChangeT oDirty , InvalT oDirty • Fetch Bl k , Fe tc hB lk Spec (va lid ), Evic t • [...]

2–34 Internal Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual I/O Write Buffer a nd the WMB Instruction Because t he MB instru ction is exe cuted speculati vely , MB processi ng can begin and the o riginal MB c an be killed. In the internal acknowledge c ase, the MB may have alr eady been sent t o the system in terface, and the syste[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–35 I/O Write Buffer and the WMB Instruction Also consi der the re lated sequence shown in T able 2–13. In this case, t he data could be cached i n the Bcache; Pj s hould fetch datai i f it is using P TEi. The 21264/ EV67 processes Dstr eam loads to the P TE by injecting, in[...]

2–36 Internal Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual Performance Measurement Support—Performance Counters 2.13 Performance Measurement Support—Performance Counters The 21264/ EV67 provides hardwar e support for t wo methods of obtai ning program perfor m ance feedback information. The t wo methods do not r equire program[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–37 Floating-Point Control Register UNFD [6 1] R W Und erflow Disable. The 21 264/EV67 hardwar e cannot generate IE EE compli- ant denormal results. UNF D is u sed in conjun ction with UND Z as follows: UNDZ [60] R W Underflow to zero. When UNDZ is set together with UNFD, unde[...]

2–38 Internal Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual AMASK and IMPLVER Instruction Values 2.15 AMASK and IMPL VER Instruction V a lues The AMASK and IMP L VER instruc tions return proc essor type an d supported archi tec- ture ex tensions, res pectively . 2.15.1 AMASK The 21264/ EV67 returns the AMASK ins truction values p r[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Internal Archite ct ure 2–39 Design Examples 2.16 Design Examples The 21264/EV67 ca n be desi gne d into many dif ferent unipro ces sor and mult ip rocessor system co nfiguration s. Figures 2–12 and 2–13 illu strate two possi ble configur ations. These conf igurations empl oy additiona l system/me[...]

2–40 Internal Archit ecture Alpha 212 64/EV 67 Hardwar e Referenc e Manual Design E xamples Figure 2–13 Typical Mult iprocessor Configuration 64-bi t PCI Bus 64-bit PCI B us 21264 L2 Cache 21264 L2 Cache 21272 Core Logic Chipset Control Chip Data S lice Chips Host PCI Bridge Chip Host PCI Bridge Chip DRAM Arrays Address Dat a DRAM Arrays Addres[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Hardware Interfac e 3–1 3 Hardware Interface This chap ter co ntains the 212 64/ EV67 micro proces sor log ic symbol an d pr ovides infor - mation ab out signal na m es, their fun ction, and the ir locatio n. This chapter also descri bes the mechani cal specifi cations of the 21264/EV67. I t is organ [...]

3–2 Hardware Int erface Alpha 212 64/EV 67 Hardwar e Referenc e Manual 21264/EV67 Microprocessor Logic S ymbol Figure 3–1 2 1 264 /EV67 Microprocessor Logic Symbol 21264 System Interfac e Bcache Interface SysAddIn_L[14:0] SysAddInClk_L SysAddOut_L[14:0] SysAddOutClk_L SysVref SysData_L[63:0] SysCheck_L[7:0] SysDataInClk_H[7:0] SysDataOutClk_L[7[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Hardware Interfac e 3–3 21264/EV67 Signal N ames and Functions 3.2 21264/EV67 Signal Names and Functions T able 3– 1 defines the 212 64/EV67 signal t ypes referred to in this s ection. T able 3– 2 lists all si gnal pins i n alphabetic ord er and provide s a full fun ctional descri p- tion of the p[...]

3–4 Hardware Int erface Alpha 212 64/EV 67 Hardwar e Referenc e Manual 21264/EV67 Signal N ames and Functions BcDataOut Clk_H[3:0] BcDataOut Clk_L[3:0] O_PP 8 Bcache data output clocks. These free-run ning clocks are dif- ferential copies of the B cache clock and are derived fro m the 21264/EV67 GCLK. Their period i s a multiple of the GCLK and i[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Hardware Interfac e 3–5 21264/EV67 Signal N ames and Functions FrameClk_H FrameClk_L I_DA_CLK 2 A skew-controlled differen tial 50% duty cycle copy of the sys- tem clo ck. It is used by the 21264 /EV67 as a reference, or framing, clock. IRQ_H[5:0 ] I_DA 6 These six interrupt signal lines may be assert[...]

3–6 Hardware Int erface Alpha 212 64/EV 67 Hardwar e Referenc e Manual 21264/EV67 Signal N ames and Functions T able 3– 3 lists signal s by function and provides an abbreviat ed descripti on. SysV ref I_DC_REF 1 System interface reference voltage. Tc k _ H I_DA 1 IEEE 1 149.1 t est clock. Tdi_H I_DA 1 IEEE 1 149.1 test data-in signal. Tdo_ H O_[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Hardware Interfac e 3–7 21264/EV67 Signal N ames and Functions BcV ref I_DC _ REF 1 T ag data in pu t reference voltage. SysV ref Domain SysAdd In_L[ 14:0] I_DA 15 T im e-multiplexe d S ysAddIn, sy stem-to-21 2 64/EV67. SysAddIn Clk_L I_DA 1 Singl e-ended forwarded clock from sy stem for SysAdd In_L[ [...]

3–8 Hardware Int erface Alpha 212 64/EV 67 Hardwar e Referenc e Manual Pin Assignments 3.3 Pin Assignment s The 21264/EV67 package ha s 587 pins aligne d in a pin grid ar ray (PGA) design. Ther e are 380 f unctional si gnal pins , 1 dedicated 3.3 -V pin for the P LL, 1 12 gr ound VSS pins, and 94 VDD pins. T able 3–4 list s the s ignal pin s an[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Hardware Interfac e 3–9 Pi n As si gnm en t s BcData_H _106 L45 BcDat a_H _107 N45 BcData_H_108 T4 4 BcData_H _109 U45 BcData_H _1 1 M2 BcData_H_1 10 W4 5 BcData_H _1 1 1 AA43 BcData_H_1 12 AC43 BcData_H_1 13 AD44 BcData_H _1 14 AE41 BcData_H_1 15 AG45 BcData_H_1 16 AK44 BcData_H _1 17 AL43 BcData_H_1[...]

3–10 Hardware Interface Alpha 212 64/EV 67 Hardwar e Referenc e Manual Pin Assignments BcData_H _9 K2 BcData _H_90 BA3 BcData_H_91 BC3 BcData_H _92 BD6 BcDat a_H _93 BA9 BcData_H_94 BC9 BcData_H _95 AY 1 2 BcDat a_H _96 A39 BcData_H_97 D36 BcData_H _98 A41 BcDat a_H _99 B42 BcDataInClk_H_0 E7 BcDataInClk_H_1 R3 BcDataIn Clk_H_2 AH2 BcDataInClk_H [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Hardware Interfac e 3–1 1 Pi n As si gnm en t s SysA ddI n_L _5 BA27 SysA ddIn _L_ 6 BD28 Sys AddI n_L_ 7 BE27 SysA ddI n_L _8 AY 2 6 Sys AddI n_ L_9 BC25 Sy sAddI nCl k_L BB26 SysA ddO ut_L _0 AW 3 3 SysA ddO ut_ L_1 BE39 SysA ddOut _L_1 0 BE33 SysA ddO ut_L _1 1 AW 2 9 SysA ddO ut_L _12 BC31 SysAd d[...]

3–12 Hardware Interface Alpha 212 64/EV 67 Hardwar e Referenc e Manual Pin Assignments SysDataOutClk_L _5 R41 SysDataOutClk_L_6 AH40 S y sDataOutClk_L_7 AW 3 9 SysDataOutV alid_L BB22 SysFillV alid_L BC23 SysV ref BA25 Tc k _ H BE19 Tdi_H BA21 Tdo_H BB20 Te s t S t a t _ H BA19 Tms_H BD18 Tr s t _ L AY 2 0 Table 3–5 Pin List Sorted by PGA Locat[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Hardware Interfac e 3–13 Pi n As si gnm en t s AR1 BcData_H _22 AR3 Spare AR39 SysData_L_58 AR43 BcDataOutClk_H_3 AR45 BcData_H_1 1 9 AR7 SysData_L_25 AT 2 BcCheck_H_ 2 AT 3 8 SysData _L_59 AT 4 S p a r e AT 4 2 BcDataOutClk_L_3 AT 4 4 BcCheck _H_14 AT 8 SysDa ta_L_26 AU3 BcDataOutClk_H_1 AU41 BcData_[...]

3–14 Hardware Interface Alpha 212 64/EV 67 Hardwar e Referenc e Manual Pin Assignments BC25 SysAd dIn_ L_9 BC29 Sy sAd dIn _L_ 1 BC3 BcData _H_91 BC31 SysAd dOut_ L_12 BC35 Sy sAddO ut_ L_3 BC37 BcCheck _H_7 BC41 BcData_H _125 BC43 BcData _H_60 BC5 BcDa taInClk_H_3 BC9 BcData_H _94 BD10 BcCheck _H_1 1 BD12 PllBypass_ H BD16 Reset_L BD18 Tms_H BD2[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Hardware Interfac e 3–15 Pi n As si gnm en t s G39 SysData_L_37 G41 Bc Data_H _38 G45 BcData _H_104 G5 BcData_H _70 G7 SysData_L_ 5 H10 SysData_L_ 4 H12 SysData_L_3 H16 BcT ag_H_21 H18 Bc T ag_ H_29 H22 BcT ag_H _42 H24 BcT agOE_L H28 BcAdd_H_13 H30 BcAdd_H_21 H34 SysData_L_ 34 H36 SysDataOutClk_L_4 H[...]

3–16 Hardware Interface Alpha 212 64/EV 67 Hardwar e Referenc e Manual Pin Assignments T able 3–6 l ists the 21264/EV6 7 ground and power ( VSS and VDD , re spe ctiv ely) p in list . Table 3–6 Ground and Power (VSS and VDD) Pin List Signal PGA Location VSS A15 A21 A25 A3 A31 A37 A43 A9 AA1 AA39 AA45 AA7 AC41 AC5 AE1 AE39 AE45 AE7 AG3 AG3 9 AG[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Hardware Interfac e 3–17 Mechanic al Specifications 3.4 Mechanical Specifications This sec tion shows the 21264/EV67 mechani cal package di mensions withou t a heat sink. For heat sink inform ation and dimensi ons, refer to Chap ter 10. Figure 3– 2 shows the pack age physical dimensions wit hout a h[...]

3–18 Hardware Interface Alpha 212 64/EV 67 Hardwar e Referenc e Manual 21264/ EV67 Packagi ng 3.5 21264/EV67 P ackaging Figure 3– 3 shows the 21264/EV67 pinout from th e top view with pin s facing down. Figure 3–3 21264/EV67 Top View (Pin Dow n) FM-05644-EV6 7 BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Hardware Interfac e 3–19 21264/E V67 Packaging Figure 3– 4 shows the 21264/EV67 pinout from th e bottom view with pi ns facing up. Figure 3–4 21264/EV67 Bottom View (Pi n Up) FM-05645-EV6 7 BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A[...]

[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–1 4 Cache and Exte rnal Interfaces This chap ter describ es the 21264/EV67 c ache and exter nal interf ace, which include s the secon d-level cac he (Bcache) i nterface and the syst em interface. It also desc ribes lo cks, interr upt signals , and ECC/parity gen erati[...]

4–2 Cache and Externa l Interfaces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Introduction to the External I nterfaces • The Bcache interface in cludes a 128-bi t bidirectio nal data bus, a 20-bit unidi rec- tional address bus, a nd several co ntrol signals. –T h e BcDataOutClk_ x [3:0] clocks are f ree-running and are derived f rom the i[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–3 Introduction to the External Interfaces Figure 4–1 21264/EV 67 Syst em and Bcache Int erfaces 4.1.1 S yste m Inte rfa ce This sec tion introd uces the syst em (external) bu s interface . The system int erface is made up of t wo unidirect ional 15-bit ad dress buse[...]

4–4 Cache and Externa l Interfaces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Physical Address Considerations 4.1.1.1 Commands and Addresses The syste m sends probe a nd data mov ement command s to the 21264/EV6 7. The 21264 / EV67 can hol d up to eight prob e commands from the system. The system c ontrols the number of out st an din g pr obe[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–5 Physical Address Considerations Prefet ches (LDL, LDF , LDG , LDT , LDBU, LDWU) to R31 use th e LDx flow , and prefet ch with modif y intent (LDS) uses the STx flow . If the prefe tch tar g et is addres sed to I/O s pace, the upper address bit is cleared, con vertin[...]

4–6 Cache and Externa l Interfaces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Physical Address Considerations T able 4– 1 notes: 1. Se t Dirty Flow: Based on the Cbox CSR SET_DIR TY_ENABLE[2:0], SetDirty request s can be eith er internally acknowledged ( called a SetMod ify) or sent to the system e nvi ronment for pr oc essing. Whe n e xt e[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–7 Bcache Structure 4.3 Bcache Structure The 21264/ EV67 Cbox provides control sign als and an int erface for a s econd-level cache (Bc ache). The 21264/ EV67 supports a Bcach e from 1MB to 16MB, with 64-b yte blocks. A 128 - bit bi direc tional d ata b us is used f or[...]

4–8 Cache and Externa l Interfaces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Victim Data Buffer • Issuing probes and SysDc fill comman ds to the 21264 /EV67 out-of-orde r with respect to their or der at the sy stem serializ ation point • Filter ing out all probe misses from t he 21264/EV67 cac he system If a probe mi sses in the 2 1264/E[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–9 Cache Coherency Figure 4–3 Cache Subset Hierarchy The foll owing tasks must be performed to mai ntain cache coherency: • Istrea m data from memory spaces may b e cached in the Icache a nd Bcache. Ica che coherenc e is not maint ained by hard ware—it must be ma[...]

4–10 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Cache Coherency 4.5.3 Cache Block S t ate T ransitions Cache bloc k state tr ansitions are r eflected by 2126 4/EV67-generat ed commands to th e system. Cac he block stat e transitions can also be c aused by syste m -generated c om- mands to t he 21264/EV67 (pr ob[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–1 1 Cache Coherency 4.5.4 Using SysDc Commands Note th e foll ow in g: • The conven tional resp onse for RdBlk co m mands is SysDc ReadData or ReadD- ataShar ed. • The conven tional resp onse for a RdBlkMod command is SysDc Read DataDirty . • The conven tional r[...]

4–12 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Cache Coherency RdBlkM odx ReadData ReadDataShared ReadDataShared/Dirty The cache block is filled an d marked with a nonwritable status. If the store in struction that generated t he RdBlkModx com mand is still active (not killed), the 21 264/EV67 will retry the i[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–13 Cache Coherency The 21264/ EV67 sends a W rV ictimBl k command to th e system when it evicts a Dirty or Dirt y/Shared cache bl ock. The 21264/EV67 may be configured t o send a CleanV ic- timBlk to the system (by way o f the Cbox CSR BC_CLEAN_VICTIM[0]) when evict- [...]

4–14 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Lock Mechanis m 1. When the Mbox requests a Dca che fi ll, the Cbox uses t he CT AG array entry t o find if the Dcache alread y contains the r equested physi cal address in another vir tually- indexed Dc ache line. If it does, the Cbox invalidate s that cache line[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–15 Lock Mechanis m 4.6.1 In-Order Processing of LDx_L/STx_C Instructions The 21264 /EV67 uses t he stW ait logic in the I Q to ens ure that LDx_L /STx_C pair s are issued i n order . The stW ait logic tr eats an Ldx_L in struction l ike Stx instructions. STx_C inst ru[...]

4–16 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Syste m Port If the ChangeT oDirty c ommand succeeds, t he STx_C ente rs the writable state, and t he Mbox locks t he Dcache lin e. The Mbox does not release the Dcache line unti l the STx_C data i s transferred to th e Dcache. This ensur es that no ot her agent, [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–17 Syste m Port Figure 4–4 System In terface Si gnals 4.7.1 S yste m Port P ins T able 3– 1 defines the 212 64/EV67 signal t ypes referred to in this s ection. T able 4–6 lists the system por t pin groups a long with their type, number , and functional descrip- [...]

4–18 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Syste m Port 4.7.2 Programming the System I nterface Clock s The syste m forwarded clocks are free running and de rived from th e 21264/EV67 GCLK. The peri od of the system f orwarded clocks i s controlled by thr ee Cbox CSRs, base d on th e b it- rate ra tio (sim[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–19 Syste m Port T able 4–9 l ists the progra m values for CSR SYS_ FRAME_LD_VECTOR[4:0 ] that set the rat io between th e forwarded cl ocks and the f rame clock. 4.7.3 2 1264 /EV6 7-to-S yste m Co mmands This sec tion descri bes the 2126 4/EV67-to-sys tem commands f[...]

4–20 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Syste m Port 4.7.3.2 Page Hit Mode T able 4– 11 shows the comma nd format for page hit mode (21264/ EV67-to-syst em). T able 4– 12 describes the field defi nitions for T ables 4–10 a nd 4–1 1. Cycle 2 P A[27:22], P A[12:6] P A[35] P A[37] Cycle 3 M2 Mask[7[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–21 Syste m Port System des igners can min imize pin count for s ystems with a small memory by config- uring bot h the bank int erleave on cach e block boundar y mode and the pag e hit mode forma ts into a sho rt bus format. The pin SysAddOut_L[1] and/or Sy sAddOut_L[0[...]

4–22 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Syste m Port ReadBlkMod 10001 Memory read with modif y intent. ReadBlkI 10010 Memory read for Istream. FetchBlk 1001 1 Noncached memory read. ReadBl kS pec 2 10100 Specu lative memory read ( optional). ReadBlkModS pec 2 10101 Speculative mem ory read with modify i[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–23 Syste m Port T able 4– 14 footnotes: 1. Sy stems can op tionally enab le MB instruct ions to the ext ernal syste m by asserting Cbox CSR SYSBUS_MB_ENABLE. This mode i s described in Sect ion 2.12.1. 2. T o minimize l oad-to-use me mory latency , systems can opti [...]

4–24 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Syste m Port System s that require an explicit indication of ChangeT oDirty s tatus change s initi- ated by STx _C instructions can assert Cbox CSR STC_ ENABLE[0]. When this regist er fi el d = 000, CleanT oDirty and Shar ed T oDirty comma nds ar e us ed. The dis-[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–25 Syste m Port T able 4– 18 describes the ProbeResponse c ommand fields. The syst em uses t he SysD c signal lines to retri eve data for pr obes that request ed a ca che block fr om the 21264/EV67. See Se ction 4.7.7.2 f or more informa tion about 2-cycle data tr a[...]

4–26 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Syste m Port • There is no mechanism fo r the syst em to rejec t a 21264/EV67 -to-syst em command. ProbeRespo nse, VDBFlushReq, NOP , NZNOP , and RdBlk x Spec (wit h a clear R V bit) co m mands do no t require a res ponse from the sys tem. Systems must provide a[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–27 Syste m Port T able 4– 20 describes the system-t o-21264/EV67 prob e commands fiel ds descripti ons. The probe command field Pro be[4:0] has t wo sections, P robe[4:3] an d Probe[2:0]. T able 4– 21 lists the da ta movement sele cted by Probe[ 4:3]. T able 4– [...]

4–28 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Syste m Port The 21264/ EV67 holds pendin g probe commands in a 8 -entry deep probe queue. The system mu st co unt the nu mber of prob es t h at have been se nt and ens ure that the prob es do not ove rrun the 21264/EV67 queue. The 21264/ EV67 removes probes from [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–29 Syste m Port T able 4– 24 describes the SysDc[4:0] fi eld. The A bit i n the firs t cycl e indicat es th at th e c ommand i s ackn owledge d. When A = 1 , the 21264/EV67 d ecrements it s command outs tanding count er , but the A bit is not neces - saril y relate [...]

4–30 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Syste m Port The ChangeT oDirtySucc es s a nd Cha nge T oDirtyFail command s c annot be iss ued in the shadow of S ysDc cache fil l commands (ReadDataErro r , ReadData, ReadDataDirt y , ReadDataSh ared, and Rea dDataShared /Dirty). Each cache f ill command a lloca[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–31 Syste m Port If both the sender an d the receive r are sampli ng at the same rat e, these three p rinciples are suf ficie nt to safel y make point-to- point trans fers using cloc k forwarding. However , it is o ften desirabl e for systems to align clock- forwarded [...]

4–32 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Syste m Port The comman d precedes dat a by at leas t one SYSCLK period. T able 4–25 shows the number of SYSCLK cycles between SysAdd Out and SysData for all system c lock ratios (clock forwa rded bit times) and system fra ming clock mult iples. Figure 4– 5 sh[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–33 Syste m Port T able 4– 26 shows four example configurat ions and shows t heir use of t he SYSDC_DELA Y[4:0]. System 1 ha s six GCLKs to ever y SYSCLK and only sends 4- cycle commands t o the 21264/EV67. Thus , a period of thr ee SYSCLKs between th e SysDc command[...]

4–34 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Syste m Port T able 4– 27 lists infor mation for th e four timing examples. In T able 4–27, note the fol- lowi ng: • SysD c wri te co m man ds ar e no t affect ed by the S Y SDC _ DEL A Y par am et er . • The SYS_RCV_MUX_PRESET adds del ay at the rate of o[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–35 Syste m Port 1. The SysDataI nV alid_L si gnal must be as serted for b oth cycles of a Sy sDc fill command, a nd t wo quad w ord s of dat a must be del ive re d to the 2126 4/EV6 7 in suc - ceeding bit-clock c ycles with the ap propriate t iming in refe rence to th[...]

4–36 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Syste m Port Figure 4–6 SysFillValid_L Timing 4.7.8.6 Data Wrapping All dat a movement bet ween the 2 1264/EV67 and the s ystem is compos ed of 64 bytes in eight c ycles on the d ata bus. All 64 bytes of memory data are valid. Thi s applies t o memory read trans[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–37 Syste m Port point i s the QW pointed to b y the 21264/EV67; howe ver , some systems may fi nd it more benef icial to begin the transf er elsewhere. The system must alway s indicate t he starting point to the 21264/EV67. The wrap ord er for subsequen t QWs is inter[...]

4–38 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Syste m Port T able 4– 31 defines th e wrap order for double-pumped da ta transfers. 4.7.9 Nonexistent Memory P rocessing Like it s predecessors, the 21264/EV67 can ge nerate refere nces to nonexist ent (NXM) memory or I /O space. However , unlike the earlier Al[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–39 Syste m Port T able 4–32 sh ows each 21 264/EV67 c ommand, with NXM add resses , and the appropri - ate system res pons e. Table 4–32 21264/E V67 Commands with N XM Addresses and System Response 21264/EV6 7 Command NXM Address System/21 264/EV67 Response ProbeR[...]

4–40 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Syste m Port 4.7.1 0 Order ing of Sy stem P ort T ransa ctio ns This sec tion descri bes ordering of system port tr ansactions. The two classe s of transac - tion s are listed he re: • 21264/EV67 c omm ands and syste m probes • System probes and SysDc transfer[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–41 Syste m Port • Probes th at invali date loc ked blocks d o not genera te a ReadBlkMod c ommand. The 21264/EV67 f ails the STx_ C instruction as defined in t he Alpha Ar chitectur e Handbook, V ersion 4 . • All re ad co mmands (RdB lk, R d BlkM od, F etc h, Inva[...]

4–42 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Bcache Port 4.7.10.2 System Pr obes and SysD c Commands Ordering of cache transacti ons at the system seri alizati on point must be reflect ed in the 21264/EV67 c ache system. T able 4–34 sh ows the rules that a system mu st follow to control the order of cache [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–43 Bcache Port The Bcache supports the following mult iples of th e GCLK period: 1.5X ( dual-data mode only), 2X, 2.5 X, 3X, 3.5X, 4X, 5X, 6X, 7X, and 8X. Ho w ever , the 21264/EV67 imposes a maximum Bcac he clock period bas ed on the SYSCLK ratio. T able 4–35 lists[...]

4–44 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Bcache Port 4.8. 2 Bca che Cl ocking For cloc king, the Bcache port pins ca n be divided i nto three gr oups. 1. The Bcache ind ex pins (address and control) are reference d to Int_Ad d_BcClk, an intern al version of the Bcache fo rwarded clock. The index pins are[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–45 Bcache Port BcT agShar ed_H BcT agV alid_H 3. The Bcache clock p ins ( BcDataOutClk _ x [3:0] and BcT agOutClk _ x ) clock the index and data pins at th e SSRAMs. These clocks ca n be delayed from In t _D a t a _B c C lk f r om 0 to 2 GCLK phases (half cycles) us i[...]

4–46 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Bcache Port 3. BC_FDBK_EN[7:0] T o program th ese three CSRs, the programmer must k now the bit-rate of the Bcache data, a nd whether o nly the ri sing edge or both edg es of the clock are used to l atch data. For exampl e, a 200-MHz late -write SSRAM has a data p[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–47 Bcache Port In addit ion to programming the clock CSRs, the d ata-sample/dri ve Cbox CSRs, at the pads, mu st be set appropr iately . T able 4–41 lists th ese CSRs and pro vides their pro - grammed val ue. 4.8. 3 Bca che T ransactions The Cbox uses t he progr amm[...]

4–48 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Bcache Port have be en programme d for the Bcache clock period, and with satis factory de lay param- eters f or the SSRAM setup/ hold Bcache ad dress latch requirements , a Bcache read command proc eeds through the 2 1264/EV67 Cbox as f ollows: 1. When the 21264/ [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–49 Bcache Port priate programmi ng of the Bcache cloc k period and dela y paramet ers to satisfy SSRAM setup/h old require ments of the Bca che address l atch, a Bcache writ e transact ion pro- ceeds t hrough the Cbox a s follows: 1. The Cbox trans mits the inde x and[...]

4–50 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Bcache Port Ratio The number of GCLK cycles per pea k Bcache bandwidth transfer . For example, a ratio of 2.5 means the peak Bcache bandwidth is 16 bytes for every 2.5 GCLK cycles. rd_wr The minimum spacing required between the read and write indices at the data/t[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–51 Bcache Port The Relationship Between Write-to-Rea d — BC_WR_RD_ BUBBLES and wr_rd The foll owing formulas calculate the relationshi p between the Cbox CSR BC_WR_RD_BUBBLES and wr_rd: wr_rd = (BC_WR_RD_BUB BLES – 1) * bcfr m or BC_WR_RD _BUBBLES = (( wr_rd + bcf[...]

4–52 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Bcache Port When the Cbox CSR BC_BANK_ENABLE[0] is not se t, the unused Bc Add_H[23:4 ] pins ar e tied to zero. Fo r example, when confi gured as a 4MB cac he, the 21264/E V 67 never ch anges BcAdd_H[23:22] f rom logic zero, and when BC_BANK_ENABLE[0] is asse rted[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Cache and Externa l Interfac es 4–53 Bcache Port T able 4–46 l ists the combina tion of control pin assertion for RAM_TYPE C. T able 4–47 l ists the combina tion of control pin assertion for RAM_TYPE D. Notes: 1. The NOP condition f or RAM_TYPE B is consis tent with burst ing nonPentium style S SR[...]

4–54 Cache and Externa l Interfa ces Alpha 212 64/EV 67 Hardwar e Referenc e Manual Interrupts 4.8. 5 Bca che Ba nking Bcache ban king is possibl e by decoding the i ndex MSB (as deter mined by Cbox CSR BC_SIZE[3:0 ]) and asserti ng Cbox CSR BC_BANK_ENABLE[0]. T o facili tate bank- ing, the 21264/EV67 provides the complement of t he MSB bit in th[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–1 5 Internal Proces sor Registers This chap ter descri bes 21264/EV67 in ternal proce ssor register s (IPRs). They are sepa- rated int o the following c ircuit logic g roups: Ebox, Ibox, Mbox, and Cbox. The gray a reas in regist er figures indicate rese rved fields. [...]

5–2 Intern al Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Instruction V A format IV A_FORM 0000 011 1 5 RO 0L 3 Current mode CM 0000 1 001 4 R W 0L 3 Inte rrupt en able I ER 0000 1010 4 R W 0L 3 Interrupt enable and current mode IER_CM 00 00 10xx 4 R W 0L 3 Software interrupt request SIRR 0000 1 100 4 R W 0L 3 Interrupt s[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–3 Ebox IPRs 5.1 Ebox IPRs This sec tion descri bes the inte rnal processor registers t hat control Ebo x functions. 5.1.1 Cycle Counter Register – CC The cycle counter regi ster (CC) is a read-write r egister . The lower h alf of CC is a counter that, when enabled [...]

5–4 Intern al Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Ebox IPRs T able 5– 2 describes th e CC_CTL register f ields. 5.1. 3 Virtua l Address Regi ster – V A The virt ual address register (V A) is a rea d-only regis ter . When a DTB mis s or fault occurs, t he a sso ciated ef f ective virt ual add re ss i s wri t te[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–5 Ebox IPRs T able 5– 3 describes th e virtual add ress control register fi elds. 5.1.5 Virtual Addre ss Format Regist er – V A_FORM The virt ual address format regis ter (V A_FORM) is a read-only r egister . It contain s the virtua l page table entry address de [...]

5–6 Intern al Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Ibox IPRs Figure 5–6 Virtual A ddress Format Re gister (VA_4 8 = 1, VA_FORM_32 = 0) Figure 5– 7 shows V A_FORM when V A_CTL(V A_48) equals 0 and V A_CTL(V A_FORM_32) equals 1 . Figure 5–7 Virtual A ddress Format Re gister (VA_4 8 = 0, VA_FORM_32 = 1) 5.2 Ibox[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–7 Ibox IPRs Figure 5–9 ITB PTE Arra y Write Register 5.2.3 ITB Invali date All Process (ASM=0) Register – ITB_IAP The IT B invali date all pr ocess registe r (ITB_IAP) is a pseudo registe r that, when wri t- ten to , inv al ida te s all ITB e nt ries who se ASM b[...]

5–8 Intern al Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Ibox IPRs 5.2.6 P rofi l eMe PC Regist er – PMPC The Profi leMe PC register (P MPC) is a read-only r egister that c ontains the PC of the last pr ofiled ins truction. Additi onal informat ion is avai lable in the I_ST A T and PCTR_CTL regis ter descripti ons. Usa[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–9 Ibox IPRs 5.2.8 Instruction Virtual Ad dress Format Register — IV A_FORM The inst ruction vir tual address fo rmat regist er (IV A_FORM) is a read-only regi ster . It contain s the virtua l P TE addr ess derived fro m the faultin g virtual ad dress stored in the [...]

5–10 Internal Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Ibox IPRs Figure 5–16 Interrupt Enable and C urrent Proc essor Mode Regist er T able 5– 5 describes th e interrupt e nable and cur rent process or mode regist er fields. 5.2.10 Software Interrupt Request Register – SIRR The so ftwa re in terr upt re que st re[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–1 1 Ibox IPRs Figure 5–17 Software Interrupt Reques t Register T able 5– 6 describes th e software int errupt request register fields. 5.2.1 1 Inter rupt Summ ary Re gister – I SUM The inte rrupt summary r egister (ISUM) is a read-only register t hat records al[...]

5–12 Internal Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Ibox IPRs T able 5– 7 describes th e interrupt s ummary regis ter fields. 5.2.12 Hardware Interrupt Cl ear Register – HW_INT_CLR The h ar dwa re inte rru pt cle ar re gis te r (H W_ INT_ C LR) is a wr ite- only r egi ster u sed to clear ed ge-sensi tive interr [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–13 Ibox IPRs T able 5– 8 describes th e hardware int errupt clear r egister fi elds. 5.2.13 Excepti on S ummar y Register – EXC_S UM The except ion summary regi ster (EXC_ SUM) is a read -only register that conta ins informat ion about ins tructions th at have tr[...]

5–14 Internal Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Ibox IPRs Figure 5–20 Exc eption Summary Register T able 5– 9 describes th e exception summar y register fields. Table 5–9 E xception Summary Regis ter Fields Descr iption Name Extent Type Description SEXT(SET_IOV) [63:48 ] RO, 0 Sign-extend ed value of bi t [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–15 Ibox IPRs 5.2. 14 P AL Base Re gister – P AL_BASE The P AL base regis ter (P AL_BASE) is a read-write re gist er that contai ns the bas e phys- ical add ress for P ALcode. Its cont ent s are cleare d by chip reset but are not c le are d after waking up f rom sle[...]

5–16 Internal Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Ibox IPRs Figure 5–22 I box Control Register T able 5– 11 describes th e Ibox control r egister fi elds. Table 5–11 Ibox Control Register Fie lds Description Name Extent Type Description SEXT(VP TB[47]) [63:48 ] R W ,0 Sign ext ended VP TB[47]. VP TB[47:30] [[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–17 Ibox IPRs MCH K_EN [21] RW ,0 Machine check enable — s et to enable machine checks. ST_W AIT_64K [20] R W ,0 The stW ait table is used to reduce lo ad/s tore order traps . When set, the stW ait table is cleared after 64K cycles. When clear , the stW ait table is[...]

5–18 Internal Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Ibox IPRs 5.2. 16 Ibox St atus Register – I_ST A T The Ibox s tatus regis ter (I_ST A T) is a read /write-1-t o-clear regis ter that co ntains Ibox status information. Usage of I _ST A T in performanc e monitoring i s described in Section 6.10 . Figure 5– 23 sh[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–19 Ibox IPRs Figure 5–23 I box Status Register T able 5– 12 describes the Ibox status register fie lds. Table 5–12 Ibox Status Register Fields Description Name Extent Ty pe Description Reserved [63:41] RO Reser ved for Compaq. MIS [40] RO ProfileMe Mispredict T[...]

5–20 Internal Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Ibox IPRs TRAP TYPE[3:0] [37:34 ] RO ProfileMe T rap T ypes. If the profiled instruction caused a trap (indicated by I_ST A T[TRP]), th is field indicates the trap type as list ed here: Va l u e T rap T ype 0R e p l a y 1 I nvalid (unus ed) 2 DTB Double miss (3 lev[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–21 Ibox IPRs 5.2.17 Icache Fl ush Register – IC_FLUSH The Icach e flush regi ster (IC_FLUSH) is a pseudo regis ter . W riting to thi s register invali dates all Icac he blocks. The cach e is flushed when t he next HW_RET/ST ALL instru ction is re tired. See Sec tio[...]

5–22 Internal Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Ibox IPRs Figure 5–24 Process Conte xt Register T able 5– 14 describes the process cont ext register fields. Table 5–14 Process Conte xt Register Fields Des cription Name Extent Type Description Reserved [63:47] —— ASN[7:0] [46:39 ] R W Address spac e num[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–23 Ibox IPRs 5.2.22 Performance Counter Control Register – PCTR_CTL The perf ormance counter control re gister (PCTR_CTL) is a read-writ e register tha t control s the functi on of the perfor mance counters for either aggregate count ing or Pro- fileMe sampli ng co[...]

5–24 Internal Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Ibox IPRs T able 5– 15 describes the performance c ounter control register f ields. Table 5–15 Performance Counter Control Re gister Fields Desc ription Name Ex tent Type Description SEXT(PCTR0_CTL[47] ) [63:48] RO When read, this field is si gn extended from P[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–25 Mbox IPRs 5.3 Mbox IPRs This sec tion descri bes the inte rnal processor registers t hat control Mbox f unctions. 5.3. 1 DTB T ag A rray Wri te Registers 0 and 1 – DTB_T A G0, DTB_T AG1 The DTB tag a rray write regist ers 0 and 1 (DTB_T AG0 and DTB_T AG1) are wr[...]

5–26 Internal Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Mbox IPRs 5.3.2 DTB P TE Arra y Writ e Regist ers 0 and 1 – DTB_PT E0 , DTB_P T E1 The D T B P TE a rr ay w rit e regi ster s 0 a nd 1 (D TB_ P TE0 a nd DT B _P TE1 ) are r egi ster s through which the DTB P TE ar rays are writ ten. The ent ries to be written are[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–27 Mbox IPRs T able 5–17 de scribes the DTB_AL TMODE register fields. 5.3.4 Dstream TB Inval idate Al l Process (ASM=0) Re gister – DT B_IAP The Ds tre am tr ansla tion b uffer in vali date all p roce ss (A SM=0 ) re giste r (DT B_IA P) is a write- onl y pseu do [...]

5–28 Internal Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Mbox IPRs 5.3.7 Dstream TB Address Sp ace Number Regis ters 0 a nd 1 – DTB_ASN0,1 The Dstre am translation b uffer a ddress space number register s (DTB_ASN0 and DTB_ASN1) are wr ite-only regi sters that should be writ ten with the addr ess space numb er (ASN) of[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–29 Mbox IPRs Note: The R a fiel d of the instr uct ion that tr igg ere d the e rro r can be ob tai ned fr om the Ibox EXC_SUM register . 5.3.9 Mbox Control Register – M_CTL The Mbox cont r ol register ( M_ CTL) i s a write-onl y r egi st er . Its contents ar e c le[...]

5–30 Internal Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Mbox IPRs T able 5– 19 describes the Mbox control r egister field s. Note: Superpage access es are only al lo wed in ker nel mode . Non-ker nel mode r ef- erences to superpage s result in access violati ons. 5.3.10 Dcach e Cont rol Register – DC_CTL The Dcache [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–31 Mbox IPRs Figure 5–33 Dcache Control Regi ster T able 5– 20 describes the Dcache contro l register fields. 5.3.1 1 Dcache St atus Regi ster – DC _ST A T The Dcache status regi ster (DC_ST A T) is a re ad-write re gister . If a Dcache ta g parity error or d a[...]

5–32 Internal Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Cbox CSRs and IPRs Figure 5–34 Dcache St atus Register T able 5– 21 describes the Dcache statu s register fields. 5.4 Cb ox CSRs and IPRs This sec tion descri bes the Cbox CSRs an d IPRs. The C b ox c o nfi gur at ion re gis ters are s pli t into t hre e sh if [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–33 Cbox CSRs and IPRs 5.4.1 Cbox Data Register – C_DA T A Figure 5– 35 shows the Cbox dat a register . Figure 5–35 Cbox Data Register T able 5– 22 describes the Cbox data regi ster fields. 5.4.2 Cbox Shift Register – C_SHFT Figure 5– 36 shows the Cbox shi[...]

5–34 Internal Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Cbox CSRs and IPRs • Only a bri ef description of each CSR is given. Th e functional descr iption of these CSRs is cont ained in Chapter 4. • The o rd er of m ulti bit v e cto rs is [MS B:L SB], s o th e L SB is firs t b it in th e Cbo x chain . T able 5–24 d[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–35 Cbox CSRs and IPRs DUP_T AG_ENABLE Duplicate CSR. SKEWED _ FILL_ MODE Du plicate C SR. BC_RDVICTIM Duplicate CSR. SKEWED _ FILL_ MODE Du plicate C SR. BC_RDVICTIM Duplicate CSR. BC_CLEAN_VICTIM Duplicate CSR. DUP_T AG_MODE Duplicate CSR. SKEWED _ FILL_ MODE Du pli[...]

5–36 Internal Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Cbox CSRs and IPRs BC_T AG_DDM_RISE_EN[0] Enables the update of the 21264/EV67 Bcache tag ou tputs based on the rising edge of the fo rwarded clock. BC_CLKFWD_ENABLE[0] Enable clock forwarding on the Bcache interface. BC_RCV_MUX_CNT_PRESET[0:1] Initial value fo r t[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–37 Cbox CSRs and IPRs SYS_ D DM_F AL L_E N D u plic ate CSR . SYS_ D DM _R IS E_ EN D upli cate C SR. SYS_CLKFWD_ENABLE Duplicate CSR. SYS_RCV_MUX_CNT_PRES ET[0:1] Duplicate CSR. SYS_C LK_D E LA Y[0: 1] Duplicate C SR. SYS_ D DMR _ENA BLE Duplicate CSR. SYS_ D DMF _E[...]

5–38 Internal Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Cbox CSRs and IPRs 5.4.4 Cbox WRITE_MANY Chain Description The WRITE_MANY chain o rder is contained in T able 5–25. Note th e following : • Many CSRs are dupl icated for ea se of hardware i m plementa tion. These CSR names are ind icated in it alics and have t [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–39 Cbox CSRs and IPRs T able 5–25 de scribes the Cbox WRITE_MANY chain order f rom LSB to MSB. Figure 5–37 shows an example of P ALcode use d to write t o the WRITE_MANY chain. Figure 5–37 WRITE_MA NY Chain Write Tr ansaction Exa mple ; ; Initialize the Bcache [...]

5–40 Internal Proc essor Reg isters Alpha 212 64/EV 67 Hardwar e Referenc e Manual Cbox CSRs and IPRs ; SET_DIRTY_ENABLE = 6 ; BC_BANK_ENABLE = 1 ; BC_WRT_STS = 0 ; ; The value for the write_many chain i s based on Table 5–25. ; ; The value is sampled from MSB, 6 bit s at a time, as it is written ; to EV6__DATA. Therefore, before the value can [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Inte r nal Proc essor Reg isters 5–41 Cbox CSRs and IPRs 5.4.5 Cbox Read Register (IP R) Description The Cbox re ad reg ister is r ead 6 bit s at a time. T able 5–26 sho ws the ordering from LSB to MSB. Table 5–26 Cbox Read IPR Fields Descr iption Name Descript ion C_SYNDRO ME_1[ 7: 0] If CMD is C[...]

[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Privile ged Arc hitectur e Library Code 6–1 6 Priv ile ged Architec ture Library Cod e This chapt er describe s the 21264/EV67 privi leged archi tecture library code (P ALcode). The chapt er is or ganized as f ollows: • P ALcode descript ion • P AL m od e en vir onm ent • Required P ALcode f unc[...]

6–2 Pri vileged Architect ure Libr ary Cod e Alpha 212 64/EV 67 Hardwar e Referenc e Manual PALmode Environment • There ar e some necessar y support fun ctions that ar e too complex to implement direct ly in a proce ssor chip’ s hardwar e, but that ca nnot be handled by a normal operati ng system soft ware routine. Routines to fi ll the tran [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Privile ged Arc hitectur e Library Code 6–3 Required PALcode Function Codes When exe cuting in P ALmode, th ere are certai n restricti ons for using the privileged instru ctions becau se P ALmode gives the programmer co m plete access to many o f the intern al details of the 21264/EV6 7. Refer to Sect[...]

6–4 Pri vileged Architect ure Libr ary Cod e Alpha 212 64/EV 67 Hardwar e Referenc e Manual Opcodes Re s erved for P ALco de Figure 6–1 HW_LD Instruction Format T able 6– 3 describes th e HW_LD instructio n fields. 6.4.2 HW_S T In struc tion P ALcode uses t he HW_ST instr uction to ac cess memory outside the realm of normal Alpha memory manag[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Privile ged Arc hitectur e Library Code 6–5 Opcodes Reserved for PALcode T able 6– 4 describes th e HW_ST instruct ion fields. 6.4.3 HW _RET Inst ructi on The HW_R ET instruction i s used to ret urn instruc tion flow to a sp ecified PC. The RB fiel d of th e HW _ RET inst ru cti on s p ecif ies an i[...]

6–6 Pri vileged Architect ure Libr ary Cod e Alpha 212 64/EV 67 Hardwar e Referenc e Manual Opcodes Re s erved for P ALco de Figure 6–3 HW_RET Instruction Format T able 6– 5 describes th e HW_RET instruct ion fields. 6.4.4 HW_MFPR and HW_MTPR Instructions The HW_MFPR and HW_MTP R i nst ru ct ions are used to acces s int er n al pro ces sor re[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Privile ged Arc hitectur e Library Code 6–7 Internal Pr ocessor Regist er Access Mechanisms T able 6–6 de scribes the HW _MFPR and HW_MTPR instructio ns fields. 6.5 Internal Processor Register A ccess Mechanisms This sec tion descri bes the hardware a nd software a ccess mechanis ms that are used f [...]

6–8 Pri vileged Architect ure Libr ary Cod e Alpha 212 64/EV 67 Hardwar e Referenc e Manual Intern a l Proc esso r Regi st er Ac cess Me chani sms 6.5.1 IPR Scoreboard Bit s In previ ous Alpha imple mentations, I PR registers w ere not score boarded in har dware. Software was required to schedule HW _MTPR and HW_MFPR instru ctions for e ach machi[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Privile ged Arc hitectur e Library Code 6–9 Internal Pr ocessor Regist er Access Mechanisms 6.5. 3 Hardware S tructure of Im plicitly W ritte n IPRs Implici tly written IPRs are physical ly built us ing only a singl e level of re gister , how- ever th e IPR has two h ardware states associated with it:[...]

6–10 Privileged Archite cture Li brary Cod e Alpha 212 64/EV 67 Hardwar e Referenc e Manual Intern a l Proc esso r Regi st er Ac cess Me chani sms For conve nience of i mple mentat ion, t here i s no IPR scor eboar d bit checki ng wit hin the same fetch bl ock (octaword-a ligned octaword) . • W ithin one fetch block, the re can be only one expl[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Privile ged Arc hitectur e Library Code 6–1 1 PALshadow Registers 6.5.6 Correct Ordering of Explici t Readers Followed by Implicit W riters Certain IPRs that are updated as a r esult of fa ulting memory opera tions requi re P AL- code ass ista nce to mai ntain order ing ag ainst newer ins tructio ns. [...]

6–12 Privileged Archite cture Li brary Cod e Alpha 212 64/EV 67 Hardwar e Referenc e Manual PALcode Entry Points 3. Correct actions mus t occur when the FPCR i s written by way o f a MT_FPCR instru ction. 6.7. 1 St atus Flag s The FPCR stat us bits in the 21264/EV67 are set wi th P ALcode assistance. Floating- poin t exc e ptio ns , f or w h ich [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Privile ged Arc hitectur e Library Code 6–13 PALcode Entry Points Each CALL_ P AL instruct ion incl udes a func tion fi eld that is used to calc ulate t he PC of its as sociated P ALcode entry p oint. The P A Lcode OPCDEC except ion flow will be invoked i f the CALL_P AL function f ield sati sfies any[...]

6–14 Privileged Archite cture Li brary Cod e Alpha 212 64/EV 67 Hardwar e Referenc e Manual Translation Buffer (TB) Fill Flows 6.9 T ranslation Buffer (TB) Fill Flows This sec tion shows the expe cted P ALcode flows fo r DTB miss and ITB miss. Fa m iliar- ity wit h 21264/EV67 IPRs is a ssumed. 6.9.1 DTB Fill Figure 6– 5 shows single -miss DTB i[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Privile ged Arc hitectur e Library Code 6–15 Translation Buffer (TB) Fill Flows hw_mtp r p4, <EV6__DTB_PTE0 ! ^x44> ; (0,4,2,6) (0L) write pte0 hw_mtp r p4, <EV6__DTB_PTE1 ! ^x22> ; (3,7,1,5) (1L) write pte1 ASSUME <tb_mb_en + pte_eco> ne 2 .if ne pte_eco bne p7, trap__dtbm_singl e_m[...]

6–16 Privileged Archite cture Li brary Cod e Alpha 212 64/EV 67 Hardwar e Referenc e Manual Translation Buffer (TB) Fill Flows • The c on ditio na l b ranch is p la ced in the co de so tha t a ll of th e MT PR in st ruc ti ons are is sued and retired or none of them ar e issue d and retired. This a llows the TB f ill hardware to update the TB w[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Privile ged Arc hitectur e Library Code 6–17 Performance Counter Support srl r4, #OSF_PTE__PF N__S, r6 ; (xU) shif t PFN to <0> sll r6, #EV6__ITB_PT E__PFN__S, r6 ; (x U) shift PFN i nto place and r4, #<1@OSF_PTE_ _FOE__S>, r7 ; (xL) get FOE bit blbc r4, trap__invali d_ipte ; (xU) invalid [...]

6–18 Privileged Archite cture Li brary Cod e Alpha 212 64/EV 67 Hardwar e Referenc e Manual Performance Counter Support Profil eMe mode, supports a new way of statis tically sa mpling individua l instruct ions during pr ogram executi on. This mode count s events tr iggered by a tar geted i nflight instru ction. Counter s upport uses t he hardware[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Privile ged Arc hitectur e Library Code 6–19 Performance Counter Support The legal range for PCTR0 w hen writing th e IPR is 0 : (2**20-16). The legal range for PCTR1 w hen writing th e IPR is 0 : (2**20-4). 6.10.2.2 Oper ation 1. Setup The foll owing IPRs need t o be set up by P ALcode inst ructions.[...]

6–20 Privileged Archite cture Li brary Cod e Alpha 212 64/EV 67 Hardwar e Referenc e Manual Performance Counter Support 6.10.2.3 A ggregate Counting Mode Description 6.10 .2.3. 1 Cycle co unti ng Coun t s cy cles . PCTR0 is inc remented by the number of cycl es counted, th at is, 1. 6.10.2.3.2 Retired instructions cycles PCTR0 is inc remented by [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Privile ged Arc hitectur e Library Code 6–21 Performance Counter Support The C M OV instru cti on i s deco mpo se d in to t w o vali d fet che d in st ruc tio ns tha t, in t he absence of stalls, a re fetched in c onsecutive cy cles. See T able 6–12 for more informa- tion. 6.10.3.2 Oper ation 1. Set[...]

6–22 Privileged Archite cture Li brary Cod e Alpha 212 64/EV 67 Hardwar e Referenc e Manual Performance Counter Support For in stru cti ons th at ca use a tr ap, the las t cyc le in the wi ndo w is th e 2nd cy cle afte r the tra p. Mispredict ed branches ar e included in th is category . For n ont ra ppi ng i ns tru ction s th at re tire , the la[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Privile ged Arc hitectur e Library Code 6–23 Performance Counter Support 6.10.3.3 P rofileMe C ounting Mode Description 6.10 .3.3. 1 Cycle co unti ng In Profi leMe mode, either c ounter counts cyc les during the wi ndow of the profi led instru ction. 6.10.3.3.2 Inum retire delay cycles This inp ut is [...]

6–24 Privileged Archite cture Li brary Cod e Alpha 212 64/EV 67 Hardwar e Referenc e Manual Performance Counter Support 6.10.3.4 C ounter Modes for ProfileMe Mode T able 6– 14 shows the coun ter modes that ar e used with Pr ofileMe mode. Table 6–14 ProfileMe Mode P CTR_CTL Input Selec t Fields SL0[ 4] SL 1[3 :2] PCT R0 PCTR 1 1 00 Retired ins[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Initial izati on and Conf igu ra tio n 7–1 7 Initialization and Configuration This chap ter provides information on 21264/EV67-spe cific micropro cessor syste m ini- tiali zation and confi guration. It is org anized as foll ows: • Power -up reset flow • Faul t res et fl ow • Ener gy star cer tif[...]

7–2 Initia liza tion an d Confi guration Alpha 212 64/EV 67 Hardwar e Referenc e Manual Power-Up Rese t Flow and the Reset_L and DCOK_ H Pins 1. The clock for warding and sy stem clock rat io configurat ion informati on is loaded onto the 21264/EV67. See Sec tion 7.1.2. 2. The interna l PLL is ramp ed up to operat ing frequency . 3. The i ntern a[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Initial izati on and Conf igu ra tio n 7–3 Power-Up Reset Flow and the Reset_L and DCOK_H Pins Figure 7–1 Power-Up Timing Sequence 7.1.1 Power Sequencing and Reset St ate for Signal Pins Power s equencing and avoi ding potenti al failure mech anisms is desc ribed in Sect ion 9.3. The rese t state fo[...]

7–4 Initia liza tion an d Confi guration Alpha 212 64/EV 67 Hardwar e Referenc e Manual Power-Up Rese t Flow and the Reset_L and DCOK_ H Pins In add iti on, a s po w er is be ing ramp e d, Reset_L must be as serted — th is allows th e 21264/EV67 t o r eset intern al s tate. Once the tar get voltage leve ls are at ta ined, systems should ass ert[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Initial izati on and Conf igu ra tio n 7–5 Power-Up Reset Flow and the Reset_L and DCOK_H Pins T able 7– 3 summarizes th e pins and the suggested/r equired initi alization s tate. Most of this i nformation is supplied by pl acing (swit ch-selecta ble or hardwired ) weak pull-up s or pul l-downs on t[...]

7–6 Initia liza tion an d Confi guration Alpha 212 64/EV 67 Hardwar e Referenc e Manual Power-Up Rese t Flow and the Reset_L and DCOK_ H Pins 7.1.3 PLL Ramp Up After t he configuration i s loaded through t he IRQ_H pins, the next ph ase in the power up flow i s the internal PLL r amp up sequence. Ra m ping up of the PLL is required to guarant ee [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Initial izati on and Conf igu ra tio n 7–7 Power-Up Reset Flow and the Reset_L and DCOK_H Pins As BiST completes, the Te s t S t a t _ H pin is held l ow for 16 GCLK cy cles. Then, if BiST succeeds , the pin remai ns low . Otherwis e, it is ass erted. After successfully c ompleting BiST , the 21264/EV[...]

7–8 Initia liza tion an d Confi guration Alpha 212 64/EV 67 Hardwar e Referenc e Manual Fault Reset Flow 7.2 Fault Reset Flow The faul t r eset sequen ce of op eration is trigge red b y t he as sert ion of the ClkFwdRst _H signal line. Figure 7–2 shows the fa ult reset s equence of operat ion. The reset state machine i s initiall y in RUN state[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Initial izati on and Conf igu ra tio n 7–9 Energy Star Certification and Sleep Mode Flow Figure 7–2 Fault Re set Sequence of Operation 7.3 Energ y St ar Certification and Sleep Mode Flow The 21264/ EV67 is Energy S tar compl iant. Ener gy Star is a program administe red by the Envir onmental Prot ec[...]

7–10 Initializa tion an d Confi guration Alpha 212 64/EV 67 Hardwar e Referenc e Manual Energy Star Certification and Sleep Mode Flow After t he PLL has fini shed ramping down, the reset state machi ne enters th e W AIT_INTERRUP T state. Not e the effe cts of the e ntry into th at state on th e IPRs liste d in T able 7–6. Note that Interrupt en[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Initial izati on and Conf igu ra tio n 7–1 1 Warm Reset Flow Figure 7–3 Sleep M ode Sequence of Operation T able 7– 7 describes e ach signal and co nstraint f or the sleep mo de sequence. 7.4 W arm Reset Flow The warm reset sequence o f operation is triggere d by the asser tion of the Rese t_L sig[...]

7–12 Initializa tion an d Confi guration Alpha 212 64/EV 67 Hardwar e Referenc e Manual Array Init ial izati on The 21264/ EV67 waits until Res et_L is deassert ed before t ransitioning f rom the W AIT_RESET state. Th e 21264/EV67 ramps up the PLL unt il the sta te machine ent ers the W AIT_ClkFwdRst0 st ate. Note that t he system must asse rt Cl[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Initial izati on and Conf igu ra tio n 7–13 Initialization Mode Processing Except f or INIT_MODE, all th e CSR register s have been des cribed in earli er section s. When asser ted, INIT_MODE has the f ollowing behavior : • Cach e bl oc k up d ate s to t he Dc ach e set t he b lock t o th e Cl ea n [...]

7–14 Initializa tion an d Confi guration Alpha 212 64/EV 67 Hardwar e Referenc e Manual External Interface Initialization SweepMem ory: ;Wri te good parity/ecc to memo ry by ; wri ting a all me mory location s. This is ;done by WH64 of m emory address es turn_on_ bcache: ;bc_ena ble_a 0 ;bc_size_a Actual Bcache size ;zeroblk_e nable_a 3 ;set_dirt[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Initial izati on and Conf igu ra tio n 7–15 Internal Proces sor Register Powe r-Up Reset S t ate ITB_IAP ITB invalidate-all (ASM=0) X — ITB_IA ITB invalidate all X Must be written to in P ALcode. ITB_IS ITB invalid ate si ngle X — PMPC ProfileM ePC X — EXC_ADDR Exception address X — IV A_FORM [...]

7–16 Initializa tion an d Confi guration Alpha 212 64/EV 67 Hardwar e Referenc e Manual IEEE 11 49.1 Test Port Reset 7.9 IEEE 1 149.1 T est Port Reset Signal Tr s t _ L must be asse rted when power ing up the 21264/EV67. Tr s t _ L must not be deass erted prior to assertion o f DCOK _H . Tr s t _ L can remain as serted duri ng nor- mal opera tion[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Initial izati on and Conf igu ra tio n 7–17 Reset S tate Ma chine Figure 7–5 21264/EV 67 Reset State Machine State Diagram Table 7–11 21264/E V67 Reset State Mac hine State Des criptions State Name Descript ion COLD Chip cold. Tran sitioned to W AIT_SETTLE with assertion of Reset_L , PLL_VDD, and [...]

7–18 Initializa tion an d Confi guration Alpha 212 64/EV 67 Hardwar e Referenc e Manual Reset St ate Ma chine RAMP2 Trig gered by the duration counter reach ing 4108 cycles, the X div and Z div divisors are changed to 1 and 2, respectively , and the frequency is increased. T he duration counter is reloaded to cou nt 8205-cycles. W AIT_ClkFwdRst0 [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Initial izati on and Conf igu ra tio n 7–19 Phase-Lock Loop (PLL) Functional Description 7.1 1 Phase-Lock Loop (PLL) Function al Description The PLL multipl ies the clock f requency of a dif ferential i nput reference cl ock and aligns the pha se o f its output t o th at dif feren ti al inp ut clo ck.[...]

7–20 Initializa tion an d Confi guration Alpha 212 64/EV 67 Hardwar e Referenc e Manual Phase-Lock Loop (PLL) Functional Description T able 7– 12 shows the allowa ble ClkIn_ x frequencies for a given ope rating frequen cy of the 21 264/EV67 and the Y di v divider . For exa m ple, to set the 21264/EV67 GCLK frequen cy to 500 MHz with a ClkIn _ x[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Error Detecti on and Error Handling 8–1 8 Error Detection and Error Handling This chap ter gives an overview of th e 21264/EV67 error detection an d error handl ing mechanisms , and is orga nized as follows : • Data error c orr ec tio n cod e • Icache d ata or tag pa rity error • Dcache ta g par[...]

8–2 Error Detection and Er ror Handling Alpha 212 64/EV 67 Hardwar e Referenc e Manual Data Error Correction Code 8.1 Dat a Error Correction Code The 21264/EV67 supp ort s a quadword error co rre cti on co de (ECC) for the syst em dat a bus. ECC is ge ner ate d by th e 21264 /EV67 for all memory writ e t ran sact ion s (W rV icti mBl k) emitted f[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Error Detecti on and Error Handling 8–3 Dcache Data Single-Bit Correctable EC C Error 3. The virtual address ass ociated with the error is avai lable in the V A register . 4. The P ALcode flush es the error bl ock by temporar ily disabling DC_CTL[DCT AG_P A R_EN] and ev icting the block us ing two HW_[...]

8–4 Error Detection and Er ror Handling Alpha 212 64/EV 67 Hardwar e Referenc e Manual Dcache Store Second Error – C_ADDR contains bits [19:6] of the Dca che address of the b lock that conta ins the err or (bits [42: 20] of the phys ical addres s are not update d). – DC_ST A T[ECC_ERR_LD] is set. – The load qu eue retrie s the load and rewr[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Error Detecti on and Error Handling 8–5 Bcache Tag Parity Error • C_ST A T[DC_PERR] is set. • C_ADDR contains bit s [ 42: 6] of t he Dca che duplicat e ta g ad dress of the bl ock that contain s the error . • When enable d, a mac hine che ck ( MCHK) is p ost ed. Th e MCHK is ta ken wh en no t in[...]

8–6 Error Detection and Er ror Handling Alpha 212 64/EV 67 Hardwar e Referenc e Manual Bcache Data Single-Bit Correctable ECC Error 8.8.2 Dcache Fill from B cache If the qua dw or d in er ror i s no t u sed to sat isfy a lo ad ins tru ctio n, a h ardw are recov ery flow is not invoked. The quad word in error , and its assoc iated check bits, a re[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Error Detecti on and Error Handling 8–7 Memory/System Port Si ng le-Bit Data Correctable ECC Error The Bcache acc ess error i s wri t ten out to memory and is subs equ ently detect ed and c or- rected by the next con sumer of the da ta. • No correc tion is made. • No status i s logged (C_ST A T = [...]

8–8 Error Detection and Er ror Handling Alpha 212 64/EV 67 Hardwar e Referenc e Manual Bcache Data Single-Bit Correc table ECC Error on a Probe If the qua dw or d in er ror i s us ed to s atis fy a lo ad i nstr u ctio n, th en t he flo w is ve ry s imi - lar to that used for a Dcache ECC erro r: • The load i nstruction ’ s desti nation regist[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Error Detecti on and Error Handling 8–9 Double-Bit Fill Errors 8.1 1 Double-Bit Fill E rrors Double-bi t errors f or fills a re detected, but not correct ed, in the 21264/EV67 . The fol- lowing ev ents may cause a double-bit fill error: • Icach e fi ll f rom B c ach e • Dcache fi ll from Bcache ?[...]

8–10 Erro r De tection and Error Handli ng Alpha 212 64/EV 67 Hardwar e Referenc e Manual Error Case Su mmary Dcache single-bit ECC error on speculative load CRD DC_ST A T[ECC_ERR_L D] C_ST A T contains zero None Log as C RD Dcache single-bit ECC error on small store CRD DC_ST A T[ECC_ERR_ST] Corrected and scrubbed Log as CRD Dcache single-bit EC[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Error Detecti on and Error Handling 8–1 1 Error Case Summary Bcache double-bit error on Dcach e fill MCHK 1 C_ST A T[DSTREAM _BC_DB L] C_ADDR[error address] 4 None Log as MCHK Memory doubl e-bit error on I cache fill MCHK 1 C_ST A T[ISTREA M_MEM_DB L] C_ADDR[error address] 4 None Log as MCHK Memory do[...]

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Alpha 21264/E V67 Hard ware Ref erence Manual Electric al Data 9–1 9 Electric al Dat a This cha pter desc ri bes the elect rical char acteristi cs of the 212 64/ EV67 a nd i ts inte rf ace pins. The chapter cont ains both ac a nd dc electrica l character istics and power supply consider ations, and i s organ ized as follows: • Electr ical chara[...]

9–2 Elec trical Data Alpha 212 64/EV 67 Hardwar e Referenc e Manual DC Characte ristics 9.2 DC Characteristics This sec tion contain s the dc char acteristics for the 21264/ EV67. The 21264/EV67 p ins can be di vided into 10 distinct elec trical si gnal types. The mapping between t hese sig- nal type s and the package pin s is shown in Cha pt er [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Electric al Data 9–3 DC Characteristics Note: Current out of a 21264/EV67 pi n is represent ed by a – symbol while a + symbol i ndi cat es cur r ent f lowi ng int o a 2 1264/EV67 pin. Table 9–3 V DD (I_DC_POWER) Parameter Sym bol Description Test Conditions Minimum Maximum VDD Processo r core supp[...]

9–4 Elec trical Data Alpha 212 64/EV 67 Hardwar e Referenc e Manual DC Characte ristics Table 9–7 P in Type: Open-Drain Output Driver (O_OD) Parameter Symbol Des cription Test Conditions M inimum Maxi mum V OL Low-level output volta ge I OL = 70 mA —4 0 0 m V |I OZ | Hig h impe danc e outp ut c ur rent 0 < V < VD D — 150 µ A C OD Ope[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Electric al Data 9–5 Power Supply Sequencing and Avoiding Potential Failure Mechanisms 9.3 Power Supply Seq uencing and A voiding Poten tial Failure M ech- anisms Before t he power- on sequencing can occur , syst ems should ensu re that DCOK_H is deasser ted and Reset_ L is asserted. The n, systems ra[...]

9–6 Elec trical Data Alpha 212 64/EV 67 Hardwar e Referenc e Manual AC Characte ristics the tes ter environment and does not need t o be disabled. EV6Clk_L and EV6Clk_H are out puts that ar e both generated and consumed by the 21264/EV67; th us, VDD tracks for both the pro ducer and consumer . On the push -pull inte rfaces: • Disabli ng all out[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Electric al Data 9–7 AC Characteristics • The input voltage swing is V ref ± 0.40 V olts. • All outp ut skew data is based on simul ation into a 50- ohm transmissi on line that is terminated with 50 ohms to VDD/2 for Bcache timing , and with 50 ohms to VDD for al l othe r timi ng. T imings a re m[...]

9–8 Elec trical Data Alpha 212 64/EV 67 Hardwar e Referenc e Manual AC Characte ristics BcT agShared_H B_ DA_PP BcT a gInClk_H 400 ps 40 0 ps NA NA 1.0 V/ns BcT ag V alid_H B_ DA_PP BcT agInClk_H 40 0 ps 40 0 ps NA NA 1.0 V/ns BcT ag V alid_H B_ DA_PP BcT agOutClk_ x NA NA ± 300 ps 6 45 -55% NA BcT ag Dirty_ H B_DA_PP 38 -63% 8 NA BcT agShared_H[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Electric al Data 9–9 AC Characteristics 6 The TSkew value app l ies only when the BC_CLK_DELA Y[0:1] entry in the Cb ox WRITE_ONCE chain (T able 5–24) is set to zero phases of delay for Bcache clock. 7 The TSkew specified for BcA dd_H signals is only w ith respect to the associated clock. 8 The duty[...]

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Alpha 21264/E V67 Hard ware Ref erence Manual Thermal Managemen t 10–1 10 Thermal Management This chap ter descri bes the 21264/E V67 thermal ma nagement and the rmal design consider ations, and i s organ ized as follows: • Operating t emperature • Heat sin k specifica tions • Thermal de sign consider ations 10.1 Operating T emperature The [...]

10–2 Thermal Mana gement Alpha 212 64/EV 67 Hardwar e Referenc e Manual Operating Temperature T able 10 –2 lists th e values for the cente r of heat-si nk-to-amb ient ( θ c a) for the 21 264/ EV67 587-pi n PGA. T ables 10–3 thr ough 10–8 show the allowable T a (without exceedi ng T c ) at var ious airflows. Table 10–2 θ c a a t Various [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Thermal Managemen t 10–3 Heat Sink Spec ifications 10.2 Heat Sink Specificati ons Three heat sink t ypes are specif ied. The mounting ho les fo r all t hree ar e in li ne with t he cooling fins. Figure 10 –1 shows the heat s ink type 1, along wi th its approxi mate dimensions . Table 10–7 Maximum [...]

10–4 Thermal Mana gement Alpha 212 64/EV 67 Hardwar e Referenc e Manual Heat Sink Spe cifications Figure 10–1 Type 1 Heat Sink 25.4 mm (1.0 in) 32.5 mm (1.280 in) 80.5 mm (3.17 in) 80.5 mm (3.17 in) FM-06119.AI4[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Thermal Managemen t 10–5 Heat Sink Spec ifications Figure 10 –2 shows the heat s ink type 2, along wi th its approxi mate dimensions . Figure 10–2 Type 2 Heat Sink 25.4 mm (1.0 in) 44.5 mm (1.75) 81.0 mm (3.19 in) 81.0 mm (3.19 in) FM-06120.AI4[...]

10–6 Thermal Mana gement Alpha 212 64/EV 67 Hardwar e Referenc e Manual Heat Sink Spe cifications Figure 10 –3 shows heat sink type 3, along with i ts approximate d imensions. The cooli ng fins of heat sink type 3 are c ross-cut. Also, an 80 mm × 80 mm × 15 mm fan is att ached to heat si nk type 3. Figure 10–3 Type 3 Heat Sink 80.0 mm (3.15[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Thermal Managemen t 10–7 Thermal Design Considerations 10.3 Thermal Desig n Considerations Follow th ese guidelin es for printed circuit boa rd (PCB) component placement: • Orient t he 2126 4/EV67 on the PCB with the he at sink fin s al ign ed wit h th e ai rf low direct ion. • A void preheating a[...]

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Alpha 21264/E V67 Hard ware Ref erence Manual Testa bility a nd D iagnosti cs 11 – 1 11 T est ability and Diagnostic s This cha pter descri bes the 21264/ EV67 user- oriented test ability and diagnostic fea - tures. Th ese feature s include aut omatic power -up self-t est, Icache initialization from exter nal seri al RO Ms, and th e se rial dia g[...]

1 1–2 Tes tability and Diagno stic s Alpha 212 64/EV 67 Hardwar e Referenc e Manual SROM/Serial Diagnostic Terminal Port 1 1.2 SROM/S erial Diag nostic T ermin al P ort This port supports t w o funct ions. During powe r-up, it s upports automa tic initi alization of the Cbo x configurat ion registe rs and the Icach e from the syst em serial ROMs.[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Testa bility a nd D iagnosti cs 11 – 3 IEEE 114 9.1 Port On the re ceive side, while in native mode, an y transition on the Ibox I_CTL [SL_RCV], dri ven from the Sr omData_H pin, resul ts in a t rap to the P AL code inte r - rupt han dler . When in P ALmode, all interru pts are blocked. The interrupt [...]

1 1–4 Tes tability and Diagno stic s Alpha 212 64/EV 67 Hardwar e Referenc e Manual TestSt at_H Pin Figure 11–1 TAP Controller S tate Machine 1 1.4 T estS t at_H Pin The T estS tat_H pin serves two purposes. During powe r-up, it i ndicates BiST pas s/fail status . After power -up, it indi cates the 212 64/EV67 timeout event. The sy stem reset f[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Testa bility a nd D iagnosti cs 11 – 5 Power-Up Self-Te st and Initialization Figure 11–2 Te stStat_H Pin Timing During Power-Up Built-In Self-Test (BiST) Figure 11–3 Te stStat_H Pin Timing During Built-In Self-Initialization (BiSI) 1 1.5 Power-U p Self-T est and I nitializati on Upon poweri ng up[...]

1 1–6 Tes tability and Diagno stic s Alpha 212 64/EV 67 Hardwar e Referenc e Manual Power-Up Self-Test and Initial ization In the SROM re presented in Fi gure 1 1–4, the lengt h for fields Cbox Config Data(0,n) pl us MBZ(m,0) must equa l 367 bits. (If Cbox Config Data(0,n) is (0,366), MBZ woul d be zero.) For the 2 1264/EV67, Cbox Config Dat a [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Testa bility a nd D iagnosti cs 11 – 7 Notes on IE EE 1149. 1 Opera tion and C o mplia nce The inst ruction cach e lines are loa ded in the re verse order . If the fetch_count (9,0) is zer o, the n, n o inst ruct ion cach e lin es a re loa ded . Sin ce t he va lid b its ar e alr ead y cl ear ed by the[...]

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Alpha 21264/E V67 Hard ware Ref erence Manual Alpha Instru ction Set A–1 A Alpha Instruction Set This appe ndix provides a summary of the Alpha instruc tion set and des cribes the 21264/EV67 I EEE floating-point conformance. It i s organize d as follows: • Alpha ins truction su mmary • Reserved opcodes • IEEE floa ting-point ins tructions ?[...]

A–2 Alpha Instructi on Set Alpha 212 64/EV 67 Hardwar e Referenc e Manual Alpha Instruction Summa ry Qualifi ers for operat e instruct ions are shown in T able A–2. Qual ifiers fo r IEEE and V AX floating-poin t instruct ions are shown in T ables A–5 a nd A–6, respecti vely . Memory/ branch Mbr o o.h oo is the 6-bit op code field. h is the [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Alpha Instru ction Set A–3 Alpha Instruction Summa ry BSR Mbr 34 Branch to subrou tine CALL_PAL Pcd 00 Trap to PALc ode CMOVEQ Opr 11 .24 CMOVE if = zero CMOVGE Opr 11 .46 CMOVE if ≥ zero CMOVGT Opr 11 .66 CMOVE if > zero CMOVLBC Opr 11.16 CMOVE if lo w bit clear CMOVLBS Opr 11.14 CMOVE if lo w b[...]

A–4 Alpha Instructi on Set Alpha 212 64/EV 67 Hardwar e Referenc e Manual Alpha Instruction Summa ry CVTGQ F-P 15.0AF Convert G_floating to quadword CVTLQ F-P 17.010 Convert l ongword to quadword CVTQF F-P 15.0BC Convert qu adword to F_float ing CVTQG F-P 15.0BE Convert quadword t o G_floating CVTQL F-P 17.030 Con vert quadword to l ongword CVTQS[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Alpha Instru ction Set A–5 Alpha Instruction Summa ry FCMOVGT F-P 17.02F FCMOVE if > zero FCMOVLE F-P 17.02E FCMOVE if ≤ zero FCMOVLT F-P 17.02C FCMOVE if < zero FCMOVNE F-P 17.02B FCMOVE if ≠ zero FETCH Mfc 18.8000 Prefet ch data FETCH_M Mfc 18.A000 Prefetch data, modi fy intent FTOIS F-P 1[...]

A–6 Alpha Instructi on Set Alpha 212 64/EV 67 Hardwar e Referenc e Manual Alpha Instruction Summa ry LDS Mem 22 Load S_float ing LDT Mem 23 Load T_float ing LDWU Mem 0C Loa d zero-extended word MAXSB8 Opr 1C.3E Vecto r signed byte m aximum MAXSW4 Opr 1C.3F Vecto r signed word maximum MAXUB8 Opr 1C.3C Vector unsi gned byte maximum MAXUW4 Opr 1C.3D[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Alpha Instru ction Set A–7 Alpha Instruction Summa ry PKWB Opr 1C.36 Pack words to bytes RC Mfc 18.E000 Read and cl ear RET Mbr 1A.2 Return from subroutine RPCC Mfc 18.C000 Read proce ss cycle counter RS Mfc 18.F000 Read and se t S4ADDL Opr 10.02 Scaled add longwor d by 4 S4ADDQ Opr 10.22 Scaled add q[...]

A–8 Alpha Instructi on Set Alpha 212 64/EV 67 Hardwar e Referenc e Manual Reserved Op codes A.2 Reserved Opcodes This sec tion descr ibes t he opc odes t hat a re re served in t he Alpha a rchit ectur e. They can be reser ved for Compa q or for P ALcode. A.2.1 Opcode s Reserve d for Compaq T able A–3 lists opcodes r eserved for Compaq. STW Mem [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Alpha Instru ction Set A–9 IEEE Floating-Point Instructions A.2.2 Opcodes Reserved for P ALcode T able A–4 lists the 21264 /EV67-specifi c instruct ions. See Chapte r 2 for more info rmation. A.3 IEEE Floating-Point In structions T able A–5 lists the hexa decimal value of the 1 1-bit func tion cod[...]

A–10 Alpha Ins tructi on Set Alpha 212 64/EV 67 Hardwar e Referenc e Manual IEEE Floating-Point Instructions SQRTS 08B 00B 04B 0CB 18B 10B 14B 1CB SQRTT 0AB 02B 06B 0EB 1AB 12B 16B 1EB SUBS 08 1 0 01 041 0C1 181 101 141 1C1 SUBT 0A1 0 21 061 0E 1 1A 1 1 21 161 1 E1 Mnemonic /SU /SUC /SUM /SUD /SUI /SUIC /SUIM /SUID ADDS 580 500 540 5C0 780 70 0 7[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Alpha Instru ction Set A–1 1 VAX Floating-Point Instructions Programming Note: In order to use CMPTxx with sof tware completion t rap handling, i t is necessary to specif y the /SU I EEE trap mode, even though an unde rflow trap is not possi ble. In order to use CVTQS or CVTQT with software co m pleti[...]

A–12 Alpha Ins tructi on Set Alpha 212 64/EV 67 Hardwar e Referenc e Manual Opcode Summary Table A–7 Independent Floating-Point Instruction Function Codes A.6 Opcode Summary T able A–8 li sts all Alpha op codes from 00 (CALL_P AL) through 3F (BG T). In the table, t he column headi ngs that appear over the inst ructions ha ve a granularit y of[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Alpha Instru ction Set A–13 Required PALcode Function Codes T able A–9 expl ains the symbo ls used in T able A–8. A.7 Requir ed P A Lcode Functio n Codes T able A–1 0 lists opcod es required for all Alpha impl ementations. The notation u sed is oo.ffff , where oo i s the hexadecimal 6- bit opcod[...]

A–14 Alpha Ins tructi on Set Alpha 212 64/EV 67 Hardwar e Referenc e Manual IEEE Floating-Point Conformance A.8 IEEE Floating-Point Confo rmance The 21264/ EV67 supports th e IEEE floati ng-point operat ions defined in the Alp ha Sys- tem Refer ence Manual , Re visi on 7 and therefo re also from th e Alpha Ar chitectur e Handbook, V ersion 4 . Su[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Alpha Instru ction Set A–15 IEEE Floating-Point Conformance The 21264/ EV67 does not prod uce a denormal r esult for t he underflo w exception. Instea d, a true zero (+0) is writt en to the dest ination reg ister . In the 21264/EV67, the FPCR underflow to zero (UNDZ) bit must be set i f the underflow [...]

A–16 Alpha Ins tructi on Set Alpha 212 64/EV 67 Hardwar e Referenc e Manual IEEE Floating-Point Conformance MULx INPUT Inf operand ± Inf (none) QNaN operand QNaN (none) SNaN operand QNaN In valid Op 0 * Inf CQNaN Invali d Op MULx OUTPUT (same as ADDx) DIVx INPUT QNaN operand QNaN (none) SNaN operand QNaN In valid Op 0/0 o r I nf/ Inf CQNa N Inva[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Alpha Instru ction Set A–17 IEEE Floating-Point Conformance See Secti on 2.14 for in formation abou t the float ing-point co ntrol registe r (FPCR). SNaN operand 0 In valid Op CVTfi OUTPUT Inexact result Result Inexact Integer overf low Tru ncated result In valid Op CVT if OUTP UT Inexact result Resul[...]

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Alpha 21264/E V67 Hard ware Ref erence Manual 21264/EV 67 Bo unda ry -Sc an Register B–1 B 21264/EV67 Boundary-Scan Register This appe ndix contains the BSDL descri ption of the 21264 /EV67 boundary-s can regis- ter . B.1 Bound ary-Scan Register The Boundar y - Scan Reg ister (BSR) on the 21264/EV67 is 367 bits l ong. It is ac ces sed by the t hr[...]

B–2 21264/E V67 Bou ndary- Scan Regi ster Alpha 212 64/EV 67 Hardwar e Referenc e Manual Boundary-Scan Register SysDataInClk_H :in bit_vector (0 to 7) ; BcDataOutClk_L :out bit_vector (0 to 3) ; -- JWB corrected BcDataOutClk_H :out bit_vector (0 to 3) ; -- JWB corrected ClkIn_H :linkage bit ; -- Oscillator ClkIn_L :linkage bit ; -- Oscillator PLL[...]

Alpha 21264/E V67 Hard ware Ref erence Manual 21264/EV 67 Bo unda ry -Sc an Register B–3 Boundary-Scan Register " AB38, AC39, AD38, AF40, AH38, AJ39, AL41, AK38, "& " AN39, AP38, AR39, AT38, AY38, AV36, AW35, AV34),"& "SysCheck_L : (L7 , AA5 , AK8 , BA13, L39 , AA41, AM40, AY34),"& "SysDataInClk_H : [...]

B–4 21264/E V67 Bou ndary- Scan Regi ster Alpha 212 64/EV 67 Hardwar e Referenc e Manual Boundary-Scan Register "NoConnect_0 : BB14, "& "NoConnect_1 : BD2 , "& "ClkFwdRst_H : BE11, "& "EV6Clk_H : AM6 , "& "EV6Clk_L : AL7 , "& "Spare_4 : AT4 , "& "Spare_5 : AR[...]

Alpha 21264/E V67 Hard ware Ref erence Manual 21264/EV 67 Bo unda ry -Sc an Register B–5 Boundary-Scan Register "BcLoad_L : 124 , "& "BcDataWr_L : 79 , "& "BcData_H : (26 , 71 , 2 , 46 , 45 , 90 , 159 , 89 , "& " 179 , 186 , 195 , 202 , 234 , 242 , 250 , 267 , "& " 290 , 298 , 307 , 322[...]

B–6 21264/E V67 Bou ndary- Scan Regi ster Alpha 212 64/EV 67 Hardwar e Referenc e Manual Boundary-Scan Register "VSS : (44 , 259 , 388 , 138 , 97 , 146 , 60 , 278 , "& " 497 , 233 , 178 , 323 , 479 , 436 , 485 , 444 , "& " 538 , 310 , 21 , 281 , 226 , 371 , 47 , 53 , "& " 578 , 106 , 358 , 155 , 313 [...]

Alpha 21264/E V67 Hard ware Ref erence Manual 21264/EV 67 Bo unda ry -Sc an Register B–7 Boundary-Scan Register " 364 ( BC_2, SromClk_H, OUTPUT2, x ), "& -- " 363 ( BC_2, SromData_H, INPUT, x ), "& -- " 362 ( BC_3, reset_L, INPUT, x ), "& -- " 361 ( BC_3, IRQ_H(5), INPUT, x ), "& -- " 3[...]

B–8 21264/E V67 Bou ndary- Scan Regi ster Alpha 212 64/EV 67 Hardwar e Referenc e Manual Boundary-Scan Register " 299 ( BC_2, BcData_H(83), BIDIR, x, 305, 0, Z ), "& -- " 298 ( BC_2, SysData_L(19), BIDIR, x, 302, 0, WEAK1 ), "& -- " 297 ( BC_2, BcData_H(18), BIDIR, x, 305, 0, Z ), "& -- " 296 ( BC_2,[...]

Alpha 21264/E V67 Hard ware Ref erence Manual 21264/EV 67 Bo unda ry -Sc an Register B–9 Boundary-Scan Register " 234 ( BC_2, BcData_H(3) , BIDIR, x, 239, 0, Z ), "& -- " 233 ( BC_2, BcData_H(67), BIDIR, x, 239, 0, Z ), "& -- " 232 ( BC_2, SysData_L(3), BIDIR, x, 236, 0, WEAK1 ), "& -- " 231 ( BC_2, [...]

B–10 21264/EV 67 Bou ndary-Sc an Regist er Alpha 212 64/EV 67 Hardwar e Referenc e Manual Boundary-Scan Register " 169 ( BC_2, BcAdd_H(21), OUTPUT2, x ), "& -- " 168 ( BC_2, BcAdd_H(22), OUTPUT2, x ), "& -- " 167 ( BC_2, BcAdd_H(23), OUTPUT2, x ), "& -- " 166 ( BC_2, SysData_L(32), BIDIR, x, 150, 0, [...]

Alpha 21264/E V67 Hard ware Ref erence Manual 21264/EV 67 Bo unda ry -Sc an Register B–1 1 Boundary-Scan Register " 104 ( BC_2, BcData_H(47), BIDIR, x, 116, 0, Z ), "& -- " 103 ( BC_2, SysCheck_L(5), BIDIR, x, 119, 0, WEAK1 ), "& -- " 102 ( BC_2, BcCheck_H(13), BIDIR, x, 116, 0, Z ), "& -- " 101 ( BC[...]

B–12 21264/EV 67 Bou ndary-Sc an Regist er Alpha 212 64/EV 67 Hardwar e Referenc e Manual Boundary-Scan Register " 39 ( BC_2, BcData_H(127), BIDIR, x, 50, 0, Z ), "& -- " 38 ( BC_2, BcData_H(63), BIDIR, x, 50, 0, Z ), "& -- " 37 ( BC_2, SysCheck_L(7), BIDIR, x, 53, 0, WEAK1 ), "& -- " 36 ( BC_2, BcCh[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Serial I cache Lo ad Prede code V alues C–1 C Serial Icache Load Predecode V alues See th e Alp ha M oth erb oa rds Softw ar e Dev elo pe r ’ s Kit (S DK) for inform at ion.[...]

[...]

Alpha 21264/E V67 Hard ware Ref erence Manual PALcod e Restri ctions a nd Guide lines D–1 D P ALcode Restrictions and Guidelines D.1 Restr iction 1 : Reset Seq uence Required by Retire Lo gic and Mapper For conve nience of imple mentation, the Ibox retire logic done s tatus bits are not initial- ized dur ing reset. I nstead, as sho wn in the exam[...]

D–2 PALcode Restric tions an d Guidel ines Alpha 212 64/EV 67 Hardwar e Referenc e Manual Restriction 1 : Reset Sequence Required by Retire Log ic and Mapper addt f 31,f31,f2 /* initi alize F.P. Re g. 2*/ mult f 31,f31,f3 /* initi alize F.P. Re g. 3*/ addq r 31,r31,r4 /* initi alize Int. Re g. 4*/ addq r 31,r31,r5 /* initi alize Int. Re g. 5*/ ad[...]

Alpha 21264/E V67 Hard ware Ref erence Manual PALcod e Restri ctions a nd Guide lines D–3 Restriction 1 : Reset Sequence Required by Retire Logic and Mapper addq r 31,r31,r27 /* initiali ze Int. Reg. 27*/ addt f 31,f31,f26 /* initiali ze F.P. Reg. 26*/ mult f 31,f31,f27 /* initiali ze F.P. Reg. 27*/ addq r 31,r31,r28 /* initiali ze Int. Reg. 28*/[...]

D–4 PALcode Restric tions an d Guidel ines Alpha 212 64/EV 67 Hardwar e Referenc e Manual Restriction 1 : Reset Sequence Required by Retire Log ic and Mapper ** or th e PALcode, bu t it must be don e in the mann er and order below. ** ** It as sumes that th e retirator has been initiali zed, that the ** non-s hadow registe rs are mapped, a nd tha[...]

Alpha 21264/E V67 Hard ware Ref erence Manual PALcod e Restri ctions a nd Guide lines D–5 Restriction 1 : Reset Sequence Required by Retire Logic and Mapper addq r 31,r31,r21 /* initiali ze Shadow Reg . 5*/ br r 31, nxt8 /* conti nue executing in next bloc k*/ tch7: br r31, tch8 /* fetch in next bloc k*/ nxt8: addq r31,r31,r22 /* initiali ze Shad[...]

D–6 PALcode Restric tions an d Guidel ines Alpha 212 64/EV 67 Hardwar e Referenc e Manual Restriction 1 : Reset Sequence Required by Retire Log ic and Mapper br r 31,bccshf /* conti nue shifting* / bccend: mtp r r31,EV6__ EXC_ADDR + 16 /* dummy IPR write - s ets SCBD bit 4 */ addq r 31,r31,r0 /* nop*/ addq r 31,r31,r1 /* nop*/ mtpr r 31,EV6__EXC_[...]

Alpha 21264/E V67 Hard ware Ref erence Manual PALcod e Restri ctions a nd Guide lines D–7 Restriction 1 : Reset Sequence Required by Retire Logic and Mapper mtpr r 31,EV6__PCTR_ CTL /* 2nd buffer fetch block f or above map- stall /* an d 2nd clear P CTR_CTL (SCRB RD=4)*/ bis r 31,1,r0 /* set up valu e for demon w rite*/ bis r 31,1,r0 /* set up va[...]

D–8 PALcode Restric tions an d Guidel ines Alpha 212 64/EV 67 Hardwar e Referenc e Manual Restriction 2 : No Multiple Writers to IPRs in Sam e Scoreboard Group br r 31,palbase_in it palbase_ init: br r 0, br60 /* r0 <- curre nt location */ br60: lda r1, (EntryP oint-br60)(r 0) /* r1 <- l ocation of co debase */ mtpr r 1, EV6__PAL_B ASE /* s[...]

Alpha 21264/E V67 Hard ware Ref erence Manual PALcod e Restri ctions a nd Guide lines D–9 Guideline 6 : Avoid Consecutive Read-Modify-Write-Read-Modify-Write D.4 Guideline 6 : A void Consecutive Read-Modify-Write-Read- Modify-W rite A void consecutive read- modify-wr ite-re ad-modify- write sequences t o IPRs in t he same scoreboa rd group. The l[...]

D–10 PALcode Restricti ons and G uidelin es Alpha 212 64/EV 67 Hardwar e Referenc e Manual Restriction 9 : PALmode Istream Address Ranges Bad_inte rrupt_flow_en try: ADDQ R31,R3 1,R0 STF Fa,( Rb) ; This S TF might not undergo a dirty source regist er ; check and might gi ve wrong results ADDQ R31,R3 1,R0 ADDQ R31,R3 1,R0 ........ ............. ..[...]

Alpha 21264/E V67 Hard ware Ref erence Manual PALcod e Restri ctions a nd Guide lines D–1 1 Restriction 11: Ibox IPR Update Synchronization D.8 Restr iction 1 1 : Ibox IPR Up date Synchronization When updatin g any Ibox IPR, a retur n to native (vi rtual) mode should us e the HW_RET instru ction with th e associate d ST ALL bit set t o ensure tha[...]

D–12 PALcode Restricti ons and G uidelin es Alpha 212 64/EV 67 Hardwar e Referenc e Manual Guideline 16 : JSR-BAD VA D.12 Guideline 16 : JSR-BAD V A A JSR memory for mat instructi on that generate s a bad V A (IACV) trap r equires P AL- code ass istance to d etermine the correct excepti on address. I f the EXC_SUM[BAD_IV A] is set, bits [ 63,1] o[...]

Alpha 21264/E V67 Hard ware Ref erence Manual PALcod e Restri ctions a nd Guide lines D–13 Restriction 22: HW_RET/STALL After HW _MTPR IS0/IS1 BIS R31, R31, R31 HW_MTPR R9, ASN0, SCBD<4> HW_MTPR R9, ASN1, SCBD<7> This sequ ence guarante es, through t he register dep endency on R0, tha t neither HW_MTPR ar e issued befo re scoreboar d [...]

D–14 PALcode Restricti ons and G uidelin es Alpha 212 64/EV 67 Hardwar e Referenc e Manual Restriction 24: HW_RET/STALL After HW_MTPR IC_FLUSH, IC_FLUSH_ASM, xxx HW_ST/C -> R0 Bxx R0, try_again STQ ; Force next ST/C to fail if no pre ceding LDxL HW_RET D.20 Restriction 24: HW_RET/ ST ALL After HW_MTPR IC_FLUSH, IC_FLUSH_ASM, CLEAR_MAP There mu[...]

Alpha 21264/E V67 Hard ware Ref erence Manual PALcod e Restri ctions a nd Guide lines D–15 Restriction 27: Reset of ‘Force-Fail Lock Flag’ State in PA Lcode D.23 Restriction 27: Reset o f ‘Force-Fail Lock Flag’ St ate in P ALcode A virtua l mode load or s tore is requir ed in P ALcode befor e the execution of any load - locked or store-co[...]

D–16 PALcode Restricti ons and G uidelin es Alpha 212 64/EV 67 Hardwar e Referenc e Manual Restriction 30 : HW_ MTPR and HW_MFPR to the Cbox CSR ALIGN_FE TCH_BLOCK sys__cbo x: mb ; quiet the dstream hw_mfpr p6, EV6_ _I_CTL ; (4,0L) ge t i_ctl lda p4, ^xFCFF(r31 ) ; mask for cleari ng SBE bits and p6, p4, p4 ; clear SBE bits sbe_off_ offset = <[...]

Alpha 21264/E V67 Hard ware Ref erence Manual PALcod e Restri ctions a nd Guide lines D–17 Restriction 31 : I_CTL[VA_48] Update sys__cbo x_over6: ; block 6 beq p6, sys__cb ox_over8 ; branch if done bis r31, r31, r 31 ; nop br r31, sys__cbox _over7 ; go to blo ck 7 sys__cbo x_touch6: ; br r31, sys__cbox _touch7 ; touch block 7 sys__cbo x_over7: ; [...]

D–18 PALcode Restricti ons and G uidelin es Alpha 212 64/EV 67 Hardwar e Referenc e Manual Restriction 3 3 : HW_LD Physi cal/Lock Use D.29 Restriction 33 : HW_LD Physical/Lock Use The HW_LD phys ical/lock instruction must be one of the first thr ee instruction s in a quad-ins truction a ligned fetch bl ock. A pipeline error can oc cur if the HW_L[...]

Alpha 21264/E V67 Hard ware Ref erence Manual PALcod e Restri ctions a nd Guide lines D–19 Guideline 39 : Writing Multiple DTB Entries in the Same PAL Flow D.35 Guideline 39: W riting Multi ple DTB Entries i n the Same P AL Flow If a P ALcode flow intends t o write multipl e DTB entries ( as would occur i n a double miss), i t must take care to k[...]

D–20 PALcode Restricti ons and G uidelin es Alpha 212 64/EV 67 Hardwar e Referenc e Manual Restriction 40: Scrubbing a Single-Bit Error hw_mtpr r31 , EV6__DTB_IA ; (7,1L) flush dtb lda r20, ^x3301(r 31) ; set WE , RE bis r31, r31, r31 bis r31, r31, r31 hw_mtpr r31 , <EV6__MM_STAT ! ^x80> ; wait for retire srl r4, #13, r6 ; shift byt e offse[...]

Alpha 21264/E V67 Hard ware Ref erence Manual PALcod e Restri ctions a nd Guide lines D–21 Restriction 41: MTPR ITB_TAG, MTPR ITB_PTE Must Be in the Same Fetch Block D.37 Restriction 41: MTPR ITB_T AG , MT PR ITB_PTE Must Be in the Same Fe tch Bl oc k W rite the ITB_T AG and ITB_P TE regist ers in the same f etch block. This avoi ds a mispre dict[...]

D–22 PALcode Restricti ons and G uidelin es Alpha 212 64/EV 67 Hardwar e Referenc e Manual Restriction 46: Av oiding Live locks in Speculative Load CRD Ha ndlers D.42 Restriction 46: A voiding Live locks in Speculative Load CRD Handlers Speculat ive load CRD handl ers that rel ease from the i nterrupt witho ut scrubbing a cache bl ock could suf f[...]

Alpha 21264/E V67 Hard ware Ref erence Manual PALcod e Restri ctions a nd Guide lines D–23 Restric tion 47: Cache Evi ction for Singl e-Bit Cache Erro rs If "CBOX_ERR[C_ADDR]" has not c hanged when the CRD_HANDLER is re- entere d, or "CBOX_ERR[C_ST A T] == 0x0", all cache locatio ns should be evi cted to avoid th e live lock d[...]

D–24 PALcode Restricti ons and G uidelin es Alpha 212 64/EV 67 Hardwar e Referenc e Manual Restriction 48: MB Bracketing of Dcache Writes t o Force Bad Data ECC and Force D.44 Restriction 48: MB Bracketi ng of Dcache Wr ites to Force Bad Dat a ECC and Force Ba d T ag Par ity W rites to DC_CTL[F_BAD_DECC] and DC_CTL[DCDA T_ERR_EN] must be br ack- [...]

Alpha 21264/E V67 Hard ware Ref erence Manual 21264/EV 67-to-B cache P in Intercon necti ons E–1 E 21264/EV67-to-Bcache Pin Interconnections This appe ndix provides the pin interf ace between t he 21264/EV67 and Bc ache SSRAMs. E.1 Forwarding C lock Pin Groupings T able E– 1 lists the cor respondance be tween the clo ck signals for t he 21264/E[...]

E–2 21264/EV67- to-Bca che P in Intercon nectio ns Alpha 212 64/EV 67 Hardwar e Referenc e Manual Late-Write Non-Burst ing SSRAMs E.2 Late-W rite Non-Bursting SSRAMs T able E–2 pr ovi des t he dat a pi n conne ct ion s between late-wr it e non -bur st in g SSRAMs and the 2126 4/EV67 or the s yst em boa rd. T able E–3 provide s the same inform[...]

Alpha 21264/E V67 Hard ware Ref erence Manual 21264/EV 67-to-B cache P in Intercon necti ons E–3 Dual-Dat a Rate SSRAMs E.3 Dual-Dat a Rate SSRAMs T able E– 4 provides the dat a pin connect ions between d ual-data rate SSRAMs and the 21264/EV67 o r the system bo ard. T able E–5 pro vides the same information f or the tag pins. Data and Tag Pi[...]

E–4 21264/EV67- to-Bca che P in Intercon nectio ns Alpha 212 64/EV 67 Hardwar e Referenc e Manual Dual-Dat a Rate SSRAMs From board, pulled up to VDD TMS_H From board, pulled up to VDD TDI_H Unconnected or pulled down to VSS TRST_L BcData OE_L OE_L (G_L) From bo ard, pulled down to VSS SD/DD_L (B3) Table E–5 Dua l-Data Rate SSRAM Tag Pin Usa ge[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Gl o s s a r y –1 Glossary This glo ssary provide s definitions for specifi c terms and ac ronyms associa ted with the Alpha 21264 /EV67 microproce ssor and chip s in general . abort The unit stops the operat ion it is perfor m ing, without savin g status, to p erform some other op eration. address sp[...]

Glossary –2 Alpha 212 64/EV 67 Hardwar e Referenc e Manual asynchronous system trap (AST) A software -simulat ed i n te rr upt to a user - def ine d routine . AS T s enable a use r pr oce ss to be notifi ed asyn chronously , with respe ct to that pr oces s, of the occurrence of a specif ic event. If a user proc ess has defined an AST routine f or[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Glossar y –3 boot Short fo r bootstrap. Loading an oper ating syste m into memory is ca lled bootin g. BSR Boundary- scan regist er . buffer An inter nal memory area u sed for temporar y storage of d ata records dur ing input or output o perations. bugcheck A software condit io n, usual ly the resp on[...]

Glossary –4 Alpha 212 64/EV 67 Hardwar e Referenc e Manual cach e hit The stat us returned w hen a logic uni t probes a ca che memory and fi nds a valid ca che entry a t the probed a ddress. cach e inte rfere nce The resul t of an o peration that adve rsely af fec ts the mech anisms and p rocedures used to keep fre quently used items in a cac he.[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Glossar y –5 clock of fset (or cl koffset) The delay intentiona lly added to t he forwarded c lock to meet the s etup and hold requ iremen ts at th e Rec eiv e F lop. CMOS Complementar y metal-oxide se miconductor . A silic on device for med by a process that combines PMOS a nd NMO S semiconductor m a[...]

Glossary –6 Alpha 212 64/EV 67 Hardwar e Referenc e Manual direct-mapping cache A cache or ganizat ion in which on ly one address co mparison is needed to loc ate any data in the cache, bec ause any block of ma in memory data can be placed in only on e possibl e position i n the cache. direct me mory access (DM A) Access t o memory by an I/O de v[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Glossar y –7 exter nal ca c he See seco nd-level cac he. FEPROM Flash-e rasable programmab le read-only memor y . FEPROMs can be bank- or bulk- erased. Cont rast with EEPROM. FET Field-e ffect transistor . FEU The unit within the 212 64/EV67 microproc essor that performs floati ng-point calcul a- tion[...]

Glossary –8 Alpha 212 64/EV 67 Hardwar e Referenc e Manual of the c lock forward logic. Additionally , the framing clock c an have a period t hat is less t han, equal to, o r greater th an the time it t akes to send a full four cy cle command/ addr ess. GCLK Global cl ock within the 21 264/EV67. granularity A charact eri st i c of storage sys te [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Glossar y –9 interf ace r ese t A synchron ously receiv ed reset sig nal that is used to preset a nd start the clock forwar d- ing cir cuitry . During t his reset, all forwarded cl ocks are sto pped and the prese ttable count val ues are appl ied to the co unters; then, so me number of c ycles later ,[...]

Glossary –10 Alpha 212 64/EV 67 Hardwar e Referenc e Manual machine che ck An operat ing system act ion trigger ed by certain sy stem hardware- detected er rors that can be fa tal to syst em operation. On ce triggered, mach ine check hand ler software ana- lyze s the error . MAF Miss addr ess file. main memory The lar ge mem ory , ext ernal to th[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Glossary –1 1 MSI Medium-s ca le int egr at ion. multiprocessing A process ing method that replicate s the sequentia l computer and i nterconnects t he col- lecti on so that eac h processor c an execute th e same or a dif ferent pr ogram at the sa me time. must be one (MBO) A field tha t must be suppl[...]

Glossary –12 Alpha 212 64/EV 67 Hardwar e Referenc e Manual output mux count er Counter u sed to select the output mux that drives address and d ata. It is rese t with the Interf ace Reset and incremented by a copy of the l ocally generat ed forwarded c lock. PAL Privil eged archite cture librar y . See also PA L c o d e . See also Pro grammable [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Glossary –13 PQFP Plasti c quad flat p ack. primary ca che The cache that is th e fastest a nd closest to the processor . The first- level caches, l ocated on the CPU ch ip, composed o f the Dcache and I cache. program counter That port ion of the CPU t hat contains th e virtual a ddress of the next i[...]

Glossary –14 Alpha 212 64/EV 67 Hardwar e Referenc e Manual read str eam buffers Arrangemen t whereby each memory module in dependently pr efetches DRAM dat a prior t o an actual r ead request for that data. Re duces average memory late ncy while improving total memory ba ndwidth. receive counter Coun ter used to ena ble the receiv e fl ops . It [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Glossary –15 SDRAM Synchronou s dynamic random-acc ess memory . second-leve l cache A cache memor y provided outsid e of the micropro cessor chip, u sually located on t he same module. Also called b oard-level, external, or module-level cac he. set-ass ociative A form of c ache organi zation in which [...]

Glossary –16 Alpha 212 64/EV 67 Hardwar e Referenc e Manual STRAM Self-t imed random-acc ess memory . superpipelined Describes a pipelined machin e that has a lar ger number of pipe stages and more com- plex sch eduling and co ntrol. See also pipeline. superscalar Describe s a machine ar chitecture tha t allows multipl e independent instructions [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Glossary –17 UNPREDICTABLE Results or occurrenc es that do not disrupt the bas ic operation of the process or; the pro- cessor continues to execute inst ructions in it s normal manner . Privileged or u nprivi- leged so ftware can tr igger UNPREDICT ABLE results or o ccurrences. (This meaning only appl[...]

Glossary –18 Alpha 212 64/EV 67 Hardwar e Referenc e Manual WAR W rite- after -read. word T wo conti guous b yte s (16 bits) starti ng on an ar bitr ary byte boun dary . The bits are n um- bered fr om right to left, 0 through 15. write- back A cache mana gement techniq ue in which wri te operation dat a is written i nto cache but is not wr itten [...]

Alpha 21264/E V67 Hard ware Ref erence Manual Index–1 Index Numerics 21264/EV67 , features of , 1–3 32_BYTE_IO C box CSR defin ed , 5–34 A Abbreviations , xix binary mu ltiples , xix register access , xix AC characteristics , 9–6 Address conventions , xx Aggregate mode , 6–18 Aligne d convention , xx Alpha instructio n s ummary , A–1 AM[...]

Index–2 Alpha 212 64/EV 67 Hardwar e Referenc e Manual BC_SJ_BANK_ENABLE Cbox CSR defin ed , 5–34 BC_TAG_DDM_ F ALL_EN Cbox CSR , 4–47 defin ed , 5–35 BC_TAG_DDM_ RISE_EN Cbox CSR , 4–47 defin ed , 5–36 BC_WR_ RD_BUBBL ES Cbox CSR , 4–49 defin ed , 5–34 BC_WR _WR _BUBB LE Cb ox CSR , 4–54 defin ed , 5–34 BC_ WR T_S TS Cb ox CS R[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Index–3 Cbox data register C_DATA , 5–33 desc ribe d , 2–11 , 4–3 duplicate Dcache tag array , 2– 11 duplicate Dcache tag array with , 4–13 HW_MTP R and HW_MFP R to CSR , D– 15 I/O write buffer , 2– 11 internal processor registers , 5–3 probe queu e , 2–11 read register , 5 –41 shi[...]

Index–4 Alpha 212 64/EV 67 Hardwar e Referenc e Manual Dcache desc ribe d , 2–12 duplicate tag parity errors , 8–4 duplicate tags with , 4–13 error case summary for , 8–9 fill from Bcache error , 8–6 fill from memory errors , 8– 7 initialized by Bi ST , 7–12 pipeli ned , 2–16 single-bit correctable ECC err or , 8– 3 store second[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Index–5 ECC 64-bit data and check bit cod e , 8–2 Dcache data single-bi t correctable errors , 8–3 for system data b us , 8–2 memory/system port single-bit corr ectable errors , 8– 7 store instructions , 8– 4 ENABLE_EVICT Cb ox CSR , 4–23 , 5–3 9 ENABLE_PROBE_CHECK Cb ox CSR , 8–2 defi[...]

Index–6 Alpha 212 64/EV 67 Hardwar e Referenc e Manual I_CTL Ibo x control register , 5–15 after fault reset , 7–8 aft er wa rm res et , 7–11 at power-on reset state , 7–1 5 PALshado w registers , 6–11 throug h sleep mode , 7–10 VA_ 48 fie ld up date , D–17 I_DA pin ty pe , 3–3 , 9–2 val ues for , 9–3 I_DA_CLK pin type , 3–3[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Index–7 2–16 Integer execution unit. See Ebox Integer issue queue , 2–6 pipeli ned , 2–15 Internal process or registers , 5–1 accessing , 6–7 explicitly writt en , 6–8 implicitly wri tten , 6– 9 ordering access , 6–9 pair ed fe tch orde r , 6–9 scoreboard bits for , 6–8 INTERRUPT i[...]

Index–8 Alpha 212 64/EV 67 Hardwar e Referenc e Manual MB, 21264 /EV67 command , 4–13 , 4 –21 MB_C NT Cbox CSR, op era tio n , 2–32 MBDone, SysDc command , 4–13 Mbox Dcache control reg i ster DC_CTL , 5–30 Dcache status register D C_STAT , 5–31 desc ribe d , 2–12 Dstream translation bu ffer , 2–13 DTB address space number reg iste[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Index–9 PALcode conditional branches in , D–14 desc ribe d , 6–1 entries poin ts for , 6–12 exception ent ry poi nt s , 6–13 guidelines for , D–1 HW_LD instructio n , 6–3 HW_MFPR in st ruction , 6– 6 HW_MTPR instru ction , 6–6 HW_RET instruction , 6–5 HW_ST inst ruction , 6–4 requi[...]

Index–10 Alpha 212 64/EV 67 Hardwar e Referenc e Manual ReadBlk, 21 264/EV67 comman d , 4–21 system prob e s, with , 4–41 ReadBlkI, 2 1264/EV67 command , 4 –22 ReadBlkMod, 21264/EV67 command , 4–2 2 system prob e s, with , 4–41 ReadBlkModS pec, 21264/E V67 command , 4–22 ReadBlkModVic , 21264/EV67 command , 4–22 ReadBlkSpec, 21 264/[...]

Alpha 21264/E V67 Hard ware Ref erence Manual Index–11 Store in stru ctions Dcache ECC errors with , 8–4 I/O address space , 2–29 I/O reference ord ering , 2–31 Mbox order traps , 2–31 memory address space , 2–29 memory refer ence ordering , 2–31 translation to ex ternal in terface , 4–5 Store queue , 2–1 3 Store-load order trap ,[...]

Index–12 Alpha 212 64/EV 67 Hardwar e Referenc e Manual Traps load-load order , 2–32 Mbox order , 2–31 replay , 2–31 store-load order , 2–3 2 Trst_L signal pin , 3–6 U UNALIGN fault , 6–13 Unaligned co nvention , xx V VA vi rt ual a d dres s re gis ter , 5–4 at power-on reset state , 7–1 5 VA_CTL virtual address control r egister [...]