Cypress CY7C601xx manual

CY7C601xx, CY7C602xx enCoRe™ II Low V olt age Microcontroller Cypress Semiconducto r Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document 38-16016 Rev . *E Revised December 0 8, 2008 1. Features ■ enCoRe ™ II Low V olt age (enCoRe II L V)—enhanced component reduction ❐ Internal crystalless osci llator [...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 2 of 68 3. Applications The CY7C601xx and CY7C602xx are targeted for the following applications: ■ PC wireless HID devices ❐ Mice (optomechanical, optical, trackball) ❐ Keyboards ❐ Presenter tools ■ Gaming ❐ Joysticks ❐ Gamepad ■ General purpose wireless application s ❐ Remote c[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 3 of 68 6. Pinout s Figure 6-1. Package Configu ration s 1 2 3 4 5 6 9 11 15 16 17 18 19 20 22 21 NC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 CLKINP0.0 P2.0 P1.5/SMOSI P1.3/SSEL P3.1 P3.0 V DD P1.2 P1.1 P1.0 14 P1.4/SCLK 10 P2.1 NC V SS 12 13 7 8 INT0/P0.2 CLKOUTP0.1 24 23 P1.7 P1.6/SMISO 2[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 4 of 68 6.1 Pin Assignment s T able 6-1. Pin Assignment s 48 SSOP 40 PDIP 28 SSOP 24 QSOP 24 SOIC 24 PDIP Name Description 7 3 P4.0 GPIO Port 4—configured as a grou p (n ibble) 62 P 4 . 1 42 38 P4.2 43 39 P4.3 34 30 19 18 1 P3.0 GPIO Port 3—config ured as a group (byte) 35 31 20 19 2 P3. 1 36[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 5 of 68 23 19 13 9 9 16 P0.0/CL KIN GPIO Po rt 0 bit 0—Configured individually On CY7C601xx, opti onal Clock In when external osci llator is disabled or external oscillator inp ut wh en external oscillator is enabled. On CY7C602xx, oscillator input when configured as Clock In. 22 18 12 8 8 15 P[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 6 of 68 7. Register Summary T able 7-1. enCoRe II L V Register Summary The XIO bit in the CPU Flags Register must be set to access the extended regi ster space for all registers above 0xFF . Addr Name 7 6 5 4 3 2 1 0 R/W Default 00 P0DA T A P0.7 P0.6/TIO1 P 0.5/TIO0 P0.4/INT2 P0.3/I NT1 P0.2/INT0[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 7 of 68 Note In the R/W column: b = Both Re ad and Write r = Read O nly w = Write Only c = Read or Clear d = Calibra tion V alue. Must not cha nge during norma l use 34 IOSCTR foff set[2:0] Gain[4:0] bbbbbbbb 000ddddd 35 XOSCTR Reserved XOSC XGM [2 :0] Reserved Mode ---bbb-b 000ddddd 36 LPOSCTR 3[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 8 of 68 8. CPU Architecture This family of microcontrollers is based on a high performan ce, 8-bit, Harvard architec ture microprocessor . Fi ve registers control the primary operation of the CPU core. These registers are affected by various instructions, but are not directly acce ssible through [...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 9 of 68 9.1.1 Accum ulator Regist er 9.1.2 Index Register 9.1.3 S tack Pointer Register 9.1.4 CPU Program Counter High Register 9.1.5 CPU Program Counter Low Register T able 9-2. CPU Accumulator Register (C PU_A) Bit # 76543210 Field CPU Accumulator [7:0] Read/Write –––––––– Defau[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 10 of 68 9.2 Addressi ng Modes 9.2.1 Source Immediate The result of an instruction using this addressing mode is placed in the A register , the F register , the SP register , or the X register , which is specified as part of the instruction opcode. Ope rand 1 is an immediate value that serves as [...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 1 1 of 68 9.2.5 Destination Indexed The result of an instruction using this addressing mode is placed within either th e RAM memory space or the register space. Operand 1 is adde d to the X register forming the a ddress that poi nts t o th e l oca tio n of th e re sult. The source for the instruc[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 12 of 68 9.2.9 Source Indirect Post Increment The result of an instruction using this addressing mode is placed in the Accumulator. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the s ource of the instruction. The indi[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 13 of 68 13 7 2 SUB A, [X+expr] C, Z 40 4 1 NOP 6D 4 1 RRC A C, Z 14 7 2 SUB [expr], A C, Z 41 9 3 AND reg[expr], expr Z 6E 7 2 RRC [expr] C, Z 15 8 2 SUB [X+expr], A C, Z 42 10 3 AND reg[X+expr], expr Z 6F 8 2 RRC [X+expr] C, Z 16 9 3 SUB [expr], expr C, Z 43 9 3 OR reg[expr], expr Z 70 4 2 AND [...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 14 of 68 1 1. Memory Organization 1 1.1 Flash Progra m Memory Organization Figure 1 1-1. Program Memo ry Space with Interrupt V ector T able after reset Address 16-bit PC 0x0000 Program execution begins here after a reset 0x0004 POR/L VD 0x0008 INT0 0x000C SPI Transm itter Empty 0x0010 SPI Receiv[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 15 of 68 1 1.2 Dat a Memory Organization The CY7C601xx and CY7C602xx microcon tro llers provid e up to 256 bytes of data RAM Figure 1 1-2 . Data Memory Organization 1 1.3 Flas h This section describes the Flash blo ck of enCoRe II L V . Much of the visible Flash functionality , including programm[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 16 of 68 T wo important variables used for all functions are KEY1 and KEY2. These variables help discrimi nate between valid and inadvertent SSCs. KEY1 always ha s a value of 3Ah, while KEY2 has the same value as the stack pointer when the SRO M function begins execution. This is the St ack Point[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 17 of 68 1 1.5.3 WriteBlock Function The Wr iteBlock func tion is used to stor e data in Flash. Dat a is moved 64 bytes at a time from SRAM to F lash using this functio n. The WriteBlock function first checks the protection bits and deter- mines if the desired BLOCKID is writable. If write protec[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 18 of 68 1 1.5.6 EraseAll Function The EraseAll function performs a series of steps that destroy the user data in the Flash macros and resets the protection block in each Flash macro to all zeros (the unprotected state). The EraseAll function does not affect the three hidden blocks a bove the pro[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 19 of 68 1 1.6 SROM T able Read Description The Silicon IDs for enCoRe II L V devices are stored in SROM tables in the part, as shown in Figure 1 1-3. on page 20 The Silicon ID can be read out from the part using SROM T able reads. This is demo nstrated in the foll owing pseudo code. As mentioned[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 20 of 68 Figure 1 1-3. SROM T abl e 1 1.6.1 Checksum F unct i on The Checksum function calculates a 16-bit checksum over a user specifiable number of blocks, within a single Flash macro (Bank) starting from block zero. The BLOCKID parameter i s used to p a ss in th e n umber of bloc ks to cal cul[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 21 of 68 12. Clocking The enCoRe II L V has two internal oscillators, the internal 24 MHz oscillator and the 32 kHz low power oscilla tor . The internal 24 MHz oscillator is designed such that it is trimmed to an output frequency of 24 MHz over temperature and voltage variation. The internal 24 M[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 22 of 68 When using the 32 kHz oscillator , the PITMRL/H is read un til two consecutive readings match before sending a nd receiving d ata. The following firmware example a ssumes the developer i s interested i n the lower byte of the PIT . Read_PIT_counter: mov A, reg[PITMRL] mov [57h], A mov A,[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 23 of 68 Figure 12-1. CPU Clock Block Diagram SCALE (divid e b y 2 n, n = 0- 5,7) MUX CLK_EXT CLK_ 24MH z CPUCLK SEL CLK_C PU Doubl er CLK_HS LP OS C 32-KHz CLK_32KHz XTAL OSC 1-24MHz CY7C601xx onl y MUX Crys ta l O s cilla to r Dis ab le d XOSC SEL EN CLK_EXT EFTB P0. 0 CLKIN P0. 1 CLKOUT CY7C 6[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 24 of 68 Read/Write – – R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit [7:6]: Reserved Bit 5: No Buzz During sleep (the Sleep bi t is set in the CPU_SCR Register— T able 13-1 ), the L VD and POR dete ction circuit is turne d on periodi cally to detect any POR and L VD events on the V C[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 25 of 68 12.2.2 Interval Timer Clock (ITMRCLK) The Interval T i mer Clock (ITMRCLK) is sourced from the external crystal oscillator , the internal 24 MHz oscillator , the internal 32 kHz low power oscillator , or the T imer Capture clock. A program- mable prescal er of 1, 2, 3, or 4 then divi des[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 26 of 68 Figure 12-2. Programmable Interv al Timer Block Dia gra m 12.2.3 T imer Capt ure Clock (TCAPCL K) The T i mer Capture clock (TCAPCLK) is sourced from the external cryst al oscillator , the internal 24 MHz oscillator or the intern al 32 kHz low power oscillator . A programmable prescaler [...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 27 of 68 T able 12-5. Ti mer Clock Config uration (TMRCLKCR) [0x31] [R/W] Bit # 76543210 Field TCAPCLK Divide r TCAPCLK Select ITMRCLK Divider ITMRCLK Select Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 10001111 Bit [7:6]: TCAPCLK Divider [1:0] TCAPCLK Divider controls the TCAPCLK divisor .[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 28 of 68 12.2.4 I nternal Clock T rim 12.2.5 External Clock T rim T able 12-6. IOSC T rim (IOSCTR ) [0x34] [R /W] Bit # 76543210 Field fo ffset[2: 0] Gain[4:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 D D D D D The IOSC Calibrate Register is used to calibrate the internal oscillat[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 29 of 68 12.2.6 LPO SC T rim 12.3 CPU Clock During Sleep Mode When the CPU enters sleep mode the CPUCLK Select (Bit 0, T able 12-2 ) is forced to the internal os cilla tor , and the oscillator is stopped. When the CPU comes out of sleep mo de it runs on the internal oscilla tor . The internal osc[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 30 of 68 13. Reset The microcontroller su pports two types of resets: Power on Reset (POR) and W atch dog Reset (WDR). When reset is initi ated, all registers are restored to their default states and al l interrupts are disabled. The occurrence of a reset is recorded in the System S tatus and Con[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 31 of 68 13.1 Power On Reset POR occurs every time the powe r to the device is switched on. POR is released when the supply is typically 2.6V for the upward supply transition, with typicall y 50 mV of hyster esis during the power on transient. Bit 4 of the System St atus and Control Register (CPU[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 32 of 68 14.1 Sleep Sequence The SLEEP bit is an input into th e sleep logic circuit. This circuit is designed to seque nce the device into a nd out of the hardware sleep state. The hardware sequence to put th e device to sleep is shown i n Figure 1 4-1. and is defined as follows. 1. Firmware set[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 33 of 68 14.2 Wakeup Sequen ce When asleep, the onl y event that wakes the system up is an interrupt. The g lobal interrupt enable o f the CPU flag register need not be set. Any unmasked interrupt wakes the system up. It is optional for the CPU to actually take the interrupt after the wakeup sequ[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 34 of 68 15. Low V oltage Detect Control T able 15-1. Low V olt age Control Regis ter (L VDCR) [0x1E3 ] [R/W] Bit # 76543210 Field Reserved PORLEV[1:0] Reserved VM[2:0] Read/Write – – R/W R/W –R / W R/W R/W Default 0000 00 0 0 This register controls t he configuration of the Power on Rese t[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 35 of 68 15.1 POR Comp are St ate 15.2 ECO T rim Registe r T able 15-2. V olt age Monitor Comparators Register (VL TCMP) [0x1E4] [R] Bit # 76543210 Field Reserved L VD PPOR Read/Write –––– –– R R Default 0000 00 0 0 This read-only register allows reading the current state of the L VD [...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 36 of 68 16. General Purpose IO P ort s 16.1 Port Da ta Registers 16.1.1 P0 Data 16.1.2 P1 Data T able 16-1. P0 Data Register (P0DA T A)[0x00] [R/W] Bit # 76543210 Field P0.7 P0.6/TIO1 P0.5/TIO0 P0.4/INT2 P0.3/INT 1 P0.2/INT0 P0. 1/CLKOUT P0.0/ CLKIN Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Def[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 37 of 68 16.1.3 P2 Data 16.1.4 P3 Data 16.1.5 P4 Data 16.2 GPIO Port Configurat ion All GPIO configuration registers have common configuration controls. By default all GPIOs are confi gured as inputs. T o prevent the inputs from floating , pull up resistors are ena bled. Firmware configures each [...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 38 of 68 16.2.4 Hi gh Sink When set, the outp ut sinks up to 50 mA. When clear , the output sinks up to 8 mA. On the CY7C601xx, only the P3.7, P2.7, P0.1, and P0.0 have 50 mA sink drive capability . Other pins have 8 mA sink drive capability . On the CY7C602xx, only the P1.7–P1.3 have 50 mA sin[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 39 of 68 16.2.10 P0.1 /C LK OUT Configu r at ion 16.2.1 1 P0.2/INT0–P0.4/INT2 Configuration T able 16-7. P0.1/CLKOUT Configuration (P01CR) [0x06] R/W] Bit # 76543210 Field CLK Ou tput Int Enable Int Act Low TTL Thresh High Sink Open Drain Pull up Enable Output Enable Read/Write R/W R/W R/W R/W [...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 40 of 68 16.2.12 P0.5/TIO0–P0.6/T IO1 Config uration 16.2.13 P0.7 Configuratio n 16.2.14 P1.0 Configuratio n T able 16-9. P0.5/TIO 0–P0.6 /TIO1 Configur at ion (P05CR– P06CR) [0x0A–0x0B] [R/W] Bit # 76543210 Field TIO Out put Int Enable Int Act Low TTL Thresh Reserved Open Drain Pull up E[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 41 of 68 16.2.15 P1.1 Configuratio n 16.2.16 P1.2 Configuratio n 16.2.17 P1.3 Co nfiguration (SSEL) T able 16-12. P1.1 Configuration (P1 1CR) [0x0E] [R/W] Bit # 76543210 Field Reserved Int Enable Int Act Low Reser ved Open Dra in Reserved Output Enable Read/Write – R/W R/W – –R / W– R/W D[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 42 of 68 16.2.18 P1.4– P1.6 Configurat ion (SCLK, SMOSI, SMISO) 16.2.19 P1.7 Configuratio n 16.2.20 P2 Configuratio n T able 16-15. P1.4–P1.6 Configuration (P14CR–P16CR) [0x1 1–0x 13] [R/W] Bit # 76543210 Field S PI Use Int Enable Int Act Low Reserved High Sink Open Drain Pull Up Enable O[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 43 of 68 16.2.21 P3 Configuratio n 16.2.22 P4 Configuratio n T able 16-18. P3 Configuration (P3CR) [0x16] [R/W] Bit # 76543210 Field Reserved Int Enable Int Act Low TTL Thresh High Sink Open Drain Pull Up Enable Output Enable Read/Write –R / W R / W R / W R/W R/W R/W R/W Default 00000000 In CY7[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 44 of 68 17. Serial Periphe ral Interface (SPI) The SPI Master and Slave Interface core logic runs on the SPI clock domain. T he SPI cloc k is a divider off of the CPUCLK when i n Master Mode. SPI is a four pin serial interface compri sed of a clock, an enable, and two data pins. Figure 17-1. SPI[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 45 of 68 17.1 SPI Data Register When an interrupt occurs to indicate to firmware tha t a byte of receive data is availabl e or the transmitter hold ing register i s empty , firmware has seven SPI clocks to manage the buffers—to empty the receiver buffer or to refill the transmit holding registe[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 46 of 68 T able 17-3. SPI Mode Timing vs. LSB First, CPOL, and CPHA LSB First CPHA CPOL Diagram 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1 SCL K SSEL DA T A X X MSB Bit 2 Bi t 3 Bi t 4 Bi t 5 Bi t 6 Bi t 7 LSB SC L K SSEL X X DATA MSB Bi t 2 Bi t 3 Bi t 4 Bi t 5 Bi t 6 Bi t 7 LSB SC L K SSEL X X DAT[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 47 of 68 17.3 SPI Interface Pins The SPI interface uses the P1.3–P1.6 p ins. These pins ar e configured using the P1.3 and P1.4 –P1.6 configuration. 18. Timer Registers All timer func tions of the enCoRe II L V ar e provided by a single timer block. The time r block is a synchronous from the [...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 48 of 68 18.1.2 Time Capture enCoRe II L V has two 8-bit captures. Each capture has a separate register for rising and falling time. The two 8-bit captures c an be configured as a single 1 6-bit capture. When config ured in this way , the capture 1 registers hold the hig h order byte of the 16- b[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 49 of 68 T able 18-4. Captur e Interrupt Enable (TCAPINTE) [0x2B] [R/W] Bit # 76543210 Field Reserved Cap1 Fall Enable Cap1 Rise Enable Cap0 Fall Enable Cap0 Rise Enable Read/Write –––– R/W R/W R/W R/W Default 0000 00 0 0 Bit [7:4]: Reserved Bit 3: Cap1 Fall En able 0 = Disable the captur[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 50 of 68 ‘ 18.1.3 Programmable I nte rval Timer T able 18-8. Timer Capture 1 Falling (TCAP1F) [0x25 ] [R/W] Bit # 76543210 Field Capture 1 Fallin g [7:0] Read/Write RRRR RR R R Default 0000 00 0 0 Bit [7:0]: Capture 1 Falling [7:0] This register holds the va lue of the free running timer when t[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 51 of 68 T able 18-1 1. Programmable Interval Timer High (PITMRH) [0x27] [R] Bit # 76543210 Field Reserved Prog Interval T imer [1 1:8] Read/Write -- -- -- -- RR R R Default 0000 00 0 0 Bit [7:4]: Reserved Bit [3:0]: Prog Intern al Timer [1 1:8] This register holds the high order nibble of th e 1[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 52 of 68 Figure 18-3. Timer Functional Sequence Diagra m [+] Feedback [+] Feedback[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 53 of 68 Figure 18-4. 1 6-Bit Free Running Co unter Loading Timing Diagram Figure 18-5. Memory Mapped Registers Re ad and Write Timing Diagram clk_sy s writ e valid addr write data FRT reload ready Clk Tim er 12b Prog Tim er 12b reload interrupt Capture tim er clk 16b free running counter load 16[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 54 of 68 19. Interrupt Controller The interrupt controller and its associated registers allow the user ’s code to respond to an interrupt from almost every functional block in the enCoRe II L V devices. The reg isters associated with the interrupt controller are disabled either globally or indi[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 55 of 68 19.2 Interru pt Processi ng The sequence of events that occur during interrupt processing i s as follows: 1. An interrupt becomes active, either because : a. The interrupt condition occurs (for example, a timer expires). b. A previously posted interrupt is ena bled through an update of a[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 56 of 68 19.4.2 I nterrupt Mask Registers The Interrupt Mask Registers (INT_MSKx) enable th e individual interrupt sources’ ability to create pending interrupts. There are four Interrupt Mask Registers (INT _MSK0, INT_MSK1, INT_MSK2, and IN T_MSK3) which are referred to in general as INT_MSKx. [...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 57 of 68 T able 19-6. Interrupt Mask 2 (INT_MSK2) [0xDF] [R/W] Bit # 76543210 Field Reserved GPIO Port 4 Int Enable GPIO Port 3 Int Enable GPIO Port 2 Int Enable Reserved INT2 Int Enable 16-bit Counter Wrap In t Ena ble TCAP1 Int Enable Read/Write – R/W R/W R/W –R / W R/W R/W Default 0000 00 [...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 58 of 68 19.4.3 Interrupt V ector Clear Register T able 19-8. Interrupt Mask 0 (INT_MSK0) [0xE0] [R/W] Bit # 76543210 Field GP IO Port 1 Int Enable Sleep T imer Int Enable INT1 Int Enable GPIO Port 0 Int Enable SPI R eceive Int Enable SP I Transmit Int Enable INT0 Int Enable PO R/L VD Int Enable [...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 59 of 68 20. Absolute Maximum Ratings S torage T emperature ..................... ... ... ........ –40°C to +90°C Ambient T emperature with Power Applied ..... –0°C to +70°C Supply V oltage on V CC Relative to V SS ..........–0.5V to +7.0V DC Input V oltage .............. ..............[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 60 of 68 Figure 20-1. Clock Timing 20.2 AC Characteri stics Parameter Descript ion Conditions Min T ypical Max Unit Clock T ECLKDC External Clock Duty Cycle 45 55 % T ECLK2 External Clock Frequency 1 24 MHz F IMO Internal Main Oscillator Frequency With proper trim values loaded [5] 18.72 26.4 MHz[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 61 of 68 Figure 20-2. GPIO Timing Diagram Figure 20-3. SPI Master Timing, CPHA = 1 10% T R_GPIO T F_GPIO GP IO P in O u tp u t Volt age 90% MSB T MSU LSB T MHD T SCKH T MDO SS SCK (CPOL=0) SCK (CPOL=1) MOSI MISO (SS is under firmware control in SPI Master mode) T SCKL MSB LSB [+] Feedback [+] Fee[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 62 of 68 Figure 20-4. SPI Slave Timing, CPHA = 1 Figure 20-5. SPI Master Timing, CPHA = 0 MSB T SSU LSB T SHD T SCKH T SDO SS SCK (CPOL=0) SCK (CPOL=1) MOSI MISO T SCKL T SSS T SSH MSB LSB MSB T MSU LSB T MHD T SCKH T MDO1 SS SCK (CPOL=0) SCK (CPOL=1) MOSI MISO (SS is under firmware control in SP[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 63 of 68 Figure 20-6. SPI Slave Timing, CPHA = 0 1 MSB T SSU LSB T SHD T SCKH T SDO1 SS SCK (CPOL=0) SCK (CPOL=1) MOSI MISO T SCKL T SDO LSB MSB T SSS T SSH 21. Ordering Information Ordering Code FLASH Size RAM Size Package T ype CY7C60123-PVXC 8K 256 48-SSOP CY7C60123-PXC 8K 256 40-PDIP CY7C601 [...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 64 of 68 23. Package Diagrams Figure 23-1. 24-Pin (300-Mil) SOIC S13 Figure 23-2. 24-Pin (300-Mil) PDIP P13 PIN 1 ID SEA TING PLANE 0.597[15.163] 0.615[15.621] 1 12 13 24 * * * 0.291[7.391] 0.300[7.620] 0.394[10.007] 0.419[10.642] 0.050[1.270] TYP . 0.092[2.336] 0.105[2.667] 0.004[0.101] 0.0118[0[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 65 of 68 Figure 23-3. 24-Pin QSOP O241 Figure 23-4. 28-Pin (5.3 mm) Shrunk Small Outline Pack age O28 0.033 0.228 0.150 0.337 0.053 0.004 0.025 0.008 0.016 0.007 0° -8° REF. 0.344 0.157 0.244 BSC. 0.012 0.010 0.069 0.034 0.010 SEATING PLANE MAX. DIMENSIONS IN INCHES MIN. PIN 1 ID 1 12 24 13 0.0[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 66 of 68 Figure 23-5. 40-Pin (600-Mil) Molded DIP P17 Figure 23-6. 48-Pin Shrunk Small Outline Package O48 51-85019-*A 51-85061 -*C [+] Feedback [+] Feedback[...]

CY7C601xx, CY7C602xx Document 38-16016 Rev . *E Page 67 of 68 24. Document History Page Document Title: CY7C601x x, CY7C602xx enCoR e ™ II Low V olt age Microcontroller Document Number: 38-16016 Rev . ECN Orig . of Change Submission Date Description of Change ** 327 601 BON See ECN New data sheet *A 400134 BHA See ECN Updated Power consumptio n v[...]

Document 38-16016 Rev . *E Revised December 08, 20 08 Page 68 of 68 PSoC is a registere d trademark and enCo Re is a trademark of Cypre ss Semiconductor Corpo ration. All product and company name s me ntioned in this d ocument may b e the trademarks o f their respecti ve holders . CY7C601xx, CY7C602xx © Cypress Semicondu ctor Corpor ation, 2006-20[...]