Cypress CY7C68053 manual

MoBL-USB™ FX2LP18 USB Microcontroller CY7C68053 Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document # 001-06120 Rev *F Revised September 9th 2006 1.0 CY7C68053 Features • USB 2.0 – USB-IF High-S peed and Full-S peed Compliant (TID# 40000188 ) • Single-chip integrated USB 2.0 tr[...]

CY7C68053 Document # 001-06120 Rev *F Page 2 of 39 Cypress Semiconductor Corporation’s MoBL-USB  FX2LP18 (CY7C68053) is a low-voltage (1.8 volt) version of the EZ- USB ® FX2LP (CY7C68013A), which is a hi ghly integrated, low-power USB 2.0 microcontrolle r . By integrating the USB 2.0 transceiver , serial interface engine (SIE), enhanced 8051 [...]

CY7C68053 Document # 001-06120 Rev *F Page 3 of 39 3.3 I 2 C™ Bus FX2LP18 supports the I 2 C bus as a master only at 100-/400- KHz. SCL and SDA pins h ave open-drain outputs and hysteresis inputs. These si gnals must be pulled u p to either V CC or V CC_IO , even if no I 2 C device is connected.(Connecting to V CC_IO may be more convenient.) 3.4 [...]

CY7C68053 Document # 001-06120 Rev *F Page 4 of 39 pushes the program counter onto its stack then jumps to address 0x0043, where it expe cts to find a ‘jump’ instruction to the USB inter rupt service rout ine. The FX2LP18 jump i nstruction is encode d as shown in Ta b l e 3 - 2 . If Autovectoring is enabled (A V2EN = 1 in the INT SET -UP regist[...]

CY7C68053 Document # 001-06120 Rev *F Page 5 of 39 3.9 Rese t and W akeup The reset and wakeup pins are describe d in detail in this section. 3.9.1 Reset Pin The input pin, RESET#, resets the FX2LP18 when asserted. This pin has hysteresis and is active LOW . When a crystal is used with the CY7C68053, the reset pe riod must allow for the stabilizati[...]

CY7C68053 Document # 001-06120 Rev *F Page 6 of 39 3.10 Program/Dat a RAM This sectio n describes the FX2LP1 8 RAM. 3.10.1 Size The FX2LP18 has 16 kBytes of internal program/data RAM. No USB control re gisters appear in this space. Memory maps are shown in Figure 3-3 and Figure 3-4 . 3.10.2 Interna l Code M emory This mode implements the internal 1[...]

CY7C68053 Document # 001-06120 Rev *F Page 7 of 39 vertical columns of Figure 3-5 . When operating in fu ll-speed BULK mode only the first 64 bytes of e ach buffer are used. For example, in high-speed the maximum packet size is 512 bytes, but in full-speed it is 64 bytes. Even though a buffer is configured to be a 512 byte buffer , in full-speed on[...]

CY7C68053 Document # 001-06120 Rev *F Page 8 of 39 3.12.6 Defaul t High-Speed Alte rnate Settings 3.13 External FIFO In terface The architecture, control si gnals, and clock rates are presented in th is section. 3.13.1 Architecture The FX2LP18 slave FIFO architecture h as eight 512-byte blocks in the endpoint RAM th at directly serve as FIFO memori[...]

CY7C68053 Document # 001-06120 Rev *F Page 9 of 39 3.14.1 Three Control OUT Sign als The 56-pin package brings out three of these si gnals, CTL0–CTL2. The 8051 programs the GPIF unit to defi ne the CTL waveforms. C TLx waveform edges can be pro grammed to make transitions as fast as once per clock cycle (20.8 ns using a 48 MHz clock). 3.14.2 T wo[...]

CY7C68053 Document # 001-06120 Rev *F Page 10 of 39 3.18.2 I 2 C Interface Boot Load Access At power on reset the I 2 C interface boo t loader loads the VID/PID/DID and configuration bytes and up to 16 kBytes of program/data. The available RAM spaces are 16 kBytes from 0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF . Th e 8051 is reset. I 2 C i[...]

CY7C68053 Document # 001-06120 Rev *F Page 1 1 of 39 Figure 4-2. CY7C68053 56-pin VF BGA Pin Assignment - T op view 12345 678 A B C D E F G H 1A 2A 3A 4A 5A 6A 7A 8A 1B 2B 3B 4B 5B 6B 7B 8B 1C 2C 3C 4C 5C 6C 7C 8C 1D 2D 7D 8D 1E 2E 7E 8E 1F 2F 3F 4F 5F 6F 7F 8F 1G 2G 3G 4G 5G 6G 7G 8G 1H 2H 3H 4H 5H 6H 7H 8H [+] Feedback[...]

CY7C68053 Document # 001-06120 Rev *F Page 12 of 39 4.1 CY7C68053 Pin Description s Note 9. Unused inputs must not be left float ing. T ie either HIGH or LOW as appropriate. Output s should only be pulled up or down to ensure signals at power up and in standby . Note also that no pins should be driven while the devi ce is powered down T able 4-1. F[...]

CY7C68053 Document # 001-06120 Rev *F Page 13 of 39 6F P A4 or FIFOADR0 I/O/Z I (P A4) Multiplexed pin whose function is selected by: IFCONFIG[1:0] . PA 4 is a bidirectional IO port pin. FIFOADR0 is an i nput-only address select for the slave FIFO’s connected to FD[7:0] or FD[15:0]. 8C P A5 or FIFOADR1 I/O/Z I (P A5) Multiplexed pin whose functio[...]

CY7C68053 Document # 001-06120 Rev *F Page 14 of 39 PORT D 8A PD0 or FD[8] I/O/Z I (PD0) Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG .0 (wordwide) bi ts. FD[8] is the bidirection al FIFO/GPIF data bus. 7A PD1 or FD[9] I/O/Z I (PD1) Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG .0 ([...]

CY7C68053 Document # 001-06120 Rev *F Page 15 of 39 2G IFCLK I/O/Z Z Interface Clock, u sed for syn chronousl y clocking data into or out of the slave FIFO’s. IFCLK also serves as a timing reference for a ll slave FIFO control signals and GPIF . When internal clocking is use d (IFCONFIG . 7 = 1) the IFCLK pin can be configured to out put 30/48 MH[...]

CY7C68053 Document # 001-06120 Rev *F Page 16 of 39 5.0 Register Summary FX2LP18 register bit definit ions are described in the MoBL-USB TRM in greater de tail. T able 5-1. FX2 LP18 Register Summary Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access GPIF W aveform Me mories E400 128 WA VE DAT A GPIF W aveform Descriptor 0, 1, 2, 3 dat[...]

CY7C68053 Document # 001-06120 Rev *F Page 17 of 39 E62C 1 ECC1B2 ECC1 Byte 2 Address COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 00000000 R E62D 1 ECC2B0 ECC2 Byte 0 Address LINE15 LINE14 LINE13 LINE12 LINE1 1 LINE10 LINE 9 LINE8 00000000 R E62E 1 ECC2B1 ECC2 Byte 1 Address LINE7 LINE6 LINE5 LINE 4 LINE3 LINE2 LINE1 LINE0 0 0000000 R E62F 1 ECC2B2[...]

CY7C68053 Document # 001-06120 Rev *F Page 18 of 39 E65E 1 EPIE End point Interrupt Enables EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OU T EP0IN 00000000 RW E65F 1 EPIRQ [1 1] Endpoint Interrupt Requests EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OU T EP0IN 0 RW E660 1 GPIFIE [10] GPIF Interrupt Enable 0 0 0 0 0 0 GPIFWF GPIFDONE 00000000 RW E661 1 GPIFIRQ [10] GPIF In[...]

CY7C68053 Document # 001-06120 Rev *F Page 19 of 39 E6A1 1 EP1OUTCS Endpoint 1 OUT Cont rol and S ta tus 0 0 0 0 0 0 BUSY ST ALL 00000000 bbbbbbrb E6A2 1 EP1INCS Endpoin t 1 IN Control an d Sta t u s 0 0 0 0 0 0 BUSY ST ALL 00000000 bbbbbbrb E6A3 1 EP2CS End point 2 C ontrol an d Sta t u s 0 NP AK2 NP AK1 NP AK0 FULL EMPTY 0 ST ALL 0010 1000 rrrrrr[...]

CY7C68053 Document # 001-06120 Rev *F Page 20 of 39 E6CF 1 GPIFTCB2 [10] GPIF T ransaction Count Byte 2 TC23 TC22 TC21 TC20 TC19 TC18 TC17 TC16 00000000 RW E6D0 1 GPIFTCB1 [10] GPIF T ransaction Count Byte 1 TC15 TC14 TC13 TC12 TC1 1 TC10 TC9 TC8 0000 0000 RW E6D1 1 GPIFTCB0 [10] GPIF T ransaction Count Byte 0 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 000000[...]

CY7C68053 Document # 001-06120 Rev *F Page 21 of 39 81 1 SP S tack Pointer D7 D6 D5 D4 D3 D2 D1 D0 000001 1 1 RW 82 1 DPL0 Data Pointer 0 L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW 83 1 DPH0 Data Pointer 0 H A15 A14 A13 A1 2 A1 1 A10 A9 A8 00000000 RW 84 1 DPL1 [12] Data Pointer 1 L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW 85 1 DPH1 [12] Data Pointer 1 H A15[...]

CY7C68053 Document # 001-06120 Rev *F Page 22 of 39 C9 1 Reserved CA 1 RCAP2L Captur e for T imer 2, auto- reload, up- counter D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW CB 1 RCAP2H Captur e for T imer 2, auto- reload, up- counter D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW CC 1 TL2 T imer 2 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW CD 1 TH2 T imer 2 reload H [...]

CY7C68053 Document # 001-06120 Rev *F Page 23 of 39 6.0 Absolute Maximum Ratings S torage T emperature . .............. ............ .............. .............. ........... .............. .............. ........... ... ........... .............. ...... – 65°C to +150°C Ambient T emperature with Pow er Supplied Industrial ......... ...........[...]

CY7C68053 Document # 001-06120 Rev *F Page 24 of 39 8.0 DC Characteristics T able 8-1. DC Characteristics Parameter Description Conditions Min. Ty p . Ma x. Unit AV CC 3.3 V supply (to Osc. and PHY) [15] 3.00 3.3 3.60 V V CC_IO 1.8V to 3.3V supply (to I/O) 1.71 1.8 3.60 V V CC_A 1.8 V supply to Analog Core 1.71 1.8 1.89 V V CC_D 1.8 V supply to Dig[...]

CY7C68053 Document # 001-06120 Rev *F Page 25 of 39 9.0 AC Electrical Characteristics 9.1 USB T ransceiver USB 2.0-compliant in full- and high -speed modes. 9.2 GPIF Synchronous Signa ls 8 DATA(output) t XGD IFCLK RDY X DATA(input) valid t SRY t RYH t IFCLK t SGD CTL X t XCTL t DAH N N+1 GPIFADR[8:0] t SGA Figure 9-1. GPIF Sync hronous Signa ls Tim[...]

CY7C68053 Document # 001-06120 Rev *F Page 26 of 39 9.3 Slave FIFO Synchronous Read IFCLK SLRD FLAGS SLOE t SRD t RDH t OEon t XFD t XFLG DATA t IFCLK N+1 t OEoff N Figure 9-2. Slave FIFO Synchronou s Read Timing Diagram [17] T able 9-3. Slave FIFO Synchron ous Read Parameters with Interna lly Sourced IFCLK [18] Parameter Description Min. Max. Unit[...]

CY7C68053 Document # 001-06120 Rev *F Page 27 of 39 9.4 Slave FIFO Asynchronous Read SLRD FLAGS t RDpwl t RDpwh SLOE t XFLG t XFD DATA t OEon t OEoff N+1 N Figure 9-3. Sla ve FIFO Asynchrono us Read T iming Diagram [17] Note 20. Slave FIFO asynchronous pa rameter values use internal IFCLK setting at 48 MHz. T able 9-5. Slave FIFO Asynchrono us Read[...]

CY7C68053 Document # 001-06120 Rev *F Page 28 of 39 9.5 Slave FIFO Synchronous W rite Z Z t SFD t FDH DATA IFCLK SLWR FLAGS t WRH t XFLG t IFCLK t SWR N Figure 9-4. Slave FI FO Synchronous W rite T iming Dia gram [17] T able 9-6. Slave FIFO Synchronou s Write Parameters with Internally Sourced IFCLK [18] Parameter Description Min. Max. Unit t IFCLK[...]

CY7C68053 Document # 001-06120 Rev *F Page 29 of 39 9.6 Slave FIFO Asynchronous W rite 9.7 Slave FIFO Synchronous Packet End S trobe DATA t SFD t FDH FLAGS t XFD SLWR/SLCS# t WRpwh t WRpwl Figure 9-5. Slave FI FO Asynchronous Write T iming Diagram [17] T able 9-8. Slave FIFO Asynchrono us Write Parameters with Internally Sourced IFCLK [20] Paramete[...]

CY7C68053 Document # 001-06120 Rev *F Page 30 of 39 There is no specific timing requ irement that nee ds to be met for asserting the PKTEND pin with regards to asserting SL WR. PKTEND can be asserted with the last data value clocked into the FIFO’s or thereafter . The only consideration is that the set- up time t SPE and the hold time t PEH must [...]

CY7C68053 Document # 001-06120 Rev *F Page 31 of 39 9.9 Slave FIFO Output Enable 9.10 Slave FIFO Address to Flags/Dat a T able 9-12. Slave F IFO Output Enable Pa rameters Parameter Description Min. Max. Unit t OEon SLOE Assert to FIFO DA T A Outp ut 10.5 ns t OEoff SLOE Deassert to FIFO DA T A Hold 2.15 10.5 ns T able 9-13. Slave FIFO Address to Fl[...]

CY7C68053 Document # 001-06120 Rev *F Page 32 of 39 9.1 1 Slave FIFO Synchronous Address 9.12 Slave FIFO Asynchronous Address T able 9-14. Slave FIFO Synchronous Ad dress Parameters [10] Parameter Description Min. Max. Unit t IFCLK Interface Clock Period 20.83 200 ns t SF A FIFOADR[1:0] to Clock Set-up T ime 25 ns t FA H Clock to FIFOADR[1:0] Ho ld[...]

CY7C68053 Document # 001-06120 Rev *F Page 33 of 39 9.13 Sequence Diagram V arious sequence diagrams and examples are presented in this section. 9.13.1 Singl e and Burst Synchronous Read Example Figure 9-13 shows the timi ng relationship of the SLA VE FIFO signals during a synch ronous FIFO read using IFCLK as the synchronizing clock. T he diagram [...]

CY7C68053 Document # 001-06120 Rev *F Page 34 of 39 9.13.2 Singl e and Burst Synchronous Write Figure 9-15 shows the timi ng relationship of the SLA VE FIFO signals during a synchronous write using IFCLK as the synchronizing clock. The diagram illustrates a single write followed by burst write of 3 bytes and committing all 4 byte s as a short packe[...]

CY7C68053 Document # 001-06120 Rev *F Page 35 of 39 9.13.3 Seque nce Diagram of a Single and Burst Asynch ronous Read Figure 9-16 illustrates the timing rel ationship of the SLA VE FIFO signals during an asynchronous FIFO read. It shows a single read followed by a burst read. • At t = 0, the FIFO address is stable and the SLCS signal is asserted.[...]

CY7C68053 Document # 001-06120 Rev *F Page 36 of 39 9.13.4 Seque nce Diagram of a Single and Burst Asynch ronous Write Figure 9-18 illustrates the timing rel ationship of the SLA VE FIFO write in an asynchron ous mode. The diagram shows a single wri te followe d by a burst write of 3 bytes an d committing the 4-byte-short packet using PKTEND. • A[...]

CY7C68053 Document # 001-06120 Rev *F Page 37 of 39 10.0 Ordering Information 1 1.0 Package Diagram The FX2LP18 is a vailable in a 56-pin VFBGA package. Figure 1 1-1. 56 VFBGA (5 x 5 x 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56 T able 10-1. Ordering Information Ordering Code Package T ype RAM Size # Prog I/Os 8051 Address/Data Busses CY7C68053-56BAXI 56 VF[...]

CY7C68053 Document # 001-06120 Rev *F Page 38 of 39 © Cypress Semi conductor Corpora tion, 2006. The i nformation cont ained here in is subject to ch ange withou t notice. Cypress S emic onductor Corporation assu mes no responsibility for the use of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor does it convey or imply a[...]

CY7C68053 Document # 001-06120 Rev *F Page 39 of 39 Document History Page Document Title: CY7C68053 MoBL-USB FX2LP18 USB Microcontroller Document Number: 001-06120 REV . ECN N O. Issue Date Orig. of Change Description of Change ** 430449 03 /03/06 OSG New data sheet *A 434754 03/24/06 OSG In Section 3. 3, stated that SCL and SDA pi ns can be connec[...]