Excalibur electronic A-MNL-NIOSPROG-01.1 manual

A-MNL-NI OSPROG- 01.1 Nios Embedded Processor 101 Innov atio n Drive San Jose , CA 95134 (408) 544 -7000 http:// www.altera.com Programm er’s Refere nce Man ual July 2001 Version 1.1.1[...]

ii Altera Corporat ion Nios Embedde d Processor Progra mmer ’ s R efer ence Man ual Copyrig ht  2001 A ltera Corporation. Alter a, The Programmable So lutions Company, the s tylized Altera logo, s pecific device designations, a nd all other words and logos that are identified as trademarks and /or service marks are unless noted otherwise, the [...]

Alt era Corporat ion iii Abo ut this Ma nu al This ma nual pro vides compre hensiv e informati on about t he Nios TM em bedded pro ces sor. The terms Ni os p roces sor o r Ni os em be dded proce sso r are us ed wh en referring to the Altera soft core micropro cessor in a general or abstract contex t. The term Nios CPU is us ed when referrin g to th[...]

iv Altera Corporat ion About this Man ual How to C ontact Altera For the most up -to-dat e infor mation a bout Altera p roducts, g o to the Alter a worl d-wi de web site at htt p://w ww.al tera .com . For addition al information about Alte ra product s, consult the sources shown in Table 2 . Not e: (1) You can also contact your local Altera sales o[...]

Altera Corporat ion v Getting About this Manual T ypo graphic Convent ions The Nios E mbe dde d P roc essor P rogr amme r’ s Re fere nc e Ma nual uses the typogr aphic c onvent ions show n in T able 3. Tabl e 3. Co nvent ion s Visua l Cu e Mea ning Bo ld Ty pe w ith In i tia l Capi tal Let ters Comm and names , dialog box titles , checkbox option[...]

Notes: vi Altera Corporat ion[...]

Alt era Corporat ion vii Cont ents How t o Contac t Al tera ....... ........ ......... ........ ..... ........ ......... ........ ......... ........ ......... .... ........ ...... ... ...... iv Typog raphic Co nventions ..... ......... ........ ......... .... ........ ......... ........ ......... ........ ......... ........ ......... . ... ....v Ov[...]

vi ii Alt era Corporat ion Content s 32-Bit In struction Set .......... .......... .... ......... .......... ......... ......... ......... ........ 33 ABS .. ........ ......... ........ ......... ........ ......... .... ........ ......... ........ ......... ........ ......... ........ ......... .... ......... ........ .. 3 4 ADD .... ........ .....[...]

ix Alt era Corporat ion Content s RET ...... ........ ......... ........ ......... ........ ......... ........ ......... .... ......... ........ ......... ........ ......... ....... ..... ......... ...... 79 RLC...... ........ ......... .... ......... ........ ......... ........ ......... ........ ......... ........ ......... .... ........ ........[...]

Notes: x Altera Corporat ion[...]

Alt era Corporat ion xi List o f T able s Table 1. Revision His tory ............ ........ ......... ........ .... ......... ........ ......... ........ ......... ........ ......... .. ...... ......... .... .. iii Table 2. How to C ontact Altera ...... ........ ......... .... ......... ........ ......... ........ ......... ........ .... ......... .[...]

Notes: xii Altera Corp oration[...]

Alt era Corporat ion 1 Overvi ew 1 Overview Introdu ction The Nios TM embedde d proces sor is a s oft cor e CPU o ptimized for programmable log ic and s ystem-on-a-pr ogrammable chip (SOPC) integrati on. It is a c onfigurable , genera l-purpose RISC p rocessor that can be combined with us er logic and progra mmed into an A ltera programmable logic [...]

2 Altera Corporat ion Over view The Nios C PU ship s with the GNUPro c ompiler an d debugger from Cygnus, a n industr y-stand ard open -source C/C ++ compiler , linker an d debugger too lkit. The GNUPro t oolkit inclu des a C/C++ c ompiler, macr o- assemble r, linke r, debu gger, binar y utilitie s, an d librarie s. Inst ruction Set The Nios ins tr[...]

Altera Corporat ion 3 Gettin g Ov ervi ew Overvi ew 1 . Table 6. Pr ogr am mer’ s Mo del 31 16 15 0 I N %i7 %r 31 SAVE D return -add ress %i6 %r30 %fp — frame pointer %i5 %r29 %i4 %r28 %i3 %r27 %i2 %r26 %i1 %r25 %i0 %r24 L O C A L %L7 %r23 %L6 %r22 %L5 %r21 %L4 %r20 %L3 %r19 Base-pointer 3 for STP/LDP (or general-pur pose local) %L2 %r18 Base-p[...]

4 Altera Corporat ion Over view The K Regi ster The K r egister is an 11-bit p refix va lue and is always se t to 0 by ever y instruct ion excep t PFX. A PFX inst ruction se ts K directly from the I MM11 instruct ion field. Register K contai ns a non-z ero value on ly for an instruct ion immediat ely followin g PFX. A PFX in struc tion disa bles in[...]

Altera Corporat ion 5 Gettin g Ov ervi ew Overvi ew 1 Interrrupt Enable (IE) IE is the interr upt enable bi t. When IE=1, it enab les extern al interrup ts and interna l exc eptions . IE=0 disabl es ex ternal i nter rupts an d ex cepti ons. Software T RAP instr uctions w ill still execute no rmally ev en when IE =0. Note tha t IE can be set direct [...]

6 Altera Corporat ion Over view Condition Code Flags Some ins tructions modify the co ndition code fla gs. These flags are the four le ast s ignifica nt bi ts of th e stat us reg ister as shown in Table 7. ISTATUS (%ctl1) ISTAT US is the saved copy of the STATUS reg ister. When an e xception is process ed, the value of th e STATU S regis ter is c o[...]

Altera Corporat ion 7 Gettin g Ov ervi ew Overvi ew 1 CLR_IE(%ctl 8) Any WR CTL ope ratio n to the CLR_I E regist er c lear s the I E bit in the STATUS r egiste r (IE ← 0) and the WRCTL va lue is ignored. A RDCTL operat ion from CLR_IE produ ces an undefined res ult. SET_IE (%ctl9) Any WR CTL oper ation t o the SE T_IE r egist er sets the IE bit [...]

8 Altera Corporat ion Over view Read ing from Me mor y (or Peri pherals ) The Nios C PU can only perform al igned memory acc esses. A 32-bit read operati on can only read a full wor d star ting at a b yte add ress th at is a multiple of 4. A 16-bit r ead operati on can on ly read a half-w ord startin g at a byte a ddress t hat is a multiple of 2. I[...]

Altera Corporat ion 9 Gettin g Ov ervi ew Overvi ew 1 Writing to Memor y (or Peripherals) The Nios C PU can pe rform aligne d writes to memory in w idths of b yte, half-word, or word (only the 32-bit Nios CPU can write a word). A word (32-bit N ios CPU) ca n be writ ten t o any ad dress th at is a mult iple of 4 in one ins truction. A half-wor d ca[...]

10 Altera Corporat ion Over view Code E xample 2 sho ws ho w to write a single byte to m emory, eve n if th e address of the b yte is n ot nativ e-word-alig ned. Code Exam ple 2 : Single Byte Writ ten to Mem or y — Address is not Native-word-alig ned Addres sing Modes The topi cs in th is sec tion inc ludes a de scriptio n of the following addres[...]

Altera Corporat ion 11 Gettin g Ov ervi ew Overvi ew 1 The followin g example show s an ADDI instr uction being used both with and wi tho u t a PF X. Code E xample 3: The AD DI Instructio n Used with /without a PFX Besides a rithmetic a nd logical instruction s, seve ral other inst ructions us e immedia te-mo de const ants o f vario us wid ths, a n[...]

12 Altera Corporat ion Over view Full W idth Regist er -Indirec t The LD and ST inst ructi ons can load and st ore, respe ctively, a full na tive- word t o or from a reg ister u sing a nother re giste r to spe cify th e ad dress. The ad dress is first aligned d ownward t o a nat ive-word alig ned addre ss, as de scribe d in th e “ Memor y Acce ss[...]

Altera Corporat ion 13 Gettin g Ov ervi ew Overvi ew 1 Full W idth Regist er -Indir ect with Off set The LDP, LDS, STP and STS ins tructions can loa d or s tore a full na tive- word t o or from a regist er u sing anoth er re gister to spe cify an a ddress, and an immediate value to specify an offset, in native words, from that address . Unli ke th [...]

14 Altera Corporat ion Over view Thes e in stru ctions m ay each only u se t he sta ck po inte r, re gist er %sp (eq uiva lent t o %o6 ), a s t heir addr ess r egis ter, and may o nly u se regi ster %r0 (e quival ent to %g0, but must be call ed %r0 in the asse mbly instruct ion) as the dat a regis ter. The se instr uctions are conv enient to use wi[...]

Altera Corporat ion 15 Gettin g Ov ervi ew Overvi ew 1 Abs olu te-Jump I nst ruct ion s There are two absolut e (computed) jump instruct ions: JMP a nd CALL. The jump- tar get a ddre ss is giv en by the cont ents o f a gene ral- purp ose regi ster . Th e re giste r c ontents ar e lef t-s hift ed by one and t rans ferr ed into the PC. CALL is identi[...]

16 Altera Corporat ion Over view Except ions The topi cs i n this sec tion inc lude a de scription of the fo llowing: ■ Except ion vect or tabl e ■ How e xternal hard ware interru pts, interna l exception s, regis ter window unde rflow, register w indow ove rflow and T RAP instr uctions ar e hand led ■ Direct s oftw are ex cept ions (TRA P) a[...]

Altera Corporat ion 17 Gettin g Ov ervi ew Overvi ew 1 Exte rnal Hardw are Inte rrupt So urces An ex ternal sourc e can re ques t a ha rdware interr upt by d riving a 6-b it interrupt number on the Ni os CPU ir q_number input s while simultan eously asse rting tru e (1) th e Nios CPU ir q input p in. Th e Nios CPU will p rocess t he indic ated e xc[...]

18 Altera Corporat ion Over view When a SAV E inst ructi on causes a reg ister w indow und erflow e xception , CWP is decremen ted o nly once be fore contr ol is passed to the excepti on- handling subrou tine. T he unde rflow ex cepti on handle r wil l see CWP = LO_LIM IT – 1. Th e registe r wind ow underflow except ion is e xception number 1. Th[...]

Altera Corporat ion 19 Gettin g Ov ervi ew Overvi ew 1 The act ion take n by the overflow excepti on hand ler subr outine depends upon the requir ements of the sy stem. F or syste ms runn ing larg er or mor e complex co de, the overflow and underflow handlers can impl ement a virtual reg ister file that e xtends beyon d the limits of the ph ysical [...]

20 Altera Corporat ion Over view 3. IE is se t to 0, disabling inte rrupt s. 4. IPRI i s set with th e 6-b it num ber of the e xception. 5. The ad dre ss of th e n ext non- execut ed i nstru ction i n the inter rupted progra m is transferr ed into %o7. 6. The start-ad dress of the ex ception h andler is fetched from the exceptio n vecto r table and[...]

Altera Corporat ion 21 Gettin g Ov ervi ew Overvi ew 1 Inter rupts are autom atical ly disa bled upon en try to an exception ha ndler, so the re is no danger o f ISTAT US being overwritt en by a subseq uent interrupt or e xception. The case of neste d except ion han dlers (exce ption handlers that u se or re-ena ble ex ceptions) is discuss ed in d [...]

22 Altera Corporat ion Over view Comp lex Ex cepti on Ha ndlers An exce ption ha ndler is cons idered comple x if it viola tes a ny of the requireme nts of a simple ex ceptio n handler , listed above. Comple x except ion handle rs allow nested ex cepti on handlin g and th e execution of more complex code (e.g. subrouti nes th at SAVE and R ESTOR E)[...]

Altera Corporat ion 23 Gettin g Ov ervi ew Overvi ew 1 Pipe line Op erati on The Nios CPU is p ipeline d RISC arch itecture . The pi peline implementat ion is hidden fr om softw are except for bra nch del ay slots and when CWP is mo difi ed by a WRC TL direc t w rite. The pipel ine s tag es include: ■ Instruction Fetch — the Nios C PU issues an[...]

24 Altera Corporat ion Over view After b ranch instr uction (b) is take n, inst ructio n (c) is ex ecuted befor e contr ol is tra nsfer red to the br anch t arget (e). The ex ecution sequ ence o f the above code fragment would be (a), (b), (c ), and (e). Instruction (c) is instruct ion (b) ’ s branch d elay slot . Instruct ion (d) i s not exe cut[...]

Altera Corporat ion 25 Gettin g Ov ervi ew Overvi ew 1 Table 16 . Notat ion D eta ils Not ati on Me aning Not ati on Me ani ng X ← Y X is w ritten with Y X >> n T he value X af ter be ing right- shifted n bit positions ∅← e Expre ssion e is evaluat ed, and the res ult is d iscarded X << n T he value X after b eing lef t-shif ted n[...]

26 Altera Corporat ion Over view In struc tion Form at (S heet 1 of 2) RR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 op6 B A R i 5 1 5 1 4 1 3 1 2 1 1 1 0 98765 43210 op6 IMM5 A R i 4 1 5 1 4 1 3 1 2 1 1 1 0 98765 43210 op6 0 I MM4 A RPi5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 op4 P B A R i 6 1 5 1 4 1 3 1 2 1 1 1 0 98765 43210 op5 IMM6 A R i 8 1 5 1 4 1[...]

Altera Corporat ion 27 Gettin g Ov ervi ew Overvi ew 1 i 8 v 1 5 1 4 1 3 1 2 1 1 1 0 98765 43210 op6 op2v IMM8v i 6 v 1 5 1 4 1 3 1 2 1 1 1 0 98765 43210 op6 op2v 0 0 IMM6v Rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 op6 op5w A i 4 w 1 5 1 4 1 3 1 2 1 1 1 0 98765 43210 op6 op5w 0 IMM4w w 1 5 1 4 1 3 1 2 1 1 1 0 98765 43210 op6 op5w 0 0 0 0 0 In struc [...]

28 Altera Corporat ion Over view Table 17 . 3 2- bit Maj or Opco de Table (S hee t 1 of 3) Opco de M nem on ic For mat Su mma ry 000000 ADD RR RA ← RA + RB Flags af fected: N, V, C, Z 000001 ADDI Ri5 RA ← RA + (0 × 0 0.0 0 : K : I MM 5 ) Flags af fected: N, V, C, Z 000010 SUB RR RA ← RA – RB Flags af fected: N, V, C, Z 000011 SUBI Ri5 RA ?[...]

Altera Corporat ion 29 Gettin g Ov ervi ew Overvi ew 1 010111 ST RR Mem32 [align 32( RB + ( σ (K) × 4))] ← RA 011000 STS8s i10 b n Mem3 2 [align32( %sp + IMM10 )] ← b n %r0 where n = IMM 10[1..0] 011001 STS 16s i9 h n Mem32 [ align32( %sp + IM M9 × 2)] ← hn %r0 where n = IMM9[ 0] 011010 EXT16d RR RA ← (0 × 00.00 : h n RA) where n = RB [[...]

30 Altera Corporat ion Over view 011111 01111 011111 10000 ST8d R w b n Mem3 2 [alig n32(RA +( σ (K ) × 4))] ← b n %r0 where n = RA[1 ..0] 011111 10001 ST1 6d Rw h n Mem3 2 [alig n32(RA + ( σ (K) × 4))] ← h n %r 0 where n = RA[ 1] 011111 10010 FILL8 Rw %r0 ← ( b0 RA : b0 RA : b0 RA : b 0 RA) 011111 10011 FILL1 6 R w %r0 ← ( h0 RA : h0 R[...]

Altera Corporat ion 31 Gettin g Ov ervi ew Overvi ew 1 The follow ing pseudo-in struc tions are g enerated b y nios-e lf-gcc (GNU compiler) a nd underst ood by nios-elf-a s (GNU asse mbler). The follow ing operato rs are un derstood b y nios-elf-as. T hese oper ators may be used with con stants and symbolic a ddresses, and ca n be correctl y resolv[...]

Notes: 32 Altera Corporat ion[...]

Alt era Corporat ion 33 2 32-Bit Instruction Set This sec tion provid es a det ailed de scription of th e 32-bit Ni os CPU instruct ions. T he descr iptions are arran ged in a lphabet ical order accord ing to inst ruct ion mnemoni c. Each i nstructi on pa ge include s the following info rmation: ■ Instruc tion mnem onic and de scription ■ Descr[...]

34 Altera Corporat ion 32- Bi t Ins tr uct i on Se t ABS Absolute Va lue Operati on: RA ← |RA| Assembl er Syn tax: ABS %r A Example: AB S %r6 Descripti on: Calculate t he absolu te value of RA; store the result in RA. Condi tion Codes: F lags: U naffect ed Instructi on Format: Rw Instructi on Fields: A = Register inde x of opera nd RA 1 5 1 4 1 3[...]

Altera Corporat ion 35 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set AD D Add Without Carr y Operati on: RA ← RA + RB Assembl er Syn tax: ADD %r A,%rB Example: AD D %L3,%g 0 ; ADD %g0 to %L3 Descripti on: Adds t he c ontents of regi ster A to registe r B a nd stores t he res ult in r egiste r A. Condi tion Codes: F lags: N: Re sult[...]

36 Altera Corporat ion 32- Bi t Ins tr uct i on Se t ADDI Add Immediate Operati on: RA ← RA + (0x0 0.00 : K : IMM5) Assembl er Syn tax: ADDI % rA,IMM5 Example: Not prece ded by PFX: ADDI % L5,6 ; a dd 6 to %L5 Prec eded by PFX: PFX %h i(1000) ADDI % g3,%lo(1 000) ; A DD 1000 to %g3 Desc ription : Not preceded by PFX: Adds 5-bit immediat e value t[...]

Altera Corporat ion 37 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set AN D Bitwise Logi cal AND Operati on: Not precede d by PFX: RA ← RA & RB Prec eded by PFX: RA ← RA & (0x00 .00 : K : IMM5) Assembl er Syn tax: Not p recede d by PFX: AND %r A,%rB Prec eded by PFX: PFX %h i(const) AND %r A,%lo(co nst) Example: Not prece d[...]

38 Altera Corporat ion 32- Bi t Ins tr uct i on Se t ANDN Bi twise Logi cal A ND NOT Operati on: Not precede d by PFX: RA ← RA & ~RB Prec eded by PFX: RA ← RA & ~(0x00. 00 : K : IMM5) Assembl er Syn tax: Not p recede d by PFX: ANDN % rA,%rB Prec eded by PFX: PFX %h i(const) ANDN % rA,%lo(c onst ) Example: Not prece ded by PFX: ANDN % g0[...]

Altera Corporat ion 39 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set ASR Arithmetic Shift Ri ght Operati on: RA ← (RA >> RB[4..0]), fill from left with RA[3 1] Assembl er Syn tax: ASR %r A,%rB Example: AS R %L3,%g 0 ; shif t %L3 ri ght by % g0 bits Descripti on: Arithme tically shi ft rig ht the valu e in RA by the valu e o f[...]

40 Altera Corporat ion 32- Bi t Ins tr uct i on Se t ASRI Arithmetic Shift R ight Immediate Operati on: RA ← (RA >> IMM 5), fil l from left with R A[31] Assembl er Syn tax: ASRI % rA,IMM5 Example: AS RI %i5,6 ; shift %i5 right 6 bits Descripti on: Arithme tically shif t righ t the cont ents of RA by IM M5 bi ts. If IM M5 is 31 , RA w ill be[...]

Altera Corporat ion 41 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set BGEN Bit Gen erat e Operati on: RA ← 2 IMM5 Assembl er Syn tax: BGEN % rA,IMM5 Example: BG EN %g7,6 ; set %g7 t o 64 Descripti on: Sets RA to an intege r power-of -two with t he exponent given by IMM5 . This is equiv alent to setting a sin gle bit in RA, and clear[...]

42 Altera Corporat ion 32- Bi t Ins tr uct i on Se t BR Branc h Operati on: PC ← PC + (( σ (IMM11) + 1) << 1) Assembl er Sy ntax: BR add r Example: BR Mai nLoop NOP ; (del ay s lot) Descripti on: The offset giv en by IMM11 is interpreted as a signed numb er of half-wo rds (instruc tions) rela tive to the ins truction immediately following [...]

Altera Corporat ion 43 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set BSR Bran ch T o Subr outin e Operati on: %o7 ← ((PC + 4) >> 1) PC ← PC + (( σ ( I M M 1 1 )+1 )< <1 ) Assembl er Syn tax: BSR ad dr Example: BS R SendCh arac ter NOP ; (del ay s lot) Descripti on: The offset giv en by IMM11 is interpreted as a signe[...]

44 Altera Corporat ion 32- Bi t Ins tr uct i on Se t CALL Call Subroutine Operati on: %o7 ← ((P C + 4) >> 1) PC ← (RA << 1) Assembl er Syn tax: CALL % rA Example: CA LL %g0 NOP ; (del ay s lot) Descripti on: The value of RA is shifted left by on e and transfe rred into PC. RA cont ains the addres s of the called subr outine right-sh[...]

Altera Corporat ion 45 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set CMP Com par e Operati on: ∅← RA − RB Assembl er Sy ntax: CM P %r A,%rB Example: CM P %g0,%g 1 ; set flag s by %g0 - % g1 Descripti on: Subtrac t the conte nts of R B f rom RA, and discar d the re sult. Set the cond ition code s according to the su btractio n. [...]

46 Altera Corporat ion 32- Bi t Ins tr uct i on Se t CMPI Com pare I m medi ate Operati on: ∅← R A–( 0 x 0 0 . 0 0:K :I M M 5 ) Assembl er Syn tax: CMPI & %rA ,IMM 5 Example: Not prece ded by PFX: CMPI %i3,2 4 ; compare %i3 to 24 Prec eded b y PFX: PFX %h i(1000) CMPI % i4,%lo(1 000) Desc ription : Not preceded by PFX: Subtr act a 5 -bit [...]

Altera Corporat ion 47 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set EXT16d Half-Word Extract (Dynamic) Operati on: RA ← (0x00.0 0 : hn RA) where n = RB[1] Assembl er Syn tax: EXT16d %rA ,%rB Example: LD %i3 ,[%i4] ; get 32 bits from [%i4 & 0xFF.FF .FF. FC] EXT16d %i3 ,%i4 ; extract short int at %i4 Descripti on: Extracts one o[...]

48 Altera Corporat ion 32- Bi t Ins tr uct i on Se t EXT16s Half-Wor d Extract (Static) Operati on: RA ← (0x0 0.00 : hn RA) w here n = IM M1 Assembl er Syn tax: EXT16s %rA ,IMM1 Example: EX T16s %L3,1 ; %L3 gets upper shor t int of itself Descripti on: Extracts one of the two ha lf-words in RA. The half-w ord to-be-ex tracted is ch osen by the on[...]

Altera Corporat ion 49 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set EXT8d Byte-Ext ract (Dyn amic) Operati on: RA ← (0x0 0.00.00 : bn RA) where n = RB [1..0] Assembl er Syn tax: EXT8d %rA, %rB Example: LD %g4 ,[%i0] ; get 32 bits from [%i0 & 0xFF.FF .FF. FC] EXT8d %g4, %i0 ; ex tract th e pa rticular byt e at %i0 Descripti on:[...]

50 Altera Corporat ion 32- Bi t Ins tr uct i on Se t EXT8s Byte-E xtract (Static) Operati on: RA ← (0x0 0.00.00 : bn RA) where n = IM M2 Assembl er Syn tax: EXT8s % rA,IMM2 Example: EX T8s %g6,3 ; %g6 gets the 3rd byte of itself Descripti on: Extracts one of the fou r bytes in R A. The by te to-be -extr acted is chos en by the immedia te value IM[...]

Altera Corporat ion 51 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set FI LL1 6 Hal f-W ord Fi ll Operati on: R0 ← ( h0 RA : h0 RA) Assembl er Syn tax: FILL16 %r0 ,%rA Example: FI LL16 %r0,%i3 ; %r0 gets 2 copies of %i3[ 0..1 5] ; f irst ope rand mus t be %r0 Descripti on: The least sig nificant ha lf-word of RA is copied into both h[...]

52 Altera Corporat ion 32- Bi t Ins tr uct i on Se t FILL8 Byte -Fi ll Operati on: R0 ← ( b0 RA : b0 RA : b0 RA : b0 RA) Assembl er Syn tax: FILL8 %r 0,%rA Example: FI LL8 %r0, %o3 ; %r 0 gets 4 copies of % o3[0 ..7] ; fi rst oper and must be %r0 Descripti on: The least-s ignificant byte of RA is copied int o all four byte-pos itions in %r0. %r0 [...]

Altera Corporat ion 53 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set IF0 Equi valent to SK P1 Instruc tio n Operati on: if (RA [IMM5] = = 1) then begi n if (Mem 16[PC + 2 ] is PF X) the n PC ← PC + 6 else PC ← PC + 4 en d Assembl er Syn tax: IF0 %rA,IM M5 Example: IF 0 %o3,21 ; do if 21s t bi t of %o3 is zero ADDI % g0,1 ; i ncre[...]

54 Altera Corporat ion 32- Bi t Ins tr uct i on Se t IF1 Equiva lent to SK P0 I nstru ction Operati on: if (RA [IMM5] = = 0) then begi n if (Mem 16[PC + 2 ] is PF X) the n PC ← PC + 6 else PC ← PC + 4 en d Assembl er Syn tax: IF1 %rA,IM M5 Example: AD DI %g0,1 ; include i f bi t 7 was set Descripti on: Ski p ne xt ins tru ct ion if the sing l e[...]

Altera Corporat ion 55 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set IF Rn z Equival ent t o SKPR z Instruc tion Operati on: i f ( R A==0 ) then begi n if (Mem 16[PC + 2 ] is PF X) the n PC ← PC + 6 else PC ← PC + 4 en d Assembl er Syn tax: IFRnz % rA Example: IF Rnz %o3 BSR SendIt ; only call if %o3 is not 0 NOP ; (del ay s lot)[...]

56 Altera Corporat ion 32- Bi t Ins tr uct i on Se t IFRz Equi valent to SK PRn z Inst ruc tion Operati on: if (RA ! = 0) then begi n if (Mem 16[PC + 2 ] is PF X) the n PC ← PC + 6 else PC ← PC + 4 en d Assembl er Syn tax: IFRz %r A Example: IF Rz %g3 BSR SendIt ; only call if %g3 is zero NOP ; (del ay s lot) exe cuted in either case Descripti [...]

Altera Corporat ion 57 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set IFS Con ditiona lly Execut e Ne xt Instr uctio n Operati on: if ( con di tion IM M4 is fal se ) then begi n if (Mem 16[PC + 2 ] is PF X) the n PC ← PC + 6 else PC ← PC + 4 en d Assembl er Syn tax: IFS cc _IMM4 Example: IF S cc_ne BSR Se ndIt ; o nly call if Z fl[...]

58 Altera Corporat ion 32- Bi t Ins tr uct i on Se t JMP Comp uted Jum p Operati on: PC ← (RA < < 1) Assembl er Syn tax: JMP %rA Example: JM P %o7 ; return NOP ; (del ay s lot) Descripti on: Jump to the targe t-addres s given by (RA << 1 ). Note that t he t arget add ress will always be half-word alig ned for any va lue of RA. Condi t[...]

Altera Corporat ion 59 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set LD Load 3 2-bit Data From Memo r y Operati on: Not precede d by PFX: RA ← Mem3 2[alig n32(RB) ] Prec eded by PFX: RA ← Mem3 2[alig n32(RB + σ (K) × 4))] Assembl er Syn tax: LD %rA,[%r B] Example: Not prece ded by PFX: LD %g0 ,[%i3] ; load word a t [% i3] into [...]

60 Altera Corporat ion 32- Bi t Ins tr uct i on Se t LDP Load 32- bit D ata Fr om M emor y ( Point er Add ressing Mo de) Operati on: Not precede d by PFX: RA ← Mem3 2[alig n32(RP + (IMM5 × 4)) ] Prec eded by PFX: RA ← Mem3 2[alig n32(RP + ( σ (K : IM M5) × 4)) ] Assembl er Syn tax: LDP %r A,[%rP,I MM5] Example: Not prece ded by PFX: LDP %o 3[...]

Altera Corporat ion 61 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set LDS Load 32- bit Da ta F rom Me mor y (Stack Addr essing Mod e) Operati on: RA ← Mem32[a lign32(% sp + (IMM8 × 4) )] Assembl er Syn tax: LDS %r A,[%sp,I MM8] Example: LD S %o1,[% sp,3 ] ; load %o1 from stack + 12 ; seco nd regis ter can only be %sp Descripti on: [...]

62 Altera Corporat ion 32- Bi t Ins tr uct i on Se t LRET Equiva lent to JM P %o 7 Operati on: PC ← (%o7 << 1) Assembl er Syn tax: LRET Example: LR ET ; ret urn NOP ; (del ay s lot) Descripti on: Jump to th e target-ad dress given by (% o7 << 1 ). Note that the targe t address will always be half-word alig ned for any va lue of %o7. C[...]

Altera Corporat ion 63 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set LSL Logi cal Shi ft Left Operati on: RA ← (RA << RB [4..0]), zero -fill from rig ht Assembl er Syn tax: LSL %rA,% rB Example: LS L %L3,%g 0 ; Shif t %L3 le ft b y %g0 bi ts Descripti on: The value in RA is shifted-le ft by the numbe r of bits indicated by RB[...]

64 Altera Corporat ion 32- Bi t Ins tr uct i on Se t LSLI Logical Shift Left Immediate Operati on: RA ← (RA << IM M5), zero -fill fr om right Assembl er Syn tax: LSLI %r A,IMM5 Example: LS LI %i1,6 ; Shift %i1 left by 6 b its Descripti on: The value in RA is shifted-le ft by the numbe r of bits indicated by IMM5. Condi tion Codes: F lags: U[...]

Altera Corporat ion 65 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set LSR Logical Shift Ri ght Operati on: RA ← (RA >> RB [4..0]), zero -fill from left Assembl er Syn tax: LSR %rA,% rB Example: LS R %L3,%g 0 ; Shif t %L3 ri ght by % g0 bits Descripti on: The value in RA is shifted- right by the nu mber of bits indi cated by RB[...]

66 Altera Corporat ion 32- Bi t Ins tr uct i on Se t LSRI Logi cal Sh ift R ight Immedi ate Operati on: RA ← (RA >> IM M5), zero -fill fr om left Assembl er Syn tax: LSRI %r A,IMM5 Example: LS RI %g1,6 ; Right-shi ft %g1 by 6 bits Descripti on: The value in RA is shifted-rig ht by the number of bits indicated by IMM5. The result is left-fil[...]

Altera Corporat ion 67 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set MOV Regi ster-to-Reg ister M ove Operati on: RA ← RB Assembl er Syn tax: MOV %rA,% rB Example: MO V %o0,%L 3 ; copy %L3 into %o0 Descripti on: Copy the con tents of RB to RA . Condi tion Codes: F lags: U naffect ed Instructi on Format: RR Instructi on Fields: A = [...]

68 Altera Corporat ion 32- Bi t Ins tr uct i on Se t MOVHI Move Immediate Into High Half-Wo rd Operati on: h1 RA ← (K : IMM5), h0 RA unaffected Assembl er Syn tax: MOVHI %rA, IMM5 Example: Not prece ded by PFX: MOVHI %g3,23 ; upp er 16 bi ts of %g 3 ge t 23 Prec eded by PFX: PFX %h i(100) MOVHI %g3, %lo(100) ; upper 16 bits of %g3 get 100 Desc ri[...]

Altera Corporat ion 69 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set MOVI Mov e Imme di ate Operati on: RA ← (0x0 0.00 : K : IMM5) Assembl er Syn tax: MOVI %r A,IMM5 Example: Not prece ded by PFX: MOVI %o3,7 ; load %o3 with 7 Prec eded by PFX: PFX %h i(301) MOVI % o3,%lo(3 01) ; lo ad %o3 w ith 301 Desc ription : Not preceded by PF[...]

70 Altera Corporat ion 32- Bi t Ins tr uct i on Se t MSTEP Multiply-Step Operati on: If (R0[ 31] = = 1) then R0 ← (R 0 << 1 ) + RA el se R0 ← (R0 << 1) Assembl er Sy ntax: MS TEP %rA Example: MS TEP %g1 ; accumulate par tial -product Descripti on: Implement s a single step of an unsign ed multiply. The m ultiplier in %r 0 and multip[...]

Altera Corporat ion 71 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set MUL Multiply Operati on: R0 ← (R0 & 0x0 000.f f ff) x ( RA & 0x0000. ff ff ) Assembl er Sy ntax: MU L %r A Example: MU L %i5 Descripti on: Multiply the low half-word s of %r0 and %rA toge ther, and put the 32 bit resu lt into %r0. This performs an inte ger[...]

72 Altera Corporat ion 32- Bi t Ins tr uct i on Se t NEG Arithmetic Negation Operati on: RA ← 0 – RA Assembl er Sy ntax: NE G %rA Example: NE G %o4 Descripti on: Negate the v alue of RA. Per form two ’ s comple ment negation of RA. Condi tion Codes: F lags: U naffect ed Instructi on Format: Rw Instructi on Fields: A = Register inde x of opera[...]

Altera Corporat ion 73 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set NOP Equi valent to MO V %g0 , %g 0 Operati on: None Assembl er Syn tax: NOP Example: NO P ; do n othi ng Descripti on: No operat ion. Condi tion Codes: F lags: U naffect ed Instructi on Format: RR Instructi on Fields: None 1 5 1 4 1 3 1 2 1 1 1 0 98765 43210 0011 00[...]

74 Altera Corporat ion 32- Bi t Ins tr uct i on Se t NOT Logica l N ot Operati on: RA ← ~RA Assembl er Syn tax: NOT %rA Example: NO T %o4 Descripti on: Bitwise-inv ert the val ue of RA. Condi tion Codes: F lags: U naffect ed Instructi on Format: Rw Instructi on Fields: A = Register inde x of operand R A 1 5 1 4 1 3 1 2 1 1 1 0 98765 43210 0111 11[...]

Altera Corporat ion 75 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set OR Bitwise Logical OR Operati on: Not precede d by PFX: RA ← RA | RB Prec eded by PFX: RA ← RA | (0 x00.00 : K : IMM5 ) Assembl er Syntax: No t precede d by PFX: OR %rA,%rB Prec eded by PFX: PFX %h i(const) OR %ra,%lo (const) Example: Not prece ded by PFX: OR %i[...]

76 Altera Corporat ion 32- Bi t Ins tr uct i on Se t PFX Prefix Operati on: K ← IMM11 (K set to z ero b y all oth er instru ctions) Assembl er Syn tax: PFX IM M11 Example: PF X 3 ; af fect s next i nstructi on Descripti on: Loads t he 11 -bit c onstant value IMM11 into the K-registe r. The value in t he K-regis ter may affect th e next instruc ti[...]

Altera Corporat ion 77 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set RDCTL Read Contr ol Re gister Operati on: RA ← CTLk Assembl er Syn tax: RDCTL %rA Example: Not prece ded by PFX: RDCTL %g7 ; Loa ds % g7 from STA TUS reg (%c tl0) Prec eded by PFX: PFX 2 RDCTL %g7 ; Loa ds % g7 from WVA LID reg (%ctl2) Desc ription : Not preceded [...]

78 Altera Corporat ion 32- Bi t Ins tr uct i on Se t RE STORE Res tore C aller’ s Reg ister Wind ow Operati on: CWP ← CWP + 1 if (old- CWP = = HI_LIM IT) then TRAP #2 Assembl er Syn tax: RESTOR E Example: RE STORE ; bump up the register win dow Descripti on: Moves C WP up by one position in the reg ister file. I f CWP is e qual to HI_L IMIT (fr[...]

Altera Corporat ion 79 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set RET Equi valent to J MP % i7 Operati on: PC ← (% i7 << 1 ) Assembl er Syn tax: RET Example: RE T ; retu rn RESTOR E ; (res tore s caller ’ s regis ter window) Descripti on: Jump to t he targe t-address giv en by (%i7 << 1 ). Note that the target addr[...]

80 Altera Corporat ion 32- Bi t Ins tr uct i on Se t RLC Rota te Le ft T hrough Ca rr y Operati on: C ← RA[31] RA ← (RA << 1 ) : C Assembl er Syn tax: RLC %rA Example: RL C %i4 ; rotate %i4 l eft one bit Descripti on: Rotates the bits of RA left by one pos ition throug h the carry flag. Condi tion Codes: F lags: C: Bit 31 of RA be fore ro[...]

Altera Corporat ion 81 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set RRC Rot ate Ri ght Through C arr y Operati on: C ← RA[0] RA ← C:( R A> > 1 ) Assembl er Syn tax: RRC %rA Example: RRC %i4 ; rotat e %i4 right one bit Descripti on: Rotates the bit s of RA right by one position thro ugh the carry flag . If Precede d by PFX:[...]

82 Altera Corporat ion 32- Bi t Ins tr uct i on Se t SA VE Sav e Calle r ’ s R egiste r Wind ow Operati on: CWP ← CWP – 1 %sp ← %fp – (IMM8 × 4) If (o ld-CWP = = LO _LIMIT) then TRAP #1 Assembl er Syn tax: SAVE % sp,-IMM8 Example: SA VE %sp,- 23 ; sta rt subro utin e with n ew regs ; first opera nd c an only be % sp Descripti on: Moves C[...]

Altera Corporat ion 83 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set SEXT16 Sign Extend 16-b it Valu e Operati on: RA ←σ ( h0 RA ) Assembl er Syn tax: SEXT16 %rA Example: SE XT16 %g3 ; convert s igne d short to s igne d long Descripti on: Replace bits 16..31 of RA w ith bit 15 of RA. Condi tion Codes: F lags: U naffect ed Instruct[...]

84 Altera Corporat ion 32- Bi t Ins tr uct i on Se t SEXT8 Sign Exten d 8- bit Value Operati on: RA ←σ ( b0 RA ) Assembl er Syn tax: SEXT8 %rA Example: SE XT8 %o3 ; convert signed byt e to signed long Descripti on: Re pl ace bi t s 8. .3 1 of RA wit h bi t 7 of RA. Condi tion Codes: F lags: U naffect ed Instructi on Format: Rw Instructi on Field[...]

Altera Corporat ion 85 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set SKP0 Skip If Register Bit Is 0 Operati on: if (RA [IMM5] = = 0) then begi n if (Mem 16[PC + 2 ] is PF X) the n PC ← PC + 6 else PC ← PC + 4 en d Assembl er Syn tax: SKP0 %r A,IMM5 Example: AD DI %g0, 1 ; incl ude if b it 7 was set Descripti on: Ski p ne xt ins t[...]

86 Altera Corporat ion 32- Bi t Ins tr uct i on Se t SKP1 Skip If Register Bit Is 1 Operati on: if (RA [IMM5] = = 1) then begi n if (Mem 16[PC + 2 ] is PF X) the n PC ← PC + 6 else PC ← PC + 4 en d Assembl er Syn tax: SKP1 %r A,IMM5 Example: SK P1 %o3,21 ; skip if 21st bit of %o3 is set ADDI % g0, 1 ; increment if 21s t bit cl ear Descripti on:[...]

Altera Corporat ion 87 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set SKPRnz Skip If R egi ster N ot Equa l T o 0 Operati on: if (RA ! = 0) then begi n if (Mem 16[PC + 2 ] is PF X) the n PC ← PC + 6 else PC ← PC + 4 en d Assembl er Syn tax: SKPRnz %rA Example: SK PRnz %g3 BSR SendIt ; only call if %g3 is zero NOP ; (del ay s lot) [...]

88 Altera Corporat ion 32- Bi t Ins tr uct i on Se t SKPRz Skip If Reg ister Equa ls 0 Operati on: i f ( R A==0 ) then begi n if (Mem 16[PC + 2 ] is PF X) the n PC ← PC + 6 else PC ← PC + 4 en d Assembl er Syn tax: SKPRz % rA Example: SK PRz %o3 BSR SendIt ; only call if %o3 is not 0 NOP ; (del ay s lot) exe cuted in either case Descripti on: S[...]

Altera Corporat ion 89 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set SKPS Skip On Condition Code Operati on: if (condit ion IM M4 is true ) then begi n if (Mem 16[PC + 2 ] is PF X) the n PC ← PC + 6 else PC ← PC + 4 en d Assembl er Syn tax: SKPS c c_IMM4 Example: SK PS cc_ne BSR Se ndIt ; o nly call if Z fl ag c lear NOP ; (delay[...]

90 Altera Corporat ion 32- Bi t Ins tr uct i on Se t ST Stor e 32-b it Dat a T o Memo r y Operati on: Not precede d by PFX: Me m3 2[a li gn3 2( RB) ] ← RA Preced ed by PFX: Me m3 2[a li gn3 2( RB + ( σ (K ) × 4))] ← RA Assembl er Syn tax: ST [%rB],%r A Example: Not prece ded by PFX: ST [%g0],% i3 ; %g0 is pointer, %i3 stored Prec eded by PFX:[...]

Altera Corporat ion 91 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set ST16d Stor e 16-B it Data T o Mem or y (C omp uted Half -Word Po inter Addre ss) Operati on: Not precede d by PFX : hn Mem32[a lign3 2(RA)] ← hn R0 where n = RA[1] Prec eded by PFX: hn Mem32[a lign3 2(RA + ( σ (K) × 4))] ← hn R0 wh ere n = R A[1] Assembl er Sy[...]

92 Altera Corporat ion 32- Bi t Ins tr uct i on Se t ST16s Stor e 16-B it Da ta T o Mem or y (S tatic Half -Word-Off set A ddress) Operati on: Not precede d by PFX: hn Mem32[a lign3 2(RA)] ← hn R0 where n = IMM1 Prec eded by PFX: hn Mem32[a lign3 2(RA + ( σ (K) × 4))] ← hn R0 where n = IMM1 Assembl er Syn tax: ST16s [%rA ],%r0,IM M1 Example: [...]

Altera Corporat ion 93 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set ST8d St ore 8- Bit Da ta T o Memo r y (C omp uted By te- Point er Addr ess) Operati on: Not p receded by PFX: bn M em32[a lign32 (RA)] ← bn R0 where n = R A[1..0 ] Preceded by PFX : bn M em32[a lign32 (RA + σ (K) × 4))] ← bn R0 where n = RA[1 ..0] Assembl er S[...]

94 Altera Corporat ion 32- Bi t Ins tr uct i on Se t ST8s Store 8-bit Data T o Memory (Static Byte-Offset Address) Operati on: Not precede d by PFX: bn Mem32[a lign3 2(RA)] ← bn R0 where n = IMM2 Prec eded by PFX: bn Mem32[a lign3 2(RA + ( σ (K) × 4))] ← bn R0 where n = IM M2 Assembl er Syn tax: ST8s [ %rA],%r0 ,IMM 2 Example: Not prece ded b[...]

Altera Corporat ion 95 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set STP Sto re 32- bit D ata T o M em ory (Poin ter Addre ssing Mod e) Operati on: Not precede d by PFX: Me m3 2[a li gn3 2( RP + ( IMM 5 × 4))] ← RA Prec eded by PFX: Me m3 2[a li gn3 2( RP + ( σ (K : IMM5) × 4))] ← RA Assembl er Syn tax: STP [%r P,IMM5] ,%rA Ex[...]

96 Altera Corporat ion 32- Bi t Ins tr uct i on Se t STS Stor e 32-b it Data T o Memo ry ( Stack A ddr essing M ode) Operati on: Mem32[a lign3 2(%sp + (IM M8 × 4))] ← RA Assembl er Syn tax: STS [%sp ,IMM8] ,%rA Example: ST S [%sp,1 7],% i5 ; sto re %i5 a t st ack + 68 ; first r egister can only be %sp Descripti on: Stores the 32- bit value in RA[...]

Altera Corporat ion 97 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set STS16s Stor e 16-bi t Data T o M emo ry (Stack- Addre ssing Mod e) Operati on: hn Mem32[a lign3 2(%sp + IMM9 × 2)] ← hn R0 wh ere n = IMM9[0 ] Assembl er Syn tax: STS16s [%s p,IMM9], %r0 Example: ST S16s [%s p,7] ,%r0 ; c an only be %sp and % r0 Descripti on: Sto[...]

98 Altera Corporat ion 32- Bi t Ins tr uct i on Se t STS8s Stor e 8-bi t Dat a T o Me mor y (Stac k-Addr essin g Mode ) Operati on: bn Mem32[a lign3 2(%sp + IMM1 0)] ← bn R0 wher e n = IMM10[1. .0] Assembl er Syn tax: STS8s [%sp ,IMM10], %r0 Example: ST S8s [%sp ,13] ,%r0 ; c an only be %sp and % r0 Descripti on: Stores one of the four by tes of [...]

Altera Corporat ion 99 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set SUB Subt ract Operati on: RA ← RA − RB Assembl er Syn tax: SUB %r A,%rB Example: SU B %i3,%g0 ; SUB %g0 from %i3 Descripti on: Subtrac ts the conten ts of RB from RA, store s result in RA. Condi tion Codes: F lags: N: Re sult bit 31 V: Signe d-arithme tic overfl[...]

100 Al tera Corp oration 32- Bi t Ins tr uct i on Se t SUBI Subtract Immediate Operati on: RA ← RA − (0x00 .00 : K : IMM5) Assembl er Syn tax: subi % rB,IMM5 Example: Not prece ded by PFX: SUBI % L5,6 ; s ubtr act 6 fr om %L5 Prec eded by PFX: PFX %h i(1000) SUBI % o3,%lo(1 000) ; s ubtract 1000 from %o 3 Desc ription : Not preceded by PFX: Sub[...]

Altera Corporat ion 101 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set SW AP Sw ap Regist er Half- Words Operati on: RA ← h0 RA : h1 RA Assembl er Sy ntax: SW AP %r A Example: SW AP %g3 ; Exchange tw o ha lf-words in %g3 Descripti on: Swaps (exc hanges positions ) of the two 16-bit half-word va lues in RA. Writes resu lt back into R[...]

102 Al tera Corp oration 32- Bi t Ins tr uct i on Se t TRAP Unconditional T rap Operati on: IST A TUS ← ST A TUS IE ← 0 CWP ← CWP − 1 IPRI ← I MM6 %o7 ← ((PC + 2) >> 1) PC ← Mem 32 [V ECBA SE + ( IM M6 × 4)] << 1 Assembl er Syn tax: TRAP I MM6 Example: TR AP 0 ; reset the boa rd Descripti on: CWP is dec remented by one, o[...]

Altera Corporat ion 103 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set TRET Tr a p R e t u r n Operati on: PC ← (RA << 1) ST A TUS ← IST A T US Assembl er Syn tax: TRET % ra Example: TR ET %o7 ; return from TRA P Descripti on: Execution is trans ferred to the addres s give n by (RA << 1). The v alue w ritten in %o7 by [...]

104 Al tera Corp oration 32- Bi t Ins tr uct i on Se t WRCTL Wr ite Cont rol Reg ister Operati on: CTLk ← RA Assembl er Syn tax: WRCTL %rA Example: Not prece ded by PFX: WRCTL %g7 ; writes %g7 to STAT US reg NOP ; requ ired Prec eded by PFX: PFX 1 WRCTL %g7 ; writes %g7 to ISTA TUS reg Desc ription : Not preceded by PFX: Loads the STATU S registe[...]

Altera Corporat ion 105 32323 232 32- Bit Instru ction Se t 2 32-Bit Instruction Set XO R Bitw ise L ogical Exclu sive OR Operati on: Not precede d by PFX: RA ← RA ⊕ RB Prec eded by PFX: RA ← RA ⊕ (0x00 .00 : K : IMM5) Assembl er Syn tax: Not p recede d by PFX: XOR %rA,% rB Prec eded by PFX: PFX %h i(const) XOR %r A,%lo(co nst) Example: Not[...]

Notes: 106 Altera C orporat ion[...]

Alt era Corporat ion 107 Inde x 3 Num eri cs 5/1 6-bit Imm edi ate V alue 10 A About T his Manu al iii ABS ins truct ion 34 Absolute Value 34 Absolute -Jump I nstruction s 15 Add Immediate 36 ADD ins truct ion 35 Add Without Ca rry 35 ADDI i ns tru ct ion 36 Addr essing Mode s 10 AND ins truct ion 37 ANDN in str uc ti on 38 Arithme tic Negation 72 [...]

Inde x 108 Alt era Co rporati on F FILL16 ins truct ion 51 FILL8 instr uction 52 Full Wid th Reg ister- Indire ct with Offse t 13 G General-Purp ose Registers 2 GNU Compiler /Assembler Pseudo -Instru ctions 3 1 H Half-Word Extract (Dynamic) 47 Half-Word Extract (Static) 48 Half-Word Fill 5 1 I IF0 ins truction 53 IF1 ins truction 54 IFRnz in struct[...]

Index Altera Corporat ion 109 Inde x 3 Rota te Righ t Throug h Car ry 81 RRC ins truction 8 1 S Save Caller ’ s Reg ister Windo w 82 SAVE i nstructio n 8 SET_IE (%ctl9) 7 SEXT8 in struction 84 Sign Ex tend 16-b it Value 8 3 Sign E xte nd 8-bi t Va lue 84 Simple a nd Complex Exception Handlers 21 Simple E xceptio n Handle rs 21 Skip If Regi ster B[...]

11 0 Altera Corp oration Notes:[...]