Intel Core 2 Duo T5850 manual

Document Number: 252046 -026 Intel ® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes December 2009 Notice: The Intel ® 64 and IA -32 architectures may contain design defects or errors known as err ata that may cause the product to deviate from publishe d specifications. Current characterized err ata are documented i[...]

2I n t e l ® 64 and IA-32 Architectures Software De veloper’s Manual Docu mentation Changes Legal Lines and Discla ime rs INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL ® PRODUCTS. NO LIC ENSE, EXPRESS O R IMPLIED, BY ESTOPPEL OR O THERWISE, TO ANY INTELLECTUAL PROPER TY RIGHTS IS GRANTED BY THIS DOCUMENT . EXCEPT AS PROVIDE[...]

Intel ® 64 and IA-32 Architectures Software De veloper’s Manu al Docume nt ation Cha nges 3 Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Summary Tables of Changes . . .[...]

Revision History 4I n t e l ® 64 and IA-32 Architectures Software De veloper’s Manual Docu mentation Changes Revision History Revision Description Date -001 • Initial release Novembe r 2002 -002 • Added 1-10 Documentation Ch anges. • Removed ol d Documentation Changes items that already ha ve been incorporated in the publishe d Software De[...]

Revision History Intel ® 64 and IA-32 Architectures Software De veloper’s Manu al Docume nt ation Cha nges 5 § -024 • Removed Documentatio n Changes 1 -21 • Added Documentation Changes 1-16 June 2009 -025 • Removed Documentatio n Changes 1 -16 • Added Documentation Changes 1-18 September 2009 -026 • Removed Documentatio n Changes 1 -1[...]

Revision History 6I n t e l ® 64 and IA-32 Architectures Software De veloper’s Manual Docu mentation Changes[...]

Intel ® 64 and IA-32 Architectures Software De veloper’s Manu al Docume nt ation Cha nges 7 Preface Preface This document is an update to th e specifications contained in the Affected Documents table below . This document is a compilation of device and documentation err ata, specification clarifications and changes. It is intended for hardware s[...]

Intel ® 64 and IA-32 Architectures Software De veloper’s Manu al Docume nt ation Cha nges 8 Summary Tables of Changes Summary Tables of Changes The following table indicates documentat ion changes which apply to the Intel ® 64 and IA -32 architectures. This table uses the following n otations: Codes Used in Summary Tables Change bar to left of [...]

Intel ® 64 and IA-32 Architectures Software De veloper’s Manu al Docume nt ation Cha nges 9 Documentation Changes Documentation Changes 1. Updates to Chapter 3, Volume 2A Change bars show changes to Chapter 3 of the Int el ® 64 and IA-32 Architectures Soft- ware Developer’s Manual, Volume 2A: Instruction Set Reference, A -M. -----------------[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 10 Documentation Changes 3.1.1.4 64-bit Mode Column in the Ins truction Summary T able The “64-bit Mode” column indicates whether the opcode sequence is supported in 64-bit mode. The column uses the following n otation: • Valid — Supported. • Invali[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 11 Documentation Changes AAA—ASCII Adjust A fter Addition Instru ction Oper and Enc oding ... 64-Bit Mode Exc eptions #UD If in 64-bit mode. ... AAD—ASCII Adjust AX Be f ore Division Instru ction Oper and Enc oding ... AAM—ASCII Adjust AX A fter Multipl[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 12 Documentation Changes AAS—ASCII Adjust AL A fter Subtr action Instru ction Oper and Enc oding ... ADC—Add with Carry Opcode Instruction Op/ En 64-bit Mode Compat/ Leg Mode Description 3F AAS A Invalid Valid ASCII adjust AL after subtractio n. Op/En Ope[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 13 Documentation Changes Instru ction Oper and Enc oding ... ADD—Add Opcode Instruction Op/ En 64-bit Mode Compat/ Leg Mode Description REX.W + 11 / r ADC r/m64, r64 AV a l i d N . E . A d d w i t h C F r64 to r/m64. 12 / r ADC r8, r/m8 AV a l i d V a l i d[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 14 Documentation Changes Instru ction Oper and Enc oding ... ADDPD—Add Pack ed Double-Precision Floating-P oint V alues Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-bit Mode Compat/ Leg Mode Description REX.W + 83 /0 ib ADD r/m64, imm8 B[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 15 Documentation Changes ADDPS—Add Pack ed Single-Precision Floating-P oint V alues Instru ction Oper and Enc oding ... ADDSD—Add Scalar Double-Precision Floating-Poin t V alues Instru ction Oper and Enc oding ... ADDSS—Add Scalar Single-Precision Float[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 16 Documentation Changes ADDSUBPD—Pack ed Double-FP Add/Subtra ct Instru ction Oper and Enc oding ... ADDSUBPS—Pack ed Single -FP Add/Subtr act Instru ction Oper and Enc oding ... AND—Logical AND Opcode Instruction Op/ En 64-bit Mode Compat/ Leg Mode De[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 17 Documentation Changes Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-bit Mode Compat/ Leg Mode Description 83 /4 ib AND r/m16, imm8 BV a l i d V a l i d r/m16 AND imm8 (sign- extended). 83 /4 ib AND r/m32, imm8 BV a l i d V a l i d r/m32 [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 18 Documentation Changes ANDPD—Bitwise Logical AND o f P ack ed Double-Pr ecision Floating-Poin t Va l u e s Instru ction Oper and Enc oding ... ANDPS—Bitwise Logical AND o f P ack ed Single-Pr ecision Floating-Point Va l u e s Instru ction Oper and Enc o[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 19 Documentation Changes ANDNPS—Bitwise Logical AND NO T o f Pa ck ed Single-Precision Floating- Poi nt Valu e s Instru ction Oper and Enc oding ... ARPL —Adjust RPL Field o f Segment Select or Instru ction Oper and Enc oding Descripti on Compares the RPL[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 20 Documentation Changes See “Checking Caller Access Privile ges” in Ch apter 3, “Protected-M ode Mem ory Manage- ment, ” of the Intel ® 64 and IA-32 Architectures Softwa re Developer’s Manual, Volume 3A , for more information about the use of this[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 21 Documentation Changes BLEND VPD — V ariable Blend P ack ed Double Precision Floating-Poin t Va l u e s Instru ction Oper and Enc oding ... BLEND VPS — V ariable Blend P ack ed Single Pr ecision Floating-Poin t Va l u e s Instru ction Oper and Enc oding[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 22 Documentation Changes BOUND—Check Array Inde x Agains t Bounds Instru ction Oper and Enc oding ... BSF—Bit Scan F orw ard Instru ction Oper and Enc oding ... BSR—Bit Scan Re v erse Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-bit [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 23 Documentation Changes BSW AP—Byte S w ap Instru ction Oper and Enc oding ... B T—Bit T est Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-bit Mode Compat/ Leg Mode Description 0F C8+ rd BSWAP r32 A Valid* Valid Reverses the by te orde[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 24 Documentation Changes B T C—Bit T est and Complement Instru ction Oper and Enc oding ... BT R— B i t T est a n d Res et Opcode Instruction Op/ En 64-bit Mode Compat/ Leg Mode Description 0F BB BTC r/m16, r16 A Valid Valid Store selected bit in CF flag [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 25 Documentation Changes Instru ction Oper and Enc oding ... BT S— B i t Test a n d S et Instru ction Oper and Enc oding ... CAL L —Call Pr ocedur e Op/En Oper and 1 Oper and 2 Oper and 3 Operan d 4 A ModRM:r/m (r, w) ModRM:reg (r) NA NA B ModRM:r/m (r, w[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 26 Documentation Changes Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-bit Mode Compat/ Leg Mode Description FF /2 CALL r/m64 B Valid N.E. Call near , absolute indirect, address gi ven in r/m 64. 9A cd CALL pt r16:16 A Invalid Valid Call fa[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 27 Documentation Changes BW/CWDE/CDQE—Con vert Byte t o W ord /Con vert W or d to Doublew ord/ Con vert Doublew or d to Quadw ord Instru ction Oper and Enc oding ... CLC—Clear Carry Flag Instru ction Oper and Enc oding ... CLD—Clear Direction Flag Instr[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 28 Documentation Changes CLFL USH—Flush Cache Line Instru ction Oper and Enc oding Descripti on Inv alidates the cache line that contains the linear address specifie d with the source operand from all levels of the processor cache hierarchy (data and instru[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 29 Documentation Changes CLI — Clear Interrup t Flag Instru ction Oper and Enc oding ... CL TS—Clear T ask-Switched Flag in CR0 Instru ction Oper and Enc oding ... CMC—Complement Carry Flag Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 6[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 30 Documentation Changes CMO V cc —Conditional Mov e Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg M ode Descriptio n 0F 47 /r CMOVA r16, r/m16 A Valid Valid Move if above (CF=0 an d ZF=0). 0F 47 /r CMOVA r32, r/m32 A Valid Valid Move if above (CF=0 an [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 31 Documentation Changes Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg M ode Descriptio n 0F 4C /r CMOVL r16, r/m16 A Valid Valid M ove if less (SF ≠ OF). 0F 4C /r CMOVL r32, r/m32 A Valid Valid M ove if less (SF ≠ OF). REX.W + 0F 4C /r CMOVL r64, r/m[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 32 Documentation Changes Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg M ode Descriptio n 0F 4E /r CMOVNG r32, r/m32 A Valid Valid Move if not greater ( ZF=1 or SF ≠ OF). REX.W + 0F 4E /r CMOVNG r64, r/m64 A Valid N.E. M ove if not great er (ZF=1 or SF [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 33 Documentation Changes Instru ction Oper and Enc oding ... CMP—Compare T wo Oper ands Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg M ode Descriptio n 0F 4A /r CMOVP r16, r/m16 A Valid Valid M ove if parity (PF=1). 0F 4A /r CMOVP r32, r/m32 A Valid Va[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 34 Documentation Changes Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 81 /7 id CMP r/m32, imm32 CV a l i d V a l i d C o m p a r e imm32 with r/m32. REX.W + 81 /7 id CMP r/m64, imm32 C Valid N.E. Comp[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 35 Documentation Changes CMPPD—Compare P ack ed Double-Precision Floating-Poin t V alues Instru ction Oper and Enc oding ... CMPPS—Compare P ack ed Single-Precision Floating-Poin t V alues Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-B[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 36 Documentation Changes CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compar e S t ring Operands Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description A6 CMPS m8, m8 A Valid Valid For lega cy mode, compare byte at address DS:(E)SI with byte at address ES:(E)D[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 37 Documentation Changes Instru ction Oper and Enc oding ... CMPSD—Compare Scalar Double-Pr e cision Floating-Poin t V alues Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description A7 CMPSD A Valid Valid For l[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 38 Documentation Changes CMPSS—Compare Scalar Single-Pr ecision Floating-Poin t V alues Instru ction Oper and Enc oding Descripti on Compares the low single-precision floating-point values in the source operand (second operand) and the destination oper and [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 39 Documentation Changes CMP X CHG—Compar e and Ex change Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 0F B0/ r CMPXCHG r/m8, r8 AV a l i d V a l i d * C o m p a r e A L w i t h r/m8 . If equal, ZF [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 40 Documentation Changes CMP X CHG8B/CMPX CHG16B—Compare and Ex change Bytes Instru ction Oper and Enc oding ... C OMISD—Compare Scalar Or der ed Double-Pr ecision Floating-Poin t V alues and Set EFLA GS Instru ction Oper and Enc oding ... Opcode Instruct[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 41 Documentation Changes COMISS—Compare Scalar Or der ed Single-Pr ecision Floating-Poin t V alues and Set EFLA GS Instru ction Oper and Enc oding ... CPUID—CPU Identification Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compa[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 42 Documentation Changes T able 3-20. Information Re turned by CPUID Ins truction (Conti nued) ... T able 3-24. More on F eatur e Inf orm ation R eturned in the ED X R egister ... Initial EAX Value Information Provid ed about the Processor Basic CPUID Inf orm[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 43 Documentation Changes CRC32 — Ac cumulate CR C32 V alue Instru ction Oper and Enc oding ... CVTDQ2PD—Con vert P a ck ed Dw or d Integers t o P ack ed Double-Precision FP V alues Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 44 Documentation Changes CVTDQ2PS—Conv ert Pack ed Dword In te gers t o P ack ed Single-Pr ecision FP V alues Instru ction Oper and Enc oding ... CVTPD2DQ—Con vert P ack ed Double-Preci sion FP V alues to P a ck ed Dword Integers Instru ction Oper and Enc[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 45 Documentation Changes Instru ction Oper and Enc oding ... CVTPD2PS—Conv ert P a ck ed Double-Preci sion FP V alues t o P ack ed Single- Precision FP V alues Instru ction Oper and Enc oding ... CVTPI2PD—Con vert P ack ed Dword Inte gers t o Pa ck ed Dou[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 46 Documentation Changes CVTPI2PS—Con vert P ack ed Dwor d Integers t o P ack ed Single-Pr ecision FP Va l u e s Instru ction Oper and Enc oding ... CVTPS2DQ—Conv ert P ack ed Single-Precision FP V alues to P ack ed Dw ord Integers Instru ction Oper and E[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 47 Documentation Changes Instru ction Oper and Enc oding ... CVTPS2PI—Con vert P ack ed Single-Precision FP V alues to P ack ed Dw or d Integers Instru ction Oper and Enc oding ... CVTSD2SI—Con vert Scalar Double-Pr ecision FP V alue to Integer Instru cti[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 48 Documentation Changes CVTSD2SS—Con ve rt Scalar Double-Precision FP V alue to Scalar Sin gle- Precision FP V alue Instru ction Oper and Enc oding ... CVTSI2SD—Con vert Dw or d Integer t o Scalar Double-Pr ecision FP V alue Instru ction Oper and Enc odi[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 49 Documentation Changes CVTSI2SS—Conv ert Dw ord In teger to Scalar Single-Pr ecision FP V alue Instru ction Oper and Enc oding ... CVTSS2SD—Con vert Scalar Single-Pr ecision FP V alue to Scalar Double- Precision FP V alue Instru ction Oper and Enc oding[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 50 Documentation Changes Instru ction Oper and Enc oding ... CVTTPD2DQ—Con v ert with T runcatio n Pack ed Double-Precision FP V alues to Pack ed Dwor d Integers Instru ction Oper and Enc oding ... CVTTPD2PI—Conv ert with Truncatio n Pa ck ed Double-Pr ec[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 51 Documentation Changes CVTTPS2DQ—Con vert with T r uncation P a ck ed Single-Pr ecision FP V alues to P ack ed Dw ord In tegers Instru ction Oper and Enc oding ... CVTTPS2PI—Con v ert with T runcation P ack ed Single-Precision FP V alues to P ack ed Dw [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 52 Documentation Changes CVTTSD2SI—Conv ert with Truncation Scal ar Double-Pr ecision FP V alue to Signed Integer Instru ction Oper and Enc oding ... CVTTSS2SI—Con v ert with T runcation Scalar Single-Precisi on FP V alue to Dwor d Integer Instru ction Op[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 53 Documentation Changes CW D /C D Q /CQ O — Co nve r t Wo rd t o Do u b le wo rd / Co nve rt D o ub l e wo rd t o Quadword Instru ction Oper and Enc oding ... DAA—Decimal Adjust A L after Addition Instru ction Oper and Enc oding ... DAS—Decimal Adjust [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 54 Documentation Changes DEC—Decremen t b y 1 Instru ction Oper and Enc oding ... DIV—Unsigned Divide Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description FE /1 DEC r/m8 AV a l i d V a l i d D e c r e m e n t r/m8 by 1. REX + FE /1 DEC r/m8[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 55 Documentation Changes Instru ction Oper and Enc oding ... DIVPD—Divide Pack ed Double-Precision Floating-Poin t V alues Instru ction Oper and Enc oding ... DIVPS—Divide Pack ed Single-Pre cision Floating-Poin t V alues Instru ction Oper and Enc oding .[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 56 Documentation Changes Instru ction Oper and Enc oding ... DIVSS—Divide Scalar Single-Pre cision Floating-Poin t V alues Instru ction Oper and Enc oding ... DPPD — Do t Pr oduct of Pack ed Doub le Precision Floating-P oint V alues Instru ction Oper and [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 57 Documentation Changes DPPS — Dot Pr oduct of P ack ed Single Pr ecision Floating-Poin t V alues Instru ction Oper and Enc oding ... EMMS—Empty MMX T echnology State Instru ction Oper and Enc oding ... EN T ER—Mak e S tack Frame f or Pr ocedur e P ar [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 58 Documentation Changes EXTRACTPS — Ex tr act P ack ed Single Pr ecision Floating-Po int V alue Instru ction Oper and Enc oding ... FSA V E/FNS A V E—S tor e x87 FPU S tate ... IA-32 Architectur e Compatibility For Intel math coprocessors and FPUs prior [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 59 Documentation Changes FXRST OR—Restor e x87 FPU, MMX , XMM, and MX CSR S tate Instru ction Oper and Enc oding ... FXSA V E—Sav e x87 FPU, MMX T echnology , and SSE S tate Instru ction Oper and Enc oding ... HADDPD—Pack ed Double-FP Horizon tal Add In[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 60 Documentation Changes HADDPS—Pack ed Single-FP Horizon tal Add Instru ction Oper and Enc oding ... HL T—Halt Instru ction Oper and Enc oding ... HSUBPD—Pack ed Double-FP Horizon tal Subtr a ct Instru ction Oper and Enc oding ... HSUBPS—Pack ed Sing[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 61 Documentation Changes Instru ction Oper and Enc oding ... IDIV—Signed Divide Instru ction Oper and Enc oding ... Op/En Oper and 1 Oper and 2 Oper and 3 Operan d 4 A ModRM:r eg (r , w) ModRM:r/m (r) NA NA Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 62 Documentation Changes IMUL —Signed Multiply Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description F6 /5 IMUL r/m8* AV a l i d V a l i d A X ← AL ∗ r/m byte. F7 /5 IMUL r/m16 AV a l i d V a l i d D X :[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 63 Documentation Changes IN—Input from Port Instru ction Oper and Enc oding ... INC—Incremen t b y 1 Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description E4 ib IN AL, i mm8 A Valid Valid Input byte from imm8 I/O port address into AL. E5 ib [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 64 Documentation Changes Instru ction Oper and Enc oding ... INS/INSB/INSW/INSD—Input fr om Port to S tring Instru ction Oper and Enc oding ... Op/En Oper and 1 Oper and 2 Oper and 3 Operan d 4 A ModRM:r/m (r, w) NA NA NA B reg (r, w) NA NA NA Opcode Instru[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 65 Documentation Changes INSER TPS — Insert P ack ed Single Pr ecision Floating-Poin t V alue Instru ction Oper and Enc oding ... IN T n/IN T O/IN T 3—Call t o Interru pt Pr ocedure Instru ction Oper and Enc oding ... Operation The following operational d[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 66 Documentation Changes IF (VM = 1 and IOPL < 3 AND INT n ) THEN #GP(0); ELSE (* Protected mode, IA-32e mode, or virtua l-8086 mode inte rrupt *) IF (IA32_EFER.LMA = 0) THEN (* Protected mode , or virtual-8086 mode interrupt *) GOTO PROTECTED-MODE; ELSE ([...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 67 Documentation Changes FI; IF software interrupt (* Ge nerated by INT n , INT 3, but not INTO *) THEN IF gate descriptor DPL < CPL THEN #GP((vector_number « 3) + 2 ); (* PE = 1, DPL < CPL, software interrupt *) FI; ELSE (* Generated by INTO *) #UD; F[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 68 Documentation Changes INVD—In validate In ternal Caches Instru ction Oper and Enc oding ... INVLPG—In validate TLB En try Instru ction Oper and Enc oding ... IR ET /IRETD—In terrup t R e t urn Instru ction Oper and Enc oding ... Opcode Instruction Op[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 69 Documentation Changes J cc —Jump if Condition Is Met Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 77 cb JA rel8 A Valid Valid Jump short if above (CF=0 and ZF=0 ). 73 cb JAE rel8 A Valid Valid Jump shor t if abov e or equ al (CF=0)[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 70 Documentation Changes 71 cb JNO rel8 A Valid Vali d Jump sh ort if not overf low (OF=0). 7B cb JNP rel8 A Valid Valid Jump short if not parity (PF=0). 79 cb JNS rel8 A Valid Valid Jump shor t if not sign (SF=0). 75 cb JNZ rel8 A Valid V alid Jum p short if[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 71 Documentation Changes 0F 84 cd JE rel32 A Valid Valid Jump near if equal (ZF=1). 0F 84 cw JZ rel16 A N.S. Valid Jump near if 0 (ZF=1). No t supported in 64-bit m ode. 0F 84 cd JZ rel32 A Valid Valid Jump near if 0 (ZF=1). 0F 8F cw JG rel16 A N.S. Valid Jum[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 72 Documentation Changes 0F 87 cd JNBE rel32 A Valid Valid Jump near if not below or equal (CF=0 and ZF=0). 0F 83 cw JNC rel16 A N.S. Valid Jump near if no t carry (CF=0). Not supported in 64- bit mode. 0F 83 cd JNC rel32 A Valid Valid Jump near if not carry [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 73 Documentation Changes Instru ction Oper and Enc oding ... 0F 89 cw JNS rel16 A N.S. Valid Jump near if not sign (SF= 0). Not supported in 64-bit mode. 0F 89 cd JNS rel32 A Valid Valid Jump near if not sign (SF=0). 0F 85 cw JNZ rel16 A N.S. Valid Jump near [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 74 Documentation Changes JMP—Jump Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description EB cb JMP rel8 A Valid Vali d Jump short, RIP = RIP + 8- bit displacement sign extended to 64-bits E9 cw JMP rel16 A N.[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 75 Documentation Changes LAHF—Load S tatus Flags into AH R egister Instru ction Oper and Enc oding ... LAR—Load Ac cess Righ ts Byte Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Desc ription 9F LAHF A Invali [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 76 Documentation Changes LDDQU—Load Unaligned In teger 128 Bits Instru ction Oper and Enc oding ... LDMX CSR—L oad MX CSR R egister Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description F2 0F F0 / r LDDQU [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 77 Documentation Changes LDS/LE S/LFS/L GS/LSS—L oad F ar Pointer Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description C5 / r LDS r16,m16:16 AI n v a l i d V a l i d L o a d D S : r16 with far pointer from [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 78 Documentation Changes L EA—Load Eff ectiv e Address Instru ction Oper and Enc oding ... L EA VE—High L e vel Pr oc edure Exit Instru ction Oper and Enc oding ... LFENCE—Load F ence Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 79 Documentation Changes L GD T /L IDT—L oad Global/Interru p t Descrip tor T able R egis ter Instru ction Oper and Enc oding ... L LDT—L oad L ocal Descript or T able Register Instru ction Oper and Enc oding ... LMSW—L oad Machine S tatus W ord Instru [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 80 Documentation Changes LOCK—Assert L OCK# Signal Pre fix Instru ction Oper and Enc oding Descripti on Causes the processor’s L OCK# signal to be asserted during execution of the accompa- nying instruction (turns the instruction into an atomic instructio[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 81 Documentation Changes L ODS/L ODSB/L ODSW/LODSD/L ODSQ—Load S tring Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description AC LODS m8 A Valid Valid For legacy mode, Load byte at address DS:(E)SI into AL. F[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 82 Documentation Changes LO O P / LO O P cc —Loop Accor ding to ECX Coun ter Instru ction Oper and Enc oding ... LSL—Lo ad Se gm ent L i mit Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description E2 cb LOOP[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 83 Documentation Changes LT R — L o a d T a s k R e g i s t e r Instru ction Oper and Enc oding ... MASKMO VDQU—S tor e Selected Bytes o f Double Quadword Instru ction Oper and Enc oding Descripti on Stores selected bytes from the source oper and (first o[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 84 Documentation Changes MASKMO V Q—S tor e Selected Bytes o f Quadwor d Instru ction Oper and Enc oding ... MAXPD—R eturn Maximum P ack ed Double-Precision Floating-Poin t V alues Instru ction Oper and Enc oding ... MAXPS—R eturn Maximum P ack ed Singl[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 85 Documentation Changes MAXSD—Re turn Maximum Scalar Double -Pr ecision Floating-Poin t V alue Instru ction Oper and Enc oding ... MAXSS—R eturn Maximum Scalar Single -Precision Floating-Poin t V alue Instru ction Oper and Enc oding ... MFENCE—Memory F[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 86 Documentation Changes any serializing instructions (such as the CP UID instruction). MFENCE does not serialize the instruction stream. W eakly ordered me mory types can be used to achieve higher processor performance through such techniques as out-of -orde[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 87 Documentation Changes MINPS—R eturn Minimum P ack ed Single-Precision Floating-Poin t V alues Instru ction Oper and Enc oding ... MINSD—Re turn Minimum Scalar Double -Pr ecision Floating-Poin t V alue Instru ction Oper and Enc oding ... MINSS—Re turn[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 88 Documentation Changes MONIT OR—Set Up Monit or Addr ess Instru ction Oper and Enc oding ... MOV—Mo v e Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 0F 01 C8 MONITOR A Valid Valid Sets up a linear addres s range to be monitored by[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 89 Documentation Changes Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description A1 MOV AX, moffs16 * C Valid Valid Move word at ( seg:offset ) to AX. A1 MOV EAX, moffs32 * CV a l i d V a l i d M o v e doubleword at ( seg:offset ) to EAX. REX.W + [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 90 Documentation Changes Instru ction Oper and Enc oding ... MOV—Mo v e to/fr om Con tr ol R egisters Instru ction Oper and Enc oding ... Op/En Oper and 1 Oper and 2 Oper and 3 Operan d 4 A ModRM:r/m (w) ModRM:reg (r) NA NA B ModRM:reg (w) ModRM:r/m (r) NA [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 91 Documentation Changes MOV—Mo v e to/fr om Debug R egisters Instru ction Oper and Enc oding ... MOV A PD—Mo ve Aligned P ack ed Double -Precision Floating-P oint V alues Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ L[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 92 Documentation Changes MOV A PS—Mo ve Aligned P ack ed Single-Precision Floating-Point V alues Instru ction Oper and Enc oding ... MOVBE—Mo ve Data A fter S w apping Bytes Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 93 Documentation Changes MOVD/MO VQ—Mov e Doublewor d/Mo ve Quadw ord Instru ction Oper and Enc oding ... MOVDDUP—Mo v e One Double-FP and Duplicate Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 0F[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 94 Documentation Changes MOVDQ A—Mo v e Aligned Double Quadwor d Instru ction Oper and Enc oding ... MO VDQU—Mov e Unaligned Double Quadword Instru ction Oper and Enc oding ... MOVDQ2Q—Mo ve Quadwor d fr om XMM to MMX T echnology Register Instru ction O[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 95 Documentation Changes MOVHLPS— Mo ve Pa ck ed Single-Pr ecision Floating-Po int V alues High to Low Instru ction Oper and Enc oding ... MOVHPD—Mo ve High Pack ed Double-Precision Floating-Poin t V alue Instru ction Oper and Enc oding ... Opcode Instruc[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 96 Documentation Changes MOVHPS—Mo v e High P ack ed Single-Pr ecision Floating-Poin t V alues Instru ction Oper and Enc oding ... MOVLHPS—Mo ve Pa ck ed Single-Pr ecision Floating-Poin t V alues Low t o High Instru ction Oper and Enc oding ... Opcode Ins[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 97 Documentation Changes MOVLPD—Mo v e L ow P ack ed Double-Precision Floating-Poin t V alue Instru ction Oper and Enc oding ... MOVLPS—Mo ve Lo w Pack ed Single-Precision Floating-Poin t V alues Instru ction Oper and Enc oding ... Opcode Instruction Op/ [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 98 Documentation Changes MO VMSKPD—Ex tr act P ack ed Double-Pr e cision Floating-P oin t Sign Mask Instru ction Oper and Enc oding ... MO VMSKPS—Ex tra ct Pack ed Single-Precision Floating-Poin t Sign Mask Instru ction Oper and Enc oding ... MO VN TDQ A [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 99 Documentation Changes MO VN TDQ—S tore Double Quadw ord Using Non-T emporal Hin t Instru ction Oper and Enc oding ... MO VN TI—S tore Doublew ord Usi ng Non-T empor al Hin t Instru ction Oper and Enc oding ... MOVN TPD—St ore P acked Double-Pr ecisio[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 100 Documentation Changes MOVN TPS—St ore P ack ed Single-Precisi on Floating-Point V alues Using Non-T empor al Hin t Instru ction Oper and Enc oding ... MO VN T Q—S to re o f Quadw ord Using Non-T emporal Hin t Instru ction Oper and Enc oding ... Opcode[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 101 Documentation Changes MO V Q—Mo v e Quadwor d Instru ction Oper and Enc oding ... MOV Q2DQ—Mov e Quadwor d fr om MMX T echnology to XMM R egister Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 0[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 102 Documentation Changes MO VS / M OV S B / M OVS W / M OV S D / M OVS Q — M ove D a t a fro m St r i n g to St r i n g Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description A4 MOVS m8 , m8 A Valid Valid [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 103 Documentation Changes MOV SD—Mo v e Scalar Double-Pr ecision Floating-Poin t V alue Instru ction Oper and Enc oding ... MO VSHDUP—Mo ve Pack ed Single-FP High and Duplicate Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Comp[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 104 Documentation Changes MOV SLDUP—Mo v e P ack ed Single-FP Lo w and Duplicate Instru ction Oper and Enc oding ... MOV SS—Mov e Scalar Single-Precision Floati ng-Point V alues Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Com[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 105 Documentation Changes MOV SX/MO VS XD—Mov e with Sign-Ex tension Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 0F BE / r MOVSX r16, r/m8 A Valid Valid Mov e byte to word with sign-extension. 0F B[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 106 Documentation Changes MOVUPD—Mo ve Unaligned Pack ed Double-Precision Floating-Poin t Va l u e s Instru ction Oper and Enc oding ... MO VUPS—Mov e Unaligned Pack ed Single -Pr ecision Floating-P oint V alues Instru ction Oper and Enc oding ... Opcode [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 107 Documentation Changes MOVZX —Mov e with Zer o-Ex tend Instru ction Oper and Enc oding ... MPSADBW — Compute Multiple P ack ed Sums o f Absolute Diff erenc e Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de De[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 108 Documentation Changes MUL—Unsigned Multiply Instru ction Oper and Enc oding ... MULPD—Multiply Pack ed Double-Precision Floating-P oint V alues Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description F6 [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 109 Documentation Changes MULPS—Multiply Pack ed Single-Precision Floating-P oint V alues Instru ction Oper and Enc oding ... MULSD—Multiply Scalar Double-Pr ecision Floating-Poin t V alues Instru ction Oper and Enc oding ... MULSS—Multiply Scalar Singl[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 110 Documentation Changes MWAIT—Monit or W ait Instru ction Oper and Enc oding ... 2. Updates to Chapter 4, Volume 2B Change bars show changes to Chapter 4 of the Int el ® 64 and IA-32 Architectures Soft- ware Developer’s Manual, Volume 2B: Instruction S[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 111 Documentation Changes Instru ction Oper and Enc oding ... NOP—No Oper ation Instru ction Oper and Enc oding ... NO T—One's Complement Negation Instru ction Oper and Enc oding ... Op/En Oper and 1 Oper and 2 Oper and 3 Operan d 4 A ModRM:r/m (r, w[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 112 Documentation Changes OR—Logical Inclusiv e OR Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 0C ib OR AL, i mm8 AV a l i d V a l i d A L O R imm8. 0D iw OR AX, i mm16 AV a l i d V a l i d A X O R[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 113 Documentation Changes ORPD—Bitwise L ogical OR o f Double-Pr ecision Floating-P oint V alues Instru ction Oper and Enc oding ... ORPS—Bitwise Logical OR o f Single-Precision Floating-P oint V alues Instru ction Oper and Enc oding ... OUT—Output to P[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 114 Documentation Changes Instru ction Oper and Enc oding ... IA-32 Architectur e Compatibility After executing an OUT instruction, the Pentium ® processor ensures that the EWBE# pin has been sampled active before it begins to execute the next instruction. ([...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 115 Documentation Changes Instru ction Oper and Enc oding ... IA-32 Architectur e Compatibility After executing an OUTS , OUTSB, OUTSW , or OUTSD instruction, the Pentium processor ensures that the EWBE# pin has been sampled active before it begins to execute[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 116 Documentation Changes P ACKSS WB/P ACKSSD W—P ack with Signed Satur ation Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 0F 63 /r P ACKSSWB mm1, mm2/m64 A Valid V alid Conve rts 4 pack ed signed w[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 117 Documentation Changes P ACKUSD W — P ack with Unsigned Satur ation Instru ction Oper and Enc oding ... P ACKUS WB—P ack with Unsigned Satur ation Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 6[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 118 Documentation Changes P ADDB/P ADDW/P ADDD—Add Pack ed Integers Instru ction Oper and Enc oding ... P ADDQ—Add Pack ed Quadwor d In tegers Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 0F FC / [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 119 Documentation Changes P ADDSB/P ADDS W—Add Pack ed Signed Integers with Signed Satur ation Instru ction Oper and Enc oding ... P ADDUSB/P ADDUS W—Add Pack ed Unsigned Integers with Unsigned Satur ation Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 120 Documentation Changes Instru ction Oper and Enc oding ... P ALIGNR — P ack ed Align Right Instru ction Oper and Enc oding ... P AND—Logical AND Instru ction Oper and Enc oding ... Op/En Oper and 1 Oper and 2 Oper and 3 Operan d 4 A ModRM:r eg (r , w) [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 121 Documentation Changes P ANDN—Logical AND NO T Instru ction Oper and Enc oding ... P AUSE—Spin L oop Hint Instru ction Oper and Enc oding ... P A VG B / PA VG W — Avera ge Pa c ked I nt e g e rs Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 122 Documentation Changes Instru ction Oper and Enc oding ... PBLEND VB — V ariable Blend P ack ed Bytes Instru ction Oper and Enc oding ... PBLEND W — Blend Pack ed Wor ds Instru ction Oper and Enc oding ... Op/En Oper and 1 Oper and 2 Oper and 3 Operan [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 123 Documentation Changes PCMPEQB/PCMPEQW/PCMPEQD— Compar e P ack ed Data f or Equal Instru ction Oper and Enc oding ... PCMPEQQ — Compare P ack ed Qword Data f or Equal Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 124 Documentation Changes PCMPESTRI — Pack ed Compare Explicit Length S trings, R e turn Index Instru ction Oper and Enc oding ... PCMPESTRM — Pack ed Compare Explicit L ength S trings, R e turn Mask Instru ction Oper and Enc oding ... PCMPISTRI — Pa ck[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 125 Documentation Changes PCMPISTRM — Pack ed Compare Implici t Length S trings, Re turn Mask Instru ction Oper and Enc oding ... PCMPGTB/PCMPGTW/PCMPGTD—Compare P ack ed Signed Integers f or Greater Than Instru ction Oper and Enc oding ... Opcode Instruc[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 126 Documentation Changes PCMPGT Q — Compare P ack ed Data for Gr eater Than Instru ction Oper and Enc oding ... PEXTRB/PEXTRD/PEXTR Q — Ex tract Byte/Dw or d/Qwor d Instru ction Oper and Enc oding Description Copies a data element (byte, dword, quadwo rd[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 127 Documentation Changes In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15, R8-15). PEXTRQ requires REX.W . If the destination operand is a gener al-purpose register , the default oper[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 128 Documentation Changes Instru ction Oper and Enc oding ... PHADDSW — P ack ed Horizontal Add and Satur ate Instru ction Oper and Enc oding ... PHMINPOSUW — Pack ed Horizontal W or d Minimum Instru ction Oper and Enc oding ... Op/En Oper and 1 Oper and [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 129 Documentation Changes PHSUBW/PHSUBD — Pack ed Horizon tal Sub tract Instru ction Oper and Enc oding ... PHSUBSW — P ack ed Horizon tal Sub tr act and Satur ate Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 130 Documentation Changes PINSRB/PINSRD/PINSR Q — Insert Byte/Dwor d/Qwor d Instru ction Oper and Enc oding ... PINSRW—Ins ert Wor d Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 66 0F 3A 20 /r ib [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 131 Documentation Changes PMADDUBSW — Multiply and Add P ack ed Signed and Unsigned Bytes Instru ction Oper and Enc oding ... PMADDWD—Multiply and Add P ack ed In tegers Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 132 Documentation Changes PMAXSB — Maximum of P acked Signed Byte In tegers Instru ction Oper and Enc oding ... PMAXSD — Maximum of P ack ed Signed Dword In tegers Instru ction Oper and Enc oding ... PMAXSW—Maximum o f P ack ed Signed W or d In tegers O[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 133 Documentation Changes Instru ction Oper and Enc oding ... PMAX UB—Maximum of P a ck ed Unsigned Byte In tegers Instru ction Oper and Enc oding ... PMAX UD — Maximum of Pack ed Unsigned Dwor d Integers Instru ction Oper and Enc oding ... Op/En Oper and[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 134 Documentation Changes PMAX UW — Maximum of P ack ed Wor d In tegers Instru ction Oper and Enc oding ... PMINSB — Minimum of P ack ed Signed Byte Integers Instru ction Oper and Enc oding ... PMINSD — Minimum of P ack ed Dword In tegers Instru ction O[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 135 Documentation Changes PMINSW—Minimum o f P ack ed Signed Wor d Integers Instru ction Oper and Enc oding ... PMINUB—Minimum of P ack ed Unsigned Byte Integers Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de D[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 136 Documentation Changes PMINUD — Minimum of P ack ed Dword In tegers Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 66 0F 38 3B /r PMINUD xmm1, xmm2/m128 A V alid V alid Compare pack ed unsigned dwo[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 137 Documentation Changes PMINUW — Minimum of P ack ed Wor d Integers Instru ction Oper and Enc oding ... PMOV MSKB—Mov e Byte Mask Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 66 0F 38 3A /r PMIN[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 138 Documentation Changes PMOV SX — P ack ed Mov e with Sign Ex tend Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-bit Mode Compat/ Leg Mode Description 66 0f 38 20 /r PMOVSXBW xmm1, xmm2/m64 A V alid V alid Sign extend 8 packed signed 8-[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 139 Documentation Changes PMOV ZX — Pack ed Mov e with Z er o Ex tend Instru ction Oper and Enc oding ... PMULDQ — Multiply Pa ck ed Signed Dwor d Integers Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-bit Mode Compat/ Leg Mode Descript[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 140 Documentation Changes PMULHRS W — Pack ed Multiply High with R ound and Scale Instru ction Oper and Enc oding ... PMULHUW—Multiply Pa ck ed Unsigned In tegers and S tor e High R esult Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bi[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 141 Documentation Changes PMULHW—Multiply Pa ck ed Signed In tegers and S tor e High R esult Instru ction Oper and Enc oding ... PMUL LD — Multiply Pack ed Signed Dwor d Integers and S tore L ow R esult Instru ction Oper and Enc oding ... Opcode Instructi[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 142 Documentation Changes PMUL LW—Multiply P acked Signed In tegers and S t ore L ow R esult Instru ction Oper and Enc oding ... PMUL UDQ—Multiply P ack ed Unsigned Doublew ord In tegers Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 143 Documentation Changes POP—Pop a V alue fr om the S tack Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 8F /0 POP r/ m16 A Valid V alid Pop top o f stack i nto m16 ; increment stack pointer . 8F /0 POP r/ m32 A N.E. V alid Pop top o [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 144 Documentation Changes Instru ction Oper and Enc oding ... POP A/POP AD—Pop All Gener al-Purpose R egisters Instru ction Oper and Enc oding ... POPCN T — R e turn the Count o f Number o f Bits Se t to 1 Instru ction Oper and Enc oding ... Op/En Oper an[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 145 Documentation Changes POPF/POPFD/POPFQ—Pop S tack in to EFLA GS R egister Instru ction Oper and Enc oding ... POR—Bitwise Logical OR Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 9D POPF A V al[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 146 Documentation Changes PR EFET CH h —Pre f e tch Data In to Caches Instru ction Oper and Enc oding ... PSADBW—Compute Sum o f Absolute Diff erenc es Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 0F 18 /1 PREFET CHT0 m8 AV a l i d [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 147 Documentation Changes Instru ction Oper and Enc oding ... PSHUFB — Pa ck ed Shuffle Bytes Instru ction Oper and Enc oding ... PSHUFD—Shuffle Pack ed Doublewords Instru ction Oper and Enc oding ... Op/En Oper and 1 Oper and 2 Oper and 3 Operan d 4 A Mo[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 148 Documentation Changes PSHUFHW—Shuffle Pa ck ed High W or ds Instru ction Oper and Enc oding ... PSHUFL W—Shuffle P ack ed L ow W ords Instru ction Oper and Enc oding ... PSHUFW—Shuffle Pa ck ed W or ds Instru ction Oper and Enc oding ... Opcode Inst[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 149 Documentation Changes PSIGNB/PSIGNW/PSIGND — Pack ed SIGN Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mode Desc rip t ion 0F 38 08 /r PSIGNB mm1, mm2/m64 A Vali d V alid Negate/z er o/pr eserve pack ed byte in t[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 150 Documentation Changes PSL LDQ—Shift Double Quadwor d Le ft L ogical Instru ction Oper and Enc oding ... PS LLW / P S LL D / P S LLQ — S h i ft Pa cke d D a t a Lef t L o gi c a l Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 66 0[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 151 Documentation Changes Instru ction Oper and Enc oding ... PSRAW/PSRAD—Shift Pack ed Data Righ t Arithme tic Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 66 0F 73 /6 ib PSLLQ xmm1 , imm8 B V alid V alid Shift quadwords in xmm1 left[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 152 Documentation Changes Instru ction Oper and Enc oding ... PSR LDQ—Shift Double Quadw ord Righ t Logical Instru ction Oper and Enc oding ... PS RLW/ P S RL D / P S RLQ — S h i f t Pa c ke d Da t a R i g ht L o g i c a l Op/En Oper and 1 Oper and 2 Oper[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 153 Documentation Changes Instru ction Oper and Enc oding ... PSUBB/PSUBW/PSUBD—Subtr act P ack ed Integers Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 66 0F 72 /2 ib PSRLD xmm1 , imm8 B V alid V alid Shift doubleword s in xmm1 right[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 154 Documentation Changes Instru ction Oper and Enc oding ... PSUBQ—Subtr act P ack ed Quadword In tegers Instru ction Oper and Enc oding ... PSUBSB/PSUBSW—Sub tract P a ck ed Signed In tegers with Signed Satur ation Opcode Instruction Op/ En 64-Bit Mode [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 155 Documentation Changes Instru ction Oper and Enc oding ... PSUBUSB/PSUBUSW—Sub tr act P ack ed Unsigned In tegers with Unsigned Satur ation Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 66 0F E9 /[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 156 Documentation Changes PT EST - Logical C ompar e Instru ction Oper and Enc oding ... PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/P UNPCKHQDQ— Unpack High Data Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 66 0[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 157 Documentation Changes PUNPCKLBW/PUNPCK L WD/PUNPCKL DQ/PUNPCKL QDQ— Unpack Lo w Data Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 0F 60 / r PUNPCKLBW mm, mm/m32 A V alid Valid Interlea ve lo w-o[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 158 Documentation Changes PUSH—Push W or d, Doublewor d or Quadw ord On t o the S tack Opcode* Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description FF /6 PUSH r/m16 AV a l i d V a l i d P u s h r/m16. FF /6 PUSH r/m32 AN . E . V a l i d P u s h r/m3[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 159 Documentation Changes Instru ction Oper and Enc oding ... PUSHA/PUSHAD—Push All Ge neral-Purpose R egis ters Instru ction Oper and Enc oding ... PUSHF/PUSHFD—Push EFLAGS R egister on to the S tack Instru ction Oper and Enc oding ... Op/En Oper and 1 O[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 160 Documentation Changes P X OR—Logical Ex clusive OR Instru ction Oper and Enc oding ... RCL / RC R / ROL / RO R -— Rot at e Opcode* Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 0F EF / r PXOR mm, mm/m64 A V alid V alid Bitwise X OR of m[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 161 Documentation Changes Opcode** Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description C1 /2 ib RC L r/m32, imm8 CV a l i d V a l i d R o t a t e 3 3 b i t s ( C F , r/m32 ) left imm8 times. REX.W + C1 /2 ib RCL r/m64, imm8 C Valid N.E. Ro ta te 65 b[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 162 Documentation Changes Opcode** Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description C0 /0 ib RO L r/m8, imm8 CV a l i d V a l i d R o t a t e 8 b i t s r/m8 left imm8 times. REX + C0 /0 ib RO L r/m8*, imm8 C Valid N.E. Rota te 8 bits r/m8 left imm[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 163 Documentation Changes Instru ction Oper and Enc oding ... R CPPS—Compute R ecipr ocals o f Pack ed Single-Precision Floating-Point Va l u e s Instru ction Oper and Enc oding ... Opcode** Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description REX.W[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 164 Documentation Changes R CPSS—Compute R eciprocal of Scalar Single-Pr ecision Floating-Poi nt Va l u e s Instru ction Oper and Enc oding ... RDMSR—R ead fr om Model Specific Regis ter Instru ction Oper and Enc oding ... RDPMC—R ead Perf ormanc e-Moni[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 165 Documentation Changes Instru ction Oper and Enc oding Description The EAX register is loaded with the low-order 32 bits. The EDX register is loaded with the supported high-order bits of the counter . Th e number of high-order bits loaded into EDX is imple[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 166 Documentation Changes The Pentium 4 and Intel X eon processors also support “fast” (32-bit) and “slow” (40-bit) reads on the first 18 performance counters. Se lected this option using ECX[31]. If bit 31 is set, RDPMC reads only the low 32 bits of [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 167 Documentation Changes The performance-monitoring counters are ev ent counters that can be progr ammed to count events such as the number of instruct ions decoded, number of interrupts received, or number of cache loads. Appendix A, “P erformance Monitor[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 168 Documentation Changes ELSE (* ECX is not valid or CR4.PC E is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *) #GP(0); FI; (* P6 family processors and Pentiu m processor w ith MMX technology *) IF (ECX = 0 or 1) and ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0)) [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 169 Documentation Changes RDTSC—R ead Time-Stamp Coun ter Instru ction Oper and Enc oding Description Loads the current value of the processor’s time-stamp counter (a 64-bit MSR) into the EDX:EAX registers. The EDX register is loaded with the high-orde r [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 170 Documentation Changes RDTSCP—R ead Time-Stamp Coun ter and Pr ocessor ID Instru ction Oper and Enc oding ... R EP/RE PE/REP Z/REPNE/R EPNZ—R epeat S tring Oper ation Pre fix Opcode* Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 0F 01 F9[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 171 Documentation Changes F3 REX.W 6F REP OUTS D X, r/m32 A V alid N.E. Output RCX default siz e from [RSI] t o port D X. F3 AC REP L ODS AL A V alid V a lid Load (E)CX bytes from DS:[(E)SI] to A L. F3 RE X. W AC RE P LODS AL A Vali d N .E . Loa d RC X b yt e[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 172 Documentation Changes Instru ction Oper and Enc oding ... R ET—R eturn fr om Pr oc edur e F2 A6 REPNE CMPS m8, m8 A V alid V alid Find ma tching bytes in ES:[(E)DI] and DS:[(E)SI]. F2 REX.W A6 REPNE CMPS m8, m8 A Valid N.E. Find mat chin g byte s in [RD[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 173 Documentation Changes Instru ction Oper and Enc oding ... R OUNDPD — R ound Pa ck ed Double Pr ecision Floating-Poin t V alues Instru ction Oper and Enc oding ... R OUNDPS — R ound Pack ed Single Precision Floating-Poin t V alues Instru ction Oper and[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 174 Documentation Changes R OUNDSD — R ound Scalar Double Precision Floating-P oint V alues Instru ction Oper and Enc oding ... R OUNDSS — R ound Scalar Single Precision Floating-Poin t V alues Instru ction Oper and Enc oding ... RSM—R esume fr om S yst[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 175 Documentation Changes RSQR TPS—Compute Recipr ocals o f Square R oots o f P a ck ed Single- Precision Floating-P oint V alues Instru ction Oper and Enc oding ... RSQR TSS—Compute Recipr ocal of Square R oot o f Scalar Single-Pr ecision Floating-Poin t[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 176 Documentation Changes Instru ction Oper and Enc oding ... SAL/ SAR /S H L/ SH R— S hi ft Op/En Oper and 1 Oper and 2 Oper and 3 Operan d 4 AN A N A N A N A Opcode*** Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description D0 /4 SAL r/ m8 , 1 A Va l[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 177 Documentation Changes Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description D1 /7 SAR r/m16 ,1 A V alid V alid Signed divide* r/m16 by 2, once. D3 /7 SAR r/m16 , CL B Valid Valid Sig ned divide* r/m16 by 2, CL times. C1 /7 ib SAR r/m16, imm8[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 178 Documentation Changes Instru ction Oper and Enc oding ... Opcode*** Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description REX + D0 /5 SHR r/m8** , 1 A V alid N.E. Unsi gned divide r/m8 by 2, once. D2 /5 SHR r/m8 , CL B Valid V alid Unsigned divide [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 179 Documentation Changes SBB—Integer Sub tr action with Borr o w Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 1C ib SBB AL, imm8 A V alid V alid Subtract with borr o w imm8 from AL. 1D iw SBB AX, imm16 A Valid V alid Sub tr act with [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 180 Documentation Changes Instru ction Oper and Enc oding ... SCAS/SCASB/SCASW/SCASD—Scan S tring Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 1B / r SBB r32, r/m32 D Valid Valid Subtr act with borro w r/m32 from r32. REX.W + 1B / r S[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 181 Documentation Changes Instru ction Oper and Enc oding ... SET cc—Se t Byte on Condition NOT ES: * In 64-bit mode, only 64-bit (R DI) and 32-bit (EDI) address siz e s ar e supported. In non-64-bit mode, only 32- bit (EDI) and 16-b it (DI) address siz es [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 182 Documentation Changes REX + 0F 9E SETLE r/m8* A Valid N.E. Set byte if less or equal (ZF=1 or SF ≠ OF). 0F 96 SETNA r/m8 A Valid V alid S et byte if not abo ve (CF=1 or ZF=1). REX + 0F 96 SETNA r/m8* A Valid N.E. Set byte if no t abo ve (CF=1 or ZF=1). [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 183 Documentation Changes Instru ction Oper and Enc oding ... SFENCE—S tor e F ence Instru ction Oper and Enc oding REX + 0F 99 SETNS r/m8* A Valid N.E. Set byte if not sign (SF=0). 0F 95 SETNZ r/m8 A Valid V alid Set byte if not zer o (ZF=0). REX + 0F 95 S[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 184 Documentation Changes Description P erforms a serializing operation on all stor e-to-memory instructions that were issued prior the SFENCE instruction. This serializ ing operation guar antees that every store instruction that precedes the SFENCE instructi[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 185 Documentation Changes Instru ction Oper and Enc oding ... SHRD—Double Precision Shift Righ t Instru ction Oper and Enc oding ... Opcode* Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 0F A5 SHLD r/m32, r32 , CL BV a l i d V a l i d S h i f[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 186 Documentation Changes SHUFPD—Shuffle Pack ed Double-Precision Floating-P oint V alues Instru ction Oper and Enc oding ... SHUFPS—Shuffle Pack ed Single-Precision Floating-P oint V alues Instru ction Oper and Enc oding ... SIDT—S tore In terrupt Desc[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 187 Documentation Changes SLDT —S tore L ocal Descrip tor T able Register Instru ction Oper and Enc oding ... SMSW—S t ore Machine S tatus Wor d Instru ction Oper and Enc oding ... SQR TPD—Compute Squar e R oo ts o f P ack ed Double-Pr ecision Floating-[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 188 Documentation Changes Instru ction Oper and Enc oding ... SQR TPS—Compute Square R oots o f Pack ed Single-Precision Floating- Poi nt Valu e s Instru ction Oper and Enc oding ... SQR TSD—Compute Squar e R oot of Scalar Double-Precision Floating-P oin [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 189 Documentation Changes SQR TSS—Compute Squar e R oot of Scalar Single-Pr ecision Floating-Poin t Va l u e Instru ction Oper and Enc oding ... ST C—Se t Carry Flag Instru ction Oper and Enc oding ... STD—Set Dir ection Flag Instru ction Oper and Enc o[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 190 Documentation Changes STI—Se t Interrup t Flag Instru ction Oper and Enc oding ... STMX CSR—S t ore MX CSR Register S tate Instru ction Oper and Enc oding ... S TO S / S TO S B / S TO S W / S TO S D / S TO S Q — St o r e St r i n g Opcode* Instructi[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 191 Documentation Changes Instru ction Oper and Enc oding ... STR—S tor e T ask R egister Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description AA ST OSB A V alid V alid For legacy mode, st ore AL at addr es[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 192 Documentation Changes SUB—Subtr act Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 2C ib SUB AL, i mm8 A V alid V alid Subtr act imm8 fr om AL. 2D iw SUB AX, i mm16 A Valid V alid Sub tr act imm16 from AX. 2D id SUB EAX, i mm32 A V [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 193 Documentation Changes Instru ction Oper and Enc oding ... SUBPD—Subtr act P ack ed Double-Precision Floating-Poin t V alues Instru ction Oper and Enc oding ... SUBPS—Subtr a ct Pack ed Single-Precision Floating-P oint V alues Instru ction Oper and Enc[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 194 Documentation Changes SUBSD—Subtr act Scalar Double-Pr ecision Floating-Poin t V alues Instru ction Oper and Enc oding ... SUBSS—Subtr act Scalar Single-Precision Floating-P oint V alues Instru ction Oper and Enc oding ... SW APGS—S w ap GS Base Reg[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 195 Documentation Changes SYSC ALL—F ast Syst em Ca l l Instru ction Oper and Enc oding ... SY SEN T ER—F ast System Call Instru ction Oper and Enc oding ... Operation IF CR0.PE = 0 THEN #GP(0); FI; IF SYSENTE R_CS_MSR[15:2] = 0 THEN #GP(0); FI; EFLAGS.VM[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 196 Documentation Changes SS.BASE ← 0; (* Flat segment *) SS.LIMIT ← FFFFFH; (* 4-GByte limit *) SS.ARbyte.G ← 1; (* 4-KByte granularity *) SS.ARbyte.S ←; SS.ARbyte.TYPE ← 0011B; (* Read/Write, Accessed *) SS.ARbyte.D ← 1; (* 32-bit stack segmen t[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 197 Documentation Changes T EST—Logical Compar e Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description A8 ib TES T AL , i mm8 AV a l i d V a l i d A N D imm8 with AL; set SF , ZF , P F a cco rdi n g to re su l t. A9 iw TE ST A X , i mm16 AV a [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 198 Documentation Changes Instru ction Oper and Enc oding ... UCOMISD—Unor der ed Compar e Scalar Double-Precision Floating-P oint V alues and Set EFLA GS Instru ction Oper and Enc oding ... UCOMISS—Unor der ed Compar e Scalar Single-Precision Floating-P [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 199 Documentation Changes UD2—Undefined Ins truction Instru ction Oper and Enc oding ... UNPCKHPD—Unpack and I nterleav e High Pack ed Double-Precision Floating-Poin t V alues Instru ction Oper and Enc oding ... UNPCKHPS—Unpack and Interleav e High P ac[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 200 Documentation Changes UNPCKLPD—Unpack and In terleave L o w Pack ed Double-Precision Floating-Poin t V alues Instru ction Oper and Enc oding ... UNPCKLPS—Unpack and In terle ave L o w Pack ed Single-Precision Floating- Poin t V alues Instru ction Oper[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 201 Documentation Changes Instru ction Oper and Enc oding ... W AIT /FWAIT—W ait Instru ction Oper and Enc oding Description Causes the processor to check for and handle pending, unmask ed, floating-point excep- tions before proceeding. (FWAIT is an alterna[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 202 Documentation Changes WRMSR—Write to Model Specific R egister Instru ction Oper and Enc oding ... XADD—Exchange and Add Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 0F 30 WRMSR A V alid Valid [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 203 Documentation Changes X C HG—Ex change R egister/Memory with R egister Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 90+ rw XC H G A X, r16 A V alid V alid Exchange r16 with AX. 90+ rw XC H G r16[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 204 Documentation Changes X GETB V—Ge t V alue of Extended Con tr ol R egister Instru ction Oper and Enc oding ... XLA T /X LA TB—T able Look-up T r anslation Instru ction Oper and Enc oding ... Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Desc[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 205 Documentation Changes X OR—Logical Ex clusiv e OR Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mo de Description 34 ib XO R AL , i mm8 AV a l i d V a l i d A L X O R imm8. 35 iw X OR AX, i mm16 AV a l i d V a l i d A X X O R imm16. 35 id XO R E A X[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 206 Documentation Changes Instru ction Oper and Enc oding ... X ORPD—Bitwise Logical X OR for Double-Pr ecision Floating-Poin t V alues Instru ction Oper and Enc oding ... X ORPS—Bitwise Logical X OR for Single-Pr ecision Floating-Poin t V alues Instru ct[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 207 Documentation Changes XRST OR—Rest ore Pr ocessor Extended S tates Instru ction Oper and Enc oding ... XSA V E—Sav e Pr ocessor Ex tended S t ates Instru ction Oper and Enc oding ... XSETB V—Set Ex tended Con tr ol Regis ter Instru ction Oper and En[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 208 Documentation Changes 3. Updates to Chapter 4, Volume 3A Change bars show changes to Chapter 4 of the Int el ® 64 and IA-32 Architectures Soft- ware Developer’s Manual, Volume 3A: System Progr amming Guide, Part 1. -------------------------------------[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 209 Documentation Changes • PA T : page-attribute table. If CPUID .01H:EDX .PA T [bit 16] = 1, the 8-entry page-attribute table (P A T) is supported. When the PA T is supported, three bits in certain paging-structure entries select a memory type (used to de[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 210 Documentation Changes said to reference the other paging structure; in the latter , the entry is said to map a page . The first paging structure used for any translation is located at the physical address in CR3. A linear address is translated using the f[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 211 Documentation Changes P aging structures are given different names based their uses in the tr anslation process. T able 4-2 gives the names of the different paging structures. It also provides, for each structure, the source of the physical address used t[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 212 Documentation Changes The page-directory-pointer -table comprises four (4) 64-bit e ntries called PDPTEs. Each PDPTE controls access to a 1-GByte region of the linear-address space. Corresponding to the PDPTEs, the logical processor maintains a set of fou[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 213 Documentation Changes ... T ab l e 4-8 . F ormat of a P AE P age-Directory -Pointer-T able Entry (PDPTE) ... 3. Reserved fields must be 0. 4. If I A32_EFER.N XE = 0 and the P flag of a PDE or a PTE is 1, the XD flag (bit 63) is reserv ed. Bit Posi tion (s[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 214 Documentation Changes 4.5 IA-32E P AGING A logical processor uses IA-32e paging if CR0.PG = 1, CR4.PAE = 1, and IA32_EFER.LME = 1. With IA-32e paging, linear address are translated using a hierarchy of in-memory paging structures located using the content[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 215 Documentation Changes Because a PDPTE is identified using bits 47:30 of the linear address, it controls access to a 1-GByte region of the linear- address space. Use of the PDPTE depends on its PS flag (bit 7): 1 ... • If the PDPTE’s PS flag is 1, the [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 216 Documentation Changes — Bits 51:30 are from the PDPTE. — Bits 29:0 are from the original linear address. • If the PDE’ s PS flag is 0, a 4-KByte naturally aligned page directory is located at the physical address specified in b its 51:12 of the PD[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 217 Documentation Changes — Bits 51:12 are from the PDPTE. — Bits 11:3 are bits 29:21 of the linear address. — Bits 2:0 are all 0 ... If a paging-structure entry’s P flag (bit 0) is 0 or if the entry sets any reserved bit, the entry is used neither to[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 218 Documentation Changes Figure 4-11. F ormats o f CR3 and Pagi ng-S tructur e En tries with IA-32e P aging 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 M 1 NOTES: 1. M i s an abbreviation f or MAXPHY ADDR. M-1 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 219 Documentation Changes 4.7 P AGE-F AULT EX CEP TIONS Accesses using linear addresses may cause page-fault exceptions (#PF; exception 14). An access to a linear address may cause page-fault exception for either of two reasons: (1) there is no v alid transla[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 220 Documentation Changes The P A T is a 64-bit MSR (IA32_PA T ; MSR index 277H) comprising eight (8) 8-bit entries (entry i comprises bits 8 i +7:8 i of the MSR). For an y access to a physical address, the table combines the memory type specified for that ph[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 221 Documentation Changes — If the translation does use a PTE, the page size is 4 KBytes and the page number comprises bits 47:12 of the l inear address. ... 4.10.1.2 Caching T r anslations in TLBs The processor may acceler ate the paging process by caching[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 222 Documentation Changes while the lower bits come from the linear address of the access for which the translation is created. There is no way for software to be aware that multiple translations for smaller pages have been used for a large page. If software [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 223 Documentation Changes • PDPTE cache (IA-32e paging only). 1 Each PDPTE-cache entry is referenced by an 18-bit value and is used for linear addresses for which bits 47:30 have that value. The entry contains information from the PML4E and PDPTE used to tr[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 224 Documentation Changes • If the nature of the paging structures is such that a single entry may be used for multiple purposes (see Section 4.10.2. 3), so ftware should perform invalidations for all of these purposes. For example, if a single entry might [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 225 Documentation Changes • If a paging-structure entry is modified to change the accessed flag from 1 to 0, failure to perform an invalidation may result in the processor not setting that bit in response to a subsequent access to a linear address whose tra[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 226 Documentation Changes In some cases, the consequences of delayed invalidation may not affect softw are adversely . For example, when freeing a portion of the linear-address space (by marking paging-structure entries “not present”), invalidation using [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 227 Documentation Changes 4. Updates to Chapter 5, Volume 3A Change bars show changes to Chapter 5 of the Int el ® 64 and IA-32 Architectures Soft- ware Developer’s Manual, Volume 3A: System Progr amming Guide, Part 1. -------------------------------------[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 228 Documentation Changes by privilege level 0 operating system or execut ive procedures for fast returns to privilege level 3 user code. Stack pointers for SYSCALL/S YSRET are not sp ecified through model specific registers. The clearing of bits in RFLA GS i[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 229 Documentation Changes 5. Updates to Chapter 8, Volume 3A Change bars show changes to Chapter 8 of the Int el ® 64 and IA-32 Architectures Soft- ware Developer’s Manual, Volume 3A: System Progr amming Guide, Part 1. -------------------------------------[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 230 Documentation Changes • Unaligned 16-, 32-, and 64-bit accesses to cached memory that fit within a cache line Accesses to cacheable memory that are split across bus widths, cache lines, and page boundaries are not guaranteed to be atomic by the Intel Co[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 231 Documentation Changes Software should access semaphores (shared memory used for si gnalling between multiple processors) using identical addresses and operand lengths. F or example, if one processor accesses a semaphore using a word acce ss, other process[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 232 Documentation Changes Execute a serializ ing instruction; (* For e xample, CPUID instruction *) Execute new code; The use of one of these options is not required for programs intended to run on the P entium or Intel486 processors, but are recommended to e[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 233 Documentation Changes automatically preven ts two or more processors that hav e cached the same area of memory from simultaneously modifying data in that area. ... 8.2.1 Memory Ordering in the Intel ® Pen tium ® and Intel486 ™ Pr ocessors The Pentium [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 234 Documentation Changes • LFENCE instructions cannot pass earlier reads. • SFENCE instructions cannot pass earlier writes. • MFENCE instructions cannot pass earlier reads or writes. ... 8.2.4.2 Examples Illustr ating Memo ry-Or dering Principles f or [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 235 Documentation Changes • The page attribute table (PA T) can be us ed to strengthen memory ordering fo r a specific page or group of pages (see Section 11.12 , “Page Attribute T able (PA T)”). The PA T is available only in the Pentium 4, Intel X eon,[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 236 Documentation Changes applied to an address range dedicated to memory mapped I/O devices to force strong memory ordering. • For areas of memory where weak orderi ng is acceptable, the write back (WB) memory type can be chosen. Here, read s can be perfor[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 237 Documentation Changes • Privileged serializing instructions — INVD, INVEPT , INVLPG, INVVPID, L GDT , LIDT , LLDT , L TR, MOV (to control register , with the exception of MOV CR8 1 ), MOV (to debug register), WBINVD, and WRMSR. • Non-privileged seri[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 238 Documentation Changes 1. W aits on the BIOS initialization Lock Sema phore. When control of the semaphore is attained, initialization continues. 2. Loads the microcode update into the processor . 3. Initializes the MT RRs (using the same mapping that was [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 239 Documentation Changes 6. Updates to Chap ter 10, Volume 3A Change bars show changes to Chapter 10 of the Intel ® 64 and IA-32 Architectures Soft- ware Developer’s Manual, Volume 3A: System Progr amming Guide, Part 1. -----------------------------------[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 240 Documentation Changes NO T E In processors based on Intel Microarchitecture (Nehalem) the Local APIC ID Register is no longer Read/W rite; it is Read Only . Ta b l e 1 0 - 1 L o c a l A P I C Register Address Map Address Regist er Na me Softwar e Rea d / [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 241 Documentation Changes ... FEE0 01F0H T rigger Mode Register (TMR); bits 255:224 Read Only. FEE0 0200H Interrupt R equest Register (IRR); bits 31:0 Read Only. FEE0 0210H Interru pt R eques t Regis ter (IRR); bits 63:32 Read Only. FEE0 0220H Inter ru p t Re[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 242 Documentation Changes Suppress EOI-broadcasts Indicates whether software can inhibit the broadcast of EOI message by setting bit 12 of the Spurious Interrupt V e ctor Re gister; see Section 10.8.5 and Section 10.9. ... 10.5.1 Local V ect or T able The loc[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 243 Documentation Changes thermal monitor register and its associated interrupt were introduc ed in the P entium 4 and Intel X eon processors. As shown in Figure 10-8, some of these fields and flags are not available (and reserved) for some entries. ... 10.5.[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 244 Documentation Changes when the local APIC sets one of the error bits in the ESR. The L VT error register allows selection of the interrupt vector to be delivered to the processor core when APIC error is detected. The L VT error register also provid es a m[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 245 Documentation Changes ... 10.5.4 APIC Timer The local APIC unit contains a 32-bit programmable timer that is available to software to time events or operation s. This timer is set up by programming four registers: the divide configuration register (see Fi[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 246 Documentation Changes ... ... 10.6.1 Interrup t Command R egister (ICR) The interrupt command register (ICR) is a 64-bit local APIC register (see Figure 10-12) that allows software running on the processor to specify and send interprocessor inter- rupts ([...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 247 Documentation Changes — Destination Mode — Selects one of two destination modes (physical or logical). — Destination Fie ld — In physical destination mode, used to specify the APIC ID of the destination processor; in logica l destination mode, use[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 248 Documentation Changes Upon receiving and EOI, the AP IC clears the highest priority bit in the ISR and dispatches the next highest priority interrupt to the processor . If the terminated interrupt was a level-triggered interrupt, the local APIC also se nd[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 249 Documentation Changes priority level is established when the MOV CR8 instruction completes execution. Soft- ware does not need to force serializat ion after loading the TPR using MOV CR8. Use of the MOV CRn instruction require s a priv ilege level of 0. P[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 250 Documentation Changes NO T E D o n o t p r o g r a m a n L V T o r I O A P I C R T E w i t h a s p u r i o u s v e c t o r e v e n i f y o u set the mask bit. A spurious vector ISR does not do an EOI. If for some reason an interrupt is generated by an L V[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 251 Documentation Changes • Uses MSR programming interface to access AP IC registers in x2APIC mode instead of memory-mapped interfaces. Memory -mapped interface is supported when operating in xAPIC mode. 10.12.1 De tecting and Enabling x2APIC Mode Processo[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 252 Documentation Changes each register is available on the page re ferenced by IA32_APIC_ BASE[35:12] in xAPIC mode. There is a one-to-one mapping between the x2 APIC MSRs and the legacy xAPIC register offsets with the follow ing exceptions: • The Destinat[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 253 Documentation Changes 815H 150H ISR bits 191:160 Read-only 816H 160H ISR bits 223:192 Read-only 817H 170H ISR bits 255:224 Read-only 818H 180H T rigger Mode Regis ter (TMR); bits 31:0 Re ad -o nl y 819H 190H TMR bits 63:32 Rea d-only 81AH 1A0H TMR bits 95[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 254 Documentation Changes 10.12.1.3 Reserv ed Bit Checking Section 10.12.1.2 and T able 10-6 specifies the reserved bit definitions for the APIC regis- ters in x2APIC mode. Non-zero writes (by W R MSR instruction) to reserved bits to these registers will rais[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 255 Documentation Changes 10.12.2 x2APIC Register A vailability The local APIC registers can be accessed via the MSR interface only when the local APIC has been switched to the x2 APIC mode as described in Section 10 .12.1. Accessing any APIC register in the [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 256 Documentation Changes 10.12.5 x2APIC State T ransitions This section provides a detailed description of the x2APIC states of a local x2APIC unit, transitions between these states as well as in teractions of these states with INIT and RESET . 10.12.5.1 x2A[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 257 Documentation Changes enumerating topology . The presence of CPUI D leaf 0BH in a processor does not guar- antee support for x2APIC. If CPUID .EAX=0BH , ECX=0H:EBX returns zero an d maximum input value for basic CPUID information is grea ter than 0BH, the[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 258 Documentation Changes 10.12.9 ICR Oper ation in x2APIC Mode In x2APIC mode, the layout of the Interru pt Command Register is shown in Figure 10-12. The lower 32 bits of ICR in x2APIC mode is identical to the lower half of the ICR in xAPIC mode, except the[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 259 Documentation Changes 10.12.10 Determining IPI Destination in x2APIC Mode 10.12.10.1 L ogical Destin ation Mode in x2APIC Mode In x2APIC mode, the Logical Destination R egister (LDR) is increased to 32 bits wide. It is a read-only register to system softw[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 260 Documentation Changes 10.12.10.2 Deri ving Logical x2AP I C ID from the L ocal x2APIC ID In x2APIC mode, the 32-bit logical x2APIC ID , w hich can be read from LDR, is derived from the 32-bit local x2APIC ID . Specifically , the 16-bit logical ID sub-fiel[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 261 Documentation Changes 7. Updates to Chap ter 15, Volume 3A Change bars show changes to Chapter 15 of the Intel ® 64 and IA-32 Architectures Soft- ware Developer’s Manual, Volume 3A: System Progr amming Guide, Part 1. -----------------------------------[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 262 Documentation Changes 8. Updates to Chap ter 21, Volume 3B Change bars show changes to Chapter 21 of the Intel ® 64 and IA-32 Architectures Soft- ware Developer’s Manual, Volume 3B: System Progr amming Guide, Part 2. -----------------------------------[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 263 Documentation Changes The VMPTRST instruction stores the address of the logical processor’ s current VMCS into a specified memory location (it stores the value FFFFFFFF_FFFFFFFFH if there is no current VMCS). The launch state of a VMCS determines which [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 264 Documentation Changes ... 21.10 SOFTW AR E USE O F THE VMCS AND R ELATED ST R U C T U R E S This section details guidelines that softwa re should observe when using a VMCS and related structures. It also provides descrip tions of consequences for failing [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 265 Documentation Changes data of an active VMCS on the processor and not in the VMCS region. The following items detail some of the hazards of accessing VMCS data using ordinary memory operations: • Any data read from a VMCS with an ordinary memory read do[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 266 Documentation Changes The following software u sage is consistent with these limitations: • VMCLEAR should be executed for a VMCS before it is used for VM entry for the first time. • VMLAUNCH s hould be used for the first VM entry using a VMCS after V[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 267 Documentation Changes 9. Updates to Chap ter 22, Volume 3B Change bars show changes to Chapter 22 of the Intel ® 64 and IA-32 Architectures Soft- ware Developer’s Manual, Volume 3B: System Progr amming Guide, Part 2. -----------------------------------[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 268 Documentation Changes 10. Updates to Chap ter 25, Volume 3B Change bars show changes to Chapter 25 of the Intel ® 64 and IA-32 Architectures Soft- ware Developer’s Manual, Volume 3B: System Progr amming Guide, Part 2. ----------------------------------[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 269 Documentation Changes — Bits 63:52 are all 0. — Bits 51:30 are from the EPT PDPTE. — Bits 29:0 are from the original guest-ph ysical address. • If bit 7 of the EPT PDPTE is 0, a 4-KByte naturally aligned EPT page directory is located at the physic[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 270 Documentation Changes 11. Updates to Chap ter 27, Volume 3B Change bars show changes to Chapter 27 of the Intel ® 64 and IA-32 Architectures Soft- ware Developer’s Manual, Volume 3B: System Progr amming Guide, Part 2. ----------------------------------[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 271 Documentation Changes VMCS data cached by the processor are flushed to memory and that no other software can corrupt the current VMM’s VMCS data. It is also recommended that the VMM execute VMXOFF aft er such executions of VMCLEAR. The VMX capability MS[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 272 Documentation Changes 12. Updates to Chap ter 30, Volume 3B Change bars show changes to Chapter 30 of the Intel ® 64 and IA-32 Architectures Soft- ware Developer’s Manual, Volume 3B: System Progr amming Guide, Part 2. ----------------------------------[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 273 Documentation Changes the IA32_PEBS_ENABLE register for the respective counter , the software must also initialize the DS_BUFFER_MANA GEMENT_AREA data structure in memory to support capturing PEBS records for precise events. ... 30.14.1 Overview o f P erf[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 274 Documentation Changes 13. Updates to Appe ndix A, Volume 3B Change bars show changes to Appendix A of the Intel ® 64 and IA-32 Architectures Soft- ware Developer’s Manual, Volume 3B: System Progr amming Guide, Part 2. ----------------------------------[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 275 Documentation Changes T able A-2 Non-Architectur al Perf ormance Even ts In the Proc essor Co re for Int e l C ore i 7 Proc essor and In tel X eon Proc essor 5500 Series Even t Num. Umask Va l u e Event Ma sk Mnemonic Description Comment 04H 07H SB_DRAIN.[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 276 Documentation Changes Non-architectur al Performance monitoring events that are located in the uncore sub- system are implementation specific between different platforms using processors based on Intel microarchitecture (Nehalem). Processors with CPUID si[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 277 Documentation Changes Non-Architectur al Perf ormanc e Even ts In Ne x t Generation Pr oc essor Core (Codenamed West mere) (Continued) Non-architectur al P erformance monitoring even ts of the uncore sub-system for Proces- sors with CPUID signature of Dis[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 278 Documentation Changes 0CH 04H UNC_GQ_ SNOOP .GO T O_S_HIT_M Coun ts the n umber o f r emo te snoops that ha v e requested a cache line be se t to the S sta te fr om M sta te. Req ui res writing MSR 301H with mask = 1H 0CH 04H UNC_GQ_ SNOOP .GO T O_S_HIT_S[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 279 Documentation Changes 33H 07H UNC_QHL_FR C_A CK_ CNFL TS.ANY Counts number of Force Ackno wledge Con flict messages sent by the Quickpath Home Logic. 34H 01H UNC_Q HL_SLEEPS.IO H_ORDER Coun ts number o f occurr ences a request was put to sleep due to IOH [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 280 Documentation Changes 35H 02H UNC_ADDR_OPC ODE _MA TCH.REMOT E Coun ts numbe r of r eques ts fr om the remo te sock et, address/opc ode o f request is qualified by mask value written t o MSR 396H. The f ollowing mask values are supported: 0: NONE 40000000[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 281 Documentation Changes 81H 02H UNC_TH ERMAL_THR O TTLED_T EMP .C ORE _1 Cy cles tha t the PCU rec or ds that c ore 1 is in the power thr ottled sta te due to c ore’ s tempera ture being abo ve the thermal thro ttling threshold. 81H 04H UNC_TH ERMAL_THR O[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 282 Documentation Changes ... T able A-7 Fix ed-F unction Perf ormanc e Coun ter and Pre-de fined Perf ormanc e Even ts ... 86H 01H UNC_C Y CLES_UNHAL TED_L3_F LL_DISABL E Un core cyc les th at at l ea st o ne core i s unhalted and all L3 ways ar e disabled. [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 283 Documentation Changes 14. Updates to Appe ndix B, Volume 3B Change bars show changes to Appendix B of the Intel ® 64 and IA-32 Architectures Soft- ware Developer’s Manual, Volume 3B: System Progr amming Guide, Part 2. ----------------------------------[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 284 Documentation Changes T able B-2. IA-32 Ar chitectur al MSRs Regis ter Address Ar chitectural MSR Name and bit fields (F ormer MS R Name) MSR/Bit Descrip tion Intr oduc ed as Architectura l MSR Hex Decimal ... 179H 377 IA32_MC G_CAP (MCG_CAP) Global Mac h[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 285 Documentation Changes Regis ter Address Ar chitectural MSR Name and bit fields (F ormer MS R Name) MSR/Bit Descrip tion Intr oduc ed as Architectura l MSR Hex Decimal 417H 1047 IA32_MC5_MISC MC5_MISC 06_0FH 418H 1048 IA32_MC6_CTL MC6_CTL 06_1DH 419H 1049 [...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 286 Documentation Changes ... Regis ter Address Ar chitectural MSR Name and bit fields (F ormer MS R Name) MSR/Bit Descrip tion Intr oduc ed as Architectura l MSR Hex Decimal 43AH 1082 IA32_MC14_ADDR 1 MC14_ADDR 06_2EH 43BH 1083 IA32_MC14_MISC MC14_MISC 06_2E[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 287 Documentation Changes T able B-5 MSRs in Pr oces sors Based on Intel Micr oar chitecture (Con tinued)(Nehalem) Reg i st e r Address Register Name Scope Bit Descri p tion Hex Dec ... 1C8H 456 MSR_ LBR_SELECT Core Last Br anch Rec or d Filtering Select Regi[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 288 Documentation Changes Reg i st e r Address Register Name Scope Bit Descri p tion Hex Dec 407H 1031 MSR_MC1_MIS C Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs. ” ... 40BH 1035 MSR_MC2_ MISC Core See Section 15.3.2.4, “IA32_MCi_MIS C MSRs. ” 40[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 289 Documentation Changes Reg i st e r Address Register Name Scope Bit Descri p tion Hex Dec 41EH 1054 MSR_MC7_ADDR Pa ckage See Sectio n 15.3.2.3, “IA32_MCi_ADDR MSRs. ” 41FH 1055 MSR_MC7_MISC Pack a ge See Sectio n 15.3.2.4, “IA32_MCi_MISC MSRs. ” 4[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 290 Documentation Changes Reg i st e r Address Register Name Scope Bit Descri p tion Hex Dec 43CH 1084 MS R_MC15_CTL Package See Sect ion 15.3.2.1, “IA32_MCi_CTL MSRs. ” 43DH 1085 MSR_MC15_ ST A TU S Pack age See Section 15.3.2.2, “IA32_MCi_ST A TUS MSR[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 291 Documentation Changes B-5 MSRS IN THE NEX T GENER ATION IN TEL PR OC ESSOR (CODENAMED W ESMERE) Next Generation Intel 64 processors (codenamed W esmere) supports the MSR interfaces listed in T able B-5, plus additional MSR listed in T able B-6. ... T able[...]

Intel ® 64 and IA-32 Architectures Software Deve loper’s Manual D ocumentat ion Changes 292 Documentation Changes 15. Updates to Appe ndix G, Volume 3B Change bars show changes to A ppendix G of the Intel ® 64 and IA-32 Architecture s Soft- ware Developer’s Manual, Volume 3B: System Progr amming Guide, Part 2. --------------------------------[...]