Omron C40K manual

Cat. No. W146-E1-5 Programmable Controllers SYSMAC C20K/C28K/C40K/C60K[...]

K-type Programmable Controllers OPERA TION MANUAL Revised July 1999[...]

! ! ! ii Notice: OMRON products are manufactured for use according to proper procedures by a qualified operator and only for the purposes described in this manual. The following conventions are used to indicate and classify precautions in this manual. Always heed the information provided with them. Failure to heed precautions can result in injury t[...]

iii About this Manual: The OMRON K-type Programmable Controllers offer an ef fective way to automate processing, man- ufacturing, assembly , packaging, and many other processes to save time and money . Distributed con- trol systems can also be designed to allow centralized monitoring and supervision of several separate controlled systems. Monitorin[...]

v T ABLE OF CONTENTS PRECAUTIONS ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Intended Audience x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General Precautions x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

T able of contents vi 4-4 The Programming Console 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4-1 The Keyboard 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4-2 PC Modes 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

T able of contents vii 5-15-2 BINAR Y -TO-BCD – BCD(24) 1 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15-3 4-TO-16 DECODER – MLPX(76) 1 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15-4 16-TO-4 ENCODER – DMPX(77) 118 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 BCD Calculations 120 . . . . . . [...]

ix PRECAUTIONS This section provides general precautions for using the K-type Programmable Controllers (PCs) and related devices. Th e information contained in this section is important for the safe and reliable application of Pr ogrammable Control- lers. Y ou must read this section and understand the information contained before attempting to set [...]

! ! ! ! ! 5 Application Precautions x 1 Intended Audience This manual is intended for the following personnel, who must also have knowl- edge of electrical systems (an electrical engineer or the equivalent). • Personnel in charge of installing F A systems. • Personnel in charge of designing F A systems. • Personnel in charge of managing F A s[...]

! ! ! ! 5 Application Precautions xi • Locations subject to corrosive or flammable gases. • Locations subject to dust (especially iron dust) or salts. • Locations subject to exposure to water , oil, or chemicals. • Locations subject to shock or vibration. Caution T ak e appropriate and sufficient countermeasures when installing systems in t[...]

5 Application Precautions xii • Do not apply voltages to the Input Units in excess of the rated input voltage. Excess voltages may result in burning. • Do not apply voltages or connect loads to the Output Units in excess of the maximum switching capacity . Excess voltages or loads may result in burning. • Disconnect the functional ground term[...]

1 SECTION 1 Backgr ound 1-1 Introduction 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Relay Circuits: The Roots of PC Logic 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 PC T erminology 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

2 1-1 Introduction A Programmable Controller (PC) is basically a central processing unit (CPU) containing a program and connected to input and output (I/O) devices (I/O Devices) . The program controls the PC so that when an input signal from an input device turns ON, the appropriate response is made. The response nor- mally involves turning ON an o[...]

3 Actually there is not a total equivalence between these terms, because the term condition is used only to describe ladder diagram programs in general and is specifically equivalent to one of certain basic instructions. The terms input and output are not used in programming per se, except in reference to I/O bits that are assigned to input and out[...]

4 Special I/O Units are dedicated Units that are designed to meet specific needs. These include Analog T imer Units and Analog I/O Units. Link Units are used to create Link Systems that link more than one PC or link a single PC to remote I/O points. Link Units include I/O Link Units that are used to connect K-type PCs to Remote I/O Systems controll[...]

5 The first thing that must be assessed is the number of input and output points that the controlled system will require. This is done by identifying each device that is to send an input signal to the PC or which is to receive an output sig- nal from the PC. Keep in mind that the number of I/O points available de- pends on the configuration of the [...]

6 A Host Link Unit is required to interface a computer running LSS to the PC. Using an Optical Host Link Unit also enables the use of optical fiber cable to connect the FIT to the PC. Wired Host Link Units are available when desired. (Although FIT does not have optical connectors, conversion to optical fiber cable is possible by using Converting Li[...]

7 SECTION 2 Hardware Considerations 2-1 Introduction 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Indicators 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 PC Configuration 8 . . . . . . . . . . . . . . . . . .[...]

8 2-1 Introduction This section provides information on hardware aspects of K-type PCs that are relevant to programming and software operation. These include indica- tors on the CPU and basic PC configuration. This information is covered in detail in the Installation Guide . 2-2 Indicators CPU indicators provide visual information on the general op[...]

9 SECTION 3 Memory Ar eas 3-1 Introduction 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Data Area Structure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Internal Relay (IR) Area 12 . . . . . . . . . . . . . . . . . . . . .[...]

10 3-1 Introduction V arious types of data are required to achieve effective and correct control. T o facilitate managing this data, the PC is provided with various memory areas for data, each of which performs a different function. The areas generally ac- cessible by the user for use in programming are classified as data areas . The other memory a[...]

11 used to store execution conditions at branching points in ladder diagrams. The use of TR bits is described in Section 4 Writing and Inputting the Pro- gram. The TC area consists of TC numbers, each of which is used for a spe- cific timer or counter defined in the program. Refer to 3-7 Timer/Counter (TC) Area for more details on TC numbers and to[...]

12 When referring to the entire word, the digit numbered 0 is called the right- most digit; the one numbered 3, the leftmost digit. When inputting data into data areas, it must be input in the proper form for the intended purpose. This is no problem when designating individual bits, which are merely turned ON (equivalent to a binary value of 1) or [...]

13 The maximum number of available I/O bits is 16 (bits/word) times the number of I/O words. I/O bits are assigned to input or output points as described in Word Allocations . If a Unit brings inputs into the PC, the bit assigned to it is an input bit; if the Unit sends an output from the PC, the bit is an output bit. T o turn on an out- put, the o[...]

14 The following table shows which bits can be used as I/O bits in each of the K-type CPUs. Bits in the shaded areas can be used as work bits but not as output bits. 08 09 10 11 12 13 14 15 Word 00 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Word 01 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Word 00 00 01 02 03 04 05 06 07 08 09 10 11 12 1[...]

15 The following table shows which bits can be used as I/O bits in each of the Expansion I/O Units. Bits in the shaded areas can be used as work bits but not as output bits. The word addresses depend on the CPU that the Expan- sion I/O Unit is coupled to. In all cases the first Expansion I/O Unit address for input and output words is one more than [...]

16 A K-type PC can be configured with a CPU Unit and one or more of the fol- lowing Units: Expansion I/O Units, Analog T imer Units, or an I/O Link Unit. All of these Units are connected in series with the CPU Unit at one end. An I/O Link Unit, if included, must be on the other end (meaning only one I/O Link Unit can be used) and an Analog T imer U[...]

17 The tables on the following pages show the possible configurations for a K-type PC. Although the tables branch to show the various possibilities at any one point, there can be no branching in the actual PC connections. Y ou can choose either branch at any point and go as far as required, i.e., you can break off at any point to create a smaller P[...]

18 C20K/C28K Input Output C40P/C60P Input Output Input Output C20P/C28P/TU/LU Input Output C20P/C28P/TU/LU Input Output C20P/C28P/TU/LU Input Output C20P/C28P/TU/LU Input Output C20P/C28P/TU/LU Input Output C20P/C28P/TU/LU Input Output C20P/C28P/TU/LU Input Output C40P/C60P Input Output Input Output C40P/C60P Input Output Input Output C20P/C28P/TU/[...]

19 C20K/C28K Input Output C40P/C60P Input Output Input Output C20P/C28P/TU/LU Input Output C20P/C28P/TU/LU Input Output C20P/C28P/TU/LU Input Output C20P/C28P/TU/LU Input Output C20P/C28P/TU/LU Input Output C40P/C60P Input Output Input Output C40P/C60P Input Output Input Output C40P/C60P Input Output Input Output C20P/C28P/TU/LU Input Output C20P/C[...]

20 C40P/C60P Input Output Input Output C20P/C28P/TU/LU Input Output C20P/C28P/TU/LU Input Output C20P/C28P/TU/LU Input Output C20P/C28P/TU/LU Input Output C20P/C28P/TU/LU Input Output C20P/C28P/TU/LU Input Output C40K/C60K Input Output Input Output C40K/C60K Input Output Input Output C20P/C28P/TU/LU Input Output C40P/C60P Input Output Input Output [...]

21 3-4 Special Relay (SR) Area The SR area contains flags and control bits used for monitoring system op- eration, accessing clock pulses, and signalling errors. SR area word ad- dresses range from 18 through 19; bit addresses, from 1804 through 1907. The following table lists the functions of SR area flags and control bits. Most of these bits are [...]

! ! 22 These clock pulse bits are often used with counter instructions to create tim- ers. Refer to 5-1 1 Timer and Counter Instructions for an example of this. Pulse width 0.1 s 0.2 s 1.0 s Bit 1900 1901 1902 Bit 1900 0.1-s clock pulse 0.1 s .05 s .05 s Bit 1901 0.2-s clock pulse 0.2 s 0.1 s 0.1 s Bit 1902 1.0-s clock pulse 1.0 s 0.5 s 0.5 s Cauti[...]

23 SR bit 1904 turns ON when there is a carry in the result of an arithmetic op- eration. The content of CY is also used in some arithmetic operations, e.g., it is added or subtracted along with other operands. This flag can be set and cleared from the program using the SET CARRY and CLEAR CARR Y in- structions. Use CLC before any instruction using[...]

24 Once a TC number has been defined using one of these instructions, it can- not be redefined elsewhere in the program using the same or a different in- struction. If the same TC number is defined in more than one of these in- structions or in the same instruction twice, an error will be generated during the program check. There are no restriction[...]

25 SECTION 4 W riting and Inputting the Pr ogram 4-1 Introduction 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Instruction T erminology 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 The Ladder Diagram 27 . . . . . . . . . . . . .[...]

26 4-1 Introduction This section explains how to convert ladder diagrams to mnemonic code and input them into the PC. It then describes the basic steps and concepts in- volved in programming and introduces the instructions used to build the basic structure of the ladder diagram and control its execution. The entire set of instructions used in progr[...]

27 Most instructions have at least one or more operands associated with them. Operands indicate or provide the data on which an instruction is to be per- formed. These are sometimes input as the actual numeric values, but are usually the addresses of data area words or bits that contain the data to be used. For instance, a MOVE instruction that has[...]

28 4-3-1 Basic T erms Each condition in a ladder diagram is either ON or OFF depending on the status of the operand bit that has been assigned to it. A normally open condi- tion is ON if the operand bit is ON; OFF if the operand bit is OFF . An normally closed condition is ON if the operand bit is OFF; OFF if the operand bit is ON. Generally speaki[...]

29 The program is input into addresses in Program Memory . Addresses in Pro- gram Memory are slightly different to those in other memory areas because each address does not necessarily hold the same amount of data. Rather , each address holds one instruction and all of the definers and operands (de- scribed in more detail later) required for that i[...]

30 4-3-3 Ladder Instructions The ladder instructions are those that correspond to the conditions on the ladder diagram. Ladder instructions, either independently or in combination with the logic block instructions described next, form the execution conditions upon which all other instructions are executed. The first condition that starts any logic [...]

31 When two or more conditions lie on separate instruction lines running in par- allel and then joining together , the first condition corresponds to a LOAD or LOAD NOT instruction; the rest of the conditions correspond to OR or OR NOT instructions. The following example shows three conditions which corre- spond in order from the top to a LOAD NOT [...]

32 4-3-4 OUT and OUT NOT The OUT and OUT NOT instructions are used to control the status of the designated operand bit according to the execution condition. With the OUT instruction, the operand bit will be turned ON as long as the execution condi- tion is ON and will be turned OFF as long as the execution condition is OFF . With the OUT NOT instru[...]

33 Although simple in appearance, the diagram below requires an AND LOAD instruction. Instruction 0002 0003 0000 0001 Address Instruction Operands 0000 LD 0000 0001 OR 0001 0002 LD 0002 0003 OR NOT 0003 0004 AND LD --- The two logic blocks are indicated by dotted lines. Studying this example shows that an ON execution condition would be produced wh[...]

34 The following diagram requires AND LOAD to be converted to mnemonic code because three pairs of parallel conditions lie in series. The two means of coding the programs are also shown. 0000 0002 0004 0001 0003 0005 0100 Address Instruction Operands Address Instruction Operands 0000 LD 0000 0001 OR NOT 0001 0002 LD NOT 0002 0003 OR 0003 0004 AND L[...]

35 Both of the coding methods described above can also be used when using both AND LD and OR LD, as long as the number of blocks being combined does not exceed eight. The following diagram contains only two logic blocks as shown. It is not nec- essary to break block b down further , because it can coded directly using only AND and OR. 0000 0001 000[...]

36 The following diagram must be broken down into two blocks and each of these then broken into two blocks before it can be coded. As shown below , blocks a and b require an AND LD. Before AND LD can be used, however , OR LD must be used to combine the top and bottom blocks on both sides, i.e., to combine a1 and a2; b1 and b2. 0000 0001 0004 0005 0[...]

37 The following diagram requires first an OR LD and an AND LD to code the top of the three blocks, and then two more OR LDs to complete the mne- monic code. 0002 0003 0105 0000 0001 0004 0005 0006 0007 Address Instruction Operands 0000 LD 0000 0001 LD 0001 0002 LD 0002 0003 AND NOT 0003 0004 OR LD --- 0005 AND LD --- 0006 LD NOT 0004 0007 AND 0005[...]

38 Again, this diagram can be redrawn as follows to simplify program structure and coding and to save memory space. 0006 0007 0105 0005 0001 0002 0003 0004 0000 Address Instruction Operands 0000 LD 0006 0001 AND 0007 0002 OR 0005 0003 AND 0003 0004 AND 0004 0005 LD 0001 0006 AND 0002 0007 OR LD --- 0008 AND 0000 0009 OUT 0105 Our last example may a[...]

39 4-3-7 Coding Multiple Right-hand Instructions If there is more than one right-hand instruction executed with the same exe- cution condition, they are coded consecutively following the last condition on the instruction line. In the following example, the last instruction line contains one more condition that corresponds to an AND. 0000 0003 0001 [...]

40 There are two means of programming branching programs to preserve the execution conditions. One is to use TR bits; the other , to use interlocks (IL(02)/ILC(03)). The TR area provides eight bits, TR 0 through TR 7, that can be used to tem- porarily preserve execution conditions. If a TR bit is used as the operand of the OUTPUT instruction placed[...]

41 TR bits can be used as many times as required as long as the same TR bit is not used more than once in the same instruction block. Here, a new instruc- tion block is begun each time execution returns to the bus bar . If more than eight branching points requiring that the execution condition be saved are necessary in a single instruction block, i[...]

42 The problem of storing execution conditions at branching points can also be handled by using the INTERLOCK (IL(02)) and INTERLOCK CLEAR (ILC(03)) instructions. The branching point and all the conditions leading to it are placed on a separate line followed by all of the lines from the branching point. Each branch line is thus established as an ne[...]

43 If 0000 in the above diagram was OFF (i.e., if the execution condition for the first INTERLOCK instruction was OFF), instructions 1 through 4 would be executed with OFF execution conditions and execution would move to the instruction following the INTERLOCK CLEAR instruction. If 0000 was ON, the status of 0001 would be loaded to form the executi[...]

44 JUMP END instruction with a jump number of 00. Although, as in all jumps, no status is changed and no instructions are executed between the JUMP 00 and JUMP END 00 instructions, the program must search for the next JUMP END 00 instruction, producing a slightly longer execution time. Execution of programs containing multiple JUMP 00 instructions [...]

45 Except for the SHIFT key on the upper right, the gray keys are used to input instructions and designate data area prefixes when inputting or changing a program. The SHIFT key is similar to the shift key of a typewriter , and is used to alter the function of the next key pressed. (It is not necessary to hold the SHIFT key down; just press it once[...]

! ! 46 In PROGRAM mode, the PC does not execute the program. PROGRAM mode is for creating and changing programs, clearing memory areas, and registering and changing the I/O table. A special Debug operation is also available within PROGRAM mode that enables checking a program for cor- rect execution before trial operation of the system. DANGER Do no[...]

47 3. Connect the Programming Console to the PC. Make sure that the Pro- gramming Console is securely connected or mounted to the CPU; im- proper connection may inhibit operation. 4. Set the mode switch to PROGRAM mode. 5. T urn on PC power . 6. Enter the password. 7. Clear memory . Each of these operations from entering the password on is describe[...]

48 Key Sequence The following procedure is used to clear memory completely . 0000 0000MEMOR Y CLR? HR CNT DM 0000MEMOR Y CLR END HR CNT DM 0000 0000 It is possible to retain the data in specified areas and/or part of the Program Memory . T o retain the data in the HR and TC, and/or DM areas, press the appropriate key after entering REC/RESET . The [...]

49 For example, to leave the TC area uncleared and retaining Program Memory addresses 0000 through 0122, input as follows: 0000 0000 0000 0000MEMOR Y CLR? HR CNT DM 0000MEMOR Y CLR? HR DM 0123MEMOR Y CLR? HR DM 0000MEMOR Y CLR END HR DM 4-5-3 Clearing Error Messages Any error messages recorded in memory should also be cleared. It is as- sumed here [...]

50 Before starting to input a program, check to see whether there is a program already loaded. If there is a program already loaded that you do not need, clear it first using the program memory clear key sequence, then input the new program. If you need the previous program, be sure to check it with the program check key sequence and correct it as [...]

! 51 4-6-2 Inputting or Overwriting Programs Programs can be input or overwritten only in PROGRAM mode. The same procedure is used to either input a program for the first time or to overwrite a program that already exists. In either case, the current contents of Program Memory are overwritten, i.e., if there is no previous program, the NOP(00) inst[...]

52 The following ladder diagram can be input using the key inputs shown below . Displays will appear as indicated. 0000 0200 0200 LD 0002 0201READ NOP (00) 0201 TIM 00 0201 TIM DA T A #0000 0201 TIM #0123 0202READ NOP (00) 0202 FUN (??) 0202 TIMH (15) 01 0202 TIMH DA T A #0000 0202 TIMH #0500 0203READ NOP (00) Address Instruction Operands 0200 LD 0[...]

53 4-6-3 Checking the Program Once a program has been input, it should be checked for syntax to be sure that no programming rules have been violated. This check should also be performed if the program has been changed in any way that might create a syntax error . T o check the program, input the key sequence shown below . If an error is discovered,[...]

54 Message Meaning and appropriate response SBS UNDEFD A defined subroutine is not called by the main program. When this message is displayed because of interrupt routine definition, there is no problem. In all other cases, correct the program. STEP OVER STEP is used for more than 16 program sections. Correct the program to decrease the number of s[...]

55 Example 0000 0000SCAN TIME A VG 054.1MS 0000SCAN TIME A VG 053.9MS 4-6-5 Program Searches The program can be searched for occurrences of any designated instruction or data area bit address used in an instruction. Searches can be performed from any currently displayed address or from a cleared display . T o designate a bit address, press SHIFT , [...]

56 Example: Instruction Search 0000 0000 LD 0000 0200SRCH LD 0000 0202 LD 0000 1082SRCH END (01) 0000 0100 0100 TIM 01 0203SRCH TIM 01 0203 TIM DA T A #0123 Example: Bit Search 0000 0000 CONT 0005 0200CONT SRCH LD 0005 0203CONT SRCH AND 0005 1078CONT SRCH END (01) Inputting, Modifying, and Checking the Program Section 4-6[...]

! 57 4-6-6 Inserting and Deleting Instructions In PROGRAM mode, any instruction that is currently displayed can be de- leted or another instruction can be inserted before it. These are not possible in RUN or MONITOR modes. T o insert an instruction, display the instruction before which you want the new instruction to be placed, input the instructio[...]

58 The following key inputs and displays show the procedure for achieving the program changes shown above. Find the address prior to the insertion point Insert the instruction Program After Insertion Inserting an Instruction 0000 0000 OUT 0000 0000 OUT 0201 0207SRCH OUT 0201 0206READ AND NOT 0104 0206 AND 0000 0206 AND 0105 0206INSER T? AND 0105 02[...]

59 Find the instruction that requires deletion. Confirm that this is the instruction to be deleted. Program After Deletion Deleting an Instruction 0000 0000 OUT 0000 0000 OUT 0201 0208SRCH OUT 0201 0207READ AND NOT 0104 0207 DELETE? AND NOT 0104 0207DELETE END OUT 0201 0206READ AND 0105 Address Instruction Operands 0000 LD 0100 0001 AND NOT 0101 00[...]

60 Here, 0500 will be turned ON for one cycle after 0000 goes ON. The next time DIFU(13) 0500 is executed, 0500 will be turned OFF , regardless of the status of 0000. With the DIFFERENTIA TE DOWN instruction, 0501 will be turned ON for one cycle after 0001 goes OFF (0501 will be kept OFF until then) and will be turned ON the next time DIFD(14) is e[...]

61 4-8 Work Bits (Internal Relays) In programming, combining conditions to directly produce execution condi- tions is often extremely difficult. These dif ficulties are easily overcome, how- ever , by using certain bits to trigger other instructions indirectly . Such pro- gramming is achieved by using work bits. Sometimes entire words are re- quire[...]

62 Work bits can be used to simplify programming when a certain combination of conditions is repeatedly used in combination with other conditions. In the following example, IR 0000, IR 0001, IR 0002, and IR 0003 are combined in a logic block that stores the resulting execution condition as the status of IR 01 12. IR 01 12 is then combined with vari[...]

63 Differentiated Conditions W ork bits can also be used if differential treatment is necessary for some, but not all, of the conditions required for execution of an instruction. In this exam- ple, IR 0100 must be left on continuously as long as IR 0001 is ON and both IR 0002 and IR 0003 are OFF , or as long as IR 0004 is ON and IR 0005 is OFF . It[...]

64 Often, complicated programs are the result of attempts to reduce the number of times a bit is used. Every instruction line must also have at least one condition on it to determine the execution condition for the instruction at the right. Again, diagram A , be- low , must be redrawn as diagram B. If an instruction must always be exe- cuted (e.g.,[...]

65 4-10 Program Execution When program execution is started, the CPU cycles the program from top to bottom, checking all conditions and executing all instructions accordingly as it moves down the bus bar . It is important that instructions be placed in the proper order so that, for example, the desired data is moved to a word before that word is us[...]

67 SECTION 5 Instruction Set 5-1 Introduction 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Notation 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Instruction Format 68 . . . . . . . . . . . . . . . . . . .[...]

68 5-1 Introduction The K-type PCs have large programming instruction sets that allow for easy programming of complicated control processes. This section explains each instruction individually and provides the ladder diagram symbol, data areas, and flags used with each. Basic application examples are also provided as required in describing the inst[...]

! 69 paired with which JUMP END instruction. Bit operands are also contained in the same word as the instruction itself, although these are not considered definers. 5-4 Data Areas, Definer V alues, and Flags Each instruction is introduced with the ladder diagram symbol(s), the data areas that can be used with any operand(s), and the values that can[...]

70 The first word of any instruction defines the instruction and provides any de- finers and sometimes bit operands required by the instruction. All other oper- ands (i.e., operand words) are placed in words after the instruction word, one operand to a word, in the same order as these appear in the ladder symbol for the instruction. Although the SV[...]

71 If a right-hand instruction requires multiple instruction lines, all of the lines for the instruction are coded before the right-hand instruction. Each of the lines for the instruction are coded starting with LD or LD NOT to form ‘logic blocks’ that are combined by the right-hand instruction. An example of this for CNTR(12) is shown below . [...]

72 If the condition assigned 0004 was not in the diagram, the second LD using TR 0 would not be necessary because OUT with 0102 and the AND NOT with 0005 both require the same execution condition, i.e., the execution con- dition stored in TR 0. The diagram and mnemonic code for this program are shown below . 0000 0001 0002 0003 0005 0100 0101 0102 [...]

73 5-5 Ladder Diagram Instructions Ladder diagram instructions include ladder instructions and logic block in- structions. Ladder instructions correspond to the conditions on the ladder diagram. Logic block instructions are used to relate more complex parts of the diagram that cannot be programmed with ladder instructions alone. 5-5-1 LOAD, LOAD NO[...]

74 These six basic instructions correspond to the conditions on a ladder dia- gram. As described in Section 4 Writing and Inputting the Program , the status of the bits assigned to each instruction determines the execution con- ditions for all other instructions. Each of these instructions can be used as many times and a bit address can be used in [...]

75 5-6 Bit Control Instructions There are five instructions that can be used generally to control individual bit status. These are OUT , OUT NOT , DIFU(13), DIFD(14), and KEEP(1 1). These instructions are used to turn bits ON and OFF in different ways. 5-6-1 OUTPUT and OUTPUT NOT – OUT and OUT NOT B : Bit IR, HR, TR Ladder Symbol Operand Data Are[...]

76 Any output bit can be used in only one instruction that controls its status. See 3-3 Internal Relay (IR) Area for details. DIFU(13) and DIFD(14) are used to turn the designated bit ON for one cycle only . Whenever executed, DIFU(13) compares its current execution with the previ- ous execution condition. If the previous execution condition was OF[...]

77 5-6-3 KEEP – KEEP(1 1) B : Bit IR, HR Ladder Symbol Operand Data Areas S R KEEP(1 1) B KEEP(1 1) is used to maintain the status of the designated bit based on two execution conditions. These execution conditions are labeled S and R. S is the set input; R, the reset input. KEEP(1 1) operates like a latching relay that is set by S and reset by R[...]

78 Never use an input bit in an normally closed condition on the reset (R) for KEEP(1 1) when the input device uses an AC power supply . The delay in shutting down the PC’s DC power supply (relative to the AC power supply to the input device) can cause the designated bit of KEEP(1 1) to be reset. This situation is shown below . Input Unit A NEVER[...]

79 If the execution condition for IL(02) condition is OFF , the interlocked section between IL(02) and ILC(03) will be treated as shown in the following table: Instruction T reatment OUT and OUT NOT Designated bit turned OFF . TIM and TIMH(15) Reset. CNT , CNTR(12) PV maintained. KEEP(1 1) Bit status maintained. DIFU(13) and DIFD(14) Not executed ([...]

80 The following diagram shows IL(02) being used twice with one ILC(03). 0000 LD 0000 0001 IL(02) 0002 LD 0001 0003 TIM 1 1 # 0015 0004 LD 0002 0005 IL(02) 0006 LD 0003 0007 AND NOT 0004 0008 LD 0100 0009 CNT 01 10 0010 LD 0005 001 1 OUT 0502 0012 ILC(03) 0000 0001 ILC(03) IL(02) 0004 0005 0003 0002 IL(02) 0502 CP R CNT 01 IR 10 0100 Address Instru[...]

81 will not be changed. Each of these jump numbers can be used to define one jump. Because all of instructions between JMP(04) and JME(05) are skipped, jump numbers 01 through 08 can be used to reduce cycle time. If the jump number for JMP(04) is 00, the CPU will look for the next JME(05) with a Jump number of 00. T o do so, it must search through [...]

82 5-1 1 Timer and Counter Instructions TIM and TIMH are decrementing ON-delay timer instructions which require a TC number and a set value (SV). CNT is a decrementing counter instruction and CNTR is a reversible counter instruction. Both require a TC number and a SV . Both are also connected to multiple instruction lines which serve as an input si[...]

83 5-1 1-1 TIMER – TIM N : TC number # (00 through 47) Ladder Symbol Definer V alues SV : Set value (word, BCD) IR, HR, # Operand Data Areas TIM N SV SV may be between 000.0 and 999.9 seconds. The decimal point of SV is not input. Each TC number can be used as the definer in only one timer or counter in- struction. TC 00 through TC 47 should not [...]

84 All of the following examples use OUT in diagrams that would generally be used to control output bits in the IR area. There is no reason, however , why these diagrams cannot be modified to control execution of other instructions. The following example shows two timers, one set with a constant and one set via input word 01. Here, 0200 will be tur[...]

85 In the following example, 0500 would be turned ON 5.0 seconds after 0000 goes ON and then turned OFF 3.0 seconds after 0000 goes OFF . It is neces- sary to use both 0500 and 0000 to determine the execution condition for TIM 02; 0000 in an normally closed condition is necessary to reset TIM 02 when 0000 goes ON and 0500 is necessary to activate T[...]

86 Bits can be programmed to turn ON and OFF at a regular interval while a designated execution condition is ON by using TIM twice. One TIM functions to turn ON and OFF a specified bit, i.e., the completion flag of this TIM turns the specified bit ON and OFF . The other TIM functions to control the opera- tion of the first TIM, i.e., when the first[...]

87 T imers in interlocked program sections are reset when the execution condi- tion for IL(02) is OFF . Power interruptions also reset timers. If a timer that is not reset under these conditions is desired, SR area clock pulse bits can be counted to produce timers using CNT . Refer to 5-1 1-4 COUNTER – CNT for details. Program execution will cont[...]

88 T imer ranges are set in the output words as shown in the following table. Timer Output word bit 0.1 to 1s 1 to 10s 10 to 60s 1 to 10m T 0 08 OFF ON OFF ON 09 OFF OFF ON ON T 1 10 OFF ON OFF ON 11 OFF OFF ON ON T 2 12 OFF ON OFF ON 13 OFF OFF ON ON T 3 14 OFF ON OFF ON 15 OFF ON OFF ON Example This example uses an Analog T imer Unit connected to[...]

89 5. T 2 and T 3 are made inoperative if IR 0015 is turned ON. MOV(21) #0400 06 First Cycle Flag 15 14 13 12 1 1 10 09 08 07 06 05 04 03 02 01 00 1110010000000000 Content of IR O6 after MOV(21) Range settings 1815 Address Instruction Operands 0000 LD 1815 0001 MOV(21) # 0400 06 0606 0015 0607 0600 0002 0500 0100 0601 0003 0501 0101 0502 0102 0503 [...]

90 5-1 1-4 COUNTER – CNT N : TC number # (00 through 47) Ladder Symbol Definer V alues SV : Set value (word, BCD) IR, HR, # Operand Data Areas CP R CNT N SV Each TC number can be used as the definer in only one timer or counter in- struction. CNT is used to count down from SV when the execution condition on the count pulse, CP , goes from OFF to [...]

91 In the following example, the PV will be decremented whenever both 0000 and 0001 are ON provided that 0002 is OFF and either 0000 or 0001 was OFF the last time CNT 04 was executed. When 150 pulses have been counted down (i.e., when PV reaches zero), 0205 will be turned ON. 0000 CP R CNT 04 #0150 0002 0001 0205 CNT 04 Address Instruction Operands[...]

92 Because in this example the SV for CNT 01 is 100 and the SV for CNT 02 is 200, the completion flag for CNT 02 turns ON when 100 x 200 or 20,000 OFF to ON changes have been counted in 0001. This would result in 0203 being turned ON. 0203 CP R CNT 01 #0100 CP R CNT 02 #0200 CNT 01 0002 CNT 02 0000 0001 0002 CNT 01 CNT 02 Address Instruction Operan[...]

! 93 As the SV for CNT 01 is 700, the completion flag for CNT 02 turns ON when 1 second x 700 times, or 10 minutes and 40 seconds have expired. This would result in 0202 being turned ON. CP R CNT 01 #0700 0000 1902 0001 CNT 01 0202 Address Instruction Operands 0000 LD 0000 0001 AND 1902 0002 LD NOT 0001 0003 CNT 01 # 0700 0004 LD CNT 01 0005 OUT 02[...]

94 CNTR(12) is reset with a reset input, R. When R goes from OFF to ON, the PV is reset to zero. The PV will not be incremented or decremented while R is ON. Counting will begin again when R goes OFF . The PV for CNTR(12) will not be reset in interlocked program sections or for power interruptions. Changes in II and DI execution conditions, the com[...]

95 In the hard reset mode, the reset signal must have an ON time of at least 250 µ s. 250 µ s max. Input 0001 Description The high-speed counter counts the signals input from an external device con- nected to input 0000 and, when the high-speed counter instruction is ex- ecuted, compares the current value with a set of ranges which have been pres[...]

96 SR bit 1807 is the soft reset. When it is turned ON, the present value in the high-speed counter buffer is reset to “0000.” As for the hard reset, when the soft reset is ON, the count signal from input 0000 is not accepted. When pro- grammed with the soft reset, the high-speed counter would appear as below . Note that when the soft reset is [...]

97 The values must be four-digit BCD in the range 0000 to 9999. Note that fail- ure to enter BCD values will not activate the ERR flag. Always set a lower limit which is less than the corresponding upper limit. MOV is useful in setting limits. The following ladder diagram shows the use of MOV for setting limits and the associated timing diagram sho[...]

98 Examples The high-speed counter normally provides 16 output bits. If more than 16 are required, the high-speed counter may be programmed more than once. In the following program example, the high-speed counter is used twice to pro- vide 32 output bits. 1813 (normally ON) 0002 MOV(21) “S1” DM 32 MOV(21) “S2” DM 33 MOV(21) “S32” DM 35 [...]

99 Note that in the program just mentioned, the present value in the counter buffer is transferred to counter number 47 at points A and B. In this case, if S31 (=1,000) < S < S32 (=2,000) and S33 (=2,000) < S < S34 (=3,000), and if the present count value of the first high-speed counter (at point A) is 1,999 and that of the second count[...]

100 The high-speed counter is a ring counter and thus when its present count value is incremented from 9999 to 0000, the completion flag of CNT 47 is turned ON for one cycle. By using this flag as an input to the UP input of the reversible counter (i.e., cascade connection) you can increase the number of digits to eight. Although an ordinary counte[...]

101 The following diagram shows the packaging system and the corresponding timing chart. Pusher Packages Rotary encoder E6A (0000) Reflective photoelectric switch PH1 (0002) Motor 2 (M2) Rear limit switch for pusher LS1 (0003) Fixed stopper Front limit switch for pusher LS2 (0004) Upper limit switch for stopper LS3 (0005) Moving stopper Lower limit[...]

102 Here is the program example for the application. MOV(21) #0905 DM 32 MOV(21) #1 150 DM 33 MOV(21) #1450 DM 34 MOV(21) #1550 DM 35 1815 1807 HDM(61) 47 HR 0 HR 000 001 1 0006 0005 0100 0005 0003 0100 0004 0102 0004 0102 0003 0103 1000 0005 0006 0101 DIFU(13) 1000 0005 0002 1813 (normally ON) HR 001 0102 0103 0003 0101 001 1 0100 T ransfer limit [...]

103 0000 LD 1813 0001 MOV(21) # 0905 DM 32 0002 MOV(21) # 1 150 DM 33 0003 MOV(21) # 1450 DM 34 0004 MOV(21) # 1550 DM 35 0005 LD 1815 0006 OR 0005 0007 OUT 1807 0008 LD 0002 0009 HDM(61) 47 HR 0 0010 LD HR 000 001 1 AND NOT 001 1 0012 LD HR 001 0013 AND 001 1 0014 OR LD 0015 AND 0006 0016 OR 0100 0017 AND NOT 0005 0018 OUT 0100 0019 LD 0005 0020 A[...]

104 The transferred count value is then compared with the upper and lower limits of a set of ranges which have been preset in DM 00 through DM 31. If the current value is within any of the preset ranges, the corresponding bit of the results word, R, is turned ON. The bit in the result word will remain ON until the current value is no longer within [...]

105 The values must be four-digit BCD in the range 0000 through 9999. Failure to enter BCD values will not activate the ERR flag. Always set a lower limit which is less than the corresponding upper limit. MOV(21) is useful in setting limits. The following ladder diagram shows the use of MOV(21) for setting limits. 1813 (normally ON) 0002 (start inp[...]

106 The following timing example uses HR 0 as the results word. Start input 0002 HR 000 Limits: 0001 to 0002 Count input (1805) 0000 0001 0002 0003 0004 0005 0004 0003 0002 0001 0000 9999 9998 9997 0000 0000 0000 HR 001 Limits: 0002 to 0004 Present value Reset input (1804) UP/DOWN selection (1806) HR 015 Limits: 9980 to 9999 5-12 Data Shifting This[...]

107 SFT(10) shifts an execution condition into a shift register . SFT(10) is con- trolled by three execution conditions, I, P , and R. If SFT(10) is executed and 1) execution condition P is ON and was OFF the last execution and 2) R is OFF , then execution condition I is shifted into the rightmost bit of a shift regis- ter defined between St and E,[...]

108 When 1280 is OFF (all times but the first cycle after 0204 has changed from OFF to ON), the jump is taken and the status of 0100 will not be changed. I P R SFT(10) 00 01 JME(05) 00 JMP(04) 00 0200 0100 DIFU(13) 1280 0201 0202 0203 0204 1280 1280 Address Instruction Operands 0000 LD 0200 0001 AND 0201 0002 LD 0202 0003 LD 0203 0004 SFT(10) 00 01[...]

109 The program is set up so that a rotary encoder (0000) controls execution of SFT(10) through a DIFU(13), the rotary encoder is set up to turn ON and OFF each time a product passes the first sensor . Another sensor (0002) is used to detect faulty products in the chute so that the pusher output and HR 003 of the shift register can be reset as requ[...]

! 11 0 SFTR(84) is used to create a single- or multiple-word shift register that can be shifted to either the right or the left. T o create a single-word shift register , designate the same word for St and E. The control word provides the shift direction, the status to be input into the register , the shift pulse, and the reset input. The control w[...]

111 When the execution condition is OFF , WSFT(16) is not executed and the next instruction is moved to. When the execution condition is ON, 0000 is moved into St, the content of St is moved to St + 1, the content of St + 1 is moved to St + 2, etc., and the content of E is lost. F 0C 234521029 E St + 1 St 345210290000 E St + 1 St Lost 0000 Flags ER[...]

11 2 5-13-2 MOVE NOT – MVN(22) S : Source word IR, SR, DM, HR, TC, # D : Destination word IR, DM, HR Ladder Symbol Operand Data Areas MVN(22) S D When the execution condition is OFF , MVN(22) is not executed and the next instruction is moved to. When the execution condition is ON, MOV(21) trans- fers the inverted content of S (specified word or f[...]

11 3 The following example shows how to save the comparison result immedi- ately . If the content of HR 8 is greater than that of 9, 0200 is turned ON; if the two contents are equal, 0201 is turned ON; if content of HR 8 is less than that of HR 9, 0202 is turned ON. In some applications, only one of the three OUT s would be necessary , making the u[...]

11 4 The branching structure of this diagram is important so that 0200, 0201, and 0202 are controlled properly as the timer counts down. Because all of the comparisons here are to the timer ’s PV , the other operand for each CMP(20) must be in 4-digit BCD. TIM 10 0500 s. #2000 CMP(20) TIM 10 #3000 CMP(20) TIM 10 CMP(20) TIM 10 #4000 0201 0204 020[...]

11 5 5-15 Data Conversion The conversion instructions convert word data that is in one format into an- other format and output the converted data to specified result word(s). Con- versions are available to convert between binary (hexadecimal) and BCD and between multiplexed and non-multiplexed data. All of these instructions change only the content[...]

11 6 5-15-3 4-TO-16 DECODER – MLPX(76) S : Source word IR, SR, DM, HR, TC Di : Digit designator IR, DM, HR, TC, # Ladder Symbol Operand Data Areas R : First result word IR, DM, HR MLPX(76) S Di R The rightmost two digits of Di must each be between D and 3. All result words must be in the same data area. When the execution condition is OFF , MLPX([...]

11 7 Some example Di values and the digit-to-word conversions that they produce are shown below . 0 1 2 3 R R + 1 R R + 1 R + 2 0 1 2 3 0 1 2 3 0 1 2 3 R R + 1 R + 2 R + 3 R R + 1 R + 2 R + 3 S Di : 0031 Di : 0023 Di : 0030 Di : 0010 S S S ER : Undefined digit designator , or R plus number of digits exceeds a data area. The following program conver[...]

11 8 5-15-4 16-TO-4 ENCODER – DMPX(77) S : First source word IR, SR, DM, HR, TC R : Result word IR, DM, HR Ladder Symbol Operand Data Areas Di : Digit designator IR, DM, HR, TC, # DMPX(77) S R Di The rightmost two digits of Di must each be between 0 and 3. All source words must be in the same data area. When the execution condition is OFF , DMPX([...]

11 9 Some example Di values and the word-to-digit conversions that they produce are shown below . 0 1 2 3 R Di : 001 1 S S + 1 0 1 2 3 S S + 1 S + 2 S + 3 Di : 0030 R S S + 1 S + 2 S + 3 0 1 2 3 Di : 0032 R Di : 0013 0 1 2 3 S S + 1 R ER : Undefined digit designator , or S plus number of digits exceeds a data area. Content of a source word is 0000.[...]

120 5-16 BCD Calculations The BCD calculation instructions perform mathematic operations on BCD data. These instructions change only the content of the words in which results are placed, i.e., the contents of source words are the same before and after exe- cution of any of the BCD calculation instructions. STC(40) and CLC(41), which set and clear t[...]

121 If 0002 is ON, the following diagram clears CY with CLC(41), adds the con- tent of IR 02 to a constant (6103), places the result in DM 01, and then moves either all zeros or 0001 into DM 02 depending on the status of CY (1904). This ensures that any carry from the last digit is preserved in R + 1 so that the entire result can be later handled a[...]

! 122 case DM 05 and DM 04 are used to represent the intermediate 4 digits and the 4 right digits respectively . DM 06 represents the leftmost digit, the 9th dig- it. If a carry is generated, SR 1904 (CY) is turned ON and the constant 0001 is transferred to DM 06. If a carry is not generated SR 1904 remains OFF and the constant 0000 is transferred [...]

123 If CY is not set by executing SUB(31), the result is positive, the second sub- traction is not performed and HR 300 is not turned ON. HR 300 is pro- grammed as a self-maintaining bit so that a change in the status of CY will not turn it OFF when the program is recycled. CLC(41) SUB(31) 10 DM 01 HR 2 CLC(41) SUB(31) #0000 HR 2 HR 2 TR 0 1904 HR [...]

124 When the execution condition is OFF , MUL(32) is not executed and the next instruction is moved to. When the execution condition is ON, the contents of Md and Mr are multiplied and the rightmost four digits of the result are placed in R; the leftmost four digits, in R + 1. Md word Mr word R +1 word R word X ER : Md or Mr is not in BCD. Indirect[...]

125 When the execution condition is OFF , DIV(33) is not executed and the next instruction is moved to. When the execution condition is ON, the content of Dd is divided by the content of Dr and the result is placed in R and R + 1: the quotient in R and the remainder in R + 1. Dd word Dr word R word R + 1 word ÷ Quotient Remainder ER : Dd or Dr is [...]

126 5-17 Subroutines Subroutines can be used for one of two dif ferent purposes: either to separate off sections of large control tasks so that they can be handled as smaller ones and to enable you to reuse a given set of instructions at different places within one program or as a part of different programs. When the main pro- gram calls a subrouti[...]

! 127 SBS(91) may be used as many times as desired in the program (i.e., the same subroutine may be called from different places in the program). SBS(91) may also be placed into a subroutine to shift program execution from one subroutine to another , i.e., subroutines may be nested. When the second subroutine has been completed (i.e., RET(93) has b[...]

128 5-18 Step Instructions The step instructions STEP(08) and SNXT(09) are used in conjunction to set up breakpoints between sections in large programs so that the sections can be executed as units and reset upon completion. A step of program will usu- ally be defined to correspond with an actual process in the application. (Refer to the applicatio[...]

129 Interlocks, jumps, SBN(92), and END(01) must not be used within step pro- grams. Bits used as control bits must not be used anywhere else in the program un- less they are used to control the step (see example 3, below). If IR bits are used for control bits, their status will be lost during any power interruption. If it is necessary to maintain [...]

130 Examples The following three examples demonstrate the three types of execution con- trol possible with step programming. Example 1 demonstrates sequential execution; example 2, branching execution; and example 3, parallel execu- tion. The following process requires that three processes, loading, part installa- tion, and inspection/discharge, be[...]

131 The program for this process, shown below , utilizes the most basic type of step programming: each step is completed by a unique SNXT(09) that starts the next step. Each step starts when the switch that indicates the previous step has been completed turns ON. 0000 LD 0001 0001 SNXT(09) 1000 0002 STEP(08) 1000 Address Instruction Operands Addres[...]

132 The following diagram demonstrates the flow of processing and the switches that are used for execution control. Here, either process A or process B is used depending on the status of SW A1 and SW B1. Process A Process C End SW A1 SW B1 SW A2 SW B2 SW D Process B The program for this process, shown below , starts with two SNXT(09) that start pro[...]

133 The following process requires that two parts of a product pass simultane- ously through two processes each before they are joined together in a fifth process. V arious sensors are positioned to signal when processes are to start and end. Process C SW1 SW2 Process A SW3 SW4 Process D Process B Process E SW6 SW5 SW7 The following diagram demonst[...]

134 Thus, process B is reset directly and process B is set indirectly before exe- cuting the step for process E. 0200 LD 1003 0201 OUT 1003 0202 AND 0004 0203 SNXT(09) 1004 0204 STEP(08) 1002 STEP(08) 1000 SNXT(09) 1001 STEP(08) 1001 STEP(08) 1004 SNXT(09) 1005 STEP(08) Process A Process B Process C 0002 (SW3) 0005 (SW7) Process A started. Process [...]

135 5-19 Special Instructions The following instructions provide for special purposes: refreshing I/O bits during program execution, designating minimum cycle time, and inserting comments into a program. 5-19-1 I/O REFRESH – IORF(97) St : Starting word IR (00 through 09) Ladder Symbol E : End word IR (00 through 09) Operand Data Areas IORF(97) St[...]

136 5-19-3 NOT A TION INSERT – NETW(63) C1 : Comment 1 (Hex) # C2 : Comment 2 (Hex) # Ladder Symbol Operand Data Areas NETW(63) C1 C2 NETW(63) is not executed regardless of its execution condition. It is provided so that the programmer can leave comments in the program. The operands may be any hexadecimal value from 0000 through FFFF . There are [...]

137 SECTION 6 Pr ogram Execution T iming 6-1 Introduction 138 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Cycle T ime 139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Calculating Cycle T ime 141 . . . . . . . . . [...]

138 6-1 Introduction When writing and debugging a program, the timing of various operations must be considered. Not only is the time required to execute the program and perform other CPU operations important, but also the timing of each sig- nal coming into and leaving the PC must be such that the desired control ac- tion is achieved at the right t[...]

139 6-2 Cycle Time T o aid in PC operation, the average cycle time can be displayed on the Pro- gramming Console or any other Programming Device. Understanding the operations that occur during the cycle and the elements that affect cycle time is essential to effective programming and PC operations. The overall flow of CPU operation is as shown in t[...]

140 The first three operations immediately after power application are performed once each time the PC is turned on. The then on the operations shown above are performed in cyclic fashion, with each cycle forming one cycle. The cycle time is the time that is required for the CPU to complete one of these cycles. This cycle includes four types of ope[...]

141 6-3 Calculating Cycle Time The PC configuration, the program, and program execution conditions must be taken into consideration when calculating the cycle time. This means tak- ing into account such things as the number of I/O points, the programming instructions used, and whether or not Peripheral Devices are employed. This subsection shows so[...]

142 The cycle time is the total of all these calculations. 1.6 ms + 0.51 ms + 4.43 ms = 6.54 ms If a peripheral device had been present it would have been: 1.6 ms + 0.51 ms + 4.43 ms + 1 ms = 7.54 ms Process Formula Peripheral device servicing (ms) With Without 1. Overseeing 2. Input/output refreshing 3. Peripheral device servicing 4. Instruction e[...]

143 The cycle time is the total of all these calculations. 1.6 ms + 0.75 ms + 34.50 ms = 36.85 ms If a peripheral device had been present it would have been: 1.6 ms + 0.75 ms + 34.50 ms + 1.50 ms = 38.35 ms Process Formula Peripheral device servicing (ms) With Without 1. Overseeing 2. Input/output refreshing 3. Peripheral device servicing 4. Instru[...]

144 Function code Conditions Execution time( µ s) Instruction 09 SNXT 100 Always 10 SFT 102 When shifting 1 word 248 When shifting 13 words 90 to 254 When reset (1 to 13 words) 11 KEEP 19 When set 20 When reset 12 CNTR 95 When counting DOWN 190.5 When counting UP (word specified) 13 DIFU 60.5 When input = 1 56.5 When input = 0 14 DIFD 59 When inpu[...]

145 Function code Conditions Execution time( µ s) Instruction 84 SFTR 136 to 668 When resetting 1 to 64 DM words 44 NOP 42 IL 91 SBS 75 Always 92 SBN 26 Always 93 RET 49 Always 97 IORF 108 When refreshing 1 word 6-5 I/O Response T ime The I/O response time is the time it takes for the PC to output a control signal after it has received an input si[...]

146 The PC takes longest to respond when it receives the input signal just after the input refresh phase of the cycle. In this case the CPU does not recognize the input signal until the end of the next cycle. The maximum response time is thus one cycle longer than the minimum I/O response time, except that the input refresh time would not need to b[...]

147 SECTION 7 Pr ogram Debugging and Execution 7-1 Introduction 148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Debugging 148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Monitoring Operation and Modifying Data 14[...]

148 7-1 Introduction This section provides the procedures for inputting and debugging a program and monitoring and controlling the PC through a Programming Console. The Programming Console is the most commonly used Programming Device for the K-type PCs. It is compact and available both in hand-held models or CPU-mounted models. Refer to Appendix A [...]

149 The following displays show some of the messages that may appear . Refer to Section 8 T roubleshooting for an inclusive list of error messages, mean- ings, and appropriate responses. Note Cycle time is displayed as scan time. Fatal errors Non-fatal errors All errors have been cleared 0000 0000 FUN (??) 0000ERR CHK OK MEMOR Y ERR NO END INST I/O[...]

150 7-3-1 Bit/Digit Monitor The status of any bit or word in any data area can be monitored using the following operation. Although the operation is possible in any mode, ON/OFF status displays will be provided for bits only in MONITOR or RUN mode. The Bit/Digit Monitor operation can be entered either from a cleared display by designating the first[...]

151 The following examples show various applications of this monitor operation. Program Read then Monitor Indicates Completion flag is ON Monitor operation is cancelled 0100 0100READ TIM 00 T00 1234 T00 !0000 0100 TIM 01 Key Sequence Examples Monitoring Operation and Modifying Data Section 7-3[...]

152 Bit Monitor 0000 0000 LD 0001 0001 ON 0000 CONT 0001 Word Monitor 0000 0000 CHANNEL 00 0000 CHANNEL HR 1 cH1 FFFF cH0 0000 Monitoring Operation and Modifying Data Section 7-3[...]

153 Multiple Address Monitoring 0000 0000 TIM 00 T00 0100 0000 T00 0100 0001 T00 0100 0001 T00 OFF 0100 D00 0001 T00 OFF 0100 D00 0001 T00 10FF OFF 0100 T00 D00 0001 0100 10FF OFF D00 0001 10FF^ OFF 0001 OFF 0000 CONT 0001 0000 CHANNEL DM 00 Cancels monitoring of leftmost address Cancels Monitor operation 7-3-2 Force Set/Reset When the Bit/Digit Mo[...]

154 Key Sequence The following example shows how either bits or timers can be controlled with the Force Set/Reset operation. The displays shown below are for the follow- ing program section. 0200 LD 0002 0201 TIM 00 # 0123 0202 LD TIM 00 0203 OR 0501 0204 AND NOT 0003 0205 OUT 0501 TIM 00 SV 0002 TIM 00 0501 0501 0003 Address Instruction Operands E[...]

155 The following displays show what happens when TIM 00 is set with 0100 OFF (i.e., 0500 is turned ON) and what happens when TIM 00 is reset with 0100 ON (i.e., timer starts operation, turning OFF 0500, which is turned back ON when the timer has finished counting down the SV). Indicates that the time is up Returns to the original condition after a[...]

156 T o change contents of the leftmost word address, press CHG, input the de- sired value, and press WRITE. Key Sequence The following example shows the effects of changing the PV of a timer . This example is in MONITOR mode Timing Timing PV changed Timing Timing 0000 0000 TIM 00 T00 0122 0000PRES V AL? T00 01 19 ???? 0000PRES V AL? T00 0100 0200 [...]

157 Key Sequence The following example shows inputting a new constant and changing from a constant to a word designation. Inputting New SV 0000 0000 TIM 00 0201SRCH TIM 00 0201 TIM DA T A #0123 0201 TIM DA T A T00 #0123 #???? 0201 TIM DA T A T00 #0123 #0124 0201 TIM DA T A #0124 0201 DA T A? T00 #0123 c??? 0201 DA T A? T00 #0123 c 10 0201 TIM DA T [...]

158 The PC must be in PROGRAM mode for all cassette tape operations. While the operation is in progress, the cursor will blink and the block count will be incremented on the display . Cassette tape operations may be halted at any time by pressing the CLR key . The following error messages may appear during cassette tape operations. Message Meaning [...]

159 Example 0000 0000MT FILE NO!00000012 0000MT FILE NO!00000000 Blinking Continue within 5 seconds Recording in progress When it comes to END Stop recording with CLR Saved up to stop address Start recording 0000MT RECORD ~ FILE NO!00000012 0075MT RECORD ~ FILE NO!00000012 0145MT RECORD ~ END (01) 0145MT DISCONTD END (01) (0100) 1 193RECORD END END[...]

160 Key Sequence Example Restoring in progress END reached Restored up to END Comparison in progress END reached Stop comparison using CLR Compared up to end of tape 0000MT PLA Y ~ FILE NO!00000012 0242MT PLA Y ~ FILE NO!00000012 0480MT RECORD ~ END (01) 1 193MT DISCONTD END (01) (0100) 0145 RECORD END END (01) (0100) 0034MT PLA Y ~ FILE NO!0000001[...]

161 SECTION 8 T r oubleshooting 8-1 Introduction 162 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Reading and Clearing Errors and Messages 162 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 Error Messages 162 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

! 162 8-1 Introduction The K-type PCs provide self-diagnostic functions to identify many types of abnormal system conditions. These functions minimize downtime and enable quick, smooth error correction. This section provides information on hardware and software errors that occur during PC operation. Program input and program syntax errors are descr[...]

163 The following error messages appear for errors that occur after program exe- cution has been started. PC operation and program execution will continue after one or more of these error have occurred. The POWER, RUN, and ALARM indicators will be lit and the ERR indicator will not be lit for any of these errors. The RUN output will be ON. Error an[...]

164 8-4 Error Flags The following table lists the flags and other information provided in the SR area that can be used in troubleshooting. Details are provided in 3-4 Special Relay (SR) Area . SR Area Address Function 1808 Battery Alarm Flag 1809 Cycle T ime Error Flag 1903 Instruction Execution Error (ER) Flag A number of other error messages are [...]

165 Appendix A Standard Models There are four K-type C-series CPUs. A CPU can be combined with any of six types of Expansion I/O Unit and/or an Analog T imer , Analog I/O Unit, or I/O Link Unit. CPUs Expansion I/O Units Analog Timer Unit Analog I/O Units I/O Link Unit C20K-C jj - j C28K-C jj - j C40K-C jj - j C60K-C jj - j C4K-I j /O jj C4K-TM C16P[...]

Standard Models Appendix A 166 CPUs Name Power supply Inputs Outputs Model number Standards C20K 100 to 240 V AC 24 VDC, 12 pts Relay w/socket 8 pts C20K-CDR-A U, C T ransistor , 1 A C20K-CDT1-A U, C T riac, 1 A C20K-CDS1-A U, C 24 VDC, 2 pts Relay w/socket C20K-CAR-A U, C, N, L 100 to 120 V AC, 10 pts Triac, 1A C20K-CAS1-A U, C 24 VDC 24 VDC, 12 p[...]

Appendix A Standard Models 167 I/O Units Name Power Supply Inputs Outputs Model number Standards C4K I/O Unit --- 24 VDC, 4 pts --- C4K-ID U, C 100 to 120 V AC, 4 pts --- C4K-IA U, C --- Relay w/socket 4 pts C4K-OR2 U, C T ransistor , 1 A C4K-OT2 U, C T riac, 1A C4K-OS2 U, C C16P I/O Unit 100 to 240 V AC 24 VDC, 16 pts --- C16P-ID-A U, C --- Relay [...]

Standard Models Appendix A 168 Special Units Name Specifications Model number Standards Analog T imer Unit Settings: 0.1 s to 10 min (one cable, C4K-CN502, included) C4K-TM U, C Analog T imer External Connector 2-m cable and connector C4K-CN223 --- Analog Input Unit 1 input; input ranges: 4 to 20 mA, 1 to 5 V C1K-AD U, C 4 inputs; input ranges: 4 t[...]

Appendix A Standard Models 169 Mounting Rail and Accessories Name Specifications Model number Standards DIN T rack Length: 50 cm Not usable with C60K PFP-50N Length: 1 m PFP-100N --- PFP-100N2 End Plate --- PFP-M Spacer --- PFP-S Factory Intelligent T erminal (FIT) Name Specifications Model number Standards FIT 1. FIT Computer 2. SYSMA TE Ladder Pa[...]

Standard Models Appendix A 170 Peripheral Devices Name Specifications Model number Standards Programming Console V ertical, with backlight 3G2A5-PRO13-E U, C Horizontal, with backlight 3G2A6-PRO15-E --- Hand-Held, with backlight. The Programming Console Adapter AP003 and connecting cable CN222/CN422 are necessary . They are sold separately . C200H-[...]

171 Appendix B Programming Instructions and Execution T imes Function code Name Mnemonic Page - LOAD LD 73 - LOAD NOT LD NOT 73 - AND AND 73 - AND NOT AND NOT 73 - OR OR 73 - OR NOT OR NOT 73 - AND LOAD AND LD 74 - OR LOAD OR LD 74 - OUTPUT OUT 75 - OUTPUT NOT OUT NOT 75 - TIMER TIM 83 - COUNTER CNT 90 00 NO OPERA TION NOP 81 01 END END 81 02 INTER[...]

Programming Instructions and Execution T imes Appendix B 172 Function code Page Mnemonic Name 61 HIGH-SPEED DRUM COUNTER HDM 94 62 END W AIT ENDW 135 63 NOT A TION INSERT NETW 136 76 4-TO-16 DECODER MLPX 11 6 77 16-TO-4 ENCODER DMPX 11 8 84 REVERSIBLE SHIFT REGISTER SFTR 109 91 SUBROUTINE ENTER SBS 126 92 SUBROUTINE DEFINE SBN 126 93 RETURN RET 126[...]

Appendix B Programming Instructions and Execution T imes 173 Function code Conditions Execution time( µ s) Instruction --- TIM 95 When timing 95.5 to 186.5 When reset CNT 80.5 When counting 91.5 TO 184 When reset 00 NOP 2 Always 01 END — Refer to Cycle Time Calculation Example. 02 IL 2.5 Always 03 ILC 3 Always 04 JMP 94 Always 05 JME 38 Always 0[...]

Programming Instructions and Execution T imes Appendix B 174 Function code Conditions Execution time( µ s) Instruction 33 DIV 572 When dividing a DM word by a DM word 40 STC 16 Always 41 CLC 16 Always 60 RDM 695 At reset 61 HDM 734 Always 62 ENDW 197 With DM word 63 NETW 58 Always 76 MLPX 212.5 Word, 1 digit (constant) —> word 288 Word, 4 dig[...]

Appendix B Programming Instructions and Execution T imes 175 Ladder Diagram Instructions Name Mnemonic Symbol Function Operands LOAD LD LD B Used to start instruction block with status of designated bit. B: IR SR HR TC TR LOAD NOT LD NOT LD NOT B Used to start instruction block with in- verse of designated bit. B: IR SR HR TC TR AND AND AND B Logic[...]

Programming Instructions and Execution T imes Appendix B 176 Name Mnemonic Operands Function Symbol OUTPUT OUT B OUT B T urns ON designated bit. B: IR HR TR OUTPUT NOT OUT NOT OUT NOT B B T urns OFF designated bit. B: IR HR TR TIMER TIM TIM N SV TIM N SV ON-delay (decrementing) timer opera- tion. Set value: 999.9 s; accuracy: +0.0/-0.1 s. Same TC b[...]

Appendix B Programming Instructions and Execution T imes 177 Special Instructions Name Mnemonic Symbol Function Operands NO OPERA TION NOP (00) None Nothing is executed and next instruc- tion is moved to. None END END(01) END(01) Required at the end of the program. None INTERLOCK IL(02) INTERLOCK CLEAR ILC(03) IL(02) ILC(03) If interlock condition [...]

Programming Instructions and Execution T imes Appendix B 178 Name Mnemonic Operands Function Symbol DIFFERENTIA TE UP DIFU(13) DIFFERENTIA TE DOWN DIFD(14) DIFU(13) DIFD(14) B B DIFU turns ON the designated bit (B) for one cycle on the rising edge of the input signal; DIFD turns ON the bit for one cycle on the trailing edge. The maximum number of D[...]

Appendix B Programming Instructions and Execution T imes 179 Name Mnemonic Operands Function Symbol BINAR Y -TO-BCD BCD(24) BCD(24) S R Converts binary data in source word (S) into BCD, and outputs converted data to result word (R). x16 0 x16 1 x16 2 x16 3 x10 1 x10 2 x10 3 S R ( BIN) (BCD ) x10 0 S: IR SR HR DM R: IR HR DM BCD ADD ADD(30) ADD(30) [...]

Programming Instructions and Execution T imes Appendix B 180 Name Mnemonic Operands Function Symbol END W AIT ENDW(62) ENDW(62) N Used to force a cycle time longer than normal causing the CPU to wait. N: IR HR TC DM # NOT A TION INSERT NETW(63) NETW(63) C1 C2 Used to leave comments in the pro- gram. # 4-TO-16 DECODER MLPX(76) MLPX(76) S Di R Conver[...]

Appendix B Programming Instructions and Execution T imes 181 Name Mnemonic Operands Function Symbol RETURN RET(93) RET(93) Indicates the end of a subroutine defi- nition. None I/O REFRESH IORF(97) IORF(97) St E Refreshes I/O words between a speci- fied range. Refreshes words in word units. St/E: 00 to 09 Refer to table at beginning of Appendix B fo[...]

183 Appendix C Programming Console Operations Name Function Page Data Clear Used to erase data, either selectively or totally , from the Program Memory and the IR, AR, HR, DM, and TC areas. 47 Address Designation Displays the specified address. 50 Program Search Searches a program for the specified data address or instruction. 55 Instruction Insert[...]

Programming Console Operations Appendix C 184 Programming Operations Operation/Description Modes* Key sequence Address Designation Displays the specified address. Can be used to start programming from a non-zero address or to access an address for editing. Leading zeros need not be entered. The contents of the address will not be displayed until th[...]

Appendix C Programming Console Operations 185 Monitoring and Data Changing Operations Operation/Description Modes* Key sequence Bit/Word Monitor Up to six memory addresses, containing either words or bits, or a combination of the two, can be monitored at once. Only three can be displayed at any one time. If operated in RUN or MONITOR mode, the stat[...]

Programming Console Operations Appendix C 186 Operation/Description Key sequence Modes* SV Change, SV Reset There are three ways of modifying the SVs for timers and counters. One method is to enter a new value. The second is to increment or decrement the existing SV . In MONITOR mode the SV can be changed while the program is being executed. Increm[...]

Appendix C Programming Console Operations 187 Cassette T ape Operations Operation/Description Modes* Key sequence Program Memory Save Copies data from the Program Memory to tape. The file no. specified in the instructions provides an identifying address for the information within the tape. Each file number should be used only once per tape. If only[...]

189 Appendix D Error and Arithmetic Flag Operation The following table shows which instructions affect the ER, CY , GT , L T and EQ flags. In general, ER indicates that operand data is not within requirements. CY indicates arithmetic or data shift results. GT indicates that a compared value is larger than some standard, L T that it is smaller; and [...]

191 Appendix E Binary–Hexadecimal–Decimal T able Decimal BCD Hex Binary 00 00000000 00 00000000 01 00000001 01 00000001 02 00000010 02 00000010 03 0000001 1 03 0000001 1 04 00000100 04 00000100 05 00000101 05 00000101 06 000001 10 06 000001 10 07 000001 1 1 07 000001 1 1 08 00001000 08 00001000 09 00001001 09 00001001 10 00010000 0A 00001010 11[...]

193 Appendix F W ord Assignment Recording Sheets This appendix contains sheets that can be copied by the programmer to record I/O bit allocations and terminal assignments on the Racks, as well as details of work bits, data storage areas, timers, and counters.[...]

W ord Assignment Recording Sheets Appendix F 194 Programmer: Program: Date: Page: Word: Unit: Bit Field device Notes 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Word: Unit: Bit Field device Notes 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Word: Unit: Bit Field device Notes 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Word: Unit: Bit Fie[...]

Appendix F W ord Assignment Recording Sheets 195 Programmer: Program: Date: Page: Area: Word: Bit Usage Notes 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Area: Word: Bit Usage Notes 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Area: Word: Bit Usage Notes 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Area: Word: Bit Usage Notes 00 01 02 03 [...]

W ord Assignment Recording Sheets Appendix F 196 Programmer: Program: Date: Page: Word Contents Notes Word Contents Notes Data Storage[...]

Appendix F W ord Assignment Recording Sheets 197 Programmer: Program: Date: Page: TC address T or C Set value Notes TC address T or C Set value Notes Timers and Counters[...]

199 Appendix G Program Coding Sheet The following page can be copied for use in coding ladder diagram programs. It is designed for flexibility , al- lowing the user to input all required addresses and instructions. When coding programs, be sure to specify all function codes for instructions and data areas (or # for constant) for operands. These wil[...]

Program Coding Sheets Appendix G 200 Programmer: Program: Date: Page: Address Instruction Operand(s) Address Instruction Operand(s) Address Instruction Operand(s)[...]

201 Glossary address The location in memory where data is stored. For data areas, an address consists of a two-letter data area designation and a number that designate the word and/or bit location. For the UM area, an address designates the in- struction location (UM area); for the FM area, the block location (FM area), etc. allocation The process [...]

Glossary 202 call A process by which instruction execution shifts from the main program to a subroutine. The subroutine may be called by an instruction or by an interrupt. carry flag A flag that is used with arithmetic operations to hold a carry from an addition or multiplication operation or to indicate that the result is negative in a sub- tracti[...]

Glossary 203 data area boundary The highest address available in a data area. When designating an operand that requires multiple words, it is necessary that the highest address in the data area is not exceeded. debug A process by which a draft program is corrected until it operates as intended. Debugging includes both removal of syntax errors as we[...]

Glossary 204 exection condition The ON or OFF status under which an instruction is executed. The execution condition is determined by the logical combination of conditions on the same instruction line and up to the instruction being executed. execution time The time required for the CPU to execute either an individual instruction or an entire progr[...]

Glossary 205 Host Link System One or more host computers connected to one or more PCs through Host Link Units so that the host computer can be used to transfer data to and re- ceive data from the PC(s). Host Link Systems enable centralized manage- ment and control of a PC System. Host Link Unit An interface used to connect a PC to a host computer i[...]

Glossary 206 input bit A bit in the IR area that is allocated to hold the status of an input. input device An external device that sends signal(s) into the PC System. input point The point at which an input enters the PC System. An input point physically corresponds to terminals or connector pin(s). input signal A change in the status of a connecti[...]

Glossary 207 ladder diagram symbol A symbol used in a ladder-diagram program. ladder instruction An instruction that represents the ‘rung’ portion of a ladder-diagram program. The other instructions in a ladder diagram fall along the right side of the dia- gram and are called terminal instructions. leftmost (bit/word) The highest numbered bits [...]

Glossary 208 nonfatal error A hardware or software error that produces a warning but does not stop the PC from operating. normally closed condition A condition that produces an ON execution condition when the bit assigned to it is OFF , and an OFF execution condition when the bit assigned to it is ON. normally open condition A condition that produc[...]

Glossary 209 output bit A bit in the IR area that is allocated to hold the status to be sent to an output device. output device An external device that receives a signal(s) from the PC System. output point The point at which an output leaves the PC System. An output point physical- ly corresponds to terminals or connector pin(s). output signal A ch[...]

Glossary 210 Programming Device A peripheral device used to input a program into a PC or to alter or monitor a program already held in the PC. There are dedicated programming devices, such as Programming Consoles, and there are non-dedicated devices, such as a host computer . PROGRAM mode A mode of operation that allows for inputting and debugging [...]

Glossary 21 1 right-hand instruction Another term for terminal instruction. rightmost (bit/word) The lowest numbered bits of a group of bits, generally of an entire word, or the lowest numbered words of a group of words. These bits/words are often called least significant bits/words. RUN mode The operating mode used by the PC for normal control ope[...]

Glossary 212 SV Short for set value. switching capacity The voltage/current that a relay can switch on and of f. syntax error An error in the way in which a program is written. Syntax errors can include ‘spelling’ mistakes (i.e., a function code that does not exit), mistakes in speci- fying operands within acceptable parameters (e.g., specifyin[...]

Glossary 213 Wired Slave Rack A Slave Rack connected through a Wired Remote I/O Slave Unit. word A unit of storage in memory that consists of 16 bits. All data areas consists of words. Some data areas can be accessed by words; others, by either words or bits. word address The location in memory where a word of data is stored. A word address must sp[...]

215 Index Numbers 16−TO−4 ENCODER − DMPX(77). See instruction set 4−TO−16 DECODER − MLPX(76). See instruction set A ADD(30). See instruction set Always ON/OFF flags. See data areas Analog Timer Unit. See instruction set AND. See instruction set AND LD. See instruction set AND LO AD. See instruction set AND NOT . See instruction set AND [...]

Index 216 reading and clearing messages, 162 SR area flags, 164 F F actory Intelligent T erminal. See Peripheral Devices First Cycle Flag. See instruction set FIT . See Peripheral Devices flags execution affect, 69 usage, 10 Floppy Disk Interface Unit. See P eripheral Devices G GPC. See P eripheral Devices Graphic Programming Console. See P eripher[...]

Index 217 IR area. See data areas J JME(05). See instruction set JMP(04). See instruction set JUMP − JMP(04). See instruction set JUMP END − JME(05). See instruction set K KEEP(11). See instruction set L ladder diagram branching use of, 39 using IL(02) and ILC(03), 42 using JMP(04) and JME(05), 43 using TR bits, 40 converting to mnemonic code, [...]

Index 218 PROM W riter. See P eripheral Devices R RDM(60). See instruction set restore. See cassette tape operation RET(93). See instruction set RETURN − RET(93). See instruction set REVERSIBLE COUNTER − CNTR(12). See instruc tion set REVERSIBLE DRUM COUNTER − RDM(60). See instruction set REVERSIBLE SHIFT REGISTER − SFTR(84). See instruc[...]