Renesas M16C/6NK manual

RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C F AMIL Y / M16C/60 SERIES 16 Rev. 2.00 Revision date: Nov. 28, 2005 Hardware Manual www.renesas.com Before using this material, please visit our website to verify that this is the most updated document available. REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM)[...]

Keep safety first in your circuit designs! Notes regarding these materials • Renesas T echnology Corporation puts the maximum effort into making semiconductor prod- ucts better and more reliable, but there is always the possibility that trouble may occur with them. T rouble with semiconductors may lead to personal injury , fire or property damage[...]

How to Use This Manual 1. Introduction This hardware manual provides detailed information on the M16C/6N Group (M16C/6NK, M16C/6NM) of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, used for bit function in each register are sho[...]

3. M16C Family Documents The following documents were prepared for the M16C family (1) . Document Contents Short Sheet Hardware overview Data Sheet Hardware overview and electrical characteristics Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, timing charts) Software Man[...]

A-1 T able of Contents SFR Page Reference ............................................................................................................ B -1 1. Overview .................................................................................................................... ........... 1 1.1 Applications ..................................[...]

A-2 7.2 Bus Control ................................................................................................................ ................................ 46 7.2.1 Address Bus .............................................................................................................. ......................... 46 7.2.2 Data Bus ........[...]

A-3 10.5.4 Interrupt Sequence ...................................................................................................... .................... 89 10.5.5 Interrupt Response T ime ................................................................................................. ................. 90 10.5.6 V ariation of IPL when Interrupt Re[...]

A-4 16. A/D Converter .............................................................................................................. .... 202 16.1 Mode Description .......................................................................................................... ......................... 206 16.1.1 One-shot Mode ............................[...]

A-5 20. Programmable I/O Ports ................................................................................................. 247 20.1 PDi Register .............................................................................................................. ............................. 248 20.2 Pi Register , PC14 Register .....................[...]

A-6 23.9 DMAC ...................................................................................................................... .............................. 349 23.9.1 Write to DMAE Bit in DMiCON Register .................................................................................... .... 349 23.10 T imers ..............................[...]

B-1 SFR Page Reference PM0 PM1 CM0 CM1 CSR AIER PRCR CM2 WDTS WDC RMAD0 RMAD1 CSE PLC0 PM2 SAR0 DAR0 TCR0 DM0CON SAR1 DAR1 TCR1 DM1CON Address Register Symbol Page The blank areas are reserved. 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 001 1h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h[...]

B-2 Address Register Symbol Page 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h[...]

B-3 Address Register Symbol Page The blank areas are reserved. 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 01 10h 0 111 h 01 12h 01 13h 01 14h 01 15h 01 16h 01 17h 01 18h 01 19h 01 1Ah 01 1Bh 01 1Ch 01 1Dh 01 1Eh 01 1Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch [...]

B-4 The blank areas are reserved. FMR1 FMR0 RMAD2 AIER2 RMAD3 Address Register Symbol Page 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 0[...]

B-5 C0MCTL0 C0MCTL1 C0MCTL2 C0MCTL3 C0MCTL4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 C0MCTL9 C0MCTL10 C0MCTL1 1 C0MCTL12 C0MCTL13 C0MCTL14 C0MCTL15 C0CTLR C0STR C0SSTR C0ICR C0IDR C0CONR C0RECR C0TECR C0TSR C1MCTL0 C1MCTL1 C1MCTL2 C1MCTL3 C1MCTL4 C1MCTL5 C1MCTL6 C1MCTL7 C1MCTL8 C1MCTL9 C1MCTL10 C1MCTL1 1 C1MCTL12 C1MCTL13 C1MCTL14 C1MCTL15 C1CTLR C1STR C1SS[...]

B-6 Address Register Symbol Page 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0290h 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029Ah 029Bh 029Ch 029Dh 029Eh 029Fh 02A0h 02A1h 02A2h 02A3h 02A4h 02A5h 02A6h 02A7h 02A8h 02A9h 02AAh 02ABh 02ACh 02ADh 02AEh 02AFh 02B0h 02B1h 02B2h 02B3h 02B4h[...]

B-7 Address Register Symbol Page The blank areas are reserved. 0300h 0301h 0302h 0303h 0304h 0305h 0306h 0307h 0308h 0309h 030Ah 030Bh 030Ch 030Dh 030Eh 030Fh 0310h 031 1h 0312h 0313h 0314h 0315h 0316h 0317h 0318h 0319h 031Ah 031Bh 031Ch 031Dh 031Eh 031Fh 0320h 0321h 0322h 0323h 0324h 0325h 0326h 0327h 0328h 0329h 032Ah 032Bh 032Ch 032Dh 032Eh 032F[...]

B-8 T ABSR CPSRF ONSF TRGSR UDF TA 0 TA 1 TA 2 TA 3 TA 4 TB0 TB1 TB2 T A0MR T A1MR T A2MR T A3MR T A4MR TB0MR TB1MR TB2MR TB2SC U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON DM0SL DM1SL CRCD CRCIN The blank areas are reserved. Address Register Symbol Page 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 0[...]

Rev.2.00 Nov 28, 2005 page 1 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev .2.00 Nov 28, 2005 Under development This document is under development and its contents are subject to change 1. Overview The M16C/6N Group (M16C/6NK, M16C/6NM) of single-chip microcomputers are built using the high-perf[...]

Rev.2.00 Nov 28, 2005 page 2 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. 1.2 Performance Outline Tables 1.1 and 1.2 list a performance outline of M16C/6N Group (M16C/6NK, M16C/6NM). Table 1.1 Performance Outline of M16C/6N Group (1[...]

Rev.2.00 Nov 28, 2005 page 3 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. Table 1.2 Performance Outline of M16C/6N Group (128-pin Version: M16C/6NM) Item Performance Normal-ver. T/V-ver. C P U Number of Basic Instructions 9 1 instru[...]

Rev.2.00 Nov 28, 2005 page 4 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. 1.3 Block Diagram Figure 1.1 shows a block diagram of M16C/6N Group (M16C/6NK, M16C/6NM). Figure 1.1 Block Diagram NOTES: 1: ROM size depends on microcomputer[...]

Rev.2.00 Nov 28, 2005 page 5 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. 1.4 Product List Table 1.3 lists the M16C/6N Group (M16C/6NK, M16C/6NM) products and Figure 1.2 shows the type numbers, memory sizes and packages. Table 1.3 P[...]

Rev.2.00 Nov 28, 2005 page 6 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. PIN CONFIGURATION (top view) Figure 1.3 Pin Configuration (Top View) (1) 1.5 Pin Configuration Figures 1.3 and 1.4 show the pin configuration (top view). Tabl[...]

Rev.2.00 Nov 28, 2005 page 7 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. Table 1.4 Pin Characteristics for 100-Pin Package (1) Pin No. Control Port Interrupt Timer Pin UART Pin Analog CAN Module Bus Control Pin Pin Pin Pin Pin (1) [...]

Rev.2.00 Nov 28, 2005 page 8 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. Pin No. Control Port Interrupt Timer Pin UART Pin Analog CAN Module Bus Control Pin Pin Pin Pin Pin (1) 51 P4_1 A17 52 P4_0 A16 53 P3_7 A15 54 P3_6 A14 55 P3_[...]

Rev.2.00 Nov 28, 2005 page 9 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. PIN CONFIGURATION (top view) Figure 1.4 Pin Configuration (Top View) (2) 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 [...]

Rev.2.00 Nov 28, 2005 page 10 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. Table 1.6 Pin Characteristics for 128-Pin Package (1) Pin No. Control Port Interrupt Timer Pin UART Pin Analog CAN Module Bus Control Pin Pin Pin Pin Pin (1)[...]

Rev.2.00 Nov 28, 2005 page 11 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. Pin No. Control Port Interrupt Timer Pin UART Pin Analog CAN Module Bus Control Pin Pin Pin Pin Pin (1) 51 P5_6 ALE 52 P5_5 ___________ HOLD 53 P5_4 ________[...]

Rev.2.00 Nov 28, 2005 page 12 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. Pin No. Control Port Interrupt Timer Pin UART Pin Analog CAN Module Bus Control Pin Pin Pin Pin Pin (1) 101 P1_2 D10 102 P1_1 D9 103 P1_0 D8 104 P0_7 AN0_7 D[...]

Rev.2.00 Nov 28, 2005 page 13 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. 1.6 Pin Description Tables 1.9 to 1.11 list the pin descriptions. Table 1.9 Pin Description (100-pin and 128-pin Versions) (1) I I I I I I/O I/O O I/O I/O O [...]

Rev.2.00 Nov 28, 2005 page 14 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. Table 1.10 Pin Description (100-pin and 128-pin Versions) (2) I O I O O O I I I I/O I I I O I O I/O I I O O O I/O I/O I I I I/O I O I O XIN XOUT XCIN XCOUT B[...]

Rev.2.00 Nov 28, 2005 page 15 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. Table 1.11 Pin Description (100-pin and 128-pin Versions) (3) 8-bit I/O ports in CMOS, having a direction register to select an input or output. Each pin is [...]

Rev.2.00 Nov 28, 2005 page 16 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 2. Central Processing Unit (CPU) Under development This document is under development and its contents are subject to change. Figure 2.1 CPU Registers 2.1 Data Registers (R0, R1, R2, and R3) The R0 register consists of 16 bits, and is used mainly for transfers a[...]

Rev.2.00 Nov 28, 2005 page 17 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 2. Central Processing Unit (CPU) Under development This document is under development and its contents are subject to change. 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) [...]

Rev.2.00 Nov 28, 2005 page 18 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 3. Memory Under development This document is under development and its contents are subject to change. 3. Memory Figure 3.1 shows a memory map of the M16C/6N Group (M16C/6NK, M16C/6NM). The address space extends the 1 Mbyte from address 00000h to FFFFFh. The int[...]

Rev.2.00 Nov 28, 2005 page 19 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. 4. Special Function Register (SFR) SFR (Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.16[...]

Rev.2.00 Nov 28, 2005 page 20 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.2 SFR Information (2) XXXXX000b XXXXX000b XXXXX000b XX00X000b XXXXX000b XXXXX000b XXXXX000b XX00X000b XX00X000b XXXXX000b XXXX[...]

Rev.2.00 Nov 28, 2005 page 21 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.3 SFR Information (3) X: Undefined 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 0[...]

Rev.2.00 Nov 28, 2005 page 22 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.4 SFR Information (4) X: Undefined 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 0[...]

Rev.2.00 Nov 28, 2005 page 23 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.5 SFR Information (5) X: Undefined 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 0[...]

Rev.2.00 Nov 28, 2005 page 24 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.6 SFR Information (6) X: Undefined NOTE: 1. The blank areas are reserved and cannot be accessed by users. 0140h 0141h 0142h 01[...]

Rev.2.00 Nov 28, 2005 page 25 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.7 SFR Information (7) X: Undefined NOTES: 1. These registers are included in the flash memory version. Cannot be accessed by u[...]

Rev.2.00 Nov 28, 2005 page 26 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.8 SFR Information (8) T imer B3, B4, B5 Count Start Flag T imer A1-1 Register T imer A2-1 Register T imer A4-1 Register Three-[...]

Rev.2.00 Nov 28, 2005 page 27 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. X: Undefined 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh 020Fh 0210h 021 1h 0212h 0213h [...]

Rev.2.00 Nov 28, 2005 page 28 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. X: Undefined NOTE: 1. The blank areas are reserved and cannot be accessed by users. XXh XXh XXh XXh 00h 00h XXh XXh XXh XXh XXh XXh XX[...]

Rev.2.00 Nov 28, 2005 page 29 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.11 SFR Information (11) X: Undefined 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh[...]

Rev.2.00 Nov 28, 2005 page 30 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.12 SFR Information (12) X: Undefined 02C0h 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02CBh 02CCh 02CDh 02CEh[...]

Rev.2.00 Nov 28, 2005 page 31 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.13 SFR Information (13) X: Undefined 0300h 0301h 0302h 0303h 0304h 0305h 0306h 0307h 0308h 0309h 030Ah 030Bh 030Ch 030Dh 030Eh[...]

Rev.2.00 Nov 28, 2005 page 32 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.14 SFR Information (14) X: Undefined NOTE: 1. The blank areas are reserved and cannot be accessed by users. 0340h 0341h 0342h [...]

Rev.2.00 Nov 28, 2005 page 33 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. X: Undefined NOTES: 1. The TA2P to TA4P bits in the UDF register are set to "0" after reset. However, the contents in these [...]

Rev.2.00 Nov 28, 2005 page 34 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03[...]

Rev.2.00 Nov 28, 2005 page 35 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 5. Reset Under development This document is under development and its contents are subject to change. 5. Reset Hardware reset, software reset, watchdog timer reset and oscillation stop detection reset are available to reset the microcomputer. 5.1 Hardware Reset [...]

Rev.2.00 Nov 28, 2005 page 36 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 5. Reset Under development This document is under development and its contents are subject to change. Figure 5.2 Reset Sequence ____________ Table 5.1 Pin Status When RESET Pin Level is “ L ” td(P-R) More than 20 cycles are needed BCLK Address Address s XIN [...]

Rev.2.00 Nov 28, 2005 page 37 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 5. Reset Under development This document is under development and its contents are subject to change. Figure 5.3 CPU Register Status After Reset 0000h 0000h 0000h b15 b0 Static Base Register (SB) User Stack Pointer (USP) Interrupt Stack Pointer (ISP) b19 00000h [...]

Rev.2.00 Nov 28, 2005 page 38 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode Under development This document is under development and its contents are subject to change. 6.1 Types of Processor Mode Three processor modes are available to choose from: single-chip mode, memory expansion mode, and microprocessor mode. (Not [...]

Rev.2.00 Nov 28, 2005 page 39 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode Under development This document is under development and its contents are subject to change. 6.2 Setting Processor Modes Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register. Table 6.2 shows the processor m[...]

Rev.2.00 Nov 28, 2005 page 40 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode Under development This document is under development and its contents are subject to change. Figure 6.1 PM0 Register NOTES: 1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable). 2. The PM01 t[...]

Rev.2.00 Nov 28, 2005 page 41 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode Under development This document is under development and its contents are subject to change. Figure 6.2 PM1 Register Symbol Address After reset PM1 0005h 00001000b PM17 PM13 PM12 PM10 PM11 - (b6-b4) CS2 Area Switch Bit (Data Block Enable Bit) ([...]

Rev.2.00 Nov 28, 2005 page 42 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode Under development This document is under development and its contents are subject to change. Figure 6.3 Memory Map in Single-chip Mode Single-chip mode SFR Internal RAM Can not use Internal ROM Capacity 16 Kbytes 20 Kbytes 31 Kbytes Address XXX[...]

Rev.2.00 Nov 28, 2005 page 43 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode Under development This document is under development and its contents are subject to change. NOTES: 1. If the PM13 bit in the PM1 register is set to "0", 192 Kbytes of the internal ROM can be used. 2. Not available memory expansion an[...]

Rev.2.00 Nov 28, 2005 page 44 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode Under development This document is under development and its contents are subject to change. XXXXXh 04000h SFR Internal RAM Reserved area Reserved area Internal ROM Reserved area External area SFR Internal RAM CS3 (16 Kbytes) Reserved area Exte[...]

Rev.2.00 Nov 28, 2005 page 45 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change. During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform data _______ _______ input/output to and from external devices.[...]

Rev.2.00 Nov 28, 2005 page 46 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change. Figure 7.1 CSR Register 7.2 Bus Control The following describes the signals needed for accessing external devices and the functionality of software wait. 7.2.2 Da[...]

Rev.2.00 Nov 28, 2005 page 47 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change. ______ Figure 7.2 Example of Address Bus and CSi Signal Output NOTE: 1. These examples show the address bus and chip select signal when accessing areas in two suc[...]

Rev.2.00 Nov 28, 2005 page 48 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change. _____ ______ ________ Table 7.4 Operation of RD, WR and BHE Signals _____ ________ _________ Table 7.3 Operation of RD, WRL and WRH Signals 7.2.4 Read and Write S[...]

Rev.2.00 Nov 28, 2005 page 49 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change. ________ Figure 7.4 Example in which Wait State was Inserted into Read Cycle by RDY Signal BCLK RD CSi (i=0 to 3) RDY tsu(RDY - BCLK) BCLK RD CSi (i=0 to 3) tsu(R[...]

Rev.2.00 Nov 28, 2005 page 50 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change. __________ HOLD > DMAC > CPU __________ 7.2.7 HOLD Signal This signal is used to transfer control of the bus from CPU or DMAC to an external circuit. When t[...]

Rev.2.00 Nov 28, 2005 page 51 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change. Table 7.6 Pin Functions for Each Processor Mode Processor Mode Memory Expansion Mode or Microprocessor Mode Memory Expansion Mode PM05 to PM04 Bits 00b (separate [...]

Rev.2.00 Nov 28, 2005 page 52 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change. 7.2.10 Software Wait Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits in the CSR register, and the CSE regist[...]

Rev.2.00 Nov 28, 2005 page 53 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change. Table 7.8 Software Wait Related Bits and Bus Cycles Area Bus Mode SFR Internal ROM, RAM External Area - - - - Separate Bus Multiplexed Bus (2) PM1 Register PM17 B[...]

Rev.2.00 Nov 28, 2005 page 54 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change. Figure 7.7 Typical Bus Timings Using Software Wait (1) NOTE: 1. These example timing charts indicate bus cycle length. After this bus cycle sometimes come read an[...]

Rev.2.00 Nov 28, 2005 page 55 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change. Figure 7.8 Typical Bus Timings Using Software Wait (2) Address Output Input Address BCLK CS Write signal Read signal Data bus Address bus (1) Separate bus, 3-wait[...]

Rev.2.00 Nov 28, 2005 page 56 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 8. Clock Generating Circuit 8.1 Types of Clock Generating Circuit Four circuits are incorporated to generate the system clock signal: • Mai[...]

Rev.2.00 Nov 28, 2005 page 57 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 8.1 Clock Generating Circuit 1/16 CLKOUT CM01-CM00=00b PM01-PM00=00b, CM01-CM00=01b PM01-PM00=00b, CM01-CM00=10b PM01-PM00=00b, CM01-C[...]

Rev.2.00 Nov 28, 2005 page 58 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 8.2 CM0 Register System Clock Control Register 0 (1) NOTES: 1. Write to this register after setting the PRC0 bit in the PRCR register [...]

Rev.2.00 Nov 28, 2005 page 59 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 8.3 CM1 Register RW RW RW RW RW RW RW Bit Name Function Bit Symbol CM10 CM15 CM16 CM17 CM11 - (b4-b2) All Clock Stop Control Bit (2) ([...]

Rev.2.00 Nov 28, 2005 page 60 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 8.4 CM2 Register Oscillation Stop Detection Register (1) Symbol Address After Reset CM2 000Ch 0X000000b (2) Function b7 b6 b5 b4 b3 b2[...]

Rev.2.00 Nov 28, 2005 page 61 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 8.5 PCLKR Register NOTES: 1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable). 2[...]

Rev.2.00 Nov 28, 2005 page 62 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Symbol Address After Reset PM2 001Eh XXX00000b Processor Mode Register 2 (1) b7 b6 b5 b4 b3 b2 b1 b0 00 0 Specifying Wait when Accessing SFR [...]

Rev.2.00 Nov 28, 2005 page 63 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 8.8 PLC0 Register PLC07 Function PLL Control Register 0 (1) Operation Enable Bit (3) 0 : PLL Off 1 : PLL On Bit Name Bit Symbol Symbol[...]

Rev.2.00 Nov 28, 2005 page 64 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. The following describes the clocks generated by the clock generating circuit. 8.1.1 Main Clock The main clock is generated by the main clock [...]

Rev.2.00 Nov 28, 2005 page 65 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 8.1.2 Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as[...]

Rev.2.00 Nov 28, 2005 page 66 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 8.1.3 On-chip Oscillator Clock This clock, approximately 1 MHz, is supplied by a on-chip oscillator. This clock is used as the clock source f[...]

Rev.2.00 Nov 28, 2005 page 67 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 8.11 Procedure to Use PLL Clock as CPU Clock Source Set the PLC02 to PLC00 bits (multiplying factor). (When PLL clock > 16 MHz) Set[...]

Rev.2.00 Nov 28, 2005 page 68 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 8.2 CPU Clock and Peripheral Function Clock Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the perip[...]

Rev.2.00 Nov 28, 2005 page 69 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 8.4 Power Control Normal operation mode, wait mode and stop mode are provided as the power consumption control. All mode states, except wait [...]

Rev.2.00 Nov 28, 2005 page 70 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 8.4.1.6 On-chip Oscillator Mode The on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on-chip osci[...]

Rev.2.00 Nov 28, 2005 page 71 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 8.4.2 Wait Mode In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the watchdog timer. However[...]

Rev.2.00 Nov 28, 2005 page 72 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Interrupt CM02 Bit = 0 CM02 Bit = 1 _______ NMI Interrupt Can be used Can be used Serial Interface Interrupt Can be used when operating with [...]

Rev.2.00 Nov 28, 2005 page 73 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 8.4.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the[...]

Rev.2.00 Nov 28, 2005 page 74 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 8.4.3.3 Exiting Stop Mode _______ Stop mode is exited by a hardware reset, NMI interrupt or peripheral function interrupt. _______ When the h[...]

Rev.2.00 Nov 28, 2005 page 75 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 8.12 State Transition to Stop Mode and Wait Mode Stop Mode Reset Normal Mode PLL Operation Mode High-Speed Mode, Medium-Speed Mode Med[...]

Rev.2.00 Nov 28, 2005 page 76 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 8.13 State Transition in Normal Operation Mode CPU clock : f(PLL) CM07 = 0 CM06 = 0 CM17 = 0 CM16 = 0 PLL operation mode PLL operation[...]

Rev.2.00 Nov 28, 2005 page 77 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Table 8.8 Allowed Transition and Setting (9) State after transition High-Speed Mode, Low-Speed Low Power PLL Operation On-chip Oscillator On-[...]

Rev.2.00 Nov 28, 2005 page 78 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 8.5 Oscillation Stop and Re-oscillation Detection Function The oscillation stop and re-oscillation detection function is such that main clock[...]

Rev.2.00 Nov 28, 2005 page 79 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 8.5.3 How to Use Oscillation Stop and Re-oscillation Detection Function • The oscillation stop, re-oscillation detection interrupt shares t[...]

Rev.2.00 Nov 28, 2005 page 80 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 9. Protection Under development This document is under development and its contents are subject to change. 9. Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Fi[...]

Rev.2.00 Nov 28, 2005 page 81 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. Figure 10.1 Interrupts • Maskable Interrupt: A n interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt prior[...]

Rev.2.00 Nov 28, 2005 page 82 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. 10.2 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. 10.2.1 Undefined[...]

Rev.2.00 Nov 28, 2005 page 83 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. 10.3 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts. 10.3.1 Special Interr[...]

Rev.2.00 Nov 28, 2005 page 84 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. Figure 10.2 Interrupt Vector 10.4.1 Fixed Vector Tables The fixed vector tables are allocated to the addresses from FFFDCh to FFFFFh. Table 10.1 lists the [...]

Rev.2.00 Nov 28, 2005 page 85 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. Table 10.2 Relocatable Vector Tables 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 to 63 BRK Instruction (2) CAN[...]

Rev.2.00 Nov 28, 2005 page 86 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. 10.5 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted.[...]

Rev.2.00 Nov 28, 2005 page 87 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. Figure 10.4 Interrupt Control Registers (2) 0044h 0048h 0049h 005Dh to 005Fh 0057h 0058h 005Bh Interrupt Control Register (1) INT3IC (2) C1RECIC/S4IC/INT5I[...]

Rev.2.00 Nov 28, 2005 page 88 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. 10.5.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “ 1 ” (enabled) enables the maskable interrupt. Setting the [...]

Rev.2.00 Nov 28, 2005 page 89 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. 10.5.4 Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt[...]

Rev.2.00 Nov 28, 2005 page 90 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. Figure 10.6 Interrupt response time 10.5.6 Variation of IPL when Interrupt Request is Accepted When a maskable interrupt request is accepted, the interrupt[...]

Rev.2.00 Nov 28, 2005 page 91 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. 10.5.7 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 [...]

Rev.2.00 Nov 28, 2005 page 92 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. 10.5.8 Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are r[...]

Rev.2.00 Nov 28, 2005 page 93 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. Figure 10.10 Interrupts Priority Select Circuit Timer B2 Timer B0, SI/O6 (2) Timer A3, INT6 (2) Timer A1 Timer B1, INT8 (2) Timer A4 DMA1 DMA0 CAN1 Success[...]

Rev.2.00 Nov 28, 2005 page 94 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. ______ 10.6 INT Interrupt _______ INTi interrupt (i = 0 to 8) (1) is triggered by the edges of external inputs. The edge polarity is selected using the IFS[...]

Rev.2.00 Nov 28, 2005 page 95 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. Figure 10.11 IFSR0 Register NOTES: 1. When the IFSR16 bit in the IFSR1 register = 0, CAN1 successful transmission and SI/O3 share the vector and interrupt [...]

Rev.2.00 Nov 28, 2005 page 96 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. Figure 10.12 IFSR1 Register Interrupt Request Cause Select Register 1 RW Symbol Address After Reset IFSR1 01DFh 00h RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 [...]

Rev.2.00 Nov 28, 2005 page 97 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. Figure 10.13 IFSR2 Register Interrupt Request Cause Select Register 2 RW Symbol Address After Reset IFSR2 01CFh X0000000b RW RW RW RW RW RW RW - b7 b6 b5 b[...]

Rev.2.00 Nov 28, 2005 page 98 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. ______ 10.7 NMI Interrupt _______ _______ ______ An NMI interrupt request is generated when input on the NMI pin changes state from high to low. The NMI in[...]

Rev.2.00 Nov 28, 2005 page 99 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. 10.10 Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the ad- dress indicated by th[...]

Rev.2.00 Nov 28, 2005 page 100 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. Figure 10.16 AIER Register, AIER2 Register and RMAD0 to RMAD3 Registers RW - Address Match Interrupt Enable Register Address Match Interrupt 0 Enable Bit [...]

Rev.2.00 Nov 28, 2005 page 101 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1 1. Watchdog T imer Under development This document is under development and its contents are subject to change. 11. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog t[...]

Rev.2.00 Nov 28, 2005 page 102 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1 1. Watchdog T imer Under development This document is under development and its contents are subject to change. Figure 11.2 WDC Register and WDTS Register 11.1 Count Source Protective Mode In this mode, a on-chip oscillator clock is used for the watchdog time[...]

Rev.2.00 Nov 28, 2005 page 103 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change. 12. DMAC The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA[...]

Rev.2.00 Nov 28, 2005 page 104 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change. Item Specification No. of Channels 2 (cycle steal method) Transfer Memory Space • From any address in the 1-Mbyte space to a fixed address • From a fixed a[...]

Rev.2.00 Nov 28, 2005 page 105 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change. Figure 12.2 DM0SL Register DMA0 Request Cause Select Register Symbol Address After Reset DM0SL 03B8h 00h DSEL0 DSEL1 DSEL2 DSEL3 DSR DMS - (b5-b4) Function Bit[...]

Rev.2.00 Nov 28, 2005 page 106 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change. Figure 12.3 DM1SL Register, DM0CON and DM1CON Registers DMA1 Request Cause Select Register Symbol Address After Reset DM1SL 03BAh 00h DSEL0 DSEL1 DSEL2 DSEL3 D[...]

Rev.2.00 Nov 28, 2005 page 107 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change. Figure 12.4 SAR0 and SAR1 Registers, DAR0 and DAR1 Registers, TCR0 and TCR1 Registers Symbol After Reset SAR0 SAR1 Indeterminate Indeterminate Setting Range RW[...]

Rev.2.00 Nov 28, 2005 page 108 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change. 12.1 Transfer Cycle The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read a[...]

Rev.2.00 Nov 28, 2005 page 109 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change. Figure 12.5 Transfer Cycles for Source Read NOTE: 1. The same timing changes occur with the respective conditions at the destination as at the source. (1) When[...]

Rev.2.00 Nov 28, 2005 page 110 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change. 12.2 DMA Transfer Cycles Any combination of even or odd transfer read and write addresses is possible. Table 12.2 shows the number of DMA transfer cycles. Tabl[...]

Rev.2.00 Nov 28, 2005 page 111 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change. 12.3 DMA Enable When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0, 1) to “ 1 ” (enabled), the DMAC operates as follows: [...]

Rev.2.00 Nov 28, 2005 page 112 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change. 12.5 Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected active in the [...]

Rev.2.00 Nov 28, 2005 page 113 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. 13. Timers Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer A (five) and timer B ([...]

Rev.2.00 Nov 28, 2005 page 114 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Figure 13.2 Timer B Configuration f1 or f2 f8 f32 fC32 1 0 00 01 10 11 TCK1 TMOD1 to TMOD0 00: Timer mode 10: Pulse width / period measuring mode 01: Event [...]

Rev.2.00 Nov 28, 2005 page 115 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. 13.1 Timer A Figure 13.3 shows a block diagram of the timer A. Figures 13.4 to 13.6 show the timer A-related registers. The timer A supports the following f[...]

Rev.2.00 Nov 28, 2005 page 116 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Figure 13.4 TA0MR to TA4MR Registers and TA0 to TA4 Registers Timer Ai Mode Register (i = 0 to 4) TA0MR to TA4MR Bit Name Function Bit Symbol RW b7 b6 b5 b4[...]

Rev.2.00 Nov 28, 2005 page 117 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Figure 13.5 TABSR Register and UDF Register Timer A4 Up/Down Flag Timer A3 Up/Down Flag Timer A2 Up/Down Flag Timer A1 Up/Down Flag Timer A0 Up/Down Flag Ti[...]

Rev.2.00 Nov 28, 2005 page 118 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Figure 13.6 ONSF Register, TRGSR Register and CPSRF Register One-Shot Start Flag Symbol Address ONSF 0382h Timer A0 One-Shot Start Flag Timer A1 One-Shot St[...]

Rev.2.00 Nov 28, 2005 page 119 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Item Specification Count Source f1, f2, f8, f32, fC32 Count Operation • Down-count • When the timer underflows, it reloads the reload register contents [...]

Rev.2.00 Nov 28, 2005 page 120 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Item Specification Count Source • External signals input to TAiIN pin (effective edge can be selected in program) • Timer B2 overflows or underflows, Ti[...]

Rev.2.00 Nov 28, 2005 page 121 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Figure 13.8 TA0MR to TA4MR Registers in Event Counter Mode (when not using two-phase pulse signal processing) Symbol Address After Reset TA0MR to TA4MR 0396[...]

Rev.2.00 Nov 28, 2005 page 122 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Item Specification Count Source • Two-phase pulse signals input to TAiIN or TAiOUT pins Count Operation • Up-count or down-count can be selected by two-[...]

Rev.2.00 Nov 28, 2005 page 123 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Figure 13.9 TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase pulse signal processing with timer A2, A3 or A4) Timer Ai Mode Register (i [...]

Rev.2.00 Nov 28, 2005 page 124 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. 13.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value to “ 0 ” by Z-phase (counter initia[...]

Rev.2.00 Nov 28, 2005 page 125 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Item Specification Count Source f1, f2, f8, f32, fC32 Count Operation • Down-count • When the counter reaches 0000h , it stops counting after reloading [...]

Rev.2.00 Nov 28, 2005 page 126 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Bit Name Symbol TA0MR to TA4MR Function Bit Symbol b7 b6 b5 b4 b3 b2 b1 b0 Operation Mode Select Bit 1 0 : One-shot timer mode b1 b0 TMOD1 TMOD0 MR0 Pulse O[...]

Rev.2.00 Nov 28, 2005 page 127 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. 13.1.4 Pulse Width Modulation (PWM) Mode In pulse width modulation mode, the timer outputs pulses of a given width in succession. The counter functions as e[...]

Rev.2.00 Nov 28, 2005 page 128 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Figure 13.12 TA0MR to TA4MR Registers in Pulse Width Modulation Mode Bit Name Timer Ai Mode Register (i = 0 to 4) Function Bit Symbol b7 b6 b5 b4 b3 b2 b1 b[...]

Rev.2.00 Nov 28, 2005 page 129 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Figure 13.13 Example of 16-bit Pulse Width Modulator Operation 1 / fi ✕ (2 — 1) 16 Count source Input signal to TAiIN pin PWM pulse output from TAiOUT p[...]

Rev.2.00 Nov 28, 2005 page 130 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. 13.2 Timer B Figure 13.15 shows a block diagram of the timer B. Figures 13.16 and 13.17 show the timer B-related registers. Timer B supports the following t[...]

Rev.2.00 Nov 28, 2005 page 131 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Figure 13.16 TB0MR to TB5MR Registers and TB0 to TB5 Registers Timer Bi Mode Register (i = 0 to 5) Bit Name Function Bit Symbol RW b7 b6 b5 b4 b3 b2 b1 b0 0[...]

Rev.2.00 Nov 28, 2005 page 132 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Figure 13.17 TABSR Register, TBSR Register and CPSRF Register Symbol Address After Reset TABSR 0380h 00h Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Bit Name B[...]

Rev.2.00 Nov 28, 2005 page 133 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Item Specification Count Source f1, f2, f8, f32, fC32 Count Operation • Down-count • W hen the timer underflows, it reloads the reload register contents[...]

Rev.2.00 Nov 28, 2005 page 134 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Item Specification Count Source • E xternal signals input to TBiIN pin (effective edge can be selected in program) • Timer Bj overflow or underflow Coun[...]

Rev.2.00 Nov 28, 2005 page 135 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Item Specification Count Source f1, f2, f8, f32, fC32 Count Operation • Up-count • Counter value is transferred to reload register at an effective edge [...]

Rev.2.00 Nov 28, 2005 page 136 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Figure 13.20 TB0MR to TB5MR Registers in Pulse Period and Pulse Width Measurement Mode Timer Bi Mode Register (i = 0 to 5) Bit Name Bit Symbol RW b7 b6 b5 b[...]

Rev.2.00 Nov 28, 2005 page 137 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Figure 13.22 Operation Timing When Measuring Pulse Width Figure 13.21 Operation Timing When Measuring Pulse Period Count source Measurement pulse TBiS bit I[...]

Rev.2.00 Nov 28, 2005 page 138 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. 14. Three-Phase Motor Control Timer Function Timers A1, A2, A4 and B2 can be used to output three-phase motor drive wavefo[...]

Rev.2.00 Nov 28, 2005 page 139 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 14.1 Three-Phase Motor Control Timer Function Block Diagram 1/2 DUB1 bit DQ T DQ T DQ T DQ T TQ TQ Trigger Trigger [...]

Rev.2.00 Nov 28, 2005 page 140 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 14.2 INVC0 Register NOTES: 1. Set the INVC0 register after the PRC1 bit in the PRCR register is set to "1"[...]

Rev.2.00 Nov 28, 2005 page 141 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 14.3 INVC1 Register INV10 INV1 1 INV12 INV13 INV15 T A1 1, T A21 and T A41 Registers INV00 and INV01 Bit Not used U[...]

Rev.2.00 Nov 28, 2005 page 142 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 14.4 IDB0 and IDB1 Registers and DTT Register Three-Phase Output Buffer Register i (i = 0, 1) (1) Symbol Address Af[...]

Rev.2.00 Nov 28, 2005 page 143 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 14.5 TA1, TA2, TA4, TA11, TA21 and TA41 Registers, and TB2 Register T imer Ai, Ai-1 Register (i = 1, 2, 4) (1) (2) [...]

Rev.2.00 Nov 28, 2005 page 144 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 14.6 ICTB2 Register and TB2SC Register T imer B2 Interrupt Occurrence Frequency Set Counter (1) (2) (3) Symbol Addr[...]

Rev.2.00 Nov 28, 2005 page 145 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 14.7 TRGSR Register and TRBSR Register T rigger Select Register Symbol Address After Reset TRGSR 0383h 00h b7 b6 b5[...]

Rev.2.00 Nov 28, 2005 page 146 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 14.8 TA1MR, TA2MR and TA4MR Registers, and TB2MR Register T imer Ai Mode Register (i = 1, 2, 4) Symbol Address Afte[...]

Rev.2.00 Nov 28, 2005 page 147 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 14.9 Triangular Wave Modulation Operation The three-phase motor control timer function is enabled by setting the IN[...]

Rev.2.00 Nov 28, 2005 page 148 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 14.10 Sawtooth Wave Modulation Operation Timer B2 U-Phase Sawtooth Wave Signal Wave U-Phase Output Signal (1) U-Pha[...]

Rev.2.00 Nov 28, 2005 page 149 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15. Serial Interface Serial interface is configured with 7 channels: UART0 to UART2 and SI/O3 to SI/O6 (1) . NOTE: 1. 100-pin version supports 5 ch[...]

Rev.2.00 Nov 28, 2005 page 150 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.1 UART0 Block Diagram RXD0 1 / (n0+1) 1/16 1/16 1/2 U0BRG register Clock synchronous type (when internal clock is selected) Clock synchro[...]

Rev.2.00 Nov 28, 2005 page 151 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.3 UART2 Block Diagram RXD2 1 / (n2+1) 1/16 1/16 1/2 U2BRG register Clock synchronous type (when internal clock is selected) Clock synchro[...]

Rev.2.00 Nov 28, 2005 page 152 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.4 UARTi Transmit/Receive Unit SP SP PAR 2SP 1SP UART TXDi D8 D7 D6 D5 D4 D3 D2 D1 D0 2SP 1SP UART RXDi D7 D6 D5 D4 D3 D2 D1 D0 D8 0 00000[...]

Rev.2.00 Nov 28, 2005 page 153 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.5 U0TB to U2TB Registers, U0RB to U2RB Registers, and U0BRG to U2BRG Registers Nothing is assigned When write, set to "0". When[...]

Rev.2.00 Nov 28, 2005 page 154 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.6 U0MR to U2MR Registers and U0C0 to U2C0 Registers Function UARTi Transmit/Receive Control Register 0 (i = 0 to 2) Bit Name Bit Symbol S[...]

Rev.2.00 Nov 28, 2005 page 155 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.7 U0C1, U1C1 Registers and U2C1 Register b7 b6 b5 b4 b3 b2 b1 b0 Function UARTj Transmit/Receive Control Register 1 (j = 0, 1) Bit Name B[...]

Rev.2.00 Nov 28, 2005 page 156 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.8 UCON Register and U0SMR to U2SMR Registers b7 b6 b5 b4 b3 b2 b1 b0 Function UART Transmit/Receive Control Register 2 Bit Name Bit Symbo[...]

Rev.2.00 Nov 28, 2005 page 157 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.9 U0SMR2 to U2SMR2 Registers and U0SMR3 to U2SMR3 Registers b7 b6 b5 b4 b3 b2 b1 b0 Function UARTi Special Mode Register 2 (i = 0 to 2) B[...]

Rev.2.00 Nov 28, 2005 page 158 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.10 U0SMR4 to U2SMR4 Registers b7 b6 b5 b4 b3 b2 b1 b0 Function UARTi Special Mode Register 4 (i = 0 to 2) Bit Name Bit Symbol Symbol Addr[...]

Rev.2.00 Nov 28, 2005 page 159 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.1 Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 15.1 lists[...]

Rev.2.00 Nov 28, 2005 page 160 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Table 15.2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode Register Bit Function UiTB (1) 0 to 7 Set transmission data UiRB [...]

Rev.2.00 Nov 28, 2005 page 161 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Table 15.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 15.3 shows pin functions for the case where[...]

Rev.2.00 Nov 28, 2005 page 162 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.11 Transmit and Receive Operation (1) Example of Transmit Timing (when internal clock is selected) (2) Example of Receive Timing (when ex[...]

Rev.2.00 Nov 28, 2005 page 163 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.1.1 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in clock synchronous serial[...]

Rev.2.00 Nov 28, 2005 page 164 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.1.3 LSB First/MSB First Select Function Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format. Figure 15.13 shows [...]

Rev.2.00 Nov 28, 2005 page 165 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.1.5 Serial Data Logic Switching Function When the UiLCH bit in the UiC1 register (i = 0 to 2) = 1 (reverse), the data written to the UiTB regi[...]

Rev.2.00 Nov 28, 2005 page 166 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. _______ _______ 15.1.1.7 CTS/RTS Function _______ ________ ________ When the CTS function is used transmit and receive operation start when “ L ?[...]

Rev.2.00 Nov 28, 2005 page 167 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Item Specification Transfer Data Format • Character bit (transfer data): Selectable from 7, 8 or 9 bits • Start bit: 1 bit • Parity bit: Sele[...]

Rev.2.00 Nov 28, 2005 page 168 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Table 15.6 Registers to Be Used and Settings in UART Mode Register Bit Function UiTB 0 to 8 Set transmission data (1) UiRB 0 to 8 Reception data ca[...]

Rev.2.00 Nov 28, 2005 page 169 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Table 15.7 lists the functions of the input/output pins during UART mode. Table 15.8 lists the P6_4 pin functions during UART mode. Note that for a[...]

Rev.2.00 Nov 28, 2005 page 170 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. (1) Example of Transmit Timing when Transfer Data is 8-bit Long (parity enabled, one stop bit) (2) Example of Transmit Timing when Transfer Data is[...]

Rev.2.00 Nov 28, 2005 page 171 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. • Example of Receive Timing when Transfer Data is 8-bit Long (parity disabled, one stop bit) The above timing diagram applies to the case where t[...]

Rev.2.00 Nov 28, 2005 page 172 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.2.2 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in UART mode, follow the pr[...]

Rev.2.00 Nov 28, 2005 page 173 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.21 TXD and RXD I/O Polarity Inverse 15.1.2.4 Serial Data Logic Switching Function The data written to the UiTB register has its logic rev[...]

Rev.2.00 Nov 28, 2005 page 174 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. _______ _______ 15.1.2.6 CTS/RTS Function _______ ________ ________ When the CTS function is used transmit operation start when “ L ” is applie[...]

Rev.2.00 Nov 28, 2005 page 175 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.3 Special Mode 1 (I 2 C Mode) I 2 C mode is provided for use as a simplified I 2 C interface compatible mode. Table 15.10 lists the specificat[...]

Rev.2.00 Nov 28, 2005 page 176 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.23 I 2 C Mode Block Diagram CLK control Falling edge detection External clock Internal clock Start/stop condition detection interrupt req[...]

Rev.2.00 Nov 28, 2005 page 177 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Table 15.11 Registers to Be Used and Settings in I 2 C Mode Register Bit Function Master Slave UiTB (1) 0 to 7 Set transmission data UiRB (1) 0 to [...]

Rev.2.00 Nov 28, 2005 page 178 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. No acknowledgment detection (NACK) Rising edge of SCLi 9th bit Acknowledgment detection (ACK) Rising edge of SCLi 9th bit Rising edge of SCLi 9th b[...]

Rev.2.00 Nov 28, 2005 page 179 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.24 Transfer to UiRB Register and Interrupt Timing i = 0 to 2 This diagram applies to the case where the following condition is met. The C[...]

Rev.2.00 Nov 28, 2005 page 180 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.3.1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined. A start condition-detected inte[...]

Rev.2.00 Nov 28, 2005 page 181 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Table 15.13 STSPSEL Bit Functions Figure 15.26 STSPSEL Bit Functions 15.1.3.3 Arbitration Unmatching of the transmit data and SDAi pin input data i[...]

Rev.2.00 Nov 28, 2005 page 182 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.3.4 Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 15.24. The CSC bit in the UiSMR2 register [...]

Rev.2.00 Nov 28, 2005 page 183 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.3.7 ACK and NACK If the STSPSEL bit in the UiSMR4 register is set to “ 0 ” (start and stop conditions not generated) and the ACKC bit in t[...]

Rev.2.00 Nov 28, 2005 page 184 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.4 Special Mode 2 Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 15.14 l[...]

Rev.2.00 Nov 28, 2005 page 185 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.27 Serial Bus Communication Control Example (UART2) Microcomputer (Master) Microcomputer (Slave) Microcomputer (Slave) P1_3 P1_2 P7_2(CLK[...]

Rev.2.00 Nov 28, 2005 page 186 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Table 15.15 Registers to Be Used and Settings in Special Mode 2 Register Bit Function UiTB (1) 0 to 7 Set transmission data UiRB (1) 0 to 7 Recepti[...]

Rev.2.00 Nov 28, 2005 page 187 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.4.1 Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the Ui[...]

Rev.2.00 Nov 28, 2005 page 188 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.29 Transmission and Reception Timing (CKPH = 0) in Slave Mode (External Clock) Figure 15.30 Transmission and Reception Timing (CKPH = 1) [...]

Rev.2.00 Nov 28, 2005 page 189 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.5 Special Mode 3 (IE Mode) In this mode, one bit of IEBus is approximated with one byte of UART mode waveform. Table 15.16 lists the registers[...]

Rev.2.00 Nov 28, 2005 page 190 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.31 Bus Collision Detect Function-Related Bits (3) SSS Bit in UiSMR Register (transmit start condition select) Transmission enable conditi[...]

Rev.2.00 Nov 28, 2005 page 191 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Item Specification Transfer data format • Direct format • Inverse format Transfer clock • The CKDIR bit in the U2MR register = 0 (internal cl[...]

Rev.2.00 Nov 28, 2005 page 192 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Table 15.18 Registers to Be Used and Settings in SIM Mode Register Bit Function U2TB (1) 0 to 7 Set transmission data U2RB (1) 0 to 7 Reception dat[...]

Rev.2.00 Nov 28, 2005 page 193 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.32 Transmit and Receive Timing in SIM Mode The above timing diagram applies to the case where data is received in the direct format. STPS[...]

Rev.2.00 Nov 28, 2005 page 194 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.33 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up. Figure 15.33 SIM Interface Connection 15.1[...]

Rev.2.00 Nov 28, 2005 page 195 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.6.2 Format When direct format, set the PRY bit in the U2MR register to “ 1 ” , the UFORM bit in the U2C0 register to “ 0 ” and the U2L[...]

Rev.2.00 Nov 28, 2005 page 196 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.2 SI/Oi (i = 3 to 6) (1) SI/Oi is exclusive clock-synchronous serial I/Os. Figure 15.36 shows the block diagram of SI/Oi, and Figures 15.37 and [...]

Rev.2.00 Nov 28, 2005 page 197 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.37 S3C to S6C Registers, S3BRG to S6BRG Registers, and S3TRR to S6TRR Registers 0 0 : Selecting f1SIO or f2SIO 0 1 : Selecting f8SIO 1 0 [...]

Rev.2.00 Nov 28, 2005 page 198 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.38 S3456TRR Register 0 : During transmission/reception 1 : Transmission/reception completed S3TRF S4TRF S5TRF Symbol S3456TRR Address 01D[...]

Rev.2.00 Nov 28, 2005 page 199 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Item Specification Transfer Data Format Transfer data length: 8 bits Transfer clock • SMi6 bit in SiC register = 1 (internal clock) : fj/2(n+1) f[...]

Rev.2.00 Nov 28, 2005 page 200 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.2.1 SI/Oi Operation Timing Figure 15.39 shows the SI/Oi operation timing. Figure 15.39 SI/Oi Operation Timing 15.2.2 CLK Polarity Selection The [...]

Rev.2.00 Nov 28, 2005 page 201 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.2.3 Functions for Setting an SOUTi Initial Value If the SMi6 bit in the SiC register = 0 (external clock), the SOUTi pin output can be fixed hig[...]

Rev.2.00 Nov 28, 2005 page 202 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. Item Performance Method of A/D Conversion Successive approximation (capacitive coupling amplifier) Analog Input Voltage (1) 0V to AVCC (VCC) Operating[...]

Rev.2.00 Nov 28, 2005 page 203 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. Figure 16.1 A/D Converter Block Diagram ANEX0 ANEX1 OPA0=1 OPA1=1 ADGSEL1 to ADGSEL0=00b OPA1 to OPA0=11b =000b =001b =010b =011b =100b =101b =110b =1[...]

Rev.2.00 Nov 28, 2005 page 204 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. Figure 16.2 ADCON0 Register and ADCON1 Register CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 RW RW RW RW RW RW RW RW SCAN0 SCAN1 MD2 BITS VCUT OPA0 OPA1 CKS1 Fun[...]

Rev.2.00 Nov 28, 2005 page 205 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. Figure 16.3 ADCON2 Register, and AD0 to AD7 Registers NOTES: 1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will [...]

Rev.2.00 Nov 28, 2005 page 206 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. Item Specification Function T he CH2 to CH0 bits in the ADCON0 register, the ADGSEL1 to ADGSEL0 bits in the ADCON2 register and the OPA1 to OPA0 bits [...]

Rev.2.00 Nov 28, 2005 page 207 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. Figure 16.4 ADCON0 Register and ADCON1 Register in One-shot Mode CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 0 0 : One-shot mode (3) 0 : Software trigger 1 : AD[...]

Rev.2.00 Nov 28, 2005 page 208 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. 16.1.2 Repeat Mode In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 16.3 lists the specificat[...]

Rev.2.00 Nov 28, 2005 page 209 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. Figure 16.5 ADCON0 Register and ADCON1 Register in Repeat Mode CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 RW RW RW RW RW RW RW RW SCAN0 SCAN1 MD2 BITS VCUT OPA[...]

Rev.2.00 Nov 28, 2005 page 210 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. 16.1.3 Single Sweep Mode In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital code. Table 16.4 l[...]

Rev.2.00 Nov 28, 2005 page 211 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. Figure 16.6 ADCON0 Register and ADCON1 Register in Single Sweep Mode CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 1 0 : Single sweep mode 0 : Software trigger 1 [...]

Rev.2.00 Nov 28, 2005 page 212 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. 16.1.4 Repeat Sweep Mode 0 In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital code. Table 16.5 lists[...]

Rev.2.00 Nov 28, 2005 page 213 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. Figure 16.7 ADCON0 Register and ADCON1 Register in Repeat Sweep Mode 0 CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 1 1 : Repeat sweep mode 0 or Repeat sweep mod[...]

Rev.2.00 Nov 28, 2005 page 214 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. Item Specification Function The input voltages on all pins selected by the ADGSEL1 to ADGSEL0 bits in the ADCON2 register are A/D converted repeatedly[...]

Rev.2.00 Nov 28, 2005 page 215 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. Figure 16.8 ADCON0 Register and ADCON1 Register in Repeat Sweep Mode 1 CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 1 1 : Repeat sweep mode 0 or Repeat sweep mod[...]

Rev.2.00 Nov 28, 2005 page 216 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. 16.2 Function 16.2.1 Resolution Select Function The desired resolution can be selected using the BITS bit in the ADCON1 register. If the BITS bit is s[...]

Rev.2.00 Nov 28, 2005 page 217 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. 16.2.5 Current Consumption Reducing Function When not using the A/D converter, its resistor ladder and reference voltage input pin (VREF) can be separ[...]

Rev.2.00 Nov 28, 2005 page 218 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. R0 R (7.8 k Ω ) C (1.5 pF) VIN Microcomputer Sensor equivalent circuit VC Sampling time Sample and hold enabled: Sample and hold disabled: 3 φ AD 2[...]

Rev.2.00 Nov 28, 2005 page 219 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 17. D/A Converter Under development This document is under development and its contents are subject to change. 17. D/A Converter This is an 8-bit, R-2R type D/A converter. These are two independent D/A converters. D/A conversion is performed by writing to the D[...]

Rev.2.00 Nov 28, 2005 page 220 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 17. D/A Converter Under development This document is under development and its contents are subject to change. Figure 17.2 DACON Register, DA0 and DA1 Registers Figure 17.3 D/A Converter Equivalent Circuit D/A Control Register (1) Symbol Address After Reset Sym[...]

Rev.2.00 Nov 28, 2005 page 221 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 18. CRC Calculation Under development This document is under development and its contents are subject to change. 18. CRC Calculation The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses a generator polynomial of CR[...]

Rev.2.00 Nov 28, 2005 page 222 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 18. CRC Calculation Under development This document is under development and its contents are subject to change. Figure 18.3 CRC Calculation b15 b7 b15 1189h b7 b15 0A41h b0 b0 b0 b0 b0 CRCD register CRCIN register Two cycles later, the CRC code for "80h,&[...]

Rev.2.00 Nov 28, 2005 page 223 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19. CAN Module The CAN (Controller Area Network) module for the M16C/6N Group (M16C/6NK, M16C/6NM) of microcomputers is a communication controller implem[...]

Rev.2.00 Nov 28, 2005 page 224 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.1 CAN Module-Related Registers The CANi (i = 0, 1) module has the following registers. 19.1.1 CAN Message Box A CAN module is equipped with 16 slots ([...]

Rev.2.00 Nov 28, 2005 page 225 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.2 CANi Message Box (i = 0, 1) Table 19.1 shows the memory mapping of the CANi message box. It is possible to access to the message box in byte or word[...]

Rev.2.00 Nov 28, 2005 page 226 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. Figures 19.2 and 19.3 show the bit mapping in each slot in byte access and word access. The content of each slot remains unchanged unless transmission or[...]

Rev.2.00 Nov 28, 2005 page 227 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. Figure 19.4 Bit Mapping of Mask Registers in Byte Access 19.3 Acceptance Mask Registers Figures 19.4 and 19.5 show the CiGMR register (i = 0, 1), the CiL[...]

Rev.2.00 Nov 28, 2005 page 228 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.4 CAN SFR Registers Figures 19.6 to 19.11 show the CAN SFR registers. Figure 19.6 C0MCTLj and C1MCTLj Registers b7 b6 b5 b4 b3 b2 b1 b0 Bit Sy mbo l B[...]

Rev.2.00 Nov 28, 2005 page 229 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. Figure 19.7 C0CTLR and C1CTLR Registers Function Bit Sy mbol Reset CAN Module Reset Bit (1) Loop Bac k Mode Select Bit (2) LoopBack Message Ord er Select[...]

Rev.2.00 Nov 28, 2005 page 230 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. Figure 19.8 C0STR and C1STR Registers (b15) (b8) b7 b6 b5 b4 b3 b2 b1 b0 Reset State Flag Loop Back State Flag Message Order State Flag Basic CAN Mode St[...]

Rev.2.00 Nov 28, 2005 page 231 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. Figure 19.9 C0SSTR, C1SSTR Registers, C0ICR, C1ICR Registers, and C0IDR, C1IDR Registers (b15) (b8) b7 b0 b7 b0 Func tion Slot status bits Each bit corre[...]

Rev.2.00 Nov 28, 2005 page 232 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. Figure 19.10 C0CONR and C1CONR Registers b7 b6 b5 b4 b3 b2 b1 b0 0 : O ne time sampling 1 : Three times sampling 0 0 0 0 : Divide-by-1 of fCAN 0 0 0 1 : [...]

Rev.2.00 Nov 28, 2005 page 233 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. Figure 19.11 C0RECR, C1RECR Registers, C0TECR, C1TECR Registers, C0TSR, C1TSR Registers, and C0AFS, C1AFS Registers Reception error counting function The[...]

Rev.2.00 Nov 28, 2005 page 234 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.5 Operational Modes The CAN module has the following four operational modes. • CAN Reset/Initialization Mode • CAN Operation Mode • CAN Sleep Mo[...]

Rev.2.00 Nov 28, 2005 page 235 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.5.2 CAN Operation Mode The CAN operation mode is activated by setting the Reset bit in the CiCTLR register (i = 0, 1) to “ 0 ” . If the Reset bit [...]

Rev.2.00 Nov 28, 2005 page 236 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.5.5 Bus Off State The bus off state is entered according to the fault confinement rules of the CAN specification. When returning to the CAN operation [...]

Rev.2.00 Nov 28, 2005 page 237 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.6 Configuration CAN Module System Clock The M16C/6N Group (M16C/6NK, M16C/6NM) has a CAN module system clock select circuit. Configuration of the CAN [...]

Rev.2.00 Nov 28, 2005 page 238 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.8 Bit-rate Bit-rate depends on f1, the division value of the CAN module system clock, the division value of the baud rate prescaler, and the number of[...]

Rev.2.00 Nov 28, 2005 page 239 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. Figure 19.16 Correspondence of Mask Registers to Slots Figure 19.17 Acceptance Function When using the acceptance function, note the following points. (1[...]

Rev.2.00 Nov 28, 2005 page 240 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.10 Acceptance Filter Support Unit (ASU) The acceptance filter support unit has a function to judge valid/invalid of a received ID through table search[...]

Rev.2.00 Nov 28, 2005 page 241 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.11 Basic CAN Mode When the BasicCAN bit in the CiCTLR register (i = 0, 1) is set to “ 1 ” (Basic CAN mode enabled), slots 14 and 15 correspond to [...]

Rev.2.00 Nov 28, 2005 page 242 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.12 Return from Bus Off Function When the protocol controller enters bus off state, it is possible to make it forced return from bus off state by setti[...]

Rev.2.00 Nov 28, 2005 page 243 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.15 Reception and Transmission Table 19.3 shows configuration of CAN reception and transmission mode. Table 19.3 Configuration of CAN Reception and Tra[...]

Rev.2.00 Nov 28, 2005 page 244 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.15.1 Reception Figure 19.20 shows the behavior of the module when receiving two consecutive CAN messages, that fit into the slot of the shown CiMCTLj [...]

Rev.2.00 Nov 28, 2005 page 245 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.15.2 Transmission Figure 19.21 shows the timing of the transmit sequence. CTX TrmRe q bit TrmAc ti ve bit CANi Successful Transmission Interrupt TrmSt[...]

Rev.2.00 Nov 28, 2005 page 246 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.16 CAN Interrupt The CAN module provides the following CAN interrupts. • CANi Successful Reception Interrupt ( i = 0, 1) • CANi Successful Transmi[...]

Rev.2.00 Nov 28, 2005 page 247 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change. 20. Programmable I/O Ports The programmable input/output ports (hereafter referred to simply as I/O ports) consist of 87 lines P0 to P10 in t[...]

Rev.2.00 Nov 28, 2005 page 248 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change. 20.1 PDi Register (100-pin Version: i = 0 to 10, 128-pin Version: i = 0 to 13) Figure20.7 shows the PDi register. This register selects wheth[...]

Rev.2.00 Nov 28, 2005 page 249 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure20.1 I/O Ports (1) NOTES: 1. Symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed VCC. 2. P11 to P14 [...]

Rev.2.00 Nov 28, 2005 page 250 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure20.2 I/O Ports (2) "1" Output Data bus Direction register Port latch Pull-up selection (NOTE 1) Input to respective periphera[...]

Rev.2.00 Nov 28, 2005 page 251 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure20.3 I/O Ports (3) Data bus Pull-up selection Direction register Port latch Input to respective peripheral functions Switching between [...]

Rev.2.00 Nov 28, 2005 page 252 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Data bus Direction register Pull-up selection Port latch Analog input Input to respective peripheral functions (NOTE 1) D/A output enabled An[...]

Rev.2.00 Nov 28, 2005 page 253 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure20.5 I/O Ports (5) Figure20.6 I/O Pins fC Rf Rd Data bus Direction register Pull-up selection Port latch "1" Output Direction[...]

Rev.2.00 Nov 28, 2005 page 254 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure20.7 PD0 to PD13 Registers Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Port Pi Dire[...]

Rev.2.00 Nov 28, 2005 page 255 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure20.8 P0 to P13 Registers and PC14 Register Port P8 Register Bit name Bit symbol RW b7 b6 b5 b4 b3 b2 b1 b0 P8 03F0h Indeterminate Symbo[...]

Rev.2.00 Nov 28, 2005 page 256 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Pull-up Control Register 0 (1) Bit Name Bit Symbol RW b7 b6 b5 b4 b3 b2 b1 b0 PUR0 03FCh 00h Symbol Address After Reset NOTES: 1. During memo[...]

Rev.2.00 Nov 28, 2005 page 257 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure20.10 PUR3 Register Pull-up Control Register 3 (128-pin version) Bit Name Bit Symbol RW b7 b6 b5 b4 b3 b2 b1 b0 PUR3 03DFh 00h Symbol A[...]

Rev.2.00 Nov 28, 2005 page 258 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Table 20.2 Unassigned Pin Handling in Single-chip Mode Pin Name Connection Ports P0 to P7, P8_0 to P8_4, P8_6, P8_7, P9 to P14 (5) XOUT (4) _[...]

Rev.2.00 Nov 28, 2005 page 259 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure 20.12 Unassigned Pins Handling NOTES: 1. If the PM07 bit in the PM0 register is set to "1" (BCLK not output), connect this p[...]

Rev.2.00 Nov 28, 2005 page 260 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21. Flash Memory Version Aside from the built-in flash memory, the flash memory version microcomputer has the same functions as the masked ROM[...]

Rev.2.00 Nov 28, 2005 page 261 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.1 Memory Map The flash memory contains the user ROM area and a boot ROM area. The user ROM area has space to store the microcomputer operat[...]

Rev.2.00 Nov 28, 2005 page 262 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.1.1 Boot Mode The microcomputer enters boot mode when a hardware reset occurs while an “ H ” signal is applied to the CNVSS and P5_0 pi[...]

Rev.2.00 Nov 28, 2005 page 263 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 21.2 ROMCP Register Figure 21.3 Address for ID Code Stored ROM Code Protect Control Address (5) Symbol Address Value when Shipped ROMCP[...]

Rev.2.00 Nov 28, 2005 page 264 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Item EW0 Mode EW1 Mode Operation Mode • Single-chip mode Single-chip mode • Memory expansion mode (3) • Boot mode Space where Rewrite ?[...]

Rev.2.00 Nov 28, 2005 page 265 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.3.1 EW0 Mode The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “ 1 ” (CPU rewrite mode enabled[...]

Rev.2.00 Nov 28, 2005 page 266 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 21.4 FMR0 Register and FMR1 Register Flash Memory Control Register 0 Symbol Address After Reset FMR0 01B7h 00000001b b7 b6 b5 b4 b3 b2 [...]

Rev.2.00 Nov 28, 2005 page 267 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.3.3.1 FMR00 Bit This bit indicates the flash memory operating status. It is set to “ 0 ” while the program, block erase, erase all unlo[...]

Rev.2.00 Nov 28, 2005 page 268 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.3.3.7 FMR07 Bit This is a read-only bit indicating the auto erase operation status. The FMR07 bit is set to “ 1 ” when an erase error o[...]

Rev.2.00 Nov 28, 2005 page 269 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 21.6 Setting and Resetting of EW1 Mode Figure 21.5 Setting and Resetting of EW0 Mode Procedure to enter EW0 mode Set CM0, CM1, and PM1 [...]

Rev.2.00 Nov 28, 2005 page 270 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 21.7 Processing Before and After Low Power Dissipation Mode or On-chip Oscillator Low Power Dissipation Mode Transfer a low power dissi[...]

Rev.2.00 Nov 28, 2005 page 271 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.3.4 Precautions on CPU Rewrite Mode 21.3.4.1 Operating Speed Set the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 regi[...]

Rev.2.00 Nov 28, 2005 page 272 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.3.4.9 Writing Command and Data Write commands and data to even addresses in the user ROM area. 21.3.4.10 Wait Mode When entering wait mode,[...]

Rev.2.00 Nov 28, 2005 page 273 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.3.5 Software Commands Software commands are described below. The command code and data must be read and written in 16-bit unit, to and from[...]

Rev.2.00 Nov 28, 2005 page 274 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 21.8 Program Command 21.3.5.4 Program Command (40h) The program command writes 2-byte data to the flash memory. By writing “ xx40h ?[...]

Rev.2.00 Nov 28, 2005 page 275 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 21.9 Block Erase Command 21.3.5.5 Block Erase Command The block erase command erases each block. By writing “ xx20h ” in the first [...]

Rev.2.00 Nov 28, 2005 page 276 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.3.5.6 Erase All Unlocked Block The erase all unlocked block command erases all blocks except the block A. By writing “ xxA7h ” in the f[...]

Rev.2.00 Nov 28, 2005 page 277 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.3.5.8 Read Lock Bit Status Command (71h) The read lock bit status command reads the lock bit state of a specified block. By writing “ xx7[...]

Rev.2.00 Nov 28, 2005 page 278 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.3.6 Data Protect Function Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02 bit in th[...]

Rev.2.00 Nov 28, 2005 page 279 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Table 21.5 Status Register SR0 (D0) SR1 (D1) SR2 (D2) SR3 (D3) SR4 (D4) SR5 (D5) SR6 (D6) SR7 (D7) Reserved Reserved Reserved Reserved Program[...]

Rev.2.00 Nov 28, 2005 page 280 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. FRM00 Register (Status Register) Status Error Error Occurrence Conditions FMR07 bit FMR06 bit (SR5) (SR4) 1 1 Command • Command is written i[...]

Rev.2.00 Nov 28, 2005 page 281 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 21.12 Full Status Check and Handling Procedure for Each Error Full status check FMR06 =1 and FMR07=1? NO YES FMR07=0? YES NO FMR06=0? Y[...]

Rev.2.00 Nov 28, 2005 page 282 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.4 Standard Serial I/O Mode In standard serial I/O mode, the serial programmer supporting the M16C/6N Group (M16C/6NK, M16C/6NM) can be used[...]

Rev.2.00 Nov 28, 2005 page 283 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Table 21.7 Pin Functions for Standard Serial I/O Mode NOTES: ____________ 1. When using the standard serial I/O mode, It is necessary to input[...]

Rev.2.00 Nov 28, 2005 page 284 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 21.13 Pin Connections for Standard Serial I/O Mode (1) CNVSS RESET VSS VCC1 VCC2 TXD SCLK EPM CE RXD BUSY M16C/6N Group (M16C/6NK) (Fla[...]

Rev.2.00 Nov 28, 2005 page 285 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 21.14 Pin Connections for Standard Serial I/O Mode (2) 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 52 62 72 82 93 [...]

Rev.2.00 Nov 28, 2005 page 286 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.4.2 Example of Circuit Application in Standard Serial I/O Mode Figures 21.15 and 21.16 show example of circuit application in standard seri[...]

Rev.2.00 Nov 28, 2005 page 287 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.5 Parallel I/O Mode In parallel I/O mode, the user ROM area and the boot ROM area can be rewritten by a parallel programmer supporting the [...]

Rev.2.00 Nov 28, 2005 page 288 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.6 CAN I/O Mode In CAN I/O mode, the CAN programmer supporting the M16C/6N Group (M16C/6NK, M16C/6NM) can be used to rewrite the flash memor[...]

Rev.2.00 Nov 28, 2005 page 289 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 21.17 Pin Connections for CAN I/O Mode (1) CNVSS RESET CTX CRX VSS VCC1 VCC2 SCLK EPM CE M16C/6N Group (M16C/6NK) (Flash memory version[...]

Rev.2.00 Nov 28, 2005 page 290 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 21.18 Pin Connections for CAN I/O Mode (2) 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 2 2 32 42 52 62 72 82 93 0 73 74 75 76 77 78 79 [...]

Rev.2.00 Nov 28, 2005 page 291 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.6.2 Example of Circuit Application in CAN I/O Mode Figure 21.19 shows example of circuit application in CAN I/O mode. Refer to the user ’[...]

Rev.2.00 Nov 28, 2005 page 292 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. 22. Electrical Characteristics 22.1 Electrical Characteristics (Normal-ver.) Table 22.1 Absolute Maximum Ratings NOTE: 1. Po[...]

Rev.2.00 Nov 28, 2005 page 293 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Table 22.2 Recommended Operating Conditions (1) (1) Supply Voltage (VCC1 = VCC2) Analog Supply Voltage Supply Voltage Analog[...]

Rev.2.00 Nov 28, 2005 page 294 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Table 22.3 Recommended Operating Conditions (2) (1) Main Clock Input Oscillation N o Wait Mask ROM Version V C C = 3.0 to 5.[...]

Rev.2.00 Nov 28, 2005 page 295 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Table 22.4 Electrical Characteristics (1) (1) V CC -2.0 V CC -0.3 3.0 3.0 0.2 0.2 0.2 30 2.0 2.5 1.6 0 0 50 1.5 15 HIGH Outp[...]

Rev.2.00 Nov 28, 2005 page 296 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Table 22.5 Electrical Characteristics (2) (1) Mask ROM f(BCLK) = 24MHz, PLL operation, No division On-chip oscillation, No d[...]

Rev.2.00 Nov 28, 2005 page 297 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Table 22.6 A/D Conversion Characteristics (1) 10 ± 3 ± 7 ± 5 ± 7 ± 2 ± 3 ± 7 ± 5 ± 7 ± 2 ± 1 ± 3 ± 3 40 V CC V [...]

Rev.2.00 Nov 28, 2005 page 298 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. 2 150 150 ms µ s µ s Time for Internal Power Supply Stabilization During Powering-On STOP Release Time Low Power Dissipati[...]

Rev.2.00 Nov 28, 2005 page 299 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. 15 15 ns ns ns ns ns External Clock Input Cycle Time External Clock Input HIGH Pulse Width External Clock Input LOW Pulse Wi[...]

Rev.2.00 Nov 28, 2005 page 300 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Timing Requirements (Referenced to VCC = 5V, VSS = 0V, at Topr = – 40 to 85 ° C unless otherwise specified) Table 22.13 T[...]

Rev.2.00 Nov 28, 2005 page 301 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. ns ns ns ns ns ns TBiIN Input Cycle Time (counted on one edge) TBiIN Input HIGH Pulse Width (counted on one edge) TBiIN Inpu[...]

Rev.2.00 Nov 28, 2005 page 302 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. t d(BCLK-AD) t h(BCLK-AD) t h(RD-AD) t h(WR-AD) t d(BCLK-CS) t h(BCLK-CS) t d(BCLK-ALE) t h(BCLK-ALE) t d(BCLK-RD) t h(BCLK-[...]

Rev.2.00 Nov 28, 2005 page 303 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. t d(BCLK-AD) t h(BCLK-AD) t h(RD-AD) t h(WR-AD) t d(BCLK-CS) t h(BCLK-CS) t d(BCLK-ALE) t h(BCLK-ALE) t d(BCLK-RD) t h(BCLK-[...]

Rev.2.00 Nov 28, 2005 page 304 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. 4 (NOTE 1) (NOTE 1) 4 (NOTE 1) (NOTE 1) 0 0 4 (NOTE 2) (NOTE 1) – 4 (NOTE 3) (NOTE 4) 0 0 t d(BCLK-AD) t h(BCLK-AD) t h(RD[...]

Rev.2.00 Nov 28, 2005 page 305 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.4 Timing Diagram (1) t su(D — C) CLKi TXDi RXDi t c(CK) t w(CKH) t w(CKL) t w(INL) t w(INH) t d(C — Q) t h(C ?[...]

Rev.2.00 Nov 28, 2005 page 306 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.5 Timing Diagram (2) Measuring conditions : VCC = 5 V Input timing voltage : Determined with V IL = 1.0 V, V IH = [...]

Rev.2.00 Nov 28, 2005 page 307 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.6 Timing Diagram (3) BCLK CSi t d(BCLK-CS) 25ns.max ADi 25ns.max ALE 25ns.max -4ns.min RD 25ns.max t h(BCLK-RD) 0n[...]

Rev.2.00 Nov 28, 2005 page 308 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.7 Timing Diagram (4) BCLK CSi t d(BCLK-CS) 25ns.max ADi t d(BCLK-AD) 25ns.max ALE 25ns.max t h(BCLK-ALE) -4ns.min [...]

Rev.2.00 Nov 28, 2005 page 309 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.8 Timing Diagram (5) Read timing Write timing BCLK CSi ALE DBi ADi BHE WR, WRL WRH Memory Expansion Mode and Micro[...]

Rev.2.00 Nov 28, 2005 page 310 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.9 Timing Diagram (6) Read timing Write timing BCLK CSi ALE DBi ADi BHE WR, WRL WRH Memory Expansion Mode and Micro[...]

Rev.2.00 Nov 28, 2005 page 311 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.10 Timing Diagram (7) Memory Expansion Mode and Microprocessor Mode (For 1- or 2-wait setting, external area acces[...]

Rev.2.00 Nov 28, 2005 page 312 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.11 Timing Diagram (8) Read timing Write timing Memory Expansion Mode and Microprocessor Mode (For 3-wait setting, [...]

Rev.2.00 Nov 28, 2005 page 313 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Table 22.28 Electrical Characteristics (1) V CC -0.5 V CC -0.5 V CC -0.5 0.2 0.2 0.2 50 2.0 2.5 1.6 0 0 100 3.0 25 HIGH Outp[...]

Rev.2.00 Nov 28, 2005 page 314 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. 15 15 ns ns ns ns ns External Clock Input Cycle Time External Clock Input HIGH Pulse Width External Clock Input LOW Pulse Wi[...]

Rev.2.00 Nov 28, 2005 page 315 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Timing Requirements (Referenced to VCC = 3.3V, VSS = 0V, at Topr = – 40 to 85 ° C unless otherwise specified) Table 22.31[...]

Rev.2.00 Nov 28, 2005 page 316 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. ns ns ns ns ns ns TBiIN Input Cycle Time (counted on one edge) TBiIN Input HIGH Pulse Width (counted on one edge) TBiIN Inpu[...]

Rev.2.00 Nov 28, 2005 page 317 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. t d(BCLK-AD) t h(BCLK-AD) t h(RD-AD) t h(WR-AD) t d(BCLK-CS) t h(BCLK-CS) t d(BCLK-ALE) t h(BCLK-ALE) t d(BCLK-RD) t h(BCLK-[...]

Rev.2.00 Nov 28, 2005 page 318 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. t d(BCLK-AD) t h(BCLK-AD) t h(RD-AD) t h(WR-AD) t d(BCLK-CS) t h(BCLK-CS) t d(BCLK-ALE) t h(BCLK-ALE) t d(BCLK-RD) t h(BCLK-[...]

Rev.2.00 Nov 28, 2005 page 319 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. 4 (NOTE 1) (NOTE 1) 4 (NOTE 1) (NOTE 1) 0 0 4 (NOTE 2) (NOTE 1) – 4 (NOTE 3) (NOTE 4) 0 0 t d(BCLK-AD) t h(BCLK-AD) t h(RD[...]

Rev.2.00 Nov 28, 2005 page 320 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.13 Timing Diagram (1) t su(D — C) CLKi TXDi RXDi t c(CK) t w(CKH) t w(CKL) t w(INL) t w(INH) t d(C — Q) t h(C [...]

Rev.2.00 Nov 28, 2005 page 321 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.14 Timing Diagram (2) Measuring conditions : VCC = 3.3 V Input timing voltage : Determined with V IL = 0.6 V, V IH[...]

Rev.2.00 Nov 28, 2005 page 322 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.15 Timing Diagram (3) BCLK CSi t d(BCLK-CS) 30ns.max ADi 30ns.max ALE 30ns.max -4ns.min RD 30ns.max t h(BCLK-RD) 0[...]

Rev.2.00 Nov 28, 2005 page 323 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.16 Timing Diagram (4) BCLK CSi t d(BCLK-CS) 30ns.max ADi t d(BCLK-AD) 30ns.max ALE 30ns.max t h(BCLK-ALE) -4ns.min[...]

Rev.2.00 Nov 28, 2005 page 324 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.17 Timing Diagram (5) Read timing Write timing BCLK CSi ALE DBi ADi BHE WR, WRL WRH Memory Expansion Mode and Micr[...]

Rev.2.00 Nov 28, 2005 page 325 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.18 Timing Diagram (6) Read timing Write timing BCLK CSi ALE DBi ADi BHE WR, WRL WRH Memory Expansion Mode and Micr[...]

Rev.2.00 Nov 28, 2005 page 326 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.19 Timing Diagram (7) Memory Expansion Mode and Microprocessor Mode (For 2-wait setting, external area access and [...]

Rev.2.00 Nov 28, 2005 page 327 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.20 Timing Diagram (8) Read timing Write timing Memory Expansion Mode and Microprocessor Mode (For 3-wait setting, [...]

Rev.2.00 Nov 28, 2005 page 328 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change. 22.2 Electrical Characteristics (T/V-ver.) Table 22.46 Absolute Maximum Ratings option: All options are on request basis. NOTE[...]

Rev.2.00 Nov 28, 2005 page 329 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change. Table 22.47 Recommended Operating Conditions (1) (1) Supply Voltage (VCC1 = VCC2) Analog Supply Voltage Supply Voltage Analog [...]

Rev.2.00 Nov 28, 2005 page 330 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change. Table 22.48 Recommended Operating Conditions (2) (1) Main Clock Input Oscillation N o Wait Flash Memory VCC = 4 . 2 to 5.5V Fr[...]

Rev.2.00 Nov 28, 2005 page 331 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change. Table 22.49 Electrical Characteristics (1) (1) V CC -2.0 V CC -0.3 3.0 3.0 0.2 0.2 0.2 30 2.0 2.5 1.6 0 0 50 1.5 15 HIGH Outpu[...]

Rev.2.00 Nov 28, 2005 page 332 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change. Table 22.50 Electrical Characteristics (2) (1) Flash Memory f(BCLK) = 20MHz, PLL operation, No division On-chip oscillation, N[...]

Rev.2.00 Nov 28, 2005 page 333 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change. Table 22.51 A/D Conversion Characteristics (1) (NOTE 2) 8 1.0 3 20 1.5 Bits % µs k Ω mA Resolution Absolute Accuracy Setup [...]

Rev.2.00 Nov 28, 2005 page 334 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change. Table 22.53 Flash Memory Version Electrical Characteristics (1) 2 150 150 ms µs µs Time for Internal Power Supply Stabilizat[...]

Rev.2.00 Nov 28, 2005 page 335 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change. VCC = 5V 15 15 ns ns ns ns ns External Clock Input Cycle Time External Clock Input HIGH Pulse Width External Clock Input LOW P[...]

Rev.2.00 Nov 28, 2005 page 336 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change. ns ns ns ns ns ns TBiIN Input Cycle Time (counted on one edge) TBiIN Input HIGH Pulse Width (counted on one edge) TBiIN Input [...]

Rev.2.00 Nov 28, 2005 page 337 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change. Figure 22.23 Timing Diagram t su(D — C) CLKi TXDi RXDi t c(CK) t w(CKH) t w(CKL) t w(INL) t w(INH) t d(C — Q) t h(C — D)[...]

Rev.2.00 Nov 28, 2005 page 338 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23. Usage Precaution 23.1 SFR There is the SFR which can not be read (containg bits that will result in unknown data when read). Please set these r[...]

Rev.2.00 Nov 28, 2005 page 339 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.2 External Bus (Normal-ver. only) When resetting CNVSS pin with "H" input, contents of internal ROM cannot be read out.[...]

Rev.2.00 Nov 28, 2005 page 340 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.3 External Clock Do not stop the external clock when it is connected to the XIN pin and the main clock is selected as the CPU clock.[...]

Rev.2.00 Nov 28, 2005 page 341 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.4 PLL Frequency Synthesizer Stabilize supply voltage so that the standard of the power supply ripple is met. (Refer to 22. Electrical characteri[...]

Rev.2.00 Nov 28, 2005 page 342 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.5 Power Control • ____________ When exiting stop mode by hardware reset, set RESET pin to “ L ” until a main clock oscillation is stabiliz[...]

Rev.2.00 Nov 28, 2005 page 343 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. • Suggestions to reduce power consumption. Ports The processor retains the state of each I/O port even when it goes to wait mode or to stop mode.[...]

Rev.2.00 Nov 28, 2005 page 344 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.6 Oscillation Stop, Re-oscillation Detection Function If the following conditions are all met, the following restriction occur in operation of o[...]

Rev.2.00 Nov 28, 2005 page 345 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.7 Protection Set the PRC2 bit to “ 1 ” (write enabled) and then write to any address, and the PRC2 bit will be set to “ 0 ” (write prote[...]

Rev.2.00 Nov 28, 2005 page 346 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.8 Interrupt 23.8.1 Reading Address 00000h Do not read the address 00000h in a program. When a maskable interrupt request is accepted, the CP U r[...]

Rev.2.00 Nov 28, 2005 page 347 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.8.4 Changing Interrupt Generate Factor If the interrupt generate factor is changed, the IR bit of the interrupt control register for the changed[...]

Rev.2.00 Nov 28, 2005 page 348 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.8.6 Rewrite Interrupt Control Register (a ) The interrupt control register for any interrupt should be modified in places where no interrupt req[...]

Rev.2.00 Nov 28, 2005 page 349 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.9 DMAC 23.9.1 Write to DMAE Bit in DMiCON Register (i = 0, 1) When both of the conditions below are met, follow the steps below. Conditions • [...]

Rev.2.00 Nov 28, 2005 page 350 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.10 Timers 23.10.1 Timer A 23.10.1.1 Timer A (Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. usi[...]

Rev.2.00 Nov 28, 2005 page 351 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.10.1.2 Timer A (Event Counter Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 t[...]

Rev.2.00 Nov 28, 2005 page 352 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.10.1.3 Timer A (One-shot Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 [...]

Rev.2.00 Nov 28, 2005 page 353 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.10.1.4 Timer A (Pulse Width Modulation Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR[...]

Rev.2.00 Nov 28, 2005 page 354 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.10.2 Timer B 23.10.2.1 Timer B (Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR [...]

Rev.2.00 Nov 28, 2005 page 355 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.10.2.3 Timer B (Pulse Period/pulse Width Measurement Mode) The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR [...]

Rev.2.00 Nov 28, 2005 page 356 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.11 Thee-Phase Motor Control Timer Function If there is a possibility that you may write data to TAi-1 register (i = 1, 2, 4) near Timer B2 overf[...]

Rev.2.00 Nov 28, 2005 page 357 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.12 Serial Interface 23.12.1 Clock Synchronous Serial I/O Mode 23.12.1.1 Transmission/reception _______ ________ With an external clock selected,[...]

Rev.2.00 Nov 28, 2005 page 358 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.12.2 Special Modes 23.12.2.1 Special Mode 1 (I 2 C Mode) When generating start, stop and restart conditions, set the STSPSEL bit in the UiSMR4 r[...]

Rev.2.00 Nov 28, 2005 page 359 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.12.3 SI/Oi (i = 3 to 6) (1) The SOUTi default value which is set to the SOUTi pin by the SMi7 in the SiC register bit approximately 10ns may be [...]

Rev.2.00 Nov 28, 2005 page 360 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.13 A/D Converter Set the ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before a trigger occurs). When the V[...]

Rev.2.00 Nov 28, 2005 page 361 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. If the CPU reads the ADi register at the same time the conversion result is stored in the ADi register after completion of A/D conversion, an incor[...]

Rev.2.00 Nov 28, 2005 page 362 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.14 CAN Module 23.14.1 Reading CiSTR Register (i = 0, 1) The CAN module on the M16C/6N Group (M16C/6NK, M16C/6NM) updates the status of the CiSTR[...]

Rev.2.00 Nov 28, 2005 page 363 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. Figure 23.5 When Updating Period of CAN Module Matches Access Period from CPU fCAN ✕✕ ✕ ✕✕ CPU read signal CPU reset signal Updating peri[...]

Rev.2.00 Nov 28, 2005 page 364 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.14.2 Performing CAN Configuration If the Reset bit in the CiCTLR register (i = 0, 1) is changed from “ 0 ” (operation mode) to “ 1 ” (re[...]

Rev.2.00 Nov 28, 2005 page 365 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.14.3 Suggestions to Reduce Power Consumption When not performing CAN communication, the operation mode of CAN transceiver should be set to “ s[...]

Rev.2.00 Nov 28, 2005 page 366 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.14.4 CAN Transceiver in Boot Mode When programming the flash memory in boot mode via CAN bus, the operation mode of CAN transceiver should be se[...]

Rev.2.00 Nov 28, 2005 page 367 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.15 Programmable I/O Ports _______ If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase ___[...]

Rev.2.00 Nov 28, 2005 page 368 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.16 Dedicated Input Pin When dedicated input pin voltage is larger than VCC pin voltage, latch up occurs. When different power supplied to the sy[...]

Rev.2.00 Nov 28, 2005 page 369 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.17 Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers Flash memory version and mask ROM version may [...]

Rev.2.00 Nov 28, 2005 page 370 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.18 Mask ROM Version When using the masked ROM version, write nothing to internal ROM area.[...]

Rev.2.00 Nov 28, 2005 page 371 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.19 Flash Memory Version 23.19.1 Functions to Prevent Flash Memory from Rewriting ID codes are stored in addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FF[...]

Rev.2.00 Nov 28, 2005 page 372 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.19.9 Prohibited Instructions The following instructions cannot be used in EW0 mode because the CPU tries to read data in flash memory: UND instr[...]

Rev.2.00 Nov 28, 2005 page 373 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.20 Flash Memory Programming Using Boot Program When programming the internal flash memory using boot program, be careful about the pins state an[...]

Rev.2.00 Nov 28, 2005 page 374 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.21 Noise Connect a bypass capacitor (approximately 0.1 µF) across the VCC1 and VSS pins, and VCC2 and VSS pins using the shortest and thicker p[...]

Rev.2.00 Nov 28, 2005 page 375 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) Appendix 1. Package Dimensions Under development This document is under development and its contents are subject to change. Appendix 1. Package Dimensions Terminal cross section b 1 c 1 b p c 2. 1. DIMENSIONS " * 1" AND " * 2" DO NOT INCLUDE[...]

Rev.2.00 Nov 28, 2005 page 376 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) Appendix 1. Package Dimensions Under development This document is under development and its contents are subject to change. Memo[...]

Rev.2.00 Nov 28, 2005 page 377 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) Register Index Under development This document is under development and its contents are subject to change. Register Index A AD0 to AD7 ................................... 205 ADCON0 ..... 204,207,209,21 1,213,215 ADCON1 ..... 204,207,209,21 1,213,215 ADCON2 ..[...]

Rev.2.00 Nov 28, 2005 page 378 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) Register Index Under development This document is under development and its contents are subject to change. U U0BCNIC t o U2BCNIC ..................... 86 U0BRG to U2BRG ........................ 153 U0C0 to U2C0 ............................... 154 U0C1 to U2C1 [...]

REVISION HISTORY M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Rev . Date Description Page Summary C-1 1.00 Sep. 30, 2004 1.01 Nov. 01, 2004 1.10 Jul. 01, 2005 – First edition issued – Revised edition issued * Revised parts and revised contents are as follows (except for expressional change). 3 Table 1.2 Performance Outline of M16C/6N Grou[...]

REVISION HISTORY M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Rev . Date Description Page Summary C-2 212 Figure 18.11 C0RECR, C1RECR Registers, C0TECR, C1TECR Registers, C0TSR, C1TSR Registers, and C0AFS, C1AFS Registers • C0RECR, C1RECR Registers: NOTE 2 is deleted. • C0TECR, C1TECR Registers: NOTE 1 is deleted. • C0TSR, C1TSR Registe[...]

REVISION HISTORY M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Rev . Date Description Page Summary C-3 37 5.2 Software Reset, 5.3 Watchdog Timer Reset, 5.4 Oscillation Stop Detection Reset: Last sentence (Processor mode remains ...) is added to each section. 5.5 Internal Space is added. 38 6.1 Types Processor Mode is added. Table 6.1 Features [...]

REVISION HISTORY M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Rev . Date Description Page Summary C-4 108 12.1.3 Effect of Software Wait: 3rd to 9th lines is moved from next section of 12.1.2. ________ 12.1.4 Effect of RDY Signal is added. 110 Table 12.2 DMA Transfer Cycles is revised. Table 12.3 Coefficient j, k is revised. 112 12.5 Channel [...]

REVISION HISTORY M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Rev . Date Description Page Summary C-5 258 Table 20.3 Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode (Normal-ver. only) is added. 259 Figure 20.12 Unassigned Pins Handling • Figure of memory expansion mode or microprocessor mode is added. • NOTES 1 an[...]

REVISION HISTORY M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Rev . Date Description Page Summary C-6 291 Figure 21.19 Circuit Application in CAN I/O Mode: “VCC1” and “VCC2” are added. 293 Table 22.2 Recommended Operating Conditions (1) is partly revised. 297 __________ ________ Table 22.4 Electrical Characteristics (1): HOLD and RDY [...]

M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Publication Data : Rev.1.00 Sep 30, 2004 Rev.2.00 Nov 28, 2005 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.[...]

M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual 2- 6 -2, Ote-machi, Chiyoda-ku, Tokyo, 1 00-0004, Japan[...]