Samsung S3C2440A manual

S3C2440A 32-BIT RISC MICROPROCESSOR USER'S MANUAL PRELIMINA RY Rev isio n 0.14 (June 30, 2004)[...]

S3C2440A RISC MICROPROCESSO R PRODUCT OVERVIEW 1-1 1 PRODUCT OVERVIEW INTRODUCTION This user’s m anual describes SAMSUNG 's S3C2440A 16/32-bit RISC m ic roproces sor. SAMSUNG’s S3C2440A is designed to provide hand-held devic es and general applic ations with low-power, and high-perform ance m icro- controller s olution in sm all die size. [...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-2 FEA TURES A rchit ecture • Integrated system f or hand-held devic es and general em bedded applications. • 16/32-Bit RISC architec ture and powerful instruction s et with ARM920T CPU core. • Enhanced ARM architec ture MMU to support W inCE, EPOC 32 and Linux. • Instruction c ache, data cac h[...]

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-3 FEA TURES (Continued) Interrupt Controller • 60 Interrupt sour ces (One W atch dog tim er, 5 tim ers , 9 UARTs, 24 external interrupts , 4 DMA, 2 RTC, 2 ADC, 1 IIC, 2 SPI, 1 SDI, 2 USB, 1 LCD, 1 Battery Fault, 1 NAND and 2 Camer a), 1 AC97 • Level/Edge mode on ex ternal interrupt s ource • Pro[...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-4 FEA TURES (Continued) A /D Converter & Touch Screen Inter face • 8-ch m ultiplexed AD C • Max. 500KSPS and 10-bit Res olution • Internal FET for dir ect Touc h scr een interfac e Watchdog Timer • 16-bit W atchdog T imer • Interrupt request or system res et at time- out IIC-Bus Interf a[...]

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-5 BLOCK DIA GRAM A RM920T ARM 9 T D M I Processo r core (Inte rnal E mbedded ICE) DD[31:0 ] Writ eBack PA Tag RA M Data MMU C13 DVA[31:0] DVA[31:0] Instr ucti on CACHE (16KB) Inst ructi on MMU External Copr oc Inte rface C13 ID[31: 0] IPA[31: 0] IVA[31: 0] CP15 Write Buffer AM B A Bus I/F JTAG Data CA[...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-6 PIN A SSIGNMENTS BOTTOM VIEW U T R P N M L K J H G F E D C B A 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 Figure 1-2. S3C2440A Pin A ssignm ents (289-F BGA )[...]

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-7 Table 1- 1. 289-Pin FBG A Pin Assignments – Pin Numb er Order (Sheet 1 o f 3) Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name A1 VDDi C1 VDDMOP E1 nFRE/GPA20 A2 SCKE C2 nGCS5/GPA16 E2 VSSMOP A3 VSSi C3 nGCS2/GPA13 E3 nGCS7 A4 VSSi C4 nGCS3/GPA14 E4 nW AIT A5 VSSMOP C5 nOE E5 nBE3 A6 VD[...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-8 Table 1- 1. 289-Pin FBG A Pin Assignments – Pin Numb er Order (Sheet 2 o f 3) Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name G1 VSSOP J1 VDDOP L1 LEND/GPC0 G2 CAMHREF/GPJ10 J2 VDDiarm L2 VDDiarm G3 CAMDAT A1/GPJ1 J3 CAMCLKOUT /GPJ11 L3 nXDACK0/GPB9 G4 VDDalive J4 CAMRESET/G PJ12 L4 VC[...]

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-9 Table 1- 1. 289-Pin FBG A Pin Assignments – Pin Numb er Order (Sheet 3 o f 3) Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name N1 VSSOP R1 VD3/GPC11 U1 VDDiarm N2 VD0/GPC8 R2 VD8/GPD0 U2 VDDiarm N3 VD4/GPC12 R3 VD11/GPD3 U3 VSSOP N4 VD2/GPC10 R4 VD13/GPD5 U4 VSSiarm N5 VD10/GPD2 R5 VD18[...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-10 Table 1- 2. S3C2440A 289- Pin FBGA Pin A ssignmen ts (Sheet 1 o f 9) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @Sleep I/O State @nRESET I/O Type F7 ADDR0/GPA0 ADDR0 Hi-z/– O(L)/– O(L) t10s E7 ADDR1 ADDR1 Hi-z O(L) O(L) t10s B7 ADDR2 ADDR2 Hi-z O(L) O(L) t10s F8 ADDR3 ADD[...]

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-11 Table 1- 2. S3C2440A 289- Pin FBGA Pin A ssignmen ts (Sheet 2 o f 9) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @Sleep I/O State @nRESET I/O T ype P16 XP/AIN7 X P –/– –/– AI r10 H6 CAMDATA0/GPJ 0 GPJ 0 –/– Hi-z/– I t8 G3 CAMDATA1/G PJ1 G PJ1 –/– Hi-z/– I t[...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-12 Table 1- 2. S3C2440A 289- Pin FBGA Pin A ssignmen ts (Sheet 3 o f 9) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @Sleep I/O State @nRESET I/O T ype E13 DATA19 DATA19 Hi-z Hi-z ,O (L) I b12s E12 DATA20 DATA20 Hi-z Hi-z ,O (L) I b12s E16 DATA21 DATA21 Hi-z Hi-z ,O (L) I b12s F15[...]

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-13 Table 1- 2. S3C2440A 289- Pin FBGA Pin A ssignmen ts (Sheet 4 o f 9) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @Sleep I/O State @nRESET I/O T ype T10 EINT 16/GPG8 GPG 8 –/– Hi-z/– I t8 M11 EINT17/nRT S1/GPG9 GPG9 –/–/– Hi-z/O(H) /– I t8 N10 EINT18/nCT S1/GPG10 [...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-14 Table 1- 2. S3C2440A 289- Pin FBGA Pin A ssignmen ts (Sheet 5 o f 9) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @Sleep I/O State @nRESET I/O T ype E3 nGCS7 nG CS7 Hi-z Hi-z,O(H) O(H) t10s D6 nSCAS nSCAS Hi-z Hi-z,O(H) O(H) t10s C6 nSRAS nSRAS Hi-z Hi-z,O(H) O(H) t10s H15 nTRS[...]

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-15 Table 1- 2. S3C2440A 289- Pin FBGA Pin A ssignmen ts (Sheet 6 o f 9) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @Sleep I/O State @nRESET I/O T ype A2 SCKE SCKE Hi- z O( L) O(H) t10s B4 SCLK0 SCLK0 Hi-z O(L) O(SCLK) t12s B3 SCLK1 SCLK1 Hi-z O(L) O(SCLK) t12s P7 I2SLRCK/AC_SYNC[...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-16 Table 1- 2. S3C2440A 289- Pin FBGA Pin A ssignmen ts (Sheet 7 o f 9) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @Sleep I/O State @nRESET I/O T ype N4 VD2/GPC10 GPC10 –/– O(L)/– I t8 R1 VD3/GPC11 GPC11 –/– O(L)/– I t8 N3 VD4/GPC12 GPC12 –/– O(L)/– I t8 P2 VD5[...]

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-17 Table 1- 2. S3C2440A 289- Pin FBGA Pin A ssignmen ts (Sheet 8 o f 9) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @Sleep I/O State @nRESET I/O Type A1 VDDi VDDi P P P d12c A10 VDDi VDDi P P P d12c A16 VDDi VDDi P P P d12c A6 VDDi VDDi P P P d12c B11 VDDi VDDi P P P d12c F1 VDDi[...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-18 Table 1- 2. S3C2440A 289- Pin FBGA Pin A ssignmen ts (Sheet 9 o f 9) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @Sleep I/O State @nRESET I/O Type F2 VSSi VSSi P P P s i G17 VSSi VSSi P P P s i H1 VSSiarm VSSiarm P P P si K1 VSSiarm VSSiarm P P P si T1 VSSiar m VSSiarm P P P s[...]

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-19 NOTE: 1. The @BUS REQ. shows the pin state at the ex ternal bus, which is used by the other bus master. 2. ' – ‘ mark indicates the unchanged pin state at Bus Request mode. 3. Hi-z or Pre means Hi-z or early state and it is determined by the setting of MISCCR register. 4. AI/AO means analo[...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-20 THE T ABLE BELOW SHOWS I/O TY PES A ND DESCRIPT IONS. Input (I)/Output (O) Type Descriptions d12i(vdd12ih) 1.2V Vdd for alive power d12c(vdd12ih_cor e), si(vss ih) 1.2V Vdd/Vss for inter nal logic d33o(vdd33oph), so( vssoph) 3.3V Vdd/Vs s for external logic d33th(vdd33th_abb) ,sth(vssbbh_abb) 3.3V [...]

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-21 SIGNAL DESCRIPTIONS Table 1- 3. S3C2440A Sign al Descriptions ( Sheet 1 of 6) Signal Input/Output Descriptions Bus Contro ller OM[1:0] I OM[1:0] sets S3C2440A in the T EST m ode, which is used only at fabrication. Also, it determ ines the bus width of nG CS0. The pull- up/down resistor determ ines [...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-22 Table 1- 3. S3C2440A Sign al Descriptions ( Sheet 2 of 6) Signal Input/Output Descriptions LCD Control Unit VD[23:0] O STN /TFT/ SEC TFT: LCD Data Bus LCD_PW REN O STN /TFT/ SEC TFT: LCD panel power enable control signal VCLK O STN /TFT: LCD clock signal VFRAME O STN: LCD F ram e signal VLINE O STN[...]

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-23 Table 1- 3. S3C2440A Sign al Descriptions ( Sheet 3 of 6) Signal Input/Output Descriptions UA RT RxD[2:0] I UART rec eives data input TxD[2:0] O UART transm its data output nCTS[1:0] I UART c lear to send input signal nRTS[1:0] O UART reques t to send output signal UEXT CLK I External clock input f[...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-24 Table 1- 3. S3C2440A Sign al Descriptions ( Sheet 4 of 6) Signal Input/Output Description SPI SPIMISO[1:0] IO SPIMISO is the m aster data input line, when SPI is c onfigured as a mas ter. W hen SPI is conf igured as a slave, thes e pins revers e its role. SPIMOSI[1:0] IO SPIMO SI is the m aster dat[...]

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-25 Table 1- 3. S3C2440A Sign al Descriptions ( Sheet 5 of 6) Signal Input/Output Description Reset, Clock & Pow er XT Opll AO Cry s tal Output for internal osc circuit. W hen OM[3:2] = 00b, XT Ipll is used f or MPLL CLK sour ce and UPLL CLK source. W hen OM[3:2] = 01b, XT Ipll is used f or MPLL CL[...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-26 Table 1- 3. S3C2440A Sign al Descriptions ( Sheet 6 of 6) Signal Input/Output Description Pow er VDDalive P S3C2440A reset block and port status register VDD. It should be alway s supplied whether in norm al m ode or in Sleep m ode. VDDiarm P S3C2440A core logic VDD f or ARM core. VDDi P S3C2440A c[...]

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-27 S3C2440A SPECIAL REGISTERS Table 1- 4. S3C2440A Sp ecial Registers (Sheet 1 of 14) Register Name A dd ress (B. Endian) A ddress (L. Endian) Acc. Unit Read/ Write Function Mem ory Controller BW SCON 0x48000000 ← W R/W Bus W idth & W ait Status Contr ol BANKCON0 0x48000004 Boot ROM Control BANK[...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-28 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 2 of 14) Register Name A dd ress (B. Endian) A ddress (L. Endian) Acc. Unit Read/ Write Function USB Host Controller HcRevision 0x49000000 ← W Control and Status Gr oup HcControl 0x49000004 HcCom m onStatus 0x49000008 HcInterruptStatus 0x 4900000C Hc[...]

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-29 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 3 of 14) Register Name A dd ress (B. Endian) A ddress (L. Endian) Acc. Unit Read/ Write Function DMA DISRC0 0x4B000000 ← W R/W D MA 0 Initial Source DISRCC0 0x4B000004 DMA 0 Initial Source Contr ol DIDST0 0x 4B000008 DMA 0 Initial Destination DIDSTC0[...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-30 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 4 of 14) Register Name A dd ress (B. Endian) A ddress (L. Endian) Acc. Unit Read/ Write Function Clock & Power Management LOCKTI ME 0x4C000000 ← W R/W PLL Lock Tim e Counter MPLLCON 0x4C000004 MPLL Control UPLLCON 0x4C000008 UPLL Control CLKCON 0[...]

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-31 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 5 of 14) Register Name A dd ress (B. Endian) A ddress (L. Endian) Acc. Unit Read/ Write Function NA ND Flash NFCONF 0x4E000000 ← W R/W NAND Flash Conf iguration NFCONT 0x4E000004 NAND Flash Control NFCMD 0x4E000008 NAND Flash Com m and NFADDR 0x4E000[...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-32 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 6 of 14) Register Name A ddress (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Func tion Camera Interface CISRCFMT 0x 4F000000 ← W RW Input Source Form at CIW DOFST 0x4F000004 W indow off set regis ter CIGCT RL 0x4F000008 Global control regis [...]

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-33 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 7 of 14) Register Name A ddress (B. Endian) Address (L. Endian) A cc. Unit Read/ Write Function UA RT ULCON0 0x50000000 ← W R/W UART 0 Line Control UCON0 0x50000004 UART 0 Control UFCON0 0x50000008 UART 0 FIFO Control UMCON0 0x5000000C UART 0 Modem C[...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-34 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 8 of 14) Register Name A ddress (B. Endian) Address (L. Endian) A cc. Unit Read/ Write Func tion PWM T imer TCF G0 0x51000000 ← W R/W T imer Configuration TCF G1 0x51000004 Tim er Configuration TCO N 0x51000008 Tim er Co ntrol TCNT B0 0x5100000C T im[...]

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-35 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 9 of 14) Register Name A dd ress (B. Endian) Address (L. Endian) A cc. Unit Read/ Write Func tion USB Device FUNC_ADDR_REG 0x52000143 0x52000140 B R/W Func tion Address PW R_REG 0x52000147 0x52000144 Power Management EP_INT_REG 0x 5200014B 0x52000148 E[...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-36 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 10 of 14) Register Name A dd ress (B. Endian) Address (L. Endian) Acc. Unit Read/Write Function USB Device (Continued) EP2_DMA_CON 0x5200021B 0x52000218 B R/W EP2 DMA Inter face Control EP2_DMA_UNIT 0x5200021F 0x5200021C EP2 DMA Tx Unit Counter EP2_DMA[...]

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-37 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 11 of 14) Register Name A d dress (B. Endian) A dd ress (L. Endian) A cc. Unit Read/ Write Func tion I/O port GPACON 0x 56000000 ← W R / W P o r t A C o n t r o l GPADAT 0x56000004 Port A Data GPBCON 0x 56000010 Port B Control GPBDAT 0x56000014 Port [...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-38 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 12 of 14) Register Name A d dress (B. Endian) Address (L. Endian) Acc. Unit Read / Write Function I/O port (Continued) EINTFLT 0 0x56000094 ← W R / W R e s e r v e d EINTFLT 1 0x56000098 Res erved EINTFLT 2 0x5600009C External Interrupt F ilter Contr[...]

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-39 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 13 of 14) Register Name Address (B. Endian) Address (L. Endian) A cc. Un it Read/ Write Function A /D converter ADCCON 0x58000000 ← W R/W ADC Control ADCTSC 0x58000004 ADC Touc h Screen Control ADCDLY 0x 58000008 ADC Start or Interval Delay ADCDAT0 0[...]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-40 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 14 of 14) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function A C97 Audio-CODEC Interf ace AC_GLBCTRL 0x5B000000 R/W AC97 G lobal Control Register AC_GLBST AT 0x5B000004 R AC97 Global Status Register AC_CODEC_CMD 0x 5B0[...]

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-1 2 PROGRA MMER'S MODEL OVERVIEW S3C2440A is developed using the advanced ARM920T cor e, which has been designed by Advanced RISC Machines, Ltd. PROCESSOR O PERA T ING ST A TES From the program m er's point of view, the ARM920T c an be in one of the two states: • ARM state which ex [...]

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-2 BIG-ENDIA N FORM A T In Big-Endian for mat, the m os t significant byte of a word is stor ed at the lowest number ed by te and the leas t significant byte at the highest num bered byte. By te 0 of the m em ory sy stem is therefor e connected to data lines 31 through 24. 31 8 4 0 23 9 5 1 10 6[...]

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-3 OPERA TING MO DES ARM920T s upports seven m odes of operation: • User (usr): T he norm al ARM progr am ex ecution state • FIQ (fiq): Designed to support a data trans fer or channel proces s • IRQ (irq): Used for general- purpose interr upt handling • Supervisor (s vc): Protected m ode[...]

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-4 R0 R1 R2 R3 R4 R5 R6 R7 R9 R8 R10 R11 R12 R13 R14 R15 (PC) R0 R1 R2 R3 R4 R5 R6 R7 R9 R8 R10 R11 R12 R13_ svc R14_ svc R15 (PC) R0 R1 R2 R3 R4 R5 R6 R7 R9_ fiq R10_ fiq R11_ fiq R12_ fiq R13_ fiq R14_ fiq R15 (PC) R8_ fiq R0 R1 R2 R3 R4 R5 R6 R7 R9 R8 R10 R11 R12 R13_ abt R14_ abt R15 (PC) R0[...]

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-5 The T HUM B State Regist er Set The THUMB state regis ter set is a s ubset of the ARM s tate set. T he program m er has direc t acces s to eight general register s, R0-R7, as well as the Program Counter (PC), a stack pointer regis ter (SP), a link r egister (LR), and the CPSR. There ar e bank[...]

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-6 The relat ionship b etween A RM and THUM B state reg isters The relations hip between ARM and THUMB state r egisters ar e as below:- • THUMB state R0- R7 and ARM state R0-R7 ar e identical • THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs ar e identical • THUMB state SP m aps on[...]

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-7 A ccessing Hi-Registers in T HUM B State In THUMB st ate, registers R8-R15 (“Hi regi sters”) are not par t of the standar d register s et. However, the assem bly language programm er has lim ited access to them , and can use them for fast tem por ary storage. A value may be transfer red f[...]

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-8 The Condition Code Flags The N, Z, C and V bits are the condition c ode flags. T hese m ay be changed as a result of arithm etic and logical operations, and m ay be tested to determine whether an instr uction should be ex ecuted. In ARM state, all instr uctions m ay be executed conditionally:[...]

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-9 Table 2- 1. PSR Mo de Bit Values M[ 4:0] M ode Visible T HUM B state regist ers Visible A R M st ate registers 10000 User R7..R0, LR, SP PC, CPSR R14..R0, PC, CPSR 10001 FIQ R7..R0, LR_fiq, SP_f iq PC, CPSR, SPSR_fiq R7..R0, R14_fiq..R8_f iq, PC, CPSR, SPSR_fiq 10010 IRQ R7..R0, LR_irq, SP_ir[...]

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-10 EXCEPTIO NS Exceptions ar ise whenever the norm al flow of a program has to be halted tem porarily, for exam ple to s ervice an interrupt f rom a peripheral. Bef ore an exception c an be handled, the current pr ocessor state m ust be pres erved so that the original program can r esum e when [...]

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-11 Exception Entry/Exit Summary Table 2-2 s um mar izes the PC value preserved in the relevant R14 on ex ception entry, and the recom mended instruc tion for ex iting the exception handler. Tabl e 2-2. Exception Entry/Exit Return Inst ruction Previous St ate Notes A RM R14_x THUM B R14_x BL MO [...]

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-12 IRQ The IRQ (Interrupt Request) exception is a norm al inter rupt caused by a LOW level on the nIRQ input. IRQ has a lower priority than FIQ and is mas ked out when a FIQ sequence is entered. It m ay be dis abled at any time by setting I bit in the CPSR, though this can only be done from a p[...]

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-13 Software Interr upt The Sof tware Interrupt Inst ruction (SW I) is used for entering Supervisor m ode, usually to request a particular supervisor function. A SW I handler should return by executing the following irres pective of the s tate (ARM or Thum b): MOV PC,R14_svc This restores the PC[...]

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-14 Exception Priorities W hen multiple ex ceptions aris e at the sam e tim e, a fixed pr iority system determ ines the or der in which they are handled: Highest priority : 1. Reset 2. Data abor t 3. FIQ 4. IRQ 5. Pr efetch abor t Lowest priority : 6. Undef ined Instruc tion, Software interr upt[...]

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-15 INTERRUPT LA T ENCIES The worst c ase latency for FIQ, as sum ing that it is enabled, cons ists of the longest tim e the request c an take to pass through the s y nchroniz er (T syncmax if asynchronous), plus the time f or the longest ins truction to c om plete (Tldm , the longes t instruc t[...]

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-16 NOTES[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-1 3 A RM INSTRUCTION SET INSTRUCTION SET SUMMAY This chapter desc ribes the ARM instr uction set in the ARM920T core. FORMAT SUMM ARY The f ollowing figure shows the ARM instr uction set. Cond Rn Data/Processing/ PSR Transfer 0 0I S Opcode 00 0 P U 0 W L 00 0 P U 1 W L 01IP U B W L 01I 10 0 P U B W[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-2 NOT ES Some ins truction c odes are not def ined but does not cause Undef ined instruc tion trap to be tak en, for instance a m ultiply instruction with bit 6 changed to a 1. Thes e instruc tions should not be us ed, as their action m ay change in future ARM im plem entations. INSTRUCT ION SUM MA[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-3 Table 3-1. The A RM Instruction Set (Continued) Mnemonic Instruction A ction MRC Move from coproc essor r egister to CPU register Rn: = cRn {<op>cR m} MRS Move PSR status/f lags to register Rn: = PSR MSR Move register to PSR s tatus/flags PSR: = Rm MUL Multiply Rd: = Rm × Rs MVN Move negat[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-4 THE CONDITION FIELD In ARM state, all instr uctions are c onditionally executed acc ording to the state of the CPSR condition codes and the instruct ion's condition f ield. This f ield (bits 31:28) determ ines the circ ums tances under which an instruction is to be executed. If the state of [...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-5 BRA NCH AND EXCHA NGE (BX) This instruct ion is only executed if the condition is true. The var ious conditions ar e defined in T able 3-2. This instruction per form s a br anch by copy ing the contents of a general r egister, Rn, into the Progr am Counter , PC. The branc h causes a pipeline flus[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-6 Examples A DR R0, Into_T HUMB + 1 G enerate branch target addr ess and set bit 0 high – hence it com es in T HUMB state BX R0 Branch and change to T HUMB state. CODE16 Assem ble subs equent code as Into_THUM B T HUMB i nstructio ns A DR R5, Back_to _A RM Generate branc h target to word aligned [...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-7 BRA NCH AND BRA NCH W ITH LINK (B, BL) The ins truction is only executed if the condition is true. T he various c onditions are def ined Table 3- 2. The instruc tion encoding is shown in Figure 3- 3, below. 31 24 27 Cond Offset 28 23 [24] Link bit 0 = Branch 1 = Branch with link [31:28] Condition[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-8 A SSEM BLER SY NTAX Items in “{}” ar e optional. Items in “<>” m us t be present. B{L}{cond} <expression> {L} Used to request the Br anch with Link f orm of the instr uction. If absent, R14 will not be af fected by the instruction. {cond} A two-charac ter m nem onic as s hown [...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-9 DA TA PROCESSING The data proc essing ins truction is only executed if the condition is true. T he conditions are defined in T able 3-2. The ins truction encoding is shown in Figure 3-4. 31 24 27 19 15 Cond Operand2 28 16 11 12 21 [15:12] Destination register 0 = Branch 1 = Branch with link [19:1[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-10 The ins truction produc es a res ult by per form ing a spec ified arithm etic or logical operation on one or two operands. The f irst operand is alway s a r egister (R n). The s econd operand m ay be a shifted register ( Rm ) or a rotated 8 bit im m ediate value (Im m ) ac cording to the value o[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-11 CPSR FLAGS The data proc essing operations can be clas sified as logic al or arithm etic. T he logical operations (AND, EOR, T ST, TEQ, O RR, MOV, BIC, MVN) perf orm the logical action on all c orresponding bits of the operand or operands to produce the res ult. If the S bit is s et (and Rd is n[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-12 SHIFTS W hen the second operand is specif ied to be a shifted r egister, the oper ation of the barrel s hifter is controlled by the Shift f ield in the instruction. T his f ield indicates the type of shif t to be perfor med ( logical left or right, arithm etic right or rotate right). T he am oun[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-13 31 Contents of Rm Value of Operand 2 0 carry out 4 5 0 0 0 0 0 Figure 3-7. Logica l Shift Right The f orm of the s hift field which m ight be expec ted to corres pond to LSR #0 is used to encode LSR #32, which has a zero result with bit 31 of Rm as the carr y output. Logical shif t right zero is[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-14 Rotate right (ROR) operations reus e the bits which "overs hoot" in a logical shif t right operation by reintroducing them at the high end of the result, in plac e of the zeros us ed to fill the high end in logical r ight operations. For exam ple, ROR #5 is s hown in Figure 3-9. 31 Con[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-15 Register Spec ified Shift Amount Only the least significant byte of the contents of Rs is used to determ ine the shif t am ount. Rs can be any general register other than R15. If this byte is zero, the unchanged contents of Rm will be used as the second oper and, and the old value of the CPSR C [...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-16 IMM EDIATE OPERA ND ROTA T ES The im m ediate operand rotate f ield is a 4 bit unsigned integer which specif ies a shif t operation on the 8 bit imm ediate value. T his value is zero extended to 32 bits, and then subjec t to a rotate right by tw ice the value in the rotate field. T his enables m[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-17 A SSEM BLER SY NTAX • • • • MOV,MVN (single oper and instruc tions). <opcode>{cond} {S} Rd,<Op2> • • • • CMP,CMN,T EQ,TST (instruc tions which do not produce a r esult). <opcode>{cond} Rn,<Op2> • • • • AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC <op[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-18 PSR TRA NSFER (MR S, MSR) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The MRS and MSR ins tructions ar e form ed f rom a subset of the Data Proces sing operations and are im plem ented using the T EQ, TST , CMN and CMP instr uc[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-19 MSR (transfer register contents or immediate value to PSR flag bits only) Cond Source operand Pd 101001111 31 22 27 28 11 12 21 23 I1 0 00 26 25 24 0 Cond 00000000 00010 Pd 101001111 31 22 27 28 11 12 21 23 Rm MSR (transfer register contents to PSR) 43 0 Cond 000000000000 00010 Rd Ps 001111 31 2[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-20 RESERVED BITS Only tw elve bits of the PSR are def ined in ARM920T ( N,Z,C,V,I,F, T & M[4:0]) ; the rem aining bits are res erved for use in futur e versions of the proces sor. Ref er to Figure 2-6 f or a f ull description of the PSR bits. To ens ure the m axim um c om patibility between ARM[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-21 A SSEM BLY SYNT A X • • • • MRS - transf er PSR contents to a register MRS{cond} Rd,<ps r> • • • • MSR - trans fer regis ter contents to PSR MSR{cond} <ps r>,Rm • • • • MSR - trans fer r egister contents to PSR flag bits only MSR{cond} <ps rf>,Rm The m o[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-22 MULTIPLY A ND MULTIP LY-A CCUMULATE (MUL, MLA ) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The instruc tion encoding is shown in Figur e 3-12. The m ultiply and multiply-accum ulate instruc tions use an 8 bit Booth's algo[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-23 If the Op erands Are Interpreted as Signed Operand A has the value - 10, operand B has the value 20, and the res ult is -200 which is correc tly represented as 0xFFFFFF38. If the Op erands Are Interpreted as Unsigned Operand A has the value 4294967286, oper and B has the value 20 and the result [...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-24 CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. T he N (Negative) and Z (Zero) flags are s et corr ectly on the result (N is m ade equal to bit 31 of the r esult, and Z is s et if and only if the result is zero). The C (C arry) flag is set to a m[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-25 MULTIPLY LONG A ND MULTIP LY-ACCUMULA TE LONG (MULL, MLA L) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The instruc tion encoding is shown in Figur e 3-13. The m ultiply long instructions per form integer m ultiplic ation on tw[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-26 OPERA ND REST RICTIONS • R15 mus t not be used as an operand or as a destination regis ter. • RdHi, RdLo, and Rm m us t all specif y dif fer ent registers . CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. T he N and Z f lags are set correc tl[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-27 A SSEM BLER SY NTAX Table 3- 5. A ssemb ler Syntax Descriptions Mn emonic Descripti on Purpose UMULL{cond}{S} RdLo,RdHi,Rm,Rs Uns igned Multiply Long 32 x 32 = 64 UMLAL{cond}{S} RdLo,RdHi,Rm, Rs Uns igned Multiply & Ac cum ulate Long 32 x 32 + 64 = 64 SMULL{cond}{S} RdLo,RdHi,Rm, Rs Signed M[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-28 SINGLE DA TA TRANSFER (LDR, STR) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The instruc tion encoding is shown in Figur e 3-14. The s ingle data transfer instructions are used to load or s tore single bytes or words of data. T[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-29 OFFSET S A ND A UT O-INDEXING The of fset f rom the base m ay be either a 12 bit unsigned binary imm ediate value in the instruc tion, or a second register ( possibly shifted in som e way ). The of fs et m ay be added to ( U=1) or subtr acted fr om (U=0) the base register Rn. T he off set m odif[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-30 LDR from word aligned address A+3 A A+2 A+1 memory 24 16 8 0 A B C D register 24 16 8 0 A B C D LDR from address offset by 2 A+3 A A+2 A+1 memory 24 16 8 0 A B C D register 24 16 8 0 A B C D Figure 3-15. L ittle-End ian Off set A d dressing Big-Endian Configuration A by te load ( LDRB) expects t[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-31 USE OF R15 W rite-back m ust not be spec ified if R15 is spec ified as the bas e register ( Rn). W hile using R15 as the bas e register, you mus t rem ember it contains an addres s of 8 by tes on from the addres s of the c urrent instr uction. R15 mus t not be specif ied as the regis ter off set[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-32 A SSEM BLER SY NTAX <LDR| STR>{cond}{B}{T} Rd,<Address> where: LDR Load fr om mem ory into a register STR Store f rom a regis ter into m em ory {cond} Two-charac ter condition m nem onic. See T able 3-2. {B} If B is present then byte transfer, other wise word transfer {T} If T is pre[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-33 EXA M PL ES STR R1,[R2,R4]! ; Store R1 at R2+R4 ( both of which are regis ters) ; and write bac k addr ess to R2. ST R R1,[R2],R4 ; Store R1 at R2 and write back R2+R4 to R2. LDR R1,[R2,#16] ; Load R1 from contents of R2+16, but don't write back. LDR R1,[R2,R3,LSL#2] ; Load R1 from c ontent[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-34 HA LFWORD AND SIGNED DA TA TRANSFER (LDRH/STRH/LDRSB/LDRSH) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The instruc tion encoding is shown in Figur e 3-16. Thes e instructions are used to load or s tore half- words of data and [...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-35 31 27 19 15 Cond 28 16 11 12 21 23 1 20 LR n R d [3:0] Immediate Offset (Low Nibble) [6][5] S H 0 0 = SWP instruction 0 1 = Unsigned halfword 1 1 = Signed byte 1 1 = Signed halfword [11:8] Immediate Offset (High Nibble) [15:12] Source/Destination Register [19:16] Base Register [20] Load/Store 0 [...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-36 HA LFWORD LOAD A ND STORES Setting S=0 and H=1 may be used to transf er unsigned Half -words between an ARM920T r egister and m em ory. The ac tion of LDRH and ST RH instructions is influenced by the BIGEND control signal. T he two possible configur ations are desc ribed in the sec tion below. S[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-37 Big-Endian Configuration A signed byte load (LDRSB) expects data on data bus inputs 31 through to 24 if the s upplied address is on a word boundary, on data bus inputs 23 through to 16 if it is a word addr ess plus one byte, and so on. The s elected byte is placed in the bottom 8 bit of the des [...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-38 A SSEM BLER SY NTAX <LDR|STR>{cond}<H|SH|SB> Rd,<address> LDR Load fr om mem ory into a register STR Store f rom a regis ter into m em ory {cond} Two-charac ter condition m nem onic. See T able 3-2.. H T rans fer halfword quantity SB Load sign ex tended by te ( Only valid for L[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-39 EXA M PL ES LDRH R1,[R2,-R3]! ; Load R1 from the c ontents of the half word address ; c ontained in R2-R3 (both of which are regist ers) ; and write bac k addr ess to R2 ST RH R3,[R4,#14] ; Store the halfword in R3 at R14+14 but don't write back . LDRSB R8,[R2],#-223 ; Load R8 with the sign[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-40 BLOCK DA TA TRA NSFE R (LDM, STM) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The instruc tion encoding is shown in Figur e 3-18 . Block data transf er instruc tions are us ed to load (LDM) or st ore (ST M) any subset of the cu[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-41 A DDRESSING MO DES The trans fer addr esses ar e determ ined by the c ontents of the bas e register ( Rn), the pre/post bit ( P) and the up/ down bit (U). T he registers are transf erred in the order lowest to highest, so R15 ( if in the list) will always be transf erred last. T he lowest regist[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-42 Rn 1 R1 R1 2 R5 3 R1 R5 4 R7 Rn 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 Figure 3-20. Pre- Increment Addressing Rn 1 R1 R1 2 R5 3 R1 R5 4 R7 Rn 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 Figure 3-21. Po st-Decrem[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-43 Rn 1 R1 R1 2 R5 3 R1 R5 4 R7 Rn 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 Figure 3-22. Pre- Decrement Addressing USE OF T HE S BIT W hen the S bit is set in a LDM/ST M instruc tion it depends on R15 is available in the trans fer list and on the type of i[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-44 INCLUSION OF T HE BASE IN THE REGIST ER LIST W hen write-back is specif ied, the base is written back at the end of the second c ycle of the instruction. Dur ing a STM, the f irst regis ter is written out at the star t of the sec ond cycle. A STM which includes stor ing the base, with the base a[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-45 A SSEM BLER SY NTAX <LDM|STM>{cond} <FD|ED| F A|EA| IA|IB|DA|DB> Rn{!},<Rlis t>{^} where: {cond} Two charac ter condition m nem onic. See T able 3-2. Rn An ex press ion evaluating to a valid register num ber <Rlist> A lis t of regis ters and regis ter ranges enclosed in {[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-46 EXA M PL ES LDMFD SP! ,{R0,R1,R2} ; Unstack 3 r egisters. ST MIA R0,{R0-R15} ; Save all registers. LDMFD SP!,{ R15} ; R15 ← (SP), CPSR unc hanged. LDMFD SP!,{ R15}^ ; R15 ← (SP), CPSR <- SPSR_mode ; ( allowed only in pr ivileged modes ). ST MFD R13,{R0-R14}^ ; Save user mode r egs on stac[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-47 SINGLE DATA SW A P (S W P) 31 19 15 Cond 28 16 11 12 21 23 B 20 00 Rn Rd [3:0] Source Register [15:12] Destination Register [19:16] Base Register [22] Byte/Word Bit 0 = Swap word quantity 1 = Swap word quantity [31:28] Condition Field 22 00010 0000 Rm 1001 2 7 87 43 0 Figure 3-23. Sw ap Inst ruc[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-48 USE OF R15 Do not use R15 as an operand ( Rd, Rn or Rs) in a SW P ins truction. DA TA A BORTS If the addres s used f or the swap is unacc eptable to a mem ory managem ent system , the mem or y m anager c an flag the problem by driving ABORT HIGH . This c an happen on either the read or the write[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-49 SOFTWARE INTERRUPT (SWI) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The instruc tion encoding is shown in Figure 3- 24, below. 31 24 27 1111 Cond Comment Field (Ignored by Processor) 28 23 [31:28] Condition Field 0 Figure 3-24[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-50 A SSEM BLER SY NTAX SW I{cond} <ex pression> {cond} Two charac ter condition m nem onic, T able 3-2. <express ion> Evaluated and placed in the c om ment f ield (which is ignor ed by ARM920T ). Exam ples SW I ReadC ; Get nex t character f rom read str eam. SW I W r iteI+"k” ; O[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-51 COPROCESSOR D A TA OPERA TIONS (CD P) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The instruc tion encoding is shown in Figur e 3-25. This class of instruc tion is used to tell a c oprocess or to perf orm som e internal operati[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-52 INSTRUCT ION CYCLE T IMES Coprocess or data operations tak e 1S + bI incr emental c y cles to execute, where b is the num ber of c y c les spent in the coproces sor busy-wait loop. S and I are defined as sequential (S-c y c le) and internal ( I-cycle). Assemble r sy ntax CDP{cond} p#,<ex pres[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-53 COPROCESSOR DA TA TR ANSFER S (LDC, STC) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The instruc tion encoding is shown in Figure 3- 26. This class of instruc tion is used to load (LDC) or store ( STC) a s ubset of a coproces s[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-54 THE CO PROCESSOR FI ELDS The CP# f ield is used to identif y the coproces sor which is required to supply or accept the data, and a copr ocessor will only res pond if its num ber matc hes the contents of this f ield. The CRd f ield and the N bit contain infor mation f or the copr ocessor which m[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-55 A SSEM BLER SY NTAX <LDC|STC>{cond}{ L} p#,cd,<Addres s> LDC Load fr om mem ory to coprocess or STC Store f rom coproces sor to m em ory {L} W hen present perf orm long transf er (N=1) , otherwise perfor m s hort transf er (N=0) {cond} Two charac ter condition m nem onic. See T able [...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-56 COPROCESSOR REG ISTER T RANSFERS (MRC, M CR) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The instruc tion encoding is shown in Figur e 3-27. This class of instruc tion is used to c om munic ate inform ation dir ectly betw een A[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-57 TRANSFERS TO R15 W hen a coproces sor register transf er to ARM920T has R15 as the destination, bits 31, 30, 29 and 28 of the transf erred word are copied into the N, Z , C and V flags res pectively. The other bits of the transfer red word are ignored, and the PC and other CPSR bits ar e unaffec[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-58 UNDEFINED INSTRUCT ION The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The instruc tion form at is s hown in Figure 3-28. 31 27 Cond 28 25 24 011 xxxxxxxxxxxxxxxxxxxx 1 xxxx 543 0 Figure 3-28. Unde fined Instruction If the conditio[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-59 INSTRUCT ION SET EXAMPLES The f ollowing examples show way s in which the basic ARM920T instruc tions can c om bine to give effic ient code. None of these m ethods saves a great deal of execution tim e (although they may save som e), m ostly they jus t save code. USING THE CONDIT IONA L INST RUC[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-60 Division and Remainder A number of divide routines for s pecif ic applications ar e provided in sourc e form as part of the ANSI C libr ary provided with the ARM Cross Developm ent T oolkit, available f rom your supplier. A short gener al purpose divide routine follows. ; Enter with numbers in R[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-61 5. Overf low in unsigned multiply accum ulate with a 64 bit result UMULL Rl,Rh,Rm,Rn ; 3 to 6 cy c les ADDS Rl,Rl,Ra1 ; Lower accum ulate ADC Rh,Rh,Ra2 ; Upper ac cum ulate BCS overflow ; 1 c y cle and 2 register s 6. Overf low in signed multiply accum ulate with a 64 bit result SMULL Rl,Rh,Rm,R[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-62 Multiplication by 6 ADD Ra,Ra,Ra,LSL #1 ; Multiply by 3 MOV Ra,Ra,LSL#1 ; and then by 2 Multiply by 10 and add in extra num ber ADD Ra,Ra,Ra,LSL#2 ; Multiply by 5 ADD Ra,Rc,Ra,LSL#1 ; Multiply by 2 and add in next digit General rec ursive m ethod for Rb := Ra*C, C a constant: 1. If C even, say C[...]

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-63 LOA DING A WORD FROM A N UNKNOW N A LIGNM ENT ; Enter with address in Ra (32 bits) uses ; Rb, Rc result in Rd. Note d m ust be les s than c e.g. 0,1 BIC Rb,Ra,#3 ; Get word aligned address LDMIA Rb,{Rd,Rc} ; Get 64 bits containing answer AND Rb,Ra,#3 ; Cor rection f actor in bytes MOVS Rb,Rb,LSL[...]

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-64 NOTES[...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-1 4 THUMB INSTRUCTION SET THUMB INSTRUCTION SET FORMAT The thum b instruction sets are 16-bit versions of ARM ins truction sets (32-bit f orm at). T he ARM instruc tions are reduced to 16-bit ver sions.T hum b instruct ions, at the cost of versatile f unctions of the ARM instruc tion sets . T he [...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-2 FORMAT SUMM ARY The T HUMB instruc tion set f orm ats are shown in the f ollowing figure. Move Shifted register 0 0 0 000 000 000 1 0 0 010 0 0 0 0 0 1 1 1 1 1 1 1 0 0 000 1 1 1 1 1 1 1 1 0 L 0 1 1 1111 1111 1111 1 1 000 0 11 11 00 1 0 0 L 10 R 110 10 S P 1L L S H 0 0 1BL 01 H 01 B 001 11 I O p[...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-3 OPCODE SUMM ARY The following table summ arizes the THUMB inst ruction set. F or fur ther infor m ation about a particular ins truction please ref er to the sections listed in the right-m os t colum n. Table 4- 1. THUM B Instru ction Set O pcodes Mn emonic Instru ction Lo-Register Operand Hi-Re[...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-4 Table 4-1. THUM B Instruction Set Opc odes (Continued) Mn emonic Instru ction Lo-Register Operand Hi-Register Operand Condition Codes Set NEG Negate Y – Y OR R O R Y – Y POP Pop register Y – – PUSH Push register Y – – ROR Rotate Right Y – Y SBC Subtract w ith Carry Y – Y STMIA S[...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-5 FORMA T 1: MOV E SHIFTED REGISTER 15 0 0 14 10 [2:0] Destination Register [5:3] Source Register [10:6] Immediate Vale [12:11] Opcode 0 = LSL 1 = LSR 2 = ASR Offset5 65 32 Rd 00 13 12 11 Op Rs Figure 4-2. For mat 1 OPERA T ION Thes e instructions m ove a shifted value between Lo regis ters. T he[...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-6 INSTRUCT ION CYCLE T IMES All instructions in this for m at have an equivalent ARM instruc tion as shown in T able 4-2. The ins truction c ycle times for the THUMB inst ruction are identic al to that of the equivalent ARM instr uction. EXA M PL ES LSR R2, R5, #27 ; Logical shift right the c ont[...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-7 FORMA T 2: A DD/SUBTRACT 15 0 14 10 [2:0] Destination Register [5:3] Source Register [8:6] Register/Immediate Vale [9] Opcode 0 = ADD 1 = SUB [10] Immediate Flag 0 = Register operand 1 = Immediate oerand Rn/Offset3 Rd 00 13 12 11 Op Rs 98 111 65 32 0 Figure 4-3. For mat 2 OPERA T ION Thes e ins[...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-8 INSTRUCT ION CYCLE T IMES All instructions in this for m at have an equivalent ARM instruc tion as shown in T able 4-3. The ins truction c ycle times for the T HUMB instr uction are identic al to that of the equivalent ARM instr uction. EXA M PL ES ADD R0, R3, R4 ; R0 := R3 + R4 and set conditi[...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-9 FORMA T 3: MOVE/COMPARE/A DD/SUBTRA CT IMME DIATE 15 0 0 14 10 [7:0] Immediate Vale [10:8] Source/Destination Register [12:11] Opcode 0 = MOV 1 = CMP 2 = ADD 3 = SUB Offset8 Rd 00 13 12 11 Op 7 8 Figure 4-4. For mat 3 OPERA TIONS The instruc tions in this group perform oper ations between a Lo [...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-10 INSTRUCT ION CYCLE T IMES All instructions in this for m at have an equivalent ARM instruc tion as shown in T able 4-4. The ins truction c ycle times for the THUMB inst ruction are identic al to that of the equivalent ARM instr uction. EXA M PL ES MOV R0, #128 ; R0 := 128 and set condition cod[...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-11 F O R M AT 4 : AL U O P E R AT I O N S 15 0 0 14 10 [2:0] Source/Destination Register [5:3] Source Register 2 [9:6] Opcode 5 6 3 Rd 00 13 12 11 Op Rs 0 00 9 2 Figure 4-5. For mat 4 OPERA T ION The f ollowing instructions perform ALU oper ations on a Lo register pair. NOTE All instruc tions in [...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-12 INSTRUCT ION CYCLE T IMES All instructions in this for m at have an equivalent ARM instruc tion as shown in T able 4-5. The ins truction c ycle times for the THUMB inst ruction are identic al to that of the equivalent ARM instr uction. EXA M PL ES EOR R3, R4 ; R3 := R3 EOR R4 and set c onditio[...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-13 FORMA T 5: HI-REGISTER OPERATIONS/BRA NCH EXCHANGE 15 0 0 14 10 [2:0] Destination Register [5:3] Source Register [6] Hi Operand Flag 2 [7] Hi Operand Flag 1 [9:8] Opcode 65 32 Rd/Hd 00 13 12 11 Op Rs/Hs 0 00 9 8 7 H1 H2 Figure 4-6. For mat 5 OPERA T ION There are four sets of instructions in t[...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-14 Table 4-6. Summary of Format 5 Instructions (Continued) Op H1 H2 THUMB assemb ler ARM equiv alent Description 01 1 1 CMP Hd, Hs CMP Hd, Hs Compar e two registers in the range 8-15. Set the condition code f lags on the result. 10 0 1 MOV Rd, Hs MOV Rd, Hs Move a value from a r egister in the ra[...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-15 EXA M PL ES Hi-Register Operations ADD PC, R5 ; PC := PC + R5 but don't set the condition codes . CMP R4, R12 ; Set the condition codes on the result of R4 - R12. MOV R15, R14 ; Move R14 (LR) into R15 (PC) but don't set the condition codes , eg. return f rom subroutine. Branch and Ex[...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-16 FORMA T 6: PC-RELA TIVE LOA D 15 0 0 14 10 [7:0] Immediate Value [10:8] Destination Register Word 8 00 13 12 11 Rd 0 0 87 Figure 4-7. For mat 6 OPERA T ION This instruction loads a word fr om an addr ess s pecified as a 10-bit im m ediate off set fr om the PC. T he T HUMB assem bler s y ntax i[...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-17 INSTRUCT ION CYCLE T IMES All instruc tions in this f orm at have an equivalent ARM instr uction. T he instruc tion cy c le times for the THUMB instruc tion are identical to that of the equivalent ARM instruct ion. EXA M PL ES LDR R3,[PC,#844] ; Load into R3 the word found at the address f orm[...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-18 FORMA T 7: LOAD /STORE WITH REGISTER OFFSET [2:0] Source/Destination Register [5:3] Base Register [8:6] Offset Register [10] Byte/Word Flag 0 = Transfer word quantity 1 = Transfer byte quantity [11] Load/Store Flag 0 = Store to memory 1 = Load from memory 15 0 0 14 10 65 32 Rd 10 13 12 11 Rb 1[...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-19 OPERA T ION Thes e instructions transf er byte or word values between registers and m em ory. Memory addresses are pre- indexed using an of fset r egister in the range 0- 7. The T HUMB assem bler syntax is shown in Table 4-8. Table 4- 8. Summary of Format 7 Inst ructions L B THUMB assembler A [...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-20 FORMA T 8: LOA D/STORE S IGN-E X TENDED BYTE/HALFWORD [2:0] Destination Register [5:3] Base Register [8:6] Offset Register [10] Sign-Extended Flag 0 = Operand not sing-extended 1 = Operand sing-extended [11] H Flag 15 0 0 14 10 65 32 Rd 10 13 12 11 Rb 1 HS 98 Ro 1 Figure 4-9. For mat 8 OPERA T[...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-21 INSTRUCT ION CYCLE T IMES All instructions in this for m at have an equivalent ARM instruc tion as shown in T able 4-9. The ins truction c ycle times for the THUMB inst ruction are identic al to that of the equivalent ARM instr uction. EXA M PL ES STRH R4, [R3, R0] ; Store the lower 16 bits of[...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-22 FORMA T 9: LOAD /STORE WITH IMMEDIA TE OFFSET [2:0] Source/Destination Register [5:3] Base Register [10:6] Offset Register [11] Load/Store Flag 0 = Store to memory 1 = Load from memory [12] Byte/Word Flad 0 = Transfer word quantity 1 = Transfer byte quantity 15 0 0 14 10 65 32 Rd 11 13 12 11 R[...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-23 OPERA T ION Thes e instructions transf er byte or word values between registers and m em ory using an imm ediate 5 or 7-bit off set. The T HUMB ass em bler syntax is shown in Table 4-10. Table 4- 10. Summary of Format 9 Inst ructions L B THUMB assembler A RM equ ivalent Description 0 0 STR Rd,[...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-24 FORMA T 10: LOAD/STORE HA LFW ORD [2:0] Source/Destination Register [5:3] Base Register [10:6] Immediate Value [11] Load/Store Flag 0 = Store to memory 1 = Load from memory 15 0 0 14 10 65 32 Rd 10 13 12 11 Rb 0 L Offset5 Figure 4-11. Fo rmat 10 OPERA T ION Thes e instructions trans fer half w[...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-25 INSTRUCT ION CYCLE T IMES All instruc tions in this f orm at have an equivalent ARM instr uction as s hown in Table 4-11. T he ins truction cycle times for the THUMB inst ruction are identic al to that of the equivalent ARM instr uction. EXA M PL ES STRH R6, [R1, #56] ; Stor e the lower 16 bit[...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-26 FORMA T 11: SP-RELATIVE LOA D/STORE [7:0] Immediate Value [10:8] Destination Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory 15 0 1 14 10 00 13 12 11 Word 8 1 L Rd 7 8 Figure 4-12. Fo rmat 11 OPERA T ION The instruc tions in this gr oup per form an SP-relative load or s t[...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-27 INSTRUCT ION CYCLE T IMES All instruc tions in this f orm at have an equivalent ARM instr uction as s hown in Table 4-12. T he ins truction cycle times for the THUMB inst ruction are identic al to that of the equivalent ARM instr uction. EXA M PL ES STR R4, [SP,#492] ; Store the contents of R4[...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-28 FORMA T 12: LOA D A DDRESS [7:0] 8-bit Unsigned Constant [10:8] Destination Register [11] Source 0 = PC 1 = SP 15 0 1 14 10 01 13 12 11 Word 8 0 SP Rd 7 8 Figure 4-13. Fo rmat 12 OPERA T ION Thes e instr uctions calculate an addres s by adding a 10-bit constant to either the PC or the SP, and [...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-29 INSTRUCT ION CYCLE T IMES All instruc tions in this f orm at have an equivalent ARM instr uction as s hown in Table 4-13. T he ins truction cycle times for the THUMB inst ruction are identic al to that of the equivalent ARM instr uction. EXA M PL ES ADD R2, PC, #572 ; R2 := PC + 572, but don&a[...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-30 FORMA T 13: A DD OFFSE T TO S TACK POINTER [6:0] 7-bit Immediate Value [7] Sign Flag 0 = Offset is positive 1 = Offset is negative 15 0 1 14 10 01 13 12 11 SWord 7 1 0 0 7 8 9 6 00 S Figure 4-14. Fo rmat 13 OPERA T ION This instruction adds a 9-bit signed cons tant to the stack pointer . T he [...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-31 FORMA T 14: PUSH/POP REGISTERS [7:0] Register List [8] PC/LR Bit 0 = Do not store LR/Load PC 1 = Store LR/Load PC [11] Load/Store Bit 0 = Store to memory 1 = Load from memory 15 0 1 14 10 01 13 12 11 Rlist 1 L 0 7 8 9 1R Figure 4-15. Fo rmat 14 OPERA T ION The ins tructions in this group allow[...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-32 INSTRUCT ION CYCLE T IMES All instruc tions in this f orm at have an equivalent ARM instr uction as s hown in Table 4-15. T he ins truction cycle times for the THUMB inst ruction are identic al to that of the equivalent ARM instr uction. EXA M PL ES PUSH {R0- R4,LR} ; Store R0,R1,R2,R3,R4 and [...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-33 FORMA T 15: MULTIPLE LOAD /STORE [7:0] Register List [10:8] Base Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory 15 0 1 14 10 10 13 12 11 Rlist 0 L 7 8 Rb Figure 4-16. Fo rmat 15 OPERA T ION Thes e instruct ions allow multiple loading and s toring of Lo r egisters . The T[...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-34 FORMA T 16: CONDITIONA L BRANCH [7:0] 8-bit Signed Immediate [11:8] Condition 15 0 1 14 10 13 12 11 SOffset 8 1 7 8 Cond Figure 4-17. Fo rmat 16 OPERA T ION The instruc tions in this group all perf orm a conditional Branc h depending on the state of the CPSR c ondition codes. T he br anch of f[...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-35 Table 4-17. The Conditional Branch Instructions (Continued) L THUM B assembler A RM equiv alent Description 1001 BLS label BLS label Branch if C clear or Z s et (unsigned lower or same) 1010 BGE label BGE label Branch if N s et and V set, or N c lear and V clear (greater or equal) 1011 BLT lab[...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-36 FORMA T 17 : SOFTWARE INTERRUPT [7:0] Comment Field 15 0 1 14 10 13 12 11 Value 8 1 7 8 10 9 1111 Figure 4-18. Fo rmat 17 OPERA T ION The SW I instr uction perfor ms a software interrupt. O n taking the SW I, the proces sor switches into ARM state and enters Supervis or (SVC) m ode. The T HUMB[...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-37 FORMA T 18 : UNCONDITIONA L BRANCH [10:0] Immediate Value 15 0 1 14 11 13 12 11 Offset11 0 10 0 Figure 4-19. Fo rmat 18 OPERA T ION This ins truction perform s a PC-relative Branch. The T HUMB assembler sy ntax is shown below. The branch off set mus t take ac count of the prefetch oper ation, [...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-38 FORMA T 19: LONG BRA NCH W ITH LINK [10:0] Long Branch and Link Offset High/Low [11] Low/High Offset Bit 0 = Offset high 1 = Offset low 15 0 1 14 11 13 12 11 Offset 1 10 H Figure 4-20. Fo rmat 19 OPERA T ION This form at s pecifies a long branch with link. The as sem bler splits the 23-bit two[...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-39 INSTRUCT ION CYCLE T IMES This instruct ion form at does not have an equivalent ARM ins truction. Table 4- 20. The BL Instructio n L THUM B assembler A RM equiv alent Description 0 BL label none LR := PC + Of fs etHigh << 12 1 tem p := nex t instruction addr ess PC := LR + Off setLow <[...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-40 INSTRUCTION SET EXAMPLES The f ollowi ng ex amples s how ways in which the THUMB instr uctions ma y be used to generate s mall and ef ficient code. Each exam ple als o shows the ARM equivalent so these m ay be compar ed. MULT IPLICA TION BY A CONSTA NT USING SHIFTS AND A DDS The f ollowing ins[...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-41 GENERA L PURPOSE SIGNED DIVIDE This exam ple shows a general purpos e signed divide and rem ainder routine in both T hum b and ARM code. Thumb code ;signed_divide ; Signed divide of R1 by R0: r eturns quotient in R0, ; remainder in R1 ;Get abs value of R0 into R3 ASR R2, R0, #31 ; Get 0 or -1 [...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-42 Now fix up the signs of the quotient (R0) and r emainder (R1) POP { R2, R3} ; G et dividend/divisor signs back EOR R3, R2 ; Result sign EOR R0, R3 ; Negate if result s ign = - 1 SUB R0, R3 EOR R1, R2 ; Negate r emainder if dividend sign = - 1 SUB R1, R2 MOV pc , lr A RM Code signed_divide ; Ef[...]

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-43 DIVISION BY A CONST ANT Division by a constant can often be perf orm ed by a short fixed sequenc e of shif ts, adds and s ubtracts. Here is an exam ple of a divide by 10 routine based on the algorithm in the ARM Cook book in both Thum b and ARM code. Thumb Code udiv10 ; Tak e argum ent in a1 r[...]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-44 NOTES[...]

S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER 5-1 5 MEMORY CONTROLLER OVERVIEW The S3C2440A m em ory controller provides mem or y c ontrol signals that ar e required f or external m em ory access. The S3C2440A has the following features : — Little/Big endian (s electable by a software) — Address space: 128Mbytes per bank ( total 1GB/8 bank s)[...]

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-2 0x0000 _000 0 0x0800 _000 0 0x1000 _000 0 0x1800 _000 0 0x2000 _000 0 0x2800 _000 0 0x3000 _000 0 0x3800 _000 0 0x4000 0_00 00 SROM / SDRA M (nGCS7) SROM / SDRA M (nGCS6) SRO M (nGCS5) SRO M (nGCS4) SRO M (nGCS3) SRO M (nGCS2) SRO M (nGCS1) Boo t In t e r na l SR AM (4KB) 128MB 128MB 128MB 128MB 12[...]

S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER DEC.13, 2002 5-3 FUNCTION DESCRIPTION BA NK0 BUS WIDT H The data bus of BANK0 (nGC S0) should be conf igured with a width as one of 16-bit and 32-bit ones . Because the BANK0 works as the booting ROM bank (m ap to 0x0000_0000), the bus width of BANK0 should be determ ined before the f irst ROM ac cess[...]

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-4 SDRA M BANK A DDRESS PIN CO NNECTIO N EXA M PLE Table 5- 2. SDRA M Bank Address Configuration Example Bank Size Bus Width Base Component M emory Configuration Bank A ddress 2MBy te x8 16Mbit (1M x 8 x 2Bank) x 1 A20 x16 (512K x 16 x 2B) x 1 4MB x16 (1M x 8 x 2B) x 2 A21 x16 (1M x 8 x 2B) x 2 8MB x1[...]

S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER DEC.13, 2002 5-5 nWAIT PIN OPERA T ION If the W AIT bit(W Sn bit in BW SCON) cor responding to each m em ory bank is enabled, the nO E duration should be prolonged by the external nW AIT pin while the m em ory bank is active. nW AIT is chec ked f rom tacc- 1. nOE will be de-asser ted at the next clock[...]

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-6 nXBREQ/nXBA CK Pin Operation If nXBREQ is asser ted, the S3C2440A will respond by low ering nXBACK. If nXBACK=L, the addres s/data bus and me mor y control signals are in Hi-Z state as shown in Table 1- 1. After nX BREQ is de-as serted, the nX BACK will also be de-ass erted. HCLK SCKE, A[24:0] D[31[...]

S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER DEC.13, 2002 5-7 ROM M emory Interface Examples A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7 nWE nOE nGCSn A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE Figure 5-4. M emory Interface w ith 8- bit ROM A1 A2 A3 A4 A5 A6[...]

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-8 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE D0 D1 D2 D3 D4 D5 D6 D7 nWBE0 nOE nGCSn A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14[...]

S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER DEC.13, 2002 5-9 SRA M M emory Interface Examples A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCS nWE nOE[...]

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-10 SDRA M M emory Interface Examples A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 BA0 BA1 LDQM UDQM A21 A22 DQM0 DQM1 SCKE SCLK SCKE SCLK nSCS0 n[...]

S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER DEC.13, 2002 5-11 PROGRAMM A BL E A CCESS CY CLE Tcoh Tcos Tacs HCLK A[24:0] nGCS nOE nWE nWBE D[31:0](R) D[31:0] (W) Tacc Tacp Tcah Tacs = 1 cycle Tcos = 1 cycle Tacc = 3 cycles Tacp = 2 cycles Tcoh = 1 cycle Tcah = 2 cycles Figure 5-12. S3C2440A nGCS Timing Diag ram[...]

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-12 MCLK SCKE nSCS nSCAS ADDR A10/AP RA nSRAS BA DATA (CL2) DATA (CL3) nWE DQM Trp Trcd RA Ca Da Da BA BA Cb Cc Cd Ce Db Dc Dd De Db Dc Dd De BA BA BA BA BA Bank Precharge Row Active Write Read (CL = 2, CL = 3, BL = 1) Trp = 2 cycle Tcas = 2 cycle Trcd = 2 cycle Tcp = 2 cycle Figure 5-13. S3C2440A SDR[...]

S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER DEC.13, 2002 5-13 BUS WIDTH & W A IT CONTROL REGIST ER (BWSCON) Register Address R/W Description Reset Value BW SCON 0x48000000 R/W Bus width & wait status contr ol register 0x000000 BWSCON Bit Descrip tion Initial state ST7 [31] Determines SRAM f or using UB/LB f or bank 7. 0 = Not using UB/L[...]

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-14 BUS WIDTH & W A IT CONTROL REGIST ER (BWSCON) (Continued) W S2 [10] Determ ines W AIT status f or bank 2. 0 = W AIT disable 1 = W AIT enable 0 DW 2 [9:8] Deter m ines data bus width for bank 2. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = r eserved 0 ST1 [7] Determines SRAM f or using UB/LB f or b[...]

S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER DEC.13, 2002 5-15 BA NK CONT ROL REGISTER (BANKCONn: nGCS0-nGCS5) Register Address R/W Description Reset Value BANKCON0 0x48000004 R/W Bank 0 contr ol register 0x 0700 BANKCON1 0x48000008 R/W Bank 1 contr ol register 0x 0700 BANKCON2 0x4800000C R/W Bank 2 contr ol register 0x 0700 BANKCON3 0x48000010 [...]

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-16 BA NK CONT ROL REGISTER (BANKCONn: nGCS6-nGCS7) Register Address R/W Descrip tion Reset Value BANKCON6 0x4800001C R/W Bank 6 control regis ter 0x18008 BANKCON7 0x48000020 R/W Bank 7 control r egister 0x18008 BA NKCONn Bit Description Initial State MT [16:15] Determ ine the m em ory ty pe for bank6[...]

S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER DEC.13, 2002 5-17 REFRESH CONTROL REGIST ER Register Address R/W Descript ion Reset Value REFRESH 0x48000024 R/W SDRAM refres h control regis ter 0xac0000 REFRESH Bit Description Initial Stat e REFEN [23] SDRAM Ref resh Enable 0 = Disable 1 = Enable (self or CBR/auto ref resh) 1 TREFMD [22] SDRAM Refr[...]

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-18 BA NKSIZE REGIST ER Register Address R/W Descriptio n Reset Value BANKSIZE 0x 48000028 R/W Flexible bank size register 0x 0 BA NKSIZE Bit Descriptio n Initial State BURST_EN [7] ARM cor e burst operation enable. 0 = Disable burst operation. 1 = Enable burst operation. 0 Reserved [6] Not used 0 SCK[...]

S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER DEC.13, 2002 5-19 SDRA M M ODE REGIST ER SET REGIST ER (M RSR) Register Address R/W Descriptio n Reset Value MRSRB6 0x4800002C R/W Mode register set register bank 6 xxx MRSRB7 0x48000030 R/W Mode register set register bank7 xxx MR SR Bit Descrip tion In itial St ate Reserved [11:10] Not used - W BL [9[...]

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-20 NOT ES[...]

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-1 6 NA ND FLA SH CONTORLLER OVERVIEW In recent tim es, NO R flash m em ory gets high in price while an SDRAM and a NAND flash m em ory is com paratively economical , m otivating s ome us ers to exec ute the boot code on a NAND f lash and execute the main c ode on an SDRAM. S3C2440A boot code can [...]

NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-2 BLOCK DIA GRAM zmy ljjGn U z Gz O[riGzyhtP z Gz  j  SYST EM BUS uhuk Gmshz o p CLE ALE nFCE nFRE nFWE FRnB I/O0 - I/O 15 hoi zGpVm j GM z?[...]

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-3 PIN CONFIGURA T ION  OM[1:0] = 00: Enable NAND f lash m em ory boot  NCON : NAND f lash m em ory selection(Norm al / Advance) 0: Norm al NAND flash(256W or ds/512Bytes page siz e, 3/4 address c y c le) 1: Advance NAND flas h(1KW ords/2KBytes page size, 4/5 address cycle)  GPG 13 : NAND[...]

NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-4 NA ND FLASH MEMORY TIM ING HCLK CLE / ALE nW E T AC LS T WR PH 0 TWR P H 1 DATA COMMAND / A DDRESS Figure 6-3. CLE & A LE T iming (TACLS=1, TWRPH0=0, TWRPH1=0) HCLK nW E / nRE DATA DAT A TW RPH0 T W RPH1 Figure 6-4 nWE & nRE T iming (TWRPH0=0, TWRPH1=0)[...]

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-5 SOFTWA RE MODE S3C2440A supports only sof tware mode acces s. Using this mode, you can com pletely access the NAND flas h mem ory. The NAND Flash Contr oller supports direct acc ess interf ace with the NAND flash m em ory. 1) W riting to the c omm and r egister = the NAND Flash Mem or y c om ma[...]

NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-6 Data Register Configur ation 1) 16-b it NA ND F lash M emory Interface A . W ord A ccess Register Endian Bit [31:24] Bit [23: 16] Bit [15:8] Bit [7:0] NFDATA Little 2 nd I/O[15:8] 2 nd I/O [ 7:0] 1 st I/O[15:8] 1 st I/O[ 7:0] NFDATA Big 1 st I/O[15:8] 1 st I/O [ 7:0] 2 nd I/O[15:8] 2 nd I/O[ 7[...]

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-7 ECC(Error Correctio n Code) NAND Flash controller consis ts of f our ECC (Err or Correc tion Code) m odules. T he two ECC modules ( one for data[7:0] and the other for data[15:8]) can be used for (up to) 2048 by tes ECC Parity code generation, and the others(one f or data[7:0] and the other f o[...]

NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-8 ECC MO DULE FEA T URES ECC generation is contr olled by the ECC Loc k ( MainECCLock , SpareECCLock ) bit of the Control register . ECC Register Configur ation (Little / Big Endian) 1) 16-b it NA ND F lash M emory Interface Register Bit [ 31:24] Bit [23:16] Bit [15:8] Bit [7:0] NFMECCD0 2 nd EC[...]

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-9 NA ND FLASH MEMORY M A PPING Not Used SFR Area Not Used BootSRAM (4KB) 0xFFFF_FFFF 0x6000_0000 0x4800_0000 0x4000_0000 SFR Area Not Used SDRAM (BANK7, nGC S7) 0x3800_0000 SDRAM (BANK7, nGC S7) SDRAM (BANK6, nGC S6) 0x3000_0000 SDRAM (BANK6, nGC S6) SROM (BANK5, nGC S5) SR OM (BANK5, nGC S5) 0x2[...]

NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-10 NA ND FLASH MEMORY CONFIGURA T ION I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 R/ B WE ALE CLE CE RE RnB nFW E ALE CLE nFCE nFRE DATA[ 7] DATA[ 6] DATA[ 5] DATA[ 4] DATA[ 3] DATA[ 2] DATA[ 1] DATA[ 0] Figure 6-1 A 8-bit NA ND Flash Memo ry Interface W hen y ou write the addres s, the sam e addres[...]

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-11 Nand Flash configuration Register Register A ddress R/W Descriptio n Reset Value NFCONF 0x4E000000 R/W NAND Flash Configuration register 0x0000100X NFCONF Bit Description Init ial State Reserved [15:14] Reserved - TACLS [13:12] CLE & ALE duration setting value (0~3) Duration = HCLK x TACLS[...]

NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-12 AdvFlash (Read only) [3] Advance NAND f lash m em ory for auto-booting 0: Support 256 or 512 byte/page NAND flash mem ory 1: Support 1024 or 2048 byte/page NAND flash mem ory This bit is determ ined by NCON0 pin status during res et and wake-up f rom sleep m ode. H/W Set (NCON0) PageSize (Rea[...]

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-13 CONTROL REGIST ER Register A ddress R/W Descriptio n Reset Value NFCONT 0x4E000004 R/W NAND Flash control register 0x0384 NFCONT Bit Descript ion In itial Stat e Reserved [14:15] Reserved 0 Lock -tight [13] Lock -tight conf iguration 0: Disable lock -tight 1: Enable lock- tight, Once this bit [...]

NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-14 0: Unlock Spare ECC 1: Lock Spare ECC Spare area ECC status register is NFSECC(0x4E000034), MainECCLock [5] Lock Main data area ECC generation 0: Unlock Main data area ECC generation 1: Lock Main data area ECC generation Main area ECC status r egister is NFMECC0/1(0x4E00002C/30), 1 InitECC [4[...]

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-15 COMM AND REGISTER Register A ddress R/W Descriptio n Reset Value NFCMMD 0x4E000008 R/W NAND Flash com m and set r egister 0x00 NFCM MD Bit Description Initial State Reserved [15:8] Reserved 0x00 NFCMMD [7:0] NAND Flash m em ory comm and value 0x00 A DDRESS REG ISTER Register A ddress R/W Descr[...]

NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-16 MAIN DA T A AREA REGIST ER Register A ddress R/W Descriptio n Reset Value NFMECCD0 0x4E000014 R/W NAND Flash ECC 1 st and 2 nd register f or m ain data read Note: Refer to ECC M ODULE FEA TURES in Page 6-8. 0x00000000 NFMECCD1 0x4E000018 R/W NAND Flash ECC 3 rd 4 th register f or m ain data r[...]

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-17 SPA RE AREA ECC REGIST ER Register A ddress R/W Descriptio n Reset Value NFSECCD 0x 4E00001C R/W NAND Flash ECC(Error Correction Code) regis ter for spare area data read 0x00000000 NFSECCD Bit Description Initial State ECCData1_1 [31:24] 2 nd ECC f or I/O[15:8] 0x00 ECCData1_0 [23:16] 2 nd ECC[...]

NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-18 NFCON STATUS REGISTER Register A ddress R/W Descriptio n Reset Value NFSTAT 0x4E000020 R/W NAND Flash operation status regis ter 0xX X00 NFSTAT Bit Description In itial State Reserved [7] Reserved X Reserved [4:6] Reserved 0 IllegalAcces s [3] Once Sof t Lock or Lock -tight is enabled, The il[...]

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-19 ECC0/1 STATUS REGISTER Register A ddress R/W Description Reset Value NFESTAT 0 0x 4E000024 R/W NAND F lash ECC Status regist er for I/O [7:0] 0x00000000 NFESTAT 1 0x 4E000028 R/W NAND F lash ECC Status regist er for I/O [15:8] 0x00000000 NFESTAT0 Bit Description Initial Stat e SErrorDataNo [24[...]

NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-20 MAIN DA T A AREA ECC0 STATUS REGISTER Register A ddress R/W Descriptio n Reset Value NFMECC0 0x4E00002C R NAND Flash ECC register for data[7:0] 0xXXXXXX NFMECC1 0x4E000030 R NAND Flash ECC register for data[15:8] 0xXXXXXX NFM ECC0 Bit Description Initial State MECC0_3 [31:24] ECC3 f or data[7[...]

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-21 BLOCK ADDRESS REGISTER Register A ddress R/W Descriptio n Reset Value NFSBLK 0x4E000038 R/W NAND Flash progr am mable s tart block address 0x000000 NFEBLK 0x 4E00003C R/W NAND F lash program m able end block address Nand Flash can be progr am med between star t and end address. W hen the Soft [...]

NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-22 The NFSLK and NF EBLK can be changed while Soft loc k bit( NFCONT [12]) is enabled. But cannot be c hanged when Lock-tight bit( NFCONT [13]) is set. when Lock-tight =1 or SoftLock=1 NA ND fl ash memory Locked area (Read only) Prorammable/ Readable Ar e a Locked area (Read only) NFSBLK A ddres[...]

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT 7 - 1 7 CLOCK & POWER MA NA GEMENT OVERVIEW The Cloc k & Power m anagem ent block consis ts of thr ee parts: Cloc k c ontrol, USB control, and Power contr ol. The Cloc k c ontrol logic in S3C2440A can gener ate the required cloc k s ignals including FCLK f or CPU, HCLK for the AHB bu[...]

CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 2 FUNCTIONA L DESCRIP TION CLOCK A RCHIT ECTURE Figure 7-1 shows a bloc k diagr am of the clock arc hitecture. T he m ain cloc k source com es from an exter nal cr y stal (XT Ipll) or an external cloc k ( EXT CLK). T he clock generator inc ludes an oscillator (Os cillation Am plifier )[...]

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 3 Nand Fl a sh Contro ller OSC MPLL UPLL CLKCNTL FCL K HDIVN PDIVN Mpll Contr ol Signal Upl l POWC NTL FH P USBCNTL Test mo de OM[1:0 ] Bus Contr oller Memory Contr oller Arbitr ation DMA 4 ch WDT I 2 S SDI ADC UART(0, 1,2) PWM I 2 C GPIO RTC SPI(0, 1) USB Dev ice ARM92 0T Interru pt C[...]

CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 4 PHA SE LOCKED LOOP (P LL) The MPLL within the clock generator, as a circuit, s y nc hronizes an output signal with a referenc e input s ignal in frequenc y and phase. In this application, it inc ludes the following basic block s as s hown in Figure 7-2: the Voltage Controlled Oscilla[...]

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 5 Divider P Loop Filter Fin M[7:0] S[1:0] PFD Divider M P[5:0] F vco PUMP VCO Divider S F ref MPLL,U PLL R C Internal C LF External MPLLCAP, UPLLCAP Figure 7-2. PLL (Phase-Locked Loop) Block Diagram EXT CLK XTIp ll XTOpl l EXT CLK XTIp ll XTOpl l External OSC a) X-TAL Oscillation (OM[3[...]

CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 6 CLOCK CONTROL LOGIC The Clock Control Logic determ ines the clock sourc e to be used, i.e., the PLL clock (Mpll) or the direct ex ternal clock (XT Ipll or EXT CLK). W hen PLL is configur ed to a new frequency value, the clock control logic disables the FCLK until the PLL output is s [...]

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 7 Change PLL Se ttings In Normal Oper ation M ode During the operation of the S3C2440A in NO RMAL m ode, the user can change the fr equency by writing the PMS value and the PLL lock tim e will be automatically inserted. During the lock tim e, the cloc k is not supplied to the internal [...]

CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 8 FCLK, HCLK, and PCLK FCLK is used by ARM920T. HCLK is used f or AHB bus, which is us ed by the ARM920T, the m em ory controller, the interr upt controller, the LCD controller, the DMA and USB hos t block . PCLK is used f or APB bus, which is us ed by the peripherals s uch as W DT , I[...]

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 9 NOTE 1. CLKDIVN s hould be set car efully not to exceed the limit of HCLK and PCLK. 2. If HDIVN is not 0, the CPU bus m ode has to be changed from the f ast bus m ode to the asynchronous bus mode us ing following instruc tions(S3C2440 does not s upport synchronous bus m ode). MMU_Set[...]

CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 10 POWER MANA GEM ENT The Power Managem ent block contr ols the system c locks by software for the reduc tion of power cons umption in the S3C2440A. Thes e schem es are r elated to PLL, clock control logic s (FCLK, HCLK, and PCLK) and wakeup signals. Figure 7- 7 shows the clock distr i[...]

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 11 IDLE SLEEP NORMAL (SLOW _BIT=0) SLOW (SLOW _BIT=1) IDLE_BIT=1 Interrupts, EINT[0:23], RTC alarm SLEEP BIT=1 EINT[15:0], RTC alarm RESET Figure 7-8. Po wer M anagemen t State Diag ram Tabl e 7-2. Clock and Po wer Stat e in Each Pow er M ode Mode A RM 920T AHB Modules (1) /WDT Pow er [...]

CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 12 NORMAL Mode In Normal m ode, all peripherals and the basic blocks including power m anagement bloc k, the CPU core, the bus controller, the mem or y c ontroller, the interr upt controller, DMA, and the external m aster m ay operate com pletely. But, the clock to each peripher al, ex[...]

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 13 Users can change the frequency by enabling SLOW m ode bit in CLKSLOW register in PLL on state. T he SLOW clock is generated dur ing the SLOW m ode. Figure 7-11(Pleas e check the figure correc tly) s hows the timing diagram . Mpl l Slow mode disable FCLK Slow m ode enable SLOW _BIT D[...]

CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 14 If the user switches fr om SLOW m ode to Norm al m ode by disabling SLOW _BIT and MPLL_OF F bit sim ultaneously in the CLKSLO W register , the f requency is changed just af ter the PLL lock tim e. Figure 7-13 (Please chec k f or the f igure number correc tly) shows the timing diagra[...]

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 15 SLEEP M ode The bloc k dis connects the inter nal power. So, there occurs no power consum ption due to CPU and the internal logic exc ept the wake-up logic in this m ode. Activating the SLEEP m ode requires two independent power sourc es. One of the two power sources supplies the po[...]

CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 16 Follow the Pro cedure to W ake-up f rom SLEEP mode 1. T he internal r eset signal will be asser ted if one of the wake-up sour ces is issued. It’s ex actly same with the case of the assert ion of the exter nal nRESET pin. T his res et duration is determ ined by the internal 16-bit[...]

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 17 Power Control of VDDi and VDDiar m In SLEEP mode, VDDi, VDDiar m , VDDMPLL and VDDUPLL will be turned off, which is controlled by PW REN pin. If PW REN signal is ac tivated(H), VDDi and VDDiarm are s upplied by an exter nal voltage r egulator. If PW REN pin is inactive (L) , the VDD[...]

CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 18 Signaling EINT[15:0] for Wakeup The S3C2440A c an be woken up fr om SLEEP mode only if the following conditions are m et. a) Level signals (H or L) or edge s ignals (rising, f alling or both) are as serted on EINT n input pin. b) The EINTn pin has to be c onfigured as EINT in the G [...]

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 19 Outp ut Po rt Stat e and SLEEP M od e The output port s hould have a proper logic level in power off m ode, which mak es the current consum ption minim ized. If there is no load on an output port pin, H level is pref erred. If output is L, the cur rent will be consum ed through the [...]

CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 20 CLOCK GENER ATOR & POWER MA NAGEM ENT SPECIA L REGISTER LOCK TIM E COUNT REGIST ER (LOCKT IM E) Register Address R/W Descripti on Reset Value LOCKTIME 0x4C000000 R/W PLL l oc k tim e count register 0x FFFFFFFF LOCKT IME Bit Description Initial State U_LTIME [31:16] UPLL loc k ti[...]

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 21 PLL CONTROL REGIST ER (M PLLCON & UPLLCON) Register Address R/W Descripti on Reset Value MPLLCON 0x4C000004 R/W MPLL conf iguration regis ter 0x00096030 UPLLCON 0x4C000008 R/W UPLL conf iguration regis ter 0x 0004d030 PLLCON Bit Description Initial Stat e MDIV [19:12] Main divid[...]

CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 22 CLOCK CONTROL REGIST ER (CLKCON) Register Address R/W Descripti on Reset Value CLKCON 0x4C00000C R/W Clock generator control register 0xFFFFF0 CLKCON Bit Descript ion In itial State AC97 [20] Control PCLK into AC97 bloc k. 0 = Disable, 1 = Enable 1 Camer a [19] Control HCLK into Cam[...]

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 23 CLOCK SLOW CONTROL (CLKSLOW ) REGISTER Register Address R/W Descripti on Reset Value CLKSLOW 0x 4C000010 R/W Slow clock control r egister 0x00000004 CLKSLOW Bit Descrip tion Init ial State UCLK_ON [7] 0: UCLK ON (UPLL is also tur ned on and the UPLL lock time is inserted autom atica[...]

CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 24 CLOCK DIVIDER CONTROL (CLKDIVN) REGISTER Register Address R/W Descripti on Reset Value CLKDIVN 0x4C000014 R/W Cloc k divider control regis ter 0x00000000 CLKDIVN Bit Descriptio n Initial State DIVN_UPLL [3] UCLK select register( UCLK m ust be 48MHz for USB) 0: UCLK = UPLL clock 1: U[...]

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 25 CA M ERA CLOCK DIVIDER ( CA M DIVN) REGIST ER Register Address R/W Descript ion Reset Value CAMDIVN 0x 4C000018 R/W Cam era c lock divider register 0x00000000 CA M DIVN Bit Descripti on Initial Stat e DVS_EN [12] 0:DVS OFF ARM core will run norm ally with FCLK(MPLLout). 1:DVS ON ARM[...]

S3C2440A RISC MICROPROC ESSOR DMA 8-1 8 DMA OVERVIEW The S3C2440A s upports f our-channel DMA c ontroller located between the system bus and the peripheral bus. Each channel of DMA controller c an perfor m data movem ents between devices in the sy s tem bus and/or peripheral bus with no restr ictions. In other words , each channel can handle the f [...]

DMA S3C2440A RISC MICROPROCESSO R 8-2 DMA REQUEST SOURC ES Each channel of the DMA controller can select one of the DMA reques t source am ong four DMA sourc es, if H/W DMA request m ode is s elected by DCON register. (Note that if S/W request m ode is selected, this DMA request sources have no m eaning at all.) Table 8- 1 shows four DMA sources fo[...]

S3C2440A RISC MICROPROC ESSOR DMA 8-3 EXTERNAL DMA DREQ/DACK PROTOCOL There are thr ee ty pes of exter nal DMA request/ac knowledge protocols (Single servic e Demand, Single s ervice Handshak e and W hole service Handshak e m ode). Eac h ty pe def ines how the signals like DMA request and ack nowledge are related to these protoc ols. Basic DMA Timi[...]

DMA S3C2440A RISC MICROPROCESSO R 8-4 Demand/Handshake M ode Co mparison Demand and Hands hake m odes are related to the protocol between XnX DREQ and XnX DACK. Figure 8-2 s hows the diff erences between the two modes . At the end of one trans fer (Single/Bur st transf er), DMA c heck s the state of double-synched XnXDREQ. Demand mode - If XnX DREQ[...]

S3C2440A RISC MICROPROC ESSOR DMA 8-5 Transfer Size - There ar e two different tr ansfer sizes; unit and Burst 4. - DMA holds the bus f irm ly dur ing the transf er of the c hunk of data. Thus , other bus m asters cannot get the bus. Burst 4 T ransfer Size There will be f our sequential Reads and W r ites perf orm ed in the Burst 4 T ransf er res p[...]

DMA S3C2440A RISC MICROPROCESSO R 8-6 EXA MPLES Single service in Demand M ode w ith Unit Transfer Siz e The as sertion of XnXDREQ will be a need for every unit transfer (Single service m ode). T he operation c ontinues while the XnXDREQ is asserted ( Dem and m ode), and one pair of Read and W r ite (Single transf er size) is perform ed. XSCLK XnXD[...]

S3C2440A RISC MICROPROC ESSOR DMA 8-7 DMA SPECIA L REGISTERS Each DMA channel has nine control regis ters (36 in total since ther e are four channels for DMA controller) . Six of the control regis ters contr ol the DMA transf er, and other three ones m onitor the s tatus of DMA controller. The details of thos e registers are as f ollows. DMA INITIA[...]

DMA S3C2440A RISC MICROPROCESSO R 8-8 DMA INITIA L DEST INA TION (DIDST) REGIST ER Register Address R/W Description Reset Value DIDST0 0x4B000008 R/W DMA 0 initial destination register 0x 00000000 DIDST1 0x4B000048 R/W DMA 1 initial destination register 0x 00000000 DIDST2 0x4B000088 R/W DMA 2 initial destination register 0x 00000000 DIDST3 0x4B0000[...]

S3C2440A RISC MICROPROC ESSOR DMA 8-9 DMA CONTROL (DCON) REGISTER Register Address R/W Description Reset Value DCON0 0x4B000010 R/W DMA 0 control register 0x00000000 DCON1 0x4B000050 R/W DMA 1 control register 0x00000000 DCON2 0x4B000090 R/W DMA 2 control register 0x00000000 DCON3 0x4B0000D0 R/W DMA 3 control r egister 0x00000000 DCONn Bit Descript[...]

DMA S3C2440A RISC MICROPROCESSO R 8-10 DCONn Bit Descriptio n Initial State SERVMODE [27] Select the service m ode between Single ser vice m ode and W hole service m ode. 0: Single service m ode is selected in which af ter each atom ic tr ansfer (single or bur st of length f our) DMA s tops and waits for another DMA request. 1: W hole service m ode[...]

S3C2440A RISC MICROPROC ESSOR DMA 8-11 DMA STATUS (DSTAT) REGIST ER Register Address R/W Description Reset Value DSTAT 0 0x4B000014 R DMA 0 count r egister 000000h DSTAT 1 0x4B000054 R DMA 1 count r egister 000000h DSTAT 2 0x4B000094 R DMA 2 count r egister 000000h DSTAT 3 0x 4B0000D4 R DMA 3 count register 000000h DSTATn Bit Description Initial St[...]

DMA S3C2440A RISC MICROPROCESSO R 8-12 DMA CURRENT SOURCE (DCSRC) REGISTER Register Address R/W Description Reset Value DCSRC0 0x 4B000018 R DMA 0 c urrent Sourc e Register 0x00000000 DCSRC1 0x 4B000058 R DMA 1 c urrent Sourc e Register 0x00000000 DCSRC2 0x 4B000098 R DMA 2 c urrent Sourc e Register 0x00000000 DCSRC3 0x4B0000D8 R DMA 3 current Sour[...]

S3C2440A RISC MICROPROC ESSOR DMA 8-13 DMA MASK TRIGGER (DM ASKTRIG) REGIST ER Register Address R/W Description Reset Value DMASKTRIG0 0x4B000020 R/W DMA 0 m as k trigger register 000 DMASKTRIG1 0x4B000060 R/W DMA 1 m as k trigger register 000 DMASKTRIG 2 0x4B0000A0 R/W DMA 2 mask trigger r egister 000 DMASKTRIG 3 0x4B0000E0 R/W DMA 3 mask trigger [...]

DMA S3C2440A RISC MICROPROCESSO R 8-14 NOT ES[...]

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-1 9 I/O PORTS OVERVIEW S3C2440A has 130 m ulti-func tional input/output port pins and there ar e eight ports as s hown below: - Port A(G PA): 25-output port - Port B(G PB): 11-input/out port - Port C(GPC) : 16-input/output port - Port D(GPD) : 16-input/output port - Port E(G PE): 16-input/output port - Port [...]

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-2 Table 9- 1. S3C2440A Po rt Config uration( Sheet 1 of 5) Port A Selectable P in Functions GPA22 Output only nFCE – – GPA21 Output only nRST OUT – – GPA20 Output only nFRE – – GPA19 Output only nFW E – – GPA18 Output only ALE – – GPA17 Output only CLE – – GPA16 Output only nGCS5 – [...]

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-3 Table 9- 1. S3C2440A Po rt Config uration( Sheet 2 of 5) Port B Selectable P in Functions GPB10 Input/output nX DREQ0 – – GPB9 Input/output nXDACK0 – – GPB8 Input/output nXDREQ1 – – GPB7 Input/output nXDACK1 – – GPB6 Input/output nXBREQ – – GPB5 Input/output nXBACK – – GPB4 Input/ou[...]

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-4 Table 9- 1. S3C2440A Po rt Config uration( Sheet 3 of 5) Port D Selectable P in Functions GPD15 Input/output VD23 nSS0 – GPD14 Input/output VD22 nSS1 – GPD13 Input/output VD21 – – GPD12 Input/output VD20 – – GPD11 Input/output VD19 – – GPD10 Input/output VD18 SPICLK1 – GPD9 Input/output V[...]

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-5 Table 9- 1. S3C2440A Po rt Config uration( Sheet 4 of 5) Port F Selectable Pin Func tions GPF7 Input/output EINT7 – – GPF6 Input/output EINT6 – – GPF5 Input/output EINT5 – – GPF4 Input/output EINT4 – – GPF3 Input/output EINT3 – – GPF2 Input/output EINT2 GPF1 Input/output EINT1 GPF0 Inpu[...]

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-6 Table 9- 1. S3C2440A Po rt Config uration( Sheet 5 of 5) Port H Selectable P in Functions GPH10 Input/output CLKO UT1 – – GPH9 Input/output CLKOUT0 – – GPH8 Input/output UEXTCLK – – GPH7 Input/output RXD2 nCT S1 – GPH6 Input/output TX D2 nRTS1 – GPH5 Input/output RXD1 – – GPH4 Input/out[...]

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-7 PORT CONTROL DESCRIPTIONS PORT CONFIGURATION REGISTER (GPA CON-GPJCON) In S3C2440A, mos t of the pins are m ultiplexed pins. So, It is determ ined which function is selected f or each pins . The PnCO N(port control r egister) deter m ines which function is used f or each pin. If PE0 – PE7 is us ed for th[...]

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-8 I/O PORT CONTROL REGISTER PORT A CONTROL REGISTERS(GPA CON, GPADA T) Register Address R/W Description Reset Value GPACON 0x56000000 R/W Conf igures the pins of port A 0x ffffff GPADAT 0x 56000004 R/W The data regis ter for port A Undef. Reserved 0x56000008 - Reserved Undef Reserved 0x5600000c - Reserved Un[...]

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-9 GPA DAT Bit Description GPA[24:0] [24:0] W hen the port is configur ed as output port, the pin st ate is the sam e as the corres ponding bit. W hen the port is conf igured as f unctional pin, the undef ined value will be read. Note : nRSTO UT = nRESET & nW DT RST & SW _RESET[...]

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-10 PORT B CONT ROL REGISTERS(GPBCON, GPBDAT, GPBUP) Register Address R/W Descript ion Reset Value GPBCON 0x56000010 R/W Configur es the pins of port B 0x0 GPBDAT 0x56000014 R/W T he data regist er for por t B Undef. GPBUP 0x56000018 R/W pull-up disable r egister f or port B 0x0 Reserved 0x5600001c PBCON Bit [...]

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-11 PORT C CONT ROL REGISTERS(GPCCON, GPCDAT, GPCUP) Register Address R/W Descript ion Reset Value GPCCON 0x56000020 R/W Conf igures the pins of port C 0x0 GPCDAT 0x56000024 R/W The data regis ter for por t C Undef. GPCUP 0x56000028 R/W pull-up dis able register f or port C 0x 0 Reserved 0x5600002c - - - GPCC[...]

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-12 GPCDA T Bit Description GPC[15:0] [15:0] W hen the port is configur ed as input port, the cor responding bit is the pin state. W hen the port is c onfigured as output port, the pin state is the s ame as the corres ponding bit. W hen the port is conf igured as f unctional pin, the undefined value will be r[...]

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-13 PORT D CONT ROL REGISTERS(GPDCON, GPDDAT, GPDUP) Register Address R/W Descript ion Reset Value GPDCON 0x56000030 R/W Conf igures the pins of port D 0x0 GPDDAT 0x56000034 R/W The data regis ter for por t D Undef. GPDUP 0x56000038 R/W pull-up dis able register f or port D 0x f000 Reserved 0x5600003c - GPDCO[...]

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-14 GPDDA T Bit Description GPD[15:0] [15:0] W hen the port is configur ed as input port, the cor responding bit is the pin state. W hen the port is c onfigured as output port, the pin state is the s ame as the corres ponding bit. W hen the port is conf igured as f unctional pin, the undefined value will be r[...]

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-15 PORT E CO NTRO L REGIST ERS(GPECON , GPEDA T, GPEUP) Register Address R/W Descript ion Reset Value GPECON 0x56000040 R/W Configur es the pins of port E 0x0 GPEDAT 0x56000044 R/W T he data regist er for por t E Undef. GPEUP 0x56000048 R/W pull-up disable r egister f or port E 0x 0000 Reserved 0x5600004c - [...]

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-16 . GPEDA T Bit Description GPE[15:0] [15:0] W hen the port is conf igured as an input por t, the corres ponding bit is the pin state. W hen the port is conf igured as an output port, the pin s tate is the sam e as the corres ponding bit. W hen the port is conf igured as a f unctional pin, the undef ined va[...]

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-17 PORT F CONT ROL REGISTERS(GPFCON, GPFDAT) If GPF0 - GPF7 will be used for wake-up s ignals at power down mode, the ports will be set in interrupt m ode. Register Address R/W Descript ion Reset Value GPFCON 0x56000050 R/W Configur es the pins of port F 0x0 GPFDAT 0x56000054 R/W T he data regist er for por [...]

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-18 PORT G CONTROL REGISTERS(GPGCON, GPGDA T ) If GPG 0 - GPG7 will be used f or wake- up signals at Sleep m ode, the ports will be set in inter rupt m ode. Register Address R/W Descript ion Reset Value GPGCON 0x56000060 R/W Configur es the pins of port G 0x 0 GPGDAT 0x56000064 R/W T he data register for port[...]

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-19 GPGDAT Bit Description GPG[15:0] [15:0] W hen the port is configur ed as an input port, the cor responding bit is the pin s tate. W hen the port is conf igured as an output port, the pin s tate is the sam e as the corres ponding bit. W hen the port is conf igured as f unctional pin, the undef ined value w[...]

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-20 PORT H CONT ROL REGISTERS(GPHCON, GPHDAT) Register Address R/W Descript ion Reset Value GPHCON 0x56000070 R/W Conf igures the pins of port H 0x0 GPHDAT 0x56000074 R/W The data regis ter for por t H Undef. GPHUP 0x56000078 R/W pull-up dis able register f or port H 0x000 Reserved 0x5600007c - - GPHCON Bit D[...]

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-21 GPHDA T Bit Descrip tion GPH[10:0] [10:0] W hen the port is c onfigured as an input port, the corr esponding bit is the pin st ate. W hen the port is conf igured as an output port, the pin s tate is the sam e as the corres ponding bit. W hen the port is conf igured as f unctional pin, the undef ined value[...]

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-22 PORT J CONT ROL REGISTERS(GPJCON, GPJDAT) Register Address R/W Descript ion Reset Value GPJCON 0x 560000d0 R/W Configures the pins of por t J 0x0 GPJDAT 0x560000d4 R/W T he data register for por t J Undef . GPJUP 0x560000d8 R/W pull-up disable r egister f or port J 0x0000 Reserved 0x560000dc - - - GPJCON [...]

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-23 GPJDA T Bit Description GPJ15:0] [12:0] W hen the port is configured as an input port, the corr esponding bit is the pin s tate. W hen the port is conf igured as an output port, the pin s tate is the sam e as the corres ponding bit. W hen the port is conf igured as f unctional pin, the undef ined value wi[...]

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-24 MISCELLANEOUS control register(MISCCR) In Sleep mode, the data bus (D[31:0] or D[15:0] c an be set as Hi-Z and O utput ‘0’ state. But, becaus e of the character istics of IO pad, the data bus pull- up resisters have to be turned on or of f to reduc e the power consum ption. D[31:0] pin pull-up resiste[...]

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-25 CLKSEL1 (1) [10:8] Select source c lock with CLKOUT1 pad 000 = MPLL output 001 = UPLL output 010 = RTC cloc k output 011 = HCLK 100 = PCLK 101 = DCLK1 11x = rese rved 000 Reserved [7] - 0 CLKSEL0 (1) [6:4] Select sour ce clock with CLKOUT0 pad 000 = MPLL INPUT Cloc k(X TAL) 001 = UPLL output 010 = FCLK 01[...]

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-26 DCLK CONTROL REGIST ERS(DCLKCON) Register Address R/W Descript ion Reset Value DCLKCON 0x56000084 R/W DCLK0/1 Control Regis ter 0x0 DCLKCON Bit Descript ion DCLK1CMP [27:24] DCLK1 Com pare value clock toggle value.( < DCLK1DIV) If the DCLK1CMP is n, Low level duration is ( n + 1), High level duration i[...]

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-27 EXTINTn(External Interrupt Control Re gister n) The 8 ex ternal interrupts c an be requested by various signaling m ethods. T he EXT INT regis ter conf igures the signaling m ethod between the level trigger and edge trigger f or the external inter rupt request, and als o configur es the signal polarity. T[...]

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-28 EXTINT 1 Bit Description FLTEN15 [31] F ilter Enable for EINT15 0 = Filter Disable 1= Filter Enable EINT15 [30:28] Setting the signaling m ethod of the EINT 15. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered FLTEN14 [27] F ilter Enable f[...]

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-29 EXTINT 2 Bit Descriptio n Reset Value FLTEN23 [31] Filter Enable for EINT 23 0 = Filter Disable 1= Filter Enable 0 EINT23 [30:28] Setting the signaling m ethod of the EINT 23. 000 = Low level 001 = High level 01x = Falling edge trigger ed 10x = Ris ing edge triggered 11x = Both edge triggered 000 FLTEN22 [...]

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-30 EINT17 [6:4] Setting the signaling m ethod of the EINT 17. 000 = Low level 001 = High level 01x = Falling edge trigger ed 10x = Ris ing edge triggered 11x = Both edge triggered 000 FLTEN16 [3] Filter Enable f or EINT16 0 = Filter Disable 1= Filter Enable 0 EINT16 [2:0] Setting the signaling m ethod of the[...]

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-31 EINTFLTn(External Interrupt Filte r Register n) To r ecognize the level interrupt, the valid logic level on EXT INT n pin m ust be retained f or 40ns at leas t because of the noise filter . Register Address R/W Descriptio n Reset Value EINTFLT 0 0x56000094 R/W reser ved 0x000000 EINTFLT 1 0x56000098 R/W r[...]

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-32 EINTM ASK(External Interrupt M ask Regist er) Register Address R/W Descriptio n Reset Value EINTMASK 0x560000a4 R/W External interupt m ask Register 0x 000 fffff EINTM ASK Bit Description EINT23 [23] 0 = enable interrupt 1= m as ked EINT22 [22] 0 = enable interrupt 1= m as ked EINT21 [21] 0 = enable inter[...]

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-33 EINTPEND(Exte rnal Interr upt Pending Register ) Register Address R/W Descriptio n Reset Value EINTPEND 0x560000a8 R/W External interupt pending Regis ter 0x00 EINTPEND Bit Descrip tion Reset Value EINT23 [23] It is c leard by writing “1” 0 = not occur 1= oc cur interr upt 0 EINT22 [22] It is c leard [...]

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-34 EINT5 [5] It is clear d by writing “ 1” 0 = not occur 1= oc cur interr upt 0 EINT4 [4] It is clear d by writing “ 1” 0 = not occur 1= oc cur interr upt 0 Reserved [3:0] Reser ved 0000[...]

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-35 GSTATUSn (G eneral Statu s Registers) Register Address R/W Descriptio n Reset Value GSTAT US0 0x560000ac R External pin status Not define GSTAT US1 0x560000b0 R/W Chip ID 0x32440001 GSTAT US2 0x560000b4 R/W Reset Status 0x1 GSTAT US3 0x560000b8 R/W Inform regis ter 0x0 GSTAT US4 0x560000bc R/W Inf orm reg[...]

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-36 DSCn (Drive Stre ngth Control) Control the Mem ory I/O drive strength Register Address R/W Descriptio n Reset Value DSC0 0x560000c4 R/W strength control r egister 0 0x0 DSC1 0x560000c8 R/W strength control r egister 1 0x0 DSC0 Bit Description Reset Value nEN_DSC [31] enable Drive Str ength Control 0: enab[...]

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-37 DSC1 Bit Description Reset Value DSC_SCK1 [29:28] SCLK1 Drive str ength. 00: 12mA 10: 10m A 01: 8mA 11: 6m A 00 DSC_SCK0 [27:26] SCLK0 Drive str ength. 00: 12mA 10: 10m A 01: 8mA 11: 6m A 00 DSC_SCKE [25:24] SCKE Drive strength. 00: 10mA 10: 8m A 01: 6mA 11: 4m A 00 DSC_SDR [23:22] nSRAS/nSCAS Drive stren[...]

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-38 MSLCON (M emory S leep Control Register ) Select m em ory interface status when in SLEEP mode. Register Address R/W Descriptio n Reset Value MSLCON 0x560000cc R/W Mem ory Sleep Control Register 0x0 MSL CON Bit Descriptio n Reset Value PSC_DATA [11] DATA[31:0] pin st atus in Sleep m ode. 0: Hi-Z 1: O utput[...]

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-1 10 PWM TIMER OVERVIEW The S3C2440A has five 16-bit tim ers . Tim er 0, 1, 2, and 3 have Pulse W idth Modulation (PW M) f unction. Tim er 4 has an internal timer only w ith no output pins. The tim er 0 has a dead-zone generator, which is us ed with a large current devic e. The tim er 0 and 1 s hare an 8-bi[...]

PWM TIMER S3C2440A RISC MICROPROCESSO R 10-2 Clock Divider 5:1 MUX Dead Zone Generator TOUT0 TOUT1 TOUT2 Control Logic0 TCMPB0 TCNTB0 Control Logic1 TCMPB1 TCNTB1 5:1 MUX Clock Divider 5:1 MUX 5:1 MUX Control Logic2 TCMPB2 TCNTB2 TOUT3 Control Logic3 TCMPB3 TCNTB3 No Pin PCLK 8-Bit Prescaler 8-Bit Prescaler Dead Zone Dead Zone TCLK0 1/8 1/4 1/16 1/[...]

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-3 PWM TIMER OPERA TION PRESCA LER & DIVIDER An 8-bit presc aler and a 4-bit divider m ak e the following output fr equencies: 4-bit divider settings Minimum resolution (prescaler = 0) M aximum resolutio n (prescaler = 255) Maximum in terval (TCNT Bn = 65535) 1/2 (PCLK = 50 MHz) 0.0400 us (25.0000 MHz) 1[...]

PWM TIMER S3C2440A RISC MICROPROCESSO R 10-4 A UT O RELOA D & DOUBLE BUFFERING S3C2440A PW M Tim ers have a double buffering f unction, enabling the reload value changed f or the next tim er operation without s topping the current timer operation. So, although the new tim er value is set, a c urrent tim er operation is com pleted s ucces sfully[...]

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-5 TIM ER INITIALIZA TION USING M A NUAL UPDA TE BIT A ND INVERT ER BIT An auto reload oper ation of the timer occurs when the dow n c ounter reaches 0. So, a starting value of the TCNT n has to be def ined by the user in advance. In this case, the st arting value has to be loaded by the manual update bit. T[...]

PWM TIMER S3C2440A RISC MICROPROCESSO R 10-6 TIM ER OPERA T ION TOUTn 12 4 6 50 110 40 40 60 20 3 79 1 0 5 8 11 Figure 10-4. Examp le of a T imer Operation The above Figur e 10-4 shows the res ult of the following proc edure: 1. Enable the auto re- load function. Set the T CNTBn to 160 ( 50+110) and the T CMPBn to 110. Set the manual update bit and[...]

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-7 PULSE WIDTH M ODULATION (PWM ) Write TCMPBn = 60 Write TCMPBn = 50 Write TCMPBn = 40 Write TCMPBn = 30 Write TCMPBn = 30 Write TCMPBn = Next PWM Value 60 50 40 30 30 Figure 10-5. Examp le of PWM PW M function c an be implem ented by using the TCMPBn. PW M f requency is determ ined by TCNT Bn. Figure 10-5 [...]

PWM TIMER S3C2440A RISC MICROPROCESSO R 10-8 OUTPUT LEVEL CONT ROL Inverter off Initial State Period 1 Period 2 Timer Stop Inverter on Figure 10-6. In verter On /Off The f ollowing procedure desc ribes how to m aintain TO UT as high or low (assum e the inverter is off ): 1. Turn off the auto reload bit. And then, T OUT n goes to high level and the [...]

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-9 DEA D ZONE GENERATOR The Dead Zone is for the PW M control in a power device. T his f unction enables the inser tion of the tim e gap between a tur n-off of a switching device and a turn on of another switching device. T his tim e gap prohibits the two switching devices f rom being turned on s imultaneous[...]

PWM TIMER S3C2440A RISC MICROPROCESSO R 10-10 DMA REQUEST M ODE The PW M tim er c an generate a DMA request at ever y spec ific tim e. The timer keeps DMA request signals (nDMA_REQ) low until the timer rece ives an ACK signal. W hen the tim er rec eives the ACK signal, it m ak es the request signal inac tive. The tim er, which gener ates the DMA re[...]

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-11 PWM TIMER CONTROL REGIS TE RS TIM ER CONFIGURA T ION REGISTER0 (T CFG0) Tim er input c lock Frequency = PCLK / {prescaler value+1} / {divider value} {pres caler value} = 0~255 {divider value} = 2, 4, 8, 16 Register Address R/W Descrip tion Reset Valu e TCF G0 0x51000000 R/W Configures the two 8-bit pr es[...]

PWM TIMER S3C2440A RISC MICROPROCESSO R 10-12 TIM ER CONFIGURA T ION REGISTER1 (T CFG1) Register Address R/W Descrip tion Reset Valu e TCF G1 0x51000004 R/W 5-MUX & DMA m ode selecton r egister 0x00000000 TCFG 1 Bit Description Initial State Reserved [31:24] 00000000 DMA mode [23:20] Select DMA request c hannel 0000 = No select ( all interrupt)[...]

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-13 TIM ER CONTROL (T CON) REGISTER Register Address R/W Descriptio n Reset Value TCO N 0x51000008 R/W T imer c ontrol regis ter 0x00000000 TCO N Bit Description In itial state Tim er 4 auto reload on/of f [22] Determ ine auto reload on/off for Tim er 4. 0 = One-shot 1 = Inter val mode ( auto reload) 0 Tim e[...]

PWM TIMER S3C2440A RISC MICROPROCESSO R 10-14 TCON (Continued) TCO N Bit Description In itial state Reserved [7:5] Reserved Dead zone enable [4] Determine the dead zone operation. 0 = Disable 1 = Enable 0 Tim er 0 auto reload on/of f [3] Deter m ine auto reload on/off for T im er 0. 0 = One-shot 1 = Inter val mode( auto reload) 0 Tim er 0 output in[...]

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-15 TIM ER 0 COUNT BUFFER REGIST ER & COM PA RE BUFFER REGIST ER (TCNT B0/TCM PB0) Register Address R/W Descriptio n Reset Value TCNT B0 0x5100000C R/W T imer 0 count buff er register 0x00000000 TCMPB0 0x51000010 R/W Tim er 0 c om pare buff er register 0x00000000 TCM PB0 Bit Descript ion Initial State Ti[...]

PWM TIMER S3C2440A RISC MICROPROCESSO R 10-16 TIM ER 1 COUNT BUFFER REGIST ER & COM PA RE BUFFER REGIST ER (TCNT B1/TCM PB1) Register Address R/W Descriptio n Reset Value TCNT B1 0x51000018 R/W T im er 1 count buf fer r egister 0x 00000000 TCMPB1 0x5100001C R/W T imer 1 c om pare buff er regist er 0x00000000 TCM PB1 Bit Description Initial Stat[...]

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-17 TIM ER 2 COUNT BUFFER REGIST ER & COM PA RE BUFFER REGIST ER (TCNT B2/TCM PB2) Register Address R/W Descriptio n Reset Value TCNT B2 0x51000024 R/W T im er 2 count buf fer r egister 0x 00000000 TCMPB2 0x51000028 R/W Tim er 2 c om pare buff er register 0x00000000 TCM PB2 Bit Descrip tion Initial State[...]

PWM TIMER S3C2440A RISC MICROPROCESSO R 10-18 TIM ER 3 COUNT BUFFER REGIST ER & COM PA RE BUFFER REGIST ER (TCNT B3/TCM PB3) Register Address R/W Descriptio n Reset Value TCNT B3 0x51000030 R/W T im er 3 count buf fer r egister 0x 00000000 TCMPB3 0x51000034 R/W Tim er 3 c om pare buff er register 0x00000000 TCM PB3 Bit Descrip tion Initial Stat[...]

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-19 TIM ER 4 COUNT BUFFER REGIST ER (TCNT B4) Register Address R/W Descriptio n Reset Value TCNT B4 0x5100003C R/W T imer 4 count buff er register 0x00000000 TCNT B4 Bit Descript ion Init ial State Tim er 4 count buf fer register [15:0] Set c ount buff er value for Tim er 4 0x 00000000 TIM ER 4 COUNT OBSERVA[...]

PWM TIMER S3C2440A RISC MICROPROCESSO R 10-20 NOTES[...]

S3C2440A RISC MICROPROCESSOR UART 11-1 11 UA RT OVERVIEW The S3C2440A Univers al Asynchronous Receiver and T ransm itter ( UART) provide three independent asynchronous serial I/O (SIO) ports, each of which can operate in Inter rupt-based or DMA-based m ode. In other words, the UART c an generate an interrupt or a DMA r equest to tr ansfer data betw[...]

UART S3C2440A RISC MICROPROCESSO R 11-2 BLOCK DIA GRAM B uad- r at e G ener at or Con t r ol Uni t Transm i t ter R ecei ver P er i pher al B US TXD n C l o ck S our ce ( PC LK, FCLK/ n, U EXTCLK) RXD n Tr ansm i t F I F O R egi st er (F IF O m o d e ) Tr a ns m i t H ol d i ng R egi st er ( N on- FI FO m ode) R ecei ve FI FO Regi st er (F IF O m o[...]

S3C2440A RISC MICROPROCESSOR UART 11-3 UA RT OPERA T ION The f ollowing sections desc ribe the UART operations that include data trans m ission, data reception, interrupt generation, baud-rate generation, Loopbac k m ode, Inf rared m ode, and auto f low control. Data Transmissio n The data fram e for trans m ission is progr amm able. It c onsists o[...]

UART S3C2440A RISC MICROPROCESSO R 11-4 A uto Flow Control (A FC) The S3C2440A's UART 0 and UART 1 support auto f low control with nRTS and nCTS signals . In c ase, it can be connected to exter nal UART s. If user s want to connec t a UART to a Modem , disable auto f low control bit in UMCONn register and control the signal of nRTS by software[...]

S3C2440A RISC MICROPROCESSOR UART 11-5 RS-232C interface If the user wants to connect the UART to m odem inter face ( instead of null m odem ), nRT S, nCTS, nDSR, nDT R, DCD and nRI s ignals are needed. In this cas e, the users can c ontrol these signals with general I/O ports by software becaus e the AFC does not suppor t the RS-232C interf ace. I[...]

UART S3C2440A RISC MICROPROCESSO R 11-6 UA RT Error Sta tus FIFO UART has the error status FIFO bes ides the Rx F IFO regis ter. T he error status F IFO indicates which data, am ong FIFO regist ers, is rec eived with an error. T he error interr upt will be issued only when the data, which has an er ror, is ready to read out. To clear the err or sta[...]

S3C2440A RISC MICROPROCESSOR UART 11-7 Baud-rate Ge neration Each UART's baud- rate generator provides the serial clock for the transm itter and the receiver. The s ource cloc k for the baud-rate generator can be selected with the S3C2440A's internal system clock or UEX TCLK. In other words, dividend is selectable by setting Clock Selec t[...]

UART S3C2440A RISC MICROPROCESSO R 11-8 Infrared (IR) M od e The S3C2440A UART block supports infrar ed (IR) transm is sion and reception, which can be s elected by setting the Infrar ed-m ode bit in the UART line c ontrol register (ULCONn). F igure 11-4 illustrates how to implem ent the IR mode. In IR transmit m ode, the transm it pulse c omes out[...]

S3C2440A RISC MICROPROCESSOR UART 11-9 Start Bit Stop Bit Data Bits SIO Frame 0101001101 Figure 11-4. Serial I/O F rame Timing Diagram ( Normal UA RT ) 0 Start Bit Stop Bit Data Bits IR Transmit Frame Bit Time Pulse Width = 3/16 Bit Frame 00 0 01 1 1 1 1 Figure 11-5. Inf rared Transmit M od e Frame Timing Diagram 0 Start Bit Stop Bit Data Bits IR R[...]

UART S3C2440A RISC MICROPROCESSO R 11-10 UA RT SPECIA L REGISTERS UA RT LINE CONTROL REGIST ER There ar e three UART line c ontrol register s including ULCON0, ULCO N1, and ULCON2 in the UART bloc k. Register Address R/W Descriptio n Reset Value ULCON0 0x50000000 R/W UART channel 0 line contr ol register 0x00 ULCON1 0x50004000 R/W UART channel 1 li[...]

S3C2440A RISC MICROPROCESSOR UART 11-11 UA RT CONTROL REGIST ER There ar e three UART c ontrol register s including UCON0, UCON1 and UCO N2 in the UART bloc k. Register Address R/W Descriptio n Reset Value UCON0 0x50000004 R/W UART c hannel 0 control regist er 0x00 UCON1 0x50004004 R/W UART c hannel 1 control regist er 0x00 UCON2 0x50008004 R/W UAR[...]

UART S3C2440A RISC MICROPROCESSO R 11-12 Tx Inter rupt Type [9] Interrupt reques t ty pe. 0 = P uls e ( Interrupt is r equested as soon as the Tx buffer becom es empty in Non-FIFO m ode or reaches T x FIF O T rigger Level in FIFO mode.) 1 = Level (Interrupt is requested while T x buff er is em pty in Non- FIFO m ode or r eaches T x FIF O Tr igger L[...]

S3C2440A RISC MICROPROCESSOR UART 11-13 UART CONTROL REGISTER (Continued) Trans m it Mode [3:2] Determ ine which function is currently able to write Tx data to the UART transm it buff er regis ter. (UART Tx Enable/Disable) 00 = Disable 01 = Interrupt reques t or polling m ode 10 = DMA0 request (O nly f or UART 0), DMA3 request (Only for UART 2) 11 [...]

UART S3C2440A RISC MICROPROCESSO R 11-14 UA RT FIFO CONTROL REGIST ER There ar e three UART F IFO control r egisters inc luding UFCON0, UFCON1 and UF CON2 in the UART bloc k. Register Address R/W Descriptio n Reset Value UFCON0 0x50000008 R/W UART channel 0 F IFO control r egister 0x0 UFCON1 0x50004008 R/W UART channel 1 F IFO control r egister 0x0[...]

S3C2440A RISC MICROPROCESSOR UART 11-15 UA RT M ODEM CONT ROL REGIST ER There ar e two UART MODEM contr ol registers including UMCON0 and UMCON1 in the UART block . Register Address R/W Descriptio n Reset Value UMCON0 0x 5000000C R/W UART channel 0 Modem control r egister 0x0 UMCON1 0x 5000400C R/W UART channel 1 Modem control r egister 0x0 Reserve[...]

UART S3C2440A RISC MICROPROCESSO R 11-16 UA RT TX/RX ST ATUS REGISTER There ar e three UART T x/Rx status regis ters including UT RSTAT 0, UT RSTAT 1 and UTRST AT2 in the UART block . Register Address R/W Descriptio n Reset Value UTRST AT0 0x50000010 R UART channel 0 T x/Rx s tatus register 0x6 UTRST AT1 0x50004010 R UART channel 1 T x/Rx s tatus r[...]

S3C2440A RISC MICROPROCESSOR UART 11-17 UA RT ERROR STATUS REGISTER There ar e three UART Rx error s tatus register s including UERST AT0, UERST AT1 and UERST AT2 in the UART block . Register Address R/W Descriptio n Reset Value UERSTAT 0 0x50000014 R UART channel 0 Rx error status regis ter 0x0 UERSTAT 1 0x50004014 R UART channel 1 Rx error status[...]

UART S3C2440A RISC MICROPROCESSO R 11-18 UA RT FIFO STATUS REGISTER There ar e three UART FIFO s tatus register s including UFST AT 0, UFSTAT 1 and UFST AT2 in the UART block . Register Address R/W Descriptio n Reset Value UFSTAT 0 0x50000018 R UART channel 0 FIF O status r egister 0x00 UFSTAT 1 0x50004018 R UART channel 1 FIF O status r egister 0x[...]

S3C2440A RISC MICROPROCESSOR UART 11-19 UA RT M ODEM STATUS REGISTER There ar e two UART m odem status r egisters inc luding UMSTAT 0, UMSTAT 1 in the UART block . Register Address R/W Descript ion Reset Value UMSTAT 0 0x5000001C R UART channel 0 Modem status register 0x0 UMSTAT 1 0x5000401C R UART channel 1 Modem status register 0x0 Reserved 0x500[...]

UART S3C2440A RISC MICROPROCESSO R 11-20 UA RT TRANSMIT BUFFER REGIST ER (HOLDING REGIST ER & FIFO REGISTER) There ar e three UART tr ansm it buff er registers including UTX H0, UT XH1 and UT XH2 in the UART block . UTX Hn has an 8-bit data f or transm ission data. Register Address R/W Descripti on Reset Value UTX H0 0x50000020(L) 0x50000023(B)[...]

S3C2440A RISC MICROPROCESSOR UART 11-21 UA RT BA UD RATE DIVISOR REGISTER There ar e three UART baud r ate divisor regis ters including UBRDIV0, UBRDIV1 and UBRDIV2 in the UART block . The value s tored in the baud rate divisor register ( UBRDIVn), is us ed to determ ine the serial T x/Rx cloc k rate (baud rate) as follows: UBRDIVn = (int)( UART cl[...]

UART S3C2440A RISC MICROPROCESSO R 11-22 NOT ES[...]

S3C2440A RISC MICROPROCESSO R USB HOST 12-1 12 USB HOST CONTROLLER OVERVIEW S3C2440A supports 2- port USB host interf ace as f ollows: • OHCI Rev 1.0 com patible • USB Rev1.1 com patible • Two down stream ports • Support for both LowSpeed and FullSpeed USB devices HCI SLAVE BLOCK APP_SADR(8) APP_SDATA(32) HCI_DATA(32) CONTROL CONTROL OHCI R[...]

USB HOST S3C2440A RISC MICROPROCESSOR 12-2 USB HOST CONTR OLLER SPECIA L REGISTERS The S3C2440A USB hos t controller c omplies with OHCI Rev 1.0. Refer to Open Hos t Controller Interf ace Rev 1.0 specif ication f or detailed infor mation. OHCI REGISTERS FOR USB HOST CONTROLLER Register Base Address R/W Description Reset Value HcRevision 0x 49000000[...]

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-1 13 USB DEVICE CONTROLLER OVERVIEW Universal Serial Bus (USB) device contr oller is des igned to provide a high perf orm ance fu ll speed func tion controller s olution with DMA interface. USB devic e controller allows bulk transfer with DMA, interrupt tr ansfer and control trans fer. USB device contr oll[...]

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-2 SIE RT_VP_OUT RT_VM_IN RT_VP_IN RXD RT_UXSUSPEND RT_UX_OEN RT_VM_OUT MC_ADDR[13:0] SIU GFI FIFOs MCU & DMA I/F MC_DATA_IN[31:0] MC_DATA_OUT[31:0] USB_CLK SYS_CLK SYS_RESETN MC_WR WR_RDN MC_CSN MC_INTR DREQN[3:0] DACKN[3:0] Figure 13-1. USB Dev ice Controller Blo ck Diagram[...]

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-3 USB DEVICE CON TROLLER SPECIA L REGISTERS This section des cribes detailed f unctionalities about register s ets of USB device c ontroller. All special f unction regis ter is byte-access ible or word-acc essible. If y ou acces s by te m ode offs et-addres s is diff erent in little endian and big endian. [...]

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-4 EP2_DMA_CON Endpoint2 DMA c ontrol register 0x218( L) / 0x21B(B) EP2_DMA_UNIT Endpoint2 DMA unit counter regis ter 0x 21C(L) / 0x21F (B) EP2_DMA_FIFO Endpoint2 DMA FIFO c ounter register 0x220( L) / 0x223(B) EP2_DMA_TT C_L Endpoint2 DMA transf er counter low-byte register 0x224(L) / 0x 227(B) EP2_DMA_TT [...]

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-5 FUNCTIO N A DDRESS REGIST ER (FUNC_ADDR_REG) This register m aintains the USB device controller address as signed by the host. The Micro Contr oller Unit (MCU) writes the value received through a SET_ADDRESS des criptor to this register . This address is used for the next token. Register Address R/W Desc[...]

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-6 POWER M A NAGEMENT REGIST ER (PWR_REG) This register ac ts as a power contr ol register in the USB block . Register Address R/W Descript ion Reset Value PW R_REG 0x52000144(L) 0x52000147(B) R/W (by te) Power m anagem ent regist er 0x 00 PWR_A DDR Bit MCU USB Description Init ial State Reserved [7:4] - - [...]

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-7 INTERRUPT REGISTER (EP_INT _REG/USB_INT_REG) The USB cor e has two interrupt registers . T hese registers act as status register s for the MCU when it is interrupted. T he bits are clear ed by writing a ‘1’ ( not ‘0’) to each bit that was set. Once the MCU is interrupted, MCU should r ead the con[...]

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-8 Register Address R/W Description Reset Valu e USB_INT_REG 0x 52000158(L) 0x5200015B(B) R/W (by te) USB interrupt pending/c lear register 0x 00 USB_INT_REG Bit M CU USB Description Initial State RESET Interrupt [2] R /CLEAR SET Set by the USB when it receives reset s ignaling. 0 RESUME Interrupt [1] R /CL[...]

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-9 INTERRUPT ENA BLE REGIST ER (EP_INT_EN_REG/USB_INT _EN_REG) Corresponding to eac h interrupt regis ter, T he USB device controller also has two interrupt enable r egisters ( except resum e interrupt enable) . By default, usb r eset interrupt is enabled. If bit = 0, the interr upt is disabled. If bit = 1,[...]

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-10 Register Address R/W Description Reset Value USB_INT_EN_REG 0x 520016C(L) 0x5200016F(B) R/W (by te) Determ ine which interrupt is enabled 0x04 INT_M ASK_REG Bit M CU USB Descrip tion Init ial State RESET_INT _EN [2] R/W R Reset interrupt enable bit 0 = Interrupt disable 1 = Enable 1 Reserved [1] - - - 0[...]

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-11 FRA M E NUM BER REGISTER (FPAME_NUM 1_REG/FRA M E_NUM 2_REG) W hen the host transf ers USB pack ets, eac h Start Of Frame (SOF) pack et includes a fr am e number . The USB device controller catches this fr ame num ber and loads it into this regis ter autom atically. Register Address R/W Description Rese[...]

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-12 INDEX REGIST ER (INDEX_REG) The INDEX register is used to indicate c ertain endpoint register s eff ectively. The MCU can acc ess the endpoint registers (MAXP_REG, IN_CSR1_REG , IN_CSR2_REG, OUT _CSR1_REG, OUT _CSR2_REG, OUT _FIFO_CNT 1_REG, and OUT _FIFO _CNT2_REG ) for an endpoint ins ide the core usi[...]

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-13 END POINT0 CONT ROL STATUS REGISTER (EP0_CSR) This register has the control and st atus bits f or Endpoint 0. Since a contr ol transaction is involved with both IN and OUT tokens , there is only one CSR register, m apped to the IN CSR1 register. ( Share IN1_CSR and can acces s by writing index register [...]

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-14 END POINT IN CONT ROL STATUS REGISTER (IN_CSR1_REG/IN_CSR2_REG) Register Address R/W Descript ion Reset Value IN_CSR1_REG 0x52000184(L) 0x52000187(B) R/W (by te) IN END POINT contr ol status regis ter1 0x00 IN_CSR1_REG Bit M CU USB Description Init ial State Reserved [7] - - - - CLR_DATA_ TOGGLE [6] R/W[...]

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-15 Register Address R/W Descript ion Reset Value IN_CSR2_REG 0x52000188(L) 0x5200018B(B) R/W (by te) IN END POINT contr ol status regis ter2 0x20 IN_CSR2_REG Bit MCU USB Descriptio n Initial State AUTO_SET [7] R/W R If s et, whenever the MCU writes MAXP data, IN_PKT_RD Y will automatically be set by the c [...]

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-16 END POINT OUT CONTROL ST A T US REGISTER (OUT _CSR1_REG/OUT _CSR2_REG) Register Address R/W Descript ion Reset Value OUT _CSR1_REG 0x52000190(L) 0x52000193(B) R/W (by te) End Point out control status register 1 0x00 OUT_CSR1_REG Bit M CU USB Description Init ial State CLR_DATA_T OGGLE [7] R/W CLEAR W he[...]

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-17 Register Address R/W Descript ion Reset Value OUT _CSR2_REG 0x52000194(L) 0x52000197(B) R/W (by te) End Point out control status register 2 0x00 OUT_CSR2_REG Bit M CU USB Description Init ial State AUTO_CLR [7] R/W R If the MCU is set, whenever the MCU reads data from the O UT F IFO, OUT _PKT _RDY will [...]

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-18 END POINT OUT WRITE COUNT REGIST ER (OUT_FIFO_CNT 1_REG/OUT_FIFO_CNT 2_REG) Thes e registers maintain the num ber of bytes in the packet as the num ber is unloaded by the MCU. Register Address R/W Descriptio n Reset Value OUT _FIFO_CNT 1_REG 0x52000198( L) 0x5200019B(B) R (by te) End Point out write cou[...]

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-19 DMA INTERFA CE CONT ROL REGISTER (EPN_DM A _CON) Register Address R/W Description Reset Valu e EP1_DMA_CON 0x52000200(L) 0x52000203(B) R/W (by te) EP1 DMA interf ace c ontrol register 0x 00 EP2_DMA_CON 0x52000218(L) 0x5200021B(B) R/W (by te) EP2 DMA interf ace c ontrol register 0x 00 EP3_DMA_CON 0x52000[...]

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-20 DMA UNIT COUNTER REGIST ER (EPN_DM A _UNIT ) This register is valid in Dem and mode. In other m odes, this regis ter value m ust be set to ‘0x 01’ Register Address R/W Description Reset Value EP1_DMA_UNIT 0x 52000204(L) 0x52000207(B) R/W (by te) EP1 DMA transf er unit counter bas e register 0x00 EP2[...]

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-21 DMA FIFO COUNTER REGISTER (EPN_DM A _FIFO) This regis ter has values in byte siz e in FIFO to be transferred by DMA. In case of OUT _DMA_RUN enabled, the value in OUT FIFO W rite Count Regis ter1 will be loaded in this regis ter autom atically. In case of IN DMA m ode, the MCU should set proper value by[...]

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-22 DMA TOT A L TRANSFER COUNTER REGIST ER (EPn_DM A_TTC_L ,M,H) This register s hould have total number of bytes to be transfer red using DMA (total 20- bit counter). Register Address R/W Descrip tion Reset Value EP1_DMA_TT C_L 0x5200020C(L) 0x5200020F(B) R/W (by te) EP1 DMA total transf er counter (lower [...]

S3C2440A RISC MICROPROCESSO R INTERRUPT CONTROLLER 14-1 14 INTERRUPT CONTROLLER OVERVIEW The interrupt c ontroller in the S3C2440A rec eives the request f rom 60 interrupt s ources. T hese inter rupt sourc es are provided by internal peripherals such as DMA contr oller, UART , IIC, and others. In thes e interrupt s ources , the UARTn, AC97 and EINT[...]

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-2 INTERRUPT CONT ROLLER OPERATION F-bit and I-bit of Progra m Status Register (PSR) If the F-bit of PSR in ARM920T CPU is set to 1, the CPU does not accept the Fas t Interrupt Request ( FIQ) f rom the interrupt controller. Likewise, If I-bit of the PSR is set to 1, the CPU does not acc ept the In[...]

S3C2440A RISC MICROPROCESSO R INTERRUPT CONTROLLER 14-3 INTERRUPT SOURCES The interr upt controller s upports 60 interr upt sources as shown in the table below. Sources Descriptions A rbiter Group INT_ADC ADC EOC and T ouch interrupt (I NT_ADC_S/INT _TC) ARB5 INT_RT C RTC alarm interrupt ARB5 INT_SPI1 SPI1 interrupt ARB5 INT_UART 0 UART 0 Interrupt[...]

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-4 INTERRUPT SUB SOURCES Sub Sources Descriptio ns Source INT_AC97 AC97 interr upt INT_W DT _AC97 INT_W DT W atchdoc interrupt INT_W DT _AC97 INT_CAM_P P-port capture inter rupt in cam era interf ace INT _CAM INT_CAM_C C-por t capture interrupt in c am era interfac e INT_CAM INT_ADC_S ADC interrup[...]

S3C2440A RISC MICROPROCESSO R INTERRUPT CONTROLLER 14-5 INTERRUPT PRIORITY GENERATING BLOCK The priority logic f or 32 interrupt requests is com posed of se ven rotation based arbiters: six first-level arbiter s and one second-level ar biter as shown in Figur e 14-1 below. ARB IT ER6 ARBITER0 ARM IRQ REQ1/EINT0 ARBITER1 ARBITER2 ARBITER3 ARBITER4 A[...]

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-6 INTERRUPT PRIORITY Each arbiter can handle six interr upt requests based on the one bit arbiter m ode contr ol (ARB_MODE) and two bits of s election contr ol signals (ARB_SEL) as follows: If ARB_SEL bits ar e 00b, the priority order is REQ0, REQ1, REQ2, REQ 3, REQ4, and REQ5. If ARB_SEL bits ar[...]

S3C2440A RISC MICROPROCESSO R INTERRUPT CONTROLLER 14-7 INTERRUPT CONTROLLER SPECIA L REGISTERS There ar e five contr ol registers in the interrupt contr oller: sour ce pending r egister, interrupt m ode register , m ask register, pr iority register, and interrupt pending regist er. All the interrupt reques ts fr om the inter rupt sourc es are f ir[...]

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-8 SRCPND Bit Description Initial State INT_ADC [31] 0 = Not requested, 1 = Reques ted 0 INT_RT C [30] 0 = Not reques ted, 1 = Requested 0 INT_SPI1 [29] 0 = Not reques ted, 1 = Requested 0 INT_UART 0 [28] 0 = Not requested, 1 = Reques ted 0 INT_IIC [27] 0 = Not requested, 1 = Reques ted 0 INT_USBH[...]

S3C2440A RISC MICROPROCESSO R INTERRUPT CONTROLLER 14-9 . INTERRUPT MO DE (INTM OD) REGIST ER This r egister is com posed of 32 bits each of w hich is r elated to an interrupt source. If a specific bit is set to 1, the corres ponding interrupt is proces sed in the FIQ (fas t interrupt) m ode. Otherwise, it is process ed in the IRQ m ode (norm al in[...]

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-10 INTM OD Bit Description Initial State INT_ADC [31] 0 = IRQ, 1 = FIQ 0 INT_RT C [30] 0 = IRQ, 1 = FIQ 0 INT_SPI1 [29] 0 = IRQ, 1 = F IQ 0 INT_UART 0 [28] 0 = IRQ, 1 = FIQ 0 INT_IIC [27] 0 = IRQ, 1 = FIQ 0 INT_USBH [26] 0 = IRQ, 1 = FIQ 0 INT_USBD [25] 0 = IRQ, 1 = FIQ 0 INT_NFCON [24] 0 = IRQ, [...]

S3C2440A RISC MICROPROCESSO R INTERRUPT CONTROLLER 14-11 INTERRUPT MASK (INTM SK) REGISTER This register als o has 32 bits eac h of which is r elated to an interrupt sour ce. If a s pecific bit is set to 1, the CPU does not servic e the interrupt request fr om the corres ponding interrupt source (note that even in s uch a case, the corres ponding b[...]

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-12 INTM SK Bit Description Initial State INT_ADC [31] 0 = Service available, 1 = Mas ked 1 INT_RT C [30] 0 = Ser vice available, 1 = Mask ed 1 INT_SPI1 [29] 0 = Servic e available, 1 = Mask ed 1 INT_UART 0 [28] 0 = Service available, 1 = Mas ked 1 INT_IIC [27] 0 = Service available, 1 = Mas ked 1[...]

S3C2440A RISC MICROPROCESSO R INTERRUPT CONTROLLER 14-13 PRIORITY REGIST ER (PRIORIT Y) Register Address R/W Description Reset Value PRIORITY 0x4A00000C R/W IRQ priority control register 0x7F PRIORITY Bit Descrip tion Initial State ARB_SEL6 [20:19] Arbiter 6 group priority order set 00 = REQ 0-1-2- 3-4-5 01 = REQ 0-2-3- 4-1-5 10 = REQ 0-3-4- 1-2-5 [...]

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-14 INTERRUPT PENDING (INTPND) REGIST ER Each of the 32 bits in the interrupt pending regis ter shows whether the c orresponding interrupt request, which is unmas k ed and w aits for the interrupt to be serviced, has the highest prior ity . Since the INT PND register is located after the priority [...]

S3C2440A RISC MICROPROCESSO R INTERRUPT CONTROLLER 14-15 INTPND Bit Description Init ial State INT_ADC [31] 0 = Not requested, 1 = Reques ted 0 INT_RT C [30] 0 = Not reques ted, 1 = Requested 0 INT_SPI1 [29] 0 = Not reques ted, 1 = Requested 0 INT_UART 0 [28] 0 = Not requested, 1 = Reques ted 0 INT_IIC [27] 0 = Not requested, 1 = Reques ted 0 INT_U[...]

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-16 INTERRUPT OFFSET (INT OFFSET) REGIST ER The value in the interr upt off set register shows which interrupt r equest of IRQ m ode is in the INTPND register. This bit can be cleared autom atically by clear ing SRCPND and INTPND. Register Address R/W Descrip tion Reset Value INTOF FSET 0X4A000014[...]

S3C2440A RISC MICROPROCESSO R INTERRUPT CONTROLLER 14-17 SUB SOURCE PENDING (SUBSRCPND) REGISTER You can clear a specif ic bit of the SUBSRCPND regis ter by writing a data to this register. It clears only the bit positions of the SUBSRCPND regis ter corr esponding to those set to one in the data. T he bit positions corres ponding to those that are [...]

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-18 INTERRUPT SUB MASK (INTSUBM SK) REGISTER This register has 11 bits each of which is related to an interr upt sourc e. If a s pecific bit is s et to 1, the interr upt request from the corresponding inter rupt sourc e is not servic ed by the CPU ( note that even in such a c ase, the corres pondi[...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-1 15 LCD CONTROLLER OVERVIEW The LCD controller in the S3C2440A consists of the logic for tr ansfer ring LCD im age data from a video buf fer located in system m em ory to an external LCD driver. The LCD c ontroller suppor ts m onochrom e, 2-bit per pixel (4-level gray scale) or 4-bit per pixel ( 16-l[...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-2 COMM ON FEATURES The LCD c ontroller has a dedic ated DMA that supports to f etch the im age data fr om video buf fer located in system mem or y . Its features also include: — Dedicated interr upt functions (INT_F rSy n and INT_FiCnt) — T he system m em ory is used as the display mem ory. — Sup[...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-3 BLOCK DIA GRAM System Bus LPC3600 is a t im ing cont rol logic uni t for LTS 350Q1-PD1 or LTS350Q1-P D2. LCC3600 is a t imi ng control l ogic uni t for LTS350Q1-PE1 or LTS 350Q1-PE2. REGBANK LCDCDMA VIDPRCS LPC3600 TIMEGE N VD[23:0] VCLK /LCD_HCLK VLINE / HSYNC / CPV VFRAM E / VSYNC / STV VM / VDEN [...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-4 STN LCD CONTROLLER OPERATION TIM ING GENERA T OR (T IMEGEN) The TIMEG EN generates the c ontrol signals for the LCD dr iver, such as VF RAME, VLINE, VCLK, and VM. These control signals are c losely related to the configuration on the LCDCON1/2/3/4/5 registers in the REGBANK. Based on these programm a[...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-5 Table 15- 1. Relation betw een VCLK an d CLKVAL (STN, HCLK=60M Hz) CLKVA L 60M Hz/X VCLK 2 60 MHz/4 15.0 MHz 3 60 MHz/6 10.0 MHz : : : 1023 60 MHz/2046 29.3 k Hz VIDEO OPERATION The S3C2440A LCD c ontroller supports 8-bit c olor mode (256 co lor mode), 12-bit c olor mode (4096 color mode), 4 level g[...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-6 256 Level Colo r Mo de Operatio n The S3C2440A LCD controller can support an 8-bit per pixel 256 color display m ode. The color display m ode can generate 256 levels of color using the dithering algorithm and FRC. The 8- bit per pixel are encoded into 3-bits f or red, 3-bits for green, and 2-bits for[...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-7 DITHERING AND FRA M E RATE CONTROL In case of STN LCD display ( except m onochrom e) , video data mus t be proces sed by a dithering algorithm. T he DITHF RC block has two functions , such as T im e-based Dithering Algor ithm for reduc ing f lick er and Fram e Rate Control (FRC) for displaying gray [...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-8 Display Types The LCD controller supports 3 types of LCD drivers : 4-bit dual s c an, 4-bit s ingle sc an, and 8- bit single s can dis play mode. Figure 15-2 shows these 3 differ ent display types for m onochrom e display s, and F i gure 15-3 show these 3 diff erent display ty pes f or color displays[...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-9 MEM ORY DATA FORM A T (ST N, BSWP=0) Mono 4-bit Dual Scan Display: Video Buff er Mem ory: Address Data 0000H A[31:0] 0004H B[31:0] • • • 1000H L[31:0] 1004H M[31:0] • • • Mono 4-bit Single Scan Display & 8-bit Sing le Scan Display: Video Buff er Mem ory: Address Data 0000H A[31:0] 00[...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-10 MEM ORY DATA FORM A T ( ST N, BSWP=0 ) (CONTINUED) In 4-level gray mode , 2 bits of video data cor respond to 1 pixel. In 16-level gray mode , 4 bits of video data cor respond to 1 pixel. In 256 level colo r mode , 8 bits (3 bits of red, 3 bits of green, and 2 bits of blue) of video data corres pond[...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-11 16 BPP Color mode 16 bits (5 bits of red, 6 bits of green, 5 bits of blue) of video data cor respond to 1 pixel. But, stn contr oller will use only 12 bit c olor data. It means that only upper 4bit each c olor data will be used as pix el data ( R[15:12], G[10:7], B[4:1]). T he following table shows[...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-12 4-bit Dual Scan Display 4-bit Single Scan Display 8-bit Single Scan Display . . . . . . . . . . . . VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 . . . . . . VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 . . . . . . Figure 15-2. Monochrome Display Type s (STN)[...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-13 VD3 R1 VD2 G1 VD1 B1 VD0 R2 VD3 G2 VD2 B2 VD1 R3 VD0 G3 . . . . . . 1 Pixel . . . . . . 4-bit Dual Scan Display VD3 R1 VD2 G1 VD1 B1 VD0 R2 VD3 G2 VD2 B2 VD1 R3 VD0 G3 . . . . . . 1 Pixel 4-bit Single Scan Display VD7 R1 VD6 G1 VD5 B1 VD4 R2 VD7 G2 VD6 B2 VD5 R3 VD4 G3 . . . . . . 1 Pixel 8-bit Sin[...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-14 Timing Requirements Image data s hould be transf erred f rom the m emor y to the LCD dr iver using the VD[7:0] signal. VCLK signal is used to clock the data into the LCD dr iver's shif t register . After eac h horizontal line of data has been shif ted into the LCD driver's s hift regis ter[...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-15 WDLY WLH LINE1 LINE2 LINE3 LINE4 LINE5 LINE6 LINE1 LINEn First Line Timing LINECNT decreases & Display the 1st line LINEBLANK First Line Check & Data Timing VFRAME VM VLINE VFRAME VM VLINE LINECNT VCLK VFRAME VM VLINE VCLK VD[7:0] WDLY WDLY Display the last line of the previous frame Full F[...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-16 TFT LCD CONTROLLER OPERA TION The T IMEGEN generates the control signals f or LCD driver, s uch as VSYNC, HSYNC, VCLK, VDEN, and LEND signal. These control signals are highly related with the configurations on the LCDCON1/2/3/4/5 registers in the REGBANK. Bas e on thes e progr amm able conf iguratio[...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-17 MEM ORY DATA FORM A T (TFT ) This section inc ludes som e exam ples of each display mode. 24BPP Display (BSW P = 0, HW SW P = 0, BPP24BL = 0) D[31:24] D[23: 0] 000H Dumm y Bit P1 004H Dumm y Bit P2 008H Dumm y Bit P3 ... (BSW P = 0, HW SW P = 0, BPP24BL = 1) D[31:8] D[ 7:0] 000H P1 Dum m y Bit 004H[...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-18 16BPP Display (BSW P = 0, HW SW P = 0) D[31:16] D[15: 0] 000H P1 P2 004H P3 P4 008H P5 P6 ... (BSW P = 0, HW SW P = 1) D[31:16] D[ 15:0] 000H P2 P1 004H P4 P3 008H P6 P5 ... P1 P2 P3 P4 P5 ...... LCD Panel VD Pin Description s at 16BPP (5:6:5) VD 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4[...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-19 8BPP Display (BSW P = 0, HW SW P = 0) D[31:24] D[ 23:16] D[ 15:8] D[7:0] 000H P1 P2 P3 P4 004H P5 P6 P7 P8 008H P9 P10 P11 P12 ... (BSW P = 1, HW SW P = 0) D[31:24] D[ 23:16] D[ 15:8] D[7:0] 000H P4 P3 P2 P1 004H P8 P7 P6 P5 008H P12 P11 P10 P9 ... P1 P2 P3 P4 P5 ...... LCD Panel P6 P7 P8 P10 P11 P[...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-20 4BPP Display (BSW P = 0, HW SW P = 0) D[31: 28] D[27:24] D[ 23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 000H P1 P2 P3 P4 P5 P6 P7 P8 004H P9 P10 P11 P12 P13 P14 P15 P16 008H P17 P18 P19 P20 P21 P22 P23 P24 ... (BSW P = 1, HW SW P = 0) D[31: 28] D[27:24] D[ 23:20] D[19:16] D[15:12] D[11:8] D[7:4] [...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-21 256 PA L ETT E USA G E (T FT) Palette Configur ation and Format Control The S3C2440A provides 256 color palette f or T FT LCD Contr ol. The us er can selec t 256 colors f rom the 64K colors in these two form ats. The 256 c olor palette consis ts of the 256 ( depth) x 16-bit SPSRAM. T he palette sup[...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-22 12345 LCD Panel 16BPP 5:5:5+1 Format(Non-Palette) A[31] A[30] A[29] A[28] A[27] A[26]A[25] A[24] A[23] A[22] A[21] A[20] A[19]A[18] A[17] A[16] R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 R4 B3 B2 B1 B0 I A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] R4 R3 R2 R1 R0 G4 G3 G2[...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-23 INT_FrSyn VSYNC HSYNC VDEN HSYNC VCLK VD LEND VBPD+1 VSPW+1 VFPD+1 HBPD+1 HFPD+1 HSPW+1 VDEN 1 Frame 1 Line LINEVAL +1 HOZVAL+1 Figure 15-6. T FT LCD Timing Example[...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-24 SA M SUNG T FT LCD PA NEL (3.5” PORT RA IT / 256K COLO R / REFLECTIVE A-SI/TRANSFLECTIVE A - SI TFT LCD) The S3C2440A s upports following SEC T FT LCD panels . 1. SAMSUNG 3.5” Portr ait / 256K Color /Reflec tive a-Si TF T LCD. LTS350Q1- PD1: TF T LCD panel with touch panel and fr ont light unit [...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-25 VIRTUAL DISPLA Y (TFT /STN) The S3C2440A s upports hardware horizontal or vertic al scrolling. If the sc reen is sc rolled, the fields of LCDBASEU and LCDBASEL in LCDSADDR1/2 registers need to be changed (see F igure 15-8), exc ept the values of PAGEW IDTH and O FFSIZE. The video buf fer in which t[...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-26 LCD POWER ENA BLE (ST N/TFT ) The S3C2440A provides Power enable ( PW REN) f unc tion. W hen PW REN is s et to m ak e PW REN s ignal enabled, the output value of LCD_PW REN pin is controlled by ENVID. In other w ords, If LCD_PW REN pin is connected to the power on/of f c ontrol pin of the LCD panel,[...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-27 LCD CONT ROLLER SPECIAL REGISTERS LCD Control 1 Register Register Address R/W Description Reset Valu e LCDCON1 0X4D000000 R/W LCD control 1 regis ter 0x00000000 LCDCON1 Bit Description Initial State LINECNT (read only) [27:18] Pr ovide the status of the line counter. Down count from LINEVAL to 0 00[...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-28 LCD Control 2 Register Register Address R/W Description Reset Valu e LCDCON2 0X4D000004 R/W LCD control 2 register 0x00000000 LCDCON2 Bit Description Initial State VBPD [31:24] TFT : Vertical back porch is the number of inactive lines at the start of a fram e, af ter vertic al synchronization period[...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-29 LCD Control 3 Register Register Address R/W Description Reset Valu e LCDCON3 0X4D000008 R/W LCD control 3 regis ter 0x00000000 LCDCON3 Bit Description Initial state HBPD (TF T) [25:19] TFT : Horizontal back porc h is the number of VCLK periods between the falling edge of HSYNC and the start of acti[...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-30 LCD Control 4 Register Register Address R/W Description Reset Valu e LCDCON4 0X4D00000C R/W LCD c ontrol 4 register 0x00000000 LCDCON4 Bit Description Initial state MVAL [15:8] STN : T hese bit def ine the rate at which the VM signal will toggle if the MMODE bit is set to logic '1'. 0X00 H[...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-31 LCD Control 5 Register Register Address R/W Description Reset Valu e LCDCON5 0X4D000010 R/W LCD control 5 regis ter 0x00000000 LCDCON5 Bit Description Initial state Reserved [31:17] T his bit is res erved and the value should be ‘0’. 0 VSTAT US [16:15] TFT : Vertical Status (r ead only ) . 00 =[...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-32 LCD Control 5 Register (Continue d) LCDCON5 Bit Description Initial state INVVDEN [6] TFT : This bit indicates the VDEN signal polarity. 0 = normal 1 = inverted 0 INVPW REN [5] STN/T FT : This bit indicates the PW REN signal polar ity . 0 = normal 1 = inverted 0 INVLEND [4] TFT : This bit indicates [...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-33 FRAME BUFFER ST A RT ADDRESS 1 REGISTER Register Address R/W Description Reset Valu e LCDSADDR1 0X4D000014 R/W ST N/TF T : Fr am e buffer start addres s 1 register 0x00000000 LCDSA DDR1 Bit Descript ion Initial State LCDBANK [29:21] T hese bits indicate A[30:22] of the bank location f or the video [...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-34 FRAME Buffer St art A d dress 3 Register Register Address R/W Description Reset Valu e LCDSADDR3 0X4D00001C R/W STN/T FT : Virtual sc reen address set 0x00000000 LCDSA DDR3 Bit Description Initial State OFFSIZE [21:11] Virtual screen of fset s ize (the number of half words) . This value defines the [...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-35 RED Lookup Table Register Register Address R/W Description Reset Valu e REDLUT 0X 4D000020 R/W STN : Red look up table regis ter 0x00000000 REDLUT Bit Description Initial State REDVAL [31:0] Thes e bits define which of the 16 shades will be chos en by eac h of the 8 possible red c ombinations . 000[...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-36 Dithering Mode Register Register A ddress R/W Descriptio n Reset Value DITHMO DE 0X4D00004C R/W ST N : Dithering m ode regist er. This register r eset value is 0x 00000 But, user can change this value to 0x12210. (Refer to a sam ple program sourc e for the lates t value of this r egister.) 0x00000 D[...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-37 Temp Palette Register Register A ddress R/W Descriptio n Reset Value TPAL 0X 4D000050 R/W TFT : Tem porary palette register. This register value will be video data at next f ram e. 0x 00000000 TPAL Bit Descriptio n Initial state TPALEN [24] Tem porary palette register enable bit. 0 = Disable 1 = En[...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-38 LCD Interrupt Pe nding Register Register A ddress R/W Descriptio n Reset Value LCDINTPND 0X 4D000054 R/W Indic ate the LCD interrupt pending regis ter 0x 0 LCDINTPND Bit Description In itial state INT_FrSyn [1] LCD fram e synchronized interrupt pending bit. 0 = The interr upt has not been requested.[...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-39 LCD Interrupt M ask Register Register A ddress R/W Descriptio n Reset Value LCDINTMSK 0X 4D00005C R/W Determ ine which interrupt sour ce is m ask ed. The m ask ed interr upt source will not be ser viced. 0x 3 LCDINTM SK Bit Description Initial state FIW SEL [2] Determine the tr igger level of LCD F[...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-40 TCON Control Register Register A ddress R/W Descriptio n Reset Value TCO NSEL 0X4D000060 R/W This register c ontrols the LPC3600/LCC3600 modes . 0xF84 TCO NSEL Bit Description Initial state LCC_TEST 2 [11] LCC3600 Tes t Mode 2 ( Read Only ) 1 LCC_TEST 1 [10] LCC3600 Tes t Mode 1 ( Read Only ) 1 LCC_[...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-41 Register S etting Guide (STN) The LCD c ontroller supports m ultiple screen s izes by spec ial register setting. The CLKVAL value determines the frequency of VCLK. T his value has to be determ ined s uch that the VCLK value is greater than data tr ansmission r ate. The data transm ission rate for t[...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-42 Example 1: 160 x 160, 4-level gray, 80 fram e/sec , 4-bit single sc an display, HCLK frequency is 60 MHz W LH = 1, W DLY = 1. Data transm ission r ate = 160 x 160 x 80 x 1/4 = 512 k Hz CLKVAL = 58, VCLK = 517KHz HOZVAL = 39, LINEVAL = 159 LINEBLANK =10 LCDBASEL = LCDBASEU + 3200 Note The higher the [...]

S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-43 Gray Level Selection Guide The S3C2440A LCD controller can gener ate 16 gray level using Fram e Rate Control (FRC) . The FRC character istics m ay cause unexpected patterns in gr ay level. Thes e unwanted erroneous patterns m ay be shown in fast r esponse LCD or at lower f ram e rates. Because the [...]

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-44 Register Se tting Guide (T FT LCD) The CLKVAL regis ter value determ ines the f requency of VCLK and fram e rate. Fram e Rate = 1/ [ { (VSPW +1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1) } x {(HSPW +1) + (HBPD +1) + (HFPD+1) + (H OZVAL + 1) } x { 2 x ( CLKVAL+1 ) / ( HCLK ) } ] For applications, the sy[...]

S3C2440A RISC MICROPROCESSOR A DC AND TOUCH SCREEN INTERFACE 16-1 16 A DC & TOUCH SCREEN INTERFA CE OVERVIEW The 10-bit CMOS ADC (Analog to Digital Converter) is a rec ycling ty pe device with 8-channel analog inputs . It converts the analog input signal into 10-bit binary digital codes at a max imum c onversion rate of 500KSPS with 2.5MHz A/D [...]

ADC A ND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR 16-2 A DC & TOUCH SCREE N INTERFA CE OP E RA TION BLOCK DIA GRAM Figure 16-1 shows the f unctional block diagram of A/D converter and T ouch Scr een Interfac e. Note that the A/D converter devic e is a rec y c ling type. P ullup W ai ti ng f o r I nt e r rupt Mode I NT_TC IN T_A DC 8:[...]

S3C2440A RISC MICROPROCESSOR A DC AND TOUCH SCREEN INTERFACE 16-3 FUNCTION DESCRIPTIONS A /D Conversion Time W hen the GCLK fr equency is 50MHz and the pr escaler value is 49, total 10-bit conver sion tim e is as f ollows. A/D converter freq. = 50MHz/(49+1) = 1MHz Conversion time = 1/(1M Hz / 5cycles) = 1/200KHz = 5 us NOTE This A/D converter w as [...]

ADC A ND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR 16-4 Programming Note s 1. T he A/D converted data can be access ed by m eans of interrupt or polling m ethod. W ith interrupt m ethod the overall conversion tim e - from A/D converter start to c onverted data read - m ay be delay ed becaus e of the return tim e of interrupt ser vice rout[...]

S3C2440A RISC MICROPROCESSOR A DC AND TOUCH SCREEN INTERFACE 16-5 A DC AND TOUCH SCREEN INTERFA CE SPECI A L REGI STERS A DC CONT ROL REGISTER (ADCCON) Register Address R/W Description Reset Value ADCCON 0x5800000 R/W ADC Control Register 0x3FC4 A DCCON Bit Description Initial State ECFLG [15] End of conversion f lag(Read only) 0 = A/D conversion i[...]

ADC A ND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR 16-6 A DC T OUCH SCREEN CONTROL REGIST ER (A DCTSC) Register Address R/W Description Reset Value ADCTSC 0x5800004 R/W ADC T ouch Scr een Control Register 0x58 A DCT SC Bit Description In itial St ate UD_SEN [8] Detect Stylus Up or Down status. 0 = Detect Stylus Down Interrupt Signal. 1 = [...]

S3C2440A RISC MICROPROCESSOR A DC AND TOUCH SCREEN INTERFACE 16-7 A DC ST A RT DELA Y REGISTER (ADCDLY) Register Address R/W Description Reset Value ADCDLY 0x5800008 R/W ADC Start or Interval Delay Regis ter 0x00ff A DCDLY Bit Description Initial State DELAY [15:0] 1) Nor m al Conversion Mode, XY Position Mode, Auto Position Mode. → ADC conversio[...]

ADC A ND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR 16-8 A DC CONVERSION DATA REGIST ER (A DCDAT0) Register Address R/W Description Reset Value ADCDAT0 0x580000C R ADC Conversion Data Register - A DCDAT0 Bit Description Initial State UPDOW N [15] Up or Down state of Stylus at W aiting f or Interrupt Mode. 0 = Sty lus down state. 1 = Sty lu[...]

S3C2440A RISC MICROPROCESSOR A DC AND TOUCH SCREEN INTERFACE 16-9 A DC CONVERSION DATA REGIST ER (A DCDAT1) Register Address R/W Description Reset Value ADCDAT1 0x5800010 R ADC Conversion Data Register - A DCDAT1 Bit Description Initial State UPDOW N [15] Up or Down state of Stylus at W aiting f or Interrupt Mode. 0 = Sty lus down state. 1 = Sty lu[...]

ADC A ND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR 16-10 NOT ES[...]

S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK 17-1 17 REA L TIME CLOCK OVERVIEW The Real T im e Clock (RT C) unit can be operated by the backup batter y while the system power is off. T he RT C can transm it 8-bit data to CPU as Binary Coded Decimal (BCD) values us ing the ST RB/LDRB ARM operation. T he data include the tim e by sec ond, minute, hou[...]

REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR 17-2 REA L T IM E CLOCK OPERA TION 2 15 Clock Divider XTOrtc XTIrtc Control Register SEC MIN HOUR DAY DATE MON YEAR Leap Year Generator Alarm Gene r ator Reset Register 1 Hz INT_RTC RTCCON RTCA LM RTCRST Time Tick Generat or TIME TICK TICNT 128 Hz PMW KUP Figure 17-1. Real T ime Clock Block Diagram L E A[...]

S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK 17-3 A LARM FUNCTION The RT C generates an alar m s ignal at a specif ied tim e in the power-off mode or norm al operation m ode. In nor m al operation m ode, the alarm inter rupt ( INT_RT C) is ac tivated. In the power-off m ode, the power managem ent wakeup (PMW KUP) signal is activated as well as the [...]

REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR 17-4 REA L TIME CLOCK SPECIA L REGISTERS REA L T IM E CLOCK CONTROL (RTCCON) REGIST ER The RT CCON regis ter consis ts of 4 bits such as the RT CEN, which controls the read/write enable of the BCD registers , CLKSEL, CNTSEL, and CLKRST for testing. RTCEN bit can c ontrol all interf aces between the CPU a[...]

S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK 17-5 RTC ALA RM CONT ROL (RTCALM) REGIST ER The RT CALM register determ ines the alarm enable and the alarm tim e. Please note that the RTCALM register generates the alarm signal through both INT _RT C and PMW KUP in power down m ode, but only through INT _RT C in the norm al operation m ode. Register Ad[...]

REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR 17-6 A LARM SECOND DATA (A L MSEC) REGIST ER Register Address R/W Descript ion Reset Valu e ALMSEC 0x57000054(L) 0x57000057(B) R/W (by byte ) Alarm second data r egister 0x0 A LM SEC Bit Description Initial State Reserved [7] 0 SECDATA [6:4] BCD value for alarm second. 0 ~ 5 000 [3:0] 0 ~ 9 0000 A LARM M[...]

S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK 17-7 A LARM DA T E DA T A (ALMDA T E) REGISTER Register Address R/W Description Reset Valu e ALMDATE 0x 57000060(L) 0x57000063(B) R/W (by byte ) Alarm date data register 0x 01 A LM DATE Bit Descrip tion Initial Stat e Reserved [7:6] 00 DATEDAT A [5:4] BCD value for alarm date, f rom 0 to 28, 29, 30, 31. [...]

REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR 17-8 BCD SECOND (BCDSEC) REGISTER Register Address R/W Description Reset Value BCDSEC 0x57000070(L) 0x57000073(B) R/W (by byte ) BCD s econd register Undef ined BCDSEC Bit Description In itial Stat e SECDATA [6:4] BCD value f or sec ond. 0 ~ 5 - [3:0] 0 ~ 9 - BCD MINUT E (BCDM IN) REGISTER Register Addre[...]

S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK 17-9 BCD DA T E (BCDDA T E) REGISTER Register Address R/W Description Reset Valu e BCDDATE 0x5700007C(L) 0x5700007F(B) R/W (by byte ) BCD date regis ter Undef ined BCDDA T E Bit Description Initial State Reserved [7:6] - DATEDAT A [5:4] BCD value for date. 0 ~ 3 - [3:0] 0 ~ 9 - BCD DA Y (BCDDAY) REGISTER[...]

REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR 17-10 BCD YEA R (BCDY EA R) REGIST ER Register Address R/W Descriptio n Reset Valu e BCDYEAR 0x57000088(L) 0x5700008B(B) R/W (by byte ) BCD year register Undef ined BCDYEA R Bit Description Initial State YEARDATA [7:0] BCD value for year. 00 ~ 99 -[...]

S3C2440A RISC MICROPROCESSOR WATCHDOG TIMER 18-1 18 WA TCHDOG TIMER OVERVIEW The S3C2440A watchdog tim er is us ed to res um e the c ontroller operation whenever it is dis turbed by m alf unctions such as nois e and system error s. It can be used as a normal 16- bit interval tim er to request interrupt s ervice. T he watchdog timer generates the re[...]

WATCHDOG TIMER S3C2440A RISC MICROPROCESSOR 18-2 WA T CHDOG TIM ER OPERA T ION Figure 18-1 shows the functional block diagram of the watchdog tim er. The watchdog tim er us es only PCLK as its source c lock . The PCLK f requency is prescaled to generate the c orresponding watchdog timer clock, and the resulting f requency is divided again. Reset Si[...]

S3C2440A RISC MICROPROCESSOR WATCHDOG TIMER 18-3 WA TCHDOG TIMER SPECIA L REGISTERS WA T CHDOG TIM ER CONTROL (W TCON) REGISTER The W T CON regis ter allows the user to enable/disable the watchdog tim er, s elect the cloc k signal fr om 4 diff erent sources , enable/disable interrupts, and enable/disable the w atchdog tim er output.T he W atchdog t[...]

WATCHDOG TIMER S3C2440A RISC MICROPROCESSOR 18-4 WA T CHDOG TIM ER DA TA (WTDA T ) REGISTER The W TDAT register is us ed to specif y the tim e- out duration. The c ontent of W T DAT c annot be autom atically loaded into the tim er counter at initial watchdog tim er operation. However, using 0x 8000 (initial value) will drive the first tim e- out. I[...]

S3C2440A RISC MICROPROCESSO R MM C/SD/SDIO CONTROLLER 19-1 19 MMC/SD/SDIO Controller FEA TURES  SD Memor y Car d Spec(ver 1.0) / MMC Spec (2.11) com patible  SDIO Card Spec( Ver 1.0) com patible  16 words(64 bytes) FIFO for data Tx/Rx  40-bit Com mand Regis ter  136-bit Response Regis ter  8-bit Presc aler logic( Freq = System Clo[...]

MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR 19-2 SD OPERA TION A serial cloc k line s y nc hronizes shif ting and sam pling of the inf orm ation on the f ive data lines . T he trans m ission frequenc y is c ontrolled by making the appropr iate bit settings to the SDIPRE regis ter. You can m odify its f requency to adjust the baud rate data [...]

S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER 19-3 SDIO OPERA TION There are two functions of SDIO oper ation: SDIO Inter rupt r ec eiving and Read W ait Request generation. T hese two functions can operate w hen RcvIO Int bit and RwaitEn bit of SDICON register is activated res pectively. And tw o functions have the steps and c onditions lik [...]

MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR 19-4 SDI SPECIA L REGISTERS SDI Control Register(SDICON) Register Address R/W Description Reset Value SDICON 0x5A000000 R/W SDI Control Register 0x0 SDICON Bit Descript ion Initial Value Reserved [31:9] SDMMC Reset (SDreset) [8] Reset whole sdm m c bloc k. T his bit is autom atically cleared. 0 = [...]

S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER 19-5 SDI Command A rgument Register(S DICmdArg) Register Address R/W Description Reset Value SDICmdAr g 0x5A000008 R/W SDI Comm and Argum ent Regis ter 0x0 SDICmdA rg Bit Descript ion Initial Value CmdAr g [31:0] Com mand Argument 0x00000000 SDI Command Control Register (SDICmdCon) Register Addres[...]

MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR 19-6 SDI Command Status Re gister(SDICmdSta) Register Address R/W Description Reset Value SDICmdSta 0x 5A000010 R/(C) SDI Com m and Status Regis ter 0x0 SDICmdSta Bit Descripti on Initial Value Reserved [31:13] Response CRC Fail(Rsp Crc) [12] R/C CRC check failed when com m and respons e received.[...]

S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER 19-7 SDI Response Regist er 2(SDIRSP2) Register Address R/W Description Reset Value SDIRSP2 0x5A00001C R SDI Respons e Register 2 0x0 SDIRSP2 Bit Descript ion In itial Value Response2 [31:0] unused(short) , card status [63:32](long) 0x00000000 SDI Response Regist er 3(SDIRSP3) Register Address R/W[...]

MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR 19-8 SDI Data Control Register(SDIDatCon) Register Address R/W Description Reset Value SDIDatCon 0x5A00002C R/W SDI Data control Register 0x0 SDIDatCon Bit Description Init ial Value Reserved [31:25] Burst4 enable (Burst4) [24] Enable Bur st4 m ode in DMA m ode. This bit should be set only when Da[...]

S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER 19-9 SDI Data Remain Counte r Register(S DIDa tCnt) Register Address R/W Description Reset Value SDIDatCnt 0x5A000030 R SDI Data Rem ain Counter Regis ter 0x0 SDIDatCnt Bit Description Initial Value Reserved [31:24] BlkNum Cnt [23:12] Rem aining Block num ber 0x000 BlkCnt [11:0] Remaining data byt[...]

MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR 19-10 SDI FIFO Status Registe r(SDIFSTA ) Register Address R/W Description Reset Value SDIFSTA 0x5A000038 R/(C) SDI FIFO Status Register 0x0 SDIFSTA Bit Description Initial State Reserved [31:16] FIFO Reset(FRST) [16] C Reset FIF O value. T his bit is autom atically cleared. 0 = norm al m ode, 1 =[...]

S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER 19-11 SDI Interrupt Mask Reg ister(SDIIntM sk) Register Address R/W Description Reset Value SDIIntMsk 0x5A00003C R/W SDI Interrupt Mas k Regis ter 0x0 SDIIntM sk Bit Description Initial Value Reserved [31 : 19] NoBusy Interrupt Enable (NoBusyInt) [18] Determ ines SDI generate an inter rupt if bus [...]

MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR 19-12 SDI Data Register(SDIDA T ) Register Address R/W Descriptio n Reset Value SDIDAT 0x5A000040, 44, 48, 4C(Li/W , Li/HW , Li/B, Bi/W ) 0x5A000041(Bi/HW ), 0x5A000043(Bi/B) R/W SDI Data Register 0x0 SDIDA T Bit Descriptio n Initial State Data Register [31:0] This field c ontains the data to be t[...]

S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE 20-1 20 IIC-BUS INTERFA CE OVERVIEW The S3C2440A RISC m icr oprocess or can suppor t a multi- m aster IIC-bus serial interf ace. A dedicated serial data line (SDA) and a ser ial clock line (SCL) car ry inform ation between bus m as ters and peripher al devices which ar e connected to the IIC-bus . The [...]

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-2 PCLK Address Register SDA 4-bit Prescaler IIC-Bus Control Logic IICSTAT IICCON Comparator Shift Register Shift Register (IICDS) Data Bus SCL Figure 20-1. IIC-Bu s Block Diagram[...]

S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE 20-3 IIC-BUS INTERFACE The S3C2440A IIC-bus interfac e has four operation m odes: — Master tr ansm itter m ode — Master receive m ode — Slave transm itter m ode — Slave rec eive mode Functional relations hips am ong these operating m odes ar e described below. START A ND ST OP CONDITIONS W hen [...]

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-4 DA TA TRA NS FER FOR MA T Every by te placed on the SDA line should be eight bits in length. The bytes can be unlim itedly transmitted per transf er. T he f irst by te f ollowing a Start condition s hould have the address f ield. The addr ess f ield can be transm itted by the master when the IIC-b[...]

S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE 20-5 SDA Acknowledgement Signal from Receiver SCL S 1 27 8 9 1 2 9 Acknowledgement Signal from Receiver MSB ACK Byte C omplete, Inter rupt within Receiver Clock Line Held Low by receiver and/or transm itter Figure 20-4. Data T ransfer o n the IIC-Bu s A CK SIG NA L T RANSMISSION To com plete a one-by t[...]

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-6 REA D-WRIT E OPERA T ION In Trans m itter m ode, when the data is transfer red, the IIC-bus inter face will wait until IIC-bus Data Shift ( IICDS) register rec eives a new data. Before the new data is written into the r egister, the SCL line will be held low, and then released af ter it is written[...]

S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE 20-7 FLOWCHA RT S OF OPERATIONS IN EA CH M ODE The f ollowing steps m ust be exec uted before any IIC Tx/Rx oper ations. 1) W rite own slave address on IICADD register, if needed. 2) Set IICCON regist er. a) Enable interrupt b) Define SCL period 3) Set IICSTAT to enable Serial Output Write slave addres[...]

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-8 Write slave address to IICDS. Write 0xB0 (M/R Start) to IICSTAT. The data of the IICDS (slave address) is transmitted. ACK period and then interrupt is pending. Write 0x90 (M/R Stop) to IICSTAT. Read a new data from IICDS. Stop? Clear pending bit to resume. SDA is shifted to IICDS. START Master Rx[...]

S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE 20-9 IIC detects s tart signal. and, IICDS receives data. IIC com pares IICADD and IICDS ( the received s lave address ). W r ite data to IICDS. The IIC addres s m atch interrupt is gener ated. Clear pending bit to resume. The data of the IICDS is shifted to SDA. START Slave Tx mode has been configur e[...]

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-10 IIC detects s tart signal. and, IICDS receives data. IIC com pares IICADD and IICDS ( the received s lave address ). Read data from IICDS. The IIC addres s m atch interrupt is gener ated. Clear pending bit to resume. SDA is shifted to IICDS. START Slave Rx m ode has been configur ed. END Matched?[...]

S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE 20-11 IIC-BUS INTER FAC E SPECIAL R EGISTERS MULT I-M A ST ER IIC-BUS CONTROL (IICCON) REGIST ER Register Address R/W Descriptio n Reset Value IICCON 0x54000000 R/W IIC-Bus control r egister 0x0X IICCON Bit Description Initial St ate Ack nowledge generation (1) [7] IIC-bus ack nowledge enable bit. 0 : [...]

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-12 MULT I-M A ST ER IIC-BUS CONT ROL/STATUS (IICSTA T) REGISTER Register Address R/W Descriptio n Reset Value IICSTAT 0x 54000004 R/W IIC-Bus contr ol/status regis ter 0x0 IICSTAT Bit Description Initial State Mode selection [7:6] IIC-bus m aster /slave T x/Rx m ode select bits. 00 : Slave receive m[...]

S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE 20-13 MU LTI- MASTER IIC-BUS ADDRESS (IICA DD) REGIST ER Register Address R/W Descriptio n Reset Value IICADD 0x54000008 R/W IIC- Bus address r egister 0x XX IICA DD Bit Description In itial St ate Slave address [7:0] 7-bit slave addres s, latched f rom the IIC-bus. W hen serial output enable = 0 in th[...]

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-14 MULT I-M A ST ER IIC-BUS LINE CONTROL(IICLC) REGIST ER Register Address R/W Descriptio n Reset Value IICLC 0x54000010 R/W IIC-Bus m ulti-m aster line control regis ter 0x00 IICLC Bit Descript ion Initial St ate Filter Enable [2] IIC-bus filter enable bit. W hen SDA port is operating as input, thi[...]

S3C2440A RISC MICROPROCESSO R IIS-BUS INTERFACE 21-1 21 IIS-BUS INTERFA CE OVERVIEW Currently , m any di gital audio sy stem s are attracting the consumers on the m ark et, in the form of com pact discs, digital audio tapes , digital sound pr ocessor s, and digital T V sound. T he S3C2440A Inter-IC Sound ( IIS) bus interfac e can be used to im plem[...]

IIS-BUS INTERFACE S3C2440A RISC MICROPRO CESSOR 21-2 BLOCK DIA GRAM ADDR DAT A CNTL PCLK BRFC I PSR_A I PSR_B TxFI FO RxFI FO SCLKG CHNC SFTR L RCK SCLK SD CDCL K MP LL i n Figure 21-1. IIS-B us Block Diagram FUNCTIONA L DESCRIP TIONS Bus interf ace, register bank, and s tate m achine (BRFC): Bus interfac e logic and FIFO access are controlled by t[...]

S3C2440A RISC MICROPROCESSO R IIS-BUS INTERFACE 21-3 D M A T R AN S F E R In this m ode, transm it or rec eive FIFO is acces sible by the DMA controller. DMA service r equest in transm it or receive m ode is m ade by the FIFO ready flag automatic ally. TRANSMIT A ND RECEIVE M ODE In this m ode, IIS bus interf ace can tr ansm it and receive data sim[...]

IIS-BUS INTERFACE S3C2440A RISC MICROPRO CESSOR 21-4 IIS-bus Format (N=8 or 16) MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) LRCK SCLK SD LEFT RIGHT LEFT MSB-justified Format (N=8 or 16) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last) LRCK SCLK SD LEFT RIGHT MSB (1st) Figure 21-2. IIS-B[...]

S3C2440A RISC MICROPROCESSO R IIS-BUS INTERFACE 21-5 IIS-BUS INTERF ACE SPEC IAL REGISTERS IIS CONTROL (IISCON) REGIST ER Register Address R/W Description Reset Value IISCON 0x55000000 (Li/HW , Li/W , Bi/W ) 0x55000002 (Bi/HW ) R/W IIS c ontrol register 0x 100 IISCON Bit Descrip tion Init ial St ate Left/Right channel index (Read only) [8] 0 = Left[...]

IIS-BUS INTERFACE S3C2440A RISC MICROPRO CESSOR 21-6 IIS MO DE REGIST ER (IISMO D) REGIST ER Register Address R/W Description Reset Value IISMOD 0x 55000004 (Li/W , Li/HW , Bi/W ) 0x55000006 (Bi/HW ) R/W IIS m ode register 0x 0 IISMO D Bit Descriptio n Init ial State Maste r Clock Sele ct [9] Master clo ck select 0 = PCLK 1 = MPLLin 0 Master/slave [...]

S3C2440A RISC MICROPROCESSO R IIS-BUS INTERFACE 21-7 IIS PRESCA LER ( IISPSR) REGIST ER Register Address R/W Description Reset Value IISPSR 0x55000008 ( Li/HW , Li/W , Bi/W ) 0x5500000A (Bi/HW ) R/W IIS pr escaler regis ter 0x0 IISPSR Bit Descript ion Initial State Prescaler control A [9:5] Data value: 0 ~ 31 Note: Prescaler A mak es the m as ter c[...]

IIS-BUS INTERFACE S3C2440A RISC MICROPRO CESSOR 21-8 IIS FIFO CONT ROL (IISFCON) REGIST ER Register Address R/W Descriptio n Reset Value IISFCON 0x 5500000C (Li/HW , Li/W , Bi/W ) 0x5500000E (Bi/HW ) R/W IIS FIFO interf ace regis ter 0x 0 IISFCON Bit Description Init ial State Trans m it FIFO ac cess m ode s elect [15] 0 = Norm al 1 = DMA 0 Receive[...]

S3C2440A RISC MICROPROCESSOR SPI 22-1 22 SPI OVERVIEW The S3C2440A Serial Per ipheral Interfac e (SPI) can inter face with the ser ial data transfer . T he S3C2440A includes two SPI, eac h of which has two 8-bit shift regis ters f or trans mis sion and receiving, r espectively. During an SPI transf er, data is simultaneously transmitted (shif ted o[...]

SPI S3C2440A RISC MICROPROCESSOR 22-2 BLOCK DIA GRAM 8bit Prescaler 1 PCLK Status Register 1 Prescaler Register 1 /SS nSS 0 SCK SPICLK 0 MOSI SPIMOSI 0 MISO SPIMISO 0 Pin Control Logic 0 MSTR Tx 8bit Shift Reg 0 Rx 8bit Shift Reg 0 LSB MSB LSB MSB 8 8 Clock SPI Clock (Master) CPOL CPHA CLOCK Logic 0 MULF DCOL REDY APB I/F 0 (INT DMA 0) Master Slave[...]

S3C2440A RISC MICROPROCESSOR SPI 22-3 SPI OPERA TION Using the SPI interf ace, S3C2440A can s end/receive 8-bit data s imultaneous ly with an external device. A serial clock line is synchronized with the tw o data lines for shifting and s am pling of the inf orm ation. W hen the SPI is the mas ter, trans mis sion frequenc y can be controlled by s e[...]

SPI S3C2440A RISC MICROPROCESSOR 22-4 SPI TRANSFER FORM A T The S3C2440A s upports 4 diff erent f orm ats to transf er data. Figure 22- 2 shows the four wavef orm s for SPICLK. * LSB of previously transmitted character Cycle MOSI 12345678 MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB SPICLK MISO MSB CPOL = 1, CPHA = 1 (Format B) * MSB of character just recei[...]

S3C2440A RISC MICROPROCESSOR SPI 22-5 TRANSMITT ING PROCEDURE FOR DM A 1. SPI is conf igured as DMA m ode. 2. DMA is conf igured properly. 3. SPI r equests DMA s ervice. 4. DMA tr ansm its 1byte data to the SPI. 5. SPI tr ansm its the data to card. 6. Retur n to Step 3 until DMA count becom es 0. 7. SPI is conf igured as interr upt or polling m ode[...]

SPI S3C2440A RISC MICROPROCESSOR 22-6 SPI SPECIA L REGISTERS SPI CONTROL REGIST ER Register Address R/W Description Reset Value SPCON0 0x 59000000 R/W SPI channel 0 c ontrol register 0x00 SPCON1 0x 59000020 R/W SPI channel 1 c ontrol register 0x00 SPCONn Bit Description Init ial State SPI Mode Select (SMOD) [6:5] Determ ine how SPTDAT is read/writt[...]

S3C2440A RISC MICROPROCESSOR SPI 22-7 SPI STATUS REGIST ER Register Address R/W Description Reset Value SPSTA0 0x59000004 R SPI c hannel 0 status r egister 0x01 SPSTA1 0x59000024 R SPI c hannel 1 status r egister 0x01 SPSTAn Bit Description Initial Stat e Reserved [7:3] Data Collision Error Fla g (DCOL) [2] Th is flag is set if the SPT DAT n is wri[...]

SPI S3C2440A RISC MICROPROCESSOR 22-8 The SPIMISO (MISO) and SPIMOSI ( MOSI) data pins ar e used for transm itting and r eceiving s erial data. W hen SPI is conf igured as a m aster , SPIMISO (MISO ) is the m aster data input line, SPIMOSI (MOSI) is the m aster data output line, and SPICLK (SCK) is the clock output line. W hen SPI becom es a slave,[...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-1 23 CA MERA INTERFA CE OVERVIEW This chapter will explain the specif ication and def ines the c am era inter f ac e. CAMIF (C A Mera In terFace ) wi thin the S3C2440A consists of 7 parts – pattern mux, capturin g unit, p review scaler, codec scaler, preview DMA, codec DMA , and SFR . T he CAMIF s[...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-2 BLOCK DIA GRAM YCbCr 4:2:2 T_patternMux CatchCam YCbCr 4:2:X Preview Scaler & RGB Formatter Codec Scaler Prev iew D MA ITU -R BT 601/656 Codec DM A CamI f SFR A HB bus Figure 23-1 CAMIF Ov erview[...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-3 TIM ING DIA GRAM jht}zuj jht}zuj jht}zuj jht}zuj  j  j  j  j  j jhtoylm jhtoylm jhtoylm jhtoylm jhtoylmG jhtoylmG jhtoylmG jhtoylmG OXoP OXoP OXoP OXoP jhtwjsr jhtwjsr jhtwjsr jhtwjsr jhtkh{h jhtkh{h jhtkh {h jhtkh{h ^a W ^a W ^a W ^a [...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-4 Table 23- 2 Video T iming Reference Cod es of IT U-656 Format Data bit number First word Second word T hird word Fourth word 9 (MSB) 1 0 0 1 8 1 0 0 F 7 1 0 0 V 6 1 0 0 H 5 1 0 0 P3 4 1 0 0 P2 3 1 0 0 P1 2 1 0 0 P0 1 (N OTE) 1 0 0 0 0 1 0 0 0 For com patibility with existing 8-bit interfac es, the[...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-5 CA MERA INTERFA CE OPERA TION TWO D M A PA THS CAMIF has 2 DMA paths. P-path (Previe w path) and C-path (Codec path) are separated f rom each other on th e AHB bus. In view of the system bus, both the paths are independent. The P- path stores the RGB im age data into mem or y for PIP. The C-path s[...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-6 m al-func tioning CAMCLKOUT Divide Counter 1/1 ~ 1/16 UPLL Extern al Camera Processor CAMPCLK S3C2440A CA M IF USB PLL 96 MHz f USB /d f USB MPL L Variable Freq. Divide Counter f m pll /d f mpl l HCLK External MCLK Normally use Schmit -triggered Level-shift er Figure 23-5 CA M IF Clock Generation [...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-7 ME MOR Y S TORI NG METH OD The little-endian m ethod in c odec path is us ed to store in the f ram e m emor y . T he pixels are stored fr om LSB to MSB side. AHB bus carries 32-bit word data. So, CAMIF mak es eac h of the Y-Cb-Cr words in little-endian style. For preview path, two diff erent f orm[...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-8 TIM ING DIA G RA M FOR REGIST ER SETT ING The f irst regis ter setting f or fr ame c apture com m and can occ ur anyw here in the fr ame per iod. But, it is recom m ended that you set it at the CAMVSY NC “ L” state f irst and the CAMVSYNC inform ation can be read f rom the status SFR ( Please [...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-9 TIM ING DIA GRAM FOR LA ST IRQ IRQ except Las tIRQ is generated bef ore im age capturing. Las t IRQ which m eans captur e-end can be set by following tim ing diagram. Las tIRQEn is auto-c leared and ,as m entioned, SFR setting in ISR is for nex t fram e com m and. So, for adequate las t IRQ, you s[...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-10 CA MERA INTERFA CE SPECIA L REGISTERS SOURCE FORMAT REGISTER Register Address R/W Descrip tion Reset Value CISRCFMT 0x4F 000000 RW Input Sour ce Form at Register 0 CISRCFM T Bit Description Init ial State ITU601_656n [31] 0 = ITU-R BT .656 YCbCr 8-bit m ode enable 1 = ITU-R BT .601 YCbCr 8-bit m [...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-11 WINDOW OPTION REGIS T ER Register Address R/W Descrip tion Reset Value CIW DOFST 0x4F000004 RW W indow Offs et Register 0 CIWDOFST Bit Description Init ial State W inOfsEn [31] 0 = No off set 1 = W indow offset enable 0 ClrOvCoFiY [30] 0 = Norm al 1 = Clear the overf low indication flag of input [...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-12 GLOBA L CONT ROL REGISTER Register Address R/W Descrip tion Reset Value CIGCT RL 0x4F000008 RW G lobal Control Register 0 CIGCT RL Bit Descript ion Initial State SwRst [31] Camera Interf ace Software Reset 0 CamR st [30] Ex ternal Cam era Proces sor Reset or Power Down 0 Reserved [29] T his bit i[...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-13 Y3 ST A RT ADDRESS REGISTER Register Address R/W Descrip tion Reset Value CICOYSA3 0x4F000020 RW Y 3 rd fram e star t address f or codec DMA 0 CICOYSA3 Bit Description Initial State CICOYSA3 [31:0] Y 3 rd frame s tart address for c odec DMA 0 Y4 ST A RT ADDRESS REGISTER Register Address R/W Descr[...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-14 CB4 START A DDRESS REG ISTER Register Address R/W Descrip tion Reset Value CICOCBSA4 0x4F000034 RW Cb 4 th fram e start addres s for c odec DMA 0 CICOCBSA 4 Bit Description Initial State CICOCBSA4 [31:0] Cb 4 th fram e start addres s for codec DMA 0 CR1 START A DDRESS REG ISTER Register Address R[...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-15 CODEC TARGET FORMAT REGISTER Register Address R/W Description Reset Value CICOTR GFMT 0x 4F000048 RW Target im age for mat of codec DMA 0 CICOTRG FM T Bit Descript ion Initial State In422_Co [31] 0 = YCbCr 4:2:0 codec s caler input im age f orm at. In this cas e, horizontal line decimation is per[...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-16 CODEC DMA CONTROL REGISTER Register Address R/W Description Reset Value CICOCTRL 0x4F00004C RW Codec DMA control related 0 CICOCTRL Bit Description In itial State Yburst1_Co [23:19] Main burst length for codec Y fram es 0 Yburst2_Co [18:14] Remained burst length f or codec Y fram es 0 Cburst1_Co [...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-17 REGISTER SET T ING GUIDE FO R CODEC SCALER A ND PREVIEW SCA LER SRC_Width and DST_Width satisf y the w ord boundary constraints such that the num ber of hor izont al pixel can be represented to k n where n = 1,2,3, … and k = 1 / 2 / 8 for 24bppRGB / 16bppRGB / YCbCr420 im age, res pectively . T[...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-18 If ( SRC_Height >= 64 × DST _Height ) { Ex it(-1); /* O ut Of V ertic al Scale Range */ } else if ( SRC_Height >= 32 × DST_Height) { PreV erRatio_xx = 32; V_Shift = 5; } else if ( SRC_Height >= 16 × DST_Height) { PreV erRatio_xx = 16; V_Shift = 4; } else if ( SRC_Height >= 8 × DST[...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-19 CODEC MAIN-SCA LER CONTROL REGIST ER Register Address R/W Descript ion Reset Value CICOSCCTRL 0x 4F000058 RW Codec m ain-scaler control 0 CICOSCCTRL Bit Descrip tion Initial State ScalerBypass_Co [31] Codec scaler by pass f or upper 2048 x 2048 s ize (In this case, ImgCptEn_CoSC and Im gCptEn_PrS[...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-20 CODEC STATUS REGISTER Register Address R/W Description Reset Value CICOSTAT US 0x4F000064 R Codec path s tatus 0 CICOSTATUS Bit Descrip tion Init ial Stat e OvFiY_Co [31] Overflow state of codec sour ce FIFO Y 0 OvFiCb_Co [30] O verflow state of c odec sourc e FIFO Cb 0 OvFiCr_Co [29] Overflow st[...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-21 RGB3 START ADDRESS REGISTER Register Address R/W Description Reset Value CIPRCLRSA3 0x4F000074 RW RG B 3 rd f ram e start addr ess f or preview DMA 0 CIPRCLRSA 3 Bit Descripti on Initial State CIPRCLRSA3 [31:0] RGB 3 rd fram e start addr ess f or preview DMA 0 RGB4 START ADDRESS REGISTER Register[...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-22 PREVIEW DM A CO NTRO L REGIST ER Register Address R/W Descrip tion Reset Value CIPRCTRL 0x4F000080 RW Preview DMA control related 0 CIPRCTRL Bit Descriptio n Init ial State RGBburst1_Pr [23:19] Main burst length for pr eview RGB fram es 0 RGBburst2_Pr [18:14] Remained burst length for preview RGB[...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-23 PREVIEW PRE-SCALER CONTROL REG ISTER 2 Register Address R/W Descript ion Reset Value CIPRSCPREDST 0x4F000088 RW Preview pre-sc aler destination f orm at 0 CIPRSCPREDST Bit Description In itial State PreDstW idth_Pr [27:16] Destination width for preview pre- scaler 0 PreDstHeight_Pr [11:0] Destina[...]

S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-24 PREVIEW ST A T US REGIST ER Register Address R/W Descript ion Reset Valu e CIPRSTAT US 0x 4F000098 R Preview path status 0 CIPRSTATUS Bit Description Initial Stat e OvFiCb_Pr [31] Overf low state of preview sour ce FIFO Cb 0 OvFiCr_Pr [30] Over flow state of preview sour ce FIFO Cr 0 Fram eCnt_Pr[...]

S3C2440A RISC MICROPROCESSOR AC97 CONTROLLER 24-1 24 A C97 CONTROLLER OVERVIEW The AC97 Controller Unit of the S3C2440A s upports AC97 revis ion 2.0 features . AC97 Controller com m unicates with AC97 Codec using an audio controller link (AC- link). Contr oller sends the s tereo PCM data to Codec . T he external digital-to- analog converter ( DAC) [...]

AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR 24-2 A C97 CONTROLLE R OP E RA TION BLOCK DIA GRAM Figure 24-1 shows the f unctional block diagram of the S3C2440A AC97 Controller. T he AC97 signals for m the AC- link, which is a point-to-point s y nc hronous s erial interconnec t that supports f ull-duplex data tr ansfer s. All digital audio stream s [...]

S3C2440A RISC MICROPROCESSOR AC97 CONTROLLER 24-3 IN TERN A L DA TA PA TH Figure 24-2 shows the internal data path of the S3C2440A AC97 Controller . It has ster eo Pulse Code Modulated (PCM) In, Stereo PCM O ut and m ono Mic-in buf fers, which consis t of 16-bit, 16 entries buf fer. Also it has a 20- bit I/O shif t register via AC-link. j?[...]

AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR 24-4 OPERA TION FLOW CHA RT Syst em r eset o r Co ld r eset Set GPIO an d Release INTM SK/SU BINTM SK bits Enable Codec Ready interrupt Codec Re ady inter rupt ? Ti me out conditio n ? Disable Codec Ready in terrupt DM A operat ion or PIO (Interrupt or Polling) o peration Yes No Controller of f No Figure[...]

S3C2440A RISC MICROPROCESSOR AC97 CONTROLLER 24-5 A C-LINK DIGITA L INTERFAC E PROTOCOL Each AC97 Codec inc orpor ates a f ive-pin digital ser ial interf ac e that link s it to the S3C2440A AC97 Contr oller. T he AC-link is a full- duplex, fix ed-clock , PCM digital st ream . It em ploy s a tim e divis ion m ultiplexing (TDM) sc hem e to handle con[...]

AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR 24-6 A C-LINK INPUT FRA M E (SDATA _IN) S D AT A_ O U T BIT_CLK SYNC AC '97 sam ples SYNC assertion her e AC '97 Controller samples fir s t SDATA_IN bit of fr am e here END of previous A udio Frame Codec Ready Slot(1) Slot(2) Slot(12) "0" "0" "0" 19 0 Tag Phase Dat[...]

S3C2440A RISC MICROPROCESSOR AC97 CONTROLLER 24-7 Waking u p the AC-link - Wake Up T riggered by the AC97 Controller AC-link protocol is pr ovided for a c old AC97 reset and a warm AC97 reset. T he cur rent power-down state ultima tely dictates which AC97 r eset is used. Registers m ust stay in the same s tate during all power-down modes unless a c[...]

AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR 24-8 A C97 CONTROLLER SPECIA L REGISTERS A C97 GLOBAL CONTROL REGISTER (A C_GLBCTRL) Register Address R/W Descrip tion Reset Valu e AC_GLBCTRL 0x5B000000 R/W AC97 G lobal Control Register 0x000000 A C_G LBCTRL Bit Description Initial State Reserved [31:23] 0x 00 Codec Ready Interrupt Enable [22] 0 : Disa[...]

S3C2440A RISC MICROPROCESSOR AC97 CONTROLLER 24-9 A C97 GLOBA L STATUS REGIS TER (A C_GLBSTAT) Register Address R/W Description Reset Value AC_GLBST AT 0x5B000004 R AC97 Global Status Register 0x00000000 A C_G LBSTAT Bit Descrip tion Initial State Reserved [31:23] 0x 00 Codec Ready Interrupt [22] 0 : Not requested 1 : Requested 0 PCM Out Channel Un[...]

AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR 24-10 A C97 CODEC ST A T US REGIST ER (A C_CODEC_ST A T ) Register Address R/W Description Reset Value AC_CODEC_ST AT 0x5B00000C R AC97 Codec Status Register 0x00000000 A C_CO DEC_STAT Bit Descrip tion Initial Stat e Reserved [31:23] 0x 00 Address [22:16] CODEC Status Address 0x00 Data [15:0] CODEC Statu[...]

S3C2440A RISC MICROPROCESSOR AC97 CONTROLLER 24-11 A C97 M IC IN CHANNEL FIFO A DDRESS REGIST ER (AC_MICA DDR) Register Address R/W Description Reset Valu e AC_MICADDR 0x5B000014 R AC97 Mic In Channel FIFO Address Regis ter 0x00000000 A C_M ICA DDR Bit Description Initial State Reserved [31:20] 0000 Read Address [19:16] MIC in channel F IFO read ad[...]

AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR 24-12 NOTES[...]

S3C2440A RISC MICROPROCESSOR BUS PRIORITIES 25-1 25 BUS PRIORITIES OVERVIEW The bus arbitration logic determ ines the priorities of bus m asters . It supports a c om bination of rotation priority mode and f ixed prior ity m ode. BUS PRIORITY MAP The S3C2440A holds 13 bus masters . They include DRAM refr esh controller, LCD_DMA, CAMIF DMA, DMA0, DMA[...]

BUS PRIORITIES S3C2440A RISC MICROPROCESSOR 25-2 NOTES[...]

S3C2440A RISC MICROPROCESSOR MECHANICA L DATA 26-1 26 MECHA NICA L DA TA PA CKAGE DIMENSIONS 14.00 14.0 0 0.35 + 0.05 1.22 289-FBG A-1414 0.45 ±0.05 C 0.12 MAX 0.10 C A B 0.15 TOLER ANCE ±0.10 x 2 0.15 x 2 C C SAMSU NG Figure 26-1 289- FBGA-1414 Package Dimension 1 (T op View )[...]

MECHANICAL DA TA S3C2440A RISC MICROPROCESSOR 26-2 A1 INDEX MARK 0.80 x 16 = 12.8 0 ± 0.05 14.00 0.80 0.80 A B C D E F G H J K L M N P R T U 8 9 10 11 12 13 14 15 16 17 5 6 71 2 3 4 14.00 0.15 0.08 M M C C A B 289 - 0.45 ± 0.05 TOLERANCE ± 0.10 Figure 26-2 289- FBGA-1414 Package Dimension 2 (Bott om View) The rec om mended land open s ize is 0.3[...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-1 27 ELECTRICA L DA TA A BSO LUTE MA XI MUM RA TING S Table 27-1 Absolute M aximum Rating Paramete r Symbol Rating Unit V DDi 1.2V V DD 1.8 V DDOP 3.3V V DD 4.8 V DDMOP 1.8V/2.5V/3.0V/3.3V V DD 4.8 V DDRTC 1.8V/2.5V/3.0V/3.3V V DD 4.5 DC Supply Voltage V DDADC 3.3V V DD 4.8 3.3V Input buff er 4.8 DC [...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-2 RECOMMENDED OPERATING CONDITIONS Table 27-2 Recommende d Operating Conditions Rating Parameter Symbol T yp. Min Max Unit DC Supply Voltage f or Alive Bloc k V DD alive 300MHz : 1.2V V DD 400MHz: 1.3V V DD 1.15 1.15 1.25 1.35 DC Supply Voltage f or Internal V DDi (1) V DDiarm (1) V DDMPLL V DDUPLL 3[...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-3 D.C. ELECTRICA L CHARA CTE RISTICS Table 27-3 and 27- 4 defines the DC elec trical char acteristic s for the standard LVCMOS I/O buff ers. Table 27- 3 Normal I/O PAD DC Electrical Characteristics Normal I/O PAD DC Electrical Characteristics for M emory (V DDMOP = 2.5V ± ± ± ± 0.2V, T A = -40 to[...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-4 Normal I/O PAD DC Electrical Characteristics for M emory (V DDMOP =3.0V ± ± ± ± 0.3V, 3.3V ± ± ± ± 0.3V, T A =-40 to 85 ° ° ° ° C) Symbol P arameters Condition M in Typ. M ax Unit High level input voltage V IH LVCMOS interface 2.0 V Low level input voltage V IL LVCMOS interface 0.8 V VT[...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-5 Normal I/O PAD DC Electrical Characteristics for I/O (V DDOP = 3.3V ± ± ± ± 0.3V, T A = -40 to 85 ° ° ° ° C) Symbol P arameters Condition M in Typ. M ax Unit High level input voltage V IH LVCMOS interface 2.0 V Low level input voltage V IL LVCMOS interface 0.8 V VT Switching threshold 0.5V [...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-6 Table 27- 4 USB DC Electrical Characteristics Symbol P arameter Condition M in M ax Unit V IH High level input voltage 2.5 V V IL Low level input voltage 0.8 V I IH High level input current Vin = 3.3V -10 10 µA I IL Low level input current Vin = 0.0V - 10 10 µA V OH Static Output High 15K to GND [...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-7 400M h z P o w er c o n su m p t io n 88m W 87m W 139m W 68m W 0 50 100 150 200 250 DVS( o) DV S( x ) Ite m Power[mW] Co r e P ow e r 104% Up Tota l P ow e r 46% Up Cor e P o w e r IO P o w e r 155mW 227mW Usi n g D VS w i thout D V S NOT E: (Condition) Current m eas ure condition: Play Battlife.wm[...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-8[...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-9 A .C. ELE CTRICAL CHA RACTERISTICS 1/2 V DD 1/2 V DD t XTA L CY C NOTE: Clock input is from the X TI pll pin. Figure 27-2 XT Ipll Clock T iming Diagram t EXTHI GH V IH 1/2 V DD V IL V IL V IH V IH 1/2 V DD t EX TLOW t EX TCYC NOTE: Clock input is from the EX TCLK pin. Figure 27-3 E X T CLK Clock In[...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-10 HCLK (internal) SCLK CLKOUT (HCLK) t HC2CK t HC2SCLK Figure 27-5 HCLK/CL KOUT/SCLK in case when EXTCLK is used EXT CLK t RESW nRESET Figure 27-6 Manual Reset Input T iming Diagram[...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-11 nRESET XT Ipll or EXT CLK VCO output MCU o perates by XT Ipll or EXT CLK clcok. Clock Disable tPLL FCLK is new frequency . Pow er PLL can operate aft er OM[3:2] is la tched. PLL is configur ed by S/W first time. VCO is ad apted to new clock fr equency. FCLK ... ... ... tRST2RUN Figure 27-7 Power-O[...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-12 XTIpl l VCO Output Clock Disable FCLK Severa l slow clocks (X TIpll or EXT CLK ) Pow er_OFF mode is in itiated. t OSC 2 EXT CLK Figure 27-8 Sleep Mode Return O scillation Setting Timing Diagram[...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-13 HCLK nGCS x tRAD nOE DATA ADDR nBEx tRCD tROD tROD tRCD Tacc tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH '1' Figure 27-9 ROM /SRAM Burst READ Timing Diagram (I) (Tacs=0, T cos=0, T acc=2, T och=0, T cah=0, PM C=0[...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-14 HCLK nGCSx tRAD nOE DATA ADDR nBEx tRCD tROD tROD tRCD tRBED tRB ED Tacc tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH Figure 27-10 ROM /SRAM Burst READ Timing Diagram (II) (Tacs=0, T cos=0, T acc=2, T och=0, T cah=0, PM C=0[...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-15 HCLK nGS nOE ADDR tXnBRQ S XnBREQ tXnBRQ H XnBACK 'HZ' 'HZ' 'HZ' tXnBACKD tXnBAC KD tHZD tHZD tHZD Figure 27-11 Extern al Bus Request in ROM /SRA M Cycle (Tacs=0, T cos=0, T acc=8, T och=0, T cah=0, PM C=0, ST=0)[...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-16 HCLK nGCSx tRAD Tacs nOE Tcos DATA ADDR nW BEx '1' Toc h Tc ah tRCD tROD tRDS tRDH tROD tRCD tRAD Tac c Figure 27-12 ROM /SRAM REA D Timing Diagram (I) (Tacs=2,T cos=2, T acc=4, T och=2, T cah=2, PM C=0, ST=0)[...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-17 HCLK nGCSx tRAD Tac s nOE Tcos DATA ADDR nBEx Toc h Tc ah tRCD tROD tRDS tRDH tROD tRCD tRAD tRBED tRBED Tac c Figure 27-13 ROM /SRAM REA D Timing Diag ram (II) (Tacs=2, T cos=2, T acc=4, T och=2, T cah=2cycle, PMC=0, ST =1)[...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-18 HCLK nGCSx tRAD Tacs nWE Tcos DATA ADDR nWBEx Toch Tcah tRCD tRWD tRDD tRWD tRCD tRAD Tcos Toch tRWBED tRWBED Tacc tRDD Figure 27-14 ROM /SRAM WRIT E Timin g Diagram (I) (Tacs=2,T cos=2,T acc=4,T och=2, T cah=2, PM C=0, ST=0[...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-19 HCLK nGCSx tRAD Tac s nW E Tco s DATA ADDR nBEx Toc h Tc ah tRCD tRW D tRDD tRW D tRCD tRAD tRBED tRBED Tac c tRDD Figure 27-15 ROM /SRAM WRIT E Timin g Diagram (II) (Tacs=2, T cos=2, T acc=4, T och=2, T cah=2, PM C=0, ST=1)[...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-20 HCLK nGCSx nOE Tacc = 6c yc le nW ait DATA ADDR Tac s Tac s delayed tRC NOTE: The status of nW ait is checked at (Tacc-1) cy cle. sampling nW ait Figure 27-16 Extern al nWAIT REA D T iming Diagram (Tacs=0, T cos=0, T acc=6, T och=0, T cah=0, PM C=0, ST=0) HCLK nGCSx nW E DATA ADDR tRDD tRDD Tacc &[...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-21 HCLK nGCSx tRAD Tac s nOE Tc os DAT A ADDR tRCD tROD tRDS tRDH tRAD Tac c Figure 27-18 M asked- ROM Single READ Timing Diagram ( Tacs=2, T cos=2, T acc=8, PMC=01/10/11) HCLK nGCSx tRAD nOE DATA ADDR tRCD tROD tRDS tRDH tRAD Tac c Tpac Tpac T pac T pac tRAD tRAD tR AD tRAD tRDS tRDH tRDS tRDH tRDS [...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-22 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/ BA nBEx tSRD tSD S tSDH SCKE A10/AP nGCSx tSCS D nWE tSAD tSCD tSWD '1' Trcd tSBED Tcl Figure 27-20 SDRAM Single Bu rst REA D T iming Diag ram (Trp =2, Trcd=2, T cl=2, DW=16bit )[...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-23 SCLK nSRAS nSCAS ADDR/BA nBEx tX nBR QH tXnBRQS SCKE A10/AP nGCSx nW E '1' XnBREQ Xn BA CK EXTCLK tXnBACKD tXnBAC KD 'HZ' 'HZ' 'HZ' 'HZ' 'HZ' 'HZ' 'HZ' 'HZ' 'HZ' tHZD tHZD tHZD tHZD tHZD tHZD tHZD t[...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-24 SCLK nSRAS tSAD nSCAS DATA ADDR/BA nBEx tSRD SCKE A10/AP nGCSx tSCS D nW E tSAD tSCD tSW D '1' tSAD tSCSD tSRD 'HZ' '1' tSW D Figure 27-22 SDRAM M RS Timin g Diagram[...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-25 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDS tSDH SCKE A10/AP nGCSx tSCSD nW E tSAD tSCD tSW D '1' tSAD tSAD Trcd tSCSD tSRD tSCS D tSAD tSAD tSBED Tc l Figure 27-23 SDRAM Single READ Timing Diagram ( I) (T rp=2, T rcd=2, Tcl=2)[...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-26 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDS tSDH SCKE A10/AP nGCSx tSCSD nW E tSAD tSCD tSW D '1' tSAD tSAD Trc d tSCSD tSRD tSCSD tSAD tSAD tSBED Tcl Figure 27-24 SDRAM Single READ Timing Diagram ( II) (T rp=2, Trcd =2, Tcl=3)[...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-27 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD SCKE A10/AP nGCS x tSCSD nW E tSAD tSCD tSW D '1' tSAD tSCSD tSRD '1' '1' 'HZ' Trc NOTE: Before ex ecuting an auto/self refresh c o mmand, all the banks must be in idle state. Figure 27-25 SDRAM Auto Refresh T[...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-28 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDS tSDH SCKE A10/AP nGCS x tSCSD nWE tSAD tSCD tSWD '1' Trcd tSBED Tcl Tcl Tcl Figure 27-26 SDRAM Page Hit- Miss READ Timing Diagram ( Trp=2, T rcd=2, T cl=2)[...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-29 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD SCKE A10/AP nGCS x tSCSD nW E tSAD tSCD tSW D tSAD tSCSD tSRD '1' '1' 'HZ' Trc tCKED 'HZ ' '1' '1' '1' '1' '1' tCKED NOTE: Before ex ecuting an auto/self refre[...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-30 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDD tSDD SCKE A10/AP nGCSx tSCSD nW E tSAD tSCD tSW D '1' tSAD tSAD Trc d tSCSD tSRD tSCSD tSAD tSAD tSBED tSW D Figure 27-28. SDRAM Single W rite Timin g Diagram (T rp=2, T rcd=2)[...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-31 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDD tSDD SCKE A10/A P nGCSx tSCS D nWE tSAD tSCD tSWD '1' Trcd tSBED Figure 27-29. SDRAM Page Hit- Miss W rite Timin g Diagram (T rp=2, T rcd=2, Tcl=2)[...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-32 XSC L K tXRS tXRS tCAD L tCADH tXAD Xn XD RE Q XnXDACK Read Wr it e Min . 3 SC LK Figure 27-30. Extern al DMA Timing Diagram ( Handshake, Sing le transfer) VSYNC HSYNC VDEN Tf2hs et up Tf 2hhold Tvsp w Tvbpd Tvfpd HSYNC VCLK VD VDEN LEND Tl2c setu p Tvcl kh Tvcl k Tvclkl Tvdh ol d Tvds etup Tve2ho[...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-33 IISSCLK tLRCK IISLRCK (out) tSDO IISLRCK (out) tSDIH tSDIS IISSDI (in) Figure 27-32. IIS Int erface Timin g Diagram tST OPH tSTAR TS tSDA S tSDAH tBUF tS CLHI GH tS CLLOW fSCL IICSC L IICSD A Figure 27-33. IIC Int erface Timin g Diagram[...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-34 SDCLK tSDCD SDCM D (out) tSDCH tSDCS tSDDD SDCM D (in) tSDDH tSDDS SDDATA[ 3:0] (in) SDDATA[ 3:0] (out) Figure 27-34. SD/M M C Interf ace Timing Diag ram SPICLK tSPIM OD tSPISIH tSPIS IS tSPISOD tSPIM IH tSPIM IS SPIM OSI (MO ) SPIM OSI (SI) SPIM ISO (SO) SPIM ISO (M I) Figure 27-35. SPI Int erfac[...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-35 TA CL S TWR PH 0 TWR PH 1 COMMAND TW RPH0 T W RPH 1 ADDR ESS HCLK ALE nFW E DAT A[7:0] DAT A[7:0] HCLK CLE nFW E tCL ED tCL ED tWED tW ED tWDS tW DH tALED tW ED tWDS tALED tWED tWDH TACLS Figure 27-36. NAND Flash A ddress/Command T iming Diagram HCLK nFW E TW RPH0 TW RPH1 DATA[7:0] HCLK nFRE TW RP[...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-36 Table 27- 7 Clock Timin g Constant s (V DDi, V DDalive, V DDiarm = 1.2 V ± 0.1 V, T A = -40 to 85 ° C, V DDMOP = 3.3V ± 0.3V) Parame ter Symbol Min T yp M ax Unit Crystal clock input f requency f XT AL 12 – 20 MHz Crystal clock input c y c le time t XTA LC Y C 50 – 83.3 ns External cloc k i[...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-37 Table 27- 8 ROM /SRA M Bus T iming Const ants (V DDi, V DDalive, V DDiarm = 1.2 V ± 0.1 V, T A = -40 to 85 ° C, V DDMOP = 3.3V ± 0.3V / 3.0V ± 0.3V / 2.5V ± 0.2V / 1.8V ± 0.1V) Parameter Symbo l Mi n (V DDMOP = 3.3V/3.0V/2.5V/1.8V) Ty p M ax (V DDMOP = 3.3V/3.0V/2.5V/1.8V) Unit ROM/SRAM Addr[...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-38 Table 27- 10 External Bus Request Timing Constant s (V DD = 1.2 V ± 0.1 V, T A = -40 to 85 ° C, V EXT = 3.3V ± 0.3V) Parame ter Sy mbol Min Typ. M ax Unit External Bus Reques t Setup Tim e t XnB R QS 2 – 4 ns External Bus Reques t Hold Tim e t Xn B RQ H 0 – 1 ns External Bus Ac k Delay t Xn[...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-39 Table 27-12 TFT LCD Controller M odule Signal Timing Constants (V DD = 1.2 V ± 0.05 V, T A = -40 to 85 ° C, V EXT = 3.3V ± 0.3V) Parame ter Symbol M in T yp Max Units Vertical Sync Pulse W idth Tvspw VSPW + 1 – – Phclk (not e1) Vertical Bac k Por ch Delay T vbpd VBPD+1 – – Phclk Vertica[...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-40 Table 27-14 IIC BUS Controller Module Signal Timing (V DD = 1.2 V ± 0.05 V, T A = -40 to 85 ° C, V EXT = 3.3V ± 0.3V) Parame ter Sy mbol Min Typ. M ax Unit SCL Clock Frequency f SCL – – std. 100 fast 400 KHz SCL High Level Pulse W idth t SCLHIGH std. 4.0 fast 0.6 – – µ s SCL Low Level [...]

S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-41 Table 27- 16 SPI Interface T ransmit/Receive T iming Co nstants (V DD = 1.2 V ± 0.1 V, T A = -40 to 85 ° C, V EXT = 3.3V ± 0.3V) Parame ter Sy mbol Min Typ. Max Unit SPI MOSI Master O utput Delay T im e t SPIMOD 0 – 1 ns SPI MOSI Slave Input Setup T ime t SPISIS 0 – 1 ns SPI MOSI Slave Inpu[...]

ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-42 Table 27- 18 USB Full Speed Outp ut Buff er Electrical Characteristics (V DD = 1.2 V ± 0.05 V, T A = -40 to 85 ° C, V EXT = 3.3V ± 0.3V) Parame ter Sy mbol Condition Min Max Unit Driver Characterist ics Trans ition Tim e Rise Tim e Fall T im e TR TF CL = 50pF CL = 50pF 4.0 4.0 20 20 ns Rise/Fal[...]