SMSC COM20020 manual

COM20020 COM20020 ULANC Universal Local Area Network Controller with 2K x 8 On-Board RAM FEATURES • 24-Pin Embedded Network Controller/ Transceiver/RAM • Ideal for Industrial/Factory Automation and Automotive Applications • Deterministic, 2.5 Mbps, Token Passing ARCNET Protocol • Minimal Microcontroller and Media Interface Logic Required ?[...]

2 TABLE OF CONTENTS FEATURES ........................................................................................................................................ 1 GENERAL DESCRIPTION ................................................................................................................. 1 PIN CONFIGURATION ............................[...]

3 controller optimized for use in industrial and automotive applications. Using an ARCNET protocol engine is the ideal solution for factory automation applications because it provides a token-passing protocol, a highly reliable and proven networking scheme, and a data rate of up to 2.5 Mbps when using the COM20020. A token-passing protocol provides[...]

4 DESCRIPTION OF PIN FUNCTIONS DIP PIN NO. PLCC PIN NO. NAME SYMBOL DESCRIPTION MICROCONTROLLER INTERFACE 1-3 1-3 Address 0-2 A0/nMUX, A1,A2/ALE Input. On a non-multiplexed bus, these signals are directly connected to the low bits of the host address bus. On a multiplexed address/data bus, A0/nMUX is tied low, A1 is left open, and A2 is tied to the[...]

5 DIP PIN NO. PLCC PIN NO. NAME SYMBOL DESCRIPTION 19 23 nReset in nRESET IN Input. This active low signal issued by the microcontroller executes a hardware reset. It is used to activate the internal reset circuitry within the COM20020. 20 24 nInterrupt nINTR Output. This active low signal is generated by the COM20020 when an enabled interrupt cond[...]

6 DIP PIN NO. PLCC PIN NO. NAME SYMBOL DESCRIPTION instead, it must be connected to XTAL1 with a 390 Ω pull-up resistor, and XTAL2 should be left floating. 24 15,28 Power Supply V DD +5 Volt Power Supply pin. 12 7,14,22 Ground V SS Ground pin.[...]

7 Invitation to Transmit to this ID? Y N Free Buffer Enquiry to this ID? SOH? Y N Y N RI? Write SID to Buffer DID =0? DID =ID? Write Buffer with Packet CRC OK? LENGTH OK? DID =0? DID =ID? SEND ACK N Y N Y N Y N Broadcast Enabled? N Y N No Activity for 82 uS? Y N Set NID=ID Start Timer: T=(255-ID) Activity On Line? Y N T=0? Set RI RI? Transmit NAK T[...]

8 PROTOCOL DESCRIPTION NETWORK PROTOCOL Communication on the network is based on a token passing protocol. Establishment of the network configuration and management of the network protocol are handled entirely by the COM20020's internal microcoded sequencer. A processor or intelligent peripheral transmits data by simply loading a data packet a[...]

9 When any COM20020 senses an idle line for greater than 82 µ S, which occurs only when the token is lost, each COM20020 starts an internal timeout equal to 146 µ s times the quantity 255 minus its own ID. The COM20020 starts network reconfiguration by sending an invitation to transmit first to itself and then to all other nodes by decrementing t[...]

10 ALERT BURST EOT DID DID ALERT BURST ENQ DID DID Idle Time The Idle Time is associated with a NETWORK RECONFIGURATION. Figure 1 illustrates that during a NETWORK RECONFIGURATION one node will continually transmit INVITATIONS TO TRANSMIT until it encounters an active node. All other nodes on the network must distinguish between this operation and [...]

11 ALERT BURST ACK ALERT BURST NAK Data Packets A Data Packet consists of the actual data being sent to another node. It is sent by the following sequence: • An ALERT BURST • An SOH (Start Of Header--ASCII code 01H) • An SID (Source ID) character • Two (repeated) DID (Destination ID) characters • A single COUNT character which is the 2&ap[...]

12 SYSTEM DESCRIPTION MICROCONTROLLER INTERFACE The top halves of Figures 2 and 3 illustrate typical COM20020 interfaces to the microcontrollers. The interfaces consist of an 8- bit data bus, an address bus, and a control bus. In order to support a wide range of microcontrollers without requiring glue logic and without increasing the number of pins[...]

13 AD0-AD7 nINT1 RESET nRD nWR A15 AD0-AD2, D3-D7 nCS nRESET IN nRD/nDS nWR/DIR nINTR A2/BALE ALE A0/nMUX XTAL1 XTAL2 X T A L 1 X T A L 2 GND RXIN nPULSE1 nPULSE2 nTXEN 27 pF 27 pF 8051 FIGURE 2 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE RXIN nPULSE1 nPULSE2 TXEN GND +5V 100 Ohm BACKPLANE CONFIGURATION FIGURE A COM20020 Differenti[...]

14 RXIN nPULSE1 nPULSE2 nTXEN GND Traditional Hybrid Configuration RXIN nPULSE1 nPULSE2 17, 19, 4, 13, 14 5.6K 1/2W 5.6K 1/2W 0.01 uF 1KV 12 11 -5V 0.47 uF 10 uF + 3 0.47 uF + +5V uF 10 6 FIGURE C D0-D7 nIRQ1 nRES nIOS R/nW A7 D0-D7 nCS nRESET IN nRD/nDS nWR/nDIR nINTR A0/nMUX A0 XTAL1 XTAL2 X T A L 1 X T A L 2 A1 A1 A2/BALE A2 27 pF 27 pF RXIN nPU[...]

15 TRANSMISSION MEDIA INTERFACE The bottom halves of Figures 2 and 3 illustrate the COM20020 interface to the transmission media used to connect the node to the network. Table 1 lists different types of cable which are suitable for ARCNET applications. 1 The user may interface to the cable of choice in one of three ways: Traditional Hybrid Interfac[...]

16 FIGURE 5 - DIPULSE WAVEFORM FOR DATA OF 1-1-0 20MHZ CLOCK (FOR REF. ONLY) nPULSE1 nPULSE2 DIPULSE RXIN 1 0 100ns 100ns 200ns 400ns 1 COM20020 COM20020 COM20020 +VCC RBIAS +VCC +VCC RBIAS RBIAS RT RT FIGURE 4 - COM20020 NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS 75176B or Equiv.[...]

17 In typical applications, the serial backplane is terminated at both ends and a bias is provided by the external pull-up resistor. The RXIN signal is directly connected to the cable via an internal Schmitt trigger. A negative pulse on this input indicates a logic "1". Lack of pulse indicates a logic "0". For typical single- en[...]

18 MICRO- SEQUENCER AND WORKING REGISTERS STATUS/ COMMAND REGISTER RESET LOGIC RECONFIGURATION TIMER NODE ID LOGIC OSCILLATOR TX/RX LOGIC ADDITIONAL REGISTERS ADDRESS DECODING CIRCUITRY 2K x 8 AD0-AD2, BUS ARBITRATION CIRCUITRY nPULSE1 nPULSE2 nTXEN XTAL1 XTAL2 nINTR nRESET IN RAM A 0 / n M U X A 1 A 2 / B A L E nRD/nDS nWR/DIR nCS D3-D7 RXIN FIGUR[...]

19 Table 1 - Typical Media CABLE TYPE NOMINAL IMPEDANCE ATTENUATION PER 1000 FT. AT 5MHZ RG-62 Belden #86262 93 Ω 5.5dB RG-59/U Belden #89108 75 Ω 7.0dB RG-11/U Belden #89108 75 Ω 5.5dB IBM Type 1* Belden #89688 150 Ω 7.0dB IBM Type 3* Telephone Twisted Pair Belden #1155A 100 Ω 17.9dB COMCODE 26 AWG Twisted Pair Part #105-064-703 105 Ω [...]

20 REGISTER ADDRESS READ MSB LSB STATUS DIAG. STATUS ADDRESS PTR HIGH ADDRESS PTR LOW DATA RESERVED CONFIG- URATION TENTID NODEID SETUP NEXT ID 00 01 02 03 04 05 06 07 RI M Y - RECON RDDATA A7 D7 X RESET TID7 NID7 P1MODE NXTID7 FOUR NAKS NXTID6 X DUPID AUTO- INC A6 D6 X CCHEN TID6 NID6 X RCVACT X A5 D5 X TXEN TID5 NID5 ET3 NXTID5 POR TOKEN X A4 D4 [...]

21 REGISTER ADDRESS WRITE MSB LSB INTERRUPT COMMAND ADDRESS PTR HIGH ADDRESS PTR LOW DATA RESERVED CONFIG- URATION TENTID NODEID SETUP NEXT ID 00 01 02 03 04 05 06 07 RI RDD AT A A7 D7 0 RESET TID7 NID7 0 0 0 D6 AUTO- INC A6 D6 0 CCHEN TID6 NID6 0 D5 0 A5 D5 0 TXEN TID5 NID5 0 0 D4 0 A4 D4 0 ET1 TID4 NID4 0 EXCNAK D3 0 A3 D3 0 ET2 TID3 NID3 0 RECON[...]

22 INTERNAL REGISTERS The COM20020 contains eight internal registers. Tables 2 and 3 illustrate the COM20020 register map. Reserved locations should not be accessed. All undefined bits are read as undefined and must be written as logic "0". Interrupt Mask Register (IMR) The COM20020 is capable of generating an interrupt signal when certai[...]

23 Transmitter is disabled, the Receiver portion of the device is still functional and will provide the user with useful information about the network. The Node ID Register defaults to the value 0000 0000 upon hardware reset only. Next ID Register The Next ID Register is an 8-bit, read-only register, accessed when the sub-address bits are set up ac[...]

24 Configuration Register The Configuration Register is a read/write register which is used to configure the different modes of the COM20020. The Configuration Register defaults to the value 0001 1000 upon hardware reset only. SUBAD0 and SUBAD1 point to selection in Register 7. Setup Register The Setup Register is a read/write 8-bit register access[...]

25 Table 4 - Status Register BIT BIT NAME SYMBOL DESCRIPTION 7 Receiver Inhibited RI This bit, if high, indicates that the receiver is not enabled because either an "Enable Receive to Page fnn" command was never issued, or a packet has been deposited into the RAM buffer page fnn as specified by the last "Enable Receive to Page fnn&qu[...]

26 Table 5 - Diagnostic Status Register BIT BIT NAME SYMBOL DESCRIPTION 7 My Reconfiguration MY- RECON This bit, if high, indicates that a past reconfiguration was caused by this node. It is set when the Lost Token Timer times out, and should be typically read following an interrupt caused by RECON. Refer to the Improved Diagnostics section for fur[...]

27 Table 6 - Command Register DATA COMMAND DESCRIPTION 0000 0000 Clear Transmit Interrupt This command is used only in the Command Chaining operation. Please refer to the Command Chaining section for definition of this command. 0000 0001 Disable Transmitter This command will cancel any pending transmit command (transmission that has not yet started[...]

28 Table 7 - Address Pointer High Register BIT BIT NAME SYMBOL DESCRIPTION 7 Read Data RDDATA This bit tells the COM20020 whether the following access will be a read or write. A logic "1" prepares the device for a read, a logic "0" prepares it for a write. 6 Auto Increment AUTOINC This bit controls whether the address pointer wi[...]

29 Table 9 - Configuration Register BIT BIT NAME SYMBOL DESCRIPTION 7 Reset RESET A software reset of the COM20020 is executed by writing a logic "1" to this bit. A software reset does not reset the microcontroller interface mode, nor does it affect the Configuration Register. The only registers that the software reset affect are the Stat[...]

30 Table 10 - Setup Register BIT BIT NAME SYMBOL DESCRIPTION 7 Pulse1 Mode P1MODE This bit determines the type of PULSE1 output driver used in Backplane Mode. When high, a push/pull output is used. When low, an open drain output is used. The default is open drain. 6 Four NACKS FOUR NACKS This bit, when set, will cause the EXNACK bit in the Diagnost[...]

31 Address Pointer Register Low 2K x 8 RAM 11 Data Register 8 I/O Address 04H I/O Address 03H 11-Bit Counter Memory Address Bus Memory Data Bus D0-D7 High I/O Address 02H INTERNAL FIGURE 7 - SEQUENTIAL ACCESS OPERATION[...]

32 INTERNAL RAM The integration of the 2K x 8 RAM in the COM20020 represents significant real estate savings. The most obvious benefit is the 24-pin package in which the device is now placed (a direct result of the integration of RAM). In addition, the PC board is now free of the cumbersome external RAM, external latch, and multiplexed address/data[...]

33 • The pointer may now be read to determine how many transfers were completed. The software flow for controlling the Configuration, Node ID, Tentative ID, and Next ID registers is generally limited to the initialization sequence and the maintenance of the network map. Additionally, it is necessary to understand the details of how the other Inte[...]

34 SID DID COUNT = 256-N NOT USED DATA BYTE 1 DATA BYTE 2 DATA BYTE N-1 DATA BYTE N NOT USED SID DID 0 COUNT = 512-N NOT USED DATA BYTE 1 DATA BYTE 2 DATA BYTE N-1 DATA BYTE N SHORT PACKET FORMAT LONG PACKET FORMAT ADDRESS ADDRESS 0 1 2 COUNT 255 511 N = DATA PACKET LENGTH SID = SOURCE ID DID = DESTIN A TION ID (DID = 0 FOR BROADCASTS) 0 1 2 COUNT [...]

35 buffer address 2 contains a zero or non-zero value. The format of the buffer is shown in Figure 8. Address 0 contains the Source Identifier (SID); Address 1 contains the Destination Identifier (DID); Address 2 (COUNT) contains, for short packets, the value 256-N, where N represents the number of information bytes in the message, or for long pack[...]

36 The third possibility which may occur after a FREE BUFFER ENQUIRY is issued is if the destination node does not respond at all. In this case, the TA bit is set to a logic "1", while the TMA bit remains at a logic "0". The user should determine whether the node should try to reissue the transmit command. The fourth possibility[...]

37 TRI R I T A POR TEST RECON TMA TTA TMA TTA TRI MSB LSB FIGURE 9 - COMMAND CHAINING STATUS REGISTER QUEUE COMMAND CHAINING The Command Chaining operation allows consecutive transmissions and receptions to occur without host microcontroller intervention. Through the use of a dual two-level FIFO, commands to be transmitted and received, as well as [...]

38 In the Command Chaining Mode, at any time after the first command is issued, the processor can issue a second "Enable Transmit from Page fnn" command. The COM20020 stores the fact that the second transmit command was issued, along with the page number. After the first transmission is completed, the COM20020 updates the Status Register [...]

39 the status of the receive operation is double buffered in order to retain the results of the first reception for analysis by the processor, therefore the information will remain in the Status Register until the "Clear Receive Interrupt" command is issued. Note that the interrupt will remain active until the "Clear Receive Interrup[...]

40 INITIALIZATION SEQUENCE Bus Determination Writing to and reading from an odd address location from the COM20020's address space causes the COM20020 to determine the appropriate bus interface. When the COM20020 is powered on the internal registers may be written to. Since writing a non-zero value to the Node ID Register wakes up the core, th[...]

41 node with the same ID does not exist on the network. Once it is determined that the ID in the Node ID Register is unique, the software should write a logic "1" to bit 5 of the Configuration Register to enable the basic transmit function. This allows the node to join the network. The Receive Activity (RCVACT) bit of the Diagnostic Statu[...]

42 network. This feature is useful because it minimizes the need for human intervention. When a value placed in the Tentative ID Register matches the Node ID of another node on the network, the TENTID bit is set, telling the software that this NODE ID already exists on the network. The software should periodically place values in the Tentative ID R[...]

43 OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range ........................................................................................ 0 o C to +70 o C Storage Temperature Range ...................................................................................... - 55 o C to +150 o C Lead Temperature (soldering[...]

44 PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT Low Output Voltage 1 (nPULSE1 in Normal Mode, nPULSE2, nTXEN) High Output Voltage 1 (nPULSE1 in Normal Mode, nPULSE2, nTXEN) V OL1 V OH1 2.4 0.4 V V I SINK =4mA I SOURCE =-2mA Low Output Voltage 2 (D0-D7) High Output Voltage 2 (D0-D7) V OL2 V OH2 2.4 0.4 V V I SINK =16mA I SOURCE =-12mA Low Output Voltag[...]

45 CAPACITANCE (T A = 25 ° C; f C = 1MHz; V DD = 0V) Output and I/O pins capacitive load specified as follows: PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT Input Capacitance C IN 5.0 pF Output Capacitance 1 (All outputs except nPULSE1 in BackPlane Mode) Output Capacitance 2 (nPULSE1, in BackPlane Mode Only - Open Drain) C OUT1 C OUT2 45 400 pF pF Max[...]

46 TIMING DIAGRAMS AD0-AD2, VALID nCS t1 t3 t8 T is the Arbitration Clock Period. T is identical to XTAL1 if SLOW ARB = 0, * T is twice X TAL1 period if SLOW ARB = 1 ALE VALID DATA t2, t6 t5 t4 t7 D3-D7 The Microcontroller typically accesses the COM20020 on every other cycle. Therefore, the cycle time specified in the microcontroller's datashe[...]

47 AD0-AD2, VALID nCS t1 t3 t8 T is the Arbitration Clock Period. T is identical to X TAL1 if SLOW ARB = 0, * T is twice XTAL1 period if SLOW ARB = 1 ALE VALID DATA t2, t6 t5 t4 t7 D3-D7 The Microcontroller typically accesses the COM20020 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be dou[...]

48 AD0-AD2, VALID nCS t1 t3 t8 T is the Arbitration Clock Period. T is identical to XTAL1 if SLOW ARB = 0, * T is twice XTAL1 period if SLOW ARB = 1 ALE VALID DATA t2, t6 t5 t4 t7 D3-D7 DIR t9 t10 The Microcontroller typically accesses the COM20020 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet sho[...]

49 AD0-AD2, VALID nCS t1 t3 t8 T is the Arbitration Clock Period. T is identical to X TAL1 if SLOW ARB = 0, * T is twice XTAL1 period if SLOW ARB = 1 ALE VALID DATA t2, t6 t5 t4 t7 D3-D7 The Microcontroller typically accesses the COM20020 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be dou[...]

50 A0-A2 VALID DATA VALID D0-D7 nCS t6 t1 t7 t3 t5 T is the Arbitration Clock Period. T is identical to XTAL1 if SLOW ARB = 0, * T is twice X TAL1 period if SLOW ARB = 1 t4 t2 The Microcontroller typically accesses the COM20020 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when c[...]

51 A0-A2 VALID DATA VALID D0-D7 nCS t8 t1 t9 t3 t6 T is the Arbitration Clock Period. T is identical to XTAL1 if SLOW ARB = 0, * T is twice XTAL1 period if SLOW ARB = 1 t4 t2 The Microcontroller typically accesses the COM20020 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when co[...]

52 A0-A2 VALID DATA VALID D0-D7 t1 t3 t5 t6 t7 Parameter Address Setup to nWR Active nCS Setup to WR Active Cycle Time (nWR Low to Next Time Low)** Valid Data Setup to nWR High Data Hold from nWR High min 15 5 10 max 4T* 30** units nS nS nS nS nS nCS t6 t1 t7 t3 t5 T is the Arbitration Clock Period. T is identical to X TAL1 if SLOW ARB = 0, * T is [...]

53 A0-A2 VALID DATA VALID D0-D7 Parameter min max units nCS t8 t1 t9 t3 t6 T is the Arbitration Clock Period. T is identical to XTAL1 if SLOW ARB = 0, * T is twice XTAL1 period if SLOW ARB = 1 t4 t2 The Microcontroller typically accesses the COM20020 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet s[...]

54 nPULSE2 t1 t3 t7 Parameter nPULSE1, nPULSE2 Pulse Width nPULSE1, nPULSE2 Overlap RXIN Period min 100 -10 max units nS nS nPULSE1 t1 * t1 = 2 x (crystal period) for clock frequencies other than 20 MHz. t6 RXIN Pulse Width t2 t2 nPULSE1, nPULSE2 Period nS t1 t3 400 0 +10 typ * * * t2,t7 = 8 x (crystal period) for clock frequencies other than 20 MH[...]

55 nPULSE1 t2 * t2,t7,t10 = 4 x (crystal period) for clock frequencies other than 20 MHz. t3 * t3,t11 = 8 x (crystal period) for clock frequencies other than 20 MHz. This period applies to data of two consecutive one's. RXIN t10 t11 nPULSE2 t5 t6 (Internal Clk) t4 * t5,t6 = 2 x (crystal period) for clock frequencies other than 20 MHz. Paramete[...]

56 t1 t3 Parameter Input Clock High Time Input Clock Period min 20 50 max units nS nS X TAL1 t1 t4 Input Clock Frequency 100 t2 Input Clock Low Time nS t3 20 typ 10 t2 20 MHz FIGURE 16 - TTL INPUT TIMING ON XTAL1 PIN t1 Parameter nRESET IN Pulse Width min 3.2 max units µS nRESET IN t1 t2 nINTR High to Next nINTR Low nS typ 200 t2 nINTR FIGURE 17 -[...]

57 A A1 B B1 C D D1 D2 D3 E F G R .160-.180 .090-.120 .013-.021 .026-.032 .020-.045 .485-.495 .450-.456 .390-.430 .300 REF .050 BSC .042-.056 .042-.048 .025-.045 DIM 28L J .000-.020 NOTES: All dimensions are in inches. Circle indicating pin 1 can appear on a top surface as shown on the drawing or right above it on a beveled edge. 1. 2. PIN NO. 1 G [...]

58 E1 E Base Plane Seating Plane D S B1 e B A2 A A1 L Note: All dimensions are in inches. A e C B e DIM A A1 A2 B B1 C D E E1 e eA eB L S 24L .090-.150 .020-.065 .145-.155 .016-.021 .060-.070 .010-.014 1.245-1.265 .590-.630 .530-.545 .100BSC .600REF .610-.670 .120-.140 .065-.085 FIGURE 18A - 24-PIN DIP PACKAGE DIMENSIONS[...]

59 COM20020 ERR ATA SHEET PAGE SECTION/FIGURE/ENTRY CORRECTION DATE REVISED 5 Pin No. 18/DESCRIPTION See Italicized Text 5/29/96 8 Network Protocol See Italicized Text 5/29/96 9 Network Reconfiguration See Italicized Text 5/29/96 9 Extended Timeout Function See Italicized Text 5/29/96 10 Line Protocol See Italicized Text 5/29/96 12 Microcontroller [...]

STANDARD MICROSYSTEMS CORP. Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed [...]