Texas Instruments PCI7611 manual

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IMPORT ANT NOTICE T exas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orde[...]

iii Contents Section Title Page 1 Introduction 1−1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Controller Functional Description 1−1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 PCI7621 Controller 1−1 . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

iv Section Title Page 3.5.8 SPKROUT and CAUDPWM Usage 3−9 . . . . . . . . . . . . . . . . . . . 3.5.9 LED Socket Activity Indicators 3−9 . . . . . . . . . . . . . . . . . . . . . . . . 3.5.10 CardBus Socket Registers 3−10 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 1 48-MHz Clock Requirements 3−10 . . . . . . . . . . . . . .[...]

v Section Title Page 4 PC Card Controller Programming Model 4−1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 PCI Configuration Register Map (Functions 0 and 1) 4−1 . . . . . . . . . . . . . 4.2 V endor ID Register 4−2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Device ID Register Func[...]

vi Section Title Page 4.42 Next Item Pointer Register 4−31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.43 Power Management Capabilities Register 4−32 . . . . . . . . . . . . . . . . . . . . . . 4.44 Power Management Control/Status Register 4−33 . . . . . . . . . . . . . . . . . . . . 4.45 Power Management Control[...]

vii Section Title Page 7 OHCI Controller Programming Model 7−1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 V endor ID Register 7−2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Device ID Register 7−2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

viii Section Title Page 8.15 V endor ID Register 8−12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.16 Host Controller Control Register 8−13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.17 Self-ID Buffer Pointer Register 8−14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

ix Section Title Page 10.4 V endor-Dependent Register 10−6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 Power-Class Programming 10−7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 Flash Media Controller Programming Model 1 1−1 . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 V endor [...]

x Section Title Page 12.16 Slot Information Register 12−10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.17 Capability ID and Next Item Pointer Registers 12−1 1 . . . . . . . . . . . . . . . . . 12.18 Power Management Capabilities Register 12−12 . . . . . . . . . . . . . . . . . . . . 12.19 Power Management Control [...]

xi Section Title Page 14 Electrical Characteristics 14−1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1 Absolute Maximum Ratings Over Operating T emperature Ranges 14−1 . 14.2 Recommended Operating Conditions 14−1 . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Electrical Characteristics Over[...]

xii List of Illustrations Figure Title Page 2−1 PCI7621 GHK/ZHK-Package T erminal Diagram 2−1 . . . . . . . . . . . . . . . . . . . . . 2−2 PCI7421 GHK/ZHK-Package T erminal Diagram 2−2 . . . . . . . . . . . . . . . . . . . . . 2−3 PCI761 1 GHK/ZHK-Package T erminal Diagram 2−3 . . . . . . . . . . . . . . . . . . . . . 2−4 PCI741 1 GH[...]

xiii List of T ables T able Title Page 1−1 T erms and Definitions 1−7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1 Signal Names by GHK T erminal Number 2−5 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2 CardBus PC Card Signal Names Sorted Alphabetically 2−9 . . . . . . . . . . . . [...]

xiv T able Title Page 3−18 Function 4 Power-Management Registers 3−26 . . . . . . . . . . . . . . . . . . . . . . . . . . 3−19 Function 5 Power-Management Registers 3−26 . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1 Bit Field Access T ag Descriptions 4−1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−2 F[...]

xv T able Title Page 5−13 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers Description 5−20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−14 ExCA Card Detect and General Control Register Description 5−21 . . . . . . . . . 5−15 ExCA Global Control Register Description [...]

xvi T able Title Page 8−1 1 Host Controller Control Register Description 8−13 . . . . . . . . . . . . . . . . . . . . . . . . 8−12 Self-ID Count Register Description 8−15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−13 Isochronous Receive Channel Mask High Register Description 8−16 . . . . . . . 8−14 Isochronous R[...]

xvii T able Title Page 1 1−5 Latency Timer and Class Cache Line Size Register Description 1 1−5 . . . . . . . 1 1−6 Header T ype and BIST Register Description 1 1−6 . . . . . . . . . . . . . . . . . . . . . . . . 1 1−7 Flash Media Base Address Register Description 1 1−6 . . . . . . . . . . . . . . . . . . . . 1 1−8 PCI Interrupt Pin R[...]

xviii T able Title Page 13−15 Smart Card Configuration 1 Register Description 13−16 . . . . . . . . . . . . . . . . . . . 13−16 Smart Card Configuration 2 Register Description 13−17 . . . . . . . . . . . . . . . . . . .[...]

1−1 1 Introduction The T exas Instruments PCI7621 controller is an integrated dual-socket UltraMedia PC Card controller , Smart Card controller , IEEE 1394 open HCI host controller and PHY , and flash media controller . This high-performance integrated solution provides the latest in PC Card, Smart Card, IEEE 1394, Secure Digital (SD), MultiMedia[...]

1−2 Function 5 of the PCI7621 controller is a PCI-based Smart Card controller used for communication with Smart Cards inserted in P C Card adapters. Utilizing Smart Card technology from Gemplus, this function provides compatibility with many different types of Smart Cards. 1.1.2 PCI7421 Controller The PCI7421 controller is a five-function PCI con[...]

1−3 through a passive PC Card adapter or through a dedicated Flash Media socket. In addition, this function includes D MA capabilities for improved Flash Media performance. Function 4 o f the PCI761 1 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This function controls communication with these Flash Media car[...]

1−4 1.2 Features The PCI7x21/PCI7x1 1 controller supports the following features: • PC Card Standard 8.1 compliant • PCI Bus Power Management Interface Specification 1.1 compliant • Advanced Configuration and Power Interface (ACPI) Specification 2.0 compliant • PCI Local Bus Specification Revision 2.3 compliant • PC 98/99 and PC2001 com[...]

1−5 • External cycle timer control for customized synchronization • Extended resume signaling for compatibility with legacy DV components • PHY -Link logic performs system initialization and arbitration functions • PHY -Link encode and decode functions included for data-strobe bit level encoding • PHY -Link incoming data resynchronized [...]

1−6 • SD Memory Card Specifications, SD Group, March 2000 • Memory Stick Format Specification, V ersion 2.0 (Memory Stick-Pro) • ISO Standards for Identification Cards ISO/IEC 7816 • SD Host Controller Standard Specification, rev . 1.0 • Memory Stick Format Specification, Sony Confidential, ver . 2.0 • SmartMedia Standard 2000, May 19[...]

1−7 1.5 T erms and Definitions T erms and definitions used in this document are given in T able 1−1. T able 1−1. T erms and Definitions TERM DEFINITIONS AT A T (advanced technology , as in PC A T) attachment interface A T A driver An existing host software component that loads when any flash media adapter and card is inserted into a PC Card s[...]

1−8[...]

2−1 2 T erminal Descriptions The PCI7x21/PCI7x1 1 controller is available in the 288-terminal MicroStar BGA  package (GHK) or the 288-terminal lead-free (Pb, atomic number 82) MicroStar BGA  package (ZHK). Figure 2−1 is a pin diagram of the PCI7621 package. Figure 2−2 is a pin diagram of the PCI7421 package. Figure 2−3 is a pin diagra[...]

2−2 B_CCLKRUN //B_WP (IOIS16 ) W P D A R T U V M N K L H J F G E B C 19 15 10 5 1 14 13 12 11 1 6 9 8 7 6 4 3 2 17 18 A_CINT// A_READY (IREQ ) A_CAD25 //A_A1 VCCA A_CAD21 //A_A5 A_CAD19 //A_A25 A_CC/BE2 //A_A12 A_CDEVSEL // A_A21 A_CP AR //A_A13 VCCA A_CAD1 1 //A_OE A_CAD8 //A_D15 A_RSVD //A_D14 A_CAD3 //A_D5 A_CAD0 //A_D3 B_CAD30 //B_D9 B_CAD27 [...]

2−3 W P D A R T U V M N K L H J F G E B C 19 15 10 5 1 14 13 12 11 1 6 9 8 7 6 4 3 2 17 18 A_CINT// A_READY (IREQ ) A_CAD25 //A_A1 VCCA A_CAD21 //A_A5 A_CAD19 //A_A25 A_CC/BE2 //A_A12 A_CDEVSEL // A_A21 A_CP AR //A_A13 VCCA A_CAD1 1 //A_OE A_CAD8 //A_D15 A_RSVD //A_D14 A_CAD3 //A_D5 A_CAD0 //A_D3 A_CAUDIO //A_BVD2 (SPKR ) A_CSERR //A_WAIT A_CAD26[...]

2−4 W P D A R T U V M N K L H J F G E B C 19 15 10 5 1 14 13 12 11 1 6 9 8 7 6 4 3 2 17 18 A_CINT// A_READY (IREQ ) A_CAD25 //A_A1 VCCA A_CAD21 //A_A5 A_CAD19 //A_A25 A_CC/BE2 //A_A12 A_CDEVSEL // A_A21 A_CP AR //A_A13 VCCA A_CAD1 1 //A_OE A_CAD8 //A_D15 A_RSVD //A_D14 A_CAD3 //A_D5 A_CAD0 //A_D3 A_CAUDIO //A_BVD2 (SPKR ) A_CSERR //A_WAIT A_CAD26[...]

2−5 T able 2−1. Signal Names by GHK Terminal Number TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER CardBus PC Card 16-Bit PC Card TERMINAL NUMBER CardBus PC Card 16-Bit PC Card A02 A_CAUDIO A_BVD2(SPKR) C06 A_CAD22 A_A4 A03 A_CVS1 A_VS1 C07 A_CAD19 A_A25 A04 A_CAD25 A_A1 C08 A_CFRAME A_A23 A05 V CCA V CCA C09 A_CDEVSEL [...]

2−6 T able 2−1. Signal Names by GHK Terminal Number (Continued) TERMINAL SIGNAL NAME TERMINAL SIGNAL NAME TERMINAL NUMBER CardBus PC Card 16-Bit PC Card TERMINAL NUMBER CardBus PC Card 16-Bit PC Card F09 A_CC/BE2 A_A12 H09 V CC V CC F10 A_CPERR A_A14 H10 V CC V CC F12 A_CAD6 A_D13 H11 V CC V CC F14 B_CSTSCHG B_BVD1(STSCHG/RI) H12 V CC V CC F15 [...]

2−7 T able 2−1. Signal Names by GHK Terminal Number (Continued) TERMINAL SIGNAL NAME TERMINAL SIGNAL NAME TERMINAL NUMBER CardBus PC Card 16-Bit PC Card TERMINAL NUMBER CardBus PC Card 16-Bit PC Card K05 SC_CLK SC_CLK M18 B_CC/BE0 B_CE1 K07 SC_VCC_5V SC_VCC_5V M19 VR_PORT VR_PORT K08 V CC V CC N01 DA T A DA T A K09 GND GND N02 LA TCH LA TCH K10[...]

2−8 T able 2−1. Signal Names by GHK Terminal Number (Continued) TERMINAL SIGNAL NAME TERMINAL SIGNAL NAME TERMINAL NUMBER CardBus PC Card 16-Bit PC Card TERMINAL NUMBER CardBus PC Card 16-Bit PC Card R19 XO XO V06 AD18 AD18 T01 GRST GRST V07 FRAME FRAME T02 GNT GNT V08 PERR PERR T03 RI_OUT/PME RI_OUT/PME V09 AD15 AD15 T17 VSSPLL VSSPLL V10 AD11[...]

2−9 T able 2−2. CardBus PC Card Signal Names Sorted Alphabetically SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER AD0 W13 A_CAD5 A13 A_CPERR F10 B_CAD30 A16 AD1 N1 1 A_CAD6 F12 A_CREQ E07 B_CAD31 B15 AD2 U12 A_CAD7 C13 A_CRST A06 B_CAUDIO C17 AD3 V12 A_CAD8 E12 A_CSERR B03 B_CBLOC[...]

2−10 T able 2−2. CardBus PC Card Signal Names Sorted Alphabetically (Continued) SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER GND G08 NC W17 SD_CMD J03 TPBIAS0 U15 GND G13 PA R P09 SD_DA T0 G01 TPBIAS1 U17 GND H13 PCLK P05 SD_DA T0 H03 TPB0N W14 GND J09 PC0(TEST1) R12 SD_DA T1 G0[...]

2−1 1 T able 2−3. 16-Bit PC Card Signal Names Sorted Alphabetically SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER AD0 W13 A_A5 B06 A_INP ACK E07 B_CE1 M18 AD1 N1 1 A_A6 G09 A_IORD C1 1 B_CE2 L19 AD2 U12 A_A7 B07 A_IOWR E1 1 B_D0 C16 AD3 V12 A_A8 B10 A_OE C12 B_D1 B16 AD4 W12 A_A9[...]

2−12 T able 2−3. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued) SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER GND G08 NC W17 SD_CMD J03 TPBIAS0 U15 GND G13 PA R P09 SD_DA T0 G01 TPBIAS1 U17 GND H13 PCLK P05 SD_DA T0 H03 TPB0N W14 GND J09 PC0(TEST1) R12 SD_DA T1 G02[...]

2−13 2.1 Detailed T erminal Descriptions Please see T able 2−4 through T able 2−19 for more detailed terminal descriptions. The following list defines the column headings and the abbreviations used in the detailed terminal description tables. • I/O T ype: − I = Digital input − O = Digital output − I/O = Digital input/output − AI = A[...]

2−14 T able 2−4. Power Supply T erminals Output description, internal pullup/pulldown resistors, and the power rail designation are not applicable for the power supply terminals. TERMINAL DESCRIPTION I/O INPUT EXTERNAL PIN STRAPPING NAME NUMBER DESCRIPTION I/O TYPE INPUT EXTERNAL COMPONENTS PIN STRAPPING (IF UNUSED) AGND N12, U14, U16 Analog ci[...]

2−15 T able 2−5. PC Card Power Switch T erminals Internal pullup/pulldown resistors, power rail designation, and pin strapping are not applicable for the power switch terminals. TERMINAL DESCRIPTION I/O INPUT OUTPUT EXTERNAL NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT EXTERNAL COMPONENTS CLOCK L06 Power switch clock. Information on the DA T A li[...]

2−16 T able 2−7. PCI Address and Data T erminals Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI address and data terminals. TERMINAL DESCRIPTION I/O INPUT OUTPUT POWER NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT POWER RAIL AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD[...]

2−17 T able 2−8. PCI Interface Control T erminals Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI interface control terminals. TERMINAL DESCRIPTION I/O INPUT OUTPUT POWER EXTERNAL NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT POWER RAIL EXTERNAL COMPONENTS DEVSEL N08 PCI device select. The controller asserts DEV[...]

2−18 T able 2−9. Multifunction and Miscellaneous T erminals The power rail designation is not applicable for the multifunction and miscellaneous terminals. TERMINAL DESCRIPTION I/O INPUT OUTPUT PU/ EXTERNAL PIN STRAPPING NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT PU/ PD EXTERNAL COMPONENTS PIN STRAPPING (IF UNUSED) A_USB_EN B_USB_EN E02 E01 USB[...]

2−19 T able 2−10. 16-Bit PC Card Address and Data T erminals External components are not applicable for the 16-bit PC Card address and data terminals. If any 16-bit PC Card address and data terminal is unused, then the terminal may be left floating. SOCKET A TERMINAL SOCKET B TERMINAL † DESCRIPTION I/O POWER NAME NO. NAME NO. DESCRIPTION I/O [...]

2−20 T able 2−1 1. 16-Bit PC Card Interface Control T erminals External components are not applicable for the 16-bit PC Card interface control terminals. If any 16-bit PC Card interface control terminal is unused, then the terminal may be left floating. SKT A TERMINAL SKT B TERMINAL † DESCRIPTION I/O POWER NAME NO. NAME NO. DESCRIPTION I/O TY[...]

2−21 T able 2−1 1. 16-Bit PC Card Interface Control T erminals (Continued) SKT A TERMINAL SKT B TERMINAL † DESCRIPTION I/O POWER NAME NO. NAME NO. DESCRIPTION I/O TYPE POWER RAIL A_OE C12 B_OE L18 Output enable. OE is driven low by the controller to enable 16-bit memory PC Card data output during host memory read cycles. DMA terminal count. O[...]

2−22 T able 2−12. CardBus PC Card Interface System T erminals A 33- Ω to 47- Ω series damping resistor (per PC Card specification) is the only external component needed for terminals B08 (A_CCLK) and H17 (B_CCLK). If any CardBus PC Card interface system terminal is unused, then the terminal may be left floating. SKT A TERMINAL SKT B TERMINA[...]

2−23 T able 2−13. CardBus PC Card Address and Data T erminals External components are not applicable for the 16-bit PC Card address and data terminals. If any CardBus PC Card address and data terminal is unused, then the terminal may be left floating. SKT A TERMINAL SKT B TERMINAL † DESCRIPTION I/O INPUT OUTPUT POWER NAME NO. NAME NO. DESCRIP[...]

2−24 T able 2−14. CardBus PC Card Interface Control T erminals If any CardBus PC Card interface control terminal is unused, then the terminal may be left floating. SKT A TERMINAL SKT B TERMINAL † DESCRIPTION I/O INPUT OUTPUT PU/ POWER NAME NO. NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT PU/ PD POWER RAIL A_CAUDIO A02 B_CAUDIO C17 CardBus audio[...]

2−25 T able 2−14. CardBus PC Card Interface Control T erminals (Continued) SKT A TERMINAL SKT B TERMINAL † DESCRIPTION I/O INPUT OUTPUT PU/ POWER NAME NO. NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT PU/ PD POWER RAIL A_CSTOP A09 B_CST OP J17 CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus [...]

2−26 T able 2−15. IEEE 1394 Physical Layer T erminals TERMINAL DESCRIPTION I/O INPUT OUTPUT EXTERNAL PIN STRAPPING NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT EXTERNAL COMPONENTS PIN STRAPPING (IF USED) CNA P15 Cable not active. This terminal is asserted high when there are no ports receiving incoming bias voltage. If it is not used, then this t[...]

2−27 T able 2−16. SD/MMC T erminals If any SD/MMC terminal is unused, then the terminal may be left floating. TERMINAL DESCRIPTION I/O INPUT OUTPUT PU/ POWER EXTERNAL NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT PU/ PD POWER RAIL EXTERNAL COMPONENTS MC_PWR_CTRL_0 MC_PWR_CTRL_1 F01 F02 Media card power control for flash media sockets. O L VCO1 Pow[...]

2−28 T able 2−18. Smart Media/XD T erminals If any Smart Media/XD terminal is unused, then the terminal may be left floating. TERMINAL DESCRIPTION I/O INPUT OUTPUT PU/ POWER EXTERNAL NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT PU/ PD POWER RAIL EXTERNAL P ARTS MC_PWR_CTRL_0 MC_PWR_CTRL_1 F01 F02 Media card power control for flash media sockets. [...]

2−29 T able 2−19. Smart Card T erminals † If any Smart Card terminal is unused, then the terminal may be left floating, except for SC_VCC_5V which must be connected to 5 V . TERMINAL DESCRIPTION I/O INPUT OUTPUT PU/ POWER EXTERNAL NAME NO. DESCRIPTION I/O TYPE INPUT OUTPUT PU/ PD POWER RAIL EXTERNAL P ARTS SC_CD L02 Smart Card card detect. Th[...]

2−30[...]

3−1 3 Feature/Protocol Descriptions The following sections give an overview of the PCI7x21/PCI7x1 1 controller . Figure 3−1 shows the connections to the PCI7x21/PCI7x11 controller. The PCI interface includes all address/data and control signals for PCI protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and seri[...]

3−2 3.2 I/O Characteristics Th e PCI7x21/PCI7x11 controller meets the ac specifications of the PC Card Standard (release 8.1) and the PCI Local Bus Specification. Figure 3−2 shows a 3-state bidirectional buffer. Section 14.2, Recommended Operating Conditions , provides the electrical characteristics of the inputs and outputs. Tied for Open Drai[...]

3−3 3.4.2 Device Resets The following are the requirements for proper reset of the PCI7x21/PCI7x1 1 controller: 1. GRST and PRST must both be asserted at power on. 2. GRST must be asserted for at least 2 ms at power on 3. PRST must be deasserted either at the same time or after GRST is asserted 4. PCLK must be stable for 100 µ s before PRST is d[...]

3−4 as bus master , by reading and writing PCI configuration registers . Setting bit 3 (SBDETECT) in the serial bus control/status register (PCI offset B3h, see Section 4.50) causes the PCI7x21/PCI7x1 1 controller to route the SDA an d SCL signals to the SDA and SCL terminals, respectively . The read/write data, slave address, and byte addresses [...]

3−5 3.4.5 Function 2 (OHCI 1394) Subsystem Identification The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI configuration space (see Section 7.25, Subsystem Access Registe[...]

3−6 3.5.1 PC Card Insertion/Removal and Recognition The PC Card Standard (release 8.1) addresses the card-detection and recognition process through an interrogation procedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through this interrogation, card voltage requirements and interface (16-bit versus CardBus) a[...]

3−7 T able 3−2. PC Card—Card Detect and V oltage Sense Connections CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 Key Interface V CC V PP /V CORE Ground Ground Open Open 5 V 16-bit PC Card 5 V Per CIS (V PP ) Ground Ground Open Ground 5 V 16-bit PC Card 5 V and 3.3 V Per CIS (V PP ) Ground Ground Ground Ground 5 V 16-bit PC Card 5 V , 3.3 V , and X.[...]

3−8 3.5.5 Power Switch Interface The power switch interface of the PCI7x21/PCI7x1 1 controller is a 3-pin serial interface. This 3-pin interface is implemented such that the PCI7x21/PCI7x1 1 controller can connect to both the TPS2226 and TPS2228 power switches. Bit 10 (12V_SW_SEL) in the general control register (PCI offset 86h, see Section 4.31)[...]

3−9 3.5.7 Integrated Pullup Resistors for PC Card Interface The PC Card Standard requires pullup resistors on various terminals to support both CardBus and 16-bit PC Card configurations. The PCI7x21/PCI7x1 1 controller has integrated all of these pullup resistors and requires no additional external components. The I/O buffer on the BVD1(STSCHG )/[...]

3−10 PCI7x21/ PCI7x1 1 Current Limiting R ≈ 150 Ω Socket A LED MFUNCx Current Limiting R ≈ 150 Ω Socket B LED MFUNCy Figure 3−6. T wo Sample LED Circuits As indicated, the LED signals are driven for a period of 64 ms by a counter circuit. T o avoid the possibility of the LEDs appearing to be stuck when the PCI clock is stopped, the LED [...]

3−1 1 • Frequency stability (overtemperature and age): A crystal with ± 30 ppm frequency stability is recommended for adequate margin. NOTE: The total frequency variation must be kept below ± 100 ppm from nominal with some allowance for error introduced by board and device variations. T rade-offs between frequency tolerance and stability may [...]

3−12 SDA SCL Start Condition Stop Condition Change of Data Allowed Data Line Stable, Data V alid Figure 3−7. Serial-Bus Start/Stop Conditions and Bit T ransfers Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is unlimited; however, each byte must be completed with an acknowledge bi[...]

3−13 Figure 3−10 illustrates a byte read. The read protocol is very similar to the write protocol, except the R/W command bit must be set to 1 to indicate a read-data transfer. In addition, the PCI7x21/PCI7x11 master must acknowledge reception of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read [...]

3−14 T able 3−9. EEPROM Loading Map SERIAL ROM OFFSET BYTE DESCRIPTION 00h CardBus function indicator (00h) 01h Number of bytes (20h) PCI 04h, command register , function 0, bits 8, 6−5, 2−0 02h [7] Command register , bit 8 [6] Command register , bit 6 [5] Command register , bit 5 [4:3] RSVD [2] Command register , bit 2 [1] Command register[...]

3−15 T able 3−9. EEPROM Loading Map (Continued) SERIAL ROM OFFSET BYTE DESCRIPTION 25h PCI 2Ch, subsystem vendor ID, byte 0 26h PCI 2Dh, subsystem vendor ID, byte 1 27h PCI 2Eh, subsystem ID, byte 0 28h PCI 2Fh, subsystem ID, byte 1 29h PCI F4h, Link_Enh, byte 0, bits 7, 2, 1 OHCI 50h, host controller control, bit 23 [7] Link_Enh. enab_unfair [[...]

3−16 T able 3−9. EEPROM Loading Map (Continued) SERIAL ROM OFFSET BYTE DESCRIPTION 49h PCI 94h, slot 0 3.3 V maximum current 4Ah PCI 98h, slot 1 3.3 V maximum current 4Bh PCI 9Ch, slot 2 3.3 V maximum current 4Ch Reserved (PCI A0h, slot 3 3.3 V maximum current) 4Dh Reserved (PCI A4h, slot 4 3.3 V maximum current) 4Eh Reserved (PCI A8h, slot 5 3[...]

3−17 3.7.1 PC Card Functional and Card Status Change Interrupts PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by 16-bit I/O PC Cards and by CardBus PC Cards. Card status ch[...]

3−18 T able 3−1 1. PC Card Interrupt Events and Description CARD TYPE EVENT TYPE SIGNAL DESCRIPTION Battery conditions CSC BVD1(STSCHG)//CSTSCHG A transition on BVD1 indicates a change in the PC Card battery conditions. 16-bit memory Battery conditions (BVD1, BVD2) CSC BVD2(SPKR)//CAUDIO A transition on BVD2 indicates a change in the PC Card ba[...]

3−19 T able 3−10 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit PC Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to the flag bit to clear and the other is by reading the flag bit register . The selection of flag bit clear[...]

3−20 The INTRTIE and TIEALL bits af fect the read-only value provided through accesses to the interrupt pin register (PCI offset 3Dh, see Section 4.24). T able 3−12 summarizes the interrupt signaling modes. T able 3−12. Interrupt Pin Register Cross Reference INTRTIE Bit TIEALL Bit INTPIN Function 0 (CardBus) INTPIN Function 1 (CardBus) INTPIN[...]

3−21 • Ring indicate • PCI power management • Cardbus bridge power management • ACPI support PCI Bus PCI7x21/P CI7x1 1 1394a Socket EEPROM Power Switch SD/MMC PC Card/ UltraMedia Card Power Switch PC Card/ UltraMedia Card Power Switch SD/MMC MS/MSPRO SM/xD † Th e system connection to GRST is implementation-specific. GRST must be asserte[...]

3−22 3.8.2 Integrated Low-Dropout V oltage Regulator (LDO-VR) The PCI7x21/PCI7x1 1 controller requires 1.5-V core voltage. The core power can be supplied by the PCI7x21/PCI7x1 1 controller itself using the internal LDO-VR. The core power can alternatively be supplied by an external power supply through the VR_PORT terminal. T able 3−14 lists th[...]

3−23 3.8.5 16-Bit PC Card Power Management The COE bit (bit 7) of the ExCA power control register (ExCA offset 02h/42h/802h, see Section 5.3) and PWRDWN bit (bit 0) of the ExCA global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.20) are provided for 16-bit PC Card power management. The COE bit places the card interface in a high-impe[...]

3−24 places the PCI outputs of the controller in a high-impedance state and gates the PCLK signal internally to the controller unless a PCI transaction is currently in process (GNT is asserted). It is important that the PCI bus not be parked on the PCI7x21/PCI7x1 1 controller when SUSPEND is asserted because the outputs are in a high-impedance st[...]

3−25 3.8.9 PCI Power Management 3.8.9.1 CardBus Power Management (Functions 0 and 1) The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges establishes the infrastructure required to let the operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the [...]

3−26 For more information on PCI power management, see the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges . 3.8.9.2 OHCI 1394 (Function 2) Power Management The PCI7x21/PCI7x1 1 controller complies with the PCI Bus Power Management Interface Specification . The controller supports the D0 (unitialized), D0 (active), D1,[...]

3−27 The T exas Instruments PCI7x21/PCI7x1 1 controller addresses these D3 wake-up issues in the following manner: • T wo resets are provided to handle preservation of PME context bits: − Global reset (GRST ) is used only on the initial boot up of the system after power up. It places the PCI7x21/PCI7x1 1 controller in its default state and re[...]

3−28 • ExCA card status-change interrupt configuration register (ExCA 805h/845h, see Section 5.6): bits 3−0 • ExCA card detect and general control register (ExCA 816h/856h, see Section 5.19): bits 7, 6 • Socket event register (CardBus offset 00h, see Section 6.1): bits 3−0 • Socket mask register (CardBus offset 04h, see Section 6.2): [...]

3−29 The global reset-only (function 3) register bits: • Subsystem vendor ID register (PCI offset 2Ch, see Section 1 1.9): bits 15–0 • Subsystem ID register (PCI offset 2Eh, see Section 1 1.10): bits 15–0 • Power management control and status register (PCI offset 48h, see Section 1 1.18): bits 15, 8, 1, 0 • General control register (P[...]

3−30 3.9 IEEE 1394 Application Information 3.9.1 PHY Port Cable Connection TP A+ TP A− TPB+ TPB− Cable Port CPS TPBIAS 56 Ω 56 Ω 56 Ω 56 Ω 5 k Ω 1 µ F 400 k Ω 220 pF (see Note A) PCI7x21/ PCI7x1 1 Cable Power Pair Cable Pair A Cable Pair B Outer Shield T ermination NOTE A: IEEE Std 1394-1995 calls for a 250-pF capacitor , which i[...]

3−31 Outer Cable Shield Chassis Ground Figure 3−19. Non-DC Isolated Outer Shield T ermination 3.9.2 Crystal Selection The PCI7x21/PCI7x1 1 controller is designed to use an external 24.576-MHz crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circui[...]

3−32 X1 24.576 MHz I S X1 C PHY + C BD X0 C10 C9 Figure 3−20. Load Capacitance for the PCI7x21/PCI7x1 1 PHY The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency , minimizing noise introduced into the PHY phase-lock loop, and minimizing any emissions from the circuit. The crystal and two load capa[...]

3−33 Therefore, in order to maintain consistent gap-counts throughout the bus, the following rules apply to the use of the IBR bit, RHB, and Gap_Count in PHY register 1: • Following the transmission of a PHY -config packet, a bus reset must be initiated in order to verify that all nodes have correctly updated their RHBs and Gap_Count values and[...]

3−34[...]

4−1 4 PC Card Controller Programming Model This chapter describes the PCI7x21/PCI7x1 1 PCI configuration registers that make up the 256-byte PCI configuration header for each PCI7x21/PCI7x1 1 function. There are some bits which affect both CardBus functions, but which, in order to work properly , must be accessed only through function 0. These ar[...]

4−2 T able 4−2. Functions 0 and 1 PCI Configuration Register Map (Continued) REGISTER NAME OFFSET CardBus I/O base register 0 2Ch CardBus I/O limit register 0 30h CardBus I/O base register 1 34h CardBus I/O limit register 1 38h Bridge control † Interrupt pin Interrupt line 3Ch Subsystem ID ‡ Subsystem vendor ID ‡ 40h PC Card 16-bit I/F le[...]

4−3 4.3 Device ID Register Functions 0 and 1 This read-only register contains the device ID assigned by TI to the PCI7x21/PCI7x1 1 CardBus controller functions (PCI functions 0 and 1). Bit 15 14 13 12 11 1 0 9876543210 Name Device ID—Smart Card enabled T ype RRRRRRRRRRRRRRRR Default 1000000000110001 Register: Device ID Offset: 02h (Functions 0 [...]

4−4 4.4 Command Register The PCI command register provides control over the PCI7x21/PCI7x1 1 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification (see T able 4−3). None of the bit functions in this register are shared among the PCI7x21/PCI7x1 1 PCI functions. Three command registers exist in t[...]

4−5 T able 4−3. Command Register Description (continued) BIT SIGNAL TYPE FUNCTION 1 MEM_EN RW Memory space enable. This bit controls whether or not the PCI7x21/PCI7x1 1 controller can claim cycles in PCI memory space. 0 = Disables the PCI7x21/PCI7x1 1 response to memory space accesses (default) 1 = Enables the PCI7x21/PCI7x1 1 response to memor[...]

4−6 T able 4−4. Status Register Description (continued) BIT SIGNAL TYPE FUNCTION 4 CAPLIST R Capabilities list. This bit returns 1 when read. This bit indicates that capabilities in addition to standard PCI capabilities are implemented. The linked list of PCI power-management capabilities is implemented in this function. 3 INT_ST A TUS RU Inter[...]

4−7 4.9 Latency Timer Register The latency timer register specifies the latency timer for the PCI7x21/PCI7x1 1 controller , in units of PCI clock cycles. When the PCI7x21/PCI7x1 1 controller is a PCI bus initiator and asserts FRAME , the latency timer begins counting from zero. If the latency timer expires before the PCI7x21/PCI7x1 1 transaction [...]

4−8 4.12 CardBus Socket Registers/ExCA Base Address Register This register is programmed with a base address referencing the CardBus socket registers and the memory-mapped ExCA register set. Bits 31−12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI memory address space on a 4-Kbyte boundary . Bits 1 1−0 ar[...]

4−9 4.14 Secondary Status Register The secondary status register is compatible with the PCI-PCI bridge secondary status register . It indicates CardBus-related device information to the host system. This register is very similar to the PCI status register (PCI offset 06h, see Section 4.5), and status bits are cleared by a writing a 1. This regist[...]

4−10 4.15 PCI Bus Number Register The PCI bus number register is programmed by the host system to indicate the bus number of the PCI bus to which the PCI7x21/PCI7x1 1 controller is connected. The PCI7x21/PCI7x1 1 controller uses this register in conjunction with the CardBus bus number and subordinate bus number registers to determine when to forw[...]

4−1 1 4.18 CardBus Latency Timer Register The CardBus latency timer register is programmed by the host system to specify the latency timer for the PCI7x21/PCI7x1 1 CardBus interface, in units of CCLK cycles. When the PCI7x21/PCI7x1 1 controller is a CardBus initiator and asserts CFRAME , the CardBus latency timer begins counting. If the latency t[...]

4−12 4.20 CardBus Memory Limit Registers 0, 1 These registers indicate the upper address of a PCI memory address range. They are used by the PCI7x21/PCI7x1 1 controller to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. Bits 31−12 of these registers are read/write and allo[...]

4−13 4.22 CardBus I/O Limit Registers 0, 1 These registers indicate the upper address of a PCI I/O address range. They are used by the PCI7x21/PCI7x1 1 controller to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. The lower 16 bits of this register locate the top of the I/O wi[...]

4−14 4.24 Interrupt Pin Register Th e value read from this register is function dependent. The default value for function 0 is 01h (INT A ), the default value fo r function 1 is 02h (INTB ), the default value for function 2 is 03h (INTC ), the default value for function 3 is 01h (INT A ), the default value for function 4 is 01h (INT A ), the defa[...]

4−15 Register: Interrupt pin Offset: 3Dh T ype: Read-only Default: 01h (function 0), 02h (function 1), 03h (function 2), 04h (function 3), 04h (function 4), 04h (function 5) T able 4−6. Interrupt Pin Register Cross Reference INTRTIE BIT (BIT 29, OFFSET 80h) TIEALL BIT (BIT 28, OFFSET 80h) INTPIN FUNCTION 0 (CARDBUS) INTPIN FUNCTION 1 (CARDBUS) [...]

4−16 T able 4−7. Bridge Control Register Description (Continued) BIT SIGNAL TYPE FUNCTION 6 † CRST RW CardBus reset. When this bit is set, the CRST signal is asserted on the CardBus interface. The CRST signal can also be asserted by passing a PRST assertion to CardBus. 0 = CRST is deasserted. 1 = CRST is asserted (default). This bit is not cl[...]

4−17 4.27 Subsystem ID Register The subsystem ID register , used for system and option card identification purposes, may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register (PCI offset 80h, see Section 4.29). When bit 5 is 0, this register[...]

4−18 4.29 System Control Register System-level initializations are performed through programming this doubleword register . Some of the bits are global in nature and must be accessed only through function 0. See T able 4−8 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name System contro[...]

4−19 T able 4−8 . System Control Register Description (continued) BIT SIGNAL TYPE FUNCTION 22 ‡ CBRSVD RW CardBus reserved terminals signaling. When this bit is set, the RSVD CardBus terminals are driven low when a CardBus card has been inserted. When this bit is low , these signals are placed in a high-impedance state. 0 = Place the CardBus [...]

4−20 T able 4−8 . System Control Register Description (continued) BIT SIGNAL TYPE FUNCTION 4 ‡§ CB_DP AR RW CardBus data parity SERR signaling enable. 0 = CardBus data parity not signaled on PCI SERR signal (default) 1 = CardBus data parity signaled on PCI SERR signal 3 ‡§ RSVD R Reserved. This bit returns 0 when read. 2 ‡ EXCAPOWER R E[...]

4−21 4.31 General Control Register The general control register provides top level PCI arbitration control. It also provides the ability to disable the 1394 OHCI function and provides control over miscellaneous new functionality . See T able 4−9 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name [...]

4−22 T able 4−9. General Control Register Description BIT SIGNAL TYPE FUNCTION 15 ‡ FM_PWR_CTRL _POL RW Flash media power control pin polarity . This bit controls the polarity of the MC_PWR_CTRL_0 and MC_PWR_CTRL_1 terminals. 0 = MC_PWR_CTRL_x terminals are active low (default) 1 = MC_PWR_CTRL_x terminals are active high 14 ‡ SC_IF_SEL RWU [...]

4−23 4.32 General-Purpose Event Status Register The general-purpose event status register contains status bits that are set when general events occur , and can be programmed to generate general-purpose event signaling through GPE . See T able 4−10 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name General-purpose even[...]

4−24 4.33 General-Purpose Event Enable Register The general-purpose event enable register contains bits that are set to enable GPE signals. See T able 4−1 1 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name General-purpose event enable T ype RW RW R RW RW RW RW RW Default 0 0 0 0 0 0 0 0 Register: General-purpose eve[...]

4−25 4.35 General-Purpose Output Register The general-purpose output register is used to drive the GPO4−GPO0 outputs. See T able 4−13 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name General-purpose output T ype R R R RW RW RW RW RW Default 0 0 0 0 0 0 0 0 Register: General-purpose output Offset: 8Bh T ype: Read-o[...]

4−26 4.36 Multifunction Routing Status Register The multifunction routing status register is used to configure the MFUNC6−MFUNC0 terminals. These terminals may be configured for various functions. This register is intended to be programmed once at power-on initialization. The default value for this register can also be loaded through a serial E[...]

4−27 T able 4−14. Multifunction Routing Status Register Description (Continued) BIT SIGNAL TYPE FUNCTION 7−4 ‡ MFUNC1 RW Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal as follows: 0000 = GPI1 0100 = OHCI_LED 1000 = CAUDPWM 1 100 = LEDA1 0001 = GPO1 0101 = IRQ5 1001 = IRQ9 1 101 =[...]

4−28 4.38 Card Control Register The card control register is provided for PCI1 130 compatibility . RI_OUT is enabled through this register , and the enable bit is shared between functions 0 and 1. See T able 4−16 for a complete description of the register contents. The RI_OUT signal is enabled through this register , and the enable bit is share[...]

4−29 4.39 Device Control Register The device control register is provided for PCI1 130 compatibility . It contains bits that are shared between functions 0 and 1. The interrupt mode select is programmed through this register . The socket-capable force bits are also programmed through this register . See T able 4−17 for a complete description of[...]

4−30 4.40 Diagnostic Register The diagnostic register is provided for internal TI test purposes. It is a read/write register, but only 0s must be written to it. See Table 4−18 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name Diagnostic T ype RW R RW RW RW RW RW RW Default 0 1 1 0 0 0 0 0 Register: Diagnostic Offset:[...]

4−31 4.41 Capability ID Register Th e capability ID register identifies the linked list item as the register for PCI power management. The register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value. Bit 7 6 5 4 3 2 1 0 Name Capability ID T ype R R R R R R R R Defau[...]

4−32 4.43 Power Management Capabilities Register The power management capabilities register contains information on the capabilities of the PC Card function related to power management. Both PCI7x21/PCI7x1 1 CardBus bridge functions support D0, D1, D2, and D3 power states. Default register value is FE12h for operation in accordance with PCI Bus P[...]

4−33 4.44 Power Management Control/Status Register The power management control/status register determines and changes the current power state of the PCI7x21/PCI7x1 1 CardBus function. The contents of this register are not affected by the internally generated reset caused by the transition from the D3 hot to D0 state. See T able 4−20 for a comp[...]

4−34 4.45 Power Management Control/Status Bridge Support Extensions Register This register supports PCI bridge-specific functionality . It is required for all PCI-to-PCI bridges. See T able 4−21 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name Power management control/status bridge support extensions T ype R R R R R[...]

4−35 4.47 Serial Bus Data Register The serial bus data register is for programmable serial bus byte reads and writes. This register represents the data when generating cycles on the serial bus interface. To write a byte, this register must be programmed with the data, the serial bus index register must be programmed with the byte address, the ser[...]

4−36 4.49 Serial Bus Slave Address Register Th e serial bus slave address register is for programmable serial bus byte read and write transactions. To write a byte, the serial bus data register must be programmed with the data, the serial bus index register must be programmed with the byte address, and this register must be programmed with both t[...]

4−37 4.50 Serial Bus Control/Status Register Th e serial bus control and status register communicates serial bus status information and selects the quick command protocol. Bit 5 (REQBUSY) in this register must be polled during serial bus byte reads to indicate when data is valid in the serial bus data register. See Table 4−25 for a complete des[...]

4−38[...]

5−1 5 ExCA Compatibility Registers (Functions 0 and 1) The ExCA (exchangeable card architecture) registers implemented in the PCI7x21/PCI7x1 1 controller are register-compatible with the Intel 82365SL-DF PCMCIA controller . ExCA registers are identified by an offset value, which is compatible with the legacy I/O index/data scheme used on the Inte[...]

5−2 16-Bit Legacy-Mode Base Address PCI7x21/PCI7x1 1 Configuration Registers 10h CardBus Socket/ExCA Base Address Note: The 16-bit legacy-mode base address register is shared by function 0 and 1 as indicated by the shading. 44h Index Data Host I/O Space PC Card A ExCA Registers PC Card B ExCA Registers 00h Offset 3Fh 40h 7Fh Offset of desired reg[...]

5−3 T able 5−1. ExCA Registers and Offsets EXCA REGISTER NAME PCI MEMOR Y ADDRESS OFFSET (HEX) EXCA OFFSET (CARD A) EXCA OFFSET (CARD B) Identification and revision ‡ 800 00 40 Interface status 801 01 41 Power control † 802† 02 42 Interrupt and general control † 803† 03 43 Card status change † 804† 04 44 Card status change interru[...]

5−4 T able 5−1. ExCA Registers and Offsets (continued) EXCA REGISTER NAME PCI MEMOR Y ADDRESS OFFSET (HEX) EXCA OFFSET (CARD A) EXCA OFFSET (CARD B) Reserved 826 26 66 Reserved 827 27 67 Memory window 3 start-address low-byte 828 28 68 Memory window 3 start-address high-byte 829 29 69 Memory window 3 end-address low-byte 82A 2A 6A Memory window[...]

5−5 5.1 ExCA Identification and Revision Register This register provides host software with information on 16-bit PC Card support and 82365SL-DF compatibility. See Table 5−2 for a complete description of the register contents. NOTE: If bit 5 (SUBSYRW) in the system control register is 1, then this register is read-only . Bit 7 6 5 4 3 2 1 0 Nam[...]

5−6 5.2 ExCA Interface Status Register This register provides information on current status of the PC Card interface. An X in the default bit values indicates that the value of the bit after reset depends on the state of the PC Card interface. See Table 5−3 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name ExCA inter[...]

5−7 5.3 ExCA Power Control Register This register provides PC Card power control. Bit 7 of this register enables the 16-bit outputs on the socket interface, and can be used for power management in 16-bit PC Card applications. See Table 5−5 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name ExCA power control T ype RW [...]

5−8 5.4 ExCA Interrupt and General Control Register This register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions. See Table 5−6 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name ExCA interrupt and general control T ype RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 R[...]

5−9 5.5 ExCA Card Status-Change Register The ExCA card status-change register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions. The register enables these interrupt sources to generate an interrupt to the host. When the interrupt source is disabled, the corresponding bit in this register always read[...]

5−10 5.6 ExCA Card Status-Change Interrupt Configuration Register This register controls interrupt routing for CSC interrupts, as well as masks/unmasks CSC interrupt sources. See Table 5−8 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name ExCA card status-change interrupt configuration T ype RW RW RW RW RW RW RW RW D[...]

5−1 1 5.7 ExCA Address Window Enable Register The ExCA address window enable register enables/disables the memory and I/O windows to the 16-bit PC Card. By default, all windows to the card are disabled. The PCI7x21/PCI7x1 1 controller does not acknowledge PCI memory or I/O cycles to the card if the corresponding enable bit in this register is 0, [...]

5−12 5.8 ExCA I/O Window Control Register The ExCA I/O window control register contains parameters related to I/O window sizing and cycle timing. See Table 5−10 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window control T ype RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 Register: ExCA I /O window co[...]

5−13 5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the start address. Bit 7 6 5 4 3 2 1 0 Name ExCA I/O windows 0 and 1 start-address low-byte T ype RW RW RW RW RW RW [...]

5−14 5.1 1 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the start address. Bit 7 6 5 4 3 2 1 0 Name ExCA I/O windows 0 and 1 end-address low-byte T ype RW RW RW RW RW RW RW R[...]

5−15 5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19−A12 of the start address. Bit 7 6 5 4 3 2 1 0 Name ExCA memory windows 0−4 start-address low-byte T ype R[...]

5−16 5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the start address. In addition, the memory window data width and wait states are set in th[...]

5−17 5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3 , a n d 4 . The 8 bits of these registers correspond to bits A19−A12 of the end address. Bit 7 6 5 4 3 2 1 0 Name ExCA memory windows 0−4 end-address low-byte T ype RW RW[...]

5−18 5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the end address. In addition, the memory window wait states are set in this register . See T a[...]

5−19 5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19−A12 of the offset address. Bit 7 6 5 4 3 2 1 0 Name ExCA memory windows 0−4 offset-address low-byte T y[...]

5−20 5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers These registers contain the high 6 bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. The lower 6 bits of these registers correspond to bits A25−A20 of the offset address. In addition, the write protection and common/attribute memory config[...]

5−21 5.19 ExCA Card Detect and General Control Register This register controls how the ExCA registers for the socket respond to card removal. It also reports the status of the VS1 and VS2 signals at the PC Card interface. T able 5−14 describes each bit in the ExCA card detect and general control register . Bit 7 6 5 4 3 2 1 0 Name ExCA card det[...]

5−22 5.20 ExCA Global Control Register This register controls both PC Card sockets, and is not duplicated for each socket. The host interrupt mode bits in this register are retained for 82365SL-DF compatibility . See T able 5−15 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name ExCA global control T ype R R R RW RW R[...]

5−23 5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the offset address, and bit 0 is always 0. Bit 7 6 5 4 3 2 1 0 Name ExCA I/O windows 0 and 1 offset-address low-b[...]

5−24 5.23 ExCA Memory Windows 0−4 Page Registers The upper 8 bits of a 4-byte PCI memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows. Each window has its own page register , all of which default to 00h. By programming this register to a nonzero value, host software can locate 16-bit me[...]

6−1 6 CardBus Socket Registers (Functions 0 and 1) The 1997 PC Card Standard requires a CardBus socket controller to provide five 32-bit registers that report and control socket-specific functions. The PCI7x21/PCI7x1 1 controller provides the C ard Bu s s ock et /E xC A ba se ad dre ss register (PCI offset 10h, see Section 4.12) to locate these C[...]

6−2 6.1 Socket Event Register This register indicates a change in socket status has occurred. These bits do not indicate what the change is, only that one has occurred. Software must read the socket present state register for current status. Each bit in this register can be cleared by writing a 1 to that bit. The bits in this register can be set [...]

6−3 6.2 Socket Mask Register This register allows software to control the CardBus card events which generate a status change interrupt. The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register (offset 00h, see Section 6.1). See T able 6−3 for a complete description of the register contents.[...]

6−4 6.3 Socket Present State Register This register reports information about the socket interface. W rites to the socket force event register (of fset 0Ch, see Section 6.4), as well as general socket interface status, are reflected here. Information about PC Card V CC support and card type is only updated at each insertion. Also note that the PC[...]

6−5 T able 6−4. Socket Present State Register Description (Continued) BIT SIGNAL TYPE FUNCTION 9 † BADVCCREQ R Bad V CC request. This bit indicates that the host software has requested that the socket be powered at an invalid voltage. 0 = Normal operation (default) 1 = Invalid V CC request by host software 8 † DA T ALOST R Data lost. This b[...]

6−6 T able 6−5. Socket Force Event Register Description BIT SIGNAL TYPE FUNCTION 31−15 RSVD R Reserved. These bits return 0s when read. 14 CVSTEST W Card VS test. When this bit is set, the PCI7x21/PCI7x1 1 controller reinterrogates the PC Card, updates th e socket present state register (offset 08h, see Section 6.3), and re-enables the socket[...]

6−7 6.5 Socket Control Register This register provides control of the voltages applied to the socket V PP and V CC . The PCI7x21/PCI7x1 1 controller ensures that the socket is powered up only at acceptable voltages when a CardBus card is inserted. See T able 6−6 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23[...]

6−8 6.6 Socket Power Management Register This register provides power management control over the socket through a mechanism for slowing or stopping the clock on the card interface when the card is idle. See T able 6−7 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Socket power mana[...]

7−1 7 OHCI Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x1 1 1394 open host controller interface. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for eac[...]

7−2 7.1 V endor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to T exas Instruments is 104Ch. Bit 15 14 13 12 11 1 0 9876543210 Name V endor ID T ype RRRRRRRRRRRRRRRR Default 0001000001001100 Register: V endor ID Offset: 00h T ype: Read-only D[...]

7−3 7.3 Command Register The command register provides control over the PCI7x21/PCI7x1 1 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification , as seen in the following bit descriptions. See T able 7−2 for a complete description of the register contents. Bit 15 14 13 12 11 1 0 9876543210 Name [...]

7−4 7.4 Status Register The status register provides status over the PCI7x21/PCI7x1 1 interface to the PCI bus. All bit functions adhere to the definitions i n the PCI Local Bus Specification , as seen in the following bit descriptions. See T able 7−3 for a complete description of the register contents. Bit 15 14 13 12 11 1 0 9876543210 Name St[...]

7−5 7.5 Class Code and Revision ID Register The class code and revision ID register categorizes the PCI7x21/PCI7x1 1 controller as a serial bus controller (0Ch), controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the least significant byte. See T able 7−4 for a complete de[...]

7−6 7.7 Header T ype and BIST Register The header type and built-in self-test (BIST) register indicates the PCI7x21/PCI7x1 1 PCI header type and no built-in self-test. See T able 7−6 for a complete description of the register contents. Bit 15 14 13 12 11 1 0 9876543210 Name Header type and BIST T ype RRRRRRRRRRRRRRRR Default 0000000010000000 Re[...]

7−7 7.9 TI Extension Base Address Register The TI extension base address register is programmed with a base address referencing the memory-mapped TI extension registers. When BIOS writes all 1s to this register , the value read back is FFFF C000h, indicating that at least 16K bytes of memory address space are required for the TI registers. See T [...]

7−8 7.10 CardBus CIS Base Address Register The internal CARDBUS input to the 1394 OHCI core is tied high such that this register returns 0s when read. See T able 7−9 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CardBus CIS base address T ype RW RW RW RW RW RW RW RW RW RW RW RW RW [...]

7−9 7.12 Subsystem Identification Register The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI configuration space (see Section 7.25). See T able 7−10 for a complete descr[...]

7−10 7.14 Interrupt Line Register The interrupt line register communicates interrupt line routing information. See T able 7−1 1 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name Interrupt line T ype RW RW RW RW RW RW RW RW Default 11111111 Register: Interrupt line Offset: 3Ch T ype: Read/Write Default: FFh T able 7?[...]

7−1 1 7.16 Minimum Grant and Maximum Latency Register The minimum grant and maximum latency register communicates to the system the desired setting of bits 15−8 in the latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 7.6). If a serial EEPROM is detected, then the contents of this registe[...]

7−12 7.18 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item. See T able 7−15 for a complete description of the register contents. Bit 15 14 13 12 11 1 0 9876543210 Name Capability ID and next item pointer T [...]

7−13 7.19 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the PCI7x21/PCI7x1 1 controller related to PCI power management. See T able 7−16 for a complete description of the register contents. Bit 15 14 13 12 11 1 0 9876543210 Name Power management capabilities T ype R U RRRRRRRRRRR[...]

7−14 7.20 Power Management Control and Status Register Th e power management control and status register implements the control and status of the PCI power-management function. This register is not affected by the internally generated reset caused by the transition from the D3 hot to D0 state. See T able 7−17 for a complete description of the r[...]

7−15 7.22 PCI PHY Control Register The PCI PHY control register provides a method for enabling the PHY CNA output. See T able 7−19 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name PCI PHY control T ype RRRRRRRRRRRRRRRR Default 0000000000000000 Bit 15 14 13 12 11 1 0 9876543210 Name PC[...]

7−16 7.23 PCI Miscellaneous Configuration Register The PCI miscellaneous configuration register provides miscellaneous PCI-related configuration. See T able 7−20 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name PCI miscellaneous configuration T ype RRRRRRRRRRRRRRRR Default 00000000000[...]

7−17 T able 7−20. PCI Miscellaneous Configuration Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 1 ‡ DISABLE_ PCIGA TE RW When bit 1 is set to 1, the internal PCI clock runs identically with the chip input. This is a test feature only and must be cleared to 0 (all applications). 0 ‡ KEEP_PCLK RW When bit 0 is set to 1, the[...]

7−18 T able 7−21. Link Enhancement Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 11 RSVD R Reserved. Bit 1 1 returns 0 when read. 10 ‡ enab_mpeg_ts RW Enable MPEG CIP timestamp enhancement. When bit 9 is set to 1, the enhancement is enabled for MPEG CIP transmit streams (FMT = 20h). The default value for this bit is[...]

7−19 7.26 GPIO Control Register The GPIO control register has the control and status bits for GPIO0, GPIO1, GPIO2, and GPIO3 ports. Upon reset, GPIO0 and GPIO1 default to bus manager contender (BMC) and link power status terminals, respectively . The BMC terminal can be configured as GPIO0 by setting bit 7 (DISABLE_BMC) to 1. The LPS terminal can[...]

7−20 T able 7−23. GPIO Control Register Description (Continued) BIT SIGNAL TYPE FUNCTION 12 GPIO_ENB1 R/W GPIO1 enable control. When bit 15 (DISABLE_LPS) is set to 1, this bit controls the output enable for GPIO1. 0 = High-impedance output (default) 1 = Output is enabled 1 1−9 RSVD R Reserved. Bits 1 1−9 return 0s when read. 8 GPIO_DA T A1 [...]

8−1 8 OHCI Registers The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a 2K-byte region of memory pointed to by the OHCI base address register at of fset 10h in PCI configuration space (see Section 7.8). These registers are the primary interface for controlling the PCI7x21/PCI7x1 1 IEEE 139[...]

8−2 T able 8−1. OHCI Register Map (Continued) DMA CONTEXT REGISTER NAME ABBREVIA TION OFFSET Self-ID Reserved — 60h Self-ID buffer pointer SelfIDBuffer 64h Self-ID count SelfIDCount 68h Reserved — 6Ch — Isochronous receive channel mask high IRChannelMaskHiSet 70h Isochronous receive channel mask high IRChannelMaskHiClear 74h Isochronous r[...]

8−3 T able 8−1. OHCI Register Map (Continued) DMA CONTEXT REGISTER NAME ABBREVIA TION OFFSET Asynchronous context control ContextControlSet 180h Asynchronous Asynchronous context control ContextControlClear 184h Asynchronous Request T ransmit Reserved — 188h Request T ransmit [ A TRQ ] Asynchronous context command pointer CommandPtr 18Ch [ A [...]

8−4 8.1 OHCI V ersion Register Th e OHCI version register indicates the OHCI version support and whether or not the serial EEPROM is present. See T able 8−2 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name OHCI version T ype R R R R R R R RU R R R R R R R R Default 0000000 X 00000001 [...]

8−5 8.2 GUID ROM Register The GUID ROM register accesses the serial EEPROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI version register at OHCI offset 00h (see Section 8.1) is set to 1. See T able 8−3 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name GUID ROM T ype RSU R R[...]

8−6 8.3 Asynchronous T ransmit Retries Register The asynchronous transmit retries register indicates the number of times the PCI7x21/PCI7x1 1 controller attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See T able 8−4 for a complete description of the register contents. Bit 31 30 29 [...]

8−7 8.5 CSR Compare Register The CSR compare register accesses the bus management CSR registers from the host through compare-swap operations. This register contains the data to be compared with the existing value of the CSR resource. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CSR compare T ype RRRRRRRRRRRRRRRR Default XXXXXXXXXXXXX[...]

8−8 8.7 Configuration ROM Header Register The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset FFFF F000 0400h. See T able 8−6 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Configuration ROM header T ype RW RW RW RW RW RW [...]

8−9 8.9 Bus Options Register The bus options register externally maps to the second quadlet of the Bus_Info_Block. See T able 8−7 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Bus options T ype RW RW RW RW RW R R R RW RW RW RW RW RW RW RW Default X X X X 0 0 0 0 X X X X X X X X Bit[...]

8−10 8.10 GUID High Register The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the third quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes to 0s on a system (hardware) reset, which is an illegal GUID value. If a serial EEPROM is[...]

8−1 1 8.12 Configuration ROM Mapping Register The configuration ROM mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node. See T able 8−8 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Configuration RO[...]

8−12 8.14 Posted Write Address High Register Th e posted write address high register communicates error information if a write request is posted and an error occurs while writing the posted data packet. See T able 8−10 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Posted write addr[...]

8−13 8.16 Host Controller Control Register The host controller control set/clear register pair provides flags for controlling the PCI7x21/PCI7x1 1 controller . See T able 8−1 1 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Host controller control T ype RSU RSC RSC R R R R R R RSC R[...]

8−14 T able 8−1 1. Host Controller Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 22 aPhyEnhanceEnable RSC When bits 23 (programPhyEnable) and 17 (linkEnable) are 1, the OHCI driver can set bit 22 to 1 to use all IEEE 1394a-2000 enhancements. When bit 23 (programPhyEnable) is cleared to 0, the software does not change [...]

8−15 8.18 Self-ID Count Register The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-ID packet errors, and keeps a count of the self-ID data in the self-ID buffer . See T able 8−12 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16[...]

8−16 8.19 Isochronous Receive Channel Mask High Register The isochronous receive channel mask high set/clear register enables packet receives from the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of the isochronous receive channel mask high register . See T able 8−13 for a complet[...]

8−17 T able 8−13. Isochronous Receive Channel Mask High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 6 isoChannel38 RSC When bit 6 is set to 1, the controller is enabled to receive from isochronous channel number 38. 5 isoChannel37 RSC When bit 5 is set to 1, the controller is enabled to receive from isochronous channel numb[...]

8−18 8.21 Interrupt Event Register The interrupt event set/clear register reflects the state of the various PCI7x21/PCI7x1 1 interrupt sources. The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register . The only mechanism to clear a bit in this regist[...]

8−19 T able 8−15. Interrupt Event Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 22 cycleLost RSCU A lost cycle is indicated when no cycle_start packet is sent or received between two successive cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately follow the first subaction gap after [...]

8−20 8.22 Interrupt Mask Register The interrupt mask set/clear register enables the various PCI7x21/PCI7x1 1 interrupt sources. Reads from either the set register or the clear register always return the contents of the interrupt mask register . In all cases except masterIntEnable (bit 31) and vendorSpecific (bit 30), the enables for each interrup[...]

8−21 T able 8−16. Interrupt Mask Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 18 regAccessFail RSC When this bit and bit 18 (regAccessFail) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this register-access-failed interrupt mask enables interrupt generation. 17 busReset RSC When this[...]

8−22 8.23 Isochronous T ransmit Interrupt Event Register The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* command completes and its interrupt bits are set to 1. Upon determining th[...]

8−23 8.24 Isochronous T ransmit Interrupt Mask Register The isochronous transmit interrupt mask set/clear register enables the isochTx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register . In all cases the enables for each [...]

8−24 8.25 Isochronous Receive Interrupt Event Register The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes and its interrupt bits are set to 1. Upon determining that the iso[...]

8−25 8.26 Isochronous Receive Interrupt Mask Register The isochronous receive interrupt mask set/clear register enables the isochRx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous receive interrupt mask register . In all cases the enables for each inte[...]

8−26 8.28 Initial Channels A vailable High Register The initial channels available high register value is loaded into the corresponding bus management CSR register on a system (hardware) or software reset. See T able 8−20 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Initial channe[...]

8−27 8.30 Fairness Control Register The fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval. See T able 8−22 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Fairness cont[...]

8−28 8.31 Link Control Register The link control set/clear register provides the control flags that enable and configure the link core protocol portions of the PCI7x21/PCI7x1 1 controller . It contains controls for the receiver and cycle timer . See T able 8−23 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 [...]

8−29 8.32 Node Identification Register The node identification register contains the address of the node on which the OHCI-L ynx  chip resides, and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15−6) and the NodeNumber field (bits 5−0) is referred to as the node ID. See T able 8−24 for a comp[...]

8−30 8.33 PHY Layer Control Register The PHY layer control register reads from or writes to a PHY register . See T able 8−25 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name PHY layer control T ype RU R R R RU RU RU RU RU RU RU RU RU RU RU RU Default 0000000000000000 Bit 15 14 13 12 1[...]

8−31 8.34 Isochronous Cycle Timer Register The isochronous cycle timer register indicates the current cycle number and offset. When the PCI7x21/PCI7x1 1 controller is cycle master , this register is transmitted with the cycle start message. When the PCI7x21/PCI7x1 1 controller is not cycle master , this register is loaded with the data field in a[...]

8−32 8.35 Asynchronous Request Filter High Register The asynchronous request filter high set/clear register enables asynchronous receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for either the physical request context or the ARRQ context, the source node ID is examined. If the bit corresponding to th[...]

8−33 T able 8−27. Asynchronous Request Filter High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 18 asynReqResource50 RSC If bit 18 is set to 1 for local bus node number 50, asynchronous requests received by the controller from that node are accepted. 17 asynReqResource49 RSC If bit 17 is set to 1 for local bus node number 49[...]

8−34 8.36 Asynchronous Request Filter Low Register The asynchronous request filter low set/clear register enables asynchronous receive requests on a per-node basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to the asynchronous request filter high register . See T able 8−28 for a c[...]

8−35 8.37 Physical Request Filter High Register Th e physical request filter high set/clear register enables physical receive requests on a per-node basis, and handles th e upper node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the ARRQ registers, then the comparison is done again wit[...]

8−36 T able 8−29. Physical Request Filter High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 18 physReqResource50 RSC If bit 18 is set to 1 for local bus node number 50, physical requests received by the controller from that node are handled through the physical request context. 17 physReqResource49 RSC If bit 17 is set to 1 [...]

8−37 8.38 Physical Request Filter Low Register The physical request filter low set/clear register enables physical receive requests on a per-node basis, and handles the lower node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the asynchronous request filter registers, then the node ID c[...]

8−38 8.40 Asynchronous Context Control Register The asynchronous context control set/clear register controls the state and indicates status of the DMA context. See T able 8−31 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Asynchronous context control T ype R RRRRRRRRRRRRRRR Default[...]

8−39 8.41 Asynchronous Context Command Pointer Register The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the PCI7x21/PCI7x1 1 controller accesses when software enables the context by setting bit 15 (run) in the asynchronous context control register (see Section 8.40) to 1. See [...]

8−40 8.42 Isochronous T ransmit Context Control Register The isochronous transmit context control set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, … , 7). See T able 8−33 for a complete description of [...]

8−41 8.43 Isochronous T ransmit Context Command Pointer Register The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the PCI7x21/PCI7x1 1 controller accesses when software enables an isochronous transmit context by setting bit 15 (run) in the isochronous transmit context c[...]

8−42 T able 8−34. Isochronous Receive Context Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 29 cycleMatchEnable RSCU When bit 29 is set to 1 and the 13-bit cycleMatch field (bits 24−12) in the isochronous receive context match register (See Section 8.46) matches the 13-bit cycleCount field in the cycleStart packet, [...]

8−43 8.45 Isochronous Receive Context Command Pointer Register The isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the PCI7x21/PCI7x1 1 controller accesses when software enables an isochronous receive context by setting bit 15 (run) in the isochronous receive context contro[...]

8−44 8.46 Isochronous Receive Context Match Register The isochronous receive context match register starts an isochronous receive context running on a specified cycle number , filters incoming isochronous packets based on tag values, and waits for packets with a specified sync value. The n value in the following register addresses indicates the c[...]

9−1 9 TI Extension Registers Th e TI extension base address register provides a method of accessing memory-mapped TI extension registers. See Section 7.9, TI Extension Base Address Register , for register bit field details. See T able 9−1 for the TI extension register listing. T able 9−1. TI Extension Register Map REGISTER NAME OFFSET Reserve[...]

9−2 9.2 Isochronous Receive Digital Video Enhancements Th e DV frame sync and branch enhancement provides a mechanism in buffer-fill mode to synchronize 1394 DV data that is received in the correct order to DV frame-sized data buffers described by several INPUT_MORE descriptors (see 1394 Open Host Controller Interface Specification , Release 1.1)[...]

9−3 T able 9−2. Isochronous Receive Digital Video Enhancements Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 7−6 RSVD R Reserved. Bits 7 and 6 return 0s when read. 5 DV_Branch1 RSC When bit 5 is set to 1, the isochronous receive context 1 synchronizes reception to the DV frame start tag in bufferfill mode if input_more.b = [...]

9−4 9.4 Link Enhancement Register This register is a memory-mapped set/clear register that is an alias of the link enhancement control register at PCI offset F4h. These bits may be initialized by software. Some of the bits may also be initialized by a serial EEPROM, if one is present, as noted in the bit descriptions below . If the bits are to be[...]

9−5 T able 9−3. Link Enhancement Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 9 RSVD R Reserved. Bit 9 returns 0 when read. 8 ‡ enab_dv_ts RW Enable DV CIP timestamp enhancement. When bit 8 is set to 1, the enhancement is enabled for DV CIP transmit streams (FMT = 00h). The default value for this bit is 0. 7 ‡ enab_unfai[...]

9−6[...]

10−1 10 PHY Register Configuration There are 16 accessible internal registers in the PCI7x21/PCI7x1 1 controller . The configuration of the registers at addresses 0h through 7h (the base registers) is fixed, whereas the configuration of the registers at addresses 8h through Fh (the paged registers) is dependent upon which one of eight pages, numb[...]

10−2 T able 10−2. Base Register Field Descriptions FIELD SIZE TYPE DESCRIPTION Physical ID 6 R This field contains the physical address ID of this node determined during self-ID. The physical ID is invalid after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status transfer . R 1 R Root. This bit indicates tha[...]

10−3 T able 10−2. Base Register Field Descriptions (Continued) FIELD SIZE TYPE DESCRIPTION ISBR 1 R/W Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY layer to initiate a short (1.3 µ s) arbitrated bus reset at the next opportunity . This bit is cleared to 0 by a bus reset. NOTE: Legacy IEEE Std 1394-1995 compliant[...]

10−4 10.2 Port Status Register Th e port status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. T a ble 10−3 shows the configuration of the port status page registers and T able [...]

10−5 T able 10−4. Page 0 (Port Status) Register Field Descriptions (Continued) FIELD SIZE TYPE DESCRIPTION Int_enable 1 RW Port event interrupt enable. When the Int_enable bit is set to 1, a port event on the selected port sets the port event interrupt (Port_event) bit and notifies the link. This bit is cleared to 0 by a system (hardware) reset[...]

10−6 10.4 V endor-Dependent Register The vendor-dependent page provides access to the special control features of the PCI7x21/PCI7x1 1 controller , as well as to configuration and status information used in manufacturing test and debug. This page is selected by writing 7 to the Page_Select field in base register 7. T able 10−7 shows the configu[...]

10−7 10.5 Power-Class Programming The PC0–PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field (bits 21–23) of the transmitted self-ID packet. T able 10−9 shows the descriptions of the various power classes. The default power-class value is loaded following a system (hardware) reset, but is ove[...]

10−8[...]

1 1−1 1 1 Flash Media Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x1 1 flash media controller interface. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state[...]

1 1−2 1 1.1 V endor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to T exas Instruments is 104Ch. Bit 15 14 13 12 11 1 0 9876543210 Name V endor ID T ype RRRRRRRRRRRRRRRR Default 0001000001001100 Register: V endor ID Offset: 00h T ype: Read-on[...]

1 1−3 1 1.3 Command Register The command register provides control over the PCI7x21/PCI7x1 1 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification , as seen in the following bit descriptions. See T able 1 1−2 for a complete description of the register contents. Bit 15 14 13 12 11 1 0 9876543210[...]

1 1−4 1 1.4 Status Register The status register provides device information to the host system. All bit functions adhere to the definitions in the PCI Local Bus Specification , as seen in the following bit descriptions. Bits in this register may be read normally . A bit in the status register is reset when a 1 is written to that bit location; a 0[...]

1 1−5 1 1.5 Class Code and Revision ID Register The class code and revision ID register categorizes the base class, subclass, and programming interface of the function. The base class is 01h, identifying the controller as a mass storage controller . The subclass is 80h, identifying th e function as other mass storage controller , and the programm[...]

1 1−6 1 1.7 Header T ype and BIST Register The header type and built-in self-test (BIST) register indicates the flash media controller PCI header type and no built-in self-test. See T able 1 1−6 for a complete description of the register contents. Bit 15 14 13 12 11 1 0 9876543210 Name Header type and BIST T ype RRRRRRRRRRRRRRRR Default 0000000[...]

1 1−7 1 1.9 Subsystem V endor Identification Register The subsystem identification register , used for system and option card identification purposes, may be required for certain operating systems. This read-only register is initialized through the EEPROM and can be written through the subsystem access register at PCI offset 50h (see Section 1 1.[...]

1 1−8 1 1.12 Interrupt Line Register The interrupt line register is programmed by the system and indicates to the software which interrupt line the flash media interface has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not yet been assigned to the function. Bit 7 6 5 4 3 2 1 0 Name Interrupt lin[...]

1 1−9 1 1.14 Minimum Grant Register The minimum grant register contains the minimum grant value for the flash media controller core. B i t 76543210 Name Minimum grant T ype RU RU RU RU RU RU RU RU Default 00000111 Register: Minimum grant Offset: 3Eh T ype: Read/Update Default: 07h T able 1 1−9. Minimum Grant Register Description BIT FIELD NAME [...]

1 1−10 1 1.16 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item. See T able 1 1−1 1 for a complete description of the register contents. Bit 15 14 13 12 11 1 0 9876543210 Name Capability ID and next item poi[...]

1 1−1 1 1 1.17 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the flash media controller related to PCI power management. See T able 1 1−12 for a complete description of the register contents. Bit 15 14 13 12 11 1 0 9876543210 Name Power management capabilities T ype R U RRRRRRRRR[...]

1 1−12 1 1.18 Power Management Control and Status Register The power management control and status register implements the control and status of the flash media controller . This register is not af fected by the internally generated reset caused by the transition from the D3 hot to D0 state. See T able 1 1−13 for a complete description of the r[...]

1 1−13 1 1.20 Power Management Data Register The power management bridge support extension register provides extended power-management features not applicable to the flash media controller; thus, it is read-only and returns 0 when read. B i t 76543210 Name Power management data T ype RRRRRRRR Default 00000000 Register: Power management data Offse[...]

1 1−14 1 1.22 Subsystem Access Register The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 2Ch and 2Eh, respectively . See T able 1 1−15 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Subsystem access T ype [...]

1 1−15 1 1.23 Diagnostic Register This register programs the M and N inputs to the PLL and enables the diagnostic modes. The default values for M and N in this register set the PLL output to be 80 MHz, which is divided to get the 40 MHz and 20 MHz needed by th e flash media cores. See T able 1 1−16 for a complete description of the register con[...]

1 1−16[...]

12−1 12 SD Host Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x1 1 SD host controller interface. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for each [...]

12−2 12.1 V endor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to T exas Instruments is 104Ch. Bit 15 14 13 12 11 1 0 9876543210 Name V endor ID T ype RRRRRRRRRRRRRRRR Default 0001000001001100 Register: V endor ID Offset: 00h T ype: Read-only[...]

12−3 12.3 Command Register The command register provides control over the SD host controller interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification , as seen in the following bit descriptions. See T able 12−2 for a complete description of the register contents. Bit 15 14 13 12 11 1 0 9876543210 [...]

12−4 12.4 Status Register The status register provides device information to the host system. All bit functions adhere to the definitions in the PCI Local Bus Specification , as seen in the following bit descriptions. Bits in this register may be read normally . A bit in the status register is reset when a 1 is written to that bit location; a 0 w[...]

12−5 12.5 Class Code and Revision ID Register The class code and revision ID register categorizes the base class, subclass, and programming interface of the function. The base class is 08h, identifying the controller as a generic system peripheral. The subclass is 05h, identifying the function as an SD host controller . The programming interface [...]

12−6 12.6 Latency Timer and Class Cache Line Size Register The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size an d the latency timer associated with the SD host controller . See T able 12−5 for a complete description of the register contents. Bit 15 14 13 12 11 1 0 9876543210 Name [...]

12−7 12.8 SD Host Base Address Register The SD host base address register specifies the base address of the memory-mapped interface registers for each standard SD host socket. The size of each base address register (BAR) is 256 bytes. The number of BARs is dependent on the number of SD sockets in the implementation See T able 12−7 for a complet[...]

12−8 12.10 Subsystem Identification Register The subsystem identification register , used for system and option card identification purposes, may be required for certain operating systems. This read-only register is initialized through the EEPROM and can be written through the subsystem access register at PCI offset 8Ch (see Section 12.23). All b[...]

12−9 12.13 Interrupt Pin Register This register decodes the interrupt select inputs and returns the proper interrupt value based on T able 12−8, indicating that the SD host controller uses an interrupt. If one of the USE_INTx terminals is asserted, the interrupt select bits are ignored, and this register returns the interrupt value for the high[...]

12−10 12.15 Maximum Latency Register The maximum latency register contains the maximum latency value for the SD host controller core. Bit 7 6 5 4 3 2 1 0 Name Maximum latency T ype RU RU RU RU RU RU RU RU Default 00000100 Register: Maximum latency Offset: 3Fh T ype: Read/Update Default: 04h T able 12−10. Maximum Latency Register Description BIT[...]

12−1 1 12.17 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item. See T able 12−12 for a complete description of the register contents. Bit 15 14 13 12 11 1 0 9876543210 Name Capability ID and next item pointe[...]

12−12 12.18 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the SD host controller related to PCI power management. See T able 12−13 for a complete description of the register contents. Bit 15 14 13 12 11 1 0 9876543210 Name Power management capabilities T ype R U RRRRRRRRRRRRRRR D[...]

12−13 12.19 Power Management Control and Status Register The power management control and status register implements the control and status of the SD host controller . This register is not affected by the internally generated reset caused by the transition from the D3 hot to D0 state. See T able 12−14 for a complete description of the register [...]

12−14 12.21 Power Management Data Register The power management bridge support extension register provides extended power-management features not applicable to the SD host controller; thus, it is read-only and returns 0 when read. Bit 7 6 5 4 3 2 1 0 Name Power management data T ype RRRRRRRR Default 00000000 Register: Power management data Offset[...]

12−15 12.23 Subsystem Access Register The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 2Ch and 2Eh, respectively . See T able 12−16 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Subsystem access T ype RW [...]

12−16 12.25 Slot 0 3.3-V Maximum Current Register This register is a read/write register and the contents of this register are aliased to the 3_3_MAX_CURRENT field in the slot 0 maximum current capabilities register at offset 48h in the SD host standard registers. This register is a GRST only register . Bit 7 6 5 4 3 2 1 0 Name Slot 0 3.3-V maxim[...]

12−17 12.28 Slot 3 3.3-V Maximum Current Register This register is a read/write register and the contents of this register are aliased to the 3_3_MAX_CURRENT field in the slot 3 maximum current capabilities register at offset 48h in the SD host standard registers. This register is a GRST only register . If slot 3 is not implemented, this register[...]

12−18[...]

13−1 13 Smart Card Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x1 1 Smart Card controller interface. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for[...]

13−2 13.1 V endor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to T exas Instruments is 104Ch. Bit 15 14 13 12 11 1 0 9876543210 Name V endor ID T ype RRRRRRRRRRRRRRRR Default 0001000001001100 Register: V endor ID Offset: 00h T ype: Read-only[...]

13−3 13.3 Command Register The command register provides control over the Smart Card controller interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification , as seen in the following bit descriptions. The SERR_EN and PERR_EN enable bits in this register are internally wired-OR between other functions, [...]

13−4 13.4 Status Register The status register provides device information to the host system. All bit functions adhere to the definitions in the PCI Local Bus Specification , as seen in the following bit descriptions. Bits in this register may be read normally . A bit in the status register is reset when a 1 is written to that bit location; a 0 w[...]

13−5 13.5 Class Code and Revision ID Register The class code and revision ID register categorizes the base class, subclass, and programming interface of the function. The base class is 07h, identifying the controller as a communication device. The subclass is 80h, identifying th e function as other mass storage controller , and the programming in[...]

13−6 13.7 Header T ype and BIST Register The header type and built-in self-test (BIST) register indicates the Smart Card controller PCI header type and no built-in self-test. See T able 13−6 for a complete description of the register contents. Bit 15 14 13 12 11 1 0 9876543210 Name Header type and BIST T ype RRRRRRRRRRRRRRRR Default 00000000100[...]

13−7 13.9 Smart Card Base Address Register 1−4 Each socket has its own base address register . For example, a device supports three Smart Card sockets uses three base address registers, BA1 (socket 0), BA2 (socket 1) and BA3 (socket 2). These registers are used by this function to determine where to forward a memory transaction to the Smart Car[...]

13−8 13.1 1 Subsystem Identification Register This register is read-update and can be modified through the subsystem ID alias register . This register has no effect to the functionality . Default value is 8035h. This default value complies with the WLP (Windows Logo Program) requirements without BIOS or EEPROM configuration. All bits in this regi[...]

13−9 13.14 Interrupt Pin Register This register decodes the interrupt select inputs and returns the proper interrupt value based on T able 13−7, indicating that the Smart Card interface uses an interrupt. If one of the USE_INTx terminals is asserted, the interrupt select bits are ignored, and this register returns the interrupt value for the hi[...]

13−10 13.16 Maximum Latency Register The maximum latency register contains the maximum latency value for the Smart Card controller core. Bit 7 6 5 4 3 2 1 0 Name Maximum latency T ype RU RU RU RU RU RU RU RU Default 00000000 Register: Maximum latency Offset: 3Fh T ype: Read/Update Default: 00h T able 13−9. Maximum Latency Register Description B[...]

13−1 1 13.18 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the Smart Card controller related to PCI power management. See T able 13−1 1 for a complete description of the register contents. Bit 15 14 13 12 11 1 0 9876543210 Name Power management capabilities T ype R U RRRRRRRRRRRR[...]

13−12 13.19 Power Management Control and Status Register The power management control and status register implements the control and status of the Smart Card controller . This register is not af fected by the internally generated reset caused by the transition from the D3 hot to D0 state. See T able 13−12 for a complete description of the regis[...]

13−13 13.21 Power Management Data Register The power management bridge support extension register provides extended power-management features not applicable to the Smart Card controller; thus, it is read-only and returns 0 when read. B i t 76543210 Name Power management data T ype RRRRRRRR Default 00000000 Register: Power management data Offset: [...]

13−14 13.23 Subsystem ID Alias Register The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 2Ch and 2Eh, respectively . See T able 13−14 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Subsystem ID alias T ype[...]

13−15 13.25 Smart Card Configuration 1 Register BIOS or EEPROM configure system dependent Smart Card interface information through this register . Information of this register can be read from the Smart Card configuration 1 alias register in the Smart Card global control register set. The software utilizes this information and adjusts the softwar[...]

13−16 T able 13−15. Smart Card Configuration 1 Register Description BIT FIELD NAME TYPE DESCRIPTION 31−28 SCRTCH_P AD RW Scratch pad 27 CLASS_B_SKT3 R Socket 3 Class B Smart Card support. Since socket 3 is not implemented in the controller , this bit is a read-only 0. 26 CLASS_B_SKT2 RW Socket 2 Class B Smart Card support. Since socket 2 is n[...]

13−17 13.26 Smart Card Configuration 2 Register BIOS or EEPROM configure system dependent Smart Card interface information through this register . Information of this register can be read from the Smart Card configuration 2 alias in the Smart Card global control register set. The software utilizes this information and adjusts the software and fir[...]

13−18[...]

14−1 14 Electrical Characteristics 14.1 Absolute Maximum Ratings Over Operating T emperature Ranges † Supply voltage range, VR_PORT −0.2 V to 2.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A VDD −0.3 V to 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

14−2 Recommended Operating Conditions (continued) OPERA TION MIN NOM MAX UNIT PCI k 3.3 V 0.5 V CCP V CCP PCI k 5 V 2 V CCP 3.3 V CardBus 0.475 V CC(A/B) V CC(A/B) V IH † High-level input PC Card 3.3 V 16-bit 2 V CC(A/B) V V IH † High-level input voltage PC Card 5 V 16-bit 2.4 V CC(A/B) V voltage PC(0−2) 0.7 V CC V CC Miscellaneous ‡ 2 V [...]

14−3 Recommended Operating Conditions (continued) OPERA TION MIN NOM MAX UNIT S100 operation ± 1.08 Receive input jitter TP A, TPB cable inputs S200 operation ± 0.5 ns Receive input jitter TP A, TPB cable inputs S400 operation ± 0.315 ns S100 operation ± 0.8 Receive input skew Between TP A and TPB cable inputs S200 operation ± 0.55 ns Receiv[...]

14−4 14.3 Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted) P ARAMETER TERMINALS OPERA TION TEST CONDITIONS MIN MAX UNIT PCI 3.3 V I OH = −0.5 mA 0.9 V CC PCI 5 V I OH = −2 mA 2.4 V OH High-level output voltage 3.3 V CardBus I OH = −0.15 mA 0.9 V CC V V OH High-level output voltage PC Card 3.3 V 16-bi[...]

14−5 14.4 Electrical Characteristics Over Recommended Ranges of Operating Conditions (unless otherwise noted) 14.4.1 Device P ARAMETER TEST CONDITION MIN MAX UNIT V TH Power status threshold, CPS input † 400-k Ω resistor † 4.7 7.5 V V O TPBIAS output voltage At rated I O current 1.665 2.015 V I I Input current (PC0−PC2 inputs) V CC = 3.6 [...]

14−6 14.5 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply V oltage and Operating Free-Air T emperature P ARAMETER AL TERNA TE SYMBOL TEST CONDITIONS MIN MAX UNIT t c Cycle time, PCLK t cyc 30 ns t w(H) Pulse duration (width), PCLK high t high 11 ns t w(L) Pulse duration (width), PCLK low t low 11 ns t r , t f Slew rate, PCLK[...]

15−1 15 Mechanical Information The PCI7x21/PCI7x1 1 device is available in the 288-terminal MicroStar BGA  package (GHK) or the 288-terminal lead (Pb atomic number 82) free MicroStar BGA  package (ZHK). The following figure shows the mechanical dimensions for the GHK package. The GHK and ZHK packages are mechanically identical; therefore, o[...]

15−2[...]

PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) PCI7411GHK ACTIVE BGA GHK 288 1 TBD Call TI Level-3-220C-168 HR PCI7411ZHK ACTIVE BGA MI CROSTA R ZHK 288 1 Green (RoHS & no Sb/Br) Call TI Level-3-260C-168HRS PCI7421GHK ACTIVE BGA GHK 288 90 TBD Call [...]