Epson S1C33210 инструкция обслуживания

MF1517-01 T echnical Manual CMOS 32 - BIT SINGLE CHIP MICROCOMPUTER S1C33210 PRODUCT PART S1C33210 FUNCTION PART S1C33210[...]

NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its appl[...]

S1C33210 Technical Manual This manual describes the hardware specifications of the Seiko Epson original 32-bit microcomputer S1C 33210. S1C33210 PRODUCT PART Describes the hardware specifications of the S1C33210 except for details of the peripheral circuits. S1C33210 FUNCTION PART Describes details of all the peripheral circuit blocks for the S1C33[...]

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TABLE OF CONTENTS EPSON i S1C33210 PRODUCT PART Table of Contents 1 Outline ..................................................................................................................... A -1 1.1 Features ..........................................................................................................................................[...]

TABLE OF CONTENTS ii EPSON Appendix A <Reference> External Device Interface Timings ......................................A -9 2 A.1 DRAM (70ns) ....................................................................................................................................................A - 9 3 A.2 DRAM (60ns) ...........................[...]

TABLE OF CONTENTS EPSON iii S1C33210 FUNCTION PART Table of Contents I OUTLINE I-1 INTRODUCTION ............................................................................................... B -I-1-1 I-2 BLOCK DIAGRAM ............................................................................................ B -I-2-1 I- 3 L IS T O F PI NS .......[...]

TABLE OF CONTENTS iv EPSON Bus Speed Mode ............................................................................................................................... B-II-4-17 B u s C l o c k O u t p u t ............................................................................................................... ................B -II-4-17 Bus[...]

TABLE OF CONTENTS EPSON v III PERIPHERAL BLOCK III-1 INTRODUCTION ............................................................................................ B- II I- 1 -1 III-2 PRESCALER ................................................................................................. B- II I- 2- 1 C o n f i g u r a t i o n o f P r e s c a l e r .[...]

TABLE OF CONTENTS vi EPSON III-7 CLOCK TIMER ...............................................................................................B -III-7-1 C o n f i g u r a t i o n o f C l o c k T i m e r ................................................................................................... ...................... B -III-7-1 Control and Ope[...]

TABLE OF CONTENTS EPSON vii Overview ...............................................................................................................................................B -III-10-8 PDC Communications Control and Operation ....................................................................B -III-10-10 PHS Communications Mode ............[...]

TABLE OF CONTENTS viii EPSON IV ANALOG BLOCK IV-1 INTRODUCTION ............................................................................................ B- IV - 1- 1 IV-2 A/D CONVERTER .......................................................................................... B- I V- 2- 1 Features and Structure of A/D Converter ..................[...]

S1C33210 PRODUCT PART[...]

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1 OUTLINE S1C33210 PRODUCT PAR T EPSON A- 1 1 Outline The S1C33210 is a Seiko Epson original 32-bit microcomputer. It features high speed, low power consumption, and low-volt age operation, and is ideal for portable products that require high-speed data processing. The S1C33210 consists of an S1C33000 32-bit RISC type CPU as its core, peripheral ci[...]

1 OUTLINE A- 2 EPSON S1C33210 PRODUCT PA RT General-purpose input Sh ared with the I/O pins for internal peripheral circuits and output ports: Input port 7 bits I/O port 27 bits Mobile access interfaces One PHS, PDC, and HDLC channel each External bus interface BCU (bus control unit) built-in • 24-bit address bus (internal 28-bit processing) • [...]

1 OUTLINE S1C33210 PRODUCT PAR T EPSON A- 3 1 .2 Block Diagram V DD V SS A[23:0] D[15:0] #RD #WRL/#WR/#WE #WRH/#BSH #HCAS #LCAS #CE10EX #CE[9:4] #WAIT(P30) #DRD(P20) #DWE(P21) #GAAS(P21) #GARD(P31) OSC3 OSC4 PLLS[1:0] PLLC OSC1 OSC2 FOSC1(P14) #DMAREQx(K50, K51) #DMAACKx(P32, P33) #DMAENDx(P15, P16) AD0 – 3(K60 – 63) #ADTRG(K52) AV DD K50 – 5[...]

1 OUTLINE A- 4 EPSON S1C33210 PRODUCT PA RT 1 .3 Pin Description 1 .3 .1 Pin Layout Diagram (plastic package) QFP15-128pin 65 96 33 64 INDEX 32 1 128 97 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin name P26/TM4/SOUT2 P27/TM5/SIN2 V SS BCLK P00/SIN0 P01/SOUT0 D15 V DD P03/#SRDY0 D14 P31/#BUSGET/#GARD[...]

1 OUTLINE S1C33210 PRODUCT PAR T EPSON A- 5 1 .3 .2 Pin Functions Table 1.3.1 List of Pins for Power Supply System Pin name Pin No. I/O Pull-up Function QFP15-128 V DD 8, 27, 47, 74, 93, 111 –– Power supply (+) V SS 3, 22, 39, 54, 67, 90, 102, 104 – (104 Pull- down) Power supply (-); GND AV DD 30 –– Analog system power supply (+); AV DD =[...]

1 OUTLINE A- 6 EPSON S1C33210 PRODUCT PA RT Pin name Pin No. I/O Pull-up Function QFP15-128 #CE4 #CE11 #CE11&12 35 O – #CE4: Area 4 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00" (default) #CE11: Area 11 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01" * When CEFUNC[1:0] = "1x", this pin outputs #CE11+#[...]

1 OUTLINE S1C33210 PRODUCT PAR T EPSON A- 7 Table 1.3.3 List of Pins for HSDMA Con trol Signals Pin name Pin No. I/O Pull-up Function QFP15-128 K50 #DMAREQ0 19 I Pull-up K50: Input port when CFK50(D0/0x402C0) = "0" (default) #DMAREQ0: HSDMA Ch. 0 request input when CFK50(D0/0x402C0) = "1" K51 #DMAREQ1 23 I Pull-up K51: Input por[...]

1 OUTLINE A- 8 EPSON S1C33210 PRODUCT PA RT Table 1.3.4 List of Pins for Internal Peripheral Circuits Pin name Pin No. I/O Pull-up Function QFP15-128 K52 #ADTRG 33 I Pull-up K52: Input port when CFK52(D2/0x402C0) = "0" (default) #ADTRG: A/D converter trigger input when CFK52(D2/0x402C0) = "1" K60 AD0 32 I – K60: Input port whe[...]

1 OUTLINE S1C33210 PRODUCT PAR T EPSON A- 9 Pin name Pin No. I/O Pull-up Function QFP15-128 P13 EXCL3 T8UF3 DPCO 124 I/O – P13: I/O port when CFP13(D3/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0" EXCL3: 16-bit timer 3 event counter input when CFP13(D3/0x402D4) = "1", IOC13(D3/0x402D6) = "0" and CFEX 1(D1/0x40[...]

1 OUTLINE A- 10 EPSON S1C33210 PRODUCT PA RT Pin name Pin No. I/O Pull-up Function QFP15-128 DTR 95 O – DTR output * 1 RTS 94 O – RTS output * 1 TXD SOUT3 100 O – TXD: TXD output * 1 when MSEL pin input is at High level SOUT3: SOUT3 output when MSEL pin input is at Low level RI 97 I – RI input * 1 CTS 101 I – CTS input * 1 DCD 108 I – D[...]

2 POWER SUPPLY S1C33210 PRODUCT PAR T EPSON A- 11 2 Po we r Supply This chapter explains the operating voltage of the S1C33210. 2 .1 Power Supply Pins The S1C33210 has the power supply p ins shown in Table 2.1.1. Table 2.1.1 Power Supply Pins Pin name Pin No. Function QFP15-128 V DD 8, 27, 47, 74, 93, 111 Power supply (+) V SS 3, 22, 39, 54, 67, 90[...]

2 POWER SUPPLY A- 12 EPSON S1C33210 PRODUCT PA RT 2 .3 Power Supply for Analog Circuits (AV DD ) The analog power supply pin (AV DD ) is provided separately from the V DD and V DD pins in order that the digital circuits do not affect the analog circuit (A/D converter). The AV DD pin is used to supply an analog power voltage and the V SS pin is used[...]

3 INTERNAL MEMORY S1C33210 PRODUCT PAR T EPSON A- 13 3 Inte rnal Memo ry This chapter explains the internal memory configuration. Figure 3.1 shows the S1C33210 memory map. Areas 18 – 11 Area 10 Areas 9 – 7 Area 6 Area 5 Area 3 Area 2 Area 1 Area 0 0xFFFFFFF 0x1000000 0x0FFFFFF 0x0C00000 0x0BFFFFF 0x0400000 0x03FFFFF 0x0380000 0x037FFFF 0x030000[...]

4 PERIPHERAL CIRCUITS A- 14 EPSON S1C33210 PRODUCT PA RT 4 Pe riphe ral Circuits This chapter lists the built-in peripheral circuits and the I/O memory map. For details of the circuits, refer to the "S1C33210 FUNCTION PART". 4 .1 List of Peripheral Circuits The S1C33210 consists of the C33 Core Block, C33 Peripheral Block, C33 DMA Block a[...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 15 4 .2 I/O Memory Map Table 4.2.1 I/O Memory Map Name Address Register name Bit Function Setting Init. R/W Remarks – P8TPCK5 P8TPCK4 D7–2 D1 D0 reserved 8-bit timer 5 clock selection 8-bit timer 4 clock selection – 0 0 – R/W R/W 0 when being read. θ : selected by Prescaler clock select[...]

4 PERIPHERAL CIRCUITS A- 16 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks – – P16TON3 P16TS32 P16TS31 P16TS30 D7 – 4 D3 D2 D1 D0 reserved 16-bit timer 3 clock control 16-bit timer 3 clock division ratio selection – 0 0 0 0 – R/W R/W 0 when being read. θ : selected by Prescaler clock select[...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 17 Name Address Register name Bit Function Setting Init. R/W Remarks 1 On 0 Off P8TON3 P8TS32 P8TS31 P8TS30 P8TON2 P8TS22 P8TS21 P8TS20 D7 D6 D5 D4 D3 D2 D1 D0 8-bit timer 3 clock control 8-bit timer 3 clock division ratio selection 8-bit timer 2 clock control 8-bit timer 2 clock division ratio [...]

4 PERIPHERAL CIRCUITS A- 18 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks – TCHD5 TCHD4 TCHD3 TCHD2 TCHD1 TCHD0 D7 – 6 D5 D4 D3 D2 D1 D0 reserved Clock timer minute counter data TCHD5 = MSB TCHD0 = LSB – X X X X X X – R/W 0 when being read. 0040155 (B) – 0 to 59 minutes Clock timer minute r[...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 19 Name Address Register name Bit Function Setting Init. R/W Remarks – PTOUT0 PSET0 PTRUN0 D7 – 3 D2 D1 D0 reserved 8-bit timer 0 clock output control 8-bit timer 0 preset 8-bit timer 0 Run/Stop control – 0 – 0 – R/W W R/W 0 when being read. 0 when being read. 0040160 (B) – 1 On 0 Of[...]

4 PERIPHERAL CIRCUITS A- 20 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks – PTOUT3 PSET3 PTRUN3 D7 – 3 D2 D1 D0 reserved 8-bit timer 3 clock output control 8-bit timer 3 preset 8-bit timer 3 Run/Stop control – 0 – 0 – R/W W R/W 0 when being read. 0 when being read. 004016C (B) – 1 On 0 Of[...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 21 Name Address Register name Bit Function Setting Init. R/W Remarks WRWD – D7 D6 – 0 EWD write protection – 0 – R/W – 0 when being read. 0040170 (B) – 1 Write enabled 0 Write-protect Watchdog timer write- protect register – – – EWD – D7 – 2 D1 D0 – Watchdog timer enable [...]

4 PERIPHERAL CIRCUITS A- 22 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks CLKDT1 CLKDT0 PSCON – CLKCHG SOSC3 SOSC1 D7 D6 D5 D4 – 3 D2 D1 D0 System clock division ratio selection Prescaler On/Off control reserved CPU operating clock switch High-speed (OSC3) oscillation On/Off Low-speed (OSC1) osci[...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 23 Name Address Register name Bit Function Setting Init. R/W Remarks 0x0 to 0xFF(0x7F) TXD07 TXD06 TXD05 TXD04 TXD03 TXD02 TXD01 TXD00 D7 D6 D5 D4 D3 D2 D1 D0 Serial I/F Ch.0 transmit data TXD07(06) = MSB TXD00 = LSB X X X X X X X X R/W 7-bit asynchronous mode does not use TXD07. 00401E0 (B) Ser[...]

4 PERIPHERAL CIRCUITS A- 24 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks 0x0 to 0xFF(0x7F) TXD17 TXD16 TXD15 TXD14 TXD13 TXD12 TXD11 TXD10 D7 D6 D5 D4 D3 D2 D1 D0 Serial I/F Ch.1 transmit data TXD17(16) = MSB TXD10 = LSB X X X X X X X X R/W 7-bit asynchronous mode does not use TXD17. 00401E5 (B) Ser[...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 25 Name Address Register name Bit Function Setting Init. R/W Remarks TXEN2 RXEN2 EPR2 PMD2 STPB2 SSCK2 SMD21 SMD20 D7 D6 D5 D4 D3 D2 D1 D0 Ch.2 transmit enable Ch.2 receive enable Ch.2 parity enable Ch.2 parity mode selection Ch.2 stop bit selection Ch.2 input clock selection Ch.2 transfer mode [...]

4 PERIPHERAL CIRCUITS A- 26 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 D7 D6 D5 D4 D3 D2 D1 D0 A/D converted data (low-order 8 bits) ADD0 = LSB 0x0 to 0x3FF (low-order 8 bits) 0 0 0 0 0 0 0 0 R 0040240 (B) A/D conversion result (low- order) register 0x0 to 0[...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 27 Name Address Register name Bit Function Setting Init. R/W Remarks – 0 to 7 0 to 7 – – PP1L2 PP1L1 PP1L0 – PP0L2 PP0L1 PP0L0 D7 D6 D5 D4 D3 D2 D1 D0 reserved Port input 1 interrupt level reserved Port input 0 interrupt level – X X X – X X X – R/W – R/W 0 when being read. 0 when[...]

4 PERIPHERAL CIRCUITS A- 28 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks – 0 to 7 0 to 7 – – PSIO02 PSIO01 PSIO00 – P8TM2 P8TM1 P8TM0 D7 D6 D5 D4 D3 D2 D1 D0 reserved Serial interface Ch.0 interrupt level reserved 8-bit timer 0 – 3 interrupt level – X X X – X X X – R/W – R/W 0 when[...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 29 Name Address Register name Bit Function Setting Init. R/W Remarks – EK1 EK0 EP3 EP2 EP1 EP0 D7 – 6 D5 D4 D3 D2 D1 D0 reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 – – 0 0 0 0 0 0 – R/W R/W R/W R/W R/W R/W 0 when being read. 0040270 (B) 1 Enable[...]

4 PERIPHERAL CIRCUITS A- 30 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks – FK1 FK0 FP3 FP2 FP1 FP0 D7 – 6 D5 D4 D3 D2 D1 D0 reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 – – X X X X X X – R/W R/W R/W R/W R/W R/W 0 when being read. 0040280 (B) 1 Factor[...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 31 Name Address Register name Bit Function Setting Init. R/W Remarks R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.0 Port input 3 Port input 2 Port input 1 Port input 0 0 0 0 0 0 0 0[...]

4 PERIPHERAL CIRCUITS A- 32 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks HSD1S3 HSD1S2 HSD1S1 HSD1S0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 D7 D6 D5 D4 D3 D2 D1 D0 High-speed DMA Ch.1 trigger set-up High-speed DMA Ch.0 trigger set-up 0 0 0 0 0 0 0 0 R/W R/W 0040298 (B) 0 1 2 3 4 5 6 7 8 9 A B C Software trigge[...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 33 Name Address Register name Bit Function Setting Init. R/W Remarks – CP4 CFK52 CFK51 CFK50 D7 – 4 D3 D2 D1 D0 reserved CP4 K52 function selection K51 function selection K50 function selection – – 0 0 0 0 – R/W R/W R/W R/W Undefined when read. Always set to 0. 00402C0 (B) 1 – 0 CP4 [...]

4 PERIPHERAL CIRCUITS A- 34 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks T8CH5S0 SIO3TS0 T8CH4S0 SIO3RS0 SIO2TS0 SIO3ES0 SIO2RS0 SIO2ES0 D7 D6 D5 D4 D3 D2 D1 D0 8-bit timer 5 underflow SIO Ch.3 transmit buffer empty 8-bit timer 4 underflow SIO Ch.3 receive buffer full SIO Ch.2 transmit buffer empty [...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 35 Name Address Register name Bit Function Setting Init. R/W Remarks – SCPK04 SCPK03 SCPK02 SCPK01 SCPK00 D7 – 5 D4 D3 D2 D1 D0 reserved FPK04 input comparison FPK03 input comparison FPK02 input comparison FPK01 input comparison FPK00 input comparison – – 0 0 0 0 0 – R/W R/W R/W R/W R/[...]

4 PERIPHERAL CIRCUITS A- 36 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks – IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10 D7 D6 D5 D4 D3 D2 D1 D0 reserved P16 I/O control P15 I/O control P14 I/O control P13 I/O control P12 I/O control P11 I/O control P10 I/O control – 0 0 0 0 0 0 0 – R/W R/W R/W R/[...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 37 Name Address Register name Bit Function Setting Init. R/W Remarks – CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 CFEX0 D7-6 D5 D4 D3 D2 D1 D0 reserved P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10, P11, P13 port extended function P12, P14 p[...]

4 PERIPHERAL CIRCUITS A- 38 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks – A12SZ A12DF1 A12DF0 – A12WT2 A12WT1 A12WT0 DF – 7 D6 D5 D4 D3 D2 D1 D0 reserved Areas 12 – 11 device size selection Areas 12 – 11 output disable delay time reserved Areas 12 – 11 wait control – – 1 8 bits 0 16[...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 39 Name Address Register name Bit Function Setting Init. R/W Remarks – A6DF1 A6DF0 – A6WT2 A6WT1 A6WT0 – A5SZ A5DF1 A5DF0 – A5WT2 A5WT1 A5WT0 DF – E DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 reserved Area 6 output disable delay time reserved Area 6 wait control reserved Areas 5 – 4 d[...]

4 PERIPHERAL CIRCUITS A- 40 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks 1 Successive 0 Normal – – CEFUNC1 CEFUNC0 CRAS RPRC1 RPRC0 – CASC1 CASC0 – RASC1 RASC0 DF – C DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 reserved reserved #CE pin function selection Successive RAS mode setup DRAM RAS prechar[...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 41 Name Address Register name Bit Function Setting Init. R/W Remarks – 1 Enabled 0 Disabled 1 Enabled 0 Disabled A18AS A16AS A14AS A12AS – A8AS A6AS A5AS A18RD A16RD A14RD A12RD – A8RD A6RD A5RD DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Area 18, 17 address strobe signal Area 16, 15 a[...]

4 PERIPHERAL CIRCUITS A- 42 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR0A15 CR0A14 CR0A13 CR0A12 CR0A11 CR0A10 CR0A9 CR0A8 CR0A7 CR0A6 CR0A5 CR0A4 CR0A3 CR0A2 CR0A1 CR0A0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 0 comparison data A CR0A15 = MSB CR0A0 = LSB X X X X [...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 43 Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR1A15 CR1A14 CR1A13 CR1A12 CR1A11 CR1A10 CR1A9 CR1A8 CR1A7 CR1A6 CR1A5 CR1A4 CR1A3 CR1A2 CR1A1 CR1A0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 1 comparison data A CR1A15 = MSB CR1A0 = LSB X X X X [...]

4 PERIPHERAL CIRCUITS A- 44 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR2A15 CR2A14 CR2A13 CR2A12 CR2A11 CR2A10 CR2A9 CR2A8 CR2A7 CR2A6 CR2A5 CR2A4 CR2A3 CR2A2 CR2A1 CR2A0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 2 comparison data A CR2A15 = MSB CR2A0 = LSB X X X X [...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 45 Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR3A15 CR3A14 CR3A13 CR3A12 CR3A11 CR3A10 CR3A9 CR3A8 CR3A7 CR3A6 CR3A5 CR3A4 CR3A3 CR3A2 CR3A1 CR3A0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 3 comparison data A CR3A15 = MSB CR3A0 = LSB X X X X [...]

4 PERIPHERAL CIRCUITS A- 46 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR4A15 CR4A14 CR4A13 CR4A12 CR4A11 CR4A10 CR4A9 CR4A8 CR4A7 CR4A6 CR4A5 CR4A4 CR4A3 CR4A2 CR4A1 CR4A0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 4 comparison data A CR4A15 = MSB CR4A0 = LSB X X X X [...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 47 Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR5A15 CR5A14 CR5A13 CR5A12 CR5A11 CR5A10 CR5A9 CR5A8 CR5A7 CR5A6 CR5A5 CR5A4 CR5A3 CR5A2 CR5A1 CR5A0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 5 comparison data A CR5A15 = MSB CR5A0 = LSB X X X X [...]

4 PERIPHERAL CIRCUITS A- 48 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks DBASEL15 DBASEL14 DBASEL13 DBASEL12 DBASEL11 DBASEL10 DBASEL9 DBASEL8 DBASEL7 DBASEL6 DBASEL5 DBASEL4 DBASEL3 DBASEL2 DBASEL1 DBASEL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IDMA base address low-order 16 bits (Initial [...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 49 Name Address Register name Bit Function Setting Init. R/W Remarks TC0_L7 TC0_L6 TC0_L5 TC0_L4 TC0_L3 TC0_L2 TC0_L1 TC0_L0 BLKLEN07 BLKLEN06 BLKLEN05 BLKLEN04 BLKLEN03 BLKLEN02 BLKLEN01 BLKLEN00 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.0 transfer c ounter[7:0] (block transfer mode) C[...]

4 PERIPHERAL CIRCUITS A- 50 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks D0ADRL15 D0ADRL14 D0ADRL13 D0ADRL12 D0ADRL11 D0ADRL10 D0ADRL9 D0ADRL8 D0ADRL7 D0ADRL6 D0ADRL5 D0ADRL4 D0ADRL3 D0ADRL2 D0ADRL1 D0ADRL0 DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.0 destination address[15:0] S) Invalid [...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 51 Name Address Register name Bit Function Setting Init. R/W Remarks TC1_L7 TC1_L6 TC1_L5 TC1_L4 TC1_L3 TC1_L2 TC1_L1 TC1_L0 BLKLEN17 BLKLEN16 BLKLEN15 BLKLEN14 BLKLEN13 BLKLEN12 BLKLEN11 BLKLEN10 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.1 transfer c ounter[7:0] (block transfer mode) C[...]

4 PERIPHERAL CIRCUITS A- 52 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks D1ADRL15 D1ADRL14 D1ADRL13 D1ADRL12 D1ADRL11 D1ADRL10 D1ADRL9 D1ADRL8 D1ADRL7 D1ADRL6 D1ADRL5 D1ADRL4 D1ADRL3 D1ADRL2 D1ADRL1 D1ADRL0 DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.1 destination address[15:0] S) Invalid [...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 53 Name Address Register name Bit Function Setting Init. R/W Remarks TC2_L7 TC2_L6 TC2_L5 TC2_L4 TC2_L3 TC2_L2 TC2_L1 TC2_L0 BLKLEN27 BLKLEN26 BLKLEN25 BLKLEN24 BLKLEN23 BLKLEN22 BLKLEN21 BLKLEN20 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.2 transfer c ounter[7:0] (block transfer mode) C[...]

4 PERIPHERAL CIRCUITS A- 54 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks D2ADRL15 D2ADRL14 D2ADRL13 D2ADRL12 D2ADRL11 D2ADRL10 D2ADRL9 D2ADRL8 D2ADRL7 D2ADRL6 D2ADRL5 D2ADRL4 D2ADRL3 D2ADRL2 D2ADRL1 D2ADRL0 DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.2 destination address[15:0] S) Invalid [...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 55 Name Address Register name Bit Function Setting Init. R/W Remarks TC3_L7 TC3_L6 TC3_L5 TC3_L4 TC3_L3 TC3_L2 TC3_L1 TC3_L0 BLKLEN37 BLKLEN36 BLKLEN35 BLKLEN34 BLKLEN33 BLKLEN32 BLKLEN31 BLKLEN30 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.3 transfer c ounter[7:0] (block transfer mode) C[...]

4 PERIPHERAL CIRCUITS A- 56 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks D3ADRL15 D3ADRL14 D3ADRL13 D3ADRL12 D3ADRL11 D3ADRL10 D3ADRL9 D3ADRL8 D3ADRL7 D3ADRL6 D3ADRL5 D3ADRL4 D3ADRL3 D3ADRL2 D3ADRL1 D3ADRL0 DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.3 destination address[15:0] S) Invalid [...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 57 Name Address Register name Bit Function Setting Init. R/W Remarks – MCRS1 MCRS0 D15 – 2 D1 D0 – Master configuration selection 1 1 0 0 1 0 1 0 MCRS[1:0] – Communications mode PHS PDC HDLC UART – 0 0 – R/W 0 when being read. Only valid when MSEL pin input is at High level 0200000 ([...]

4 PERIPHERAL CIRCUITS A- 58 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks – CP4EN4 CP4EN3 CP4EN2 CP4EN1 CP4EN0 D15 – 5 D4 D3 D2 D1 D0 – Map UINT4 interrupt requests to CP4 Map UINT3 interrupt requests to CP4 Map UINT2 interrupt requests to CP4 Map UINT1 interrupt requests to CP4 Map UINT0 inter[...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 59 Name Address Register name Bit Function Setting Init. R/W Remarks – ERES RESINT – RRXINT RTXINT D15 – 8 D7 D6 D5 – 2 D1 D0 – HDLC error reset HDLC E/S interrupt reset – HDLC receive interrupt reset HDLC transmit interrupt reset – – – 0 0 – 0 0 – W W – W W 0 when being [...]

4 PERIPHERAL CIRCUITS A- 60 EPSON S1C33210 PRODUCT PA RT Name Address Register name Bit Function Setting Init. R/W Remarks – RXINTS1 RXINTS0 D15 – 2 D1 D0 – Receive interrupt operating mode – 0 0 – R/W R/W 0 when being read. 0200312 (HW) HDLC receive interrupt mode settings register – 1 1 0 0 1 0 1 0 RXINTS[1:0] Operating Mode (Not allo[...]

4 PERIPHERAL CIRCUITS S1C33210 PRODUCT PAR T EPSON A- 61 Name Address Register name Bit Function Setting Init. R/W Remarks – RCODE7 RCODE6 RCODE5 RCODE4 RCODE3 RCODE2 RCODE1 RCODE0 D15 – 8 D7 D6 D5 D4 D3 D2 D1 D0 – Residue Code Number of valid bits in excess residue code bits at end of frame – 11111110 11111100 11111000 11110000 11100000 11[...]

5 POWER-DOWN CONTROL A- 62 EPSON S1C33210 PRODUCT PA RT 5 Po we r-Do wn Control This chapter describes the controls used to reduce power consumption of the device. Points on power saving The current consumption of the device varies greatly with the CPU's operation mode, the system clocks used, and the peripheral circuits operated. Current cons[...]

5 POWER-DOWN CONTROL S1C33210 PRODUCT PAR T EPSON A- 63 Switching over the system clocks Normally, the system is clocked by the high-speed (OSC3) oscillation clock. If high-speed operation is unnecessary, switch the system clock to the low-speed (OSC1) oscillation clock and turn off the high-speed (OSC3) oscillation circuit. This helps to reduce cu[...]

5 POWER-DOWN CONTROL A- 64 EPSON S1C33210 PRODUCT PA RT Function Control bit "1" "0" Default Prescaler ON/OFF PSCON(D5)/Power control register(0x40180) ON OFF ON 16-bit timer 0 clock control P16TON0(D3)/16-bit timer 0 clock control register(0x40147) ON OFF OFF 16-bit timer 0 Run/Stop PRUN0(D0)/16-bit timer 0 control register(0x4[...]

6 BASIC EXTERNAL WIRIN G DIAGRAM S1C33210 PRODUCT PAR T EPSON A- 65 6 Basic Exte rnal Wiring Diag ram V DD AV DD DSIO TST EA10MD0 EA10MD1 #X2SPD PLLC PLLS0 PLLS1 OSC3 OSC4 OSC1 OSC2 #RESET V SS C D2 3.3V X'tal2 or CR Rf 2 A[23:0] D[15:0] #RD #DRD #GARD #GAAS #WRL/#WR/#WE #WRH/#BSH #DWR #HCAS #LCAS #CExx/#RASx #CE10EX #WAIT BCLK #BUSREQ #BUSACK[...]

7 PRECAUTIONS ON MOUNTING A- 66 EPSON S1C33210 PRODUCT PA RT 7 Precautions on Mounting The following shows the precautions when designing the board and mounting the IC. Oscillation Circuit • Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when a ceramic oscillator or crystal oscill[...]

7 PRECAUTIONS ON MOUNT ING S1C33210 PRODUCT PAR T EPSON A- 67 (2) When connecting between the V DD and V SS pins with a bypass capacitor, the pins should be connected as short as possible. V DD V SS Bypass capacitor connection example V DD V SS A/D Converter • When the A/D converter is not used, the power supply pin AV DD for the analog system sh[...]

8 ELECTRICAL CHARACTER ISTICS A- 68 EPSON S1C33210 PRODUCT PA RT 8 Electrical Characte ristics 8 .1 Absolute Maximum Rating (V SS =0V) Item Symbol Condition Rated value Unit ∗ Supply voltage V DD -0.3 to +4.0 V Input voltage V I -0.3 to V DDE +0.5 V High-level output current I OH 1 pin -10 mA Total of all pins -40 mA Low-level output current I OL[...]

8 ELECTRICAL CHARACTER ISTICS S1C33210 PRODUCT PAR T EPSON A- 69 8 .2 Recommended Operating Conditions (V SS =0V) Item Symbol Condition Min. Typ. Max. Unit ∗ Supply voltage V DD 2.70 – 3.60 V Input voltage V I V SS –V DD V CPU operating clock frequency f CPU –– 5 0 M H z Low-speed oscillation frequency f OSC1 – 32.768 – kHz Operating [...]

8 ELECTRICAL CHARACTER ISTICS A- 70 EPSON S1C33210 PRODUCT PA RT 8 .3 DC Characteristics (Unless otherwise specified: V DD =2.7V to 3.6V, Ta=-40 ° C to +85 ° C) Item Symbol Condition Min. Typ. Max. Unit ∗ Input leakage current I LI -1 – 1 µ A Off-state leakage curr ent I OZ -1 – 1 µ A High-level output voltage V OH I OH =-2mA (Type1), I O[...]

8 ELECTRICAL CHARACTER ISTICS S1C33210 PRODUCT PAR T EPSON A- 71 8 .4 Current Consumption (Unless otherwise specified: V DD =2.7V to 3.6V, V SS =0V, Ta=-40 ° C to +85 ° C) Item Symbol Condition Min. Typ. Max. Unit ∗ Operating current I DD1 When CPU is operating 20MHz – 27 37 mA 1 33MHz – 48 64 50MHz – 64 90 I DD2 HALT mode 20MHz – 16 20[...]

8 ELECTRICAL CHARACTER ISTICS A- 72 EPSON S1C33210 PRODUCT PA RT 8 .5 A/D Converter Characteristics (Unless otherwise specified: AV DD =V DD =2.7V to 3.6V, V SS =0V, Ta=-40 ° C to +85 ° C, ST[1:0]=11) Item Symbol Condition Min. Typ. Max. Unit ∗ Resolution – – 10 – bit Conversion time – 10 – 625 µ s1 Zero scale error E ZS 024 L S B Fu[...]

8 ELECTRICAL CHARACTER ISTICS S1C33210 PRODUCT PAR T EPSON A- 73 V'[000]h 3FF 3FE 3FD 003 002 001 000 V SS AV DD Integral linearity error E L = [LSB] V N ' - V N 1LSB' Digital output (hex) Analog input Ideal conversion characteristic Actual conversion characteristic V'[3FF]h V'[N]h V N ' V N V'[N-1]h N+1 N N-1 N-2[...]

8 ELECTRICAL CHARACTER ISTICS A- 74 EPSON S1C33210 PRODUCT PA RT 8 .6 AC Characteristics 8 .6 .1 Symbol Description t CYC : Bus-clock cycle time • In x1 mode, t CYC = 50 ns (20 MHz) when the CPU is operated with a 20-MHz clock t CYC = 30 ns (33 MHz) when the CPU is operated with a 33-MHz clock • In x2 mode, t CYC = 50 ns (20 MHz) when the CPU i[...]

8 ELECTRICAL CHARACTER ISTICS S1C33210 PRODUCT PAR T EPSON A- 75 8 .6 .3 C33 Block AC Characteristic Tables External clock input characteris tics (Note) These AC characteristics apply to input signals from outside the IC. The OSC3 input clock must be within V DD to V SS voltage range. (Unless otherwise specified: V DD =2.7V to 3.6V, V SS =0V, Ta=-4[...]

8 ELECTRICAL CHARACTER ISTICS A- 76 EPSON S1C33210 PRODUCT PA RT Common characteristics (Unless otherwise specified: V DD =2.7V to 3.6V, V SS =0V, Ta=-40 ° C to +85 ° C) Item Symbol Min. Max. Unit ∗ Address delay time t AD – 10 ns 1 #CEx delay time (1) t CE1 – 10 ns #CEx delay time (2) t CE2 – 10 ns Wait setup time t WTS 17 – ns Wait ho[...]

8 ELECTRICAL CHARACTER ISTICS S1C33210 PRODUCT PAR T EPSON A- 77 DRAM access cycle common characteristics (Unless otherwise specified: V DD =2.7V to 3.6V, V SS =0V, Ta=-40 ° C to +85 ° C) Item Symbol Min. Max. Unit ∗ #RAS signal delay time (1) t RASD1 10 ns #RAS signal delay time (2) t RASD2 10 ns #RAS signal pulse width t RASW t CYC (2+WC)-10 [...]

8 ELECTRICAL CHARACTER ISTICS A- 78 EPSON S1C33210 PRODUCT PA RT 8 .6 .4 C33 Block AC Characteristic Timing Charts Clock OSC3 (High-speed clock) t C3 BCLK (Clock output) t C3 t C3H t C3ED = t C3H / t C3 t CBD = t CBH / t C3 BCLK (Clock output) t C3 t CBH t CD1 t CD2 t IF t IR (1) When an external clock is input (in x1 speed mode): (2) When the high[...]

8 ELECTRICAL CHARACTER ISTICS S1C33210 PRODUCT PAR T EPSON A- 79 SRAM read cycle (basic cycle: 1 cycle) BCLK A[23:0] #CEx #RD D[15:0] #WAIT t C3 t AD t CE1 t CE2 t RDD2 t RDD1 t RDAC1 t RDS t WTS t WTH t RDH t CEAC1 t ACC1 t RDW t AD ∗ 1 *1 t RDH is measured with respect to the first signal change (negation) from among the #RD, #CEx and A[23:0] s[...]

8 ELECTRICAL CHARACTER ISTICS A- 80 EPSON S1C33210 PRODUCT PA RT SRAM write cycle (basic cycle: 2 cycles) BCLK A[23:0] #CEx #WR D[15:0] #WAIT C1 C2 t AD t CE1 t CE2 t WRD2 t WRD1 t WTS t WTH t WDD1 t WDH t WRW t AD SRAM write cycle (when wait cycles are inserted) BCLK A[23:0] #CEx #WR D[15:0] #WAIT C1 Cw (wait cycle) Cw (wait cycle) Cn (last cycle)[...]

8 ELECTRICAL CHARACTER ISTICS S1C33210 PRODUCT PAR T EPSON A- 81 DRAM random access cycle (basic cycle) BCLK A[23:0] #RAS #HCAS/ #LCAS #RD D[15:0] #WE D[15:0] RAS1 Data transfer #1 Next data transfer CAS1 PRE1 (precharge) RAS1' CAS1' t AD t AD t AD t CASD2 t CASD1 t RDS t ACCF t RACF t RDH t RASD2 t RASD1 t RASW t RDD3 t RDD1 t RDW2 t WRD[...]

8 ELECTRICAL CHARACTER ISTICS A- 82 EPSON S1C33210 PRODUCT PA RT EDO DRAM random access cycle (basic cycle) BCLK A[23:0] #RAS #HCAS/ #LCAS #RD D[15:0] #WE D[15:0] RAS1 Data transfer #1 Next data transfer CAS1 PRE1 (precharge) RAS1' CAS1' t AD t AD t AD t CASD2 t CASD1 t RDS2 t ACCE t RACE t RDH t RASD2 t RASD1 t RASW t RDD3 t RDD1 t RDW2 [...]

8 ELECTRICAL CHARACTER ISTICS S1C33210 PRODUCT PAR T EPSON A- 83 DRAM CAS-before-RAS refresh cycle BCLK #RAS #HCAS/ #LCAS #WE CBR refresh cycle C CBR1 C CBR2 C CBR3 t RASD2 t RASD1 t CASD2 t CASD1 DRAM self-refresh cycle BCLK #RAS #HCAS/ #LCAS Self-refresh mode setup Self-refresh mode t CASD2 Self-refresh mode canceration t RASD2 t RASD1 t CASD1 6-[...]

8 ELECTRICAL CHARACTER ISTICS A- 84 EPSON S1C33210 PRODUCT PA RT #BUSREQ, #BUSACK and #NMI timing BCLK #BUSREQ #BUSACK eBUS_OUT signals ∗ 1 eBUS_OUT signals ∗ 1 #NMI t BRQS Valid input t NMIW t BRQH t BAKD t Z2E t B2Z ∗ 1 eBUS_OUT indicates the following pins: A[23:0], #RD, #WRL, #WRH, #HCAS , #LCAS, #CE[17:4], D[15:0] Input, output and I/O p[...]

8 ELECTRICAL CHARACTER ISTICS S1C33210 PRODUCT PAR T EPSON A- 85 8 .7 Oscillation Characteristics Oscillation characteristics change depending on conditions (board pattern, components used, etc.). Use the following characteristics as reference values. In particular, when a ceramic or crystal oscillator is used, use the oscillator manufacturer recom[...]

8 ELECTRICAL CHARACTER ISTICS A- 86 EPSON S1C33210 PRODUCT PA RT 8 .8 PLL Characteristics Setting the PLLS0 and PLLS1 pins (recommended operating condition) V DD =2.7V to 3.6V PLLS1 PLLS0 Mode Fin (OSC3 clock) Fout 1 1 x2 10 to 25MHz 20 to 50MHz 0 1 x4 10 to 1 2.5MHz 40 to 50MHz 0 0 PLL not used –– PLL characteristics (Unless otherwise specifie[...]

9 PACKAGE S1C33210 PRODUCT PAR T EPSON A- 87 9 Package 9 .1 Plastic Package QFP15-128pin (Unit: mm) 14 ± 0.1 16 ± 0.4 65 96 14 ± 0.1 16 ± 0.4 33 64 INDEX 0.16 32 1 128 97 1.4 ± 0.1 0.1 1.7 max 1 0.5 ± 0.2 0 ° 10 ° 0.125 0.4 +0.1 –0.05 +0.05 –0.025 Limit of power consumption The chip temperature of an LSI rises according to power consump[...]

10 PAD LAYOUT A- 88 EPSON S1C3 3210 PRODUCT PART 10 Pad Layout 10 .1 Pad Layout Diagram X Y (0, 0) TBD mm TBD mm 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 175 180 185 190 195 200 Die No.[...]

10 PAD LAYOUT S1C33210 PRODUCT PAR T EPSON A- 89 10 .2 Pad Coordinate (Unit: µ m) No. Pad name X Y No. Pad name X Y 1 P15/EXCL4/#DMAEND0 -2.352 -2.54 51 K62/AD2 1.848 -2.54 2 N.C. -2.268 -2.54 52 N.C. 1.932 -2.54 3 P26/TM4/SOUT2 -2.184 -2.54 53 AV DD 2.016 -2.54 4 P27/TM5/SIN2 -2.1 -2.54 54 K61/AD1 2.1 -2.54 5V SS -2.016 -2.54 55 K60/AD0 2.184 -2.[...]

10 PAD LAYOUT A- 90 EPSON S1C3 3210 PRODUCT PART No. Pad name X Y N o. Pad name X Y 101 N.C. 2.834 1.554 151 N.C. -1.26 2.54 102 P35/#BUSACK 2.834 1.638 152 V SS -1.344 2.54 103 #HCAS 2.834 1.722 153 N.C. -1.428 2.54 104 #LCAS 2.834 1.806 154 A19 -1.512 2.54 105 P34/#BUSREQ/#CE6 2.834 1.89 155 N.C. -1.596 2.54 106 N.C. 2.834 1.974 156 P20/#DRD -1.6[...]

10 PAD LAYOUT S1C33210 PRODUCT PAR T EPSON A- 91 No. Pad name X Y 201 N.C. -2.834 -0.966 202 P23/TM1 -2.834 -1.05 203 N.C. -2.834 -1.134 204 DSIO -2.834 -1.218 205 N.C. -2.834 -1.302 206 P10/EXCL0/T8UF0/DST0 -2.834 -1.386 207 P11/EXCL1/T8UF1/DST1 -2.834 -1.47 208 N.C. -2.834 -1.554 209 P12/EXCL2/T8UF2/DST2 -2.834 -1.638 210 P13/EXCL3/T8UF3/DPC0 -2.[...]

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS A- 92 EPSON S1C33210 PRODUCT PA RT Appendix A <Refe rence> Exte rnal De v ice Inte rface Timings This section shows setup examples for setting timing conditions of the external system interface as a reference material used when configuring a system with external devices. Pay atten[...]

APPENDIX A <REFERENCE> EXTER NAL DEVICE INTERFACE TIMINGS S1C33210 PRODUCT PAR T EPSON A- 93 A.1 DRAM (70ns) DRAM interface setup examples – 70ns Operating frequency RAS precharge cycle RAS cycle CAS cycle Refresh RAS pulse width Refresh RPC delay 2 0 M H z 21 22 1 2 5 M H z 21 22 1 3 3 M H z 22 33 1 DRAM interface timing – 70ns DRAM inte[...]

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS A- 94 EPSON S1C33210 PRODUCT PA RT DRAM: 70ns, CPU: 33MHz, random read/write cycle 2 RAS cycle CAS cycle RAS precharge 3 t RC t RAD t RAH t RCD t RAC t OAC t AA t CAC t OFF t CAS t ASC t RAS t ASR t WP t RP 2 BCLK A[11:0] #RAS #CAS #RD D[15:0](RD) #WE D[15:0](WR) ROW #1 RD data ROW #2 t[...]

APPENDIX A <REFERENCE> EXTER NAL DEVICE INTERFACE TIMINGS S1C33210 PRODUCT PAR T EPSON A- 95 DRAM: 70ns, CPU: 25/20MHz, random read/write cycle 1 RAS cycle CAS cycle RAS precharge 2 t RAS 2 BCLK A[11:0] #RAS #CAS #RD D[15:0](RD) #WE D[15:0](WR) ROW #1 RD data ROW #2 WR data COL #1 DRAM: 70ns, CPU: 25/20MHz, page-mode read/write cycle 1 RAS cy[...]

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS A- 96 EPSON S1C33210 PRODUCT PA RT A.2 DRAM (60ns) DRAM interface setup examples – 60ns Operating frequency RAS precharge cycle RAS cycle CAS cycle Refresh RAS pulse width Refresh RPC delay 2 0 M H z 11 22 1 2 5 M H z 21 22 1 3 3 M H z 22 23 1 DRAM interface timing – 60ns DRAM inter[...]

APPENDIX A <REFERENCE> EXTER NAL DEVICE INTERFACE TIMINGS S1C33210 PRODUCT PAR T EPSON A- 97 DRAM: 60ns, CPU: 33MHz, random read/write cycle 2 RAS cycle CAS cycle RAS precharge 2 t RC t RAD t RAH t RCD t RAC t OAC t AA t CAC t OFF t CAS t ASC t RAS t ASR t WP t RP 2 BCLK A[11:0] #RAS #CAS #RD D[15:0](RD) #WE D[15:0](WR) ROW #1 RD data ROW #2 [...]

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS A- 98 EPSON S1C33210 PRODUCT PA RT DRAM: 60ns, CPU: 25MHz, random read/write cycle 1 RAS cycle CAS cycle RAS precharge 2 t RAS 2 BCLK A[11:0] #RAS #CAS #RD D[15:0](RD) #WE D[15:0](WR) ROW #1 RD data ROW #2 WR data COL #1 DRAM: 60ns, CPU: 25MHz, page-mode read/write cycle 1 RAS cycle CAS[...]

APPENDIX A <REFERENCE> EXTER NAL DEVICE INTERFACE TIMINGS S1C33210 PRODUCT PAR T EPSON A- 99 DRAM: 60ns, CPU: 20MHz, random read/write cycle 1 RAS cycle CAS cycle RAS precharge 2 t RAS 1 BCLK A[11:0] #RAS #CAS #RD D[15:0](RD) #WE D[15:0](WR) ROW #1 RD data ROW #2 WR data COL #1 DRAM: 60ns, CPU: 20MHz, page-mode read/write cycle 1 RAS cycle CA[...]

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS A- 100 EPSON S1C33210 PRODUCT PA RT A.3 ROM and Burst ROM Burst ROM and mask ROM interface setup examples Operating Normal read cycle Burst read cycle Output disable frequency Wait cycle Read cycle Wait cycle Read cycle delay cycle 20MHz 2 3 1 2 1.5 25MHz 3 4 1 2 1.5 33MHz 4 5 2 3 1.5 B[...]

APPENDIX A <REFERENCE> EXTER NAL DEVICE INTERFACE TIMINGS S1C33210 PRODUCT PAR T EPSON A- 101 ROM: 100ns, CPU: 25MHz, normal read BCLK A[23:0] #CE9, 10 #RD D[15:0] RD data ROM: 100ns, CPU: 25MHz, burst read Normal read cycle Burst read cycle BCLK A[23:0] #CE9, 10 #RD D[15:0] RD data RD data RD data RD data ROM: 100ns, CPU: 20MHz, normal read [...]

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS A- 102 EPSON S1C33210 PRODUCT PA RT A.4 SRAM (55ns) SRAM interface setup examples – 55ns Operating Read cycle Write cycle Output disable frequency Wait cycle Read cycle delay time 20MHz 1 2 2 1.5 25MHz 2 3 3 1.5 33MHz 2 3 3 1.5 SRAM interface timing – 55ns SRAM interface 33MHz 25MHz[...]

APPENDIX A <REFERENCE> EXTER NAL DEVICE INTERFACE TIMINGS S1C33210 PRODUCT PAR T EPSON A- 103 SRAM: 55ns, CPU: 20MHz, read cycle BCLK A[23:0] #CEx #RD D[15:0] RD data SRAM: 55ns, CPU: 20MHz, write cycle BCLK A[23:0] #CEx #WP D[15:0] WR data[...]

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS A- 104 EPSON S1C33210 PRODUCT PA RT A.5 SRAM (70ns) SRAM interface setup examples – 70ns Operating Read cycle Write cycle Output disable frequency Wait cycle Read cycle delay time 20MHz 2 3 3 1.5 25MHz 2 3 3 1.5 33MHz 3 4 4 1.5 SRAM interface timing – 70ns SRAM interface 33MHz 25MHz[...]

APPENDIX A <REFERENCE> EXTER NAL DEVICE INTERFACE TIMINGS S1C33210 PRODUCT PAR T EPSON A- 105 SRAM: 70ns, CPU: 25/20MHz, read cycle BCLK A[23:0] #CEx #RD D[15:0] RD data SRAM: 70ns, CPU: 25/20MHz, write cycle BCLK A[23:0] #CEx #WP D[15:0] WR data[...]

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS A- 106 EPSON S1C33210 PRODUCT PA RT A.6 8255A 8255A interface setup examples Operating Read cycle Write cycle Output disable frequency Wait cycle Read cycle delay time 20MHz 9 ∗ 1 1 01 03 . 5 25MHz 11 12 12 3.5 33MHz 14 15 15 3.5 ∗ 2 8255A interface timing SRAM interface 33MHz 25MHz[...]

APPENDIX B PIN CHARACTERISTICS S1C33210 PRODUCT PAR T EPSON A- 107 Appendix B Pin Characte ristics Pin No. Signal name I/O cell Characteristic Pull-up/ Power Remarks name Input Output down supply 1 P26/TM4/SOUT2 XBH1T CMOS/LVTTL SCHMITT 2 mA V DD 2 P27/TM5/SIN2 XBH1T CMOS/LVTTL SCHMITT 2 mA V DD 3V SS 4 BCLK XOB1T 2 mA V DD 5 P00/SIN0 XBH1T CMOS/LV[...]

APPENDIX B PIN CHARACTERISTICS A- 108 EPSON S1C33210 PRODUCT PA RT Pin No. Signal name I/O cell Characteristic Pull-up/ Power Remarks name Input Output down supply 52 #CE6/#CE7&8 XTB1T Note 2 2 mA V DD 53 #CE8/#RAS1/#CE14/ #RAS3 XTB1T Note 2 2 mA V DD 54 V SS 55 A0/#BSL XBB1 Note 2 2 mA V DD 56 A1 XBB1 Note 2 2 mA V DD 57 A2 XBB1 Note 2 2 mA V [...]

APPENDIX B PIN CHARACTERISTICS S1C33210 PRODUCT PAR T EPSON A- 109 Pin No. Signal name I/O cell Characteristic Pull-up/ Power Remarks name Input Output down supply 101 CTS XIBC CMOS/LVTTL V DD 102 V SS 103 PLLC XLIN V DD 104 V SS XIBCD1 CMOS/LVTTL Pull-down 105 PLLS1 XIBC CMOS/LVTTL V DD 106 PLLS0 XIBC CMOS/LVTTL V DD 107 RXD/SIN3 XIBC CMOS/LVTTL V[...]

APPENDIX B PIN CHARACTERISTICS A- 110 EPSON S1C33210 PRODUCT PA RT THIS PAGE IS BLANK.[...]

S1C33210 FUNCTION PART[...]

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S1C33210 FUNCTION PART I OUTLINE[...]

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I OUTLINE: INTRODUCTION S1C33210 FUNCTION PART EPSON B-I- 1-1 I-1 INT RODUCTION The Function Part gives a detailed description of the various function blocks built into the Seiko Epson original 32-bit microcomputer S1C33210. The S1C33210 employs a RISC type CPU, and has a powerful instruction set capable of compilation into compact code, despite th[...]

I OUTLINE: INTRODUCTION B-I- 1-2 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK.[...]

I OUTLINE: BLOCK DIAGRAM S1C33210 FUNCTION PART EPSON B-I- 2-1 I-2 BLOCK DIAGRAM The S1C33210 consists of five major blocks: C33 Core Block, C33 Peripheral Block, C33 Analog Block, C33 DMA Block and C33 Internal Memory Block. Figure 2.1 shows the configuration of the S1C33 blocks. CORE_PAD Pads C33_SBUS Internal RAM (Area 0) C33 Core Block C33 Inte[...]

I OUTLINE: BLOCK DIAGRAM B-I- 2-2 EPSON S1C33210 FUNCTION PART C33 Core Block The C33 Core Block consists of a functional block C33_CORE including CPU, BCU (Bus Control Unit), ITC (Interrupt Controller), CLG (Clock Generator) and DBG (Debug Unit), an I/O pad block for external interface, and an SBUS (Internal Silicon Integration Bus) for interfacin[...]

I OUTLINE: LIST OF PINS S1C33210 FUNCTION PART EPSON B-I- 3-1 I-3 LIST OF PINS List of External I/O Pins The following lists the external I/O pins of the C33 Core Block and Peripheral Block. Note that some pins are listed in two or more tables. Table 3 .1 List of Pins for External Bus Interface Signals Pin name I/O Pull-up Function A0 #BSL O – A0[...]

I OUTLINE: LIST OF PINS B-I- 3-2 EPSON S1C33210 FUNCTION PART Pin name I/O Pull-up Function P30 #WAIT #CE4&5 I/O – P30: I/O port when CFP30(D0/0x402DC) = "0" (default) #WAIT: Wait cycle request input when CFP30(D0/0x402DC) = "1" #CE4&5: Areas 4&5 chip enable when CFP30(D0/0x402DC) = "1" and IOC30(D0/0x402[...]

I OUTLINE: LIST OF PINS S1C33210 FUNCTION PART EPSON B-I- 3-3 Table 3 .3 List of Pins for Internal Peripheral Circuits Pin name I/O Pull-up Function K52 #ADTRG I Pull-up K52: Input port when CFK52(D2/0x402C0) = "0" (default) #ADTRG: A/D converter trigger input when CFK52(D2/0x402C0) = "1" K60 AD0 I – K60: Input port when CFK60[...]

I OUTLINE: LIST OF PINS B-I- 3-4 EPSON S1C33210 FUNCTION PART Pin name I/O Pull-up Function P16 EXCL5 #DMAEND1 I/O – P16: I/O port when CFP16(D6/0x402D4) = "0" (default) EXCL5: 16-bit timer 5 event counter input when CFP16(D6/0x402D4) = "1" and IOC16(D6/0x402D6) = "0" #DMAEND1: HSDMA Ch. 1 end-of-transfer signal outp[...]

I OUTLINE: LIST OF PINS S1C33210 FUNCTION PART EPSON B-I- 3-5 Table 3 .4 List of Pins for Clock Generator Pin name I/O Pull-up Function OSC1 I – Low-speed (OSC1) oscillation input (32 kHz crystal oscillator or external clock input) OSC2 O – Low-speed (OSC1) oscillation output OSC3 I – High-speed (OSC3) oscillation input (crystal/ceramic oscil[...]

I OUTLINE: LIST OF PINS B-I- 3-6 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK.[...]

S1C33210 FUNCTION PART II CORE BLOCK[...]

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II CORE BLOCK: INTRODUCTION S1C33210 FUNCTION PART EPSON B-II- 1-1 II-1 INT RODUCTION The core block consists of a functional block C33_CORE including CPU, BCU (Bus Control Unit), ITC (Interrupt Controller), CLG (Clock Generator) and DBG (Debug Unit), an I/O pad block for external interface, and an SBUS (Internal Silicon Integration Bus) for interf[...]

II CORE BLOCK: INTRODUCTION B-II- 1-2 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK.[...]

II CORE BLOCK: CPU AND OPERATING MODE S1C33210 FUNCTION PART EPSON B-II- 2-1 II-2 CPU A ND OPERA TING MODE CPU The C33 Core Block employs the S1C33000 32-bit RISC type CPU as the core CPU. Since it has a built-in multiplier, all instructions (105 instructions) in the S1C33000 instruction set including the MAC (multiplication and accumulation) instr[...]

II CORE BLOCK: CPU AND OPERATING MODE B-II- 2-2 EPSON S1C33210 FUNCTION PART Standby Mode The CPU supports three standby modes: two HALT modes and a SLEEP mode. By setting the CPU in the standby mode, power consumption can greatly be reduced. HALT Mode When the CPU executes the halt instruction, it suspends the program execution and enters the HALT[...]

II CORE BLOCK: CPU AND OPERATING MODE S1C33210 FUNCTION PART EPSON B-II- 2-3 Notes on Standby Mode Interrupts The standby mode can be canceled by an interrupt. Therefore, it is necessary to enable the interrupt to be used for canceling the standby mode before setting the CPU in the standby mode. It is also necessary to set the IE (interrupt enable)[...]

II CORE BLOCK: CPU AND OPERATING MODE B-II- 2-4 EPSON S1C33210 FUNCTION PART Trap Table Table 2.1 shows the trap table in the C33 Core. Refer to the "S1C33000 Core CPU Manual" for details of exceptions and Section II-5 in this manual, "ITC (Interrupt Controller)", for interrupts. Serial interface Ch.2 and Ch.3 interrupts share t[...]

II CORE BLOCK: CPU AND OPERATING MODE S1C33210 FUNCTION PART EPSON B-II- 2-5 HEX No. Vector number (Hex address) Exception/interrupt name Exception/interrupt factor IDMA Ch. Priority 38 56(Base+E0) Serial interface Ch.0 Receive error – High 39 57(Base+E4) Receive buffer full 23 ↑ 3A 58(Base+E8) Transmit buffer empty 24 59 reserved – – 3C 60[...]

II CORE BLOCK: CPU AND OPERATING MODE B-II- 2-6 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK.[...]

II CORE BLOCK: INITIAL RESET S1C33210 FUNCTION PART EPSON B-II- 3-1 II-3 INITIAL RESET Pins for Initial Reset Table 3.1 shows the pins used for initial reset. Table 3 .1 Pins for Initial Reset Pin name I/O Function #RESET I Initial reset input pin (Low active) Low: Resets the CPU. #MNI I NMI request input pin This pin is also used for selecting a r[...]

II CORE BLOCK: INITIAL RESET B-II- 3-2 EPSON S1C33210 FUNCTION PART Power-on Reset Be sure to reset (cold start) the chip after turning on the power to start operating. Since the #RESET pin is directly connected to an input gate, a power-on reset circuit should be configured outside the chip. An initial reset (#RESET = low) turns the high-speed (OS[...]

II CORE BLOCK: INITIAL RESET S1C33210 FUNCTION PART EPSON B-II- 3-3 Boot Address When the core CPU is initially reset, it reads the reset vector (program start address) from the boot address (0x0C00000) and loads the vector to the PC (program counter). Then the CPU starts executing the program from the address when the #RESET pin goes high. The tra[...]

II CORE BLOCK: INITIAL RESET B-II- 3-4 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK.[...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-1 II-4 BCU (Bus Control Unit) The BCU (Bus Control Unit) provides an interface for external devices and on-chip user logic block. The t ypes and sizes of memory and peripheral I/O devices can be set for each area of the memory map and can be controlled directly by the BCU. T[...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-2 EPSON S1C33210 FUNCTION PART User interface signals Table 4 .2 List of User Interface Signals Signal name I/O Function Internal_addr0 O • Address bu s (a0) when SBUSST(D3/0x4812E) = "0" (default) • Bus strobe (low byte) signal (#BSL) when SBUSST(D3/0x4812E) = "1" Internal_addr[[...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-3 Combination of System Bus Control Signals The bus control signal pins that have two or more functions have their functionality determined when an interface method is selected by a program. The BCU contains an ordinary external system interface (two interface method are sup[...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-4 EPSON S1C33210 FUNCTION PART Memory Area Memory Map Figure 4.1 shows the memory map supported by the BCU. Internal RAM Internal I/O (Mirror of internal I/O) (Mirror of internal I/O) (Reserved) For CPU core or debug mode (Reserved) For middleware use 0x0BFFFFF 0x0800000 0x07FFFFF 0x0600000 0x05FFFFF 0x[...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-5 External Memory Map and Chip Enable The BCU has a 24-bit external address bus (A[23:0]) and a 16-bit external data bus (D[15:0]), allowing an address space of up to 16 MB to be accessed with one chip enable signal. By default, the address space is divided into 11 areas (ar[...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-6 EPSON S1C33210 FUNCTION PART Area Area 17+18 (#CE17+18) SRAM type 8 or 16 bits Areas 15 – 16 (#CE15+16) SRAM type 8 or 16 bits Area 14 (#CE14/#RAS3) SRAM type DRAM type 8 or 16 bits Area 13 (#CE13/#RAS2) SRAM type DRAM type 8 or 16 bits Areas 11 – 12 (#CE11+12) SRAM type 8 or 16 bits Areas 9 – 1[...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-7 Using Internal Memory on External Memory Area The BCU allows using of an internal memory in the external memory areas. The AxxIO bit in the access control register (0x48132) is used to select either internal access or external access. When "1" is written, the int[...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-8 EPSON S1C33210 FUNCTION PART Area 10 Area 10 is an external memory area that includes the boot address (0xC00000). Area 10 boot mode The boot mode can be configured using the external pins EA10MD[1:0]. The pins EA10MD[1:0] specify the boot mode. These inputs must both be at High level because this dev[...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-9 Setting External Bus Conditions The type, size, and wait conditions of a device connected to the external bus can be individually set for each area using the control register (0x48120 to 0x48130). The following explains the available setup conditions individually for each [...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-10 EPSON S1C33210 FUNCTION PART Setting SRAM Timing Conditions The areas set for the SRAM allow wait cycles and output disable delay time to be set. Number of wait cycles: 0 to 7 (incremented in units of one cycle) Output disable delay time: 0.5, 1.5, 2.5, 3.5 cycles This selection can be made once ever[...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-11 Output disable delay time In cases when a device having a long output disable time is connected, if a read cycle for that device is followed by the next access, contention for the data bus may occur. (Due to the fact the read device's data b us is not placed in the h[...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-12 EPSON S1C33210 FUNCTION PART Bus Operation Data Arrangement in Memory The S1C33 Family o f devices handle data in bytes (8 bits), half-words (16 bits), and words (32 bits). When accessing data in memory, it is necessary to specify a boundary address that conforms to the data size involved. Specificat[...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-13 These bus operations are shown in the figure below, taking the example of the A0 method. With the BSL method, the following adjustments should be made when reading the figure. (1) For data reads, the operation is as shown in the figure below. (2) For little-endian data wr[...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-14 EPSON S1C33210 FUNCTION PART Byte 1 15 Data bus 0 #WRL 1 #WRH 1 A0 0 A1 ∗ No. 1 Byte 0 Bus operation 1 Sign or Zero extension Byte 1 Byte 0 31 0 Destination (general-purpose register) A[1:0]= ∗ 0 Source (16-bit device) 0 15 Little-endian Byte 1 15 Data bus 0 #WRL 1 #WRH 1 A0 0 A1 ∗ No. 1 Byte 0[...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-15 Ignored 15 Data bus 0 #WRL 1 1 1 1 #WRH X X X X A0 0 1 0 1 A1 0 0 1 1 No. 1 2 3 4 Byte 0 Ignored Byte 1 Ignored Byte 2 Ignored Byte 3 Byte 3 Byte 2 Byte 1 Byte 0 31 0 A[1:0]=10 A[1:0]=00 A[1:0]=11 A[1:0]=01 80 1 4 8 88 00 0 32 Bus operation (X: Not connected/Unused) Desti[...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-16 EPSON S1C33210 FUNCTION PART Ignored 15 Data bus 0 #WRL 1 #WRH X A0 ∗ A1 ∗ No. 1 Byte 0 Byte 0 31 0 A[1:0]= ∗∗ 0 1 8 Bus operation (X: Not connected/Unused) Destination (general-purpose register) Source (8-bit device) Sign or Zero extension Little-endian Byte 0 15 Data bus 0 #WRL 1 #WRH 1 A0 [...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-17 Since the bus clock is generated from the CPU system clock (CPU_CLK), the following settings affect the bus clock: 1. Selection of an oscillation circuit (OSC3 or OSC1) 2. PLL configuration (OSC3_CLK × 1, × 2 or × 4) 3. CPU clock division ratio for power saving (1/8, 1[...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-18 EPSON S1C33210 FUNCTION PART Bus Cycles in External System Interface The following shows a sample SRAM connection the basic bus cycles. A[9:1] D[15:0] #RD #WRH #WRL #CE S1C33 (1) A0 system (little endian/big endian) A[8:0] I/O[15:0] #RD #WRH #WRL #CE SRAM A[9:1] D[15:0] A0 #WRH #WRL #CE #RD S1C33 (2)[...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-19 The above example shows a read cycle when a wait mode is inserted via the #WAIT signal. A wait mode consisting of 0 to 7 cycles can also be inserted using the wait control bits. The settings of these bits can also be used in combination with the #WAIT signal. In this case[...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-20 EPSON S1C33210 FUNCTION PART SRAM Write Cycles Basic write cycle with no wait mode BCLK A[23:0] #CExx D[15:0] #WRH/#WRL #WAIT #WR #BSL/#BSH addr data C1 C2 Figure 4. 22 Half-word Write Cycle with No Wait BCLK A[23:0] #CExx #WRH #WRL D[15:8] D[7:0] C1 C2 C3 C4 addr Undefined Valid Valid Undefined Figu[...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-21 Write cycle with wait mode Example: When the BCU has no internal wait mode, and 1 wait cycle is inserted via the #WAIT pin BCLK A[23:0] #CExx D[15:0] #WRH/#WRL #WAIT #WR #BSL/#BSH C1 CW C2 addr data Figure 4. 25 Half-word Write Cycle with Wait The #WAIT signal is sampled [...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-22 EPSON S1C33210 FUNCTION PART Burst ROM Read Cycles Burst read cycle Example: When 4-consecutive-burst and 2-wait cycles are set during the first access BCLK A[23:2] A[1:0] #CE10(9) D[15:0] #RD addr[23:2] "11" "10" "01" "00" IR3 IR2 IR1 IR0 Figure 4. 26 Burs t R[...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-23 DRAM Direct Interface Outline of DRAM Interface The BCU incorporates a DRAM direct interface that allows DRAM to be connected directly to areas 8 and 7 or areas 14 and 13. This interface supports the 2CAS method, so that column addresses can be set at between 8 and 11 bit[...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-24 EPSON S1C33210 FUNCTION PART DRAM Setting Conditions The DRAM interface allows the following conditions to be selected. Although DRAM can be used in areas 8 and 7 or areas 14 and 13, these condition are applied to all four areas and cannot be set individually for each area. Table 4 .15 DRAM Interface[...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-25 Column address size When accessing DRAM, addresses are divided into a row address and a column address as they are output. Choose the size of this column address using RCA, as shown below. Table 4 .16 Column Address Size RCA1 RCA0 Column address size 11 1 1 10 1 0 01 9 00[...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-26 EPSON S1C33210 FUNCTION PART Refresh RPC delay Use RPC0 to set the RPC delay value of a refresh cycle (a delay time from the imme diately preceding precharge to the fall of #CAS). RPC0 = "1": 2 cycles RPC0 = "0": 1 cycle Refresh RAS pulse width Use RRA to set the #RAS pulse width [...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-27 DRAM Read/Write Cycles The following shows the basic bus cycles of DRAM. The DRAM interface does not accept wait cycles inserted via the #WAIT pin. DRAM random read cycle Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle BCLK A[11:0] #RASx #HCAS/ #LCAS #RD D[15:0] [...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-28 EPSON S1C33210 FUNCTION PART DRAM random write cycle Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle BCLK A[11:0] #RASx #HCAS/ #LCAS #WE D[15:0] ROW COL write data RAS cycle CAS cycle Precharge cycle Figure 4. 32 2CAS Type DRAM Random Write Cycle DRAM write cycle (fast page or EDO page mode)[...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-29 Operation in successive RAS mode Example: RAS: 2 cycles; CAS: 1 cycle; Precharge: 2 cycles BCLK A[11:0] #RASx #HCAS/ #LCAS #DRD #DWE RAS cycle Accsess to other device than DRAM Not asserted for areas other than DRAM Precharge cycle Deassert cycle Assert cycle CAS cycles i[...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-30 EPSON S1C33210 FUNCTION PART DRAM Refresh Cycles The DRAM interface supports a CAS-before-RAS refresh cycle and a self-refresh cycle. CAS-before-RAS refresh cycle Before performing a CAS-before-RAS refresh, set RPC2 to "1" while RPC1 = "0" in order to enable the DRAM refresh funct[...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-31 Normally, DRAM specifications require that the contents of all row addresses be refreshed within a certain time before and after a self-refresh. To meet this requirement, make sure a CAS-before-RAS refresh is executed by a program. In t his case, set the 8-bit programmabl[...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-32 EPSON S1C33210 FUNCTION PART DRAM refresh when bus ownership control is released In systems where DRAM is connected directly, a refresh request could arise while control of the bus ownership is released from the CPU. In such a case, take one of the corrective measures described below. • Monitoring [...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-33 I/O Memory of BCU Table 4.21 shows the control bits of the BCU. These I/O memories are mapped into the area (0x48000 and following addresses) used for the inter nal 16-bit peripheral circuits. However, these I/O memories can be accessed in bytes or words, as well as in ha[...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-34 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – A12SZ A12DF1 A12DF0 – A12WT2 A12WT1 A12WT0 DF – 7 D6 D5 D4 D3 D2 D1 D0 reserved Areas 12 – 11 device size selection Areas 12 – 11 output disable delay time reserved Areas 12 – 11 wait control [...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-35 Name Address Register name Bit Function Setting Init. R/W Remarks – A6DF1 A6DF0 – A6WT2 A6WT1 A6WT0 – A5SZ A5DF1 A5DF0 – A5WT2 A5WT1 A5WT0 DF – E DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 reserved Area 6 output disable delay time reserved Area 6 wait control res[...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-36 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks 1 Successive 0 Normal – – CEFUNC1 CEFUNC0 CRAS RPRC1 RPRC0 – CASC1 CASC0 – RASC1 RASC0 DF – C DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 reserved reserved #CE pin function selection Successive RAS mode s[...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-37 A18SZ :A r e a s 1 8 – 17 device size selection (DE) / Areas 18 – 15 set-up register (0x48120) A16SZ : Areas 16 – 15 device size selection (D6) / Areas 18 – 15 set-up register (0x48120) A14SZ : Areas 14 – 13 device size selection (D6) / Areas 14 – 13 set-up re[...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-38 EPSON S1C33210 FUNCTION PART At cold start, these bits are set to "111" (7 cycles). At hot start, the bits reta in their status before being initialized. A14DRA : Area 14 DRAM selection (D8) / Areas 14 – 13 set-up register (0x48122) A13DRA : Area 13 DRAM selection (D7) / Areas 14 – 13 s[...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-39 A10DRA : Area 10 burst ROM selection (D8) / Areas 10 – 9 set-up register (0x48126) A9DRA : Area 9 burst ROM selection (D7) / Areas 10 – 9 set-up register (0x48126) Set areas 10 and 9 for use of burst ROM. Write "1": Burst ROM is used Write "0": Bur[...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-40 EPSON S1C33210 FUNCTION PART RCA1 – RCA0 : Column address size selection (D[B:A]) / Bus control register (0x4812E) Select the column address size of DRAM. Table 4 .23 Column Address Size RCA1 RCA0 Column address size 11 1 1 10 1 0 01 9 00 8 The contents set here are applied to all of areas 14, 13, [...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-41 RRA1 – RRA0 : Refresh RAS pulse width selection (D[6:5]) / Bus control register (0x4812E) Select the RAS pulse width of a CAS-before-RAS refresh. Table 4 .24 Refresh RAS Pulse Width RRA1 RRA0 Pulse width 1 1 5 cycles 1 0 4 cycles 0 1 3 cycles 0 0 2 cycles The contents s[...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-42 EPSON S1C33210 FUNCTION PART SWAITE : #WAIT enable (D0) / Bus control register (0x4812E) Enable or disable wait cycle control via the #WAIT pin. Write "1": Enabled Write "0": Disabled Read: Valid A wait request from an SRAM device is made acceptable by writing "1" to SWA[...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-43 CRAS : Successive RAS mode (D8) / DRAM timing set-up register (0x4 8130) Set the successive RAS mode. Write "1": Successive RAS mode Write "0": Normal mode Read: Valid In systems using DRAM, the successive RAS mode is entered by writing "1" t[...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-44 EPSON S1C33210 FUNCTION PART A18IO : Areas 18 – 17 internal/external access selection (DF) / Access control register (0x48132) A16IO : Areas 16 – 15 internal/external access selection (DE) / Access control register (0x48132) A14IO : Areas 14 – 13 internal/external access selection (DD) / Access[...]

II CORE BLOCK: BCU (Bus Control Unit) S1C33210 FUNCTION PART EPSON B-II- 4-45 A18RD : Areas 18 – 17 read signal (D7) / G/A read signal control register (0x48138) A16RD : Areas 16 – 15 read signal (D6) / G/A read signal control register (0x48138) A14RD : Areas 14 – 13 read signal (D5) / G/A read signal control register (0x48138) A12RD : Areas [...]

II CORE BLOCK: BCU (Bus Control Unit) B-II- 4-46 EPSON S1C33210 FUNCTION PART A1X1MD : Area 1 access speed (D3) / BCLK select register (0x4813A) Select a number of access cycles for area 1 in × 2 speed mode. Write "1": 2 cycles Write "0": 4 cycles Read: Valid When × 2 speed mode is set (#X2SPD pin = L ) and A1X1MD = "1&qu[...]

II CORE BLOCK: ITC ( Interrupt Controller) S1C33210 FUNCTION PART EPSON B-II- 5-1 II-5 ITC (Inte rrupt Controlle r) The C33 Core Block contains an interrupt controller, making it possible to control all interrupts generated by the internal peripheral circuits. This section explains the functions of this interrupt controller centering around the met[...]

II CORE BLOCK: ITC ( Interrupt Controller) B-II- 5-2 EPSON S1C33210 FUNCTION PART Contents of table "Hex No." indicates an interrupt number in hexadecimal value. "Vector number (Address)" indicates the trap table's vector number. The numerals in parentheses show an offset (in bytes) from the starting address (Base) of the t[...]

II CORE BLOCK: ITC ( Interrupt Controller) S1C33210 FUNCTION PART EPSON B-II- 5-3 Interrupt Factors and Intelligent DMA Several interrupt factors can be set so that they can invoke IDMA startup. When one of these interrupt factors occurs, IDMA is started up before an interrupt request to the CPU. The interrupt request to the CPU is generated afte r[...]

II CORE BLOCK: ITC ( Interrupt Controller) B-II- 5-4 EPSON S1C33210 FUNCTION PART Trap Table The C33 Core Block allows the base (starting) address of the trap table to be set by the TTBR register. TTBR0 (D[9:0]) / TTBR low-order register (0x48134): Trap table base address [9:0] (fixed at "0") TTBR1 (D[F:A]) / TTBR low-order register (0x48[...]

II CORE BLOCK: ITC ( Interrupt Controller) S1C33210 FUNCTION PART EPSON B-II- 5-5 Control of Maskable Interrupts Structure of the Interrupt Controller The interrupt controller is configured as shown in Figure 5.1. CPU interrupt priority judgment (with interrupt level) Interrupt vector generator Interrupt factor flag Interrupt enable IDMA request ID[...]

II CORE BLOCK: ITC ( Interrupt Controller) B-II- 5-6 EPSON S1C33210 FUNCTION PART The IL is rewritten for only maskable interrupts and not for any other traps (except a reset). The IL is set to level 0 (that is, all interrupts above level 1 are enabled) by an initial reset. Note: As the S1C33000 Core CPU function, the IL allows interrupt levels to [...]

II CORE BLOCK: ITC ( Interrupt Controller) S1C33210 FUNCTION PART EPSON B-II- 5-7 Interrupt enable register This register controls the output of an interrupt request to the CPU. Only when the interrupt enable bit of this register is set to "1" can an interrupt request to the CPU be enabled by an occurrence of the corresponding interrupt f[...]

II CORE BLOCK: ITC ( Interrupt Controller) B-II- 5-8 EPSON S1C33210 FUNCTION PART Interrupt Priority Register and Interrupt Levels The interrupt priority register is a 3-bit register provided for each interrupt system. It allows the interrupt levels of a given interrupt system to be set in the range of 0 to 7. The default priorities shown in Table [...]

II CORE BLOCK: ITC ( Interrupt Controller) S1C33210 FUNCTION PART EPSON B-II- 5-9 IDMA Invocation The interrupt factors for which IDMA channel numbers are written in Table 5.1 have the function to invoke the intelligent DMA (IDMA). IDMA request register The IDMA request register is used to specify the interrupt factor that invoke an IDMA transfer. [...]

II CORE BLOCK: ITC ( Interrupt Controller) B-II- 5-10 EPSON S1C33210 FUNCTION PART Interrupt after IDMA transfer To generate an interrupt after completion of IDMA transfer: The interrupt request that has been kept pending can be generated after completion of the DMA transfer. In this case, the interrupt must be enabled by the IDMA control informati[...]

II CORE BLOCK: ITC ( Interrupt Controller) S1C33210 FUNCTION PART EPSON B-II- 5-11 HSDMA Invocation Some interrupt factors can invoke high-speed DMAs (HSDMA). HSDMA trigger set-up register The DMA block contains four channel of HSDMA circuit. Each channel allows selection of an interrupt factor as the trigger. The HSDMA trigger set-up registers are[...]

II CORE BLOCK: ITC ( Interrupt Controller) B-II- 5-12 EPSON S1C33210 FUNCTION PART I/O Memory of Interrupt Controller Table 5.3 shows the control bits of the interrupt controller. Table 5 .3 Control Bits of Interrupt Controller Name Address Register name Bit Function Setting Init. R/W Remarks – 0 to 7 0 to 7 – – PP1L2 PP1L1 PP1L0 – PP0L2 PP[...]

II CORE BLOCK: ITC ( Interrupt Controller) S1C33210 FUNCTION PART EPSON B-II- 5-13 Name Address Register name Bit Function Setting Init. R/W Remarks – 0 to 7 0 to 7 – – P16T52 P16T51 P16T50 – P16T42 P16T41 P16T40 D7 D6 D5 D4 D3 D2 D1 D0 reserved 16-bit timer 5 interrupt level reserved 16-bit timer 4 interrupt level – X X X – X X X – R[...]

II CORE BLOCK: ITC ( Interrupt Controller) B-II- 5-14 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks E16TC5 E16TU5 – E16TC4 E16TU4 – D7 D6 D5 – 4 D3 D2 D1 – 0 16-bit timer 5 comparison A 16-bit timer 5 comparison B reserved 16-bit timer 4 comparison A 16-bit timer 4 comparison B reserved 0 0 ?[...]

II CORE BLOCK: ITC ( Interrupt Controller) S1C33210 FUNCTION PART EPSON B-II- 5-15 Name Address Register name Bit Function Setting Init. R/W Remarks – FP7 FP6 FP5 FP4 FCTM FADE D7 – 6 D5 D4 D3 D2 D1 D0 reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A/D converter – – X X X X X X – R/W R/W R/W R/W R/W R/W 0 when be[...]

II CORE BLOCK: ITC ( Interrupt Controller) B-II- 5-16 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks HSD1S3 HSD1S2 HSD1S1 HSD1S0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 D7 D6 D5 D4 D3 D2 D1 D0 High-speed DMA Ch.1 trigger set-up High-speed DMA Ch.0 trigger set-up 0 0 0 0 0 0 0 0 R/W R/W 0040298 (B) 0 1 2 3 4 5 6 7[...]

II CORE BLOCK: ITC ( Interrupt Controller) S1C33210 FUNCTION PART EPSON B-II- 5-17 Name Address Register name Bit Function Setting Init. R/W Remarks T8CH5S0 SIO3TS0 T8CH4S0 SIO3RS0 SIO2TS0 SIO3ES0 SIO2RS0 SIO2ES0 D7 D6 D5 D4 D3 D2 D1 D0 8-bit timer 5 underflow SIO Ch.3 transmit buffer empty 8-bit timer 4 underflow SIO Ch.3 receive buffer full SIO C[...]

II CORE BLOCK: ITC ( Interrupt Controller) B-II- 5-18 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – A10BW1 A10BW0 A10DRA A9DRA A10SZ A10DF1 A10DF0 – A10WT2 A10WT1 A10WT0 DF-B DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 reserved Areas 10 – 9 burst ROM burst read cycle wait control Area 10 burst ROM selec[...]

II CORE BLOCK: ITC ( Interrupt Controller) S1C33210 FUNCTION PART EPSON B-II- 5-19 Fxxx : Interrupt factor flag Indicate the status of interrupt factors generated. When read Read "1": Interrupt factor ge nerated Read "0": No interrupt factor generated When written using the reset-only method (default) Write "1": Factor[...]

II CORE BLOCK: ITC ( Interrupt Controller) B-II- 5-20 EPSON S1C33210 FUNCTION PART DExxx : IDMA enable register Enable or disable the IDMA request. When using the set-only method (default) Write "1": IDMA enabled Write "0": Not changed Read: Valid When using the read/write method Write "1": IDMA enabled Write "0&q[...]

II CORE BLOCK: ITC ( Interrupt Controller) S1C33210 FUNCTION PART EPSON B-II- 5-21 DENONLY : IDMA enable register set method selection (D2) / Flag set/reset method select register (0x4029F) Select the method for setting the IDMA enable registers. Write "1": Set-only method Write "0": Read/write method Read: Valid With the set-on[...]

II CORE BLOCK: ITC ( Interrupt Controller) B-II- 5-22 EPSON S1C33210 FUNCTION PART SIO2TS0: SIO Ch.2 transmit-buffer empty/FP3 interrupt factor switching (D3) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.2 transmit-buffer empty Write "0": FP3 input Read: Valid Set t[...]

II CORE BLOCK: ITC ( Interrupt Controller) S1C33210 FUNCTION PART EPSON B-II- 5-23 SIO2RS1: SIO Ch.2 receive-buffer full/TM16 Ch.5 compare B interrupt factor switching (D0) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.2 receive-buffer full Write "0": TM16 Ch.5 com[...]

II CORE BLOCK: ITC ( Interrupt Controller) B-II- 5-24 EPSON S1C33210 FUNCTION PART SIO3ES1: SIO Ch.3 receive error/TM16 Ch.3 compare A interrupt factor switching (D5) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.3 receive error Write "0": TM16 Ch.3 compare A Read:[...]

II CORE BLOCK: ITC ( Interrupt Controller) S1C33210 FUNCTION PART EPSON B-II- 5-25 TTBR09 – TTBR00 : Trap table base address [9:0] (D[9:0]) / TTBR low-order register (0x48134[HW]) TTBR15 – TTBR10 : Trap table base addres s [15:10] (D[F:A]) / TTBR low-order register (0x48134[HW]) TTBR2B – TTBR20 : Trap table base address [27:16] (D[B:0]) / TTB[...]

II CORE BLOCK: ITC ( Interrupt Controller) B-II- 5-26 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK.[...]

II CORE BLOCK: CLG (Clock Generator) S1C33210 FUNCTION PART EPSON B-II- 6-1 II-6 CLG (Clock Gene rato r) This section describes the method for controlling the system clock. Configuration of Clock Generator The C33 Core Block has a built-in clock generator that consists of a high-speed oscillation circuit (OSC3) and a PLL. The high-speed (OSC3) osci[...]

II CORE BLOCK: CLG (Clock Generator) B-II- 6-2 EPSON S1C33210 FUNCTION PART I/O Pins of Clock Generator Table 6.1 lists the I/O pins of the clock generator. Table 6 .1 I/O Pins of Clock Generator Pin name I/O Function OSC3 I High-speed (OSC3) oscillation input pin Crystal/ceramic oscillation or external cl ock input OSC4 O High-speed (OSC3) oscilla[...]

II CORE BLOCK: CLG (Clock Generator) S1C33210 FUNCTION PART EPSON B-II- 6-3 PLL The PLL inputs the OSC3 clock and multiply its frequency. The multiply mode should be set using the PLLS[1:0] pins according to the OSC3 clock frequency. Table 6 .2 Setting the PLLS[1:0] Pins PLLS1 PLLS0 Mode fin (OSC3 clock) fout 11 x 2 10 to 25 MHz 20 to 50 MHz 01 x 4[...]

II CORE BLOCK: CLG (Clock Generator) B-II- 6-4 EPSON S1C33210 FUNCTION PART Setting and Switching Over the CPU Operating Clock Setting the CPU operating clock frequency When operating the CPU with the high-speed (OSC3) clock, the operating frequency can be switched over in four steps. Use CLKDT[1:0] (D[7:6]) / Power control register (0x40180) for t[...]

II CORE BLOCK: CLG (Clock Generator) S1C33210 FUNCTION PART EPSON B-II- 6-5 Power-Control Register Protection Flag The power-control register at address 0x40180, which is used to control the oscillation circuits and the CPU operating clock, is normally disabled against writing in order to prevent it from mal functioning due to unnecessary writing. [...]

II CORE BLOCK: CLG (Clock Generator) B-II- 6-6 EPSON S1C33210 FUNCTION PART I/O Memory of Clock Generator Table 6.4 lists the control bits of clock generator. Table 6 .4 Control Bits of Clock Generator Name Address Register name Bit Function Setting Init. R/W Remarks CLKDT1 CLKDT0 PSCON – CLKCHG SOSC3 SOSC1 D7 D6 D5 D4 – 3 D2 D1 D0 System clock[...]

II CORE BLOCK: CLG (Clock Generator) S1C33210 FUNCTION PART EPSON B-II- 6-7 CLKCHG : CPU operating clock switch (D2) / Power control register (0x40180) Selects the CPU operating cl ock. Write "1": OSC3 clock Write "0": OSC1 clock Read: Valid The OSC3 clock is selected as the CPU operating clock by writing "1" to CLKCHG[...]

II CORE BLOCK: CLG (Clock Generator) B-II- 6-8 EPSON S1C33210 FUNCTION PART The following shows the operating status in HALT mode (basic mode and HALT2 mode) and SLEEP mode. Table 6 .6 Operating Status in Standby Mode Standby mode Operating status Reactivating factor HALT mode Basic mode • The CPU clock is stopped. (CPU stop status) • BCU clock[...]

II CORE BLOCK: CLG (Clock Generator) S1C33210 FUNCTION PART EPSON B-II- 6-9 Programming Notes (1) Immediately after the high-speed (OS C3) oscillation circuit is turned on, a certain period of time is required for oscillation to stabilize (for a 3.3-V crystal resonator, this time is 10 ms max.). To prevent the device from operating erratically, do [...]

II CORE BLOCK: CLG (Clock Generator) B-II- 6-10 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK.[...]

II CORE BLOCK: DBG (Debug Unit) S1C33210 FUNCTION PART EPSON B-II- 7-1 II-7 DBG (Debug Unit) Debug Circuit The C33 Core Block has a built-in debug circuit. This functional block is provided to simply realize an advanced software development environment. Note : The debug circuit does not work during normal operation. To construct a software developm[...]

II CORE BLOCK: DBG (Debug Unit) B-II- 7-2 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK.[...]

S1C33210 FUNCTION PART III PERIPHERAL BLOCK[...]

[...]

III PERIPHERAL BLOCK : INTRODUCTION S1C33210 FUNCTION PART EPSON B-III- 1-1 III-1 INT RODUCTION The C33 peripheral block consists of a prescaler, six 8-bit programmable timer channels, six 16-bit programmable timer channels including watchdog timer and event counter functions, four serial interface channels, input and I/O ports, a low-speed (OSC1) [...]

III PERIPHERAL BLOCK : INTRODUCTION B-III- 1-2 EPSON S1C33210 FUNC TION PART THIS PAGE IS BLANK.[...]

III PERIPHERAL BLOCK : PRESCALER S1C33210 FUNCTION PART EPSON B-III- 2-1 III-2 PRESC ALER Configuration of Prescaler The prescaler divides the source clock (OSC3/PLL output clock or OSC1 clock) to generate t he clocks for the internal peripheral circuits. The prescaler division ratio can be selected for each peripheral circuit in a program. A clock[...]

III PERIPHERAL BLOCK : PRESCALER B-III- 2-2 EPSON S1C33210 FUNCTION PART Selecting Division Ratio and Output Control for Prescaler The prescaler has registers for selecting the division ratio and clock output control separately for each peripheral circuit described above, allowing each peripheral circuit to be controlled. The prescaler's divis[...]

III PERIPHERAL BLOCK : PRESCALER S1C33210 FUNCTION PART EPSON B-III- 2-3 I/O Memory of Prescaler Table 2.3 shows the control bits of the prescaler. Table 2 .3 Control Bits of Prescaler Name Address Register name Bit Function Setting Init. R/W Remarks – P8TPCK5 P8TPCK4 D7 – 2 D1 D0 reserved 8-bit timer 5 clock selection 8-bit timer 4 clock selec[...]

III PERIPHERAL BLOCK : PRESCALER B-III- 2-4 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – – P16TON3 P16TS32 P16TS31 P16TS30 D7 – 4 D3 D2 D1 D0 reserved 16-bit timer 3 clock control 16-bit timer 3 clock division ratio selection – 0 0 0 0 – R/W R/W 0 when being read. θ : selected by Presca[...]

III PERIPHERAL BLOCK : PRESCALER S1C33210 FUNCTION PART EPSON B-III- 2-5 Name Address Register name Bit Function Setting Init. R/W Remarks 1 On 0 Off P8TON3 P8TS32 P8TS31 P8TS30 P8TON2 P8TS22 P8TS21 P8TS20 D7 D6 D5 D4 D3 D2 D1 D0 8-bit timer 3 clock control 8-bit timer 3 clock division ratio selection 8-bit timer 2 clock control 8-bit timer 2 clock[...]

III PERIPHERAL BLOCK : PRESCALER B-III- 2-6 EPSON S1C33210 FUNCTION PART CLGP7 – CLGP0 :Power-control register protection flag ([D[7:0]) / Power control protection register (0x4019E) These bits remove the protection against writing to addresses 0x40180 and 0x40190. Write "0b10010110": Write protection remo ved Write other than the above[...]

III PERIPHERAL BLOCK : PRESCALER S1C33210 FUNCTION PART EPSON B-III- 2-7 P16TON0 : 16-bit timer 0 clock control (D3) / 16-bit timer 0 clock control register (0x40147) P16TON1 : 16-bit timer 1 clock control (D3) / 16-bit timer 1 clock control register (0x40148) P16TON2 : 16-bit timer 2 clock control (D3) / 16-bit timer 2 clock control register (0x40[...]

III PERIPHERAL BLOCK : PRESCALER B-III- 2-8 EPSON S1C33210 FUNCTION PART 1) Blocks that use an operating clock generated by the prescaler • 16-bit programmable timers 0 to 5 (watchdog timer) • 8-bit programmable timers 0 to 5 (DRAM refresh, serial interface) • A/D converter 2) Blocks that use the clock supplied to the prescaler (the prescaler[...]

III PERIPHERAL BLOCK : 8-BIT PROGRAMMABLE T IMERS S1C33210 FUNCTION PART EPSON B-III- 3-1 III-3 8-BIT PROGRAMMA BLE TIMERS Configuration of 8-Bit Programmable Timer The Peripheral Block contains six channels of 8-bit program mable timers (timers 0 to 5). Figure 3.1 shows the structure of the 8-bit programmable timer. Data bus 8-bit reload data regi[...]

III PERIPHERAL BLOCK : 8-BIT PROGRAMMABLE TIMERS B-III- 3-2 EPSON S1C33210 FUNCTION PART Uses of 8-Bit Programmable Timers The down-counter of the 8-bit programmable timer cyclically outputs an underflow signal according to the preset data that is set in the software. This underflow signal is used to generate an interrupt request to the CPU or to c[...]

III PERIPHERAL BLOCK : 8-BIT PROGRAMMABLE T IMERS S1C33210 FUNCTION PART EPSON B-III- 3-3 8-bit programmable timer 2 • Clock supply to the Ch.0 serial interface When using the Ch.0 serial interface in the clock-synchronized master mode or the internal clock-based asynchronous mode, the output clock derived from the underflow signal of the 8-bit p[...]

III PERIPHERAL BLOCK : 8-BIT PROGRAMMABLE TIMERS B-III- 3-4 EPSON S1C33210 FUNCTION PART Control and Operation of 8-Bit Programmable Timer With the 8-bit programmable timer, the following settings must first be made before it starts counting: 1. Setting the output pin (only when necessary) 2. Setting the input clock 3. Setting the preset data (init[...]

III PERIPHERAL BLOCK : 8-BIT PROGRAMMABLE T IMERS S1C33210 FUNCTION PART EPSON B-III- 3-5 Setting preset data (initial counter value) Each timer has an 8-bit down-counter and a reload data register. The reload data register RLDx is used to set the initial value of the down-counter of each timer. Timer 0 reload data: RLD0[7:0] (D[7:0]) / 8-bit timer[...]

III PERIPHERAL BLOCK : 8-BIT PROGRAMMABLE TIMERS B-III- 3-6 EPSON S1C33210 FUNCTION PART When both the timer RUN/STOP control bit (PTRUNx) and the timer preset bit (PSETx) are set to "1" at the same time, the timer starts counting after presetting the reload register value into the coun ter. PTRUNx PSETx RLDx Input clock PTDx7 PTDx6 PTDx5[...]

III PERIPHERAL BLOCK : 8-BIT PROGRAMMABLE T IMERS S1C33210 FUNCTION PART EPSON B-III- 3-7 Control of Clock Output When outputting an und erflow signal of the 8-bit programmable timer to external devices, or when supplying a clock generated by the underflow signal to the serial interface, it is necessary to control the clock output of the timer. Tim[...]

III PERIPHERAL BLOCK : 8-BIT PROGRAMMABLE TIMERS B-III- 3-8 EPSON S1C33210 FUNCTION PART 8-Bit Programmable Timer Interrupts and DMA The 8-bit programmable timer has a function to generate an interrupt based on the underflow stat e of the timer 0 to 3. The timing at which an interrupt is generated is shown in Figure 3.2 in the preceding section. Co[...]

III PERIPHERAL BLOCK : 8-BIT PROGRAMMABLE T IMERS S1C33210 FUNCTION PART EPSON B-III- 3-9 High-speed DMA The underflow interrupt factor of the timer 0 to 3 can also invoke high-speed DMA (HSDMA). The following shows the HSDMA channel number and trigger set-up bit corresponding to the timer 0 to 3: Table 3 .5 HSDMA Trigger Set-up Bits Timer HSDMA ch[...]

III PERIPHERAL BLOCK : 8-BIT PROGRAMMABLE TIMERS B-III- 3-10 EPSON S1C33210 FUNCTION PART I/O Memory of 8-Bit Programmable Timers Table 3.6 shows the control bits of the 8-bit programmable timers. For details on the I/O memory of the prescaler used to set a cl ock, refer to "Prescaler". Table 3 .6 Control Bits of 8-Bit Programmable Timer [...]

III PERIPHERAL BLOCK : 8-BIT PROGRAMMABLE T IMERS S1C33210 FUNCTION PART EPSON B-III- 3-11 Name Address Register name Bit Function Setting Init. R/W Remarks – PTOUT3 PSET3 PTRUN3 D7 – 3 D2 D1 D0 reserved 8-bit timer 3 clock output control 8-bit timer 3 preset 8-bit timer 3 Run/Stop control – 0 – 0 – R/W W R/W 0 when being read. 0 when bei[...]

III PERIPHERAL BLOCK : 8-BIT PROGRAMMABLE TIMERS B-III- 3-12 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – E8TU3 E8TU2 E8TU1 E8TU0 D7 – 4 D3 D2 D1 D0 reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow – – 0 0 0 0 – R/W R/W R/W R/W 0 wh[...]

III PERIPHERAL BLOCK : 8-BIT PROGRAMMABLE T IMERS S1C33210 FUNCTION PART EPSON B-III- 3-13 CFP13 – CFP10 : P1[3:0] pin function selection (D[3:0]) / P1 function select register (0x402D4) Selects the pin that is used to output a timer underflow signal to external devices. Write "1": Underflow signal output pin Write "0": I/O po[...]

III PERIPHERAL BLOCK : 8-BIT PROGRAMMABLE TIMERS B-III- 3-14 EPSON S1C33210 FUNCTION PART PTD07 – PTD00 : Timer 0 counter data (D[7:0]) / 8-bit timer 0 counter data (0x40162) PTD17 – PTD10 : Timer 1 counter data (D[7:0]) / 8-bit timer 1 counter data (0x40166) PTD27 – PTD20 : Timer 2 counter data (D[7:0]) / 8-bit timer 2 counter data (0x4016A)[...]

III PERIPHERAL BLOCK : 8-BIT PROGRAMMABLE T IMERS S1C33210 FUNCTION PART EPSON B-III- 3-15 PTOUT0 : Timer 0 clock output control register (D2) / 8-bit timer 0 control register (0x40160) PTOUT1 : Timer 1 clock output control register (D2) / 8-bit timer 1 control register (0x40164) PTOUT2 : Timer 2 clock output control register (D2) / 8-bit timer 2 c[...]

III PERIPHERAL BLOCK : 8-BIT PROGRAMMABLE TIMERS B-III- 3-16 EPSON S1C33210 FUNCTION PART F8TUx is the interrupt factor flag corresponding to each timer. It is set to "1" when the counter underflows. At this time, if the following conditions are met, an interrupt to the CPU is generated: 1. The corresponding interrupt enable register bit [...]

III PERIPHERAL BLOCK : 8-BIT PROGRAMMABLE T IMERS S1C33210 FUNCTION PART EPSON B-III- 3-17 DE8TU0 : Timer 0 IDMA enable (D2) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x4 0296) DE8TU1 : Timer 1 IDMA enable (D3) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x40296) DE8TU2 : Timer 2 IDMA enable (D4) [...]

III PERIPHERAL BLOCK : 8-BIT PROGRAMMABLE TIMERS B-III- 3-18 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK.[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS S1C33210 FUNCTION PART EPSON B-III- 4-1 III-4 16-BIT PROGRAMMA BLE TIMERS Configuration of 16-Bit Programmable Timer The Peripheral Block contains six systems of 16-bit progr ammable timers (timers 0 to 5). They also have an event counter function using an I/O port pin. Note: On the following pages,[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS B-III- 4-2 EPSON S1C33210 FUNCTION PART I/O Pins of 16-Bit Programmable Timers Table 4.1 shows the input/output pins used for the 16-bit programmable timers. Table 4 .1 I/O Pins of 16-Bit Programmable Timer Pin name I/O Function Function select bit P10/EXCL0/ T8UF0/DST0 I/O I/O port / 16-bit timer 0[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS S1C33210 FUNCTION PART EPSON B-III- 4-3 Uses of 16-Bit Progr ammable Timers The up-counters of the 16-bit programmable timer cyclically output a comparison-match signal in accordance with the comparison data that are set in the software. This signal is used to generate an interrupt request to the CP[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS B-III- 4-4 EPSON S1C33210 FUNCTION PART Control and Operation of 16-Bit Programmable Timer The following settings must first be made before the 16-bit programmable timer starts counting: 1. Setting pins for input/output (only when necessary) 2. Setting input clock 3. Selecting comparison data regist[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS S1C33210 FUNCTION PART EPSON B-III- 4-5 • External clock When using the timer as an event counter by supplying clock pulses from an external source, make sure the event cycle is at least the CPU operating clock period. Selecting comparison data register/buffer The comparison data registers A and B[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS B-III- 4-6 EPSON S1C33210 FUNCTION PART Resetting the counter Each timer includes the PRESETx bit to reset the counter. Timer 0 reset: PRESET0 (D1) / 16-bit timer 0 control register (0x48186) Timer 1 reset: PRESET1 (D1) / 16-bit timer 1 control register (0x4818E) Timer 2 reset: PRESET2 (D1) / 16-bit[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS S1C33210 FUNCTION PART EPSON B-III- 4-7 Controlling Clock Output The timers can generate a TMx signal using the comparison match signals from the counter. Setting the signal active level By default, an active high signal (normal low ) is generated. This logic can be inverted using the OUTINVx bit. W[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS B-III- 4-8 EPSON S1C33210 FUNCTION PART When OUTINVx = "0" (active high): The timer outputs a low level until the counter becomes equal to the comparison data A set in the CRxA register. When the counter is incremented to the next value from the comparison data A, the output pin goes high [...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS S1C33210 FUNCTION PART EPSON B-III- 4-9 16-Bit Programmable Timer Interrupts and DMA The 16-bit programmable timer has a function for generating an interrupt using the comparison match A and B states. The timing at which an inter rupt is generated is shown in Figure 4.2 in the preceding section. Con[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS B-III- 4-10 EPSON S1C33210 FUNCTION PART For IDMA to be invoked, the IDMA request and IDMA enable bits shown in Table 4.5 must be set to "1" in advance. Transfer conditions, etc. must also be set on the IDMA side in advance. Table 4 .5 Control Bits for IDMA Transfer Interrupt factor IDMA r[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS S1C33210 FUNCTION PART EPSON B-III- 4-11 Trap vectors The trap vector addresses for each default interrupt factor are set as shown below: Timer 0 comparison B: 0x0C00078 Timer 0 comparison A: 0x0C0007C Timer 1 comparison B: 0x0C00088 Timer 1 comparison A: 0x0C0008C Timer 2 comparison B: 0x0C00098 Ti[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS B-III- 4-12 EPSON S1C33210 FUNCTION PART I/O Memory of 16-Bit Programmable Timers Table 4.7 shows the control bits of the 16-bit programmable timers. For details on the I/O memory of the prescaler used to set a clock, refer to "Prescaler". Table 4 .7 Control Bits of 16-Bit Programmable Tim[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS S1C33210 FUNCTION PART EPSON B-III- 4-13 Name Address Register name Bit Function Setting Init. R/W Remarks R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.0 Port input 3 Port input 2 Port [...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS B-III- 4-14 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 CFEX0 D7-6 D5 D4 D3 D2 D1 D0 reserved P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10, P11, P13[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS S1C33210 FUNCTION PART EPSON B-III- 4-15 Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR1A15 CR1A14 CR1A13 CR1A12 CR1A11 CR1A10 CR1A9 CR1A8 CR1A7 CR1A6 CR1A5 CR1A4 CR1A3 CR1A2 CR1A1 CR1A0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 1 comparison data A[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS B-III- 4-16 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR2B15 CR2B14 CR2B13 CR2B12 CR2B11 CR2B10 CR2B9 CR2B8 CR2B7 CR2B6 CR2B5 CR2B4 CR2B3 CR2B2 CR2B1 CR2B0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 2 comparison data B[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS S1C33210 FUNCTION PART EPSON B-III- 4-17 Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 TC315 TC314 TC313 TC312 TC311 TC310 TC39 TC38 TC37 TC36 TC35 TC34 TC33 TC32 TC31 TC30 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 3 counter data TC315 = MSB TC30 = L[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS B-III- 4-18 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – SELFM4 SELCRB4 OUTINV4 CKSL4 PTM4 PRESET4 PRUN4 D7 D6 D5 D4 D3 D2 D1 D0 reserved 16-bit timer 4 fine mode selection 16-bit timer 4 comparison buffer 16-bit timer 4 output inversion 16-bit t[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS S1C33210 FUNCTION PART EPSON B-III- 4-19 CFP16 – CFP10 : P1[6:0] pin function selection (D[6:0]) / P1 function select register (0x402D4) Selects the pin to be used for input of an external count clock to the timer. Write "1": Clock input pin Write "0": I/O port pin Read: Valid [...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS B-III- 4-20 EPSON S1C33210 FUNCTION PART SELFM0 : Timer 0 fine mode selection (D6) / 16-bit timer 0 control register (0x48186) SELFM1 : Timer 1 fine mode selection (D6) / 16-bit timer 1 control register (0x4818E) SELFM2 : Timer 2 fine mode selection (D6) / 16-bit timer 2 control register (0x48196) S[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS S1C33210 FUNCTION PART EPSON B-III- 4-21 CKSL0 : Timer 0 input clock selection (D3) / 16-bit timer 0 control register (0x48186) CKSL1 : Timer 1 input clock selection (D3) / 16-bit timer 1 control register (0x4818E) CKSL2 : Timer 2 input clock selection (D3) / 16-bit timer 2 control register (0x48196[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS B-III- 4-22 EPSON S1C33210 FUNCTION PART PRUN0 : Timer 0 RUN/STOP control (D0) / 16-bit timer 0 control register (0x48186) PRUN1 : Timer 1 RUN/STOP control (D0) / 16-bit timer 1 control register (0x4818E) PRUN2 : Timer 2 RUN/STOP control (D0) / 16-bit timer 2 control register (0x48196) PRUN3 : Timer[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS S1C33210 FUNCTION PART EPSON B-III- 4-23 TC015 – TC00 : Timer 0 counter data (D[F:0]) / 16-bit timer 0 counter data register (0x48184) TC115 – TC10 : Timer 1 counter data (D[F:0]) / 16-bit timer 1 counter data register (0x4818C) TC215 – TC20 : Timer 2 counter data (D[F:0]) / 16-bit timer 2 c o[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS B-III- 4-24 EPSON S1C33210 FUNCTION PART F16TUx and F16TCx are the interrupt factor flags corresponding to the comparison B and comparison A int errupts, respectively. The flag is set to "1" when each interrupt factor occurs. At this time, if the following conditions are met, an interrupt [...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS S1C33210 FUNCTION PART EPSON B-III- 4-25 DE16TU0, DE16TC0 : Timer 0 IDMA enable (D6, D7) / Port input 0 – 3, HSDMA, 16-bit timer 0 IDMA enable register (0x40294) DE16TU1, DE16TC1 : Timer 1 IDMA enable (D0, D1) / 16-bit timer 1 – 4 IDMA enable register (0x40295) DE16TU2, DE16TC2 : Timer 2 IDMA en[...]

III PERIPHERAL BLOCK : 16-BIT PROGRAMMABLE TIMERS B-III- 4-26 EPSON S1C33210 FUNCTION PART THIS PA GE IS BLANK.[...]

III PERIPHERAL BLOCK : WATCHDOG TIMER S1C33210 FUNCTION PART EPSON B-III- 5-1 III-5 W A TCHDOG TIMER Configuration of Watchdog Timer The Periheral Block incorporates a watchdog timer function to detect the CPU's crash. This function is implemented through the use of the 16-bit programmable timer 0. When this function is enabled, an NMI (nonmas[...]

III PERIPHERAL BLOCK: WATCHDOG TIMER B-III- 5-2 EPSON S1C33210 FUNCTION PART Resetting the watchdog timer When using the watchdog timer, prepare a routine to reset the 16-bit programmable timer 0 before an NMI is generated in a location where it will be periodically processed. Make sure this routine is processed within the NMI generation interval d[...]

III PERIPHERAL BLOCK : WATCHDOG TIMER S1C33210 FUNCTION PART EPSON B-III- 5-3 I/O Memory of Watchdog Timer Table 5.1 shows the control bits of the watchdog timer. Table 5 .1 Control Bits of Watchdog Timer Name Address Register name Bit Function Setting Init. R/W Remarks WRWD – D7 D6–0 EWD write protection – 0 – R/W – 0 when being read. 00[...]

III PERIPHERAL BLOCK: WATCHDOG TIMER B-III- 5-4 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK.[...]

III PERIPHERAL BLOCK : LOW-SPEED (OSC1) OSCILLATION CIRCUIT S1C33210 FUNCTION PART EPSON B-III- 6-1 III-6 LO W-SPEED (OSC1) OSCILLA TION CIRCUIT Configuration of Low-Speed (OSC1) Oscillation Circuit The Peripheral Block has a built-in low-speed (OSC1) oscillation circuit. The low-speed (OSC1) oscillation circuit generates a 32.768-kHz (Typ.) subclo[...]

III PERIPHERAL BLOCK : LOW-SPEED (OSC1) OSCILLATION CIRCUIT B-III- 6-2 EPSON S1C33210 FUNCTION PART Oscillator Types In the low-speed (OSC1) oscillation circuit, either a crystal oscillation or an external clock input can be selected as the type of oscillation circuit. Figure 6.2 shows the structure of the low-speed (OSC1) oscillation circuit. V SS[...]

III PERIPHERAL BLOCK : LOW-SPEED (OSC1) OSCILLATION CIRCUIT S1C33210 FUNCTION PART EPSON B-III- 6-3 Controlling Oscillation The low-speed (OSC1) oscillation circuit can be turned on or off using SOSC1 (D0) / Power control register (0x40180). The oscillation circuit is turned off by writing "0" to SOSC1 and turned back on again by writing [...]

III PERIPHERAL BLOCK : LOW-SPEED (OSC1) OSCILLATION CIRCUIT B-III- 6-4 EPSON S1C33210 FUNCTION PART Power-Control Register Protection Flag The power-control register (SOSC1, SOSC3, CLKCHG, CLKDT[1:0]) at address 0x40180, which is u sed to control the oscillation circuits and the CPU operating clock, is normally disabled against writing in order to [...]

III PERIPHERAL BLOCK : LOW-SPEED (OSC1) OSCILLATION CIRCUIT S1C33210 FUNCTION PART EPSON B-III- 6-5 I/O Memory of Clock Generator Table 6.3 lists the control bits of clock generator. Table 6 .3 Control Bits of Clock Generator Name Address Register name Bit Function Setting Init. R/W Remarks CLKDT1 CLKDT0 PSCON – CLKCHG SOSC3 SOSC1 D7 D6 D5 D4 –[...]

III PERIPHERAL BLOCK : LOW-SPEED (OSC1) OSCILLATION CIRCUIT B-III- 6-6 EPSON S1C33210 FUNCTION PART SOSC1 : Low-speed (OSC1) oscillation control (D0) / Power control register (0x40180) Turns the low-speed (OSC1) oscillation on or off. Write "1": OSC1 oscillation turned on Write "0": OSC1 oscillation turned off Read: Valid The os[...]

III PERIPHERAL BLOCK : LOW-SPEED (OSC1) OSCILLATION CIRCUIT S1C33210 FUNCTION PART EPSON B-III- 6-7 The following shows the o perating status in HALT mode (basic mode and HALT2 mode) and SLEEP mode. Table 6 .4 Operating Status in Standby Mode Standby mode Operating status Reactivating factor HALT mode Basic mode • The CPU clock is stopp ed. (CPU [...]

III PERIPHERAL BLOCK : LOW-SPEED (OSC1) OSCILLATION CIRCUIT B-III- 6-8 EPSON S1C33210 FUNCTION PART CFP14 : P14 function selection (D4) / P1 function select register (0x402D4) Selects the pin function of the P14 I/O port. Write "1": OSC1 clock output pin Write "0": I/O port pin Read: Invalid The P14 pin is set for OSC1 clock out[...]

III PERIPHERAL BLOCK : CLOCK TIMER S1C33210 FUNCTION PART EPSON B-III- 7-1 III-7 CLOCK TIMER Configuration of Clock Timer The clock timer consists of an 8-bit binary counter that is clocked by a 256-Hz signal derived from the low-speed (OSC1) oscillation clock f OSC1 , and second, minute, hour, and day counters, allowing all data (128 Hz to 1 Hz, s[...]

III PERIPHERAL BLOCK : CLOCK TIMER B-III- 7-2 EPSON S1C33210 FUNCTION PART Control and Operation of the Clock Timer Initial setting At initial reset, the clock timer's counter data, setup contents of alarms, and control bits including RUN/STOP, are not initialized. (This does not include the CPU core power on/off flag TCHVOF or OSC1 auto-off f[...]

III PERIPHERAL BLOCK : CLOCK TIMER S1C33210 FUNCTION PART EPSON B-III- 7-3 RUN/STOP the clock timer The clock timer starts counting when "1" is written to TCRUN (D0) / Clock timer Run/Stop register (0x40151) and stops counting when "0" is written. When the clock timer is made to RUN, the 256-Hz clock input is enabled at a fallin[...]

III PERIPHERAL BLOCK : CLOCK TIMER B-III- 7-4 EPSON S1C33210 FUNCTION PART Setting alarm function The clock timer has an alarm function, enabling an interrupt to be generated at a specified time and day. This specification can be made in minutes, hours, and days for each alarm or a combination of multiple alarms. Use TCASE[2:0] (D[4:2) / Clock time[...]

III PERIPHERAL BLOCK : CLOCK TIMER S1C33210 FUNCTION PART EPSON B-III- 7-5 An interrupt can be generated on a specified alarm day at a specified time as described in the preceding section. Interrupts generated by a signal and those generated by an alarm can both be used. However, since the clock timer has only one interrupt factor flag, it is the s[...]

III PERIPHERAL BLOCK : CLOCK TIMER B-III- 7-6 EPSON S1C33210 FUNCTION PART Examples of Use of Clock Timer The following shows examples of use of the clock timer and how to control the timer in each case. To use the clock timer as a timer/counter Example in which while the CPU is inactive, the clock timer is kept operating in order to start again th[...]

III PERIPHERAL BLOCK : CLOCK TIMER S1C33210 FUNCTION PART EPSON B-III- 7-7 I/O Memory of Clock Timer Table 7.5 shows the control bits of the clock timer. Table 7 .5 Control Bits of Clock Timer Name Address Register name Bit Function Setting Init. R/W Remarks – TCRST TCRUN D7 – 2 D1 D0 reserved Clock timer reset Clock timer Run/Stop control – [...]

III PERIPHERAL BLOCK : CLOCK TIMER B-III- 7-8 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 59 minutes (Note) Can be set within 0 – 63. – TCCH5 TCCH4 TCCH3 TCCH2 TCCH1 TCCH0 D7 – 6 D5 D4 D3 D2 D1 D0 reserved Clock timer minute comparison data TCCH5 = MSB TCCH0 = LSB – X X X X X X – R/W[...]

III PERIPHERAL BLOCK : CLOCK TIMER S1C33210 FUNCTION PART EPSON B-III- 7-9 TCRUN : Clock timer RUN/STOP control (D0) / Clock timer Run/Stop register (0x40151) Controls the RUN/STOP of the clock timer. Write "1": RUN Write "0": STOP Read: Valid The clock timer is made to start counting by writing "1" to the TCRUN regist[...]

III PERIPHERAL BLOCK : CLOCK TIMER B-III- 7-10 EPSON S1C33210 FUNCTION PART TCASE2 – TCASE0 : Alarm factor select register (D[4:2]) / Clock timer interrupt control register (0x40152) Selects the factor for which an alarm is to be generated. Table 7 .7 Selecting Alarm Factor TCASE2 TCASE1 TCASE0 Alarm factor X X 1 Minute alarm X 1 X Hour alarm 1 X[...]

III PERIPHERAL BLOCK : CLOCK TIMER S1C33210 FUNCTION PART EPSON B-III- 7-11 ECTM : Clock timer interrupt enable (D1) / Port input 4 – 7, clock timer, A/D interrupt enable register (0x40277) Enables or disables generation of an interrupt to the CPU. Write "1": Interrupt enabled Write "0": Interrupt disabled Read: Valid This bit[...]

III PERIPHERAL BLOCK : CLOCK TIMER B-III- 7-12 EPSON S1C33210 FUNCTION PART Programming Notes (1) The low-speed (OSC1) oscillation circuit, which is the clock source for the clock timer, requires a muxmum of three seconds for its oscillation to stabilize after it is started up. Therefore, immediately after power-on, wait until the oscillation stabi[...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-1 III-8 SERIAL INTERFACE Configuration of Serial Interfaces Features of Serial Interfaces The Peripheral Block contains four channels (Ch.0, Ch.1, Ch.2 and Ch.3) of serial interfaces, the features of which are described below. The only differences between these four seria[...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-2 EPSON S1C33210 FUNCTION PART I/O Pins of Serial Interface Table 8.1 lists the I/O pins used by the serial interface . Table 8 .1 Serial-Interface Pin Configuration Pin name I/O Function Function select bit P00/SIN0 I/O I/O port / Serial IF Ch.0 data input CFP00(D0)/P0 function select register(0x402D[...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-3 Method for setting the serial-interface input/output pins All o f the pins used in the serial interface are shared with I/O ports. At cold start, they are all set for I/O port pins P0x (function select bit Pxx, CFPxx = "0"). When using the serial interface, ma[...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-4 EPSON S1C33210 FUNCTION PART Clock-Synchronized Interface Outline of Clock-Synchronized Interface In the clock-synchronized transfer mode, 8 bits of data are synchronized to the common clock on both the transmit and receive sides when the data is transferred. Since the transmit and receive units bot[...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-5 Setting Clock-Synchronized Interface When performing clock-synchronized transfers via the serial interface, the following settings must be made before data transfer is actually begun: 1. Setting input/output pins 2. Setting the interface mode 3. Setting the transfer mod[...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-6 EPSON S1C33210 FUNCTION PART RLD = f PSCIN × pdr - 1 (Eq. 1) 2 × bps RLD: Reload data register setup value of the 8-bit programmable timer f PSCIN : Prescaler input clock frequency (Hz) bps: Transfer rate (bits/second) pdr: Division ratio of the prescaler Note: The division ratios selected by the [...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-7 Control and Operation of Clock-Synchronized Transfer Transmit control (1) Enabling transmit operation Use the transmit-enable bit TXENx for transmit control. Ch.0 transmit-enable: TXEN0 (D7) / Serial I/F Ch.0 control register (0x401E3) Ch.1 transmit-enable: TXEN1 (D7) /[...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-8 EPSON S1C33210 FUNCTION PART • Clock-synchronized master mode The timing at which the device starts transmitting in the master mode is as follows: When #SRDY is on a low level while TDBEx = "0" (the transmit-data register contains data written to it) or when TDBEx is set to "0"[...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-9 The #SRDYx signal is returned to a high level at this point. 3. The data in the shift register is shifted 1 bit by the next falling edge of the clock, and the bit following the LSB is output from SOUTx. This operation is repeated until all 8 bits of data are transmitted[...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-10 EPSON S1C33210 FUNCTION PART Ch.0 receive data buffer full: RDBF0 (D0) / Serial I/F Ch.0 status register (0x401E2) Ch.1 receive data buffer full : RDBF1 (D0) / Serial I/F Ch.1 status register (0x401E7) Ch.2 receive data buffer full: RDBF2 (D0) / Serial I/F Ch.2 status register (0x401F2) Ch.3 receiv[...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-11 1. After setting the #SRDYx signal to a low level (ready to receive), the slave waits for clock input from the master. 2. The master device outputs each bit of data synchronously with the falling edges of the clock. The LSB is output first. 3. This serial interface tak[...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-12 EPSON S1C33210 FUNCTION PART Asynchronous Interface Outline of Asynchronous Interface Asynchronous transfers are performed by adding a start bit and a stop bit to the start and end points of each serial- converted data. With this method, there is no need to use a clock that is fully synchronized on[...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-13 Setting Asynchronous Interface When performing asynchronous transfer via the serial interface, the following must be done before data transfer can be started: 1. Setting input/output pins 2. Setting the interface mode 3. Setting t he transfer mode 4. Setting the input [...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-14 EPSON S1C33210 FUNCTION PART Any desired clock frequency can be obtained by setting the prescaler division ratio and the reload data of the 8-bit programmable timer as necessary. The relationship between the contents of these setting and the transfer rate is expressed by Eq. 2. The 8-bit p rogramma[...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-15 • Sampling clock In the asynchronous mode, TCLK (the clock output by the 8-bit progr ammable timer or input from the #SCLKx pin for Ch. 0 and Ch. 2) is internally divided in the serial interface, in order to create a sampling clock. A 1/16 division ratio is selected [...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-16 EPSON S1C33210 FUNCTION PART Setting the data format In the asynchronous mode, the data length is 7 or 8 bits as determined by the transfer mode set. The start bit is fixed at 1. The stop and parity bits can be set as shown in the Table 8.5 using the foll owing control bits: Table 8 .5 Serial I/F C[...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-17 The transfer status can be checked using the transmit-completion flag (TENDx). Ch.0 transmit-completion flag: TEND0 (D5) / Serial I/F Ch.0 status register (0x401E2) Ch.1 transmit-completion flag: TEND1 (D5) / Serial I/F Ch.1 status register (0x4 01E7) Ch.2 transmit-com[...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-18 EPSON S1C33210 FUNCTION PART Receive control (1) Enabling receive operations Use the receive-enable bit RXENx for receive control. Ch.0 receive-enable: RXEN0 (D6) / Serial I/F Ch.0 control register (0x401E3) Ch.1 receive-enable: RXEN1 (D6) / Serial I/F Ch.1 control register (0x401E8) Ch.2 receive-e[...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-19 Note : The receive operation is terminated when the first stop bit is sampled even if the stop bit is configured with two bits. • Successive receive operations When the data received in the shift register is transferred to the receive data register, RDBFx is set to &[...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-20 EPSON S1C33210 FUNCTION PART • Overrun error If during successive receive operations, a receive operation for the n ext data is completed before the receive data register is read out, the receive data register is overwritten with the new data. Therefore, the receive data register must always be r[...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-21 IrDA Interface Outline of IrDA Interface Each channel of the serial interface contains a PPM modulator circuit, allowing an infrared-ray communication circuit to be configured based on IrDA 1.0 simply by adding a simple external circuit. PPM Modulator SOUTx LED TXD LED[...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-22 EPSON S1C33210 FUNCTION PART Selecting the IrDA interface function To use the IrDA interface function, select it using the control bits shown below and then set the 8-bit (or 7-bit) asynchronous mode as the transfer mode. Ch.0 IrDA interface-function selection: IRMD0[1:0] (D[1:0]) / Serial I/F Ch.0[...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-23 Control and Operation of IrDA Interface The transmit/receive procedures have been explained in the section on the asynchronous interface, so refer to "Control and Operation of Asynchronous Transfer". The following describes the data modulation and demodulatio[...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-24 EPSON S1C33210 FUNCTION PART Serial Interface Interrupts and DMA The serial interface can generate the following three types of interrupts in each channel: • Transmit-buffer empty interrupt • Receive-buffer full interrupt • Receive-error interrupt Transmit-buffer empty interrupt factor This i[...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-25 The interrupt priority register sets the interrupt priority level of each interrupt source in a range between 0 and 7. An interrupt request to the CPU is accepted only when no o ther interrupt request of a higher priority has been generated. In addition, only when the [...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-26 EPSON S1C33210 FUNCTION PART If an interrupt factor occurs when the IDMA request and enable bits are set to "1", IDMA is invoked. No interrupt request is generated at that point. An interrupt request is generated upon completion of the DMA transfer. The bits can also be set s o as not to [...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-27 • Ch.2 and Ch.3 For Ch.2 and Ch.3, either port input interrupts or 16-bit timer interrupts are selected, and HSDMA is invoked by means of t hose interrupt factor (See Table 8.10). When port input interrupts are selected, Serial I/F Ch.2 receive buffer full correspond[...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-28 EPSON S1C33210 FUNCTION PART I/O Memo ry o f Serial Interface Table 8.14 shows the control bits of the serial interface. For details on the I/O memory of the prescaler that is used to set clocks, as well of that of 8-bit programmable timers, refer to "Prescaler" and "8-Bit Programmab[...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-29 Name Address Register name Bit Function Setting Init. R/W Remarks – TEND1 FER1 PER1 OER1 TDBE1 RDBF1 D7 – 6 D5 D4 D3 D2 D1 D0 – Ch.1 transmit-completion flag Ch.1 flaming error flag Ch.1 parity error flag Ch.1 overrun error flag Ch.1 transmit data buffer empty Ch[...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-30 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks 0x0 to 0xFF(0x7F) TXD37 TXD36 TXD35 TXD34 TXD33 TXD32 TXD31 TXD30 D7 D6 D5 D4 D3 D2 D1 D0 Serial I/F Ch.3 transmit data TXD37(36) = MSB TXD30 = LSB X X X X X X X X R/W 00401F5 (B) Serial I/F Ch.3 transmit[...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-31 Name Address Register name Bit Function Setting Init. R/W Remarks – FSTX1 FSRX1 FSERR1 FSTX0 FSRX0 FSERR0 D7 – 6 D5 D4 D3 D2 D1 D0 reserved SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full SIF Ch.1 receive error SIF Ch.0 transmit buffer empty SIF Ch.0 re[...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-32 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – CFP05 CFP04 CFP03 CFP02 CFP01 CFP00 D7-6 D5 D4 D3 D2 D1 D0 Reserved P05 function selection P04 function selection P03 function selection P02 function selection P01 function selection P00 function sele[...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-33 CFP162: P16 function selection 2 (D1) / Port SIO function extension register (0x402D7) Specifies the function of pin P16/EXCL5/#DMAEND1. Always set to "0." Write "0": P16/EXCL5/#DMAEND1 Read: Valid To use the pin as P16, EXCL5, or #DMAEND1, set this[...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-34 EPSON S1C33210 FUNCTION PART SSCLK2: Serial I/F Ch.2 SCLK selection (D2) / Port SIO function extension register (0x402DB) Switches the function of pin P25/TM3/#SCLK2. Write "1": #SCLK2 Write "0": P25/TM3 Read: Valid To use the pin as #SCLK2, set SSCLK2 (D2 / 0x402DB) to "1&[...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-35 RXD07 – RXD00 : Ch.0 receive data (D[7:0]) / Serial I/F Ch.0 receive data register (0x401E1) RXD17 – RXD10 : Ch.1 receive data (D[7:0]) / Serial I/F Ch.1 receive data register (0x401E6) RXD27 – RXD20 : Ch.2 receive data (D[7:0]) / Serial I/F Ch.2 receive data reg[...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-36 EPSON S1C33210 FUNCTION PART PER0 : Ch.0 parity-error flag (D3) / Serial I/F Ch.0 status register (0x401E2) PER1 : Ch.1 parity-error flag (D3) / Serial I/F Ch.1 status register (0x401E7) PER2 : Ch.2 parity-error flag (D3) / Serial I/F Ch.2 status register (0x401F2) PER3 : Ch.3 parity-error flag (D3[...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-37 RDBF0 : Ch.0 receive data buffer full (D0) / Serial I/F Ch.0 status register (0x401E2) RDBF1 : Ch.1 receive data buffer full (D0) / Serial I/F Ch.1 status register (0x4 01E7) RDBF2 : Ch.2 receive data buffer full (D0) / Serial I/F Ch.2 status register (0x401F2) RDBF3 :[...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-38 EPSON S1C33210 FUNCTION PART EPR0 : Ch.0 parity enable (D5) / Serial I/F Ch.0 control register (0x401E3) EPR1 : Ch.1 parity enable (D5) / Serial I/F Ch.1 control register (0x401E8) EPR2 : Ch.2 parity enable (D5) / Serial I/F Ch.2 control register (0x401F3) EPR3 : Ch.3 parity enable (D5) / Serial I/[...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-39 SSCK0 : Ch.0 input clock selection (D2) / Serial I/F Ch.0 control register (0x401E3) SSCK1 : Ch.1 input clock selection (D2) / Serial I/F Ch.1 control register (0x401E8) SSCK2 : Ch.2 input clock selection (D2) / Serial I/F Ch.2 control register (0x401F3) SSCK3 : Ch.3 i[...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-40 EPSON S1C33210 FUNCTION PART IRTL0 : Ch.0 IrDA output logic inversion (D3) / Serial I/F Ch.0 IrDA register (0x401E4) IRTL1 : Ch.1 IrDA output logic inversion (D3) / Serial I/F Ch.1 IrDA register (0x401E9) IRTL2 : Ch.2 IrDA output logic inversion (D3) / Serial I/F Ch.2 IrDA register (0x401F4) IRTL3 [...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-41 ESERR0, ESRX0, ESTX0 : Ch.0 interrupt enable (D0,D1,D2) / Serial I/F interrupt enable register (0x40276) ESERR1, ESRX1, ESTX1 : Ch.1 interrupt enable (D3,D4,D5) / Serial I/F interrupt enable reg ister (0x40276) Enable or disable interrupt generation to the CPU. Write &[...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-42 EPSON S1C33210 FUNCTION PART RSRX0, RSTX0 : Ch.0 IDMA request (D6, D7) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register (0x40292) RSRX1, RSTX1 : Ch.1 IDMA request (D0, D1) / Serial I/F Ch.1, A/D IDMA request register (0x40293) Specifies whether to invoke IDMA when an interrupt f[...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-43 SIO2RS0: SIO Ch.2 receive-buffer full/FP1 interrupt factor switching (D1) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.2 receive-buffer full Write "0": FP1 input Read: Valid Set to &quo[...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-44 EPSON S1C33210 FUNCTION PART SIO3TS0: SIO Ch.3 transmit-buffer empty/FP6 interrupt factor switching (D6) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.3 transmit-buffer empty Write " 0": FP6 input Read: Valid Set to [...]

III PERIPHERAL BLOCK : SERIAL INTERFACE S1C33210 FUNCTION PART EPSON B-III- 8-45 SIO3TS1: SIO Ch.3 transmit-buffer empty/TM16 Ch.4 compare A interrupt factor switching (D3) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.3 transmit -buffer empty Write "0": TM16 Ch.4 [...]

III PERIPHERAL BLOCK: SERIAL INTERFACE B-III- 8-46 EPSON S1C33210 FUNCTION PART Prog ramming Notes (1) Before setting various serial-interface parameters, make sure the transmit and receive operations are disabled (TXENx = RXENx = "0"). (2) When the serial interface is t ransmitting or receiving data, do not set TXENx or RXENx to "0&[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS S1C33210 FUNCTION PART EPSON B-III- 9-1 III-9 INPUT/OUTPUT PO RTS The Peripheral Block has a total of 42 input/output ports. Although each pin is used for input/output from/to the internal peripheral circuits, some pins can be used as general-purpose input/output ports unless they are used for the periphera[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS B-III- 9-2 EPSON S1C33210 FUNCTION PART Input-Port Pins The input pins concurrently serve as the input pins for peripheral circuits, as shown in Table 9.1. Whether they are used as input ports or for peripheral circuits can be set bit-for-bit using a function select register. All pins not used for periphera[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS S1C33210 FUNCTION PART EPSON B-III- 9-3 I/O Memory of Input Ports Table 9.2 shows the control bits of the input ports. Table 9 .2 Control Bits of Input Ports Name Address Register name Bit Function Setting Init. R/W Remarks – CP4 CFK52 CFK51 CFK50 D7 – 4 D3 D2 D1 D0 reserved CP4 K52 function selection K[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS B-III- 9-4 EPSON S1C33210 FUNCTION PART I/O Ports (P Ports) Structure of I/O Port The Peripheral Block contains 29 bits of I/O ports (P00 to P05, P10 to P16, P20 to P27, P30 to P35) that can be directed for input or output through the use of a program. Figure 9.2 shows the structure of a typical I/O port. V[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS S1C33210 FUNCTION PART EPSON B-III- 9-5 Pin name I/O Pull-up Function Function select bit P20/#DRD I/O – I/O port / #DRD output CFP20(D0)/P2 function select register(0x402D8) P21/#DWE/ #GAAS I/O – I/O port / #DWE output / GA address strobe output (Ex) CFP21(D1)/P2 function select register(0x402D8) CFEX2[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS B-III- 9-6 EPSON S1C33210 FUNCTION PART I/O Memory of I/O Ports Table 9.4 shows the control bits of the I/O ports. Table 9 .4 Control Bits of I/O Ports Name Address Register name Bit Function Setting Init. R/W Remarks – CFP05 CFP04 CFP03 CFP02 CFP01 CFP00 D7-6 D5 D4 D3 D2 D1 D0 Reserved P05 function selec[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS S1C33210 FUNCTION PART EPSON B-III- 9-7 Name Address Register name Bit Function Setting Init. R/W Remarks – CFP322 CFP152 CFP162 CFP332 D7 – 4 D3 D2 D1 D0 reserved P32 function selection 2 P15 function selection 2 P16 function selection 2 P33 function selection 2 – – 0 0 0 0 – R/W R/W R/W R/W 0040[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS B-III- 9-8 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 CFEX0 D7-6 D5 D4 D3 D2 D1 D0 reserved P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10, P11, P13 port ext[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS S1C33210 FUNCTION PART EPSON B-III- 9-9 IOC05 – IOC00 : P0[5:0] port I/O control (D[5:0]) / P0 port I/O control register (0x402D2) IOC16 – IOC10 : P1[6:0] port I/O control (D[6:0]) / P1 port I/O control register (0x402D6) IOC27 – IOC20 : P2[7:0] port I/O control (D[7:0]) / P2 port I/O control register[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS B-III- 9-10 EPSON S1C33210 FUNCTION PART CFEX0 : P12, P14 function extension (D0) / Port function extension register (0x402DF) CFEX1 : P10, P11, P13 function extension (D1) / Port function extension register (0x402DF) CFEX2 : P21 function extension (D2) / Port function extension register (0x402DF) CFEX3 : P[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS S1C33210 FUNCTION PART EPSON B-III- 9-11 Input Interrupt The input ports and the I/O port s support eight system of port input interrupts and two systems of key input interrupts. Port Input Interrupt The port input interrupt circuit has eight interrupt systems (FPT7– FPT0) and a port can be selected for g[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS B-III- 9-12 EPSON S1C33210 FUNCTION PART Conditions for port input-interrupt generation Each port input interrupt can be generated by the edge or level of the input signal. The SEPTx bit of the edge/level select register (0x402C9) is used for this selection. When SEPTx is set to "1", the FPTx inte[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS S1C33210 FUNCTION PART EPSON B-III- 9-13 Key Input Interrupt The key input interrupt circuit has two interrupt systems (FPK1 and FPK0) and a port group can be se lected for generating each interrupt factor. The interrupt condition can also be set by software. Figure 9.4 shows the configuration of the port i[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS B-III- 9-14 EPSON S1C33210 FUNCTION PART Selecting input pins For the FPK1 interrupt system, a four-bit input pin group can be selected from the four predefined groups. For the FPK0 system, a five-bit input pin group can be selected. Table 9.7 shows the control bits and the selectable groups for each factor[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS S1C33210 FUNCTION PART EPSON B-III- 9-15 Since K50 is masked from interrupt by SMPK00, no interrupt occurs at that point (2) above. Next, because CP4 becomes "0" at (3), an interrupt is generated due to the lack of a match between the data of the input pins K5[2:1] and CP4 that are enabled for int[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS B-III- 9-16 EPSON S1C33210 FUNCTION PART Table 9 .9 Control Bits for IDMA Transfer System IDMA request bit IDMA enable bit FPT7 RP7(D7/0x40293) DEP7(D7/0x40297) FPT6 RP6(D6/0x40293) DEP6(D6/0x40297) FPT5 RP5(D5/0x40293) DEP5(D5/0x40297) FPT4 RP4(D4/0x40293) DEP4(D4/0x40297) FPT3 RP3(D3/0x40290) DEP3(D3/0x40[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS S1C33210 FUNCTION PART EPSON B-III- 9-17 I/O Memory for Input Interrupts Table 9.10 shows the control bits for the port input and key input interrupts. Table 9 .10 Control Bits for Input Interrupts Name Address Register name Bit Function Setting Init. R/W Remarks – 0 to 7 0 to 7 – – PP1L2 PP1L1 PP1L0 [...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS B-III- 9-18 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – FP7 FP6 FP5 FP4 FCTM FADE D7 – 6 D5 D4 D3 D2 D1 D0 reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A/D converter – – X X X X X X – R/W R/W R/W R/W R/W R/W 0 when be[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS S1C33210 FUNCTION PART EPSON B-III- 9-19 Name Address Register name Bit Function Setting Init. R/W Remarks – SPPK11 SPPK10 SPPK01 SPPK00 D7 – 4 D3 D2 D1 D0 reserved FPK1 i nterrupt input port selection FPK0 i nterrupt input port selection – 0 0 0 0 – R/W R/W 0 when being read. 00402CA (B) Key input [...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS B-III- 9-20 EPSON S1C33210 FUNCTION PART SPPT7 – SPPT0 : I nput polarity selection (D[7:0]) / Port interrupt input polarity select register (0x402C8) Selects input signal porarity for port interrupt generation. Write "1": High level or Rising edge Write "0": Low level or Falling edge R[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS S1C33210 FUNCTION PART EPSON B-III- 9-21 SMPK13 – SMPK10 : FPK1 input mask (D[3:0]) / FPK1 input mask register (0x402CF) SMPK04 – SMPK00 : FPK0 input mask (D[4:0]) / FPK0 input mask register (0x402CE) Sets conditions for key-input interrupt generation (interrupt enabled/disabled). Write "1": I[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS B-III- 9-22 EPSON S1C33210 FUNCTION PART FP3 – FP0 : Port input 3 – 0 interrupt factor flag (D[3:0]) / Key input, port input 0 – 3 interrupt factor flag register (0x40280) FP7 – FP4 : Port input 7 – 4 interrupt factor flag (D[5:2]) / Port input 4 – 7, clock timer, A/D interrupt factor flag regis[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS S1C33210 FUNCTION PART EPSON B-III- 9-23 RP3 – RP0 : Port input 3 – 0 IDMA request (D[3:0]) / Port input 0 – 3, high-speed DMA, 16-bit timer 0 IDMA request register (0x40290) RP7 – RP4 : Port input 7 – 4 IDMA request (D[7:4]) / Serial I/F Ch.1, A/D, Port input 4 – 7 IDMA request register (0x4029[...]

III PERIPHERAL BLOCK : INPUT/OUTPUT PORTS B-III- 9-24 EPSON S1C33210 FUNCTION PART (5) When a port input interrupt is used to trigger a restart from HALT2 mode or SLEEP mode, the interrupt will be generated by level detection, even if edge detection is set up. See the "Programming Notes" in the Core Block CLG section for details.[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-1 III-10 Monito red Mobile Access Inte rfaces Configuration of Mobile Access Interfaces Features The C33 peripheral block includes mobile access interfaces with the following features. Used in combination with the software modem module, they support dat[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-2 EPSON S1C33210 FUNCTION PART I/O Pins for Mobile Access Interfaces Table 10.1 lists the I/O pins for the mobile access interfaces. Table 10 .1 I/O Pins for Mobile Access Interfaces Pin Name I/O Function Function Selection Bit DTR O DTR output MSEL pin input is at High level * 1 R[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-3 CTS (CTS input pin) The function of this input pin depends on the communications mode. UART communications interprets this input as the CTS signal from the mobile device. A bit in the communications block modem status register (0x020002A) tracks the i[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-4 EPSON S1C33210 FUNCTION PART List of Pin Functions Table 10.2 lists the five mobile access interface pin configurations specified by the MSEL pin input level and communications macro select (MCRS) register (D[1:0]/0x200000). Table 10 .2 Mobile Access Int erface Pin Configurations[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-5 Communications Mode Next configure the mobile access interface pins with the MSEL pin input level and communications macro select (MCRS) register (D[1:0]/0x200000). (See Table 10.4.) The default MCRS setting, after an initial reset, is 00, which speci[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-6 EPSON S1C33210 FUNCTION PART 64 kbps: 10 ms DCD (frame signal) Frame signal period PIAFS frame period CTS (bit clock, 64 kHz) TXD and RXD (data signals) 5 ms 5 ms 0123 45678 9 (Total 640 bits) Figure 10 .3 PHS Signal Format (2) 32 kbps: 20 ms 125 µ s 125 µ s 125 µ s 0 123 4567[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-7 32 kbps: 20 ms 125 µ s 125 µ s 0123 **** 45 67 **** 89 Note: * These bits are "1" for output. Their value does not matter for input. DCD (frame signal) Frame signal period PIAFS frame period CTS (bit clock, 64 kHz) TXD and RXD (data signal[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-8 EPSON S1C33210 FUNCTION PART PDC Communications Mode Overview The PDC communications mode works in combination with the software modem module to process ARQ frames for data transfers with PDC devices. For a transmit operation, this mode serially transmits 24 bytes of data from on[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-9 bit 7 ¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥ 0x0200580 0x020057E 0x0200540 0x020053E 0x0200500 0x02004FE 0x0200480 0x020047E 0x0200440 0x020043E 0x0200400 Receive Buffer B (32 bytes) Receive Buffer A (32 bytes) Transmit Buffer B (32 bytes) Transmit [...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-10 EPSON S1C33210 FUNCTION PART PDC Communications Control and Operation Transmit Control (1) Enabling transmit operation Setting the transmit enable (TXEN) bit in the PDC command register (D1/ 0x0200102) to "1" enables transmit operation, starting transmission from the s[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-11 PHS Communications Mode Overview The PHS communications mode works in combination with the software modem module to process PIAFS frames for data tr ansfers with PHS devices. For a transmit operation, this mode serially transmits 76 bytes of data fro[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-12 EPSON S1C33210 FUNCTION PART Data Bu ffers PHS communications uses two 80-byte buffers each for transmitting and receiving. Transmit operation uses only the 76 bytes at the start of a buffer; receive operation, all 80. The transmit buffers are write only; the receive buffers, re[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-13 PHS Communications Control and Operation Transmit Control (1) Enabling transmit operation Setting the transmit enable (TXEN) bit in the PHS comma nd register (D0/0x0200200) to "1" enables transmit operation, starting transmission from the s[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-14 EPSON S1C33210 FUNCTION PART HDLC Communications Mode Overview The HDLC communications mode processes HDLC frames for data transfers with PDC devices supporting packets. For a transmit operation, this mode transmits an opening flag pattern, the data from a built-in 8-bit, 4-stag[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-15 HDLC Communica tions Control and Operation Transmit Control (1) Enabling transmit operation Setting the transmit enable (TXENS) bit in the HDLC command register (D6/0x0200308) to "1" enables transmit operation, starting transmission from th[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-16 EPSON S1C33210 FUNCTION PART If the enable bit in the HDLC receive operation settings register (D7/0x020030E) specifies address compariso n, the hardware rejects frames whose address fields do not match the contents of the receive address register. Otherwise, it accepts them all[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-17 (2) HDLC Receive Interrupts (Rx INT) The Rx INT and Sp INT interrupt request timing depends on the receive interrupt setup setting in the HDLC receive interrupt mode settings register (D[1:0]/0x0200312). (a) 00 = interrupt requests on first character[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-18 EPSON S1C33210 FUNCTION PART Mobile Access Interface Interrupts Overview The mobile access interface module generates eight interrupt requests, mapped according to the communications mode under program control to five interrupt request lines to the CPU core. Interrupt Types Tabl[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-19 (5) TXINT = HDLC transmit interrupt Interrupt source The data in the transmit queue or transmit block satisfies the conditions below. Condition 1. The software has not written data for the next frame by the time that the interface sends the second CR[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-20 EPSON S1C33210 FUNCTION PART D. Interrupt source: Idle detect Condition The signal latched into the idle detect changes from "0" to "1." To clear Reset E/S INT command (8) MSINT = Modem status change interrupt Interrupt source Change in modem status input sig[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-21 I/O Memory for Mobile Access Interfaces Table 10.11 lists the contents of the I/O memory for mobile access interfa ces. Table 10 .11 I/O Memory for Mobile Access Interfaces Name Address Register name Bit Function Setting Init. R/W Remarks – MCRS1 M[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-22 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – CP3EN4 CP3EN3 CP3EN2 CP3EN1 CP3EN0 D15 – 5 D4 D3 D2 D1 D0 – Assign UINT4 to CP3 Assign UINT3 to CP3 Assign UINT2 to CP3 Assign UINT1 to CP3 Assign UINT0 to CP3 – – 0 0 0 0 [...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-23 Name Address Register name Bit Function Setting Init. R/W Remarks – RXINT – CRCER RXBS – D15 – 8 D7 D6 – 3 D2 D1 D0 – PHS receive interrupt flag – PHS receive data CRC-32 error flag PHS receive buffer select – – – – – 0 – X [...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-24 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – RXINTS1 RXINTS0 D15 – 2 D1 D0 – HDLC receive interrupt setup – 0 0 – R/W R/W 0 when being read. 0200312 (HW) HDLC receive interrupt mode settings register – 1 1 0 0 1 0 1[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-25 Name Address Register name Bit Function Setting Init. R/W Remarks – RCODE7 RCODE6 RCODE5 RCODE4 RCODE3 RCODE2 RCODE1 RCODE0 D15 – 8 D7 D6 D5 D4 D3 D2 D1 D0 – HDLC residue code – 11111110 11111100 11111000 11110000 11100000 11000000 10000000 R[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-26 EPSON S1C33210 FUNCTION PART BMODE, BHALF, FMODE : PHS signal format (D[2:0]) / Communications block PHS mode settings register (0x02 00010) These bits specify the interface signal format for PHS communications. They are ignored for other communications modes. Use only the combi[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-27 CNT2, CNT1 : Output port data (D[1:0]) /Communications block output port data register (0x020000A) Regardless of the communications macro select (MCRS) register (D[1:0]/0x200000) setting – that is, in all modes – these bits drive the CNT2 and CNT[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-28 EPSON S1C33210 FUNCTION PART SDRI, SURI, SDCTS, SUCTS, SDDCD, SUDCD, SDDSR, SUDSR : Modem status (D[7:0]) / Communications block modem status register (0x020002A) For reads, these bit pairs indicate changes in the input level for the corresponding status bit. SDRI; Read "1&[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-29 INTE : PDC interrupt enable (D1) / PDC interrupt register (0x0200100) PDCINT : PDC interr upt flag(D0) / PDC interrupt register (0x0200100) These bits respectively control and indicate the PDC interrupt requests to the CPU every 20 ms at the falling [...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-30 EPSON S1C33210 FUNCTION PART TXINTE : PHS transmit interrupt enable (D7) / PHS transmit control register (0x0200200) TXBS : PHS transmit buffer select (D1) / PHS transmit control register (0x0200200) TXEN : PHS transmit enable (D0) / PHS transmit co ntrol register (0x0200200) Th[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-31 RXINT : PHS receive interrupt flag (D7) / PHS rec eive status register (0x0200206) CRCER : PHS receive data CRC-32 error flag (D2) / PHS receive status register (0x0200206) RXBS : PHS receive buffer select (D1) / PHS receive status register (0x020020[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-32 EPSON S1C33210 FUNCTION PART ABRTIES : HDLC enable bit for Abort (D7) / HDLC interrupt enable settings register (0x0200304) TXUEIES : HDLC enable bit for Tx underrun/EOM (D6) / HDLC interrupt enable settings register (0x0200304) HUNTIES HDLC enable bit for Hunt (D5) / HDLC inter[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-33 ABRTIEC : HDLC clear enable bit f or Abort (D7) / HDLC clear interrupt enable register (0x0200306) TXUEIEC : HDLC clear enable bit for Tx underrun/EOM (D6) / HDLC clear interrupt enable register (0x0200306) HUNTIEC : HDLC clear enable bit for Hunt(D5[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-34 EPSON S1C33210 FUNCTION PART RXENS : HDLC receive enable (D7) / HDLC transfer settings register (0x0200308) TXENS : HDLC transmit enable (D6) / HDLC transfer settings register (0x0200308) RXIES : HDLC Rx and Sp INT enable (D1) / HDLC transfer settings register (0x0200308) TXIES [...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-35 RXENC : HDLC clear receive enable (D 7) / HDLC cancel transfer register (0x020030A) TXENC : HDLC clear transmit enable (D6) / HDLC cancel transfer register (0x020030A) RXIEC : HDLC clear Rx and Sp INT enable(D1) / HDLC cancel transfer register (0x020[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-36 EPSON S1C33210 FUNCTION PART TXFTH[1:0] : HDLC transmit queue interrupt threshold (D[1:0]) / HDLC transmit queue threshold register (0x020031A) These bits specify the level triggering transmit queue interrupts: from 0 for completely empty to 3 for at least one slot free. RTXUEL [...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-37 RXADD[7:0] : HDLC receive address (D[7:0]) / HDLC receive address register (0x020030C) This register specifies the address for filtering incoming frames based on the byte immediately following the opening flag pattern. If the HDLC receive operation s[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-38 EPSON S1C33210 FUNCTION PART RXINTS[1:0] : HDLC receive interrupt setup (D[1:0]) / HDLC receive interrupt mode settings register (0x0200312) These bits offer a choice of three Rx INT interrupt configurations. (1) RXINTS = 00: Rx INT and Sp INT on first receive character Note tha[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-39 RXD[7:0] : HDLC receive data (D[7:0]) / HDLC receive data register (0x0200316) This read-only register is for reading bytes from the receive queue, updating both the queue and the status registers. (For further details on the latter, see the descript[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-40 EPSON S1C33210 FUNCTION PART ABORT : HDLC Abort detected (D7) / HDLC E/S INT receive status register (0x020032C) TXUE : HDLC Tx underrun/EOM detected (D5) / HDLC E/S INT receive status register (0x020032C) Hunt : HDLC Hunt detected (D1) / HDLC E/S INT receive status register (0x[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES S1C33210 FUNCTION PART EPSON B-III- 10-41 RXOVR : HDLC Rx overrun detected (D7) / HDLC Sp INT receive status register (0x020032E) EOF : HDLC end of frame detected (D6) / HDLC Sp INT receive status register (0x020032E) SHFD : HDLC sho rt frame detected (D0) / HDLC Sp INT receive status regist[...]

III PERIPHERAL BLOCK : MONITORED MOBILE ACCESS INTERFACES B-III- 10-42 EPSON S1C33210 FUNCTION PART Important Notes on Debugging ICD33 debugging mode supports the use of the ICD33MODE signal from the CPU core to hold certain communications block input signals at their current levels and thus simulate suspension of communications. Setting the STOP b[...]

S1C33210 FUNCTION PART IV ANALOG BLOCK[...]

[...]

IV ANALOG BLOCK: INTRODUCTION S1C33210 FUNCTION PART EPSON B-IV-1-1 IV-1 INT RODUCTION The analog block consists of a 10-bit A/D converter with 4 input channels. CORE_PAD Pads C33_SBUS Internal RAM (Area 0) C33 Core Block C33 Internal Memory Block C33 DMA Block PERI_PAD Pads C33_PERI (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interf[...]

IV ANALOG BLOCK: INTRODUCTION B-IV- 1-2 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK.[...]

IV ANALOG BLOCK: A/D CONVERTER S1C33210 FUNCTION PART EPSON B-IV-2-1 IV-2 A/D CONVERTER Features and Structure of A/D Converter The Analog Block contains an A/D converter with the following features: • Conversion method: Successive comparison • Resolution: 10 bits • Input channels: Maximum of 4 • Conversion time: Maximum of 10 µ s (when a [...]

IV ANA LOG BLOCK: A/D CONVERTER B-IV- 2-2 EPSON S1C33210 FUNCTION PART I/O Pins of A/D Converter Table 2.1 shows the pins used by the A/D converter. Table 2 .1 I/O Pins of A/D Converter Pin name I/O Function Function select bit K52/#ADTRG I Input port / AD trigger CFK52(D2)/K5 function select register(0x402C0) K60/AD0 I Input port / AD converter in[...]

IV ANALOG BLOCK: A/D CONVERTER S1C33210 FUNCTION PART EPSON B-IV-2-3 Setting A/D Converter When the A/D converter is used, the following settings must be made before an A/D conversion can be performed: 1. Setting analog input pins 2. Setting the input clock 3. Selecting the analo g-conversion start and end channels 4. Setting the A/D conversion mod[...]

IV ANA LOG BLOCK: A/D CONVERTER B-IV- 2-4 EPSON S1C33210 FUNCTION PART Table 2 .3 Relationship between CS/CE and Input Channel CS2/CE2 CS1/CE1 CS0/CE0 Channel selected 0 1 1 AD3 0 1 0 AD2 0 0 1 AD1 0 0 0 AD0 The CS setting must be less than or equal to the CE setting. Example: Operation of one A/D conversion CS[2:0] = "0", CE[2:0] = "[...]

IV ANALOG BLOCK: A/D CONVERTER S1C33210 FUNCTION PART EPSON B-IV-2-5 Control and Operation of A/D Conversion Figure 2.2 shows the operation of the A/D converter. ADE Trigger ADST A/D operation ADD ADF Conversion-result read OWE Interrupt request AD0 AD0 Sampling Conversion AD1 AD1 Sampling Conversion AD2 AD0 converted data AD1 converted data (When [...]

IV ANA LOG BLOCK: A/D CONVERTER B-IV- 2-6 EPSON S1C33210 FUNCTION PART When a trigger is input, the A/D converter samples and A/D-converts the analog input signal, beginning with the conversion start channel selected by CS[2:0]. Upon completion of the A/D conversion in that channel, the A/D converter stores the conversion result, in 10- bit data re[...]

IV ANALOG BLOCK: A/D CONVERTER S1C33210 FUNCTION PART EPSON B-IV-2-7 A/D Converter Interrupt and DMA Upon completion of A/D conversion in each channel, the A/D converter generates an interrupt and invokes the DMA if necessary. Control registers of the interrupt controller The following shows the interrupt control registers available for the A/D con[...]

IV ANA LOG BLOCK: A/D CONVERTER B-IV- 2-8 EPSON S1C33210 FUNCTION PART Trap vector The A/D converter's interrupt trap-vector default address is set to 0x0C00100. The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137).[...]

IV ANALOG BLOCK: A/D CONVERTER S1C33210 FUNCTION PART EPSON B-IV-2-9 I/O Memory of A/D Converter Table 2.6 shows the control bits of the A/D converter. For details on the I/O memory of the prescaler used to set clocks, refer to "Prescaler". For details on the I/O memory of the programmable timers used for a trigger, refer to "8-Bit P[...]

IV ANA LOG BLOCK: A/D CONVERTER B-IV- 2-10 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – 0 to 7 0 to 7 – – PAD2 PAD1 PAD0 – PSIO12 PSIO11 PSIO10 D7 D6 D5 D4 D3 D2 D1 D0 reserved A/D converter interrupt level reserved Serial interface Ch.1 interrupt level – X X X – X X X – R/W – R/W [...]

IV ANALOG BLOCK: A/D CONVERTER S1C33210 FUNCTION PART EPSON B-IV-2-11 ADD9 – ADD0 : A/D converted data (D[1:0]) / A/D conversion result (high-order) register (0x40241) (D[7:0]) / A/D conversion result (low-order) register (0x40240) Stores the results of A/D conversion. The LSB is stored in ADD0, and the MSB is stored in ADD9. ADD0 and ADD1 are ma[...]

IV ANA LOG BLOCK: A/D CONVERTER B-IV- 2-12 EPSON S1C33210 FUNCTION PART ADF : Conversion-complete flag (D3) / A/D enable register (0x40244) Indicates that A/D conversion has been completed. Read "1": Conversion completed Read "0": Being converted or standing by Write: Invalid This flag is set to "1" when A/D conversion[...]

IV ANALOG BLOCK: A/D CONVERTER S1C33210 FUNCTION PART EPSON B-IV-2-13 ST1 – ST0 : Sampling-time setup (D[1:0]) / A/D sampling register (0x40245) Sets the analog input sampling time. Table 2 .8 Sampling Time ST1 ST0 Sampling Time 1 1 9-clock period 1 0 7-clock period 0 1 5-clock period 0 0 3-clock period The A/D converter input clock is used for c[...]

IV ANA LOG BLOCK: A/D CONVERTER B-IV- 2-14 EPSON S1C33210 FUNCTION PART The interrupt factor flag is set to "1" whenever interrupt generation conditions are met, regardless of how the interrupt enable and interrupt priority registers are set. If the next interrupt is to be accepted after an interrupt has occurred, it is necessary that the[...]

IV ANALOG BLOCK: A/D CONVERTER S1C33210 FUNCTION PART EPSON B-IV-2-15 Programming Notes (1) Before setting the conversion mode, start/end channels, etc. for the A/D converter, be sure to disable the A/D converter (ADE (D2) / A/D enable register (0x40244) = "0"). A cha nge in settings while the A/D converter is enabled could cause it to op[...]

IV ANA LOG BLOCK: A/D CONVERTER B-IV- 2-16 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK.[...]

S1C33210 FUNCTION PART V DMA BLOCK[...]

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V DMA BLOCK: INTRODUCTION S1C33210 FUNCTION PART EPSON B-V- 1-1 V-1 INT RODUCTION The DMA block is configured with two types of DMA controllers: HSDMA (High-Speed DMA) that has on-chip registers fo r controlling DMA command information and IDMA (Intelligent DMA) that uses a memory area for storing DMA command information. CORE_PAD Pads C33_SBUS Int[...]

V DMA BLOCK: INTRODUCTION B-V- 1-2 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK.[...]

V DMA BLOCK: HSDMA (High-Speed DMA) S1C33210 FUNCTION PART EPSON B-V- 2-1 V-2 HSDMA (High-Speed DMA) Functional Outline of HSDMA The DMA Block contains four channels of HSDMA (High-Speed DMA) circuits that support dual-address transfer and single-address transfer methods. Since the control registers required for the DMA function are built into the [...]

V DMA BLOCK: HSDMA (High-Speed DMA) B-V- 2-2 EPSON S1C33210 FUNCTION PART I/O Pins of HSDMA Table 2.1 lists the I/O pins used for HSDMA. Table 2 .1 I/O Pins of HSDMA Pin name I/O Function Function select bit K50/#DMAREQ0 I Input port / High-speed DMA request 0 CFK50(D0)/K5 function select register(0x402C0) K51/#DMAREQ1 I Input port / High-speed DMA[...]

V DMA BLOCK: HSDMA (High-Speed DMA) S1C33210 FUNCTION PART EPSON B-V- 2-3 Programming Control Information The HSDMA operates according to the control information set in the registers. Note that some control bits change their functions according to the address mode. The following explains how to set the contents of control information. Before using [...]

V DMA BLOCK: HSDMA (High-Speed DMA) B-V- 2-4 EPSON S1C33210 FUNCTION PART Block length When using block transfer mode (DxMOD = "10"), the data block length (in units of DATSIZEx) should be set using the BLKLENx[7:0] bits. BLKLEN0[7:0]: Ch. 0 block l ength (D[7:0]) / HSDMA Ch. 0 transfer counter register (0x48220) BLKLEN1[7:0]: Ch. 1 block[...]

V DMA BLOCK: HSDMA (High-Speed DMA) S1C33210 FUNCTION PART EPSON B-V- 2-5 D0ADRL[15:0]: Ch. 0 destination address [15:0] (D[F:0]) / Ch. 0 low-order destination address set-up register (0x48228) D1ADRL[15:0]: Ch. 1 destination address [15:0] (D[F:0]) / Ch. 1 low-order destination address set-up register (0x48238) D2ADRL[15:0]: Ch. 2 destination addr[...]

V DMA BLOCK: HSDMA (High-Speed DMA) B-V- 2-6 EPSON S1C33210 FUNCTION PART Setting the Registers in Single-Address Mode Make sure that the HSDMA channel is disabled (HSx_EN = "0") before seffing the control information. Address mode The address mode select bit DUALMx should be set to "0" (single-address mode). This bit is set to [...]

V DMA BLOCK: HSDMA (High-Speed DMA) S1C33210 FUNCTION PART EPSON B-V- 2-7 Address increment/decrement control The memory addresses can be incremented or decremented when one data transfer is completed. SxIN[1:0] is used to set thi s function. S0IN[1:0]: Ch. 0 memory address control (D[D:C]) / Ch. 0 high-order source address set-up register (0x48226[...]

V DMA BLOCK: HSDMA (High-Speed DMA) B-V- 2-8 EPSON S1C33210 FUNCTION PART Trig ger Facto r A HSDMA tigger factor can be selected fro m among 13 types using the HSDMA trigger set-up register for each channel. This function is supported by the interrupt controller. HSD0S[3:0]: Ch. 0 trigger set-up (D[3:0]) / HSDMA Ch. 0/1 trigger set-up register (0x4[...]

V DMA BLOCK: HSDMA (High-Speed DMA) S1C33210 FUNCTION PART EPSON B-V- 2-9 Operation of HSDMA An HSDMA channel starts data transfer by the selected trigger factor. Make sure that transfer conditions and a trigger factor are set and the HSDMA channel is enabled before starting a DMA transfer. Operation in Dual-Address Mode In dual-address mode, both [...]

V DMA BLOCK: HSDMA (High-Speed DMA) B-V- 2-10 EPSON S1C33210 FUNCTION PART Successive transfer mode The channel for which DxMOD in control information is set to "01" operates in successive transfer mode. In this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. The transfer counter is decr[...]

V DMA BLOCK: HSDMA (High-Speed DMA) S1C33210 FUNCTION PART EPSON B-V- 2-11 Block transfer mode The channel for which DxMOD in control information is set to "10" operates in block transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLENx. If a block[...]

V DMA BLOCK: HSDMA (High-Speed DMA) B-V- 2-12 EPSON S1C33210 FUNCTION PART Operation in Single-Address Mode The operation of each transfer mode is almost the same as that of dual-addr ess mode (see the previous section). However, data read/write operation is performed simultaneously in single-address mode. The following explains the data transfer o[...]

V DMA BLOCK: HSDMA (High-Speed DMA) S1C33210 FUNCTION PART EPSON B-V- 2-13 Timing Chart Dual-address mode (1) SRAM Example: When 2 (RD)/1 (WR) wait cycles are inserted BCLK A[23:0] #CE(src) #CE(dst) #RD #WRH/#WRL #DMAEND source address destination address Read cycle Write cycle Figure 2. 6 #DMAEND Signal Output Timing (SRAM) (2) DRAM Example: Page [...]

V DMA BLOCK: HSDMA (High-Speed DMA) B-V- 2-14 EPSON S1C33210 FUNCTION PART Single-address mode (1) SRAM Example: When 2 (RD)/1 (WR) wait cycles are inserted BCLK A[23:0] #CExx #RD #WRH/#WRL #DMAACK #DMAEND addr Figure 2. 8 #DMAACK/#DMAEND Signal Output Timing (SRAM) (2) Burst ROM Example: When 4-consecutive-burst and 2-wait cycles are set during th[...]

V DMA BLOCK: HSDMA (High-Speed DMA) S1C33210 FUNCTION PART EPSON B-V- 2-15 Interrupt Function of HSDMA The DMA controller can generate an interrupt when the transfer counter in each HSDMA channel reaches 0. Furthermore, channels 0 and 1 can invoke IDMA using their interrupt factor. Control registers of the interrupt controller Table 2.3 shows the c[...]

V DMA BLOCK: HSDMA (High-Speed DMA) B-V- 2-16 EPSON S1C33210 FUNCTION PART Intelligent DMA Intelligent DMA (IDMA) can be invoked by the end-of-transfer interrupt factor of channels 0 and 1 of HSDMA. The following shows the IDMA channels set in HSDMA: IDMA channel Channel 0 end-of-transfer interrupt: 0x05 Channel 1 end-of-transfer interrupt: 0x06 Be[...]

V DMA BLOCK: HSDMA (High-Speed DMA) S1C33210 FUNCTION PART EPSON B-V- 2-17 I/O Memory of HSDMA Table 2.5 shows the control bits of HSDMA. Table 2 .5 Control Bits of HSDMA Name Address Register name Bit Function Setting Init. R/W Remarks – 0 to 7 0 to 7 – – PHSD1L2 PHSD1L1 PHSD1L0 – PHSD0L2 PHSD0L1 PHSD0L0 D7 D6 D5 D4 D3 D2 D1 D0 reserved Hi[...]

V DMA BLOCK: HSDMA (High-Speed DMA) B-V- 2-18 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks HSD1S3 HSD1S2 HSD1S1 HSD1S0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 D7 D6 D5 D4 D3 D2 D1 D0 High-speed DMA Ch.1 trigger set-up High-speed DMA Ch.0 trigger set-up 0 0 0 0 0 0 0 0 R/W R/W 0040298 (B) 0 1 2 3 4 5 6 7 8 9 A B[...]

V DMA BLOCK: HSDMA (High-Speed DMA) S1C33210 FUNCTION PART EPSON B-V- 2-19 Name Address Register name Bit Function Setting Init. R/W Remarks – CFP16 CFP15 CFP14 CFP13 CFP12 CFP11 CFP10 D7 D6 D5 D4 D3 D2 D1 D0 reserved P16 function selection 1 P15 function selection 1 P14 function selection P13 function selection P12 function selection P11 functio[...]

V DMA BLOCK: HSDMA (High-Speed DMA) B-V- 2-20 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – – DUALM0 D0DIR – TC0_H7 TC0_H6 TC0_H5 TC0_H4 TC0_H3 TC0_H2 TC0_H1 TC0_H0 DF DE DD – 8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.0 address mode selection D) Invalid S) Ch.0 transfer direction control reserved Ch.0 t[...]

V DMA BLOCK: HSDMA (High-Speed DMA) S1C33210 FUNCTION PART EPSON B-V- 2-21 Name Address Register name Bit Function Setting Init. R/W Remarks D0MOD1 D0MOD0 D0IN1 D0IN0 D0ADRH11 D0ADRH10 D0ADRH9 D0ADRH8 D0ADRH7 D0ADRH6 D0ADRH5 D0ADRH4 D0ADRH3 D0ADRH2 D0ADRH1 D0ADRH0 DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.0 transfer mode D) Ch.0 destinatio[...]

V DMA BLOCK: HSDMA (High-Speed DMA) B-V- 2-22 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks S1ADRL15 S1ADRL14 S1ADRL13 S1ADRL12 S1ADRL11 S1ADRL10 S1ADRL9 S1ADRL8 S1ADRL7 S1ADRL6 S1ADRL5 S1ADRL4 S1ADRL3 S1ADRL2 S1ADRL1 S1ADRL0 DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.1 source address[15:0[...]

V DMA BLOCK: HSDMA (High-Speed DMA) S1C33210 FUNCTION PART EPSON B-V- 2-23 Name Address Register name Bit Function Setting Init. R/W Remarks D1MOD1 D1MOD0 D1IN1 D1IN0 D1ADRH11 D1ADRH10 D1ADRH9 D1ADRH8 D1ADRH7 D1ADRH6 D1ADRH5 D1ADRH4 D1ADRH3 D1ADRH2 D1ADRH1 D1ADRH0 DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.1 transfer mode D) Ch.1 destinatio[...]

V DMA BLOCK: HSDMA (High-Speed DMA) B-V- 2-24 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks S2ADRL15 S2ADRL14 S2ADRL13 S2ADRL12 S2ADRL11 S2ADRL10 S2ADRL9 S2ADRL8 S2ADRL7 S2ADRL6 S2ADRL5 S2ADRL4 S2ADRL3 S2ADRL2 S2ADRL1 S2ADRL0 DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.2 source address[15:0[...]

V DMA BLOCK: HSDMA (High-Speed DMA) S1C33210 FUNCTION PART EPSON B-V- 2-25 Name Address Register name Bit Function Setting Init. R/W Remarks D2MOD1 D2MOD0 D2IN1 D2IN0 D2ADRH11 D2ADRH10 D2ADRH9 D2ADRH8 D2ADRH7 D2ADRH6 D2ADRH5 D2ADRH4 D2ADRH3 D2ADRH2 D2ADRH1 D2ADRH0 DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.2 transfer mode D) Ch.2 destinatio[...]

V DMA BLOCK: HSDMA (High-Speed DMA) B-V- 2-26 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks S3ADRL15 S3ADRL14 S3ADRL13 S3ADRL12 S3ADRL11 S3ADRL10 S3ADRL9 S3ADRL8 S3ADRL7 S3ADRL6 S3ADRL5 S3ADRL4 S3ADRL3 S3ADRL2 S3ADRL1 S3ADRL0 DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.3 source address[15:0[...]

V DMA BLOCK: HSDMA (High-Speed DMA) S1C33210 FUNCTION PART EPSON B-V- 2-27 Name Address Register name Bit Function Setting Init. R/W Remarks D3MOD1 D3MOD0 D3IN1 D3IN0 D3ADRH11 D3ADRH10 D3ADRH9 D3ADRH8 D3ADRH7 D3ADRH6 D3ADRH5 D3ADRH4 D3ADRH3 D3ADRH2 D3ADRH1 D3ADRH0 DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.3 transfer mode D) Ch.3 destinatio[...]

V DMA BLOCK: HSDMA (High-Speed DMA) B-V- 2-28 EPSON S1C33210 FUNCTION PART IOC16 – IOC15 : P1[6:5] port I/O control (D[6:5]) / P1 I/O control register (0x402D6) Direct the I/O port for input or output. Write "1": Output mode Write "0": Input mode Read: Valid To use the #DMAEND0 pin (channel 0), direct the pin for output by wri[...]

V DMA BLOCK: HSDMA (High-Speed DMA) S1C33210 FUNCTION PART EPSON B-V- 2-29 HSD0S3 – HSD0S0 : Ch. 0 trigger set-up (D[3:0]) / HSDMA Ch. 0/1 trigger set-up register (0x40298) HSD1S3 – HSD1S0 : Ch. 1 trigger set-up (D[7:4]) / HSDMA Ch. 0/1 trigger set-up register (0x40298) HSD2S3 – HSD2S0 : Ch. 2 trigger set-up (D[3:0]) / HSDMA Ch. 2/3 trigger s[...]

V DMA BLOCK: HSDMA (High-Speed DMA) B-V- 2-30 EPSON S1C33210 FUNCTION PART HS0_EN : Ch. 0 enable (D0) / HSDMA Ch. 0 enable register (0x4822C) HS1_EN : Ch. 1 enable (D1) / HSDMA Ch. 1 enable register (0x4823C) HS2_EN : Ch. 2 enable (D2) / HSDMA Ch. 2 enable register (0x4824C) HS3_EN : Ch. 3 enable (D3) / HSDMA Ch. 3 enable register (0x4825C) Enable [...]

V DMA BLOCK: HSDMA (High-Speed DMA) S1C33210 FUNCTION PART EPSON B-V- 2-31 D0MOD1 – D0MOD0 : Ch. 0 transfer mode ( D[F:E]) / Ch. 0 high-order destination address set-up register (0x4822A) D1MOD1 – D1MOD0 : Ch. 1 transfer mode (D[F:E]) / Ch. 1 high-order destination address set-up register (0x4823A) D2MOD1 – D2MOD0 : Ch. 2 transfer mode (D[F:E[...]

V DMA BLOCK: HSDMA (High-Speed DMA) B-V- 2-32 EPSON S1C33210 FUNCTION PART D0IN1 – D0IN0 : Ch. 0 destination address control (D[D:C]) / Ch. 0 high-order destination address set-up register (0x4822A) D1IN1 – D1IN0 : Ch. 1 destination address control (D[D:C]) / Ch. 1 high-order destination address set-up register (0x4823A) D2IN1 – D2IN0 : Ch. 2[...]

V DMA BLOCK: HSDMA (High-Speed DMA) S1C33210 FUNCTION PART EPSON B-V- 2-33 S0ADRL15 – S0ADRL0 : Ch. 0 source address[15:0] (D[F:0]) / Ch. 0 low-order source address set-up register (0x48224) S0ADRH11 – S0ADRH0 : Ch. 0 source address[27:16] (D[B:0]) / Ch. 0 high-order source address set-up register (0x48226) S1ADRL15 – S1ADRL0 : Ch. 1 source a[...]

V DMA BLOCK: HSDMA (High-Speed DMA) B-V- 2-34 EPSON S1C33210 FUNCTION PART EHDM0 : Ch. 0 interrupt enable (D 0) / DMA interrupt enable register (0x40271) EHDM1 : Ch. 1 interrupt enable (D1) / DMA interrupt enable register (0x40271) EHDM2 : Ch. 2 interrupt enable (D2) / DMA interrupt enable register (0x40271) EHDM3 : Ch. 3 interrupt enable (D3) / DM[...]

V DMA BLOCK: HSDMA (High-Speed DMA) S1C33210 FUNCTION PART EPSON B-V- 2-35 RHDM0 : Ch.0 IDMA request (D4) / Port input 0 – 3, HSDMA, 16-bit timer 0 IDMA request register (0x40290) RHDM1 : Ch.1 IDMA request (D5) / Port input 0 – 3, HSDMA, 16-bit timer 0 IDMA request register (0x40290) Specify whether IDMA need to be invoked when an interrupt fac[...]

V DMA BLOCK: HSDMA (High-Speed DMA) B-V- 2-36 EPSON S1C33210 FUNCTION PART Programming Notes (1) When setting the transfer conditions, always make sure the DMA controller is inactive (HSx_EN = "0"). (2) After an initial reset, the interrupt factor flag (FHDMx) becomes indeterminate. Always be sure to reset the flag to prevent interrupts o[...]

V DMA BLOCK: IDMA (Intelligent DMA) S1C33210 FUNCTION PART EPSON B-V- 3-1 V-3 IDMA (Intelligent DMA) Functional Outline of IDMA The DMA Block contains an intelligent DMA (IDMA), a function that allows cont rol information to be programmed in RAM. Up to 128 channels can be programmed, including 31 channels that are invoked by an interrupt factor tha[...]

V DMA BLOCK: IDMA (Intelligent DMA) B-V- 3-2 EPSON S1C33210 FUNCTION PART The contents of control information (3 words) in each channel are shown in the table below. Table 3 .1 IDMA Control Information Word Bit Name Function 1st D31 LNKEN IDMA link enable "1" = Enabled, "0" = Disabled D30 – 24 LNKCHN[6:0] IDMA link field D23 ?[...]

V DMA BLOCK: IDMA (Intelligent DMA) S1C33210 FUNCTION PART EPSON B-V- 3-3 BLKLEN[7:0]: Block size/transfer counter (D[7:0]/1st Word) In block transfer mode, set the size of a block that is transferred i n one operation (in units of DATSIZ). In single transfer and successive transfer modes, set an 8-bit low-order value for the transfer count here. N[...]

V DMA BLOCK: IDMA (Intelligent DMA) B-V- 3-4 EPSON S1C33210 FUNCTION PART DSINC[1:0]: Destination address control (D[29:28]/3rd Word) Set the destination address update format. If the format is set for "address fixed" (00), the destination address is not changed by the performance of a data transfer operation. Even when transferring multi[...]

V DMA BLOCK: IDMA (Intelligent DMA) S1C33210 FUNCTION PART EPSON B-V- 3-5 IDMA Invocation The triggers by which IDMA is invoked have the following three causes: 1. Interrupt factor in an internal peripheral circuit 2. Trigger in the software application 3. Link setting Enabling/disabling DMA transfer The IDMA controller is enabled by writing "[...]

V DMA BLOCK: IDMA (Intelligent DMA) B-V- 3-6 EPSON S1C33210 FUNCTION PART These interrupt factors are used in common for interrupt requests and IDMA invocation requests. To invoke IDMA upon the occurrence of an int errupt factor, set the corresponding bits of the IDMA request and IDMA enable registers shown in the table by writing "1". Th[...]

V DMA BLOCK: IDMA (Intelligent DMA) S1C33210 FUNCTION PART EPSON B-V- 3-7 IDMA invocation request during a DMA transfer An IDMA invocation request to another channel that is generated during a DMA transfer is kept pending until the DMA transfer that was being executed at the time is completed. Since an invocation request is not cleared, new request[...]

V DMA BLOCK: IDMA (Intelligent DMA) B-V- 3-8 EPSON S1C33210 FUNCTION PART Operation of IDMA IDMA has three transfer modes, in each of which data transfer operates differently. Furthermore, an interrupt factor is processed differently depending on the type of trigger. The following describes the operation of IDMA in each transfer mode and how an int[...]

V DMA BLOCK: IDMA (Intelligent DMA) S1C33210 FUNCTION PART EPSON B-V- 3-9 Successive transfer mode The channels for which DMOD in control information is set to "01" operate in successive transfer mode. In this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. The transfer counter is decrem[...]

V DMA BLOCK: IDMA (Intelligent DMA) B-V- 3-10 EPSON S1C33210 FUNCTION PART Block transfer mode The channels for which DMOD in control information is set to "10" operate in block transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLEN. If a block t[...]

V DMA BLOCK: IDMA (Intelligent DMA) S1C33210 FUNCTION PART EPSON B-V- 3-11 Processing of interrupt factors by type of trigger • When invoked by an interrupt factor The interrupt factor flag by which IDMA has been invoked remains set even during a DMA transfer. If the transfer counter is decremented to 0 and DI NTEN = "1" (interrupt enab[...]

V DMA BLOCK: IDMA (Intelligent DMA) B-V- 3-12 EPSON S1C33210 FUNCTION PART Linking If the IDMA channel number to be executed next is set in the IDMA link field "LNKCHN" of control information and LNKEN is set to "1" (link enabled), DMA successive transfer in that IDMA ch annel can be performed. An example of link setting is show[...]

V DMA BLOCK: IDMA (Intelligent DMA) S1C33210 FUNCTION PART EPSON B-V- 3-13 Interrupt Function of Intelligent DMA IDMA can generate an interrupt that causes invocation of IDMA and an interrupt for the completion of IDMA transfer itself. Interrupt when invoked by an interrupt factor If the corresponding bits of the IDMA request and interrupt enable r[...]

V DMA BLOCK: IDMA (Intelligent DMA) B-V- 3-14 EPSON S1C33210 FUNCTION PART Trap vector The trap vector address for an interrupt upon completion of IDMA transfer by default is set to 0x0C00068. The trap table base address can be changed using the TTBR registers (0x48134 to 0x48137). I/O Memory of Intelligent DMA Table 3.3 shows the control bits of I[...]

V DMA BLOCK: IDMA (Intelligent DMA) S1C33210 FUNCTION PART EPSON B-V- 3-15 DBASEL[15:0] : IDMA base address [15:0] (D[F:0]) / IDMA base address low-order register (0x48200) DDBASEH[11:0] : IDMA base address [27:16] (D[B:0]) / IDMA base address high-order register (0x48202) Specify the starting address of the control information to be placed in RAM.[...]

V DMA BLOCK: IDMA (Intelligent DMA) B-V- 3-16 EPSON S1C33210 FUNCTION PART FIDMA : IDMA interrupt factor flag (D2) / D MA interrupt factor flag register (0x40281) Indicate the occurrence status of an IDMA interrupt request. When read Read "1": Interrupt factor occurred Read "0": No interrupt factor occurred When written using re[...]

V DMA BLOCK: IDMA (Intelligent DMA) S1C33210 FUNCTION PART EPSON B-V- 3-17 Programming Notes (1) Before setting the IDMA base address, be sure to disabl e DMA transfers (IDMAEN = "0"). Writing to the IDMA base address register is ignored when the DMA transfer is enabled (IDMAEN = "1"). Also, when the register is read during a DM[...]

V DMA BLOCK: IDMA (Intelligent DMA) B-V- 3-18 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK.[...]

S1C33210 FUNCTION PART Appendix I/O MAP[...]

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APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-1 Name Address Register name Bit Function Setting Init. R/W Remarks – P8TPCK5 P8TPCK4 D7–2 D1 D0 reserved 8-bit timer 5 clock selection 8-bit timer 4 clock selection – 0 0 – R/W R/W 0 when being read. θ : selected by Prescaler clock select register (0x40181) 0040140 (B) 1 θ /1 0 D[...]

APPENDIX: I/O MAP B-APPENDIX- 2 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – – P16TON3 P16TS32 P16TS31 P16TS30 D7 – 4 D3 D2 D1 D0 reserved 16-bit timer 3 clock control 16-bit timer 3 clock division ratio selection – 0 0 0 0 – R/W R/W 0 when being read. θ : selected by Prescaler clock se[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-3 Name Address Register name Bit Function Setting Init. R/W Remarks 1 On 0 Off P8TON3 P8TS32 P8TS31 P8TS30 P8TON2 P8TS22 P8TS21 P8TS20 D7 D6 D5 D4 D3 D2 D1 D0 8-bit timer 3 clock control 8-bit timer 3 clock division ratio selection 8-bit timer 2 clock control 8-bit timer 2 clock division ra[...]

APPENDIX: I/O MAP B-APPENDIX- 4 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – TCHD5 TCHD4 TCHD3 TCHD2 TCHD1 TCHD0 D7 – 6 D5 D4 D3 D2 D1 D0 reserved Clock timer minute counter data TCHD5 = MSB TCHD0 = LSB – X X X X X X – R/W 0 when being read. 0040155 (B) – 0 to 59 minutes Clock timer minu[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-5 Name Address Register name Bit Function Setting Init. R/W Remarks – PTOUT0 PSET0 PTRUN0 D7 – 3 D2 D1 D0 reserved 8-bit timer 0 clock output control 8-bit timer 0 preset 8-bit timer 0 Run/Stop control – 0 – 0 – R/W W R/W 0 when being read. 0 when being read. 0040160 (B) – 1 On [...]

APPENDIX: I/O MAP B-APPENDIX- 6 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – PTOUT3 PSET3 PTRUN3 D7 – 3 D2 D1 D0 reserved 8-bit timer 3 clock output control 8-bit timer 3 preset 8-bit timer 3 Run/Stop control – 0 – 0 – R/W W R/W 0 when being read. 0 when being read. 004016C (B) – 1 On [...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-7 Name Address Register name Bit Function Setting Init. R/W Remarks WRWD – D7 D6 – 0 EWD write protection – 0 – R/W – 0 when being read. 0040170 (B) – 1 Write enabled 0 Write-protect Watchdog timer write- protect register – – – EWD – D7 – 2 D1 D0 – Watchdog timer ena[...]

APPENDIX: I/O MAP B-APPENDIX- 8 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks CLKDT1 CLKDT0 PSCON – CLKCHG SOSC3 SOSC1 D7 D6 D5 D4 – 3 D2 D1 D0 System clock division ratio selection Prescaler On/Off control reserved CPU operating clock switch High-speed (OSC3) oscillation On/Off Low-speed (OSC1) [...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-9 Name Address Register name Bit Function Setting Init. R/W Remarks 0x0 to 0xFF(0x7F) TXD07 TXD06 TXD05 TXD04 TXD03 TXD02 TXD01 TXD00 D7 D6 D5 D4 D3 D2 D1 D0 Serial I/F Ch.0 transmit data TXD07(06) = MSB TXD00 = LSB X X X X X X X X R/W 7-bit asynchronous mode does not use TXD07. 00401E0 (B)[...]

APPENDIX: I/O MAP B-APPENDIX- 10 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks 0x0 to 0xFF(0x7F) TXD17 TXD16 TXD15 TXD14 TXD13 TXD12 TXD11 TXD10 D7 D6 D5 D4 D3 D2 D1 D0 Serial I/F Ch.1 transmit data TXD17(16) = MSB TXD10 = LSB X X X X X X X X R/W 7-bit asynchronous mode does not use TXD17. 00401E5 (B[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-11 Name Address Register name Bit Function Setting Init. R/W Remarks TXEN2 RXEN2 EPR2 PMD2 STPB2 SSCK2 SMD21 SMD20 D7 D6 D5 D4 D3 D2 D1 D0 Ch.2 transmit enable Ch.2 receive enable Ch.2 parity enable Ch.2 parity mode selection Ch.2 stop bit selection Ch.2 input clock selection Ch.2 transfer [...]

APPENDIX: I/O MAP B-APPENDIX- 12 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 D7 D6 D5 D4 D3 D2 D1 D0 A/D converted data (low-order 8 bits) ADD0 = LSB 0x0 to 0x3FF (low-order 8 bits) 0 0 0 0 0 0 0 0 R 0040240 (B) A/D conversion result (low- order) register 0x0[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-13 Name Address Register name Bit Function Setting Init. R/W Remarks – 0 to 7 0 to 7 – – PP1L2 PP1L1 PP1L0 – PP0L2 PP0L1 PP0L0 D7 D6 D5 D4 D3 D2 D1 D0 reserved Port input 1 interrupt level reserved Port input 0 interrupt level – X X X – X X X – R/W – R/W 0 when being read. 0[...]

APPENDIX: I/O MAP B-APPENDIX- 14 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – 0 to 7 0 to 7 – – PSIO02 PSIO01 PSIO00 – P8TM2 P8TM1 P8TM0 D7 D6 D5 D4 D3 D2 D1 D0 reserved Serial interface Ch.0 interrupt level reserved 8-bit timer 0 – 3 interrupt level – X X X – X X X – R/W – R/W 0[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-15 Name Address Register name Bit Function Setting Init. R/W Remarks – EK1 EK0 EP3 EP2 EP1 EP0 D7 – 6 D5 D4 D3 D2 D1 D0 reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 – – 0 0 0 0 0 0 – R/W R/W R/W R/W R/W R/W 0 when being read. 0040270 (B) 1 E[...]

APPENDIX: I/O MAP B-APPENDIX- 16 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – FK1 FK0 FP3 FP2 FP1 FP0 D7 – 6 D5 D4 D3 D2 D1 D0 reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 – – X X X X X X – R/W R/W R/W R/W R/W R/W 0 when being read. 0040280 (B) 1 F[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-17 Name Address Register name Bit Function Setting Init. R/W Remarks R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.0 Port input 3 Port input 2 Port input 1 Port input 0 0 0 0 0 [...]

APPENDIX: I/O MAP B-APPENDIX- 18 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks HSD1S3 HSD1S2 HSD1S1 HSD1S0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 D7 D6 D5 D4 D3 D2 D1 D0 High-speed DMA Ch.1 trigger set-up High-speed DMA Ch.0 trigger set-up 0 0 0 0 0 0 0 0 R/W R/W 0040298 (B) 0 1 2 3 4 5 6 7 8 9 A B C Software t[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-19 Name Address Register name Bit Function Setting Init. R/W Remarks – CP4 CFK52 CFK51 CFK50 D7 – 4 D3 D2 D1 D0 reserved CP4 K52 function selection K51 function selection K50 function selection – – 0 0 0 0 – R/W R/W R/W R/W Undefined when read. Always set to 0. 00402C0 (B) 1 – 0[...]

APPENDIX: I/O MAP B-APPENDIX- 20 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks T8CH5S0 SIO3TS0 T8CH4S0 SIO3RS0 SIO2TS0 SIO3ES0 SIO2RS0 SIO2ES0 D7 D6 D5 D4 D3 D2 D1 D0 8-bit timer 5 underflow SIO Ch.3 transmit buffer empty 8-bit timer 4 underflow SIO Ch.3 receive buffer full SIO Ch.2 transmit buffer e[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-21 Name Address Register name Bit Function Setting Init. R/W Remarks – SCPK04 SCPK03 SCPK02 SCPK01 SCPK00 D7 – 5 D4 D3 D2 D1 D0 reserved FPK04 input comparison FPK03 input comparison FPK02 input comparison FPK01 input comparison FPK00 input comparison – – 0 0 0 0 0 – R/W R/W R/W R[...]

APPENDIX: I/O MAP B-APPENDIX- 22 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10 D7 D6 D5 D4 D3 D2 D1 D0 reserved P16 I/O control P15 I/O control P14 I/O control P13 I/O control P12 I/O control P11 I/O control P10 I/O control – 0 0 0 0 0 0 0 – R/W R/W R[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-23 Name Address Register name Bit Function Setting Init. R/W Remarks – CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 CFEX0 D7-6 D5 D4 D3 D2 D1 D0 reserved P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10, P11, P13 port extended function P12, [...]

APPENDIX: I/O MAP B-APPENDIX- 24 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – A12SZ A12DF1 A12DF0 – A12WT2 A12WT1 A12WT0 DF – 7 D6 D5 D4 D3 D2 D1 D0 reserved Areas 12 – 11 device size selection Areas 12 – 11 output disable delay time reserved Areas 12 – 11 wait control – – 1 8 bits[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-25 Name Address Register name Bit Function Setting Init. R/W Remarks – A6DF1 A6DF0 – A6WT2 A6WT1 A6WT0 – A5SZ A5DF1 A5DF0 – A5WT2 A5WT1 A5WT0 DF – E DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 reserved Area 6 output disable delay time reserved Area 6 wait control reserved Areas 5 ?[...]

APPENDIX: I/O MAP B-APPENDIX- 26 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks 1 Successive 0 Normal – – CEFUNC1 CEFUNC0 CRAS RPRC1 RPRC0 – CASC1 CASC0 – RASC1 RASC0 DF – C DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 reserved reserved #CE pin function selection Successive RAS mode setup DRAM RAS pr[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-27 Name Address Register name Bit Function Setting Init. R/W Remarks – 1 Enabled 0 Disabled 1 Enabled 0 Disabled A18AS A16AS A14AS A12AS – A8AS A6AS A5AS A18RD A16RD A14RD A12RD – A8RD A6RD A5RD DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Area 18, 17 address strobe signal Area 16,[...]

APPENDIX: I/O MAP B-APPENDIX- 28 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR0A15 CR0A14 CR0A13 CR0A12 CR0A11 CR0A10 CR0A9 CR0A8 CR0A7 CR0A6 CR0A5 CR0A4 CR0A3 CR0A2 CR0A1 CR0A0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 0 comparison data A CR0A15 = MSB CR0A0 = LSB X X[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-29 Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR1A15 CR1A14 CR1A13 CR1A12 CR1A11 CR1A10 CR1A9 CR1A8 CR1A7 CR1A6 CR1A5 CR1A4 CR1A3 CR1A2 CR1A1 CR1A0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 1 comparison data A CR1A15 = MSB CR1A0 = LSB X X[...]

APPENDIX: I/O MAP B-APPENDIX- 30 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR2A15 CR2A14 CR2A13 CR2A12 CR2A11 CR2A10 CR2A9 CR2A8 CR2A7 CR2A6 CR2A5 CR2A4 CR2A3 CR2A2 CR2A1 CR2A0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 2 comparison data A CR2A15 = MSB CR2A0 = LSB X X[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-31 Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR3A15 CR3A14 CR3A13 CR3A12 CR3A11 CR3A10 CR3A9 CR3A8 CR3A7 CR3A6 CR3A5 CR3A4 CR3A3 CR3A2 CR3A1 CR3A0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 3 comparison data A CR3A15 = MSB CR3A0 = LSB X X[...]

APPENDIX: I/O MAP B-APPENDIX- 32 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR4A15 CR4A14 CR4A13 CR4A12 CR4A11 CR4A10 CR4A9 CR4A8 CR4A7 CR4A6 CR4A5 CR4A4 CR4A3 CR4A2 CR4A1 CR4A0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 4 comparison data A CR4A15 = MSB CR4A0 = LSB X X[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-33 Name Address Register name Bit Function Setting Init. R/W Remarks 0 to 65535 CR5A15 CR5A14 CR5A13 CR5A12 CR5A11 CR5A10 CR5A9 CR5A8 CR5A7 CR5A6 CR5A5 CR5A4 CR5A3 CR5A2 CR5A1 CR5A0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 5 comparison data A CR5A15 = MSB CR5A0 = LSB X X[...]

APPENDIX: I/O MAP B-APPENDIX- 34 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks DBASEL15 DBASEL14 DBASEL13 DBASEL12 DBASEL11 DBASEL10 DBASEL9 DBASEL8 DBASEL7 DBASEL6 DBASEL5 DBASEL4 DBASEL3 DBASEL2 DBASEL1 DBASEL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IDMA base address low-order 16 bits (Ini[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-35 Name Address Register name Bit Function Setting Init. R/W Remarks TC0_L7 TC0_L6 TC0_L5 TC0_L4 TC0_L3 TC0_L2 TC0_L1 TC0_L0 BLKLEN07 BLKLEN06 BLKLEN05 BLKLEN04 BLKLEN03 BLKLEN02 BLKLEN01 BLKLEN00 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.0 transfer c ounter[7:0] (block transfer mo[...]

APPENDIX: I/O MAP B-APPENDIX- 36 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks D0ADRL15 D0ADRL14 D0ADRL13 D0ADRL12 D0ADRL11 D0ADRL10 D0ADRL9 D0ADRL8 D0ADRL7 D0ADRL6 D0ADRL5 D0ADRL4 D0ADRL3 D0ADRL2 D0ADRL1 D0ADRL0 DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.0 destination address[15:0] S) Inv[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-37 Name Address Register name Bit Function Setting Init. R/W Remarks TC1_L7 TC1_L6 TC1_L5 TC1_L4 TC1_L3 TC1_L2 TC1_L1 TC1_L0 BLKLEN17 BLKLEN16 BLKLEN15 BLKLEN14 BLKLEN13 BLKLEN12 BLKLEN11 BLKLEN10 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.1 transfer c ounter[7:0] (block transfer mo[...]

APPENDIX: I/O MAP B-APPENDIX- 38 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks D1ADRL15 D1ADRL14 D1ADRL13 D1ADRL12 D1ADRL11 D1ADRL10 D1ADRL9 D1ADRL8 D1ADRL7 D1ADRL6 D1ADRL5 D1ADRL4 D1ADRL3 D1ADRL2 D1ADRL1 D1ADRL0 DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.1 destination address[15:0] S) Inv[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-39 Name Address Register name Bit Function Setting Init. R/W Remarks TC2_L7 TC2_L6 TC2_L5 TC2_L4 TC2_L3 TC2_L2 TC2_L1 TC2_L0 BLKLEN27 BLKLEN26 BLKLEN25 BLKLEN24 BLKLEN23 BLKLEN22 BLKLEN21 BLKLEN20 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.2 transfer c ounter[7:0] (block transfer mo[...]

APPENDIX: I/O MAP B-APPENDIX- 40 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks D2ADRL15 D2ADRL14 D2ADRL13 D2ADRL12 D2ADRL11 D2ADRL10 D2ADRL9 D2ADRL8 D2ADRL7 D2ADRL6 D2ADRL5 D2ADRL4 D2ADRL3 D2ADRL2 D2ADRL1 D2ADRL0 DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.2 destination address[15:0] S) Inv[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-41 Name Address Register name Bit Function Setting Init. R/W Remarks TC3_L7 TC3_L6 TC3_L5 TC3_L4 TC3_L3 TC3_L2 TC3_L1 TC3_L0 BLKLEN37 BLKLEN36 BLKLEN35 BLKLEN34 BLKLEN33 BLKLEN32 BLKLEN31 BLKLEN30 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch.3 transfer c ounter[7:0] (block transfer mo[...]

APPENDIX: I/O MAP B-APPENDIX- 42 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks D3ADRL15 D3ADRL14 D3ADRL13 D3ADRL12 D3ADRL11 D3ADRL10 D3ADRL9 D3ADRL8 D3ADRL7 D3ADRL6 D3ADRL5 D3ADRL4 D3ADRL3 D3ADRL2 D3ADRL1 D3ADRL0 DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D) Ch.3 destination address[15:0] S) Inv[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-43 Name Address Register name Bit Function Setting Init. R/W Remarks – MCRS1 MCRS0 D15 – 2 D1 D0 – Master configuration selection 1 1 0 0 1 0 1 0 MCRS[1:0] – Communications mode PHS PDC HDLC UART – 0 0 – R/W 0 when being read. Only valid when MSEL pin input is at High level 0200[...]

APPENDIX: I/O MAP B-APPENDIX- 44 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – CP4EN4 CP4EN3 CP4EN2 CP4EN1 CP4EN0 D15 – 5 D4 D3 D2 D1 D0 – Map UINT4 interrupt requests to CP4 Map UINT3 interrupt requests to CP4 Map UINT2 interrupt requests to CP4 Map UINT1 interrupt requests to CP4 Map UINT0 [...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-45 Name Address Register name Bit Function Setting Init. R/W Remarks – ERES RESINT – RRXINT RTXINT D15 – 8 D7 D6 D5 – 2 D1 D0 – HDLC error reset HDLC E/S interrupt reset – HDLC receive interrupt reset HDLC transmit interrupt reset – – – 0 0 – 0 0 – W W – W W 0 when b[...]

APPENDIX: I/O MAP B-APPENDIX- 46 EPSON S1C33210 FUNCTION PART Name Address Register name Bit Function Setting Init. R/W Remarks – RXINTS1 RXINTS0 D15 – 2 D1 D0 – Receive interrupt operating mode – 0 0 – R/W R/W 0 when being read. 0200312 (HW) HDLC receive interrupt mode settings register – 1 1 0 0 1 0 1 0 RXINTS[1:0] Operating Mode (Not[...]

APPENDIX: I/O MAP S1C33210 FUNCTION PART EPSON B- APPENDIX-47 Name Address Register name Bit Function Setting Init. R/W Remarks – RCODE7 RCODE6 RCODE5 RCODE4 RCODE3 RCODE2 RCODE1 RCODE0 D15 – 8 D7 D6 D5 D4 D3 D2 D1 D0 – Residue Code Number of valid bits in excess residue code bits at end of frame – 11111110 11111100 11111000 11110000 111000[...]

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T echnical Manual S1C33210 ELECTRONIC DEVICES MARKETING DIVISION http://www.epsondevice.com Issue December, 2002 Printed in Japan O B EPSON Electronic Devices Website[...]