Freescale Semiconductor 56F8122 инструкция обслуживания

56F8300 16-bit Hybrid Controllers freescale. com 56F8322/56F8122 Data Sheet Pr eliminary T echnical Data MC56F832 2 Rev. 10.0 10/20 04[...]

56F8322 T echncia l Dat a, Rev . 10.0 2 Free scal e S emic ondu cto r Preliminar y Document Revision History Version History Description of Cha nge Rev 1.0 Pre-Rele ase version, Alpha customers onl y Rev 2.0 Initial Public Rel ease Rev 3.0 Corrected typo in Table 10- 4 , Flash En durance i s 10,000 cy cles. Addres sed addit ional gram mar issues Re[...]

56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 3 Prelimin ary 56F832 2/56F8122 Block Diagram Program Controlle r and H ard wa re Looping Unit Data ALU 16 x 16 + 36 -> 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulator s Addr ess Generation Unit Bit Manipulation Unit 16-Bit 56800E Core Interrupt Controller 4 IRQA Da[...]

56F8322 T echncia l Dat a, Rev . 10.0 4 Free scal e S emic ondu cto r Preliminar y Part 1: Ov erv iew . . . . . . . . . . . . . . . . . . . . . . 5 1.1. 56F8322/56F812 2 Features . . . . . . . . . . . . . 5 1.2. Device Desc ription . . . . . . . . . . . . . . . . . . . . 7 1.3. Award-Winni ng Develo pment Env ironment . 8 1.4. Architecture Block Di[...]

56F8322/56F8122 Features 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 5 Prelimin ary Part 1 Overview 1.1 56F8322/56F8122 Featu res 1.1.1 Hybrid Controller Core • Ef ficie nt 16-bit 56800E family h ybrid cont roller engine wit h dual Harva rd archit ecture • Up to 60 Mil lion Instru ctions Per Second (MIPS) at 60MHz cor e fre[...]

56F8322 T echncia l Dat a, Rev . 10.0 6 Free scal e S emic ondu cto r Preliminar y 1.1.3 Mem ory Note: Features in italics are NOT available in the 56F8122 device. • Harva rd archit ecture permi ts as many a s three simul taneous ac cesses to pr ogram and data me mory • Flas h securit y protectio n • On-chi p memory , incl uding a low-c ost, [...]

Device Descr iption 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 7 Prelimin ary 1.1.5 Energy In formation • Fa bricated in high-dens ity CMOS with 5V -t olerant, TTL-compatib le digit al inputs • On-boa rd 3.3V down to 2.6V voltage regulato r for powering interna l logic and memories • On-c hip reg ulat ors for di gita l a[...]

56F8322 T echncia l Dat a, Rev . 10.0 8 Free scal e S emic ondu cto r Preliminar y is programmable to support a continuously variable PWM frequency. Edge -aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling m ost motor types: ACIM (AC Induction Mot ors); both BDC and [...]

Architecture Block Diagram 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 9 Prelimin ary 1.4 Architecture Blo ck Diagram Note: Features in italics are NOT available in the 56F8122 device and are shaded in the following figures. The 56F8322/56F8122 architecture is shown in Figure 1-1 and Figure 1-2 . Figure 1-1 illustrates how the [...]

56F8322 T echncia l Dat a, Rev . 10.0 10 Free scal e S emic ondu cto r Preliminar y Figure 1-1 S ystem Bus Interfac es Note: Flas h memories are e ncapsulated with in the Fla sh Memory Modu le (FM). Fla sh control i s accompli shed by the I/O to the FM over the peri pheral bu s, while reads and write s are complete d between t he core and th e Flas[...]

Architecture Block Diagram 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 11 Prelimin ary Figure 1-2 Peripheral Subsystem IPBus Time r A SPI 0 ADCA 2 6 SPI 1 GPIO A 4 Interrupt Contro ller To/From IPBus Bridge PWMA SCI 0 3 System P OR Low-V ol tage Interrupt COP Reset COP RESET Quadratur e Decoder 0 4 GPIO B GPIO C FlexCAN SCI 1 4[...]

56F8322 T echncia l Dat a, Rev . 10.0 12 Free scal e S emic ondu cto r Preliminar y Table 1-2 Bus Signal Na mes Name Function Progra m Memory I nterface pdb_m[15 :0] Program d ata bus fo r instruct ion word fetc hes or rea d operatio ns. cdbw[1 5:0] Primary core da ta bus used for prog ram memory writes. (O nly thes e 16 bits of the cd bw[31:0] bu [...]

Product Documentation 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 13 Prelimin ary 1.5 Product Documen tation The documents listed in Table 1-3 are required for a complete description and proper design with the 56F8322 and 56F8122 devices. Documentation is available from local Freescale distributors, Freescale semiconductor sale[...]

56F8322 T echncia l Dat a, Rev . 10.0 14 Free scal e S emic ondu cto r Preliminar y Part 2 Signal/Co nnection Description s 2.1 Introduct ion The input and output signals of the 56F8322 and 56F8122 devices are organized into functional groups, as detailed in Table 2-1 and as illust rated in Figure 2-1 and Figure 2-2 . In Table 2-2 , each table row [...]

Introduction 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 15 Prelimin ary Figure 2-1 56F8322 Signals Identified by Functiona l Group (48-Pin LQFP) V DD_IO V DDA_AD C V SSA_AD C EXT AL (GPIOC0) XT AL (GPIOC1 ) Other Supply Port s PLL and Clock or GPIO JTAG/ EOnCE Port 4 1 4 V CAP 1 - V CA P 2 2 1 1 TCK TMS Quadrature Decoder 0 or[...]

56F8322 T echncia l Dat a, Rev . 10.0 16 Free scal e S emic ondu cto r Preliminar y Figure 2-2 56F8122 Signals Identified by Functiona l Group (48-Pin LQFP) V DD_IO V DDA_AD C V SSA_AD C EXT AL (GPIOC0) XT AL (GPIOC1 ) Other Supply Port s PLL and Clock or GPIO JTAG/ EOnCE Port 4 1 4 V CAP 1 - V CA P 2 2 1 1 TCK TMS Quad Timer A or GPIO T A 0 (G PIO[...]

Signal Pins 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 17 Prelimin ary 2.2 Signal Pins After reset, eac h pin is configured for its primary function (lis ted first). In the 56F8122, after reset, each pin mus t be configured for the desired function. The initialization software will configure each pin for the function listed fi[...]

56F8322 T echncia l Dat a, Rev . 10.0 18 Free scal e S emic ondu cto r Preliminar y EXTAL (GPIOC0) 32 Input/ Schmitt Input/ Outp ut Inpu t Inpu t External Crys tal Oscillator Inp ut — This input can be connec ted to an 8MHz external crystal. If an exte rnal clock i s used, XTAL must b e used as the inp ut and EXTAL connected to V SS . The input c[...]

Signal Pins 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 19 Prelimin ary PHASEA0 (TA0) (GPIOB7) (oscillator_ clock ) 38 Schmitt Inpu t Schmitt Input/ Outp ut Schmitt Input/ Outp ut Outp ut Inpu t Inpu t Inpu t Outp ut Phase A — Quadrature Decoder 0, PHASEA input TA0 — Timer A, Channel 0 Port B GP IO — This GPIO pin can be [...]

56F8322 T echncia l Dat a, Rev . 10.0 20 Free scal e S emic ondu cto r Preliminar y INDEX0 (TA2) (GPIOB5) (SYS_CLK) 36 Schmitt Inpu t Schmitt Input/ Outp ut Schmitt Input/ Outp ut Outp ut Inpu t Inpu t Inpu t Outp ut Index — Quadrature Decoder 0, INDEX input TA2 — Timer A, Channel 2 Port B GP IO — This GPIO pin can be i ndividua lly p rogramm[...]

Signal Pins 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 21 Prelimin ary MOSI0 (GPIOB2) 18 Schmitt Input/ Outp ut Schmitt Input/ Outp ut Tri- stat ed Inpu t SPI 0 M aster Out/Slave In — Thi s serial dat a pin is an output f rom a maste r device and an inp ut to a sl ave devi ce. The m aster devic e places data on the MOSI l in[...]

56F8322 T echncia l Dat a, Rev . 10.0 22 Free scal e S emic ondu cto r Preliminar y PWMA1 (GPIOA1) 4S c h m i t t Outp ut Schmitt Input/ Outp ut Tri- stat ed Inpu t PWM A1 — This is one o f six PWM A output pin s. Port A GPIO - Th is GPIO pin can b e individua lly progra mmed as an input o r output pi n. In the 56F8322 , the default state after r[...]

Signal Pins 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 23 Prelimin ary PWMA4 (MOSI1) (GPIOA4) 8O u t p u t Schmitt Input/ Outp ut Schmitt Input/ Outp ut Tri- stat ed Tri- stat ed Inpu t PWM A4 — This is one o f six PWM A output pin s. SPI 1 M aster Out/Slave In — This seri al data p in is an outp ut from a maste r device a[...]

56F8322 T echncia l Dat a, Rev . 10.0 24 Free scal e S emic ondu cto r Preliminar y V REFP 28 Input/ Outp ut Input/ Outp ut V REFP , V REF MID & V REFN — Inter nal pins for voltage ref erence w hich are brou ght off-chip so that they c an b e b ypassed . C onnect to a 0.1 µ F cerami c low ESR capacito r. V REFMID 27 V REFN 26 CAN_RX (GPIOC2)[...]

Signal Pins 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 25 Prelimin ary IRQA (V PP ) 11 Schmitt Inpu t Inpu t N/A Ex te rn al I n te r ru pt R eq u es t A — T he IRQA input is an a synchronous externa l interrupt request durin g Stop and Wait mode operati on. Durin g other operating mod es, it is a synchroniz ed external inte[...]

56F8322 T echncia l Dat a, Rev . 10.0 26 Free scal e S emic ondu cto r Preliminar y Part 3 On-Chip Clock Synth esis (OCCS) 3.1 Introduct ion Refer to the OCCS chapter of the 56F8300 Per ipheral User Manual for a full descri ption of the OCCS. The material contained here identifies the spe cific features of the OCCS design. 3.2 External Clock Operat[...]

External Clock Operation 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 27 Prelimin ary 3.2.2 Ceramic Resonator (Default) It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can toler ate the r educed signal integrity. A typical c eramic resonator circuit is shown in Fi[...]

56F8322 T echncia l Dat a, Rev . 10.0 28 Free scal e S emic ondu cto r Preliminar y 3.3 Use of On-Ch ip Relaxation Oscillat or An inter nal relaxtion oscillator can s upply the refer ence fr equency whe n a n external freque ncy source of crystal is not used. During a boot or reset sequence, the relaxation oscillator is enabled by default, a nd the[...]

Registers 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 29 Prelimin ary Figure 3-4 Internal Clock Operation 3.5 Registers When referring to the re gister definitions for the O CCS in the 56F8300 Peripheral User Manu al , use the register definitions with the internal Relaxation Oscillator, since the 56F8322 and 56F8122 contain th[...]

56F8322 T echncia l Dat a, Rev . 10.0 30 Free scal e S emic ondu cto r Preliminar y Part 4 Memory Map 4.1 Introduct ion The 56F8322 and 56F8122 devices are 16-bit m otor-control chips based on the 56800E core. These parts use a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM and Flash memories are use[...]

Interrupt Vector Table 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 31 Prelimin ary Note: Program RAM is NOT available on the 56F8122 device. 4.3 Interrupt Vector Tab le Tabl e 4-3 provides the device’s reset and interrupt priority structure, including on-chip p eripherals. The table is o rganized with higher-priority vectors [...]

56F8322 T echncia l Dat a, Rev . 10.0 32 Free scal e S emic ondu cto r Preliminar y core 6 1-3 P:$0C OnCE Step Counter core 7 1 -3 P: $0E O nCE Br eak point U nit 0 Rese rved core 9 1-3 P:$12 OnCE Trace Buffer core 10 1-3 P:$ 14 OnCE Transmit Register Empty core 11 1-3 P:$ 16 OnCE Receive Re gister Full Rese rved core 14 2 P:$1C SW Interrupt 2 core[...]

Interrupt Vector Table 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 33 Prelimin ary Rese rved TMRC 56 0-2 P:$70 Timer C Ch annel 0 TMRC 57 0-2 P:$72 Timer C Ch annel 1 TMRC 58 0-2 P:$74 Timer C Ch annel 2 TMRC 59 0-2 P:$76 Timer C Ch annel 3 Rese rved TMRA 64 0-2 P:$80 Timer A Channel 0 TMRA 65 0-2 P:$82 Timer A Channel 1 TMRA 6[...]

56F8322 T echncia l Dat a, Rev . 10.0 34 Free scal e S emic ondu cto r Preliminar y 4.4 Data Map Note: Data Flash is NOT available on the 56F8122 device. 4.5 Flash Memory Map Figure 4-1 illustrates the Flash Memory (FM) m ap on the system bus. Flash Memory i s divided into three functional blocks. The Program and boot memories reside on the Program[...]

Flash Memory Map 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 35 Prelimin ary Figure 4-1 Flash Array Memory Maps Tabl e 4-5 shows the pa ge and sector sizes used within each Flash memory block on the chip. Note: Data Flash is NOT available on the 56F8122 device. Please see the 56F8300 Per ipheral User Manual for additional Flash[...]

56F8322 T echncia l Dat a, Rev . 10.0 36 Free scal e S emic ondu cto r Preliminar y 4.6 EOnCE Memory Map 4.7 Peripheral Memory Mapped Registers On-chip periphera l registers are pa rt of the da ta memory map on the 56800E series. The se locations may be accessed with the same addressing modes used for ordina ry D ata memory, except all peripher al [...]

Peripheral Memory M apped Registers 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 37 Prelimin ary The following tables list all of the peripheral registers required to control or access the per ipherals. Note: Features in italics are NOT available on the 56F8122 device. Table 4-7 Dat a Memory P eripheral Base Address Map Summa ry[...]

56F8322 T echncia l Dat a, Rev . 10.0 38 Free scal e S emic ondu cto r Preliminar y TMRA0_ CMPLD2 $9 Comparat or Load Regi ster 2 TMRA0_ COMSCR $A Comparator Sta tus and Co ntrol Regis ter Reserved TMRA1_ CMP1 $10 Compare Register 1 TMRA1_ CMP2 $11 Compare Register 2 TMRA1_ CAP $12 Captu re Register TMRA1_ LOAD $1 3 Load Reg ister TMRA1_ HOLD $14 H[...]

Peripheral Memory M apped Registers 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 39 Prelimin ary Table 4-9 Quad Timer C Re gisters Address Map (TMRC_BASE = $00 F0C0) Register A cronym Addres s Offset Register Descr iption TMRC0_CM P1 $0 Compare R egister 1 TMRC0_CM P2 $1 Compare R egister 2 TMRC0_CAP $2 Capture Register TMRC0_LO[...]

56F8322 T echncia l Dat a, Rev . 10.0 40 Free scal e S emic ondu cto r Preliminar y TMRC3_CM P2 $31 Compa re Register 2 TMRC3_CA P $32 C apture Regi ster TMRC3_LO AD $33 Load Register TMRC3_HO LD $34 Hol d Register TMRC3_CN TR $35 Cou nter Regist er TMRC3_CT RL $36 Control Regi ster TMRC3_SCR $37 Sta tus and Con trol Regist er TMRC3_CM PLD1 $38 Com[...]

Peripheral Memory M apped Registers 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 41 Prelimin ary Table 4-11 Quadrature Decoder 0 Registers Address Map (DEC0_BAS E = $00 F1 80) Quadrature Decoder is NOT available in the 56F8122 de vice Register Ac ronym Address O ffset Regis ter Descripti on DEC0_DECCR $0 Decoder Control Register[...]

56F8322 T echncia l Dat a, Rev . 10.0 42 Free scal e S emic ondu cto r Preliminar y IRQP 0 $11 IRQ Pendin g Register 0 IRQP 1 $12 IRQ Pendin g Register 1 IRQP 2 $13 IRQ Pendin g Register 2 IRQP 3 $14 IRQ Pendin g Register 3 IRQP 4 $15 IRQ Pendin g Register 4 IRQP 5 $16 IRQ Pendin g Register 5 Reserved ICTL $1D Interrup t Control R egister Table 4-1[...]

Peripheral Memory M apped Registers 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 43 Prelimin ary ADCA_HLMT 1 $1A High Limit Register 1 ADCA_HLMT 2 $1B High Limit Register 2 ADCA_HLMT 3 $1C High Lim it Register 3 ADCA_HLMT 4 $1D High Lim it Register 4 ADCA_HLMT 5 $1E High Limit Register 5 ADCA_HLMT 6 $1F High Lim it Register 6 AD[...]

56F8322 T echncia l Dat a, Rev . 10.0 44 Free scal e S emic ondu cto r Preliminar y Table 4-16 Serial Communication Interface 1 Registers Address Map (SCI1 _BASE = $00 F290) Register Ac ronym Address O ffset Regis ter Descripti on SCI1_SCIBR $0 Baud Rate Register SCI1_SCICR $1 Control Register Reserved SCI1_SCISR $3 Status Regis ter SCI1_SCIDR $4 D[...]

Peripheral Memory M apped Registers 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 45 Prelimin ary Table 4-20 Clock Generation Module Registers Address Map (CLKGEN_BASE = $00 F2D0) Register Acr onym Addres s Offset Register Descr iption PLLCR $0 Control Register PLLDB $1 Divide -By Registe r PLLSR $2 Status R egister Reserved SHU [...]

56F8322 T echncia l Dat a, Rev . 10.0 46 Free scal e S emic ondu cto r Preliminar y Table 4-23 GPIOC Re gisters Address Map (GPIOC _BASE = $00F310) Registe r Acronym Address Offset Register D escription Reset Valu e GPIOC_PU R $0 Pull-up Enab le Regi ster 0 x 007C GPIOC_DR $1 Data Register 0 x 0000 GPIOC_DDR $2 Data Direc tion Register 0 x 0000 GPI[...]

Peripheral Memory M apped Registers 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 47 Prelimin ary Table 4-26 Flash Module Registers Address Map (FM_B ASE = $00 F400) Register Ac ronym Address O ffset Register Description FMCLKD $0 Clock Divider Register FMMCR $1 Module Control Register Reserved FMSECH $3 Security High Half Regist[...]

56F8322 T echncia l Dat a, Rev . 10.0 48 Free scal e S emic ondu cto r Preliminar y FCRX14MASK_H $A Receive Buffer 14 Mas k High Registe r FCRX14MASK_L $B Receive Buffer 14 Mas k Low Register FCRX15MASK_H $C Receive Buffer 1 5 Mask High Register FCRX15MASK_L $D Receive Buffer 1 5 Mask Low Regis ter Reserved FCSTATUS $10 Error and St atus Register F[...]

Peripheral Memory M apped Registers 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 49 Prelimin ary FCMB3_CON TROL $58 Message Buffe r 3 Control / Status Re gister FCM B3_I D_HI GH $59 Me ssag e Buf fer 3 ID Hig h Regi ste r FCMB3_ID_ LOW $5A Message Buffe r 3 ID Low Register FCMB3_DATA $5B Message Buffer 3 Data Re gister FCMB3_DAT[...]

56F8322 T echncia l Dat a, Rev . 10.0 50 Free scal e S emic ondu cto r Preliminar y FCMB7_DATA $7C Message Buffe r 7 Data Registe r FCMB7_DATA $7D Message Buffe r 7 Data Registe r FCMB7_DATA $7E Message Buffer 7 Data Re gister Reserved FCMB8_CON TROL $80 Message Buffe r 8 Control / Status Re gister FCM B8_I D_HI GH $81 Me ssag e Buf fer 8 ID Hig h [...]

Peripheral Memory M apped Registers 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 51 Prelimin ary FCMB12_ ID_HIGH $A1 Message Buffe r 12 ID Hig h Register FCMB12_ID_LO W $A2 Message Buffer 12 ID Low Regist er FCMB12_ DATA $A3 Message Buffer 12 D ata Regist er FCMB12_ DATA $A4 Message Buffer 12 D ata Regist er FCMB12_ DATA $A5 Mes[...]

56F8322 T echncia l Dat a, Rev . 10.0 52 Free scal e S emic ondu cto r Preliminar y 4.8 Factory-Program med Memory The Boot Flash memory block is programmed during manufacturing with a default Serial Bootloader program. The Serial Bootloader application ca n be used to load a user appli cation into the Program and Data Flash ( not available on the [...]

Functional Description 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 53 Prelimin ary 5.3.2 Interrupt Nes ting Interrupt e xceptions may be nested to allow an IRQ of higher priority than the curr ent exce ption to be serviced. The following tables define the nesting requirements for ea ch priority level. 5.3.3 Fast Int errupt Hand[...]

56F8322 T echncia l Dat a, Rev . 10.0 54 Free scal e S emic ondu cto r Preliminar y 5.4 Block Diagram Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Mode s The ITCN module design contains two major modes of operation: • Functional Mode The ITCN i s in this mode by default. • W ait and S top Modes During W ait and Stop modes, the s [...]

Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 55 Prelimin ary 5.6 Register Descriptions A re gister a ddress is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN peripheral has 24 re gisters. Table [...]

56F8322 T echncia l Dat a, Rev . 10.0 56 Free scal e S emic ondu cto r Preliminar y Figure 5-2 ITCN Register Map Summary Add. Offset Regist er Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $0 IPR 0 R 0 0 BKPT_ U0 IPL STPCNT IPL 0 0 0 0 0 0 0 0 0 0 W $1 IPR 1 R 0 0 0 0 0 0 0 0 0 0 RX_REG IPL TX_REG IPL TRBUF IPL W $2 IPR 2 R FMCBE IPL FMCC IPL FMERR IP[...]

Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 57 Prelimin ary 5.6.1 Interrupt P riority Regi ster 0 (IP R0) Figure 5-3 Interrupt Prior ity Register 0 (IPR0 ) 5.6.1.1 Rese rved—Bits 15–1 4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.1.2 EOnC E Brea[...]

56F8322 T echncia l Dat a, Rev . 10.0 58 Free scal e S emic ondu cto r Preliminar y 5.6.2.1 Rese rved—Bits 15–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.2.2 EOnC E Receive Regis ter Full Interrupt P riority Level (RX_REG IPL)—Bits 5–4 This field is used to set the interrupt priori[...]

Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 59 Prelimin ary 5.6.3.1 Flash Memory Comman d, Data, Address Buffers E mpty Interrupt Priority Level (FMCBE IP L)—Bits 15–14 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to priorities 0 through 2. It is disabled by de[...]

56F8322 T echncia l Dat a, Rev . 10.0 60 Free scal e S emic ondu cto r Preliminar y 5.6.3.5 Low V oltage Detector I nterrupt Priority Le vel (LVI IPL)—Bits 7–6 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to priorities 0 through 2. It is disabled by default. • 00 = IRQ disabled (default ) • 01 = IRQ[...]

Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 61 Prelimin ary 5.6.4.3 FlexC AN Wake Up Inter rupt Priority Leve l (FCWKUP IPL)— Bits 7–6 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (d[...]

56F8322 T echncia l Dat a, Rev . 10.0 62 Free scal e S emic ondu cto r Preliminar y 5.6.5.1 SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)— Bits 15–14 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default ) • 01[...]

Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 63 Prelimin ary 5.6.5.6 GPIO _B Interrupt Prior ity Level (GPIOB IPL)—Bits 3–2 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default ) •[...]

56F8322 T echncia l Dat a, Rev . 10.0 64 Free scal e S emic ondu cto r Preliminar y 5.6.6.3 SCI1 Receiver Error I nterrupt Priority L evel (SCI1_RERR IPL)— Bits 9–8 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default ) • [...]

Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 65 Prelimin ary 5.6.7 Interrupt P riority Regi ster 6 (IP R6) Figure 5-9 Interrupt Prior ity Register 6 (IPR6 ) 5.6.7.1 Timer C, Channel 0 Interrupt Priority Level (TMRC_0 IPL)— Bits 15–14 This field is used to set the interr upt priority level for IRQs. This[...]

56F8322 T echncia l Dat a, Rev . 10.0 66 Free scal e S emic ondu cto r Preliminar y 5.6.8 Interrupt P riority Regi ster 7 (IP R7) Figure 5-10 Interrupt Priority Register (IPR7) 5.6.8.1 Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)— Bits 15–14 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to pri[...]

Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 67 Prelimin ary 5.6.8.5 Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)—Bits 1–0 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (def[...]

56F8322 T echncia l Dat a, Rev . 10.0 68 Free scal e S emic ondu cto r Preliminar y 5.6.9.4 SCI0 Transmitter Idle Interrupt Priority L evel (SCI0_TIDL IPL)— Bits 9–8 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default ) •[...]

Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 69 Prelimin ary 5.6.9.8 Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)—Bits 1–0 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (def[...]

56F8322 T echncia l Dat a, Rev . 10.0 70 Free scal e S emic ondu cto r Preliminar y 5.6.10.5 ADC A Zero Crossing or Limit Error Interru pt Priority Leve l (ADCA_ZC IPL)—Bits 7–6 This field is used to set the interr upt priority level for IRQs. This IRQ is l imited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (d[...]

Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 71 Prelimin ary 5.6.12 Fast Interrupt 0 Match Register (FIM0) Figure 5 -14 Fa st Interrupt 0 Match Register ( FIM0) 5.6.12.1 Rese rved—Bits 15–7 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.12.2 Fast In[...]

56F8322 T echncia l Dat a, Rev . 10.0 72 Free scal e S emic ondu cto r Preliminar y 5.6.14.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bit s 4–0 The upper f ive bi ts of the vector address used for Fast Interrupt 0. This register i s combined with F IVAL0 to form the 21-bit vector address for Fast Interrupt 0 def ined in the FIM0 register. [...]

Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 73 Prelimin ary 5.6.17.1 Rese rved—Bits 15–5 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.17.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bit s 4–0 The uppe r five bits of the vector address are [...]

56F8322 T echncia l Dat a, Rev . 10.0 74 Free scal e S emic ondu cto r Preliminar y 5.6.20 IRQ Pending 2 Registe r (IRQP2) Figure 5-22 IRQ Pending 2 Register (IRQP2) 5.6.20.1 IRQ P ending (PENDING) —Bits 48–33 This re gister combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • 0 = IRQ pending[...]

Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 75 Prelimin ary 5.6.23 IRQ Pending 5 Registe r (IRQP5) Figure 5-25 IRQ Pending Register 5 (I RQP5) 5.6.23.1 Rese rved—Bits 96–8 2 This bit field is reserved or not implemented. The bits are read as 1 and cannot be modified by writing. 5.6.23.2 IRQ P ending (P[...]

56F8322 T echncia l Dat a, Rev . 10.0 76 Free scal e S emic ondu cto r Preliminar y 5.6.30.2 Interr upt Priority Level (IPIC)—Bits 14–1 3 These read-only bits reflect the state of the new interrupt priority level bits being pre sented to the 56800E core at the time the last IRQ was taken. This f ield is only updated whe n the 56800E core jumps [...]

Resets 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 77 Prelimin ary 5.7 Resets 5.7.1 Reset Handshake Timi ng The ITCN provides the 56800E c ore wi th a reset vector address whenever R ESET is asserted. The reset vector will be presented until the second rising clock edge after RESET is released. 5.7.2 ITCN After Reset After rese[...]

56F8322 T echncia l Dat a, Rev . 10.0 78 Free scal e S emic ondu cto r Preliminar y 6.2 Features The SIM has the following features: • Flas h security f eature pr events unaut horized acce ss to code/ data contai ned in on-chip flas h memory • Po wer-sav ing clock g ating for peripheral s • Three power modes (Run, W ait, S top) to co ntrol po[...]

Operating Mode Register 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 79 Prelimin ary 6.4 Operating Mode Register Figure 6-1 OMR The reset state for the MB bit will depend on the Flash secured state. See Section 4.2 and Part 7 f o r detailed information on how the Operating Mode Register (OMR) MA and MB bits oper ate in this d ev[...]

56F8322 T echncia l Dat a, Rev . 10.0 80 Free scal e S emic ondu cto r Preliminar y Figure 6-2 SIM Register Map Summary 6.5.1 SIM Contro l R egist er (SIM _C ONTRO L) Figure 6-3 SIM Control Register (SI M_CONTROL) 6.5.1.1 Rese rved—Bits 15–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. Add. O[...]

Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 81 Prelimin ary 6.5.1.2 OnCE Enable (ONCE EBL)—Bit 5 • 0 = OnCE clock to 56800E c ore enable d when core T AP is enabled • 1 = OnCE clock to 568 00E core is al ways enable d 6.5.1.3 Softw are Reset (SW RST)—Bit 4 Writing 1 to this field will cause the par[...]

56F8322 T echncia l Dat a, Rev . 10.0 82 Free scal e S emic ondu cto r Preliminar y 6.5.2.3 COP Reset (COPR)—Bit 4 When 1, the COPR bit indicates the Computer Operating Prope rly (COP) timer-genera ted re set has occurred. This bit will be cleared by a Power-On R eset or by software. Writing a 0 to this bit position will set the bit, while writin[...]

Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 83 Prelimin ary 6.5.4 Most S ignif ican t Half of J TAG I D (SIM _MSH_ ID) This read-only re gister displays the most significant half of the JTAG ID for the chip. This register reads $01F4. Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID) 6.5.5 Least Si [...]

56F8322 T echncia l Dat a, Rev . 10.0 84 Free scal e S emic ondu cto r Preliminar y 6.5.6.3 IRQ— Bit 10 This bit controls the pull-up resistors on the IRQA pin. 6.5.6.4 Rese rved—Bits 9–4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.6.5 JTAG —Bit 3 This bit c ontrols the pull-u p resi[...]

Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 85 Prelimin ary 6.5.7.4 INDEX 0 (INDEX )—Bit 7 • 0 = Peripheral out put funct ion of GPIOB[5] i s defined t o be INDEX0 • 1 = Peripheral out put funct ion of GPIOB[5] i s defined t o be SYS_CLK 6.5.7.5 HOME 0 (HOME )—Bit 6 • 0 = Peripheral out put funct[...]

56F8322 T echncia l Dat a, Rev . 10.0 86 Free scal e S emic ondu cto r Preliminar y Note: PWM is NOT available in the 56F8122 device. As shown in Figure 6- 10 , the GPIO has the final control ove r which pin controls the I/O. SIM_GPS simply decides which peripheral will be routed to the I/O. Figure 6-10 Overall Control of Pads Using SIM_GPS Control[...]

Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 87 Prelimin ary 6.5.8.4 GPIO B1 (B1)—Bit 5 This bit selects the alternate function for GPIOB1. • 0 = MISO0 ( default) • 1 = RXD1 6.5.8.5 GPIO B0 (B0)—Bit 4 This bit selects the alternate function for GPIOB0. • 0 = SS0 (de fault) • 1 = TXD1 6.5.8.6 GPI[...]

56F8322 T echncia l Dat a, Rev . 10.0 88 Free scal e S emic ondu cto r Preliminar y 6.5.9.1 Rese rved—Bits 15–1 4 This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing. 6.5.9.2 Analo g-to-Digital Conver ter A Enable (ADCA )—Bit 13 Each bit controls clocks to the indicated peripheral. • 1 = Clocks a[...]

Register Descriptions 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 89 Prelimin ary 6.5.9.10 Seria l Communications Interface 1 Enable (SCI1 )—Bit 5 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are en abled • 0 = The clock is not provid ed to the p eripheral ( the periphe ral is di sabled) 6.5.9.11 Ser[...]

56F8322 T echncia l Dat a, Rev . 10.0 90 Free scal e S emic ondu cto r Preliminar y Figure 6-13 I/O S hort Address Determination With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register to it[...]

Clock Generation Overview 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 91 Prelimin ary 6.5.10.2 Input/ Output Short Addres s Low (ISAL[21:6])—Bit 15– 0 This field represents the lower 16 address bits of the “hard coded” I/O short addr ess. 6.6 Clock Generation Ove rview The SIM uses an internal master clock from the OCCS[...]

56F8322 T echncia l Dat a, Rev . 10.0 92 Free scal e S emic ondu cto r Preliminar y 6.8 Stop and Wait Mode Disable Fu nction Figure 6-16 Internal Stop Disable Circuit The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly [...]

Operation with Security Enabled 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 93 Prelimin ary Part 7 Security Features The 56F8322/56F8122 offer security featur es intended to prevent unauthorized users from reading the contents of the Flash Memory (FM) array. The Flash security consists of several hardware interlocks that block [...]

56F8322 T echncia l Dat a, Rev . 10.0 94 Free scal e S emic ondu cto r Preliminar y Proper implementation of Flash security requires that no access to the EOnCE port is provided w hen security is enabled. The 56800E core has an input which disables rea ding of internal memory via the JTAG/EOnCE. The FM sets this input at reset to a value determined[...]

Flash Access Blocking Mechanism s 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 95 Prelimin ary EXAMPLE 1: If the system clock is the 8M Hz crystal freque ncy bec ause the PLL has not be en set up, the input clock will be below 12.8MHz, so PRDIV8=FM_CLKDIV[6]=0. Using the following equation yields a DIV value o f 19 for a clock o[...]

56F8322 T echncia l Dat a, Rev . 10.0 96 Free scal e S emic ondu cto r Preliminar y Part 8 General Purpose Inp ut/Output (GPIO) 8.1 Introduct ion This section is intende d to supplement the GPIO information f ound in the 56F8300 Peripheral User Manual and contains only chip-specific information. This information superce des the generic information [...]

Configuration 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 97 Prelimin ary Table 8-3 GPIO E xternal Signals Map Pins in shaded rows are not available in 56F8322 / 56F8122 Pins in it alics a re NOT a vailable i n the 56F 8122 d evice GPIO Func tion Peripheral Function Pack age Pi n Not es GPIOA0 PWMA0 3 PWM i s NOT av ailable in [...]

56F8322 T echncia l Dat a, Rev . 10.0 98 Free scal e S emic ondu cto r Preliminar y 8.3 Memory Maps The width of the GPIO port defines how many bits are implemented in each of the GPIO registers. Based on this and the default function of each of the G PIO pins, the reset values of the GPIOx_PUR and GPIOx_PER registers c hange from port to port. Tab[...]

General Characterist ics 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 99 Prelimin ary Part 10 Specifications 10.1 General Characteristics The 56F8322/56F8122 are fabr icated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term “ 5V-tolerant” refers to the c apability of an I/O pin, built on a 3.3V-c [...]

56F8322 T echncia l Dat a, Rev . 10.0 100 Fr eesc ale Semi con duc tor Preliminar y Note: The 56F8122 device is specified to meet Industrial requirements only; PWM, CAN and Quad Decoder are NOT available on the 56F8122 device. Note: Th e o verall life of thi s d evice ma y b e reduce d if subjec ted to e xten ded use ove r 1 10°C jun ction. For ad[...]

General Characterist ics 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 101 Prelimin ary 1. Theta- JA determi ned on 2s2p test boar ds is freque ntly low er than would be obser ved in an application. Determined on 2 s2p the r- mal te st b oa rd . 2. Jun cti on to amb ien t ther ma l resi sta nc e, Th eta -J A (R qJA ), was sim ula[...]

56F8322 T echncia l Dat a, Rev . 10.0 102 Fr eesc ale Semi con duc tor Preliminar y Note: The 56F8122 device is guaranteed to 40MHz and specified to meet Indus trial requirements only; PWM, CAN and Quad Decoder are NOT available on the 56F8122 device. Note: Total chip source or sin k curr ent canno t exce ed 150m A. Note: Pins in italics a re NOT a[...]

DC Electrical Characteristi cs 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 103 Prelimin ary 10.2 DC Electrical C haracteristics Note: The 56F8122 device is specified to meet Industrial requirements only; PWM, CAN and Quad Decoder are NOT available on the 56F8122 device. See Pin Gr oups in Tab le 10- 1 Table 1 0-5 DC Elec trical[...]

56F8322 T echncia l Dat a, Rev . 10.0 104 Fr eesc ale Semi con duc tor Preliminar y Table 10-6 Power-On Reset Low Voltage Parameters Charac teristic Symbol Min Typ Max Units POR Trip Point Ri sing 1 1. Both V EI 2.5 and V EI3. 3 thresho lds m ust be met for PO R to be relea sed on po wer-u p. POR R ——— V POR Trip Point Fall ing POR F 1. 75 1.[...]

DC Electrical Characteristi cs 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 105 Prelimin ary 10.2.1 Voltage Regulator Specifi cations The 56F8322/56F8122 have two on-chip regulators. One supplies the PLL and has no external pins; therefore, it has no e xternal character istics whic h must be gua ranteed (other than proper oper a[...]

56F8322 T echncia l Dat a, Rev . 10.0 106 Fr eesc ale Semi con duc tor Preliminar y Table 10-9. Re gulator Parameters Cha ract eri stic Symb ol M in Typi cal Ma x Unit Unloaded Output Voltag e (0mA Loa d) V RNL 2.25 — 2.75 V Loaded Output Voltage (200m A load) V RL 2. 25 — 2.75 V Line Regu lation @ 200mA load (V DD 33 ranges from 3.0V to 3 .6V)[...]

AC Electri cal Characte ristics 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 107 Prelimin ary 10.2.2 Temperature Sense Note: Temperature Sensor is NOT available in the 56F8122 device. 10.3 AC Electrical Charact eristics Tests are conducted using the input levels specif ied in Table 10-5 . Unless otherwise specified, propagation [...]

56F8322 T echncia l Dat a, Rev . 10.0 108 Fr eesc ale Semi con duc tor Preliminar y Figure 10-1 Input Signal Measurement References Figure 10-2 shows the definitions of the following signal states: • Acti ve state, when a bus or signal is dr iven, and ente rs a low i mpedance sta te • T ri-s tate d, w he n a bus or s ign al is pla ced in a hi g[...]

External Clock Operat ion Timing 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 109 Prelimin ary 10.5 External Clock Operat ion Timing Figure 10-3 Exter nal Clock Timing Table 10-13 External Clock Operation Timing Requirements 1 1. Param eters listed are gu arante ed by design. Character istic Symbol Mi n Typ Ma x Unit Frequency o[...]

56F8322 T echncia l Dat a, Rev . 10.0 110 Fr eesc ale Semi con duc tor Preliminar y 10.6 Phase Locked Loop Timin g 10.7 Oscillator Parameters Table 10-14 PLL Timing Charac teristic Symbol Min Typ Max Unit External re ference c rystal frequen cy for the PLL 1 1. An externally suppli ed reference clock should be as free as possible from any phase jit[...]

Oscillator Parameters 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 111 Prelimin ary Note: An LSB change in the tuning code results in an 82ps shift in the frequency period, while an MS B change in the tuning code results in a 4 1ns shif t in the frequ ency pe riod. Table 10 -16 Re laxation Oscil lator Para meters Cha racte rist [...]

56F8322 T echncia l Dat a, Rev . 10.0 112 Fr eesc ale Semi con duc tor Preliminar y Figure 10-4 Frequency versus Temperature Frequency in MHz Temper ature - 50 - 30 - 10 + 10 + 30 + 50 + 70 + 90 + 110 + 130 + 150 7.5 7.6 7.7 7.9 7.8 8.0 8.1 8.2 Typic al Resp onse[...]

Reset, Stop, Wait, Mode Select, and Interrupt Timing 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 113 Prelimin ary 10.8 Reset, Stop, Wait , Mode Select, and Interrupt T iming Note: All address and data buses described he re are internal. Figure 10-5 Asynchronous Reset Timing Figure 10-6 Exter nal Interrupt Timing (Negative Edge-[...]

56F8322 T echncia l Dat a, Rev . 10.0 114 Fr eesc ale Semi con duc tor Preliminar y Figure 10-7 External Le vel-Sensitive Interrupt Tim ing Figure 10-8 Recovery from Stop State Using Asynchronous Interrupt Timing t IG General Purp ose I/O Pin IRQA b) General Purpose I/O t IDM PAB IRQA a) First Interrup t Instruct ion Exe cution First In terrupt Ins[...]

Serial Peripheral Interface (SPI) Timing 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 115 Prelimin ary 10.9 Serial Peripheral Interfac e (SPI) Timing Table 10-18 SPI Timing 1 1. Param eters listed are gu arante ed by design. Characteri stic Symbol Min Max Unit See Figure Cycle tim e Maste r Slave t C 50 50 — — ns ns 10-9 , 1[...]

56F8322 T echncia l Dat a, Rev . 10.0 116 Fr eesc ale Semi con duc tor Preliminar y 1 Figure 10 -9 SPI Maste r Timing (CPHA = 0) Figure 10-10 SPI Master Timing (CPHA = 1) SCLK ( CPOL = 0) (Output) SCLK ( CPOL = 1) (Output) MISO (Input) MOSI (Output) MSB i n Bits 14– 1 LSB in t F t C t CL t CL t R t R t F t DS t DH t CH t DI t DV t DI (re f) t R M[...]

Serial Peripheral Interface (SPI) Timing 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 117 Prelimin ary Figure 10-11 SPI Slave Timing (CPHA = 0) Figure 10-12 SPI Slave Timing (CPHA = 1) SCLK ( CPOL = 0 ) (Input) SCLK ( CPOL = 1 ) (Input) MISO (Output) MOSI (Input) Slave MS B out Bits 14– 1 t C t CL t CL t F t CH t DI MSB in Bit[...]

56F8322 T echncia l Dat a, Rev . 10.0 118 Fr eesc ale Semi con duc tor Preliminar y 10.10 Quad Timer Tim ing Figure 10-13 Timer Timing 10.11 Quadratur e Decoder Timing Note: The Quadrature Decoder is NOT available in the 56F8122 device. Table 10-19 Timer Timing 1, 2 1. In t he formulas li sted, T = the clock cycle. For 60MHz operation, T = 16.67ns.[...]

Serial Communication Inter face (SCI) Timing 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 119 Prelimin ary Figure 10-14 Quadrature Decoder Timing 10.12 Serial Commun ication Interface (SCI) Tim ing Figure 10-15 RXD Pulse Width Figure 10-16 TXD Pulse Width Table 10-21 S CI Timing 1 1. Parame ters list ed ar e guarant eed by desig[...]

56F8322 T echncia l Dat a, Rev . 10.0 120 Fr eesc ale Semi con duc tor Preliminar y 10.13 Controller Area N etwork (CAN) Tim ing Note: CAN is NOT available in the 56F8122 device. Figure 10-17 Bus Wakeup Detect ion 10.14 JTAG Timing Table 10-22 CAN Timing 1 1. Parame ters list ed ar e guarant eed by design Characteri stic Symbol Min Max Unit See Fig[...]

JTAG Timing 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 121 Prelimin ary Figure 10-18 Test Clock Input Timing Diagram Figure 10-19 Te st A cces s Po rt Ti ming Diagr am TCK (Input) V M V IL V M = V IL + (V IH – V IL )/2 t PW 1/f OP t PW V M V IH Input Data V alid Output Da ta Valid Output Da ta Valid t DS t DH t DV t TS t DV [...]

56F8322 T echncia l Dat a, Rev . 10.0 122 Fr eesc ale Semi con duc tor Preliminar y 10.15 Analog-t o-Digital Converter ( ADC) Parameters Table 10-24 ADC Parameters Characteri stic Symbol M in Typ Max U nit Input vol tages V ADIN V REFL —V REFH V Resolution R ES 12 — 12 Bits Integral N on-Linearity 1 INL — +/- 2.4 +/- 3.2 LSB 2 Different ial N[...]

Analog-to-Digital Converter (ADC) Parameters 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 123 Prelimin ary Signal- to-noise plus distorti on ratio SI NA D — 5 9.1 — db Total Ha rmonic Dis tortion THD — 60.6 — db Spurious F ree Dyna mic Range SF DR — 6 1.1 — db Effective Number Of Bits 8 ENOB — 9.6 — Bits 1. INL m[...]

56F8322 T echncia l Dat a, Rev . 10.0 124 Fr eesc ale Semi con duc tor Preliminar y Figure 10-20 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDC in = 0.60V and 2.7 0V Note: The absolute error data shown in the graphs above r eflects the effects of both gain error and offset error. The data was taken [...]

Equivalent Circuit for ADC Inputs 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 125 Prelimin ary 10.16 Equivalent Circ uit for ADC Inp uts Figure 10-21 illustrates the ADC input circuit during sample and hol d. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 closed & S3 open, one input of [...]

56F8322 T echncia l Dat a, Rev . 10.0 126 Fr eesc ale Semi con duc tor Preliminar y B, the internal [state-depe ndent component], reflects the supply current required by certain on-chip resources only when those resources are in use. These include RAM, Flash memory and the ADCs. C, the internal [ dynamic component], is classic C*V 2 *F CMOS po wer [...]

56F8322 Package and Pin-Out Informa tion 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 127 Prelimin ary Part 1 1 Packaging 11.1 56F8322 Package an d Pin-Out Informati on This section contains package and pin-out information for the 56F8322. This device comes in a 48-pin Low-profile Quad F lat Pack (LQFP). Figure 11-1 shows the pa[...]

56F8322 T echncia l Dat a, Rev . 10.0 128 Fr eesc ale Semi con duc tor Preliminar y Table 11-1 56F8322 48-Pin LQFP Package Identification by P in Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 1T C 0 1 3 V SS 25 ANA6 37 PHASEB 2 RESET 14 V DD_IO 26 V REFN 38 PHASEA 3 PWMA0 15 SS0 27 V REFMID 39 TCK 4P W M A 1[...]

56F8122 Package and Pin-Out Informa tion 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 129 Prelimin ary 11.2 56F8122 Package an d Pin-Out Informati on This section contains package and pin-out information for the 56F8122. This device comes in a 48-pin Low-profile Quad F lat Pack (LQFP). Figure 11-1 shows the package outline for t[...]

56F8322 T echncia l Dat a, Rev . 10.0 130 Fr eesc ale Semi con duc tor Preliminar y Table 11-2 56F8122 48-Pin LQFP Package Identification by P in Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 1T C 0 1 3 V SS 25 ANA6 37 TA1 2 RESET 14 V DD_IO 26 V REFN 38 TA0 3 GPIOA0 15 SS0 27 V REF MID 39 TCK 4 GPIOA1 16 MI[...]

56F8122 Package and Pin-Out Informa tion 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 131 Prelimin ary Figure 11-3 48 -Pin LQFP Mechanica l Information A A1 Z 0.200 AB T-U 4X Z 0.200 AC T -U 4X B B1 1 12 13 24 25 36 37 48 S1 S V V1 P AE AE T, U , Z DET AIL Y DET AIL Y BASE MET AL N J F D T- U M 0.080 Z AC SECTION AE-AE AD G 0.08[...]

56F8322 T echncia l Dat a, Rev . 10.0 132 Fr eesc ale Semi con duc tor Preliminar y Part 12 Design Co nsiderations 12.1 Thermal Desig n Considerations An estimation of the chip junction temperature, T J , can be obtained from the equation: T J = T A + (R θ J Α x P D ) where: The junction to ambient thermal resistance is an industry-standard value[...]

Electrical Design Considerations 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 133 Prelimin ary The thermal c haracterization parame ter is measured per JESD51-2 specific ation using a 40-gauge t ype T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple juncti[...]

56F8322 T echncia l Dat a, Rev . 10.0 134 Fr eesc ale Semi con duc tor Preliminar y • Becaus e the devi ce’ s output si gnals have fast rise a nd fall ti mes, PCB trace lengths shoul d be minimal • Con sider all device loads as well as par asitic c apacitan ce due t o PCB tra ces when calculatin g capaci tance. This is es peciall y criti cal [...]

Power Distribution and I/O Ring Implementation 56F8322 T echnica l Dat a, Rev . 10.0 Frees cale Sem iconduc tor 135 Prelimin ary Part 13 Ordering In formation Table 13-1 lists the pertinent information ne eded to place an order. Consult a Freescal e Semiconductor sales office or authorized distributor to determine availability and to order parts. T[...]

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