Freescale Semiconductor DSP56364 инструкция обслуживания

Document Number: DSP56364UM Rev. 2 08/2006 DSP56364 24-Bit Digital Signal Pr ocessor Users Manual[...]

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BookTitle, Rev . # Freescale Semiconductor iii Manual Conventions 1 Overview 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

BookTitle, Rev . # iv Freescale Semiconductor 3 Memory Configuration 3.1 Memory Spaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 Program Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3[...]

BookTitle, Rev . # Freescale Semiconductor v 5 General Purpose Input/Output Port (GPIO) 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 GPIO Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

BookTitle, Rev . # vi Freescale Semiconductor 6.3.2.4 TCR ESAI Transmit 3 Enable (TE3) - Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.3.2.5 TCR ESAI Transmit 4 Enable (TE4) - Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.3.2.6 TCR ESAI Transmit 5 Enable (TE5) - Bit 5 . . . . . . . . . .[...]

BookTitle, Rev . # Freescale Semiconductor vii 6.3.5.1 SAICR Serial Output Flag 0 (OF0) - Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 6.3.5.2 SAICR Serial Output Flag 1 (OF1) - Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 6.3.5.3 SAICR Serial Output Flag 2 (OF2) - Bit 2 . . . . . [...]

BookTitle, Rev . # viii Freescale Semiconductor 6.6.2 Initializing Just the ESAI Transmitter Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 6.6.3 Initializing Just the ESAI Receiver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 7 Serial Host Interface 7.1 Introduction . . . . [...]

BookTitle, Rev . # Freescale Semiconductor ix 7.6.2 I 2 C Data Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 7.7 SHI Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 -20 7.7.1 SPI Slave Mode . . . . . . .[...]

BookTitle, Rev . # x Freescale Semiconductor[...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 Freescale Semiconductor xi Figure 1-1 DSP56364 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Figure 2-1 Signals Identified by Functional Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2[...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 xii Freescale Semiconductor Figure C-2 Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-10 Figure C-3 Interrupt Priority Register-C ore (IPR-C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-11 Figu[...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 Freescale Semiconductor xiii Table 2-1 DSP56364 Functional Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Table 2-2 Power Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 xiv Freescale Semiconductor[...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor xv Preface This manual contains the foll owing sections and appendices. SECTION 1—DSP56364 OVERVIEW • Provides a brief description of the DSP56364, incl uding a features list and block diagram. Lists related documentation needed to use this chip and describ[...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 xvi F reescale Semico nductor Manual Con ventions The following conventions are used in this manual: • Bits within registers are always listed from most significant bi t (MSB) to least significant bit (LSB). • When several related bits are di scussed, they are referenced as AA[n:m][...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor xvii — the reset instructi on, written as “RESET ,” — the reset operating state, written as “Reset,” and — the reset function, written as “reset.”[...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 xviii F reescale Semico nductor[...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 1-1 1 Overview 1.1 Intr oduction The DSP56364 24-Bit Digital Signal Processor , a new audio digital signal processor based on the 24-bit DSP56300 architecture, is targeted to applications that require digita l audio signal processing such as sound field process[...]

Features DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 1-2 F reescale Semico nductor Figure 1-1 DSP56364 Block Diagram 1.2 Features • DSP56300 modular chassis — 100 Million Instructions Per Second (MIPS) with an 100 MHz clock at 3.3V . — Object Code Compatible with the 56K core. — Data ALU with a 24 × 24 bit multiplier -a[...]

Audio Pr oces sor Architecture DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 1-3 — V ery low-power CMOS design, fully static design with operating frequencies down to DC. — STOP and W AIT low-power standby modes. • On-chip Memory Configuration — 1.5K × 24 Bit Y -Data RAM. —1 K × 24 Bit X-Data R[...]

Core Description DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 1-4 F reescale Semico nductor 1.4 Core Description The DSP56364 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that provides up to twice the performan ce of Freescale's popular DSP56000 core family while retaining code compat[...]

DSP56300 Core Functional Blocks DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 1-5 1.5.1.1 Data ALU Registers The Data ALU registers can be read or written over the X memory data bus (XDB) and the Y memory data bus (YDB) as 24- or 48-bit operands (or as 16- or 32-bit operands in 16-bit arithmetic mode). The[...]

DSP56300 Core Functional Blocks DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 1-6 F reescale Semico nductor 1.5.3 Pr ogram Control Unit (PCU) The PCU performs instruction pref etch, instruction decoding, hardware DO loop control, and exception processing. The PCU implements a seve n-stage pipeline and controls the dif ferent proce[...]

DSP56300 Core Functional Blocks DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 1-7 • Y memory expansion bus (YM_EB) to Y memory • Global data bus (GDB) be tween registers in the DMA, AGU, OnCE, PLL, BIU, and PCU as well as the memory-mapped registers in the peripherals • DMA data bus (DDB) for carryin[...]

Data and Program memory DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 1-8 F reescale Semico nductor 1.5.7 JT A G T AP and OnCE Module The DSP56300 core provides a dedicated user -accessible T AP fully compatible with the IEEE 1149.1 Standar d T est Access P ort and Boundary Scan Ar chitectur e . Problems associated wi th testing h[...]

Internal I/O Memor y Map DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 1-9 memory switch can be accomplishe d provided that the af fected addr ess ranges are not being accessed during the instruction cycle in which the switch operation takes place. Accordingly , the following condition must be observed for[...]

Status Register (SR) DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 1-10 F reescale Semico nductor 1.8 Status Register (SR) Refer to the DSP56300 24-Bit Digi tal Signal Processor Family Manual, Freescale publication DSP56300FM/AD for a description of the Status Register bits. The Cache Enable bit (Bit 19) in the Status Regist er mu[...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 2-1 2 Signal/Connection Descriptions 2.1 Signal Gr oupings The input and output signals of th e DSP56364 are organized into functi onal groups, which are listed in Ta b l e 2 - 1 and illustrated in Figure 2-1 . The DSP56364 is operated from a 3.3 V supply; howe[...]

Signal Groupings DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 2-2 F reescale Semico nductor Figure 2-1 Signals Identified b y Functional Group PORT A ADDRESS BUS A0-A17 VCCA (4) GNDA (4) D0-D7 VCCD (1) GNDD (1) AA0-AA1/RAS0 -RAS1 RD WR TA RESERVED (4) VCCC (1) GNDC (1) PORT A BU S CONTRO L PORT A DATA BUS OnCE ON- CHIP EM ULATION[...]

Pow e r DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 2-3 2.2 P ower 2.3 Gr ound T able 2-2 P ower Inputs P ower Name Description V CCP PLL P ower —V CCP is V CC dedicated for PLL use . The voltage should be well-regulated and the input should be provided with an e xtremely low impedance path to the V CC[...]

Cloc k and PLL DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 2-4 F reescale Semico nductor 2.4 Cloc k and PLL 2.5 External Memory Expansion P ort (P or t A) When the DSP56364 enters a low-power standby mode (st op or wait), it tri-stat es the relevant port A signals: D0–D7, AA0, AA1, RD , WR , CAS . 2.5.1 External Address Bus GN[...]

External Memory Expansion P ort (Port A) DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 2-5 2.5.2 External Data Bus 2.5.3 External Bus Contr ol T ab le 2-6 External Data Bus Signals Signal Name Signal T ype State during Reset Signal Description D0–D7 Input/Output T ri-stated Data Bus —D0–D7 are active[...]

Interrupt and Mode Control DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 2-6 F reescale Semico nductor 2.6 Interrupt and Mode Contr ol The interrupt and mode control signals select the chip’ s operating m ode as it comes out of hardware reset. After RESET is deasserted, thes e inputs are hardware interrupt request lines. RD Outp[...]

Serial Host Interface DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 2-7 2.7 Serial Host Interface The SHI has five I/O signals that can be configured to allow the SHI to oper ate in either SPI or I 2 C mode T ab le 2-8 Interrupt and Mode Control Signal Name Signal Ty p e State during Reset Signal Descripti[...]

Serial Host Interface DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 2-8 F reescale Semico nductor . T ab le 2-9 Serial Host Interf ace Signals Signal Name Signal Ty p e State during Reset Signal Description SCK Input or output T ri-stated SPI Serial Clock —The SCK signal is an output when the SPI is con figured as a master and a[...]

Serial Host Interface DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 2-9 MOSI Input or output T ri-stated SPI Master-Out-Slave-In —When the SPI is configured as a master , MOSI is the master data output l ine. The MOSI signal is used in conjunction with the MISO signal f or transmitting and receiving se r[...]

Enhanced Serial A udio Interface DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 2-10 F reescale Semico nductor 2.8 Enhanced Serial A udio Interface T ab le 2-10 Enhanced Serial Au dio Interface Signal s Signal Name Signal T ype State during Reset Signal Description HCKR Input or output GPIO disconnected High Frequency Cloc k for Re[...]

Enhanced Serial Au d i o I n t e rf a c e DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 2-11 FST Input or output GPIO disconnected Frame Sync for T ransmitter —This is the transm itter frame sync input/output signal. For synchronous mode, this signal i s the frame sync for both transmitters and receiv er[...]

Enhanced Serial A udio Interface DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 2-12 F reescale Semico nductor SDO5 Output GPIO disconnected Serial Data Output 5 —When programmed as a transmitter , SDO5 is used to transmit data from the TX5 serial transmit shift register. SDI0 Input Serial Data Input 0 —When progr ammed as a re[...]

JT A G/OnCE Interface DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 2-13 2.9 JT A G/OnCE Interface SDO1 Output GPIO disconnected Serial Data Output 1 —SDO1 is used to transmit data from the TX1 serial transmit shift regist er . PC10 Input, output, or disconnected Po r t C 1 0 —When the ESAI is configur[...]

GPIO Signals DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 2-14 F reescale Semico nductor 2.10 GPIO Signals T able 2-12 GPIO Signals Signal Name Signal T ype State during Reset Signal Desc ription GPIO0- GPIO3 Input, output or disconnected disconnected GPIO0-3- The General Purpose I/O pins are used f or control and handshake funct[...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 3-1 3 Memor y Configuration 3.1 Memory Spaces The DSP56364 provides the following three independent memory spaces: •P r o g r a m • X data • Y data Each memory space uses (by default) 18 external a ddress lines for addressing, allowing access to 256K of e[...]

Memory Spaces DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 3-2 F reescale Semico nductor Customer code should not use this area. The conten ts of this program ROM segment is defined by the bootstrap ROM source code in Appendix A, "Bootstrap ROM" . 3.1.1.3 Bootstrap ROM The bootstrap code is accessed at addresses $FF0000[...]

Memory Space Configuration DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 3-3 3.1.2.2 X Data RAM The on-chip X data RAM consists of 24-bit wide, high-speed, internal st atic RAM occupying 1K locations in the X memory space. The X data RAM organization is 4 banks of 256 24-bit words. 3.1.2.3 Y Data Memory Sp[...]

Internal Memory Configuration DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 3-4 F reescale Semico nductor Memory maps for the dif ferent configurations are shown in Figure 3-1 to Figure 3-4 . 3.3.1 RAM Locations The actual memory locations for pro gram RAM a nd Y data RAM in their own memory space are determined by the MS bit. The[...]

Internal Memory Configuration DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 3-5 3.3.3 Dynamic Memory Configuration Switching The internal memory configurati on is altered by remapping RAM modul es from Y data memory into program memory space and vice-ve rsa. The contents of the swit ched RAM modules are pr[...]

Memory Maps DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 3-6 F reescale Semico nductor 3.4 Memory Maps Figure 3-1 Memory Maps for MS=0, SC=0 Figure 3-2 Memory Maps for MS=1, SC=0 PROGRAM $FFFFFF $000000 $000200 0.5K INTERNAL RAM X DATA $FFFFFF $000000 $000400 1K INTERNAL RAM INTERNAL I/O Y DATA $FF1000 $FFFF80 8K INTERNAL ROM $FF[...]

Memory Maps DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 3-7 Figure 3-3 Memory Maps for MS=0, SC=1 Figure 3-4 Memory Maps for MS=1, SC=1 PROGRAM $FFFF $0000 $0200 0.5K INTERNAL RAM X DATA $FFFF $0000 $0400 1K INTERNAL RAM INTERNAL I/O Y DATA $FF80 (128 words ) EXTERNAL EXTERNAL $FFFF $0000 $0600 1.5K INTE[...]

External Memory Suppor t DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 3-8 F reescale Semico nductor 3.5 External Memory Suppor t The DSP56364 does not support the SSRAM memory type. It does support SRAM and DRAM as indicated in the DSP56300 24-Bit Di gital Signal Processor Family Manual, Freescale publication DSP56300FM/AD. Note [...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 4-1 4 Core Configuration 4.1 Intr oduction This chapter contains DSP56300 core configuration information deta ils specific to the DSP56364. These include the following: • Operating modes • Bootstrap program • Interrupt sources and priorities • DMA reque[...]

Operating Mode Regist er (OMR) DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 4-2 F reescale Semico nductor 4.2.1 Mode C (MC) - Bit 2 The Mode C (MC) bit is set during hardware reset and should be left set in the DSP56364. 4.2.2 Address Attrib ute Priori ty Disable (APD) - Bit 14 The Address Attribute Priority Disa ble (APD) bit is[...]

Operating Modes DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 4-3 4.3 Operating Modes The operating modes are as shown in Ta b l e 4 - 1 The operating modes are latched from MODA, MODB and MODD pins during reset. Each operating mode is briefly described below . The operation of all bootstrap modes is defin[...]

Bootstrap Program DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 4-4 F reescale Semico nductor address to start loading the program words and then a 24-bi t word for each program word to be loaded. The program words will be st ored in contiguous PRAM memory locations starting at the specified star ting address. After reading the pr[...]

Interrupt Priori ty Register s DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 4-5 The interrupt vectors are shown in Ta b l e C - 2 and the interrupt priorities are shown in Ta b l e C - 3 in Appendix C, "Programmer ’ s Reference" . T ab le 4-2 Interrupt Pr iority Leve l Bits IPL bits Interrupts[...]

Interrupt Priori ty Registers DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 4-6 F reescale Semico nductor Figure 4-2 Interrupt Priority Regi ster P Figure 4-3 Interrupt Prior ity Register C ESL0 ESL1 SHL0 SHL1 23 22 21 20 19 18 17 16 15 14 13 12 0 1 2 3 4 5 6 7 8 9 10 11 ESAI IPL SHI IPL reserved reserved reserved reserved reserve[...]

DMA Request Sources DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 4-7 4.6 DMA Request Sour ces The DMA Request Source bits (DRS0-DR S4 bits in the DMA Control/S tatus registers) encode the source of DMA requests used to trigger the DMA transfer s. The DMA request sources may be the internal peripherals or [...]

Device Identification (ID) Register DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 4-8 F reescale Semico nductor 4.7.2 Crystal Rang e Bit (XTLR) - Bit 15 The Crystal Range (XTLR) bit controls the on-chip crystal oscillator transconductance. The on-chip crystal oscillator is not used on th e DSP56364 since no XT AL pin is available.[...]

JT A G Boundary Sc an Register (BSR) DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 4-9 4.10 JT A G Boundary Scan Register (BSR) The boundary scan register (BSR) in the DSP56364 JT AG implementation contains bits for all device signal and clock pins and asso ciated control signals. All bidirectional pins ha[...]

JT A G Boundary Scan Register (BSR) DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 4-10 F reescale Semico nductor A12 Output3 Data SDO2/SDI3 - Control A[17:9] - Control SDO2/SDI3 Input/Output Data A11 Output3 Data SDO1 - Control A10 Output3 Data SDO1 Input/Output Data A9 Output3 Data SDO0 - Control A8 Output3 Data SDO0 Input/Output[...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 5-1 5 General Purpose Input/Output P or t (GPIO) 5.1 Intr oduction The General Purpose Input/Output (GPI O) pins are used for control a nd handshake functions between the DSP and external circuitry . The GPIO port has 4 I/ O pins (GPIO0-GPIO3) that are controll[...]

GPIO Pr ogramming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 5-2 F reescale Semico nductor 5.2.1 P or t B Contr ol Register (PCRB) The read/write Port B Control Regist er (PCRB) controls the functionality of the GPIO pins in conjunction with the Port B Direct ion Register (PRRB). 5.2.1.1 PCRB Contr ol Bits (PC[3:0]) - Bit[...]

GPIO Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 5-3 Port B Direction Register (PRRB) The read/write Port B Direction Re gister controls the direction of data transfer for each GPIO pin. 5.2.1.3 PRRB Direction Bits (PDC[3:0]) - Bits 3-0 When PDC[i] is set, the GP IO port pin[i] is co nf[...]

GPIO Pr ogramming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 5-4 F reescale Semico nductor NO TES[...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-1 6 Enhanced Serial A UDIO Interface (ESAI) 6.1 Intr oduction The Enhanced Serial Audio Interfac e (ESAI) provides a full-duplex se rial port for seri al communication with a variety of serial devi ces including one or more industry-standard codecs, other DSP[...]

Introd uction DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-2 F reescale Semico nductor Figure 6-1 ESAI Block Diagram SDO1 [PC10] SDO0 [PC11] Shift Register RX0 TX5 SDO5/SDI0 [PC6] Shift Register RX1 TX4 SDO4/SDI1 [PC7] Shift Register RX2 TX3 SDO3/SDI2 [PC8] Shift Register RX3 TX2 SDO2/SDI3 [PC9] Shift Register TX1 Shift Registe[...]

ESAI Data and Contr ol Pins DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-3 6.2 ESAI Data and Contro l Pins Three to twelve pins are require d for operation, depending on the opera ting mode selected and the number of transmitters and receivers enable d. The SDO0 and SDO1 pins are used by transmitters 0 [...]

ESAI Data and Control Pins DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-4 F reescale Semico nductor 6.2.4 Serial T ransmit 3/Receive 2 Data Pin (SDO3/SDI2) SDO3/SDI2 is used as the SDO3 sign al for transmitting data from the TX3 serial transmit s hift register when programmed as a transmitter pin, or as the SDI2 signal for rece[...]

ESAI Data and Contr ol Pins DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-5 When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register . When configured as the output flag OF0, this pin reflects the value of the OF0 bit in the SAICR register , and the[...]

ESAI Data and Control Pins DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-6 F reescale Semico nductor SCKT may be programmed as a general-purpose I/O pi n (PC3) when the ESAI SC KT function is not being used. NO TE Although the external ESAI serial clock can be independent of and asynchronous to the DSP system clock, the DSP cloc[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-7 6.2.10 Frame Sync f or T ransmitter (FST) FST is a bidirectional pin providing the frame sync for both the transmitters and receivers in the synchronous mode (SYN=1) and fo r the transmitters only in as ynchronous mode (SYN=0) (see Ta[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-8 F reescale Semico nductor special-purpose time slot register . The following paragraphs give detail ed descriptions and operations of each bit in the ESAI registers. The ESAI pins can also function as GPIO pins (Port C), described in Section 6.5, "GPIO -[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-9 Figure 6-3 ESAI Cloc k Generator Functiona l Block Diagram 6.3.1.2 TCCR T ransmit Prescaler Rang e (TPSR) - Bit 8 The TPSR bit controls a fixed divide -by-eight prescaler in series with the variable prescaler . This bit is used to ext[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-10 F reescale Semico nductor operational (see Figure 6-3 ). The maximum internally generated bit clock frequency is Fosc/4; the minimum internally generated bit clock frequency is Fosc/(2 x 8 x 256)=Fosc/4096. NO TE Do not use the combination TPSR=1 and TPM7-TP[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-11 Figure 6-4 ESAI Frame Sync Gener ator Functional Bloc k Diagram 6.3.1.4 TCCR Tx High Frequency Cloc k D ivider (TFP3-TFP0) - Bits 14–17 The TFP3–TFP0 bits control the divide ratio of the transmitter high frequency clock to the tr[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-12 F reescale Semico nductor 6.3.1.5 TCCR T ransmit Clock P olarity (TCKP) - Bit 18 The T ransmitter Clock Polarity (TCK P) bit controls on which bit cloc k edge data and frame sync are clocked out and latched in. If TCKP is cleared the data and the frame sync [...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-13 6.3.2 ESAI T r ansmit Control Register (TCR) The read/write T ransmit Control Re gister (TCR) controls the ESAI transmitter section. Interrupt enable bits for the transmitter section are provided in this control register . Op erating[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-14 F reescale Semico nductor In the network mode, the operation of clearing TE1 and setting it again disables the transmitter #1 after completing transmission of the c urrent data word until the beginning of the next frame. During that time period, the SDO1 pin[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-15 transmitter #4 is disabled after completing transmissi on of data currently in the ESAI transmit shift register . Data can be written to TX4 when TE4 is cleared but the data is not trans ferred to the transmit shift register #4. The [...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-16 F reescale Semico nductor Since the data word is shorter than the slot length, th e data word is extended until achieving the slot length, according to the following rule: 1. If the data word is left-aligned (TW A =0), and zer o padding is disabled (P ADC=0)[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-17 Figure 6-6 Normal and Netw ork Operation Normal Mode SERIAL FRAME SYNC SERIAL DA T A DA T A DA T A TRANSMITTER INTERRU PT (OR DMA REQUEST) AND FLAGS SE T RECEIVER INTERRUP T (OR DMA REQUEST) AND FLAGS SET NOTE: Interrupts occur and d[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-18 F reescale Semico nductor 6.3.2.10 TCR Tx Slot and W ord Length Select (TSWS4-TSWS0) - Bits 10-14 The TSWS4-TSWS0 bits are used to select the length of the slot and the length of the data words being transferred via the ESAI. The word length must be equa l t[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-19 6.3.2.11 TCR T ransmit Frame Sy nc Length (TFSL) - Bit 15 The TFSL bit selects the length of frame sync to be generated or recognized. If TFSL is cleared, a word-length frame sync is selected. If TFSL is se t, a 1-bit clock period fr[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-20 F reescale Semico nductor Figure 6-7 Frame Length Selection DA T A DA T A SERIAL CLOC K RX, TX FRAME SYNC WORD LENG TH: TFSL=0, RF SL=0 RX, TX SERIAL DA T A NOTE: Frame sync occurs while data is valid. DA T A DA T A SERIAL CLOC K RX, TX FRAME SYNC ONE BIT LE[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-21 6.3.2.12 TCR T ransmit Frame Sync Relative Timing (TFSR) - Bit 16 TFSR determines the relative timing of the tr ansmit frame sync signal as referred to the serial data lines, for a word length frame sync only (TFSL=0). When T FSR is [...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-22 F reescale Semico nductor 6.3.2.17 TCR T ransmit Even Slot Data Interrupt Enable (TEDIE) - Bit 21 The TEDIE control bit is used to enable the transmit even slot data in terr upts. If TEDIE is set, the transmit even slot data interrupts are enab led. If TEDIE[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-23 Hardware and software reset clear all the bits of the RCCR register . 6.3.3.1 RCCR Receiver Prescale Modulus Select (RPM 7–RPM0) - Bits 7–0 The RPM7–RPM0 bits specify the divide ratio of the prescale divider in the ESAI receive[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-24 F reescale Semico nductor The ESAI frame sync generator functional diagram is shown in Figure 6-4 . 6.3.3.4 RCCR Rx High Frequency Cloc k Divider (RFP3-RFP0) - Bits 14-17 The RFP3–RFP0 bits control the divide ratio of the receiver high frequenc y clock to [...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-25 6.3.3.8 RCCR Receiver Cloc k Sour ce Direction (RCKD) - Bit 21 The Receiver Clock Source Direction (RCKD) bit selects the s ource of the clock signal used to clock the receive shift register in the asynchronous mode (SYN=0) and the I[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-26 F reescale Semico nductor 6.3.3.10 RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 23 The Receiver High Frequency Clock Direction (RHC KD) bit selects the sour ce of the receiver high frequency clock when in the asynchronous mode (S YN=0), and the[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-27 receivers can be enabled) if the input data pin is not used by a transmitter . Operating modes are also selected in this register . Hardware and software reset clear all the bits in the RCR register . The ESAI RCR bits are describe d[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-28 F reescale Semico nductor 6.3.4.4 RCR ESAI Receiver 3 Enable (RE3) - Bit 3 When RE3 is set and TE2 is cleared, the ESAI receiv er 3 is enabled and samples data at the SDO2/SDI3 pin. TX2 and RX3 should not be enabled at the same time (RE3=1 and TE2=1). When R[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-29 6.3.4.9 RCR Receiver Slot and W or d Select (RSWS4-RSWS0) - Bits 10-14 The RSWS4-RSWS0 bits are used to select the length of the slot and the length of the data words being received via the ESAI. The word length must be equal to or s[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-30 F reescale Semico nductor 6.3.4.10 RCR Receiver Frame Sync Length (RFSL) - Bit 15 The RFSL bit selects the lengt h of the receive frame sync to be generated or recogn ized. If RFSL is cleared, a word-length frame sync is selecte d. If RFSL is set, a 1-bit cl[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-31 6.3.4.12 RCR Receiver Section P ersonal Reset (RPR) - Bit 19 The RPR control bit is used to put the receiver section of the ESAI in the personal reset state. The transmitter section is not af fected. When RPR is cl eared, the receive[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-32 F reescale Semico nductor 6.3.5 ESAI Common Contr ol Register (SAICR) The read/write Common Control Regist er (SAICR) contains control bits for functions that af fect both the receive and transmit sect ions of the ESAI.See Figure 6-10 . Hardware and software[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-33 6.3.5.5 SAICR Synchr onous Mode Selection (SYN) - Bit 6 The Synchronous Mode Selection (SYN) bit controls whet her the receiver and tran smitter sections of the ESAI operate synchronously or asynchronous ly with respect to each other[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-34 F reescale Semico nductor Figure 6-11 SAICR SYN Bit Op eration 6.3.6 ESAI Status Register (SAISR) The S tatus Register (SAISR) is a read-only status regi ster used by the DSP to read the status and serial input flags of the ESAI. See Figure 6-12 . The status[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-35 6.3.6.1 SAISR Serial Input Flag 0 (IF0) - Bit 0 The IF0 bit is enabled only when the SCKR pin is defined as ESAI in the Port Control Register , SYN=1 and RCKD=0, indicating that SCKR is an input flag and the s ynchronous mode is sele[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-36 F reescale Semico nductor 6.3.6.5 SAISR Receive Frame Sync Flag (RFS) - Bit 6 When set, RFS indicates that a r eceive frame sync occurred during recep tion of the words in the receiver data registers. This indicates that the data words are fr om the firs t s[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-37 6.3.6.10 SAISR T ransmit Frame Sync Flag (TFS) - Bit 13 When set, TFS indicates that a trans mit frame sync occurred in the curren t time slot. TFS is set at the start of the first time slot in the frame and cleared during al l other[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-38 F reescale Semico nductor 6.3.6.14 SAISR T ransmit Odd-Data Register Empty (T ODE) - Bit 17 When set, TODE indicates that the enabled transmitte r data registers became empty at the beginning of an odd time slot. Odd time slots are a ll odd-numbered slots (1[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-39 Figure 6-13 ESAI Data P ath Pr ogramming Model ([R/T]SHFD=0) SDI 23 16 15 8 7 0 70 7 0 7 0 RECEIVE HIGH BYTE RECEIVE MID DLE BYTE RECEIVE LOW BYTE ESAI RECEIVE DA T A REGISTER (READ ONL Y) SERIAL RECEIVE SHIFT REGISTER 23 16 15 8 7 0[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-40 F reescale Semico nductor Figure 6-14 ESAI Data P ath Pr ogramming Model ([R/T]SHFD=1) SDI 23 16 15 8 7 0 70 7 0 7 0 RECEIVE HIGH BYTE RECEIVE MIDD LE BYTE RECEI VE LOW BYTE ESAI RECEIVE DA T A RE GISTER (READ ONL Y) ESAI RECEIVE SHIFT REGISTER 23 16 15 8 7 [...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-41 6.3.7 ESAI Receive Shift Register s The receive shift registers (see Figure 6-13 and Figure 6-14 ) receive the incoming data from the serial receive data pins. Data is shifted in by the selected (i nternal/external) bit clock wh en t[...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-42 F reescale Semico nductor transmitter empty condition (TDE=1), or to tri-stat e the transmitter data pi ns. TSMA and TSMB should each be considered as containing half a 32-bit register TSM. See Figure 6-15 and Figure 6-16 . Bit number N in TSM (TS**) is the [...]

ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-43 After hardware or software reset, the TSM register is preset to $FFFFFFFF , which means that all 32 possible slots are enable d for data transmission. NO TE When operating in normal mode, bit 0 of the mask register must be set, other[...]

Operating Mod es DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-44 F reescale Semico nductor When bit number N in the RSM is set, the receive seque nce is as usual: data which is shifted into the enabled receivers shift registers is transferred to the receive data registers and the RDF flag is set. Data written to the RSM af fect[...]

Operating Modes DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-45 NO TE If the ESAI receiver section is already operating with some of the receivers, enabling additional receivers on the fly (i.e. without first putting the ESAI receiver in the personal re set state) by setting their REx control bits will [...]

Operating Mod es DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-46 F reescale Semico nductor the previous setting and the new frame is servic ed with the new setti ng without synchronization problems. Note that the maximum transmit last sl ot interrupt service time should not exceed N-1 ESAI bits service time (where N is the numb[...]

Operating Modes DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-47 or they may have their own separate clock and sync signals (a synchronous operating m ode). The SYN bit in the SAICR register selects s ynchronous or asynchronous operation. Si nce the ESAI is designed to operate either synchronously or asy[...]

GPIO - Pins and Regi sters DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-48 F reescale Semico nductor programming RSHFD bit in the RCR register for the receiver section, and by programming the TSHFD bit in the TCR register for the transmitter section. 6.4.5 Serial I/O Flags Three ESAI pins (FSR, SCKR and HC KR) are available as [...]

GPIO - Pins and Regi sters DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-49 6.5.2 P ort C Direction Register (PRRC) The read/write 24-bit Port C Direct ion Register (PRRC) in conjunction with the Port C Control Register (PCRC) controls the functionali ty of the ESAI GPIO pins. T able 6 -12 describes the [...]

ESAI Initialization Examples DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-50 F reescale Semico nductor configured as GPIO. If a port pin [i] is configured as a GPIO i nput, then the corresponding PD[i] bit reflects the value present on this pin. If a port pin [i] is configured as a GPIO out put, then the value written into the [...]

ESAI Initialization Examples DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-51 6.6.2 Initializing J ust the ESAI T ransmitter Section • It is assumed that the ESAI is operational; that is, at least one pin is defined as an ESAI pin. • The transmitter section should be in its personal reset state (TPR [...]

ESAI Initialization Examples DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-52 F reescale Semico nductor NO TES[...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-1 7 Serial Host Interface 7.1 Intr oduction The Serial Host Interface (SHI) is a serial I/O interface that provides a path for commu nication and program/coefficient data transfers between the DSP and an external host processor . The SHI can also communicate [...]

Serial Host Interface Internal Arch itecture DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-2 F reescale Semico nductor 7.2 Serial Host Interface Internal Ar chitecture The DSP views the SHI as a memory-mapped periphera l in the X data memory space. The DSP may access the SHI as a normal memory-mapped peripheral using standard po[...]

SHI Cloc k Generator DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-3 7.3 SHI Cloc k Generator The SHI clock generator generates the serial clock to the SHI if the in terface operates in the Master mode. The clock generator is disabled if the interface operates in the Slave mode, except in I 2 C mode when[...]

Serial Host Interface Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-4 F reescale Semico nductor Figure 7-4 SHI Programming Mod el—DSP Side HCKFR 8 15 14 13 12 11 10 9 16 23 22 21 20 19 18 17 0 23 SHI Receive Data FIFO (HRX) (read only, X: $FFFF94) HRX SHI Transmit Data Register (HTX) (write only, X: $FFFF93) [...]

Serial Host Interfa ce Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-5 The interrupt vector table for the Serial Host Interface is shown in Ta b l e 7 - 1 and the exceptions generated by the SHI are prioritized as shown in Ta b l e 7 - 2 . 7.4.1 SHI Input/Output Shi ft Register (IOSR)?[...]

Serial Host Interface Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-6 F reescale Semico nductor Figure 7-5 SHI I /O Shift Register ( IOSR) 7.4.2 SHI Host T ransmit Da ta Register (H TX)—DSP Side The Host T ransmit data register (HTX ) is used for DSP-to-Host data tran sfers. The HTX register is 24 bits wide. [...]

Serial Host Interfa ce Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-7 7.4.4.1 HSAR Reserved Bits—Bits 17–0,19 These bits are reserved and unused. They read as 0s a nd should be written with 0s for future compatibility . 7.4.4.2 HSAR I 2 C Slave Address (HA[6:3], HA1)—Bits 23–20[...]

Serial Host Interface Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-8 F reescale Semico nductor Figure 7-6 SPI Data-T o-Clock T iming Diagram The Clock Phase (CPHA) bit controls the relationshi p between the data on the MISO and MOSI pins and the clock produced or received at th e SCK pin. This control bit is u[...]

Serial Host Interfa ce Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-9 When in Master mode and CPHA = 1, the DSP core should write the next data word to HTX when HTDE = 1, clearing HTDE. The HTX data will be transfer red to the shift register for transmission as soon as the shift regist[...]

Serial Host Interface Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-10 F reescale Semico nductor When HFM[1:0] are cleared, the filter is bypassed (spikes are not filtered out). This mode is useful when higher bit-rate transfers are required and the SHI operates in a noise-free environment. When HFM1 = 1 and HF[...]

Serial Host Interfa ce Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-11 7.4.6.1.1 SHI Individual Reset While the SHI is in the individual reset state, SHI i nput pins are inhibited, output and bidirectional pins are disabled (high impedance), the HC SR status bits and the transmit/r ece[...]

Serial Host Interface Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-12 F reescale Semico nductor It is recommended that an SHI individual reset be generated (HEN cleared) before changing HCKFR. HCKFR is cleared during hardwa re reset and software reset. 7.4.6.5 HCSR Reserved Bits—Bits 23, 18 an d 16 These bit[...]

Serial Host Interfa ce Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-13 7.4.6.9 HCSR Idle (HIDLE)—Bit 9 The read/write control/status bit Host Idle (HIDLE) is used only in the I 2 C Master mode; it is ignored otherwise. It is only possible to se t the HIDLE bit during writes to th e H[...]

Serial Host Interface Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-14 F reescale Semico nductor NO TE Clearing HBIE will mask a pending bus-error interr upt only after a one-instruction-cycle delay . If HBIE is cleared in a long interrupt service routine, it is recommended that at le ast one other instruction [...]

Serial Host Interfa ce Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-15 NO TE Clearing HRIE[1:0] will mask a pe nding receive interrupt only after a one-instruction-cycle dela y . If HRIE[1:0] are clea red in a long interrupt service routine, it is recommende d that at least one other i[...]

SPI Bus Characteristics DSP56364 24-Bit Digital Signal Processor Users Manual, Re v . 2 7-16 F reescale Semico nductor 7.4.6.16 Host Receive FIFO Full (HRFF)—Bit 19 The read-only status bit Host Receiv e FIFO Full (HRFF) indicates that the Host Receive FIFO (HRX) is full. HRFF is set when the HRX FIFO is full. HRFF is cleared when HRX is read by [...]

I 2 C Bus Characte ristics DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-17 the master data input line, and MOSI is the master data output line. When the SPI is conf igured as a slave device, these pins reverse roles. Clock control logic allows a select ion of clock polarity and a choice of two fundament[...]

I 2 C Bus Characteristics DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-18 F reescale Semico nductor • Stop data transfer —The stop event is defined as a change in the state of the data line, from low to high, while the clock is high (see Figure 7-8 ). • Data valid —The state of the data line re presents valid data when,[...]

I 2 C Bus Characte ristics DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-19 the slave device is ready for the next byte transfer . The SHI supports this fe ature when operating as a master device and will wait until the slave device releases the SCL line before proceeding with the data transfer . 7.6.2 I[...]

SHI Pr ogramming Considerations DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-20 F reescale Semico nductor 7.7 SHI Pr ogramming Considerations The SHI implements both SPI and I 2 C bus protocols and can be programmed to operate as a slave device or a single-master device. Once the operating mode is selected, the SHI may communic[...]

SHI Prog ramming Considerations DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-21 7.7.2 SPI Master Mode The SPI Master mode is initiated by enabling th e SHI (HEN = 1), selecting the SPI mode (HI 2 C = 0), and selecting the Master mode of operation (HMST = 1). Before enab ling the SHI as an SPI master dev[...]

SHI Pr ogramming Considerations DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-22 F reescale Semico nductor • SCK/SCL is the SCL serial clock input. • MISO/SDA is the SDA open drain serial data line. • MOSI/HA0 is the HA0 slav e device address input. •S S /HA2 is the HA2 slave device address input. •H R E Q is the Host [...]

SHI Prog ramming Considerations DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-23 7.7.3.2 T ransmit Data In I 2 C Slave Mode A transmit session is initiated when the personal slave device address has been co rrectly identified and the R/W bit of the received slave device a ddress byte has been set. Follow[...]

SHI Pr ogramming Considerations DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-24 F reescale Semico nductor In the I 2 C Master mode, a data transfer session is always initiated by the DSP by writing to the HTX register when HIDLE is set. This condition ensures th at the data byte written to HTX will be interpreted as being a sla[...]

SHI Prog ramming Considerations DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-25 In a receive session, only the receiv e path is enabled and the HTX-to-I OSR transfers are inhibited. If the HRNE status bit is set, the HRX FI FO contains valid data, which may be read by th e DSP using either DSP instructi[...]

SHI Pr ogramming Considerations DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-26 F reescale Semico nductor NO TES[...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor A-1 Appendix A Bootstrap R OM A.1 DSP56364 Bootstrap Program ; BOOTSTRAP CODE FOR DSP56364 - (C) Copyright 1998 Freescale Inc. ; Revised August 11, 1998. ; ; ; This is the Bootstrap program contained in the DSP56364 192-word Boot ; ROM. This program can load an[...]

Bootstrap ROM DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 A-2 F reescale Semico nductor opt cex,mex,mu ;; ;;;;;;;;;;;;;;;;;;;; GENERAL EQUATES ;;;;;;;;;;;;;;;;;;;;;;;; ;; BOOT equ $D00000 ; this is the location in P memory ; on the external memory bus ; where the external byte-wide ; EPROM would be located AARV equ $D00409 ; AAR[...]

Bootstrap R OM DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor A-3 ; MD:MC:MB:MA=1110 - Bootstrap from SHI (I2C slave, HCKFR=1) ; MD:MC:MB:MA=1111 - Bootstrap from SHI (I2C slave, HCKFR=0) SHILD ; This is the routine which loads a program through the SHI port. ; The SHI operates in the slave ; mode, with the[...]

Bootstrap ROM DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 A-4 F reescale Semico nductor ;======================================================================== ; This is the routine that loads from external EPROM. ; MD:MC:MB:MA=0101 EPROMLD move #BOOT,r2 ; r2 = address of external EPROM movep #AARV,X:M_AAR1 ; aar1 configured f[...]

Bootstrap R OM DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor A-5 bra <* ;======================================================================== ; Code for burn-in ;======================================================================== M_OGDB EQU $FFFFFC ;; OnCE GDB Register M_PCRC EQU $FFFFBF ;; Por[...]

Bootstrap ROM DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 A-6 F reescale Semico nductor ;; write pattern to all memory locations if (EQUALDATA) ;; x/y ram symmetrical ;; write x and y memory clr a #start_dram,r0 ;; start of x/y ram move #>length_dram,n0 ;; length of x/y ram rep n0 mac x0,x1,a x,l:(r0)+ ;; exercise mac, write [...]

Bootstrap R OM DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor A-7 eor x1,a add a,b ;; accumulate error in b _loopx ;; check yram clr a #start_yram,r1 ;; restore pointer, clear a do n1,_loopy move y:(r1)+,a1 ;; a0=a2=0 eor x0,a add a,b ;; accumulate error in b _loopy endif ;; check pram clr a #start_pram,r2 [...]

Bootstrap ROM DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 A-8 F reescale Semico nductor dc * endm ORG PL:PATTERNS,PL:PATTERNS ;; Each value is written to all memories dc $555555 dc $AAAAAA dc $333333 dc $F0F0F0 NUM_PATTERNS equ *-PATTERNS ;======================================================================== ; This code fills[...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor B-1 Appendix B BDSL File B.1 BSDL FILE -- M O T O R O L A S S D T J T A G S O F T W A R E -- BSDL File Generated: Sun Aug 16 10:48:15 1998 -- -- Revision History: -- entity DSP56364 is generic (PHYSICAL_PIN_MAP : string := "TQFP100"); port ( TCK: in b[...]

BDSL File DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 B-2 F reescale Semico nductor EXTAL: in bit; TA_N: in bit; CAS_N: out bit; WR_N: out bit; RD_N: out bit; CVCC: linkage bit; CGND: linkage bit; AA1: out bit; AA0: out bit; A: out bit_vector(0 to 17); AGND: linkage bit_vector(0 to 3); AVCC: linkage bit_vector(0 to 3); DVCC: lin[...]

BDSL File DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor B-3 "PVCC: 31, " & "PCAP: 32, " & "PGND: 33, " & "EXTAL: 34, " & "TA_N: 38, " & "CAS_N: 39, " & "WR_N: 40, " & "RD_N: 41, " & "CVCC: 4[...]

BDSL File DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 B-4 F reescale Semico nductor attribute BOUNDARY_LENGTH of DSP56364 : entity is 86; attribute BOUNDARY_REGISTER of DSP56364 : entity is -- num cell port func safe [ccell dis rslt] "0 (BC_1, *, control, 1)," & "1 (BC_6, GPIO(3), bidir, X, 0, 1, Z)," &am[...]

BDSL File DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor B-5 "46 (BC_1, TA_N, input, X)," & "47 (BC_1, EXTAL, input, X)," & "48 (BC_1, RESET_N, input, X)," & "49 (BC_1, NMI_N, input, X)," & "50 (BC_1, *, control, 1)," & "51 (BC_6, HR[...]

BDSL File DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 B-6 F reescale Semico nductor[...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-1 Appendix C Programmer’ s Reference C.1 Intr oduction This section has been compiled as a reference for programmers. It cont ains a table show ing th e addresses of all the DSPs memory-mapped peripherals, an interr upt address table, an inte rrupt exceptio[...]

Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-2 F reescale Semico nductor DMA $FFFFF4 DMA ST A TUS REGISTER (DSTR) $FFFFF3 DMA OFFSET REGISTER 0 (D OR0) $FFFFF2 DMA OFFSET REGISTER 1 (D OR1) $FFFFF1 DMA OFFSET REGISTER 2 (D OR2) $FFFFF0 DMA OFFSET REGISTER 3 (D OR3) DMA0 $FFFFEF DMA SOURCE ADDRESS REGIS[...]

Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-3 Reserved $FFFFD7 thru $FFFFD0 RESER VED POR T B $FFFFCF POR T B CONTROL REGISTER (PCRB) $FFFFCE PORT B DIRECTION REGISTER (PRRB) $FFFFCD POR T B GPIO D A T A REGISTER (PDRB) Reserved $FFFFCC thr u $FFFFC0 RESER VED POR T C $FFFFBF[...]

Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-4 F reescale Semico nductor ESAI $FFFFBC ESAI RECEIVE SLO T MASK REGISTER B (RSMB) $FFFFBB ESAI RECEIVE SLOT MASK REGISTER A (RSMA) $FFFFBA ESAI TRANSMIT SLOT MASK REGISTER B (TSMB) $FFFFB9 ESAI TRANSMIT SLO T MASK REGISTER A (TSMA) $FFFFB8 ESAI RECEIVE CLOC[...]

Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-5 Reserved $FFFF9F thr u $FFFF95 RESER VED SHI $FFFF94 SHI RECEIVE FIFO (HRX) $FFFF93 SHI TRANSMIT REGISTER (HTX) $FFFF92 SHI I 2 C SLA VE ADDRESS REGISTER (HSAR) $FFFF91 SHI CONTROL/ST A TUS REGISTER (HCSR) $FFFF90 SHI CLOCK CONTRO[...]

Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-6 F reescale Semico nductor VBA:$2E 0 - 2 Reser ved VBA:$30 0 - 2 ESAI Receiv e Data VBA:$32 0 - 2 ESAI Receiv e Ev en Data VBA:$34 0 - 2 ESAI Receiv e Data With Exception Status VBA:$36 0 - 2 ESAI Receiv e Last Slot VBA:$38 0 - 2 ESAI T ransmit Data VBA:$3A[...]

Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-7 IRQD (External Interrupt) DMA Channel 0 Interr upt DMA Channel 1 Interr upt DMA Channel 2 Interr upt DMA Channel 3 Interr upt DMA Channel 4 Interr upt DMA Channel 5 Interr upt ESAI Receive Data wi th Exception Status ESAI Receive [...]

Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-8 F reescale Semico nductor C.2 Programming Sheets The following worksheets list the major programmable registers for the DSP56364. The programming sheets are grouped in the following order: • Central processor , • Phase Lock Loop, (PLL), • Enhanced Se[...]

Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-9 Figure C- 1. Status R egister ( SR) Application: Date: Programme r: Sheet 1 of 5 Central Processor 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 UZ V C 19 18 17 16 23 22 21 20 L LF S1 SM I1 I0 CE SA FV S0 N Scaling Mode S(1:0) Scaling Mode 0[...]

Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-10 F reescale Semico nductor Figure C-2. Operating Mode Register (OMR) Chip Operating Modes MOD(D:A) Reset Vector Descri ption ( Ta b l e 4 - 1 in Section 4.3, “Operating Modes ) Application: Date: Programmer: Sheet 2 of 5 1 5 1 4 1 3 1 2 1 1 1 0 987654321[...]

Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-11 Figure C-3. Interrupt Priorit y Register-Core (IPR-C) CENTRAL PROCESSOR 15 14 13 12 11 10 9 8 76543210 D1L0 IDL2 IDL1 I BL2 IBL1 IBL0 IAL2 IAL1 IAL0 D0L1 D0L0 23 22 21 20 19 18 16 17 D1L1 IAL2 Trigger 0 Level 1 Neg. Edge IRQA Mod[...]

Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-12 F reescale Semico nductor Figure C-4. Interrupt Prior ity Register - P eripherals (IPR-P) CENTRAL PROCESSOR * = Reserved, Program as 0 Interrupt Priority X:$FFFFFE R/W Reset = $000000 Register (IPR–P) ESL1 ESL0 Enabled IPL 00 N o — 01 Y e s 0 10 Y e s[...]

Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-13 Figure C-5. Phase Loc k Loop Contr ol Register (PCTL) PLL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MF7 MF5 MF4 MF3 MF2 MF1 MF0 19 18 17 16 23 22 21 20 PEN COD PD1 PD3 MF6 PD2 XTLD XTLR DF2 DF1 DF0 MF11 PD0 PSTP MF10 MF9 MF8 PLL Cont[...]

Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-14 F reescale Semico nductor Figure C-6. SHI Sla ve Address (HSAR) and Clock Contr ol Register (HCKR) Application: Date: Programmer: Sheet 1 of 3 SHI * 15 14 13 12 1 1 1 0 9876543210 HDM4 HDM2 HDM1 HDM0 HRS CPOL CPHA SHI Clock Control X:$FFFF90 Reset = $0000[...]

Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-15 Figure C-7. SHI Host T ransmit Data Register (HTX) and Host Receive Data Register (HRX) (FIFO) Application : Date: Programme r: Sheet 2 of 3 SHI 1 5 1 4 1 3 1 2 1 1 1 0 9876543 210 19 18 17 16 23 22 21 20 Host Transmit Data Re gi[...]

Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-16 F reescale Semico nductor Figure C-8. SHI Host Cont r ol/Statu s Registe r (HCSR) SHI * = Reserved, write as 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 10 HRQE0 HFIF0 HM1 HM0 HI 2 CH E N SHI Control/Stat us X:$FFFF91 Reset = $008200 Register (HCSR) 19 18 17 16 2[...]

Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-17 Figure C-9. ESAI T ransmit Clock Control Register (TCCR) TCKP 0 Transmitter Clock Polarity set to clockout on rising edge of transmitter clock, latch in on falling edg e of transmit clock 1 Transmitter Clock Polatiry set to clock[...]

Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-18 F reescale Semico nductor Figure C-10. ESAI T ransmit Clock Contr ol Register (TCR) 1 5 654 19 18 17 16 10 9 8 7 14 13 12 11 TE0 3210 TE2 23 22 21 20 TE1 TE3 TE4 TE5 TS HFD TMOD0 TFSL TFSR TEIE TEDIE TIE TLIE ESAI TCR - ESAI Transmit Clock C ontrol Regist[...]

Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-19 Figure C-11. ESAI Receive Cloc k Control Register (RCCR) 15 6 5 4 19 18 17 16 10 9 8 7 14 13 12 11 RPM0 3210 RPM2 23 22 21 20 RPM1 RPM3 RPM4 RPM5 RPM6 RPM7 RPSR RDC0 RDC 1 RDC2 RDC3 RDC4 RFP0 RFP1 RFP2 RFP3 RCKP RFSP RHCKP RCKD R[...]

Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-20 F reescale Semico nductor Figure C-12. ESAI Receive Cloc k Contr o l Register (RCR) 1 5 654 19 18 17 16 10 9 8 7 14 12 13 11 RE0 3210 RE2 23 22 21 20 RE1 RE3 Rsvd Rsvd RSHFD RWA RFSL RFSR REIE REDIE RIE RLIE RFSR Descript ion 0 1 Word-lengt h frame syn c [...]

Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-21 Figure C-13. ESAI C ommon Control Register ( SAICR) 15 6 5 4 19 18 17 1 6 10 9 8 7 14 12 13 11 OF0 3210 OF2 23 2 2 21 20 OF1 SYN TEBE Description SYN ESAI SAICR - ESAI Common Control Register X: $FFFFB4 Reset: $000000 ALC Descrip[...]

Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-22 F reescale Semico nductor Figure C-14. ESAI Status Re gister (SAISR) 15 6 5 4 19 18 17 16 10 9 8 7 14 13 12 11 IF0 3210 IF2 23 22 21 20 IF1 RFS RDF Description Description 0 1 Holds data sent from SC KR pin. ESAI SAISR - ESAI Status Register X: $FFFFB3 Re[...]

Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-23 Figure C-15. P ort B R egisters (PCRB, PRRB, PDRB) Application: Date: Programmer: Sheet 2 of 3 GPIO 2 3 1 1 987654 Port B Control Register X:$FFFFCF Reset = $0 (PCRB) ReadWrite * = Reserved, Program as 0 * 0 Port B (GPIO) 2 3 1 0[...]

Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-24 F reescale Semico nductor Figure C-16. P ort C R egisters (PCRC, PRRC, PDRC) Application: Date: Programmer: Sheet 2 of 3 GPIO 2 3 1 1 987654 PC9 PC8 PC7 P C6 PC5 PC4 Port C Control Register X:$FFFFBF Reset = $0 (PCRC) ReadWrite * = Reserved, Program as 0 [...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 Freescale Semiconductor Index-1 Inde x A adder modulo 1-5 offset 1-5 reverse-carry 1-5 Address Attribute 4-2 address attribute 4-2 Address Generation Unit 1-5 Address Tracing (AT) Mode 4-2 Address Tracing Enable (ATE) 4-2 addressing modes 1-6 AGU 1-5 B barrel shifter 1-4 Block Diagram [...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 Index-2 Freescale Semiconductor Receive Interrupt Enable Bits 7-14 SHI Control/Status Register 7-10 HDM0-HDM5 (HCKR Divider Modulus Select) 7-9 HEN (HCSR SHI Enable) 7-10 HFIFO (HCSR FIFO Enable Control) 7-12 HFM0-HFM1 (HCKR Filter Mode) 7-9 HI 2 C (HCSR Serial Host Interface I 2 C/SPI[...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 Freescale Semiconductor Index-3 P PAB 1-7 PAG 1-6 PC register 1-6 PCU 1-6 PDB 1-7 PDC 1-6 Peripheral I/O Expansion Bus 1-6 Peripheral modules 1-3 Peripherals (IPR-P) C-12 Phase Lock Loop Control Register (PCTL) C-13 PIC 1-6 PLL 1-7, 2-4 PLL Pre-Divider Factor (PD0-PD3) 4-8 Port A 2-4 P[...]

DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 Index-4 Freescale Semiconductor Sixteen-bit Compatibility 3-1 Size register (SZ) 1-6 SP 1-6 SPI 7-1, 7-16 HCSR Bus Error 7-16 Host Busy 7-16 Host Receive FIFO Full 7-16 Host Receive FIFO Not Empty 7-15 Host Receive Overrun Error 7-16 Host Transmit Data Empty 7-15 Host Transmit Underrun[...]