Freescale Semiconductor MCF51QE128RM инструкция обслуживания

Micr ocontr oller s freescale.com ColdFire Get the latest version fr om freescale. com MCF51QE128 MCF51QE64 MCF51QE32 Reference Manual MCF51QE128RM Re v . 3 09/2007[...]

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Get the latest version from freescale.com MCF51QE128 Series Features • 32-Bit V ersion 1 ColdFire ® Central Processor Unit (CPU) – Up to 50.33-MHz ColdFire CPU from 3.6V to 2.1 V , and 20-MHz CPU at 2.1V to 1.8V across temperature range of -40°C to 85°C – Provides 0.94 Dhrystone 2.1 MIPS per MHz performance when running from in tern al RAM[...]

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Get the latest version fr om freescale .com MCF51QE128 Reference Manual Covers MCF51QE128 MCF51QE64 MCF51QE32 MCF51QE128RM Re v . 3 09/2007 Freescale™ and the Freescal e logo are trade marks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2007. All rights reserved. Related Document ation: • MCF51QE128 (Data Sheet) Contains pi[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 6 F reescale Semiconductor Get the latest version from freescale.com[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 7 Get the latest version from freescale.com Contents Section Number Title Page Chapter 1 Device Overview 1.1 Devices in the MCF51QE128/64/32 Series .................................................................................... 2 3 1.2 MCU Block Diagram ..................[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 8 F reescale Semiconductor Get the latest version from freescale.com Section Number Title Page 3.7 W ait Modes ................................................................................................................. ..................... 50 3.7.1 W ait Mode ...................................[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 9 Get the latest version from freescale.com Section Number Title Page 4.5.4.1 W ait Mode ....................................................................................................... 88 4.5.4.2 S top Modes .............................................................[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 10 F reescale Semiconductor Get the latest version from freescale.com Section Number Title Page Chapter 6 Parallel Input/Output Control 6.1 Port Data and Data Directio n ............................................................................................... ......... 1 13 6.2 Pull-up, Slew Rat[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 11 Get the latest version from freescale.com Section Number Title Page 6.7.4.2 Port D Data Direction Register (P TDDD) .................................................... 127 6.7.4.3 Port D Pull Enable Register (P TDPE) ........................................................[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 12 F reescale Semico nductor Get the latest version from freescale.com Section Number Title Page 6.7.1 1.1 KBI2 Interrupt Status and Co ntrol Register (KBI2SC) ................................ 142 6.7.1 1.2 KBI2 Interrupt Pin Select Register (KBI2PE) .............................................. 142 [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 13 Get the latest version from freescale.com Section Number Title Page 7.3.4.5 Miscellaneous Instruction Execution T imes ................................................. 171 7.3.4.6 Branch Instruction Execution T imes .........................................................[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 14 F reescale Semico nductor Get the latest version from freescale.com Section Number Title Page 9.3.2.2 RGPIO Data (RGPIO_DA T A) ...................................................................... 200 9.3.2.3 RGPIO Pin Enable (RGPIO_ENB) ...........................................................[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 15 Get the latest version from freescale.com Section Number Title Page 1 1.1.5 Block Diag ram ........................................................................................................... .....219 1 1.2 External Signal Description ................................[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 16 F reescale Semico nductor Get the latest version from freescale.com Section Number Title Page 1 1.6.1.3 Analog Input Pins ......................................................................................... 237 1 1.6.2 Sources of Error ..........................................................[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 17 Get the latest version from freescale.com Section Number Title Page 12.4.5 DCO Maximum Frequency with 32.768 kHz Oscillator ................................................257 12.4.6 Internal Refere nce Clock .................................................................[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 18 F reescale Semico nductor Get the latest version from freescale.com Section Number Title Page 13.6 Interrupts ................................................................................................................ .......................275 13.6.1 Byte Transfer Interrupt ..................[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 19 Get the latest version from freescale.com Section Number Title Page 15.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................300 15.2.4 SCI Status Register 1 (SCIxS1) ..........................................[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 20 F reescale Semico nductor Get the latest version from freescale.com Section Number Title Page 16.4.4 SPI Status Register (SPIxS) ............................................................................................ 3 24 16.4.5 SPI Data Register (SPIxD) .......................................[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 21 Get the latest version from freescale.com Section Number Title Page 17.6.2 Description of Interr upt Operation ................................................................................. 353 17.6.2.1 T imer Overflow Interrupt (TOF) Description ........................[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 22 F reescale Semico nductor Get the latest version from freescale.com Section Number Title Page 18.4.1.5.8NOP ..........................................................................................397 18.4.1.5.9READ_CREG ..........................................................................397[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 23 Get the latest version from freescale.com Chapter 1 De vice Over vie w The MCF51QE128, MCF51QE64, and MCF51QE32 are members of the low-cost, low-power , high-performance V e rsion 1 (V1) ColdFire family of 32-bit microcontroller units (MCUs). All MCUs in the family use the [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 24 F reescale Semico nductor Get the latest version from freescale.com Chapter 1 Device Overview 1.2 MCU Bloc k Diagram The block diagram in Figure 1-1 shows the structure of the MCF51QE128/64/32 MCU. Exter nal IRQ yes Low-V oltage Detect (L VD) yes TPM1 channels 3 TPM2 channels 3 TPM3 channels 6 XOSC[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 25 Get the latest version from freescale.com Chapter 1 Device Overview Figure 1-1. MCF51QE128/64/32 Block Dia gram TPM2CH2-0 TPM1CH2-0 ANALOG COMP ARA T OR (ACMP1) ACM P 1 O ACM P 1 - ACM P 1 + V SS V DD IIC MODULE (IIC1) SERIAL PERIPHERAL INTERF ACE MODU LE (SPI1 ) USER FLASH[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 26 F reescale Semico nductor Get the latest version from freescale.com Chapter 1 Device Overview Ta b l e 1 - 2 provides the functional vers ion of the on-chip modules 1.3 V1 ColdFire Core The MCF51QE128/64/32 devices contain the V e rsion 1 (V1) ColdFire core optimized for area and low-power . This C[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 27 Get the latest version from freescale.com Chapter 1 Device Overview Figure 1-2. Simplified ICS Block Diagram 1.4.2 System Cloc k Distribution Figure 1-3 shows a simplified clock connect ion diagram. Some modules in the MCU have selectable clock inputs as shown. The clock i [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 28 F reescale Semico nductor Get the latest version from freescale.com Chapter 1 Device Overview Figure 1-3. Syst em Clock Distrib ution Diagram • OSCOUT — This is the direct output of the external osci llator module and can be selected as the real-time counter clock source. See Chapter 14, “Rea[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 29 Get the latest version from freescale.com Chapter 1 Device Overview The ADC module also has an internally generated as ynchronous clock that allows it to run in stop mode (ADACK). This signal is not available exte rnally and is not shown in this figure. 1.4.3 ICS Modes of O[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 30 F reescale Semico nductor Get the latest version from freescale.com Chapter 1 Device Overview Figure 1-4. ICS Mode s of Operation 1.4.3.6 FLL Bypassed Externa l Low-P ower (FBELP) In FLL bypassed external low-power mode, the FLLs are disabled and bypassed, and the ICS supplies a clock derived from [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 31 Get the latest version from freescale.com[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 32 F reescale Semico nductor Get the latest version from freescale.com Chapter 1 Device Overview[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 33 Get the latest version from freescale.com Chapter 2 Pins and Connections This section describes signals that connect to package pins. It incl udes pinout diagrams, recommended system connections, and detail ed discussions of signals. 2.1 Device Pin Assignment Figure 2-1 sho[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 34 F reescale Semico nductor Get the latest version from freescale.com Chapte r 2 Pins and Con nections Figure 2-1. 80-Pin LQFP V REFH V SSAD V DD V REFL V DDAD V SS PTB7/SCL1/EXTAL PTH7/SDA2 PTD0/KBI2P0/SPSCK2 PTD1/KBI2P1/MOSI2 PTE6/RGPIO6 PTB6/SDA1/XTAL PTH6/SCL2 PTE7/RGPIO7/TPM3CLK PTH1 PTH0 PTH3 P[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 35 Get the latest version from freescale.com Chapter 2 Pins an d Connections Figure 2-2. 64-Pin LQFP 2.2 Recommended System Connections Figure 2-3 shows pin connections common to MCF51QE128/64/32 application systems. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 36 F reescale Semico nductor Get the latest version from freescale.com Chapte r 2 Pins and Con nections Figure 2-3. Basic System Connections V DD V SS BKGD/MS RESET /IRQ OPTIONAL MANU AL RESET POR T A V DD BA CKGROUND HEADER C2 C1 X1 R F R S C BY 0.1 μ F SYSTEM POWER PT A0/KBI1P0/TPM1CH0/ADP0/A CMP1+[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 37 Get the latest version from freescale.com Chapter 2 Pins an d Connections 2.2.1 P ower V DD and V SS are the primary power supply pi ns for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator . The intern al voltage r[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 38 F reescale Semico nductor Get the latest version from freescale.com Chapte r 2 Pins and Con nections NO TE The RESET pin does not contain a clamp diode to V DD and should not be driven above V DD . NO TE In EMC-sensitive applica tions, an external RC filter is recommended on the RESET pin, if enabl[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 39 Get the latest version from freescale.com Chapter 2 Pins an d Connections Although the BKGD/MS pin is a ps eudo open-drain pin, the background debug communica tion protocol provides brief, actively driven, high speed-up pulses to ensure fast rise times. Small capacitances f[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 40 F reescale Semico nductor Get the latest version from freescale.com Chapte r 2 Pins and Con nections T able 2-1. Pin Assignme nt by P ackage and Pin Sharing Priority Pin Number Low est ←⎯ Priority ⎯→ Highest 80 64 P ort Pin Alt 1 Alt 2 Alt 3 Alt 4 1 1 PTD1 KBI2P1 MOSI2 2 2 PTD0 KBI2P0 SPSCK[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 41 Get the latest version from freescale.com 44 — PTJ2 45 35 PTF3 ADP13 46 36 PTF2 ADP12 47 37 PT A7 TPM2CH2 ADP9 48 38 PT A6 TPM1CH2 ADP8 49 39 PTE4 RGPIO4 50 40 VDD 51 41 VSS 52 42 PTF1 ADP11 53 43 PTF0 ADP10 54 — PTJ1 55 — PTJ0 56 44 PTD4 KBI2P4 57 45 PTD3 KBI2P3 SS2 [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 42 F reescale Semico nductor Get the latest version from freescale.com Chapte r 2 Pins and Con nections 2 IIC1 pins (SCL1 and SD A1) can be repositioned usin g SOPT2[IIC1PS]. Default locations are PT A3 and PT A2, respectively . 3 PT A4/ACMP1O/BKGD/MS is limited to output-only f or the por t I/O funct[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 43 Get the latest version from freescale.com Chapter 3 Modes of Operation 3.1 Intr oduction The operating modes of the MCF51QE128/64/32 are describe d in this chapter . Entry into each mode, exit from each mode, and functionality while in each of the modes are described. The o[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 44 F reescale Semico nductor Get the latest version from freescale.com Chapt er 3 Modes of Operat ion 3.3 Overview The ColdFire CPU has two primary user modes of operation, run and st op. (The CPU also supports a halt mode that is used strictly for debug operations.) The ST OP instructi on is used to [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 45 Get the latest version from freescale.com Chapter 3 Modes of Operation T able 3-1. CPU / P ower Mode Selections Mode of Operation SOPT1 SIM CSR2 BDC SPMSC1 PMC SPMSC2 PMC CPU and Peripheral Clocks Effects on Sub-System ST OPE WA I T E ENBDM 1 1 ENBDM is located in the upper[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 46 F reescale Semico nductor Get the latest version from freescale.com Chapt er 3 Modes of Operat ion Figure 3-2. Allowab le P ower Mode T ransitions f or Mission Mode MCF51QE128/64/32 Figure 3-2 illustrates mission mode st ate transitio ns allowed betwee n the legal states shown in Ta b l e 3 - 1 . P[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 47 Get the latest version from freescale.com Chapter 3 Modes of Operation Figure 3-3. All Allo wable P ower Mode T ransitions f or MCF51QE128/64/32 Ta b l e 3 - 2 defines triggers for the vari ous state transitions shown in Figure 3-2 . Ta b l e 3 - 2 . Tr i g g e r s f o r Tr[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 48 F reescale Semico nductor Get the latest version from freescale.com Chapt er 3 Modes of Operat ion Individual power states are discussed in more detail in the following sections. 3.4 Deb ug Mode Debug mode functions are managed through the background debug contro ller (BDC) in the V ersion 1 ColdFi[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 49 Get the latest version from freescale.com Chapter 3 Modes of Operation 3.6 Run Modes 3.6.1 Run Mode Run mode is the normal operating mode for the MCF51QE128/64/32. This mode is selected when the BKGD/MS pin is high at the rising edge of the internal reset si gnal. Upon exit[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 50 F reescale Semico nductor Get the latest version from freescale.com Chapt er 3 Modes of Operat ion 3.7 W ait Modes 3.7.1 W ait Mode W ait mode is entered by execut ing a ST OP instruction after configuring the device as per Ta b l e 3 - 1 . Upon execution of the STOP instructi on, the CPU enters a [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 51 Get the latest version from freescale.com NOTE If neither the W A ITE nor ST OPE bit is set when the CPU executes a ST OP instruction, the MCU does not enter ei ther of the stop modes. Instead, the MCU initiates an illegal opcode reset if CPUCR[IRD] is cleared or an illegal[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 52 F reescale Semico nductor Get the latest version from freescale.com Chapt er 3 Modes of Operat ion In addition to the above, upon waking up from stop2, SPMS C2[PPDF] is set. This flag is used to direct user code to go to a stop2 recovery routine. PPDF re mains set and the I/O pin states remain latc[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 53 Get the latest version from freescale.com Chapter 3 Modes of Operation S top4 is also entered if SPMSC1[L VDE, L VDSE] are set, enabling low voltage detect when the STOP instruction is executed. The L VD may only be used when the on-chip regulator is in full regulation mode[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 54 F reescale Semico nductor Get the latest version from freescale.com Chapt er 3 Modes of Operat ion Flash Off SoftNoClk FullNoClk SoftNoClk FullNoClk SoftOn P ort I/O Registers Off SoftNoClk FullNoClk SoftOn FullOn SoftOn ADC 1,2 Off SoftAD ACK (W ake Up) FULLAD A CK (W ake Up) SoftOn FullOn SoftOn [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 55 Get the latest version from freescale.com Chapter 3 Modes of Operation 3 FBELP refers to the ICS FLL bypassed e xter nal low-pow er state. See Chapter 12, “Inter nal Clock Source (S08ICSV3), ” for more details. 4 The PT A5/IRQ/TPM1CLK/RESET pin also has a direct connect[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 56 F reescale Semico nductor Get the latest version from freescale.com Chapt er 3 Modes of Operat ion[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 57 Get the latest version from freescale.com Chapter 4 Memory 4.1 MCF51QE128/64/32 Memory Map As shown in Figure 4-1 , on-chip memory in the MCF51QE128/64/32 series of MCUs consists of RAM and flash program memory for nonvolat ile code and data storage, plus I/O and control/st[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 58 F reescale Semico nductor Get the latest version from freescale.com Chapter 4 Memor y Regions within the memory map are s ubject to restrictions with regard to the types of allowable accesses. These are outlined in Ta b l e 4 - 1 . Non-supported access type s terminate the bus cycle with an error a[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 59 Get the latest version from freescale.com Chapter 4 Memor y NO TE Peripheral register locations for MCF51QE128/64/32 are shifted 0x(FF)FF_8000 compared with the MC9S08QE128/64/32 devices. • The ColdFire interrupt controller module is mapped in the periphe ral space and oc[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 60 F reescale Semico nductor Get the latest version from freescale.com Chapter 4 Memor y T able 4-2. Di rect-P age Regist er Summary (Sheet 1 of 4) Address Register Name B i t 7 654321 B i t 0 0x(FF)FF_8000 PT AD PT AD7 PT AD6 PT AD5 PT AD4 PT AD3 PT AD2 PT AD1 PT AD0 0x(FF)FF_8001 PT ADD PT ADD7 PT A[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 61 Get the latest version from freescale.com Chapter 4 Memor y 0x(FF)FF_8020 SCI1BDH LBKDIE RXEDGIE 0 SBR12 SBR11 SBR10 SBR9 SBR8 0x(FF)FF_8021 SCI1BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0x(FF)FF_8022 SCI1C1 LOOPS SCISW AI RSRC M W AKE IL T PE PT 0x(FF)FF_8023 SCI1C2 TIE [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 62 F reescale Semico nductor Get the latest version from freescale.com Chapter 4 Memor y 0x(FF)FF_8040 TPM1SC T OF T OIE CPWMS CLKSB CLKSA PS2 PS1 PS0 0x(FF)FF_8041 TPM1CNTH Bit 15 14 13 12 11 10 9 Bit 8 0x(FF)FF_8042 TPM1CNTL B i t 7 654321 B i t 0 0x(FF)FF_8043 TPM1MODH Bit 15 14 13 12 11 10 9 Bit 8[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 63 Get the latest version from freescale.com Chapter 4 Memor y 0x(FF)FF_8061 TPM3CNTH Bit 15 14 13 12 11 10 9 Bit 8 0x(FF)FF_8062 TPM3CNTL B i t 7 654321 B i t 0 0x(FF)FF_8063 TPM3MODH Bit 15 14 13 12 11 10 9 Bit 8 0x(FF)FF_8064 TPM3MODL B i t 7 654321 B i t 0 0x(FF)FF_8065 TP[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 64 F reescale Semico nductor Get the latest version from freescale.com Chapter 4 Memor y 0x(FF)FF_9804 SIMCTSC (Reserved) TMODE TEST TRSTPE TC 0x(FF)FF_9805 SIMCO (Reserved) 0000 0C S S P C O E 0 0x(FF)FF_9806 SDIDH 000 0 ID[11:8] 0x(FF)FF_9807 SDIDL ID[7:0] 0x(FF)FF_9808 SPMSC1 L VDF L VDA CK L VDIE [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 65 Get the latest version from freescale.com 0x(FF)FF_9 82D FD A T ALO1 (Reserved) 0000000 0 0x(FF)FF_982E FD A T AHI0 (Reserved) 0000000 0 0x(FF)FF_982F FD A T ALO0 (Reserved) 0000000 0 0x(FF)FF_9830 RTC S C RT I F RT C L K S RT I E RT C P S 0x(FF)FF_9831 RTCCNT R TCCNT 0x(FF[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 66 F reescale Semico nductor Get the latest version from freescale.com Chapter 4 Memor y 0x(FF)FF_9 84C PTDPE PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0 0x(FF)FF_9 84D PTDSE PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0 0x(FF)FF_984E PTDDS PTDDS7 PTDDS6 PTDDS5 PTDDS4 P TDDS3 PTD[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 67 Get the latest version from freescale.com Chapter 4 Memor y 4.2.1 Flash Module Reserved Memory Locations Several reserved flash memory locations, shown in Ta b l e 4 - 4 , are used for storing values used by corresponding peripheral registers. These registers in clude an 8-[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 68 F reescale Semico nductor Get the latest version from freescale.com Chapter 4 Memor y The factory trim values are stored in the flash information row (IFR) 1 and are automatically load ed into the ICSTRM and ICSSC registers after any reset. The oscillator trim values stored in TRIM and FTRIM can be[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 69 Get the latest version from freescale.com Chapter 4 Memor y to disengage security is by mass-erasing the flash (normally through the background debug interface) and verifying the flash is blank. 4.2.2 ColdFire Rapid GPIO Memory Map The rapid GPIO module is mapped into a 16-[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 70 F reescale Semico nductor Get the latest version from freescale.com Chapter 4 Memor y 4.3 RAM The MCF51QE128/64/32 includes up to 8 Kbytes of static RAM. RAM is most ef ficiently accessed using the A5-relative addressing mode (addre ss register in direct with displaceme nt mode). Any sing le bit in[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 71 Get the latest version from freescale.com Chapter 4 Memor y Flash memory is ideal for single -supply applications allowing for fi eld reprogramming without requiring external high voltage sources for program or er ase operations. The flash module includes a memory controlle[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 72 F reescale Semico nductor Get the latest version from freescale.com Chapter 4 Memor y • Command interface for fast program and erase operation • Up to 100,000 program/erase cycles at typical voltage and temperature • Flexible block protection (on any 2-Kbyte memory boundary) • Security feat[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 73 Get the latest version from freescale.com Chapter 4 Memor y The FOP T register is loaded from the flash configuration field (see Section 4.2.1 ) during the reset sequence, indicated by F in Figure 4-4 . The security feature in the flash module is described in Section 4.5.5,[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 74 F reescale Semico nductor Get the latest version from freescale.com Chapter 4 Memor y 4.4.2.4 Flash Pr otection Register (FPRO T and NVPRO T) The FPROT register define s which flash sectors are protected against program or erase operations. FPROT bits are readable and writable as long as the size o[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 75 Get the latest version from freescale.com 0x00–0 x3F 1 0x0_0000–0x1_FFFF 128 Kbytes 0x40 0x0_0000–0x1_F7FF 126 Kbytes 0x41 0x0_0000–0x1_EFFF 124 Kbytes 0x42 0x0_0000–0x1_E7FF 122 Kbytes 0x43 0x0_0000–0x1_DFFF 120 Kbytes 0x44 0x0_ 0000–0x1_D7FF 118 Kbytes 0x45 [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 76 F reescale Semico nductor Get the latest version from freescale.com Chapter 4 Memor y 4.4.2.5 Flash Status Register (FST A T) The FSTAT register defines the ope rational status of th e flash module. FCBEF , FPVIOL and F ACCERR are readable and writable. FBLANK is readable and not writable. The rema[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 77 Get the latest version from freescale.com Chapter 4 Memor y 4.4.2.6 Flash Command Register (FCMD) The FCMD register is the flash co mmand register . All FCMD bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable. 4.5 Function[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 78 F reescale Semico nductor Get the latest version from freescale.com Chapter 4 Memor y 4. Effects resulting from illeg al flash command write sequences or aborting flash operations 4.5.1.1 Writing the FCDIV Register Prior to issuing any flash command after a r eset, write the FCDIV re gister to divi[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 79 Get the latest version from freescale.com Chapter 4 Memor y Figure 4-9. Determination Pr ocedure for PRDIV8 an d FDIV Bits 4.5.1.2 Command Write Sequence The flash command controller supervises the comm and write sequence to execute program, erase, and erase verify algorith[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 80 F reescale Semico nductor Get the latest version from freescale.com Chapter 4 Memor y 2. W rite a valid command to the FCMD register . 3. Clear the FCBEF flag in the FST A T register by writing a 1 to FCBEF to launch the command. After a command is launched, the completion of the command operation [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 81 Get the latest version from freescale.com Chapter 4 Memor y Figure 4-10. Example Erase V erify Command Flow 4.5.2.2 Pr ogram Command The program operation programs a prev iously erased address in th e flash memory using an embedded algorithm. An example flow to execute the [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 82 F reescale Semico nductor Get the latest version from freescale.com Chapter 4 Memor y If an address to be programmed is in a protected area of the flash block, FST A T[FPVIOL] sets and the program command does not launch. After the program command has successfully launched and the program operation[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 83 Get the latest version from freescale.com Chapter 4 Memor y 4.5.2.3 Burst Pr og ram Command The burst program operation programs previously erased data in the flash memory using an embedded algorithm. While burst programming, two in ternal data registers opera te as a buffe[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 84 F reescale Semico nductor Get the latest version from freescale.com Chapter 4 Memor y Figure 4-12. Example Burst Pr ogram Command Flow 4.5.2.4 Sector Erase Command The sector erase operation erases all addresses in a 1 Kbyte sector of flash memory using an embedded algorithm. Write: Flash Arra y Ad[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 85 Get the latest version from freescale.com Chapter 4 Memor y An example flow to execute the s ector erase operation is shown in Figure 4-13 . The sector erase command write sequence is as follows: 1. W rite to an aligned flash block address to star t the command write sequen[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 86 F reescale Semico nductor Get the latest version from freescale.com Chapter 4 Memor y 4.5.2.5 Mass Erase Command The mass erase operation erases the entire flash array memory using an embedded algorithm. An example flow to execute the mass er ase operation is shown in Figure 4-14 . The mass erase c[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 87 Get the latest version from freescale.com NOTE The BDM can also perform a mass erase and verify command. See Chapter 18, “V ersion 1 ColdFire Debug (CF1_DEBUG) ,” for details. 4.5.3 Illegal Flash Operations 4.5.3.1 Flash Access Violations The F ACCERR flag is set during[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 88 F reescale Semico nductor Get the latest version from freescale.com Chapter 4 Memor y 4.5.3.2 Flash Pr otection Violations The FPVIOL flag is set after the command is written to the FCMD regis ter if any of the f ollowing illegal operations are attempted: 1. W riting the program command if the addr[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 89 Get the latest version from freescale.com Chapter 4 Memor y 4.5.5 Security The flash module provides the necessary security info rmation to the MCU. During each reset sequence, the flash module determines the secur ity state of the MCU as defined in Section 4.2.1, “Flash [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 90 F reescale Semico nductor Get the latest version from freescale.com Chapter 4 Memor y 5. If any of the keys are written on successive MCU clock cycles. 6. Executing a STOP instruction befo re all keys have been written. After the backdoor keys have been correctly matched, the MCU is unsecured. Afte[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 91 Get the latest version from freescale.com Chapter 4 Memor y One period of the resulting clock (1/f FCLK ) is used by the command proces sor to time program and erase pulses. An integer number of these timing pulses are used by th e command processor to complete a program or[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 92 F reescale Semico nductor Get the latest version from freescale.com Chapter 4 Memor y Figure 4-15. Pr ocedure for Clearing Se curity on MCF51QE128/64/ 32 via the BDM P or t Write CSR2[25:24]= 11 to initiate BDM reset to halt or write CSR2[25:24]=01 to initiate BDM reset to run On-chip flash is eras[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 93 Get the latest version from freescale.com Chapter 5 Resets, Interrupts, and General System Contr ol 5.1 Intr oduction This section discusses basic reset a nd interrupt mechanisms and the various sources of reset and interrupt on the MCF51QE128/64/32. Some interru pt sources[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 94 F reescale Semico nductor Get the latest version from freescale.com Chapter 5 Resets, Interrupts, and General System Control 5.3.1 Computer Operating Pr operly (COP) W atchdog The COP watchdog forces a system reset when the appli cation software fails to execute as expected. T o prevent a system re[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 95 Get the latest version from freescale.com Chapter 5 Resets, Interrupts, and General System Control 5.3.2 Illegal Operation Reset By default, the V1 ColdFire core generates a MCU reset when attempting to execute an illegal instruction (except for the ILLEGAL opcode), illegal[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 96 F reescale Semico nductor Get the latest version from freescale.com Chapter 5 Resets, Interrupts, and General System Control NO TE This pin does not contain a clamp diode to V DD and should not be driven above V DD . NO TE The voltage measured on the internally pulled up RESET pin is not pulled to [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 97 Get the latest version from freescale.com Chapter 5 Resets, Interrupts, and General System Control 5.5.2 L VD Reset Operation The L VD can be configured to generate a reset upon detection of a low vol tage condition by setting L VDRE to 1. The low voltage detectio n thresho[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 98 F reescale Semico nductor Get the latest version from freescale.com Chapter 5 Resets, Interrupts, and General System Control Refer to Chapter 4, “Memory ”, for the absolute address assignments for all registers. This section re fers to registers and control bits only by their names. A Freescale[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 99 Get the latest version from freescale.com Chapter 5 Resets, Interrupts, and General System Control 5.7.2 System Reset Status Register (SRS) This high page register incl udes read-only status flags to indicate th e source of the most recent reset. When a debug host forces re[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 100 F reescale Semico nductor Get the latest version from freescale.com Chapter 5 Resets, Interrupts, and General System Control 5.7.3 System Options Register 1 (SOPT1) All SOP T1 bit fields, except W AITE, are write-once. Th erefore for the write-once bits, only the first write after reset is honored[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 101 Get the latest version from freescale.com 5.7.4 System Options Register 2 (SOPT2) This high page register contains bits to configure MCU specifi c features on the MCF51QE128/64/32 devices. T able 5-4 . SOPT1 Regi ster Field Descriptions Field Description 7 COPE COP W a tch[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 102 F reescale Semico nductor Get the latest version from freescale.com Chapter 5 Resets, Interrupts, and General System Control 5.7.5 System De vice Identificati on Register (SDIDH, SDIDL) These high page read-only registers are included so host development systems can identify the ColdFire derivativ[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 103 Get the latest version from freescale.com Chapter 5 Resets, Interrupts, and General System Control 5.7.6 System P ower Mana gement St atus and Contr ol 1 Register (SPMSC1) This high page register contains st atus and control bits to support the low voltage detect function,[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 104 F reescale Semico nductor Get the latest version from freescale.com Chapter 5 Resets, Interrupts, and General System Control 5.7.7 System P ower Mana gement St atus and Contr ol 2 Register (SPMSC2) This high page register contains st atus and control bits to configure the low-power run and wait mo[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 105 Get the latest version from freescale.com Chapter 5 Resets, Interrupts, and General System Control 5.7.8 System P ower Mana gement St atus and Contr ol 3 Register (SPMSC3) This high page register reports the status of the low voltage warning function and to select the low [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 106 F reescale Semico nductor Get the latest version from freescale.com Chapter 5 Resets, Interrupts, and General System Control 76543210 RL V W F 0 LV D V LV W V LV W I E 000 W LV W A C K POR: 0 1 0000000 LV R : 0 1 0 U U 0000 Any other reset: 0 1 0 U U 0 000 1 L VWF is set when V Supply transitions [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 107 Get the latest version from freescale.com Chapter 5 Resets, Interrupts, and General System Control 5.7.9 System Cloc k Gating Control 1 Register (SCGC1) This high page register contains control bits to enable or disable the bus clock to the TPM x , ADC, IIC x , and SCI x m[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 108 F reescale Semico nductor Get the latest version from freescale.com Chapter 5 Resets, Interrupts, and General System Control 76543210 R1 FLS IRQ KBI x AC M P x RTC SPI2 SPI1 W R e s e t : 11111111 Figure 5-11. System Cloc k Gating Contr ol 2 Register (SCGC2) T able 5-13. SCG C2 Register Fiel d Des[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 109 Get the latest version from freescale.com Chapter 5 Resets, Interrupts, and General System Control[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 110 F reescale Semico nductor Get the latest version from freescale.com Chapter 5 Resets, Interrupts, and General System Control[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 111 Get the latest version from freescale.com[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 112 F reescale Semico nductor Get the latest version from freescale.com Chapter 5 Resets, Interrupts, and General System Control[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 113 Get the latest version from freescale.com Chapter 6 P arallel Input/Output Control This section explains software c ontrols related to parallel input/ output (I/O) and pin control. The MCF51QE128/64 devices have up to nine parallel I/O ports that include a total of 70 I/O [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 114 F reescale Semico nductor Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control It is good programming practice to write to the port data register before changing the direction of a port pin to become an output. This ensures that the pin is not driven for a shor t time [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 115 Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.2.3 P or t Drive Strength Select An output pin can be selected to have high output drive strength by setting the corresponding bit in the drive strength select register (P T x DSn). When hi[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 116 F reescale Semico nductor Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control The set/clear/toggle functionality allo ws software to af fect an individua l bit with a single write instruction, rather than using a re ad-modify-write sequence. 6.3.1 P or t Data Set Regi[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 117 Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control Figure 6-3. P or t Interrupt Bloc k Diagram W riting to the KBIPE n bits in the keyboard x interrupt pin enable register (KBI x PE) independently enables or disables each port pin. Each port [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 118 F reescale Semico nductor Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.5.4 Ke yboard Interrupt Initialization When an interrupt pin is first enable d, it is possible to get a false interrupt flag. T o prevent a false interrupt request during pin interrupt in [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 119 Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control The P T A4 and P T A5 pins are unique. P T A4 is an output only , so the control bits for the input functions do not have any effect on this pin. P T A5, when configured as an output, is open[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 120 F reescale Semico nductor Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.1.4 P or t A Slew Rate Enable Register (PT ASE) 6.7.1.5 P or t A Drive Strength Selection Reg ister (PT ADS) 76543210 R PT APE7 PT APE6 PT APE5 PT APE4 1 PT APE3 PT APE2 PT APE1 PT APE0 [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 121 Get the latest version from freescale.com 6.7.2 P or t B Registers Port B is controlled by the registers listed below . 6.7.2.1 P or t B Data Register (PTBD) 6.7.2.2 P or t B Data Direction Register (PTBDD) T able 6- 5. PT ADS Re gist er Field Descriptions Field Descriptio[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 122 F reescale Semico nductor Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.2.3 P or t B Pull Enable Register (PTBPE) The port B pull enable register en ables pull-ups on the corresponding P T B pin. In some cases, a pull-down device is enabled if pull-dow ns ar[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 123 Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.2.5 P or t B Drive Strength Selection Reg ister (PTBDS) 6.7.3 P or t C Registers Port C is controlled by the registers listed below . 6.7.3.1 P or t C Data Register (PTCD) 76543210 R PTBD[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 124 F reescale Semico nductor Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.3.2 P or t C Data Direction Register (PTCDD) 6.7.3.3 P or t C Data Se t Register (PTCSET) 6.7.3.4 P or t C Data Cl ear Register (PTCCLR) 76543210 R PTCDD7 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTC[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 125 Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.3.5 P or t C T oggle Register (PTCT OG) 6.7.3.6 P or t C Pull Enable Register (PTCPE) The port C pull enable register en ables pull-ups on the corresponding P T C pin. In some cases, a pu[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 126 F reescale Semico nductor Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.3.7 P or t C Slew Rate Enable Register (PTCSE) 6.7.3.8 P or t C Drive Strength Selection Reg ister (PTCDS) 6.7.4 P or t D Registers Port D is controlled by the registers listed below . 6[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 127 Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.4.2 P or t D Data Direction Register (PTDDD) 6.7.4.3 P or t D Pull Enable Register (PTDPE) The port D pull enable regi ster enables pull-ups on th e corresponding P TD pin. In some cases,[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 128 F reescale Semico nductor Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.4.4 P or t D Slew Rate Enable Register (PTDSE) 6.7.4.5 P or t D Drive Strength Selection Reg ister (PTDDS) 6.7.5 P or t E Registers Port E is controlled by the registers listed below . 6[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 129 Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.5.2 P or t E Data Direction Register (PTEDD) 6.7.5.3 P or t E Data Set Register (PTESET) T able 6-24. PTED Register Field Descriptions Field Description 7–0 PTED n P or t E Data Registe[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 130 F reescale Semico nductor Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.5.4 P or t E Data Cl ear Register (PTECLR ) 6.7.5.5 P or t E T oggle Register (PTET OG) 6.7.5.6 P or t E Pull Enable Register (PTEPE) The port E pull enable register en ables pull-ups on[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 131 Get the latest version from freescale.com 6.7.5.7 P or t E Slew Rate Enable Register (PTESE) 6.7.5.8 P or t E Drive Strength Selection Reg ister (PTEDS) T able 6-29. PTEPE Register Field Descriptions Field Description 7–0 PTEPE n Inter nal Pull Enable for P o r t E Bits.[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 132 F reescale Semico nductor Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.6 P or t F Registers Port F is controlled by the registers listed below . 6.7.6.1 P or t F Data Register (PTFD) 6.7.6.2 P or t F Data Dir ection Register (PTFDD) 6.7.6.3 P or t F Pull En[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 133 Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.6.4 P or t F Slew Rate Enable Register (PTFSE) 6.7.6.5 P or t F Drive Strength Selection Reg ister (PTFDS) 76543210 R PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0 W R e s e t :[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 134 F reescale Semico nductor Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.7 P or t G Registers Port G is controlled by the registers listed below . 6.7.7.1 P or t G Data Register (PTGD) 6.7.7.2 P or t G Data Direction Register (PTGDD) T able 6-36. PT FDS Regis[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 135 Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.7.3 P or t G Pull Enable Register (PTGPE) The port G pull enable regi ster enables pull-ups on th e corresponding P TG pin. In some cases, a pull-down device is enabled if pull-dow ns are[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 136 F reescale Semico nductor Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.8 P or t H Registers Port H is controlled by the registers listed below . 6.7.8.1 P or t H Data Register (PTHD) 6.7.8.2 P or t H Data Direction Register (PTHDD) T able 6-41. PTG DS Regis[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 137 Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.8.3 P or t H Pull Enable Register (PTHPE) The port H pull enable regi ster enables pull-ups on th e corresponding P TH pin. In some cases, a pull-down device is enabled if pull-dow ns are[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 138 F reescale Semico nductor Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.9 P or t J Registers Port J is controlled by the registers listed below . 6.7.9.1 P or t J Data Register (PTJD) 6.7.9.2 P or t J Data Direction Register ( PTJDD) T able 6-46. PTHDS Regis[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 139 Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.9.3 P or t J Pull Enable Register (PTJPE) The port J pull enable regi ster enables pull-ups on the corresponding P TJ pin. In some cases, a pull-down device is enabled if pull-dow ns are [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 140 F reescale Semico nductor Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.10 Ke yboard Interrupt 1 (KBI1) Register s KBI1 is controlled by the registers listed below . T able 6-52 shows KBI1 pin mapping to the port I/O pins. 6.7.10.1 KBI1 Int errupt Status and[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 141 Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.10.2 KBI1 Int errupt Pin Select Register (KBI1PE) 6.7.10.3 KBI1 Int errupt Edge Select Register (KBI1ES) 6.7.11 Ke yboard Interrupt 1 (KBI2) Register s KBI2 is controlled by the registers[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 142 F reescale Semico nductor Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control 6.7.11.1 KBI2 Int errupt Status and Control Register (KBI2SC) 6.7.11.2 KBI2 Int errupt Pin Select Register (KBI2PE) 76543210 R 0000 K B F 0 KBIE KBIMOD W KBACK R e s e t : 00000000 Figure 6-[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 143 Get the latest version from freescale.com 6.7.11.3 KBI2 Int errupt Edge Select Register (KBI2ES) 76543210 R KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBEDG3 KBEDG2 KBEDG1 KBEDG0 W R e s e t : 00000000 Figure 6-60. KBI2 Edge Select Regist er (KBI2ES) T able 6-59. KBI 2ES Register Fiel d [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 144 F reescale Semico nductor Get the latest version from freescale.com Chapter 6 Parallel Input/Output Control[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 145 Chapter 7 ColdFire Core 7.1 Intr oduction This section describes the organiza tion of the V ersion 1 (V1) ColdFire ® processor core and an overview of the program-visible registers. Fo r detailed information on instructi ons, see the ISA_C definition in the ColdFir e Fami[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 146 F reescale Semico nductor instruction, fetches the required operands and then executes the required function. Because the IFP and OEP pipelines are decoupled by an inst ruction buf fer serving as a FIFO que ue, the IFP is able to prefetch instructions in advance of their actual use b[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 147 • 16-bit status register (SR) • 32-bit supervisor stack pointer (SSP) • 32-bit vector base register (VBR) • 32-bit CPU configurat ion register (CPUCR) 7.2.1 Data Registers (D0–D7) D0–D7 data registers ar e for bit (1-bit), byte (8-bit ), word (16-[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 148 F reescale Semico nductor NO TE Registers D0 and D1 contai n hardware configuration details afte r reset. See Section 7.3.3.14, “Reset Exception” for more details. 7.2.2 Address Register s (A0–A6) These registers can be used as softwa re stack pointers, index registers, or base[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 149 T o support dual stack pointers, the following two supervisor instructions are included in the ColdFire instruction set architectur e to load/store the USP: move.l Ay,USP;move to USP move.l USP,Ax;move from USP These instructions ar e described in the ColdFir[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 150 F reescale Semico nductor 7.2.5 Pr ogram Counter (PC) The PC contains the currently exec uting instruction address. During in struction execution and exception processing, the processor automatically increments contents of the PC or places a new value in the PC, as appropriate. The P[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 151 Figure 7-7. V ector Base Register (VBR) 7.2.7 CPU Configuration Register (CPUCR) The CPUCR provides supervisor mode configurability of specific core functionality . Certain hardware features can be enabled/disabled indi vidually based on the state of the CPUC[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 152 F reescale Semico nductor 7.2.8 Status Register (SR) The SR stores the processor status and includes the CCR, the interrupt priority mask, and other control bits. In supervisor mode, software can access the enti re SR. In user mode, only the lower 8 bits (CCR) are accessible. The con[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 153 7.3 Functional Description 7.3.1 Instruction Set Ar chitecture (ISA_C) The original ColdFire Instructi on Set Architecture (ISA _A) was derived from the M68000 family opcodes based on extensive analysis of em bedded application code. The ISA was optimized for[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 154 F reescale Semico nductor 7.3.2 Exception Pr ocessing Overview Exception processing for ColdFire pr ocessors is streamlined for perfor mance. The ColdFire processors differ from the M6800 0 family because they include: • A simplified exception vector table • Reduced relocation ca[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 155 3. The processor saves the current context by creating an exception stack frame on the system stack. The exception stack frame is crea ted at a 0-modulo-4 addr ess on top of the system stack pointed to by the supervisor stack pointer (SSP). As shown in Figure[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 156 F reescale Semico nductor All ColdFire processors inhibit interrupt sampling dur ing the first instruction of all exception handlers. This allows any handler to disable interrupts ef fectiv ely , if necessary , by raising the interrupt mask level contained in the status re gister . I[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 157 • There is a 4-bit fault st atus field, FS[3:0], at the top of the system stack. Th is field is defined for access and address errors only and written as zeros for all other exceptions. See Ta b l e 7 - 8 . • The 8-bit vector number , vector[7 :0], define[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 158 F reescale Semico nductor The notion of a software IACK refers to the ability to query the interrupt controller near the end of an interrupt service routine (after the cu rrent interrupt request has been clea red) to determine if there are any pending (but currently masked) interr up[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 159 7.3.3 Pr ocessor Exceptions 7.3.3.1 Access Error Exception The default operation of the V1 ColdFi re processor is the generation of an illegal address r eset event if an access error (also known as a bus error) is detected. If CPUCR[ARD] is set, the reset is [...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 160 F reescale Semico nductor 7.3.3.3 Illegal Instruction Exception The default operation of the V1 ColdFire processor is the generation of an illegal opcode reset event if an illegal instruction is det ected. If CPUCR[IRD] is set, the reset is disabled and a processor exception is gener[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 161 In the original M68000 ISA definition, lines A and F were effe ctively reserved for user -defined operations (line A) and co-processor instructions (line F). Accordingly , there are two unique exception vectors associated with illegal opw ords in these two li[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 162 F reescale Semico nductor If the processor is not in trace mode and execute s a stop instruction where the immediate operand sets SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack frame points to the instruction after the stop, and the SR ref[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 163 The selection of the format value provides some limited debug support for porting code from M68000 applications. On M68000 family proc essors, the SR was located at the top of the stack. On those processors, bit 30 of the longword addressed by the syst em sta[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 164 F reescale Semico nductor 7.3.3.14 Reset Exception Asserting the reset input signal (RESET ) to the processor causes a reset exception. The reset exception has the highest priority of any excepti on; it provides for system initiali zation and recovery from catastrophic failure. Reset[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 165 T able 7-11. D0 Hardware Configuration Info Field Description Field Description 31–24 PF Processor f amily . This field is fixed to a he x value of 0xCF indicating a ColdFire core is present. 23–20 VER ColdFire core version nu mber . Defines t he hardw ar[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 166 F reescale Semico nductor Information loaded into D1 defines the local memory hardware configuration as shown in the figure below . BDM: Load: 0x61 (D1) Store: 0x41 (D1) Access: User read-only BDM read-only 31 30 29 28 27 2 6 25 24 23 22 21 20 19 18 17 16 R 00010000 F L A S H S Z 000[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 167 7.3.4 Instruction Execution Timing This section presents p roce ssor in struction execution times in terms of processor -core clock cycles. The number of operand references for eac h instruction is enclosed in parentheses following the number of processor clo[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 168 F reescale Semico nductor 7.3.4.2 MO VE Instruction Execution Times T able 7-14 lists execution times for MOVE.{B,W} instructions; T able 7-15 lists timings for MOVE.L. NO TE For all tables in this section, the execution time of a ny instruction using the PC-relative effective addres[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 169 7.3.4.3 Standar d One Operand Instruction Execution Times (d8,A y ,Xi*SF) 3(1/0) 3 (1/1) 3(1/1) 3(1/1) — — — xxx.w 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — — xxx.l 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — — (d16,PC) 2(1/0) 2(1/1) 2 (1/1) 2(1/1) 2(1/1) — —[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 170 F reescale Semico nductor 7.3.4.4 Standar d T w o Operand Instruction Execution Times T able 7-17. T wo Operand Instruct ion Execution Times Opcode <EA> Effective Address Rn (An) (An)+ -(An) (d16,An) (d16,PC) (d8,An,Xn*SF) (d8,PC,Xn*SF) xxx.wl #xxx ADD .L <ea>,Rx 1(0/0) 3[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 171 7.3.4.5 Miscellaneous Instruction Execution Times SUB.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3( 1/0) 4(1/0) 3(1/0) 1(0/0) SUB.L Dy ,<ea> — 3(1/1) 3(1/1) 3 (1/1) 3(1/1) 4(1/1) 3(1/1) — SUBI.L #imm,Dx 1(0/0) — — — — — — — SUBQ.L #im[...]

ColdFire Core MCF51QE128 MCU Series Reference Manual, Rev . 3 172 F reescale Semico nductor 7.3.4.6 Branch Instruction Ex ecution Times T P F . W 1 ( 0 / 0 ) ———— — —— T P F . L 1 ( 0 / 0 ) ———— — —— UNLK Ax 2(1 /0) — — — — — — — WDD A T A < ea> — 3(1/0 ) 3(1/0) 3 (1/0) 3(1/0) 4 (1/0) 3(1/0) — W D[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 173 Get the latest version from freescale.com Chapter 8 Interrupt Contr oller (CF1_INTC) 8.1 Intr oduction This interrupt controller (CF1_INT C) is intended for use in low-cost microcontroller designs using the V ersion 1 (V1) ColdFire processor core. In keeping with the gener[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 174 F reescale Semico nductor Get the latest version from freescale.com Chapter 8 Interrupt Cont roller (CF1_INTC) 8.1.1 Overview Interrupt exception processing incl udes interrupt recognition, aborting the current instruction execution stream, storing of an 8-byte except ion stack frame in memory , c[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 175 Get the latest version from freescale.com Chapter 8 Interrupt Con troller (CF1_INTC) type determines whether the program counter placed in the exception stack frame defines the location of the faulting instruction (fault) or the address of the next instruction to be execut[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 176 F reescale Semico nductor Get the latest version from freescale.com Chapter 8 Interrupt Cont roller (CF1_INTC) The basic ColdFire interrupt controll er supports up to 63 request sources mapped as nine priorities for each of the seven supporte d levels (7 levels × 9 priorities per level). W ithin [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 177 Get the latest version from freescale.com Chapter 8 Interrupt Con troller (CF1_INTC) means the 30 sources are mapped to a sparsely-populated two-dimens ional ColdFire array of seven interrupt levels and nine priorities within the level. The following associa tion between t[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 178 F reescale Semico nductor Get the latest version from freescale.com Chapter 8 Interrupt Cont roller (CF1_INTC) • Memory-mapped off-platform slave module — 64-byte space located at top end of memory: 0x(FF)FF_FFC0–0x(FF)FF_FFFF — Programming model accesse d via the peripheral bus — Encode[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 179 Get the latest version from freescale.com Chapter 8 Interrupt Con troller (CF1_INTC) The programming model follows the definition from previous ColdFire interrupt controllers. This compatibility accounts for the various memo ry holes in this module’ s memory map. 8.3.1 M[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 180 F reescale Semico nductor Get the latest version from freescale.com Chapter 8 Interrupt Cont roller (CF1_INTC) NO TE T ake special notice of the bit numbers within this register , 39–32. This is for compatibility with previous Co ldFire interrupt controllers. Figure 8-2. INTC_FRC Register 8.3.2.[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 181 Get the latest version from freescale.com Chapter 8 Interrupt Con troller (CF1_INTC) NO TE The requests associated with the INTC_F RC register have a fixed level and priority that cannot be altered. The INTC_PL6P7 register specifies the highest-priorit y , maskable interru[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 182 F reescale Semico nductor Get the latest version from freescale.com Chapter 8 Interrupt Cont roller (CF1_INTC) The interrupt controller's wa ke-up signal is defined as: wake-up = INTC_WCR[ENB] & (level of any asserted_int_request > INTC_WCR[MASK] ) Reset state of the INTC_WCR is disabl[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 183 Get the latest version from freescale.com Chapter 8 Interrupt Con troller (CF1_INTC) 8.3.2.5 INTC Clear Interrupt Force Register (INTC_CFRC) The INTC_CFRC register provides a simple memory-mapped mec hanism to clear a given bit in the INTC_FRC register to negate a speci fi[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 184 F reescale Semico nductor Get the latest version from freescale.com Chapter 8 Interrupt Cont roller (CF1_INTC) 8.3.2.6 INTC Software and Level- n IA CK Regist ers ( n = 1,2,3,...,7) The eight read-only interrupt acknowledge (IACK) registers can be expl icitly addressed via memory-mapped accesses o[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 185 Get the latest version from freescale.com Chapter 8 Interrupt Con troller (CF1_INTC) 8.3.3 Interrupt Request Leve l and Priority Assignments This section provides two vi ews of the interrupt request assignment: a two-dimensional vi ew of levels and priorities within the le[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 186 F reescale Semico nductor Get the latest version from freescale.com Chapter 8 Interrupt Cont roller (CF1_INTC) T able 8-12 presents the same information on interrupt reque st assignments, but from the highest priority request to the lowest. 3 IICx 1 KBIx 2 ADC ACMPx 3 ———— force_lvl3 15 79[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 187 Get the latest version from freescale.com Chapter 8 Interrupt Con troller (CF1_INTC) 8.4 Functional Description The basic operation of the CF1_INTC ha s been detailed in th e preceding sections. Th is section describes special rules applicable to non- maskable level seven [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 188 F reescale Semico nductor Get the latest version from freescale.com Chapter 8 Interrupt Cont roller (CF1_INTC) special case. The edge-sensitive natu re of these requests means the en coded 3-bit level input from the CF1_INTC to the V1 ColdFire co re must change state before the CPU detects an inte[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 189 Get the latest version from freescale.com Chapter 8 Interrupt Con troller (CF1_INTC) T o emulate the HCS08’ s 1-level IR Q nesting mec hanisms, the ColdFire implementation enables interrupts by clearing SR[I] (typically when using R TE to return to a process) and disable[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 190 F reescale Semico nductor Get the latest version from freescale.com Chapter 8 Interrupt Cont roller (CF1_INTC) Figure 8-8. ISR Code Snippet with SWIA CK This snippet includes the prologue and epilogue for an interrupt service rout ine as well as code needed to perform software IACK. At the entry p[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 191 Get the latest version from freescale.com Chapter 8 Interrupt Con troller (CF1_INTC)[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 192 F reescale Semico nductor Get the latest version from freescale.com Chapter 8 Interrupt Cont roller (CF1_INTC)[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 193 Get the latest version from freescale.com Chapter 9 Rapid GPIO (RGPIO) 9.1 Intr oduction The Rapid GPIO (RGPIO) module provi des a 16-bit general-purpose I/O mo dule directly connected to the processor ’ s high-speed 32-bit local platform bus. This conne ction to the pro[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 194 F reescale Semico nductor Get the latest version from freescale.com Chapter 9 Rapid GPIO (RGPIO) Figure 9-1. MCF51QE128 Series Bloc k Di agram Highlighting RGPIO Block a nd Pins TPM2CH2-0 TPM1CH2-0 ANALOG COMP ARA T OR (ACMP1) ACM P 1 O ACM P 1 - ACM P 1 + V SS V DD IIC MODULE (IIC1) SERIAL PERIPH[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 195 Get the latest version from freescale.com Chapter 9 Rapid GPIO (RGPIO) 9.1.1 Overview The RGPIO module provides 16-bits of high-speed GPIO functionality , mapped to the processor ’ s platform bus. The key features of this module include: • 16 bits of high-speed GPIO fu[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 196 F reescale Semico nductor Get the latest version from freescale.com Chapter 9 Rapid GPIO (RGPIO) Figure 9-2. V1 ColdFire Bloc k Diagram IA Generation Instruction F etch Cycle FIFO Instruction Buff er Decode & Select, Operand F etch Address Generation, Ex ecute IFP OEP IA G IC IB DSOC AGE X BDC[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 197 Get the latest version from freescale.com Chapter 9 Rapid GPIO (RGPIO) A simplified block diagram of the RGPIO module is shown in Figure 9-3 . The details of the pin muxing and pad logic are device-specific. Figure 9-3. RGPIO Bloc k Diagram 9.1.2 Features The major feature[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 198 F reescale Semico nductor Get the latest version from freescale.com Chapter 9 Rapid GPIO (RGPIO) – Register for reading current pin state – The two data registers (rea d, write) are mapped to a si ngle program-visible location — Alternate addresses to perfor m data set, clear , and toggle fu[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 199 Get the latest version from freescale.com Chapter 9 Rapid GPIO (RGPIO) 9.3 Memory Map/Register Definition The RGPIO module provides a compact 16-byte progra mming model based at a sy stem memory address of 0x(00)C0_0000 (noted as RGPI O_BASE throughout the chapter) . As pr[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 200 F reescale Semico nductor Get the latest version from freescale.com Chapter 9 Rapid GPIO (RGPIO) 9.3.2 Register Descriptions The RGPIO module provides 16 bits of high-speed general-purpose input/output functionality via a connection to the processo r ’ s 32-bit local bus. As a result, the RG PIO[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 201 Get the latest version from freescale.com Chapter 9 Rapid GPIO (RGPIO) Figure 9-5. RGPIO Data Regist er (RGPIO_D A T A) 9.3.2.3 RGPIO Pin Enable (RGPIO_ENB) The RGPIO_ENB register indicates the corresponding package pin is to be configured as a RGPIO pin instead of the nor[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 202 F reescale Semico nductor Get the latest version from freescale.com Chapter 9 Rapid GPIO (RGPIO) Figure 9-7. RGPIO Clear Data Register (RGPIO_CLR) 9.3.2.5 RGPIO Set Data (RGPIO_SET) The RGPIO_SET register provides a mechanism to se t specific bits in the RGPIO_DA T A register by performing a simpl[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 203 Get the latest version from freescale.com Chapter 9 Rapid GPIO (RGPIO) Figure 9-9. RGP IO T oggle Dat a Register (RGP IO_T OG) 9.4 Functional Description The RGPIO module is a relatively-simple design with its behavior c ontrolled by the program-visible registers defined w[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 204 F reescale Semico nductor Get the latest version from freescale.com Chapter 9 Rapid GPIO (RGPIO) • BCHG_LOOP: In this loop, a bit ch ange instruction was executed using the GPIO data byte as the operand. This instruction performs a read-modify-w rite operation and invert s the addressed bit. A p[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 205 Get the latest version from freescale.com Chapter 9 Rapid GPIO (RGPIO) align 16 send_16b_spi_m essage_rgpio: 00510: 4fef fff4 lea -12(%sp),%sp # allocate stack sp ace 00514: 48d7 008c movm.l &0x8c,(%sp) # save d2,d3,d7 00518: 3439 0080 0582 mov.w RAM_BASE+message2,%d2 [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 206 F reescale Semico nductor Get the latest version from freescale.com Chapter 9 Rapid GPIO (RGPIO)[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 207 Get the latest version from freescale.com Chapter 10 Analog Comparator 3V (A CMPVLPV1) 10.1 Intr oduction MCF51QE128 Series MCUs have two independent analog comparators (ACMPs), named ACMP1 and ACMP2. The analog comparator module (ACMP) provides a circuit fo r comparing tw[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 208 F reescale Semico nductor Get the latest version from freescale.com Chapter 10 Analog Comparator 3V (A CMPVLPV1) 10.1.4 Interrupt V ectors ACMP1 and ACMP2 share a single interrupt vector . Wh en interrupts are enabled for both ACMPs, the ACF bit in ACMP1SC and ACMP2SC mu st be polled to dete rmine[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 209 Get the latest version from freescale.com Chapter 10 Analog Comparator 3V (ACMPVLPV1) Figure 10-1. M CF51QE128 Series Bloc k Diagram Highlighting A CMP Bloc k and Pins TPM2CH2-0 TPM1CH2-0 ANALOG COMP ARA T OR (ACMP1) ACM P 1 O ACM P 1 - ACM P 1 + V SS V DD IIC MODULE (IIC1[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 210 F reescale Semico nductor Get the latest version from freescale.com Chapter 10 Analog Comparator 3V (A CMPVLPV1)[...]

Analog Comparator (S08ACMPVLPV1) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 211 10.1.5 Features The ACMP has the following features: • Full rail-to-ra il supply operation • Less than 40 mV of input offset • Less than 15 mV of hysteresis • Selectable interrupt on rising edge , falling edge, or either rising or f[...]

Analog Comparator (S08ACMPVLPV1) MCF51QE128 MCU Series Reference Manual, Rev . 3 212 F reescale Semico nductor Figure 10-2. Analog Comp arator Module Bloc k Diagram 10.2 External Signal Description The ACMP has two analog input pins : ACMP0 and ACMP1. Each of these pins can accept an input voltage that varies across the full operating voltage range[...]

Analog Comparator (S08ACMPVLPV1) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 213 10.4 Functional Description The ACMP module can be used to compare: • T wo analog input voltages applied to ACMP0 and ACMP1 or • An analog input voltage applied to ACMP0 with an internal bandgap reference voltage The ACBGS bit selects t[...]

Analog Comparator (S08ACMPVLPV1) MCF51QE128 MCU Series Reference Manual, Rev . 3 214 F reescale Semico nductor ACIE bit or the ACF bit. The ACIE bit is cleared by writing a logic zero and the ACF bit is cleared by writing a logic one.[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 215 Get the latest version from freescale.com Chapter 11 Analog-to-Digital Con ver ter (S08ADC12V1) 11.1 Intr oduction The 12-bit analog-to-digital convert er (ADC) is a successive appr oximation ADC desi gned for operation within an integrated microcontroller system-on-chip. [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 216 F reescale Semico nductor Get the latest version from freescale.com Chapter 11 Analog-to-Digital Converter (S08ADC12V1) Figure 11-1. MCF51QE128 Serie s Block Di ag ram Highlighting ADC Bloc k and Pins TPM2CH2-0 TPM1CH2-0 ANALOG COMP ARA T OR (ACMP1) ACM P 1 O ACM P 1 - ACM P 1 + V SS V DD IIC MODU[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 217 Get the latest version from freescale.com Chapter 11 Analog-to-D igital Con ver ter (S08ADC12V1) 11.1.2 Module Configurations This section provides device-specific information for configuring the ADC on the MCF51QE128 Series. 11.1.2.1 Channel Assignments The ADC channel as[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 218 F reescale Semico nductor Get the latest version from freescale.com Chapter 11 Analog-to-Digital Converter (S08ADC12V1) 11.1.2.3 Hardware T rigger The ADC may initiate a conversion via software or a hardware trigger . The R TC can be enabled as the hardware trigger for the ADC module by setting AD[...]

Analog-to-Digita l Con ver ter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 219 Get the latest version from freescale.com 11.1.4 Features Features of the ADC module include: • Linear successive approximation algorithm with 12-bit resolution • Up to 28 analog inputs • Output formatted in 12-, 10-, or 8-[...]

Analog-to-Digital Converter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 220 F reescale Semico nductor Get the latest version from freescale.com Figure 11-2. ADC Bloc k Diagram 11.2 External Signal Description The ADC module supports up to 28 se parate analog inputs. It also re quires four supply/reference/ground connections. T able[...]

Analog-to-Digita l Con ver ter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 221 Get the latest version from freescale.com 11.2.1 Analog P ower (V DD AD ) The ADC analog portion uses V DDAD as its power connection. In some packages, V DDAD is connected internally to V DD . If externally available, connect the[...]

Analog-to-Digital Converter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 222 F reescale Semico nductor Get the latest version from freescale.com 7654 3 210 RC O C O AIEN ADCO ADCH W R e s e t : 0001 1 111 Figure 11-3. Status and Contr ol Register (ADCSC1) T able 11-3. ADCSC1 Field Descriptions Field Description 7 COCO Conv ersion Co[...]

Analog-to-Digita l Con ver ter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 223 Get the latest version from freescale.com 11.3.2 Status and Contro l Register 2 (ADCSC2) The ADCSC2 register controls the compare function, convers ion trigger , and conversion active of the ADC module. 11.3.3 Data Result Hi gh R[...]

Analog-to-Digital Converter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 224 F reescale Semico nductor Get the latest version from freescale.com If the MODE bits are changed, a ny data in ADCRH becomes invalid. 11.3.4 Data Result Low Register (ADCRL) ADCRL contains the lower eight bits of the result of a 12-bi t or 10-bit conversion[...]

Analog-to-Digita l Con ver ter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 225 Get the latest version from freescale.com In 10-bit mode, the ADCCVH register holds the upper two bits of the 10-bit compare value (ADCV9 – ADCV8). These bits are compared to the upper two bits of the result fo llowing a conver[...]

Analog-to-Digital Converter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 226 F reescale Semico nductor Get the latest version from freescale.com 11.3.8 Pin Control 1 Re gister (APCTL1) The pin control registers disable the I/O port contro l of MCU pins used as analog inputs. APCTL1 is 3:2 MODE Conv ersion Mode Selection. MODE b its [...]

Analog-to-Digita l Con ver ter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 227 Get the latest version from freescale.com used to control the pins associated with channels 0–7 of the ADC module. 11.3.9 Pin Control 2 Re gister (APCTL2) APCTL2 controls channels 8–15 of the ADC module. 7654 3 210 R ADPC7 AD[...]

Analog-to-Digital Converter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 228 F reescale Semico nductor Get the latest version from freescale.com 11.3.10 P in Control 3 Register (APCTL3) APCTL3 controls channels 16–23 of the ADC module. T able 11-11. APCT L2 Register Field Descript ions Field Description 7 ADPC15 ADC Pin Control 15[...]

Analog-to-Digita l Con ver ter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 229 Get the latest version from freescale.com 11.4 Functional Description The ADC module is disabled during re set or when the ADCH bits are all high. The module is idle when a conversion has completed and another conversion has not [...]

Analog-to-Digital Converter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 230 F reescale Semico nductor Get the latest version from freescale.com 11.4.1 Clock Select and Divide Contr ol One of four clock sources can be selected as the cl ock source for the ADC module. This clock source is then divided by a configurable valu e to gene[...]

Analog-to-Digita l Con ver ter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 231 Get the latest version from freescale.com 11.4.4.1 Initiating Con versions A conversion is initiated: • Following a write to ADCSC1 (wit h ADCH bits not all 1s) if so ftware triggered operation is selected. • Following a hard[...]

Analog-to-Digital Converter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 232 F reescale Semico nductor Get the latest version from freescale.com 11.4.4.4 P ower Contr o l The ADC module remains in its idle st ate until a convers ion is initiated. If ADACK is selected as the conversion clock source, the ADACK clock generator is also [...]

Analog-to-Digita l Con ver ter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 233 Get the latest version from freescale.com example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency of 8 MHz, th en the conversion time for a s[...]

Analog-to-Digital Converter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 234 F reescale Semico nductor Get the latest version from freescale.com 11.4.7 MCU Stop3 Mode Operation S top mode is a low power-consumpti on standby mode during which most or all clock so urces on the MCU are disabled. 11.4.7.1 Stop 3 Mode With AD A CK Disabl[...]

Analog-to-Digita l Con ver ter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 235 Get the latest version from freescale.com NO TE Hexadecimal values designated by a pr eceding 0x, binary values designated by a preceding %, and decimal va lues have no preceding character . 11.5.1 ADC Module In itialization Exam[...]

Analog-to-Digital Converter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 236 F reescale Semico nductor Get the latest version from freescale.com ADCCVH/L = 0xxx Holds compare value when compare functi on enabled APCTL1=0x02 AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins APCTL2=0x00 All other AD pins [...]

Analog-to-Digita l Con ver ter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 237 Get the latest version from freescale.com 11.6.1.1 Analog Supply Pins The ADC module has analog power and ground supplies (V DDAD and V SSAD ) available as separate pins on some devices. V SSAD is shared on the same pin as the MC[...]

Analog-to-Digital Converter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 238 F reescale Semico nductor Get the latest version from freescale.com For proper conversion, the input voltage must fall between V REFH and V REFL . If the input is equal to or exceeds V REF H , the converter circuit converts the signal to 0xFFF (full scale 1[...]

Analog-to-Digita l Con ver ter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 239 Get the latest version from freescale.com — For stop3 mode operation, select ADACK as th e clock source. Operation in stop3 reduces V DD noise but increases effective conve rsion time due to stop recovery . • There is no I/O [...]

Analog-to-Digital Converter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 240 F reescale Semico nductor Get the latest version from freescale.com • Dif ferential non-linearity (DNL) — This error is de fined as the worst-case difference between the actual code width and the ideal code width for all conversions. • Integral non-li[...]

Analog-to-Digita l Con ver ter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 241 Get the latest version from freescale.com[...]

Analog-to-Digital Converter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev . 3 242 F reescale Semico nductor Get the latest version from freescale.com[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 243 Get the latest version from freescale.com Chapter 12 Internal Cloc k Sour ce (S08ICSV3) 12.1 Intr oduction The internal clock source (ICS) m odule provides clock source choices for the MCU. The module contains a frequency-locked loop (FLL) as a cl ock source that is contro[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 244 F reescale Semico nductor Get the latest version from freescale.com Chapter 12 Internal Clock Source (S08ICSV3) Figure 12-1. M CF51QE128 Series Bloc k Diagram Highlighting I CS Block and Pins TPM2CH2-0 TPM1CH2-0 ANALOG COMP ARA T OR (ACMP1) ACM P 1 O ACM P 1 - ACM P 1 + V SS V DD IIC MODULE (IIC1)[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 245 Get the latest version from freescale.com Chapter 12 Internal Clock Source (S08ICSV3)[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 246 F reescale Semico nductor Get the latest version from freescale.com Chapter 12 Internal Clock Source (S08ICSV3)[...]

Internal Clock Source (S08ICSV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 247 Get the latest version from freescale.com 12.1.3 Features Key features of the ICS module are: • Frequency-locked loop (FLL) is trimmable for accurac y • Internal or external reference clocks can be used to control the FLL • Reference [...]

Internal Clock Sour ce (S08ICSV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 248 F reescale Semico nductor Get the latest version from freescale.com 12.1.4 Block Diagram Figure 12-2 is the ICS block diagram. Figure 12-2. In ternal Cloc k Source (ICS) Block Dia gram 12.1.5 Modes of Operation There are seven modes of operation for the ICS: FEI, [...]

Internal Clock Source (S08ICSV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 249 Get the latest version from freescale.com 12.1.5.4 FLL Bypassed Interna l Low P ower (FBILP) In FLL bypassed internal low-power mode, the FLL is disabled and bypassed, and the ICS supplies a clock derived from the internal reference clock. [...]

Internal Clock Sour ce (S08ICSV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 250 F reescale Semico nductor Get the latest version from freescale.com 12.3.1 ICS Contro l Register 1 (ICSC1) 7 6 5 432 1 0 R CLKS RDIV IREFS IRCLKEN IREFSTEN W Reset: 0 0 0 0 0 1 0 0 Figure 12-3. ICS Contr o l Register 1 (ICSC1) T able 12-2. ICSC 1 Field Descrip tio[...]

Internal Clock Source (S08ICSV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 251 Get the latest version from freescale.com 12.3.2 ICS Contro l Register 2 (ICSC2) 12.3.3 ICS T rim Register (ICSTRM) 7 6 5 432 1 0 R BDIV RANGE HGO LP EREFS ERCLKEN EREFS TEN W R e s e t : 0 1 0 000 0 0 Figure 12-4. ICS Contr o l Register 2 [...]

Internal Clock Sour ce (S08ICSV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 252 F reescale Semico nductor Get the latest version from freescale.com 12.3.4 ICS Status and Contro l (ICSSC) T able 12-5. ICSTRM Field Des criptions Field Description 7:0 TRIM ICS T rim Setting. The TRIM bits control the inter nal reference clock frequency b y contr[...]

Internal Clock Source (S08ICSV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 253 Get the latest version from freescale.com r 1 OSCINIT OSC Initialization. If EREFS is set an d the external refe rence cloc k is selected by ERCLKEN or by the ICS being in FEE, FBE, or FBELP mode, this bit is set after the in itialization c[...]

Internal Clock Sour ce (S08ICSV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 254 F reescale Semico nductor Get the latest version from freescale.com 12.4 Functional Description 12.4.1 Operational Modes Figure 12-7. Cloc k Switching Modes The seven states of the ICS are show n as a state diagram and are describe d below. The arrows indicate the[...]

Internal Clock Source (S08ICSV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 255 Get the latest version from freescale.com 12.4.1.2 FLL Engaged External (FEE) The FLL engaged external (FEE) mode is ente red when all the following conditions occur: • CLKS bits are written to 00. • IREFS bit is written to 0. • RDIV [...]

Internal Clock Sour ce (S08ICSV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 256 F reescale Semico nductor Get the latest version from freescale.com In FLL bypassed external mode, the ICSOUT clock is deri ved from the external reference clock. The external reference clock controls the FLL clock, a nd the FLL loop locks the F LL frequency to th[...]

Internal Clock Source (S08ICSV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 257 Get the latest version from freescale.com 12.4.4 Low P ower Bit Usage The low-power bit (LP) is provided to allow the FLL to be disabled and conserve power when it is not being used. The DRS bits can not be written while LP bit is 1. Howeve[...]

Internal Clock Sour ce (S08ICSV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 258 F reescale Semico nductor Get the latest version from freescale.com 12.4.8 Fixed Frequency Cloc k 12.4.9 The ICS presents the divided FLL reference cloc k as ICSFFCLK for use as an additional clock source. ICSFFCLK frequency must be no more than 1/4 of the IC SOUT[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 259 Get the latest version from freescale.com Chapter 13 Inter -Integrated Cir cuit (S08IICV2) 13.1 Intr oduction The inter- integrated circuit (IIC) provides a method of commu nication between a numb er of devices. The interface is designed to operate up to 100 kbps with maxi[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 260 F reescale Semico nductor Get the latest version from freescale.com Chapter 13 Inter-Integrated Circuit (S08IICV2) Figure 13-1. M CF51QE128 Series Bl ock Di agram Highlighting the IIC Modul es TPM2CH2-0 TPM1CH2-0 ANALOG COMP ARA T OR (ACMP1) ACM P 1 O ACM P 1 - ACM P 1 + V SS V DD IIC MODULE (IIC1[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 261 Get the latest version from freescale.com Chapter 13 Inter-Integrated Circuit (S08IICV2)[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 2-262 F re escale Semiconductor 13.1.3 Features The IIC includes these distinctive features: • Compatible with IIC bus standard • Multi-master operation • Software programmable for one of 64 different serial clock frequencies • Software selectable acknowledge bit • Interrupt driven byte-by-b[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 2-263 13.1.5 Block Diagram Figure 13-2 is a block diagram of the IIC. Figure 13-2. IIC Functiona l Block Diagram 13.2 External Signal Description This section describes each user -accessible pin signal. 13.2.1 SCL — Serial Clock Line The bidirectional SCL is the serial clock[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 2-264 F re escale Semiconductor Refer to the direct-page register summary in the memory chapter of this document for the absolute address assignments for all IIC registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to tran[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 2-265 For example, if the bus speed is 8 M Hz, the table below shows the possibl e hold time values with different ICR and MUL T selections to achie ve an IIC baud rate of 100kbps. T able 13-3. IICF F ield Descriptions Field Description 7–6 MUL T IIC Multip lier F actor . Th[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 2-266 F re escale Semiconductor T able 13-5. II C Divider and Hold V alues ICR (hex) SCL Divider SD A Hold Va l u e SCL Hold (Start) Va l u e SD A Hold (Stop) Va l u e ICR (hex) SCL Divider SD A Hold Va l u e SCL Hold (Start) Va l u e SCL Hold (Stop) Va l u e 00 20 7 6 1 1 20 1 6 0 1 77 88 1 01 22 7 7[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 2-267 13.3.3 IIC Contr ol Register (IICC1) 76543210 R IICEN IICIE MST TX T XAK 000 W RST A R e s e t 00000000 = Unimplemented or Reser ved Figure 13-5. IIC Contro l Register (IICC1) T able 13-6. IICC1 Field Descriptions Field Description 7 IICEN IIC Enable . The IICEN bit dete[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 2-268 F re escale Semiconductor 13.3.4 IIC Status Register (IICS) 76543210 RT C F IAAS BUSY ARBL 0S R W IICIF RXAK W R e s e t 10000000 = Unimplemented or Reser ved Figure 13-6. IIC Stat us Register (IICS) T able 13-7. IICS Field Descriptions Field Description 7 TCF T ransfer Complete Flag. This bit i[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 2-269 13.3.5 IIC Data I/O Register (IICD) NO TE When transitioning out of master r eceive mode, the IIC mode should be switched before reading the IICD register to prevent an inadvertent initiation of a master receive data transfer. In slave mode, the same functions are avai l[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 2-270 F re escale Semiconductor 13.4 Functional Description This section provides a complete func tional description of the IIC module. 13.4.1 IIC Pr otocol The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for da ta transfer. All devices connected to it must have open dra[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 2-271 Figure 13-9. II C Bus T ransmission Signals 13.4.1.1 Star t Signal When the bus is free, no master de vice is engaging the bus (SCL and SDA lines are at logical high), a master may initiate communication by se nding a start signal. As shown in Figure 13-9 , a start signa[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 2-272 F re escale Semiconductor 13.4.1.3 Data T ransfer Before successful slave addressing is achieved, the da ta trans fer can proceed byte-by-byte in a direction specified by the R/W bit sent by the calling master. All transfers that come after an addres s cycle are referred to as data transf ers , [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 2-273 the transition from master to slave mode does not ge nerate a stop condition. Meanwh ile, a status bit is set by hardware to indicate loss of arbitration. 13.4.1.7 Clock Synchr onization Because wire-AND logic is performed on the SCL line, a high-to-low transition on the[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 2-274 F re escale Semiconductor 13.4.2 10-bit Address For 10-bit addressing, 0x1 1 1 10 is used fo r the first 5 bits of the first addr ess byte. V arious combinations of read/write formats are possible within a transfer that includes 10-bit addressing. 13.4.2.1 Master-T ransmitter Ad dresses a Slave-[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 2-275 13.4.3 General Call Address General calls can be requested in 7- bit address or 10-bit addr ess. If the GCAEN bit is set, the II C matches the general call address as well as its own slave addres s. When the IIC responds to a general call, it acts as a slave-receiver and[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 2-276 F re escale Semiconductor Arbitration is lost in th e following circumstances: • SDA sampled as a low when the master drives a high during an address or data transmit cycle. • SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle. • A start c[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 2-277 13.7 Initialization/Application Inf ormation Figure 13-11. IIC Module Quic k Start Module Initializat ion (Slave) 1. Wr ite: IICC2 — to enable or disable general call — to select 10-bit or 7-bit ad dressing mode 2. Write: IICA — to set the slave address 3. Wr ite: [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 2-278 F re escale Semiconductor Figure 13-12. T ypical IIC Interrupt Routine Clear Master Mode ? Tx/Rx ? Last Byte T ransmitted ? RXAK=0 ? End of Addr Cycle (Master Rx) ? Write Next Byte to IICD Switch to Rx Mode Dummy Read from IICD Generate Stop Signal Read Data from IICD and Store Set TXA CK =1 Gen[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 2-279[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 2-280 F re escale Semiconductor[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 281 Get the latest version from freescale.com Chapter 14 Real-Time Counter (S08R TCV1) 14.1 Intr oduction The real-time counter (R TC) consists of one 8-bit counter , one 8-bi t comparator , several binary-based and decimal-based prescaler dividers, three clock sources, and on[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 282 F reescale Semico nductor Get the latest version from freescale.com Chapter 14 Real-Time Counter (S08RTCV1) 14.1.5 Interrupt V ector See Chapter 8, “Interrupt Controller (CF1_INTC) ,” for the R TC interrupt vector assignment.[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 283 Get the latest version from freescale.com Chapter 14 Real-Time Coun ter (S08RTCV1) MCF51QE128 Bloc k Diagram Hi ghlightin g RTC Bloc k and Pins TPM2CH2-0 TPM1CH2-0 ANALOG COMP ARA T OR (ACMP1) ACM P 1 O ACM P 1 - ACM P 1 + V SS V DD IIC MODULE (IIC1) SERIAL PERIPHERAL INTE[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 284 F reescale Semico nductor Get the latest version from freescale.com 14.1.6 Features Features of the R TC module include: • 8-bit up-counter — 8-bit modulo match limit — Software controllable periodic interrupt on match • Three software selectable clock sources for input to prescaler with s[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 285 Get the latest version from freescale.com 14.1.8 Block Diagram The block diagram for the R TC module is shown in Figure 14-1 . Figure 14-1. Real-Time Coun ter (R TC) Bloc k Diagram 14.2 External Signal Description The R TC does not include any off-chip signals. 14.3 Regist[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 286 F reescale Semico nductor Get the latest version from freescale.com 14.3.1 R TC Status and Co ntrol Register (R TCSC) R TCSC contains the real-time interrupt status flag (R TIF), the clock se lect bits (R TCLKS), the real-time interrupt enable bit (R TIE), and the prescaler select bits (R TCPS). 7[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 287 Get the latest version from freescale.com 14.3.2 RTC Counter Register (R TCCNT) R TCCNT is the read-only value of the current R TC count of the 8-bit counter . 14.3.3 R TC Modulo Register (R TCMOD) 14.4 Functional Description The R TC is composed of a main 8-bit up-counter[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 288 F reescale Semico nductor Get the latest version from freescale.com R TCPS and the R TCLKS[0] bit se lect the desired divide-by value. If a different value is written to RT C P S , the prescaler and R TCCNT counters are reset to 0x00. T able 14-6 shows different prescaler period values. The R TC m[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 289 Get the latest version from freescale.com Figure 14-5. R TC Counter Overflow Example In the example of Figure 14-5 , the selected clock source is the internal clock sour ce. The prescaler (R TCPS) is set to 0x2 or divide-by- 4. The modulo value in th e R TCMOD register is [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 290 F reescale Semico nductor Get the latest version from freescale.com Notes : Interrupt service routine fo r RTC module. ************************************ **********************************/ #pragma TRAP_PROC void RTC_ISR(void) { /* Clear the interrupt flag */ RTCSC.byte = RTCSC.byte | 0x80; /* R[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 291 Get the latest version from freescale.com Chapter 15 Serial Comm unications Interface (S08SCIV4) 15.1 Intr oduction Figure 15-1 shows the MCF51QE128 Series block diagram with the SCI highlighted. NO TE Ignore any references to stop1 low-power mode in th is chapter , becaus[...]

Chapter 15 Serial Communications In terface (S08SCIV4) MCF51QE128 MCU Series Reference Manual, Rev . 3 292 F reescale Semico nductor Get the latest version from freescale.com Figure 15-1. M CF51QE128 Series Bloc k Diagram Highlighting SCI Block and Pins TPM2CH2-0 TPM1CH2-0 ANALOG COMP ARA T OR (ACMP1) ACM P 1 O ACM P 1 - ACM P 1 + V SS V DD IIC MOD[...]

Chapter 15 Serial Communications Interface (S08SCIV4) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 293 Get the latest version from freescale.com Figure 15-2. SCI Module Qu ick St art SBR12 SBR11 SBR10 SBR9 SBR8 SBR4 SBR3 SBR2 SBR1 SBR0 SBR7 SBR6 SBR5 SCIxBDL SCIxBDH Baud rate = BUSCLK / (16 x SBR12:SBR0) M W AKE IL T PE [...]

Chapter 15 Serial Communications In terface (S08SCIV4) MCF51QE128 MCU Series Reference Manual, Rev . 3 294 F reescale Semico nductor Get the latest version from freescale.com[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 295 Get the latest version from freescale.com 15.1.3 Features Features of SCI module include: • Full-duplex, standard non-re turn-to-zero (NRZ) format • Double-buffered transmitter and re ceiver with separate enables • Programmable baud rates (13-bit modulo divider) • [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 296 F reescale Semico nductor Get the latest version from freescale.com 15.1.5 Block Diagram Figure 15-3 shows the transmitter portion of the SCI. Figure 15-3. SCI T ransmit ter Block Dia gram H 8765432 10L SCID – Tx Buffer (Write-Only) Internal Bus Stop 11-BIT T ransmit Shift Register Start SHIFT D[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 297 Get the latest version from freescale.com Figure 15-4 shows the receiver portion of the SCI. Figure 15-4. SCI Receiver Bloc k Diagram H 87654 3210L SCID – Rx Buffer (Read-only) Internal Bus Stop 11-Bit Receive Shift Register Start Shift Direction lsb F rom RxD Pin Rate C[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 298 F reescale Semico nductor Get the latest version from freescale.com 15.2 Register Definition The SCI has eight 8-bit registers to control baud ra te, select SCI options, report SCI status, and for transmit/receive data. Refer to the direct-page register summary in the memory chapter of this docume[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 299 Get the latest version from freescale.com 15.2.2 SCI Control Register 1 (SCIxC1) This read/write register controls vari ous optional features of the SCI system. T able 15-2. SCIxBDL Field Descriptions Field Description 7–0 SBR[7:0] Baud Rate Modulo Divisor . These 13 bit[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 300 F reescale Semico nductor Get the latest version from freescale.com 15.2.3 SCI Control Register 2 (SCIxC2) This register can be read or written at any time. 1 PE P arity Enable. Enab les hardware parity gene ration and checking. When parity is enabled, the most significa nt bit (msb) of the data c[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 301 Get the latest version from freescale.com 15.2.4 SCI Status Register 1 (SCIxS1) This register has eight read-only st atus flags. W rites have no ef fect. Special software sequences (which do not involve writing to this regi ster) clear these status flags. 2 RE Receiver Ena[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 302 F reescale Semico nductor Get the latest version from freescale.com 5 RDRF Receive Data Register Full Flag. RDRF becomes set when a character transfers from the receiv e shifter into the receive data register (SCIxD). T o clear RDRF , read SC IxS1 with RDRF set and then read the SCI data register [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 303 Get the latest version from freescale.com 15.2.5 SCI Status Register 2 (SCIxS2) This register contains one read-only status flag. When using an internal oscillator in a LIN system, it is n ecessary to raise the break detection threshold one bit time. Under the worst case t[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 304 F reescale Semico nductor Get the latest version from freescale.com framing errors are inhibited and the break detection threshold changes fr om 10 bits to 1 1 bits, preventing false detection of a 0x00 data ch aracter as a LIN break symbol. 15.2.6 SCI Control Register 3 (SCIxC3) 76543210 RR 8 T8 [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 305 Get the latest version from freescale.com 15.2.7 SCI Data Register (SCIxD) This register is actually two separate registers. R eads return the co ntents of the read-only receive data buffer and writes go to the write-only transmit data buf fer . Reads and wr ites of this r[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 306 F reescale Semico nductor Get the latest version from freescale.com 15.3.2 T ransmitter Functional Description This section describes the overall block diagram for th e SCI transmitter , as well as specialized functions for sending break and idle characters. The transmitter block diagram is shown [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 307 Get the latest version from freescale.com 15.3.3 Receiver Functional Description In this section, the r eceiver block diagram ( Figure 15-4 ) is a guide for the overa ll receiver functional description. Next, the data sa mpling technique used to r econstruct receiver data [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 308 F reescale Semico nductor Get the latest version from freescale.com level for that bit, the noise flag (NF) is set when th e received character is tran sferred to the receive data buffer . The falling edge detection logic continuously looks for falling edges. If an edge is detected, the sample clo[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 309 Get the latest version from freescale.com 15.3.3.2.2 Address-Mark W akeup When wake is set, the receiver is configured for address-mark wakeup. In this mode, R WU is cleared automatically when the receiver detect s a logic 1 in the most significant bi t of a received chara[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 310 F reescale Semico nductor Get the latest version from freescale.com If RDRF was already set when a new character is rea dy to be transferred from the receive shifter to the receive data buffer , the overrun (OR) flag is set instead of the data along with any associated NF , FE, or PF condition is [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 311 Get the latest version from freescale.com internally connected to the receiver input and the RxD pin is not used by the SCI, so it reverts to a general-purpose port I/O pin. 15.3.5.4 Sin gle-Wire Operation When LOOPS i s set, the RSRC bit in the same register chooses betwe[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 312 F reescale Semico nductor Get the latest version from freescale.com[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 313 Get the latest version from freescale.com Chapter 16 Serial P eripheral Interface (S08SPIV3) 16.1 Intr oduction Figure 16-1 shows the MCF51QE128 Series block diagram with the SPI highlighted. NO TE Ignore any references to stop1 low-power mode in th is chapter , because th[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 314 F reescale Semico nductor Get the latest version from freescale.com Chapter 16 Serial Peripheral Interface (S08SPIV3) Figure 16-1. MCF51QE12 8 Block Dia gra m Highlighting SPI Block and Pins TPM2CH2-0 TPM1CH2-0 ANALOG COMP ARA T OR (ACMP1) ACM P 1 O ACM P 1 - ACM P 1 + V SS V DD IIC MODULE (IIC1) [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 315 Get the latest version from freescale.com Chapter 16 Serial Peripheral Interface (S08SPIV3)[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 316 F reescale Semico nductor Get the latest version from freescale.com Chapter 16 Serial Peripheral Interface (S08SPIV3)[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 317 Get the latest version from freescale.com 16.1.3 Features Features of the SPI module include: • Master or slave mode operation • Full-duplex or single-w ire bidirectional option • Programmable transmit bit rate • Double-buffered transmit and receive • Serial cloc[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 318 F reescale Semico nductor Get the latest version from freescale.com Figure 16-2 shows a system where data is exchanged between two MCUs, many practical systems involve simpler connections where data is unidirectionally transfer red from the master MCU to a slave or from a slave to the master MCU. [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 319 Get the latest version from freescale.com Figure 16-3. SPI Module Bloc k Diagram 16.1.5 SPI Baud Rate Generation As shown in Figure 16-4 , the clock source for the SPI baud rate generator is the bus clock. The three prescale bits (SPIxBR[SPPR]) choose a prescale divisor of[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 320 F reescale Semico nductor Get the latest version from freescale.com Figure 16-4. SPI Baud Rate Generation 16.2 External Signal Description The SPI optionally shares four port pi ns. The function of these pins depe nds on the settings of SPI control bits. When the SPI is disabled (SPIxC1[SPE] is cl[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 321 Get the latest version from freescale.com output enable bit determines whether this pin acts as the mode fault input (SPIxC1[SSOE] = 0) or as the slave select output (SSOE = 1). 16.3 Modes of Operation 16.3.1 SPI in Stop Modes The SPI is disabled in all stop mode s, regard[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 322 F reescale Semico nductor Get the latest version from freescale.com NO TE Ensure that the SPI should not be disabled (SPE = 0) at the same time as a bit change to SPIxC1[CPHA]. Thes e changes should be performed as separate operations or unexpected behavior may occur . 16.4.2 SPI Contr ol Register[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 323 Get the latest version from freescale.com 16.4.3 SPI Baud Rate Register (SPIxBR) This register sets the prescaler and bit rate divisor for an SPI master . Th is register may be read or written at any time. 76543210 R 000 MODFEN BIDIROE 0 SPISW AI SPC0 W R e s e t 00000000 [...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 324 F reescale Semico nductor Get the latest version from freescale.com 16.4.4 SPI Status Register (SPIxS) This register has three read -only status bits. Bits 6, 3, 2, 1, and 0 are not reserved and always read 0. W rites have no meaning or effect. T able 16-4. SPIx BR Register Fi eld Descriptio ns Fi[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 325 Get the latest version from freescale.com 16.4.5 SPI Data Register (SPIxD) Reads of this register returns the da ta read from the receive data buffer . W rites to this register write data to the transmit data buf fer . When th e SPI is configured as a master , wri tin g da[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 326 F reescale Semico nductor Get the latest version from freescale.com indicate there is room in the buf fer to queue another tr ansmit character if desired, a nd the SPI serial transfer starts. During the SPI transfer , data is sampled (read) on th e MISO pin at one SPSCK e dge and shifted, changing[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 327 Get the latest version from freescale.com Figure 16-10. SPI Cloc k Formats (CPHA = 1) When CPHA is set, the slave begins to drive its MISO output when SS asserts, but the da ta is not defined until the first SPSCK edge. The first SPSC K edge shifts the firs t bit of data f[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 328 F reescale Semico nductor Get the latest version from freescale.com Figure 16-11. SPI Cloc k Formats (CPHA = 0) When CPHA is cleared, the slave begins to drive its MI SO output with the first data bit value (msb or lsb depending on LSBFE) when SS asserts. The first SPSCK edge causes the master and[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 329 Get the latest version from freescale.com 16.5.3 Mode Fault Detection A mode fault occurs and the mode fault flag (MODF) sets when a master SPI device detects an error on the SS pin (provided the SS pin is configured as the m ode fault input signal). The SS pin is configur[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 330 F reescale Semico nductor Get the latest version from freescale.com[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 331 Get the latest version from freescale.com Chapter 17 Timer/Pulse-Width Modulator (S08TPMV3) 17.1 Intr oduction Figure 17-1 shows the MCF51QE128 Series block diagram w ith the TPM highlighted. 17.1.1 A CMP/TPM Configuration Info rmation The ACMP modules can be configured to[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 332 F reescale Semico nductor Get the latest version from freescale.com Chapter 17 Timer/Pulse-Width Modulator (S08TPMV3) Figure 17-1. M CF51QE128 Series Bloc k Diagram Highlighting TPM Block and Pins TPM2CH2-0 TPM1CH2-0 ANALOG COMP ARA T OR (ACMP1) ACM P 1 O ACM P 1 - ACM P 1 + V SS V DD IIC MODULE ([...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 333 Get the latest version from freescale.com Chapter 17 Timer/Pulse-Width Modulator (S08T PMV3)[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 334 F reescale Semico nductor Get the latest version from freescale.com Chapter 17 Timer/Pulse-Width Modulator (S08TPMV3)[...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 335 Get the latest version from freescale.com 17.1.4 Features The TPM includes these distinctive features: • One to eight channels: — Each channel may be input capture, output compare, or edge-aligned PWM — Rising-Edge, falling-edge, or any-ed[...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 336 F reescale Semico nductor Get the latest version from freescale.com • Edge-aligned PWM mode The value of a 16-bit modulo regist er plus 1 sets the period of the PWM output signal. The channel value register sets the duty cycle of the PWM out put signal. Y ou may also [...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 337 Get the latest version from freescale.com Figure 1 7-2. TPM Block Diagram Prescale and Select 16-Bit Comparato r PS[2:0] TOF TO I E Interru pt 16-Bit Counter Logic 16-Bit Comparator 16-Bit Latch ELS0B ELS0A Po r t Channel 0 CH0IE CH0F Logic CPWM[...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 338 F reescale Semico nductor Get the latest version from freescale.com The TPM channels are programmable independently as input capture, output co mpare, or edge-aligned PWM channels. Alternately , the TPM can be configur ed to produce CPWM outputs on all channels. When th[...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 339 Get the latest version from freescale.com 17.2.1.1 EXTCLK — External Clock Sour ce Control bits in the timer status a nd control register allow you to select nothing (time r disable), the bus-rate clock (the normal defau lt source), a crystal-[...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 340 F reescale Semico nductor Get the latest version from freescale.com pin is forced low at the start of each new period (TPMxCNT=0x0000), and the pin is forced high when the channel value register matches the timer counter. Figure 17-3. Hig h-T rue Pulse of an Edge-Aligne[...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 341 Get the latest version from freescale.com Figure 17-6. Lo w-T rue Pulse of a Center -Aligned PWM 17.3 Register Definition This section consists of register descriptions in address order. 17.3.1 TPM Status and Contr ol Register (TPMxSC) TPMxSC co[...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 342 F reescale Semico nductor Get the latest version from freescale.com 17.3.2 TPM Counter Regist er s (TPMxCNTH:TPMxCNTL) The two read-only TPM counter regist ers contain the high and low bytes of the value in the TPM counter. Reading either byte (TPMxCNTH or TPMxCNTL) lat[...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 343 Get the latest version from freescale.com little-endian order that makes this more friendly to various co mpiler implementations. The coherency mechanism is automatically restarted by an MCU reset or any write to the time r status/control regist[...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 344 F reescale Semico nductor Get the latest version from freescale.com The latching mechanism may be manually reset by writing to the TP MxSC address (w hether BDM is active or not). When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxSC) [...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 345 Get the latest version from freescale.com T able 17- 5. TPMxC nSC Field Descriptions Field Description 7 CHnF Channel n flag. When ch annel n is an input-capture channel, this read/write bi t is set when an active edge occurs on the channel n pi[...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 346 F reescale Semico nductor Get the latest version from freescale.com 17.3.5 TPM Channel V alue Registers (TPMxCnVH:TPMxCnVL) These read/write register s contain the captured TPM counter value of the input capture function or the output compare value for the output compar[...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 347 Get the latest version from freescale.com • If CLKSB and CLKSA are not cleared and in EPWM or CPWM modes, the registers are updated after the both bytes were written, and the TPM counter changes from TPMxMODH:TPMxMODL − 1 to TPMxMODH:TPMxMOD[...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 348 F reescale Semico nductor Get the latest version from freescale.com The bus rate clock is the main system bus cl ock for the MCU. This clock source requires no synchronization because it is the clock used for all internal MCU act ivities inclu ding operation of the CPU [...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 349 Get the latest version from freescale.com 17.4.1.3 Cou nting Modes The main timer counter has two counting modes. Wh en center -aligned PWM is selected (CPWMS = 1), the counter operates in up/down counting mode. Otherwise, the counter operates a[...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 350 F reescale Semico nductor Get the latest version from freescale.com In output compare mode, values are transferred to th e corresponding timer channel re gisters only after both 8-bit halves of a 16-bit register ha ve been written and according to the value of CLKSB:CLK[...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 351 Get the latest version from freescale.com • If CLKSB and CLKSA are not cleared, the registers are updated after both bytes are written, and the TPM counter changes from TPMxMODH:TPMxMODL − 1 to TPMxMODH:TPMxMODL. If the TPM counter is a free[...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 352 F reescale Semico nductor Get the latest version from freescale.com Input capture, output compare, a nd edge-aligned PWM functions do not make sense when the counter is operating in up/down counting mode so th is implies that all act ive channels within a TPM must be us[...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 353 Get the latest version from freescale.com All TPM interrupts are lis ted in T able 17-8 , showing the interrupt name, the name of any local enable that can block the interrupt request from leaving the TPM and getting reco gnized by the separate [...]

Timer/PWM Module (S08TPMV3) MCF51QE128 MCU Series Reference Manual, Rev . 3 354 F reescale Semico nductor Get the latest version from freescale.com 17.6.2.1.2 Center-Aligned PWM Case When CPWMS is set, TOF is set when the time r counter changes direct ion from up-counting to down-counting at the end of the terminal count (the value in the modul o r[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 355 Get the latest version from freescale.com Chapter 18 V er sion 1 ColdFire Deb ug (CF1_DEBUG) 18.1 Intr oduction This chapter describes the capabilit ies defined by the V ersion 1 ColdFire debug architecture. The V ersion 1 ColdFire core supports BDM functionality using the[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 356 F reescale Semico nductor Get the latest version from freescale.com Figure 18-1. Simplified V ersion 1 ColdFire Core Bloc k Diagram 18.1.1 Overview Debug support is divided into three areas: • Background debug mode (BDM)—Provides low-level debug[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 357 Get the latest version from freescale.com concurrent operation of the pr ocessor and BDM-initiated memo ry commands. In addition, the option is provided to allow interrupts to occur . See Section 18.4.2, “Real-T ime Debug [...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 358 F reescale Semico nductor Get the latest version from freescale.com When operating in secure mode, as defined by a 2-bit field in the flash memory examined at reset, BDM access to debug resources is extremely restricted. It is possible to tell that [...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 359 Get the latest version from freescale.com Figure 18-2. Deb ug Modes State T ransition Diagram Figure 18-2 contains a simplified view of the V1 Co ldFire debug mode states. The XCSR[CLKSW] bit controls the BDC clock source. W[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 360 F reescale Semico nductor Get the latest version from freescale.com 18.3 Memory Map/Register Definition In addition to the BDM commands that provide acc ess to the processor ’ s registers and the memory subsystem, the debug module contains a numbe[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 361 Get the latest version from freescale.com NO TE Debug control registers can be written by the external development system or the CPU through the WDEBUG instru ction. These control registers are write-only from the programmin[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 362 F reescale Semico nductor Get the latest version from freescale.com DRc[4:0]: 0x00 (CSR) Access: Super visor write-only BDM read/write 31 30 29 28 27 2 6 25 24 23 22 21 20 19 18 17 16 R BST A T FOF TRG HAL T BKPT HRL 0 BKD 0 IPW W R e s e t 00000 00[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 363 Get the latest version from freescale.com 18 BKD Breakpoint disable. Disables the normal BKPT input signal an d BA CKGROUND command functionality , and allows the asser tion of this pin (or ex ecution of the BACKGR OUND comm[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 364 F reescale Semico nductor Get the latest version from freescale.com 18.3.2 Extended Configuratio n/Status Register (XCSR) The 32-bit XCSR is partitioned into two sections: the upper byte contains status and comm and bits always accessible to the BDM[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 365 Get the latest version from freescale.com DRc: 0x01 (XCSR) Access: Super visor write-only BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R CPU HAL T CPU ST OP CST A T CLKSW SEC ENBDM 0000 0000 W ESEQC ERASE R[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 366 F reescale Semico nductor Get the latest version from freescale.com 29–27 CST A T (R) ESEQC (W) During reads, indicates the BDM command status. 000 Command do ne, no errors 001 Command do ne, data inv alid 01 x Command done, illegal 1 xx Command b[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 367 Get the latest version from freescale.com 18.3.3 Configuration/Status Register 2 (CSR2) The 32-bit CSR2 is partitioned into two sections. Th e upper byte contains status and configuration bits always accessible to the BD M i[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 368 F reescale Semico nductor Get the latest version from freescale.com WRITE_DREG Writes CSR2[31 – 0] from the BDM i nterf ace. Classified as a non-intr usive BDM command. WDEBUG Instruction Writes CSR2[23 – 0] d uring the core ’ s ex ecution of [...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 369 Get the latest version from freescale.com 22–21 PSTBST PST trace b uffer state . Indicates the curren t state of the PST trace b uff er recording. 00 PSTB disab led 01 PSTB enabled and w aiting for the star t condition 10 [...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 370 F reescale Semico nductor Get the latest version from freescale.com 18.3.4 Configuration/Status Register 3 (CSR3) CSR3 contains the BDM flash cloc k divider (BFCDIV) value in a fo rmat similar to HCS08 devices. There are multiple ways to referenc e [...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 371 Get the latest version from freescale.com 18.3.5 BDM Address Attrib ute Register (B AAR) BAAR defines the address space for memory-ref erencing BDM commands. BAAR[R, SZ] are loaded directly from the BDM command, while the lo[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 372 F reescale Semico nductor Get the latest version from freescale.com 18.3.6 Address Attribute T rigger Register (AA TR) AA TR defines address attributes and a mask to be matched in the trigger . The register value is compared with address attribute s[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 373 Get the latest version from freescale.com 18.3.7 T rigger Definition Register (TDR) TDR configures the operation of the hardware breakpoint logic that corresponds with the ABHR/ABLR/AA TR, PBR/PBR1/PBR2/PBR3/PBMR, and DBR/DB[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 374 F reescale Semico nductor Get the latest version from freescale.com DRc: 0x07 (TDR) Access: Super visor write-only BDM write -only Second Lev el T rigger 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R W TRC L2EBL L2ED L2DI L2EA L2EPC L2PCI R e s [...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 375 Get the latest version from freescale.com 20–18 L2EA Enable le vel 2 address breakpoint. Setting an L2 EA bit enables the corresponding address breakpo int. Cleari ng all three bits disables the breakpoint. 17 L2EPC Enable[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 376 F reescale Semico nductor Get the latest version from freescale.com 18.3.8 Pr ogram Counter Breakpoint /Mask Registers (PBR0–3, PBMR) The PBR n registers define instruction addres ses for use as part of the trigge r . These registers’ contents a[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 377 Get the latest version from freescale.com Figure 18-12 shows PBMR. PBMR is accessible in supervis or mode using the WDEBUG instruction and via the BDM port using the WRITE_DR EG command. PBMR only masks PBR0. DRc: 0x08 (PBR0[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 378 F reescale Semico nductor Get the latest version from freescale.com 18.3.9 Address Breakpoint Registers (ABLR, ABHR) The ABLR and ABHR define regions in the processor ’ s da ta address space that can be used as part of the trigger . These register[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 379 Get the latest version from freescale.com 18.3.10 Data Breakpoint and Mask Registers (DBR, DBMR) DBR specifies data patterns used as part of the tr igger into debug mode. DBR bits are masked by setting corresponding DBMR bit[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 380 F reescale Semico nductor Get the latest version from freescale.com 18.3.11 Resulting Set of P oss ible T rig ger Combinations The resulting set of possible breakpoint trigger combinations consists of the following options where || denotes logical O[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 381 Get the latest version from freescale.com The BDC provides a singl e-wire debug interface to th e tar get MCU. As shown in the V ersion 1 ColdFire core block diagram of Figure 18-1 , the BDC module interfaces betwee n the si[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 382 F reescale Semico nductor Get the latest version from freescale.com Hardware breakpoint trigger Pe n d i n g Halt is made pending in the processor . The processor samples for pending halt and interr upt conditions once per instruction . When a pendi[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 383 Get the latest version from freescale.com The processor ’ s run/stop/ha lt status is always accessible in XCSR[CPUHAL T ,CPUSTOP]. Additionally , CSR[27–24] indicate the halt source, s howing the highest priority source [...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 384 F reescale Semico nductor Get the latest version from freescale.com When a development system is c onnected, it can pull BKGD and RESET low , release RESET to select active background (halt) mode rather than normal op erating mode, and then re lease[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 385 Get the latest version from freescale.com where the target perceives the beginning of the bit time. T en tar g et BDC cloc k cycles later , the target senses the bit level on the BKGD pin. T ypically , the host ac tively dri[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 386 F reescale Semico nductor Get the latest version from freescale.com Figure 18-16. BDC T arget-t o-Host Serial Bit Timing (Logic 1) Figure 18-17 shows the host receiving a logic 0 from the tar get MCU. Because the host is asynchronous to the target M[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 387 Get the latest version from freescale.com Figure 18-17. BDM T arget-to-Hos t Serial Bit Timing (Logic 0) 18.4.1.4 BDM Command Set Descriptions This section presents detaile d de scriptions of the BDM commands. The V1 BDM com[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 388 F reescale Semico nductor Get the latest version from freescale.com Miscellaneous Commands 76543210 W 0 0 R/W 0 MSCMD R/W Optional Command Extension Byte (Data) Memory Commands 76543210 W 0 0 R/W 1 SZ MCMD W if addr , R/W if data Command Extensio n [...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 389 Get the latest version from freescale.com T able 18-24. BDM Command Code Field Description s Field Description 5 R/W Read/Wri te . 0 Command is performing a write o peration. 1 Command is performing a rea d operation. 3–0 [...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 390 F reescale Semico nductor Get the latest version from freescale.com 18.4.1.5 BDM Command Set Summary T able 18-25 summarizes the BDM command set. Subsequent paragraphs contain detailed descriptions of each command. The nomenclature below is used in [...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 391 Get the latest version from freescale.com DUMP_MEM.sz_WS Non-Intrusive No (0 x33+4 x sz)/d/ss/rd.sz Dump (read) memor y based on operand size (sz) and report status. Used with READ_MEM{_WS} to dump large bloc ks of memor y .[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 392 F reescale Semico nductor Get the latest version from freescale.com 18.4.1.5.1 SYNC The SYNC command is unlike other BDC commands because the host does not necessarily know the correct speed to use for serial co mmunications until after it has analy[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 393 Get the latest version from freescale.com 2. Delays 16 cycles to allow the host to stop driving the high speed-up pulse. 3. Drives BKGD low for 128 BDC clock cycles. 4. Drives a 1-cycle high speed-up pulse to force a fast ri[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 394 F reescale Semico nductor Get the latest version from freescale.com 18.4.1.5.4 B A CKGROUND Provided XCSR[ENBDM] is set (BDM enabled), the BACKGROUND command causes the tar get MCU to enter active background (halt) mode as soon as the current CPU in[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 395 Get the latest version from freescale.com DUMP_MEM{_WS} is used with the READ_MEM{_WS} command to access lar ge blocks of memory . An initial READ_MEM{_WS} is executed to set-up the starting address of the block and to retri[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 396 F reescale Semico nductor Get the latest version from freescale.com FILL_MEM{_WS} is used with the WRITE_MEM{_WS} command to access large blocks of memory . An initial WRITE_MEM{_WS} is executed to set up th e starting address of the block and write[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 397 Get the latest version from freescale.com NO TE FILL_MEM_{WS} does not check for a valid address; it is a valid command only when preceded by NOP , WRITE_MEM_{WS}, or another FILL_MEM{_WS} command. Otherwise, an illegal comm[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 398 F reescale Semico nductor Get the latest version from freescale.com If the processor is halted, this co mmand reads the selected control regi ster and returns the 32-bit result. This register grouping includes the PC, SR, CPU CR, VBR, and OTHER_A7. [...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 399 Get the latest version from freescale.com Read data at the specified memory address. The refere nce address is tra nsmitted as three 8-bit packets (msb to lsb) immediately after the co mmand packet. The access attribute s ar[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 400 F reescale Semico nductor Get the latest version from freescale.com 18.4.1.5.13 READ_Rn If the processor is halted, this command reads the selected CPU ge neral-purpose register (An, Dn) and returns the 32-bit result. See T able 18-24 for the CRN de[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 401 Get the latest version from freescale.com 18.4.1.5.17 SYNC_PC Capture the processor ’ s current PC (program counter) and display it on the PST/DDA T A signals. After the debug module receives the command, it se nds a signa[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 402 F reescale Semico nductor Get the latest version from freescale.com 18.4.1.5.19 WRITE_DREG This command writes the 32-bit oper and to the selected de bug control register . This grouping includes all the debug control registers ({X}CSR n , BAAR, AA [...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 403 Get the latest version from freescale.com W rite data at the specified memory address. The reference address is transmitted as three 8-bit packets (msb to lsb) immediatel y after the command packet. The access a ttributes ar[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 404 F reescale Semico nductor Get the latest version from freescale.com 18.4.1.5.22 WRITE_XCSR_BYTE W rite the special status byte of XCSR (XCSR[31–24]). This command can be executed in any mode. 18.4.1.5.23 WRITE_CSR2_BYTE W rite the most significant[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 405 Get the latest version from freescale.com clock cycles after the BDC command was issued. The e nd of the BDC command is assumed to be the 16th BDC clock cycle of the last bit. This minimum delay assures enough time for the h[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 406 F reescale Semico nductor Get the latest version from freescale.com indicating that the addresse d byte is ready to be retr ieved. After detecting the AC K pulse, the host initiates the data-read portion of the command. Figure 18-20. Handshake Pr ot[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 407 Get the latest version from freescale.com any of the stop modes. If the host aborts a comm and by sending the sync pulse, it should then read XCSR[CST A T] after the sync response is issued by the target, checking for CST A [...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 408 F reescale Semico nductor Get the latest version from freescale.com Figure 18-21. A CK Abort Procedure at the Command Level Figure 18-22 a shows a conflict between the ACK pulse and the sync request pulse. This conflict could occur if a pod device i[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 409 Get the latest version from freescale.com • ACK_DISABLE — Disables the ACK pulse protocol. In this case, the host should verify the state of XCSR[CST A T] in order to evaluate if there are pending commands and to check i[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 410 F reescale Semico nductor Get the latest version from freescale.com For the V1 ColdFire core and its single debug signa l, support for trace functionality is completely redefined. The V1 solution provides an on-chip PST/DD A T A trace buffer (kn own[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 411 Get the latest version from freescale.com 18.4.3.1 Beg in Execution of T aken B ranch (PST = 0x05) PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may be loaded into the trace bufer (PST[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 412 F reescale Semico nductor Get the latest version from freescale.com loaded, which is indicated by the PST marker valu e immediately preceding the DDA T A entry in the PSTB that begins the address entries. Multiple byte DDA T A values are displayed i[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 413 Get the latest version from freescale.com 18.4.3.2 PST T race Buffer (PSTB) As PST and DDA T A values are captured and loaded in the trace buffer , each entry is 6 bits in size so the type of the entry can easily be determ i[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 414 F reescale Semico nductor Get the latest version from freescale.com # pst = 1c, 1c, 05, 0d # ddata = 2a, 23, 28, 20 # trg_addr = 083a << 1 # trg_addr = 1074 _isr: 01074: 46fc 2700 mov.w &0x2 700,%sr # pst = 01 01078: 2f08 mov.l %a0, -(%sp)[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 415 Get the latest version from freescale.com where the {...} definition is optional operand info rmation defined by the setting of the CSR. The CSR provides capabilities to di splay operands based on reference t ype (read, writ[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 416 F reescale Semico nductor Get the latest version from freescale.com btst.{b ,l} Dy ,<ea>x PST = 0x01, {PST = 0x08, DD = source operand} bytere v .l Dx PST = 0x01 clr .b < ea>x PST = 0x01, {PST = 0x08, DD = destination operand} clr .l <[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 417 Get the latest version from freescale.com mov ea.w <ea>y ,Ax PST = 0x01, {PST = 0x09, DD = source} mov em.l #list,<ea>x PST = 0x01, {PST = 0x0B , DD = destination},... mov em.l <ea>y ,#list PST = 0x01, {PST[...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 418 F reescale Semico nductor Get the latest version from freescale.com 18.4.3.4.2 Supervisor Instruction Set The supervisor instruction set has complete access to the user mode instructions plus the opcodes shown below . The PST/DDA T A specificati on [...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 419 Get the latest version from freescale.com The move-to-SR, STLDSR, and R TE in structions include an optional PST = 0x3 value, indicating an entry into user mode. Similar to the exception proce ssing mode, the stopped state ([...]

Chapter 18 V ersion 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev . 3 420 F reescale Semico nductor Get the latest version from freescale.com[...]

MCF51QE128 MCU Series Reference Manual, Rev . 3 F reescale Semiconductor 421 Appendix A Re vision Histor y This appendix describes corrections to the MCF51QE128 Refer ence Manual . For convenience, the corrections are grouped by revision. A.1 Changes between Rev . 2 and Rev . 3 T able 29. M CF51QE128RM Re v . 2 to Re v . 3 Changes Chapter Descripti[...]

Revision History MCF51QE128 MCU Series Reference Manual, Rev . 3 422 F reescale Semico nductor[...]

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MCF51QE128RM Rev. 3, 09/2007 Get the latest version from freescale.com How t o Reach Us: Home P age: www .freescale.com E-mail: suppor t@freescale.com USA/Eur ope or Locatio ns Not Listed: F reescale Semiconductor T echnical Inf or mation Center , CH370 1300 N. Alma School Road Chandler , Ar izona 85224 +1-800-521-6274 or +1-480-768-2130 suppor t@f[...]