Fujitsu MPA3043AT инструкция обслуживания

C141-E034-02EN MPA3017AT MPA3026AT MPA3035AT MPA3043AT MPA3052AT DISK DRIVES PRODUCT MANUAL[...]

C141-E034-02EN i REVISION RECORD Edition Date published Revised contents 01 Jan., 1997 02 August, 1997 Specification No.: C141-E034-**EN The content s of t his manual is s ubject to c hange without prior notice. All Rights Reserved. Copyright  1997 FUJITSU LIMITED[...]

C141-E034-02EN iii PREFACE This m anu al descri bes the MPA 3017AT/MPA3026A T/MPA3035A T/MPA3043A T/MPA3052A T, a 3.5-inch hard disk drive with a BUILT-IN controller that is compatible with the ATA interface. This manual explains, in detail, how to incorporate the hard disk drives into user systems. This man ual assum es that users have a basic k n[...]

iv C141-E034-02EN Conventions for Alert Messages This manual uses the following conventions to show the alert m essages. An alert message consists of an alert sign al and alert statements. The alert sign al consists of an alert sy mbol an d a signal w ord or just a signal word. The following are the alert signals and their meanings: This indicates [...]

C141-E034-02EN v LIABILITY EXCEPTION "Disk drive defects" refers to defects that involve adjustment, repair, or replacement. Fujit su is n ot liable for an y oth er disk dri ve defects, s uch as t hose cause d by us er mis operation or mi shandli ng, inappropriate operating environ men ts, def ects in t he pow er supply or cable, problem [...]

C141-E034-02EN vii CONTENTS page CHAPTER 1 DEVICE OVERVIEW ......................................................................................... 1 - 1 1.1 Features................................................................................................................................. 1 - 1 1.1.1 Functions and performance ...............[...]

C141-E034-02EN viii 3.4.1 Location of setting jumpers ............................................................................................... ... 3 - 9 3.4.2 Factory default setting ................................................................................................... ....... 3 - 10 3.4.3 Jumper configuration ..................[...]

C141-E034-02EN ix 5.2.2 Command block registers ................................................................................................... .. 5 - 8 5.2.3 Control block registers ................................................................................................... ....... 5 - 13 5.3 Host Commands...............................[...]

C141-E034-02EN x 6.3.1 Power save mode ........................................................................................................... ....... 6 - 8 6.3.2 Power commands ............................................................................................................ ...... 6 - 10 6.4 Defect Management .......................[...]

C141-E034-02EN xi FIGURES page 1.1 Current fluctuation (Typ.) at +5V when power is turned on ................................................. 1 - 7 2.1 Disk drive outerview ........................................................................................................ ..... 2 - 1 2.2 Configuration of disk media heads .....................[...]

C141-E034-02EN xii 5.4 Protocol for command abort ................................................................................................. 5 - 57 5.5 WRITE SECTOR(S) command protocol.............................................................................. 5 - 58 5.6 Protocol for the command execution without data transfer.............[...]

C141-E034-02EN xiii TABLES page 1.1 Specifications.............................................................................................................. .......... 1 - 4 1.2 Model names and product numbers ...................................................................................... 1 - 5 1.3 Current and power dissipation .........[...]

C141-E034-02EN 1 - 1 CHAPTER 1 DEVICE OVER VIEW 1.1 Features 1.2 Device Specifications 1.3 Power Requirements 1.4 Environmental Specifications 1.5 Acoustic Noise 1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate 1.9 Media Defects Overview and f eatures are described in this chapter, and specifications and power requiremen t are described. The [...]

C141-E034-02EN 1 - 2 (4) Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed. The average positioning time is 10 ms (at read). 1.1.2 Adaptability (1) Power save mode The pow er sav e m ode feat ure for idle operati on, stand by and s leep modes make s the disk drive ide[...]

C141-E034-02EN 1 - 3 (5) Error correction and retry by ECC If a recoverable error occu rs, the disk drive itself attem pts error recovery . The 18-byte ECC has improved buffer error correction for correctable data errors. (6) Write cache When th e disk driv e receives a write comm and, the disk drive posts th e comm and completion at completion of [...]

C141-E034-02EN 1 - 4 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specifications of the disk drive. Table 1.1 Specifications MPA3017AT MPA3026AT MPA3035AT MPA3043AT MPA3052AT Formatted Capacity (*1) 1750.00 MB 2625.00 MB 3500.00 MB 4375.00 MB 5250.01 MB Number of Heads 23456 Number of Cylinders (User + Alternate & [...]

C141-E034-02EN 1 - 5 1.2.2 Model and product number Table 1.2 lists the model names and product numbers. Table 1.2 Model names and product numbers Model Name Capacity (user area) Mounting Screw Order No. Others MPA3017AT 1749.56 MB No. 6-32UNC CA01602-B321 MPA3026AT 2624.86 MB No. 6-32UNC CA01602-B331 MPA3035AT 3499.13 MB No. 6-32UNC CA01602-B341 M[...]

C141-E034-02EN 1 - 6 (3) Current Requirements and Power Dissipation Table 1.3 lists the current and power dissipation. Table 1.3 Current and power dissipation Typical RMS current (*1) +12 V +5 V Model MPA 3017AT MPA 3026AT MPA 3035AT MPA 3043AT MPA 3052AT All Models MPA 3017AT MPA 3026AT MPA 3035AT MPA 3043AT MPA 3052AT Spin up 1.3 A 1.5 A peak 0.5[...]

C141-E034-02EN 1 - 7 (4) Current fluctuation (Typ.) at +5V when power is turned on Note: Maximum current is 1.5 A and is continuance is 1.5 seconds Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on (5) Power on/off sequence The voltage detector circuit m onitors +5 V and +12 V. The circuit doe s not allow a w rite signal if eithe[...]

C141-E034-02EN 1 - 8 1.4 Environmental Specifications Table 1.4 lists the environmental specifications. Table 1.4 Environmental specifications Temperature • Operating • Non-operating • Thermal Gradient 5°C to 55°C (ambient) 5°C to 60°C (disk enclosure surface) –40°C to 60°C 20°C/h or less Humidity • Operating • Non-operating • [...]

C141-E034-02EN 1 - 9 1.6 Shock and Vibration Table 1.6 lists the shock and vibration specification. Table 1.6 Shock and vibration specification Vibration (swept sine, one octave per minute) • Operating • Non-operating 5 to 300 Hz, 0.5G-0-peak (without non-recovered errors) 5 to 400 Hz, 4G-0-peak (no damage) Shock (half-sine pulse, 11 ms duratio[...]

C141-E034-02EN 1 - 10 (4) Data assurance in the event of power failure Except for the data blo ck b eing written to, the data on the disk media is assured in the event o f any power supply abnormalities. This does not includ e power supply abnormalities during disk m edia initialization (formatting) or processing of defects (alternative block assig[...]

C141-E034-02EN 2 - 1 CHAPTER 2 DEVICE CONFIGURA TION 2.1 Device Configuration 2.2 System Configuration 2.1 Device Configuration Figure 2.1 show s the disk drive. The disk drive con sists of a disk enclosu re (DE), read/write preamplif ier, and controller PCA. The disk enclosure contains the disk m edia, heads, spindle motors actuators, and a circul[...]

C141-E034-02EN 2 - 2 (1) Disk The outer diam eter of t he disk is 95 mm . The in ner diam eter is 25 m m. The nu mber of disks used varies w ith t he model , as described below . The disk s are rated at over 40,000 s tart/stop operations. MPA3017AT: 1 disk MPA3026AT: 2 disks MPA3035AT: 2 disks MPA3043AT: 3 disks MPA3052AT: 3 disks (2) Head The head[...]

C141-E034-02EN 2 - 3 Spindl e 0 1 Actu ator MPA3017 Model MPA3026AT Model Spindl e 1 2 0 Actu ator MPA3043AT Model Spindl e 2 3 4 0 1 Actu ator MPA3035AT Model Spindl e 1 3 2 0 Actu ator MPA3052AT Model Spindl e 2 3 5 4 0 1 Actu ator Figure 2.2 Configuration of disk media heads (3) Spindle motor The disks are rotated by a direct drive Hall-less DC [...]

C141-E034-02EN 2 - 4 (5) Air circulation system The disk enclosure (DE) is sealed to prevent du st and dirt from en tering. The disk enclosu re featu res a cl osed loop air circulation sy stem t hat relies on the blow er eff ect of th e rotating disk. This system continuously circulate s the air thr ough the cir culation filter to maintain the clea[...]

C141-E034-02EN 2 - 5 2.2.3 2 drives connection ATA interfac e AT bus (H ost inte rfac e) Disk d r i ve #1 Disk d r i ve #0 HA (H ost ad apto r) Hos t Note: When the drive that is not conformed to ATA is connected to the disk drive is ab ove configuration, the operation is not guaranteed. Figure 2.4 2 drives configuration IMPORTANT HA (host adapter)[...]

C141-E034-02EN 3 - 1 CHAPTER 3 INST ALLA TION CONDITIO NS 3.1 Dimensions 3.2 Mounting 3.3 Cable Connections 3.4 Jumper Settings 3.1 Dimensions Figure 3.1 illustrates the d imensions of the disk drive and positio ns of the mounting screw holes. All dimensions are in mm.[...]

C141-E034-02EN 3 - 2 Figure 3.1 Dimensions[...]

C141-E034-02EN 3 - 3 3.2 Mounting (1) Orientation Figure 3.2 illustrates the allowable orientations for the disk drive. T he mounting angle can vary ±5° from the horizontal. (a) Horizontal mounting (b) Vertical mounting –1 (c) Vertical mounting –2 Figure 3.2 Orientation (2) Frame The disk enclosu re (DE) body is connected t o signal g round ([...]

C141-E034-02EN 3 - 4 Figure 3.3 Limitation of side-mounting Figure 3.4 Mounting frame structure 5.0 or less 4.5 or less 2 B Frame of system cabinet Details of B Details of A Frame of system cabinet Screw Screw PCA DE 2.5 2.5 2.5 A DE Side surface mounting Bottom surface mounting Do not use this screw holes Use these screw holes[...]

C141-E034-02EN 3 - 5 (4) Ambient temperature The temperature conditio ns for a disk drive mounted in a cab inet ref er to the ambient temperature at a poin t 3 cm from the disk drive. Pay attention to the air f low to prevent the DE surf ace temperature from exceeding 60°C. Provide air circu lation in the cabinet su ch that the PCA side, in partic[...]

C141-E034-02EN 3 - 6 (5) Service area Figure 3.6 shows how the drive must be accessed (service areas) during and after installation. Figure 3.6 Service area (6) External magnetic fields Avoid m ounting the disk drive near strong magn etic sources such as loud speakers. Ensu re that the disk drive is not affected by external magnetic fields. [P side[...]

C141-E034-02EN 3 - 7 3.3 Cable Connections 3.3.1 Device connector The disk drive has the con nectors and termin als listed below f or connecting external devices. Figure 3.7 shows the locations of these connectors and terminals. • Power supply connector (CN1) • ATA interface connector (CN1) Figure 3.7 Connector locations ATA interface connector[...]

C141-E034-02EN 3 - 8 3.3.2 Cable connector specifications Table 3.2 lists the recommended specifications for the cable connectors. Table 3.2 Cable connector specifications Name Model Manufacturer Cable socket (closed-end type) FCN-707B040-AU/B Fujitsu Cable socket (through-end type) FCN-707B040-AU/O Fujitsu Signal cable 445-248-40 SPECTERS STRIP Ca[...]

C141-E034-02EN 3 - 9 3.3.4 Power supply connector (CN1) Figure 3.9 shows the pin assignment of the power supply connector (CN1). (View e d from cab le side) 4 3 2 1 +5VDC +5V R ETUR N +12V R ET UR N +12 VDC 4 3 2 1 Figure 3.9 Power supply connector pins (CN1) 3.4 Jumper Settings 3.4.1 Location of setting jumpers Figure 3.10 shows the location of th[...]

C141-E034-02EN 3 - 10 3.4.2 Factory default setting Figure 3.11 shows the default setting position at the factory. C04 A01 A02 C01 A39 A40 05 06 B01 B02 Figure 3.11 Factory default setting 3.4.3 Jumper configuration (1) Device type Master device (device #0) or slave device (device #1) is selected. 06 B02 05 B01 (a) Master devic e (b) S la ve de v i[...]

C141-E034-02EN 3 - 11 06 B02 CS EL c o nn ec ted to th e interf ace Ca ble s el ect i on can be don e b y th e spe c ial interfac e cab le. B01 0 5 Figure 3.13 Jumper setting of Cable Select Figures 3.14 and 3.15 show examples of cable selection using unique interface cables. By connecting the CS EL of the m aster device to the C SEL Lin e (conduct[...]

C141-E034-02EN 3 - 12 (3) Special setting 1 (SP1) The number of cylinders reported by the IDENTIFY DEVICE command is selected. (a) Default mode 2 4 6 1 3 5 2 4 6 Sl a ve Devi ce Mast er Device 1 3 5 2 4 6 1 3 5 Ca ble S el ect Model No. of cylinders MPA3017AT 3,390 MPA3026AT 5,086 MPA3035AT 6,780 MPA3043AT 9,042 MPA3052AT 10,850 (b) Special mode 2 [...]

C141-E034-02EN 4 - 1 CHAPTER 4 THEOR Y OF DEVICE OPERA TION 4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration 4.4 Power-on sequence 4.5 Self-calibration 4.6 Read/Write circuit 4.7 Servo Control This chapter ex plains basic design con cepts of the disk driv e. Also, this chapter ex plains subassem blies of the disk drive, each sequence, servo [...]

C141-E034-02EN 4 - 2 4.2.2 Head Figu re 4.1 show s the read/ writ e head stru ctures. The MPA 3017AT has 2 read/w rite h eads, the MPA3026A T has 3, MPA3035A T has 4, MPA 3043AT has 5, an d MPA3052AT has 6. T hese heads are raised from the disk surface as the spindle motor approaches the rated rotation speed. Spindl e 0 1 Actu ator MPA3017 Model MP[...]

C141-E034-02EN 4 - 3 4.2.3 Spindle The spindle con sists of a disk stack assembly and spindle m otor. T he disk stack assem bly is activated by the direct dri ve sens or-less DC spindle m otor, w hich h as a speed of 5,400 rpm ±0.5% . The spindle is co ntrolled with detecting a PHASE signal generated by counter electro motive voltage of the spindl[...]

C141-E034-02EN 4 - 4 4.3 Circuit Configuration Figure 4.2 shows the disk drive circuit configuration. (1) Read/write circuit The read/write circuit consists of tw o LSIs; read/write preamplifier (PreAMP) and read channel (RDC). The Pr eAMP consists of the write current sw itch circuit, that flows the w rite current to the head coil, and the voltage[...]

C141-E034-02EN 4 - 5 Figure 4.2 MPA30xxAT Block diagram[...]

C141-E034-02EN 4 - 6 4.4 Power-on Sequence Figure 4.3 describ es the operation seq uence of the disk drive at power-on. The outline is describ ed below. a) Af ter the pow er is turned on, th e disk drive executes th e MPU bus test, internal register read/write test, and w ork RAM read/write test. When the self-diagnosis term inates successfully, th[...]

C141-E034-02EN 4 - 7 c) b) a) R ele ase heads f rom actu ato r loc k Co nfirming spindle mo to r speed Self-di a g n osis 2 • Data b uf f er w rite/read te st The sp indle mo to r starts. Self-di a g n osis 1 • MPU bus test • I nne r re gi s te r w rite/read tes t • Wo rk R AM w rite/read te st Start Pow er on Driv e re ady state (c o mmand[...]

C141-E034-02EN 4 - 8 4.5 Self-calibration The disk drive occasionally perform s self-calibration in order to sense and calibrate mech anical external f orces on the actuator, and VCM torqu e. This enables precise seek and read/write operations. 4.5.1 Self-calibration contents (1) Sensing and compensating for external forces The actuator suff ers fr[...]

C141-E034-02EN 4 - 9 4.5.2 Execution timing of self-calibration Self-calibration is executed when: • The power is turned on. • The disk drive receives the RECALIBRATE command from the host. • The self-calibration execution timechart of the disk drive specifies self-calibration. The disk drive perform s self- calibration according to th e time[...]

C141-E034-02EN 4 - 10 4.6 Read/write Circuit The read/write circuit consists of the read/w rite preamplifier (PreAMP), the write circuit, the read circuit, and the tim e base generator in the read chann el (RDC). Figure 4.4 is a block diagram of the read/write circuit. 4.6.1 Read/write preamplifier (PreAMP) One PreAMP is mou nted on the FPC. The Pr[...]

C141-E034-02EN 4 - 11 Figure 4.4 Read/write circuit block diagram[...]

C141-E034-02EN 4 - 12 4.6.3 Read circuit The head read signal f rom the PreAMP is regu lated by th e automatic g ain control (AGC ) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the adaptive equ alizer circuit. This clock signal is converted in to the NRZ data by the 8/9 GCR decoder ci[...]

C141-E034-02EN 4 - 13 Figure 4.6 PR4 signal transfer[...]

C141-E034-02EN 4 - 14 (4) Viterbi detection circuit The sample hold waveform output from the adaptive equalizer circuit is sent to the Viterb i detection circuit. The Viterbi detection circu it demodulates data according to the survivor path sequence. (5) Data separator circuit The data sep arator circuit generates clocks in synchronization with th[...]

C141-E034-02EN 4 - 15 Table 4.3 Write clock frequency and transfer rate of each zone Zone 0 1 2 34567 Cylinder 0 to 622 623 to 1788 1789 to 2217 2218 to 2618 2619 to 3030 3031 to 3827 3828 to 4141 4142 to 4808 Transfer rate [MB/s] 14.964 14.111 13.787 13.473 13.155 12.512 12.258 11.702 Zone 8 9 10 11 12 13 14 Cylinder 4809 to 5119 5120 to 6107 6108[...]

C141-E034-02EN 4 - 16 4.7.1 Servo control circuit Figure 4.7 is the block d iagram of the servo contro l circuit. The following describes the functions of the blocks: (5) (1) (2) (3) (4) P. Amp. CS R : C urre nt S e ns e R es is to r VCM: Voice Coil Motor Spindl e mo to r c o ntro l DSP uni t Ser vo bur st captur e SVC MPU CSR Dr iver DAC ADC Po si[...]

C141-E034-02EN 4 - 17 c. Seek to specified cylinder Drives the VCM to position the head to the specified cylinder. d. Calibration Senses and stores th e thermal of fset betw een heads and th e mechan ical forces on the actu ator, and stores the calibration value. Figure 4.8 Physical sector servo configuration on disk surface[...]

C141-E034-02EN 4 - 18 (2) Servo burst capture circuit The four servo signals can be sy nchronously detected by the STROB signal, full-wave rectified integrated. (3) A/D converter (ADC) The A/D converter (A DC) receives the servo sig nals are integrated, converts them to digital, and transfers the digital signal to the DSP unit. (4) D/A converter (D[...]

C141-E034-02EN 4 - 19 4.7.2 Data-surface servo format Figure 4.8 describes the phy sical lay out of the servo f rame. The three areas in dicated by (1) to (3) in Figure 4.8 are described below. (1) Inner guard band The head is in con tact w ith the disk in this space w hen the spindle starts turn ing or stops, and the rotational speed of the spindl[...]

C141-E034-02EN 4 - 20 (1) Write/read recovery This area is used to absorb the write/read transient and to stabilize the AGC. (2) Servo mark This area generates a timing for demodulating the gray code and po sition-demodulating the servo A to D by detecting the servo mark. (3) Gray code (including index bit) This area is used as cy linder add ress. [...]

C141-E034-02EN 4 - 21 d) If the head is stopped at the reference cylinder from there. Track following control starts. (2) Seek operation Upon a data read/w rite request from the host, the MPU conf irms the n ecessity of access to the disk. If a read or instruction is issued, the MPU seeks the desired track. The MPU feeds the VCM current via the D/A[...]

C141-E034-02EN 4 - 22 e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a specif ic period, the MPU resets the SVC and starts from the beginni ng. When a PHASE sign al is sent, the SVC enters the acceleration mode. (2) Acceleration mode In this mode, the MPU stops to send the phase switching signal to the SVC. The SVC start[...]

C141-E034-02EN 5 - 1 CHAPTER 5 INTERF ACE 5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands 5.4 Command Protocol 5.5 Ultra DMA Feature Set 5.6 Timing[...]

C141-E034-02EN 5 - 2 5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals. IN TRQ : IN TER RU PT R EQ U EST IOCS16-: IOCS 16 PDIAG- : PASSE D DI AGNOST I C IORDY : I/ O C HANNEL READY DASP- : DE VIC E AC T I VE / DE VIC E 1 PRESE NT IOW-: I/O W RITE IOR - : I/O READ DMARQ: DMA REQUEST DMACK-: DMA AC KNOWLEDGE IDD Ho[...]

C141-E034-02EN 5 - 3 5.1.2 Signal assignment on the connector Table 5.1 shows the signal assignment on the interface connector. Table 5.1 Signal assignment on the interface connector Pin No. Signal Pin No. Signal 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 RESET– DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND DMARQ IOW–, STOP IO[...]

C141-E034-02EN 5 - 4 [signal] [I/O] [Description] IOR–, HDMARDY–, HSTROBE I IOR– is the strobe signal asserted by the host to read device registers or the data port. HDMARDY– is a flow control signal for Ultra DMA data in bursts. This signal is asserted by the host to indicate to the device that the host is ready to receive Ultra DMA data i[...]

C141-E034-02EN 5 - 5 [signal] [I/O] [Description] IORDY, DDMARDY–, DSTROBE O This signal is negated to extend the host transfer cycle of any host register access (Read or Write) when the device is not ready to respond to a data transfer request. DDMARDY– is a flow control signal for Ultra DMA data out bursts. This signal is asserted by the devi[...]

C141-E034-02EN 5 - 6 5.2 Logical Interface The device can operate for comm and execution in either address-specif ied mode; cy linder-h ead- sector (C HS) or L ogical block addres s (LBA ) mode. The IDENTIFY DEVICE i nform ation indicates w hether th e device supports the LBA mode. When the host s ystem specif ies the L BA mode by setting bit 6 in [...]

C141-E034-02EN 5 - 7 Table 5.2 I/O registers I/O registers Read operation Write operation Command block registers 10000 Data Data X'1F0' 10001 Error Register Features X'1F1' 10010 Sector Count Sector Count X'1F2' 10011 Sector Number Sector Number X'1F3' 10100 Cylinder Low Cylinder Low X'1F4' 10101 C[...]

C141-E034-02EN 5 - 8 5.2.2 Command block registers (1) Data register (X'1F0') The Data register is a 16-bit regi ster for data block transfer betw een the device and the host system. Data transfer mode is PIO or LBA mode. (2) Error register (X'1F1') The Error reg ister indicates the status of the com man d executed by the device[...]

C141-E034-02EN 5 - 9 [Diagnostic code] X'01': No Error Detected. X'02': HDC Register Compare Error X'03': Data Buffer Compare Error. X'05': ROM Sum Check Error. X'80': Device 1 (slave device) Failed. Error register of the master device is valid under two devices (master and slave) configuration. If [...]

C141-E034-02EN 5 - 10 (6) Cylinder Low register (X'1F4') The contents of th is register indicates low -order 8 bits of th e starting cy linder address for any disk- access. At the end of a command, the contents of this register are updated to the current cylinder number. Under the LBA mode, this register indicates LBA bits 15 to 8. (7) Cy[...]

C141-E034-02EN 5 - 11 (9) Status register (X'1F7') The contents of this reg ister indicate the status of the device. T he contents of this register are updated at the com pletion of each com m and. When the BSY bit is cleared, other bits in this regist er should be v alidated w ithin 400 ns. Wh en the BSY bi t is 1, other bits of this reg[...]

C141-E034-02EN 5 - 12 - Bit 3: Data Request (DRQ) bit. This bit indicates that th e device is ready to tran sfer data of word unit or byte unit between the host system and the device. - Bit 1: Always 0. - Bit 0: Error (ERR) bit. This bit indicates that an error was detected w hile the previou s comm and was being executed. The Error register ind ic[...]

C141-E034-02EN 5 - 13 5.2.3 Control block registers (1) Alternate Status register (X'3F6') The Alternate Status reg ister contains the sam e information as the Status register of the comm and block register. The only differen ce from the Status register is that a read of this reg ister does not imply Interrupt Acknowledge and INTRQ signal[...]

C141-E034-02EN 5 - 14 5.3.1 Command code and parameters Table 5.3 lists t he supporte d comm ands, com m and code and th e registers th at needed parameters are written. Table 5.3 Command code and parameters (1 of 2) Command code (Bit) Parameters used 765432 10 F R S C S N C Y D H READ SECTOR(S) 0 0 1 0 0 0 0 R N Y Y Y Y READ MULTIPLE 1 1 0 0 0 1 0[...]

C141-E034-02EN 5 - 15 Table 5.3 Command code and parameters (2 of 2) Command code (Bit) Parameters used 765432 10 F R S C S N C Y D H STANDBY IMMEDIATE 1 1 0 1 0 1 1 0 0 0 1 0 0 0 0 0 NNNN D SLEEP 1 1 0 1 0 1 1 0 1 0 0 1 0 1 1 0 NNNN D CHECK POWER MODE 1 1 0 1 0 1 1 0 1 0 0 1 0 0 0 1 NNNN D SMART 1 0 1 1 0 0 0 0 Y Y Y Y D Notes: FR : Features Regis[...]

C141-E034-02EN 5 - 16 5.3.2 Command descriptions The contents of th e I/O registers to be necessary for issuing a comm and and the example indication of the I/O registers at command completion are shown as following in this subsection. Example: READ SECTOR(S) WITH RETRY At command issuance (I/O registers setting contents) B i t 76543210 1F7 H (CM) [...]

C141-E034-02EN 5 - 17 Note: 1. When the L bit is specified to 1, the lower 4 bits of the DH register and all bits o f the CH, CL and SN reg isters indicate the LBA bits (bits of the DH register are the MSB (most significant bit) and bits of the SN register are the LSB (least significant bit). 2 . At error occurrence, the SC reg ister in dicates the[...]

C141-E034-02EN 5 - 18 At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) × L × D V End head No. /LBA [MSB] 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (ER) End cylinder No. [MSB] / LBA End cylinder No. [LSB] / LBA End sector No. / LBA [LSB] 00 (*1) Error information *1 If th e com mand is term[...]

C141-E034-02EN 5 - 19 Figure 5.2 shows an example of the execution of the READ MULTIPLE command. • Block cou nt specif ied by SET MULTIPLE MODE com m and = 4 (num ber of sectors in a block) • READ MULTIPLE command specifies; Number of requested sectors = 9 (Sector Count register = 9) ↓ Number of sectors in incomplete block = remainder of 9/4 [...]

C141-E034-02EN 5 - 20 Note: If the comm and is terminated due to an error, the remaining number of secto rs for wh ich d ata was not transferred is set in this register. (3) READ DMA (X'C8' or X'C9') This command operates similarly to the READ SECTOR(S) command except for following events. • The data transfer starts at the tim[...]

C141-E034-02EN 5 - 21 At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) × L × D V End head No. /LBA [MSB] 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (ER) End cylinder No. [MSB] / LBA End cylinder No. [LSB] / LBA End sector No. / LBA [LSB] 00 (*1) Error information *1 If th e com mand is term[...]

C141-E034-02EN 5 - 22 At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) × L × D V End head No. /LBA [MSB] 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (ER) End cylinder No. [MSB] / LBA End cylinder No. [LSB] / LBA End sector No. / LBA [LSB] 00 (*1) Error information *1 If th e com mand is term[...]

C141-E034-02EN 5 - 23 At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) × L × D V End head No. /LBA [MSB] 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (ER) End cylinder No. [MSB] / LBA End cylinder No. [LSB] / LBA End sector No. / LBA [LSB] 00 (*1) Error information *1 If th e com mand is term[...]

C141-E034-02EN 5 - 24 The contents of th e comm and block registers related to addresses af ter the transfer of a data block containin g an erred sector are undefin ed. To obtain a valid error inf ormation, th e host should retry data transfer as an individual requests. At command issuance (I/O registers setting contents) 1F7 H (CM) 11000101 1F6 H [...]

C141-E034-02EN 5 - 25 1) Single word DMA transfer mode 2: Sets the FR register = X'03' and SC register = X'12' by the SET FEATURES command 2) Multiword DMA transfer mode 2: Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES command 3) Ultra DMA transfer mode 2: Sets the FR register = X&a[...]

C141-E034-02EN 5 - 26 At command issuance (I/O registers setting contents) 1F7 H (CM) 00111100 1F6 H (DH) × L × D V Start head No. /L BA [MSB] 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (FR) Start cylinder No. [MSB] / LBA Start cylinder No. [LSB] / LBA Start sector No. / LBA [LSB] Transfer sector count xx R = 0 → with Retry R = 1 → wit[...]

C141-E034-02EN 5 - 27 At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) ××× DV x x 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (ER) xx xx xx xx Error information (10) SEEK (X'7x', x : X'0' to X'F') This comm and perform s a seek operation to th e track and selec[...]

C141-E034-02EN 5 - 28 (11) INITIALIZE DEVICE PARAMETERS (X'91') The host system can set the n umber of sectors per track and the m axim um head num ber (max imum head n umber is "number of heads mi nus 1") per cylin der with th is comm and. Upon receipt of th is comm and, the device sets the BSY bit of Status reg ister and saves[...]

C141-E034-02EN 5 - 29 At command issuance (I/O registers setting contents) 1F7 H (CM) 11101100 1F6 H (DH) ××× DV x x 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (FR) xx xx xx xx xx At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) ××× DV x x 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1[...]

C141-E034-02EN 5 - 30 Table 5.4 Information to be read by IDENTIFY DEVICE command (1 of 3) Word Value Description 0 X‘0C5A’ General Configuration *1 1 X‘0D3E’ X‘13DE’ X‘1A7C’ X‘2352’ X‘2A62’ Number of cylinders MPA3017AT: X‘0D3E’ MPA3026AT: X‘13DE’ MPA3035AT: X‘1A7C’ MPA3043AT: X‘2352’ MPA3052AT: X‘2A62’ [...]

C141-E034-02EN 5 - 31 Table 5.4 Information to be read by IDENTIFY DEVICE command (2 of 3) Word Value Description 89-127 X‘00’ Reserved 128 X‘00’ Security status not supported 129-159 X‘00’ Undefined 160-255 X‘00’ Reserved *1 Word 0: General configuration Bit 15: 0 = ATA device 0 Bit 14-8: Vendor specific 0 Bit 7: 1 = Removable medi[...]

C141-E034-02EN 5 - 32 Table 5.4 Information to be read by IDENTIFY DEVICE command (3 of 3) *8 Word 59: Transfer sector count currently set by READ/WRITE MULTIPLE command Bit 15-9: Reserved Bit 8: Multiple sector transfer 1=Enable Bit 7-0: Transfer sector coun t currently set by READ/WRITE MULTIPLE w ithout interrupt supports 2, 4, 8, 16 and 32 sect[...]

C141-E034-02EN 5 - 33 (13) IDENTIFY DEVICE DMA (X'EE') When this com mand is not used to transfer data to the host in DMA mode, this co mmand functions in the same way as the Identify Device command. At command issuance (I/O registers setting contents) 1F7 H (CM) 11101110 1F6 H (DH) ××× DV x x 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC[...]

C141-E034-02EN 5 - 34 Table 5.5 Features register values and settable modes Features Register Drive operation mode X‘02’ Enables the write cache function. X‘03’ Specifies the transfer mode. Supports PIO mode 4, single word DMA mode 2, and multiword DMA mode regardless of Sector Count register contents. X‘55’ Disables read cache function[...]

C141-E034-02EN 5 - 35 The host sets X' 03' to the Features register. By issuing this comm and with setting a value to the Sector Coun t register, th e transfer m ode can be selected. Upper 5 bits of the Sector C ount register defines the transfer type and lower 3 bits specifies the binary mode value. However, the IDD can operate with the [...]

C141-E034-02EN 5 - 36 At command issuance (I/O registers setting contents) 1F7 H (CM) 11000110 1F6 H (DH) ××× DV x x 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (FR) xx xx xx Sector count/block xx At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) ××× DV x x 1F5 H (CH) 1F4 H (CL) 1F3 H (SN[...]

C141-E034-02EN 5 - 37 (16) EXECUTE DEVICE DIAGNOSTIC (X'90') This comm and perf orms an intern al diagnostic test (self -diagnosis) of th e device. This comm and usually sets the DRV bit of the Drive/Head register is to 0 (however, the DV bit is not checked). If two devices are present, both devices execute self-diagnosis. If device 1 is [...]

C141-E034-02EN 5 - 38 At command issuance (I/O registers setting contents) 1F7 H (CM) 10010000 1F6 H (DH) ××× DV x x 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (FR) xx xx xx xx xx At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) ××× DV x x 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1[...]

C141-E034-02EN 5 - 39 At command issuance (I/O registers setting contents) 1F7 H (CM) 0010001 R 1F6 H (DH) × L × DV Head No. /LBA [MSB] 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (FR) Cylinder No. [MSB] / LBA Cylinder No. [LSB] / LBA Sector No. / LBA [LSB] Number of sectors to be transferred xx R = 0 → with Retry R = 1 → without Retry [...]

C141-E034-02EN 5 - 40 At command issuance (I/O registers setting contents) 1F7 H (CM) 0011001 R 1F6 H (DH) × L × DV Head No. /LBA [MSB] 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (FR) Cylinder No. [MSB] / LBA Cylinder No. [LSB] / LBA Sector No. / LBA [LSB] Number of sectors to be transferred xx R = 0 → with Retry R = 1 → without Retry [...]

C141-E034-02EN 5 - 41 At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) ××× DV x x 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (ER) xx xx xx xx Error information (21) WRITE BUFFER (X'E8') The host system can overw rite the cont ents of the sector buf fer of the dev ice with a desir[...]

C141-E034-02EN 5 - 42 (22) IDLE (X'97' or X'E3') Upon receipt of th is comm and, the device sets th e BSY bit of the Status register, and enters the idle mode. Then, th e device clears the BSY bit, and g enerates an interrupt. The dev ice generates an interrupt even if the device has no t fully entered the idle mode. If the spin[...]

C141-E034-02EN 5 - 43 At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) ××× DV x x 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (ER) xx xx xx xx Error information (23) IDLE IMMEDIATE (X'95' or X'E1') Upon receipt of th is comm and, the device sets th e BSY bit of the Statu[...]

C141-E034-02EN 5 - 44 (24) STANDBY (X'96' or X'E2') Upon receipt of th is comm and, th e device sets th e BSY bit of the Status reg ister and enters the standby mode. The device then clears the BSY bit and gen erates an interrupt. The device generates an in terrupt even if the device has n ot fully entered the standby mode. If t[...]

C141-E034-02EN 5 - 45 At command issuance (I/O registers setting contents) 1F7 H (CM) X'94' or X'E0' 1F6 H (DH) ××× DV x x 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (FR) xx xx xx xx xx At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) ××× DV x x 1F5 H (CH) 1F4 H (CL)[...]

C141-E034-02EN 5 - 46 At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) ××× DV x x 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (ER) xx xx xx xx Error information (27) CHECK POWER MODE (X'98' or X'E5') The host checks the power mode of the device with this command. The hos[...]

C141-E034-02EN 5 - 47 At command issuance (I/O registers setting contents) 1F7 H (CM) X'98' or X'E5' 1F6 H (DH) ××× DV x x 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (FR) xx xx xx xx xx At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) ××× DV x x 1F5 H (CH) 1F4 H (CL)[...]

C141-E034-02EN 5 - 48 Table 5.7 Features Register values (subcommands) and functions Features Resister Function X’D0’ SMART Read Attribute Values: A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512-byte attribute value information to the hos[...]

C141-E034-02EN 5 - 49 The host can predict failures in the device by periodically issuing the SMART Return Status subcommand (FR register = DAh) to reference the CL and CH registers. If an attribute value is below the insurance failure threshold value, the device is about to fail or the device is nearing the end of it lif e . In this case, the host[...]

C141-E034-02EN 5 - 50 The attri bute va lue in form ation i s 512-by te data; th e form at of thi s data is sh own below . The host can access this data usin g the SMAR T Read Attribute Values subcom man d (FR register = D0h). The insu rance fail ure thresh old valu e data is 512-by te data; the form at of this data is show n below. The host can ac[...]

C141-E034-02EN 5 - 51 Table 5.9 Format of insurance failure threshold value data Byte Item 00 01 Data format version number 02 Attribute 1 Attribute ID 03 Insurance failure threshold 04 to 0D Threshold 1 (Threshold of attribute 1) Reserved 0E to 169 Threshold 2 to threshold 30 (The format of each threshold value is the same as that of bytes 02 to 0[...]

C141-E034-02EN 5 - 52 • Attribute ID The attribute ID is defined as follows: Attribute ID Attribute name 0 (Indicates unused attribute data.) 1 Reserved 2 Reserved 3 Spindle motor activation time 4 Number of times the spindle motor is activated 5 Number of alternative sectors 7 Reserved 8 Reserved 9 Power-on time 10 Number of retries made to acti[...]

C141-E034-02EN 5 - 53 • Raw attribute value Raw attributes data is retained. • Failure prediction capability flag Bit 0: The attribute value d ata is saved to a medium before the device enters po wer saving mode. Bit 1: T he device automatically saves the attribute value data to a m edium after the p reviously set operation. Bits 2 to 15: Reser[...]

C141-E034-02EN 5 - 54 5.3.3 Error posting Table 5.10 lists the defined errors that are valid for each command. Table 5.10 Command code and parameters Command name Error register (X'1F1') Status register (X'1F7') BBK UN C INDF ABRT TR0NF DRDY DW F CORR ERR READ SECTOR(S) VV V V V V V V WRITE SECTOR(S) VV V V V V READ MULTIPLE VV [...]

C141-E034-02EN 5 - 55 5.4 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 pr ior to issue a comm and. If BSY b it is 1, the host should wait for issuing a command until BSY bit is cleared to 0. Comm ands can be executed on ly w hen th e DRDY bit of the Status register is 1. How ever, the following[...]

C141-E034-02EN 5 - 56 Status read Status read *1 Wh en t h e I D D r eceives a co mmand th at h its the c ache d ata during r ead-ahe ad, and tran sf ers d ata f rom the b uff er w ithout re ading f rom the d isk me diu m. 255 2 1 0 Wor d IOCS16- IOR - Data Data R eg. Se le ctio n INTRQ DRQ Min. 30 µ s (*1) Expan ded Co mmand fd d e e c b a Co mma[...]

C141-E034-02EN 5 - 57 Note: For transfer of a sector of data, the host needs to read Statu s register (X'1F7' ) in order to clear INTRQ (interrupt) signal. The Status regi ster should be read w ithin a period f rom the DR Q setting by the device to 50 µ s after the com pletion of the sector data transfer. Note that the host does not need[...]

C141-E034-02EN 5 - 58 c) When the device is ready to receive th e data of the first sector, th e device sets DRQ bit and clears BSY bit. d) The host writes one sector of data through the Data register. e) The device clears the DRQ bit and sets the BSY bit. f) When th e drive com pletes transferring th e data of the sector, the device clears BSY bit[...]

C141-E034-02EN 5 - 59 Note: For transfer of a sector of data, the host needs to read Statu s register (X'1F7' ) in order to clear INTRQ (interrupt) signal. The Status regi ster should be read w ithin a period f rom the DR Q setting by the device to 50 µ s after the com pletion of the sector data transfer. Note that the host does not need[...]

C141-E034-02EN 5 - 60 5.4.4 Other commands • READ MULTIPLE • SLEEP • WRITE MULTIPLE See the description of each command. 5.4.5 DMA data transfer commands • READ DMA • WRITE DMA Starting the DMA transfer com mand is the sam e as the REA D SECTOR(S) or W RITE SECTOR(S) comm and except the point that th e host initializes the DMA chan nel pr[...]

C141-E034-02EN 5 - 61 Status read 255 2 1 0 Word IOR- or IOW- DMACK- DMARQ DRQ Expanded [Single Word DMA transfer] Command BSY I NTRQ DRDY ~ Parameter write DRQ Data transfer • • • • • • • • • • • • • • • • • • • • DRQ [Multiword DMA transfer] • • • • DMACK- DMARQ • • • • IOR- or IOW- • • [...]

C141-E034-02EN 5 - 62 5.5 Ultra DMA feature set 5.5.1 Overview Ultra DMA is a data tran sfer protocol used w ith the R EAD DMA an d WRITE DMA comm ands. When this protocol is enabled it shall be used instead of the Multiword DMA proto col when these comm ands are issued by the host. T his protocol applies to the Ultra DMA data burst only . When thi[...]

C141-E034-02EN 5 - 63 5.5.2 Phases of operation An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts. Each Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and the Ultra DMA burst termination phase. In addition, an Ultra DMA burst may be paus ed du[...]

C141-E034-02EN 5 - 64 11) The device shall drive the fi rst w ord of the data transfer on to DD (15:0). This step may occur when the device first drives DD (15:0) in step (10). 12) To transfer the first w ord of data the device shall negate DST ROBE within t FS after the host has negated STOP a n d a sserted HDMARD Y-. The de vice shall nega te DST[...]

C141-E034-02EN 5 - 65 3) T he devic e shall stop gener ating DST ROBE edges within t RFS of the host negating HDMARDY-. 4) If the host negates HDMARDY- within t SR after the dev ice has generated a DSTROBE edge, then the host shall be prepared to receive zero or one add itional data words. If th e host negate s HDMARD Y- grea ter tha n t SR after t[...]

C141-E034-02EN 5 - 66 10) T he device shall latch the host's CRC da ta fro m DD (15:0 ) on the ne gating edge of DMACK-. 11) The device shall compare the CRC data received from the host w ith the results of its own CRC calculation. If a m iscompare error o ccurs d uring one o r more Ultra DMA bursts for any one com m and, at the end of the com[...]

C141-E034-02EN 5 - 67 10) If the host has not placed the result o f its CRC calculation on DD (15 :0) since first dr iving DD (15:0) during (9), the host shall place the result of its CRC calculation on DD (15:0 ) (see 5.5.5). 11) T he host shall nega te DMACK- no sooner than t MLI after th e device has asserted DST ROBE and negate d DMARQ and the [...]

C141-E034-02EN 5 - 68 9) T he device shall assert DDMARDY- w ithin t LI after the ho st has negate d ST OP. Afte r asserting DMARQ and DDMARDY- the device shall no t negate either signal until after the first negation of HSTROBE by the host. 10) T he host shall drive the first word of the data transfer onto DD (15:0). T his step may o ccur any time[...]

C141-E034-02EN 5 - 69 2) The device shall pause an Ultra DMA burst by negating DDMARDY-. 3) T he host shall sto p gene rating HST ROB E ed ges within t RFS of the de vice negating DDMARDY-. 4) If the device negates DDMARDY- w ithin t SR a fter the host ha s genera ted an H STROB E edge, then the device sh all be prepared to receive zero or one addi[...]

C141-E034-02EN 5 - 70 10) The device shall release DDMARDY- within t IORDYZ after the host has negated DMACK-. 11) The host shall neither negate STOP nor negate HSTROB E until at least t ACK after negating DMACK-. 12) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t AC K after negating DMACK. b) Device terminating an U[...]

C141-E034-02EN 5 - 71 13) The host shall neither negate ST OP no r HSTROBE until at least t ACK after negating DMACK-. 14) T he host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t ACK after negating DMACK. 5.5.5 Ultra DMA CRC rules The fo llowing is a list of rules fo r ca lculating CRC, d etermining if a CRC e rror has occ u[...]

C141-E034-02EN 5 - 72 5.5.6 Series termination required for Ultra DMA Series termin ation resistors are required at both the h ost and the device f or operation in any of the Ultra DMA Modes. The follow ing table describes recom mended v alues for series term ination at the host and the device. Table 5.11 Recommended series termination for Ultra DM[...]

C141-E034-02EN 5 - 73 5.6 Timing 5.6.1 PIO data transfer Figure 5.9 shows of the data transfer timing between the device and the host system.[...]

C141-E034-02EN 5 - 74 t8 t6 t12 t11 t10 t7 t5 t4 t3 t9 t2i t2 t1 t0 Addr esses IOR DY IOCS16- R ead data DD0-DD15 Write data DD0-DD15 DIOR-/DIOW- Sy m bo l Timing parameter Min. Max. Unit t0 Cycle time 120 — ns t1 Data register selection setup time for DIOR-/DIOW- 25 — ns t2 Pulse width of DIOR-/DIOW- 70 — ns t2i Recovery time of DIOR-/DIOW- [...]

C141-E034-02EN 5 - 75 5.6.2 Single word DMA data transfer Figure 5.10 show the sin gle w ord DMA data transfer tim ing betw een the device and the host system. tF tE tH tG tJ tD tI tC t0 R ead data DD0-DD15 Write data DD0-DD15 DIOR-/DIOW- DMACK- DMARQ Sy m bo l Timing parameter Min. Max. Unit t0 Cycle time 240 — ns tC Delay time from DMACK assert[...]

C141-E034-02EN 5 - 76 5.6.3 Multiword data transfer Figure 5.11 sho ws the m ultiw ord DMA data transfer timing betw een the d evice and the ho st system. tF tE tH tG tJ tD tI tC t0 R ead data DD0-DD15 Write data DD0-DD15 DIOR-/DIOW- DMACK- DMARQ tK Sy m bo l Timing parameter Min. Max. Unit t0 Cycle time 120 — ns tC Delay time from DMACK assertio[...]

C141-E034-02EN 5 - 77 5.6.4 Ultra DMA data transfer Figures 5.12 through 5.21 define the timings associated with all phases of Ultra DMA bursts. Table 5.12 contains the values for the timings for each of the Ultra DMA Modes. 5.6.4.1 Initiating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. No[...]

C141-E034-02EN 5 - 78 5.6.4.2 Ultra DMA data burst timing requirements Table 5.12 Ultra DMA data burst timing requirements NA M E MODE 0 (in ns) MODE 1 (in ns) MODE 2 (in ns) COMMENT MIN MAX MIN MAX MIN MAX t CYC 114 75 55 Cycle time (from STROBE edge to STROBE edge) t2 CYC 235 15 6 117 Two cycle time (from rising edge to next rising edge or from f[...]

C141-E034-02EN 5 - 79 NA M E MODE 0 (in ns) MODE 1 (in ns) MODE 2 (in ns) COMMENT MIN MAX MIN MAX MIN MAX t IORDYZ 20 20 20 Pull-up time before allowing IORDY to be released t ZIORDY 0 0 0 Minimum time device shall wait before driving IORDY t ACK 20 20 20 Setup and hold times for DMACK- (before assertion or negation) t SS 50 50 50 Time from STROBE [...]

C141-E034-02EN 5 - 80 5.6.4.3 Sustained Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and DSTROBE are show n at both the host and the device to emph asize that cable setting tim e as w ell as cable prop agation delay shall not allow the data signals to be considered stable at th[...]

C141-E034-02EN 5 - 81 5.6.4.4 Host pausing an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: 1) T he host may assert STOP to request termination of the Ultra DMA burst no sooner than t RP after HDMARDY- is negated. 2) If the t SR tim ing is not satisf ied, the host may receive zero, one o[...]

C141-E034-02EN 5 - 82 5.6.4.5 Device terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the ST OP, HDMARDY and DSTROB E signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.15 Device terminating an Ultra DMA data in burst[...]

C141-E034-02EN 5 - 83 5.6.4.6 Host terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the ST OP, HDMARDY and DSTROB E signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.16 Host terminating an Ultra DMA data in burst[...]

C141-E034-02EN 5 - 84 5.6.4.7 Initiating an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the ST OP, DDMARDY and HSTROB E signal lines are not in effect until DMARQ and DMACK are asserted. Figure 5.17 Initiating an Ultra DMA data out burst[...]

C141-E034-02EN 5 - 85 5.6.4.8 Sustained Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and HSTROBE signals are show n at both th e device and the host to emphasize that cable setting time as w ell as cable prop agation delay shall not allow the data signals to be considered stab[...]

C141-E034-02EN 5 - 86 5.6.4.9 Device pausing an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: 1) The device m ay negate DMARQ to request termination of the Ultra DMA burst no sooner than t RP after DDMARDY- is negated. 2) I f th e t SR timing is n ot satisfied, the device m ay receive z[...]

C141-E034-02EN 5 - 87 5.6.4.10 Host terminating an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the ST OP, DDMARDY and HSTROB E signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.20 Host terminating an Ultra DMA data out burst[...]

C141-E034-02EN 5 - 88 5.6.4.11 Device terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the ST OP, DDMARDY and HSTROB E signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.21 Device terminating an Ultra DMA data out burst[...]

C141-E034-02EN 5 - 89 5.6.5 Power-on and reset Figure 5.22 shows power-on and reset (hardware and software reset) timing. (1) Only master device is present *1: R ese t me ans includ ing Po w e r-on-R ese t, H ardw are R ese t (R ESET-), and So ftw ar e R e se t. Clear Re set *1 tP tN tM BSY DASP- Pow er- on R ESET- S o f tw are re s e t (2) Master [...]

C141-E034-02EN 6 - 1 CHAPTER 6 OPERA TIO NS 6.1 Device Response to the Reset 6.2 Address Translation 6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache 6.6 Write Cache 6.1 Device Response to the Reset This section describes how the PDIA G- and DA SP- sign als responds w hen the power of the IDD is turned on or the IDD receives a reset or dia[...]

C141-E034-02EN 6 - 2 6.1.1 Response to power-on After th e master device (dev ice 0) releases its own pow er-on reset state, th e master device sh all check a DA SP- sign al for up to 450 m s to conf irm presen ce of a slav e device (device 1). T he master dev ice recognizes presence of the slave device w hen it confirm s assertion of the DASP- sig[...]

C141-E034-02EN 6 - 3 6.1.2 Response to hardware reset Response to RESET- (hardware reset through the interface) is similar to the power-on reset. Upon receipt of h ardware res et, the mas ter device check s a DASP- s ignal for up to 450 ms to confirm presence of a slav e device. The master dev ice recognizes the presen ce of the slave device wh en [...]

C141-E034-02EN 6 - 4 6.1.3 Response to software reset The master device does n ot check the DASP- sig nal for a softw are reset. If a slave device is present, the m aster device checks th e PDIAG- signal for u p to 31 seconds to see if the slave device has completed the self-diagnosis successfully. After th e slave device receives the sof tware res[...]

C141-E034-02EN 6 - 5 6.1.4 Response to diagnostic command When the m aster device receives an EXECUTE DEVICE DIAGNOSTIC com m and and the slave device is present, the master device checks the PDIA G- signal for up to 6 seconds to see if the slave device has completed the self-diagnosis successfully. The master device does not check the DASP- signal[...]

C141-E034-02EN 6 - 6 6.2 Address Translation When the IDD receives an y com mand w hich inv olves access to the disk m edium, th e IDD always implem ents the address translation from th e logical address (a host-specifi ed address) to the physical address (logical to physical address translation). Following subsections explains the CHS translation [...]

C141-E034-02EN 6 - 7 6.2.2 Logical address (1) CHS mode Logical address assig nmen t starts from ph ysical cy linder (PC) 0, phy sical head (PH) 0, and phy sical sector (PS) 1 and is assigned by calculating th e num ber of sectors per track which is specified by the INITIALIZE DEVIC E PARAMETERS com man d. T h e head address is advanced at the su b[...]

C141-E034-02EN 6 - 8 (2) LBA mode Logical address assignm ent in the LBA m ode starts from phy sical cylin der 0, physical h ead 0, and phy sical sector 1. The logical address is advanced at the subsequen t sector from the last sector of the current track. The first phy sical sector of the su bsequent phy sical track is the consecutive logical sect[...]

C141-E034-02EN 6 - 9 Regardless of w hether the power dow n is enabled, the device enters th e idle mode. The device also enters the idle mode in the same way after power-on sequence is completed. (1) Active mode In this m ode, all the electric circuit in th e device are active or the dev ice is under seek, read or write operation. A device enters [...]

C141-E034-02EN 6 - 10 • STANDBY IMMEDIATE command • INITIALIZE DEVICE PARAMETERS command • CHECK POWER MODE command (4) Sleep mode The power consumption of the drive is minimal in this m ode. T he drive enters only the standby mode f rom t he sleep m ode. The only met hod to return from the stan dby m ode is to execute a software or hardware [...]

C141-E034-02EN 6 - 11 6.4.1 Spare area Following two types of spare area are provided for every physical head. 1) Spare cylinder for sector slip: used for alternating defective sectors at formatting in shipment (11 cylinders/head) 2) Spare cylinder for alternative assignment: used for alternative assignment by automatic alternative assignment. (4 c[...]

C141-E034-02EN 6 - 12 (2) Alternate cylinder assignment A defective sector is assigned to the spare sector in the alternate cylinder. This processing is performed when the automatic alternate processing is performed. Figure 6.8 shows an example where (physical) sector 5 is detective on head 0 in cylinder 0. 57 6 4 3 1 250 249 2 Index Cylinder 0 Hea[...]

C141-E034-02EN 6 - 13 (3) Automatic alternate assignment The device performs the automatic assignment at following case. 1) When ECC correction perform ance is increased du ring read error retry , a read error is recovered. Before autom atic alternate assignm ent, the dev ice performs rewriting the corrected data to the erred sector an d rereading.[...]

C141-E034-02EN 6 - 14 6.5.2 Caching operation Caching operation is perform ed only at issu ance of the f ollowin g comm ands. The device transfers data from the data buffer to the host system at issuance of f ollowing comm and if following data exist in the data buffer. • All sectors to be processed by the command • A part of data including loa[...]

C141-E034-02EN 6 - 15 (3) Invalidating caching data Caching data in the data buffer is invalidated in the following case. 1) Following command is issued to the same data block as caching data. • WRITE SECTOR(S) • WRITE DMA • WRITE MULTIPLE 2) Command other than following commands is issued (all caching data are invalidated) • READ SECTOR (S[...]

C141-E034-02EN 6 - 16 1) Sets the host address pointer (HAP) and the disk address pointer (DAP) to the lead of segment. Se gme nt only fo r r ead DAP HAP 2) T ransfers the requested data th at already read to the h ost system w ith reading the requested data from the disk media. Re ad-r equeste d data St or es t h e r ead - r eques t ed data upto t[...]

C141-E034-02EN 6 - 17 (3) Sequential read When the disk driv e receives the read comm and that targets the sequential address to the previous read command, the disk drive starts the read-ahead operation. a. Sequential command just after non-sequential command When the prev iously ex ecuted read comm and is an n on-sequential com m and and the last [...]

C141-E034-02EN 6 - 18 4) The disk dr ive performs the read-ahead operatio n for all area of segment with overwriting the requested data. Finally, the cache data in the buffer is as follows. Start LBA Last LBA DAP HAP Read -ah ead d ata b. Sequential hit When the prev iously ex ecuted read comm and is the sequ ential comm and and th e last sector ad[...]

C141-E034-02EN 6 - 19 3) After com pletion o f data transfer of hit data, the disk d rive pe rforms the read-ahead operation for the data area of which the disk drive transferred hit data. R ead -ahead d ata 4) Finally, the cache data in the buffer is as follows. R ead -ahead d ata c. Non-sequential read command just after sequential read command W[...]

C141-E034-02EN 6 - 20 1) In the case that th e contents of th e data buff er is as follow s for exam ple and the previous comm and is a sequential read com man d, the disk drive sets the HAP to the address of which the hit data is stored. H AP (se t to hit po sitio n fo r data tr an sf er) L ast po sitio n at pr ev io us read c o mmand L ast po sit[...]

C141-E034-02EN 6 - 21 1) The disk dr ive sets the HAP to the addr ess wh ere the partially hit data is sto red, and sets the DAP to the address just after the partially hit data. HAP DAP Partially h it data Lac k d ata 2) T he disk driv e starts transferring partially hit data and reads lack data from the disk media at the same time. However, the d[...]

C141-E034-02EN 6 - 22 6.6 Write Cache The write cach e function of the drive m akes a high speed processing in th e case that data to be written by a write comm and is logically sequent the data of p revious comm and and rand om write operation is performed. When the driv e receives a write com m and, the drive starts transf erring data of sectors [...]

C141-E034-02EN 6 - 23 At the tim e that th e drive has s topped the com man d execution af ter the error recovery has f ailed, the w rite cache fun ction is disabled autom atically. The releasing the disable state can be don e by the SET FEA TURES comm and. When th e power of the drive is turned on after the pow er is turned off on ce, the status o[...]

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