Fujitsu MPB3021AT инструкция обслуживания

C141-E045-02EN MPB3021AT MPB3032AT MPB3043AT MPB3052AT MPB3064AT DISK DRIVES PRODUCT MANUAL[...]

C141-E045-0 2EN i REVISION RECORD Edition Date published Revised contents 01 August., 1997 02 March, 1998 All pages revised. Specification No.: C141-E045-**EN The contents of this manual is subject to change without prior notice. All Rights Reserved. Copyright  1998 FUJITSU LIMITED[...]

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C141-E045-0 2EN iii PREFACE This manual describes the MPB3021AT/MPB3032AT/MPB3043AT/MPB3052AT/MPB3064AT, a 3.5 -inch hard disk drive with a BUILT-IN controller that is compatible with the ATA interface. This manual explains, in detail, how to incorporate the hard disk drives into user systems. This manual assumes that users have a basic knowledge o[...]

iv C141-E045-0 2EN Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word. The following are the alert signals and their meanings: This indicates a haz[...]

C141-E045-0 2EN v LIABILITY EXCEPTION "Disk drive defects" refers to defects that involve adjustment, repair, or replacement. Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host sys[...]

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C141-E045-0 2EN vii CONTENTS page CHAPTER 1 DEVICE OVERVIEW ................................................................................... 1 - 1 1.1 Features ................................................................................................ .......................... 1 - 1 1.1.1 Functions and performance .........................[...]

C141-E045-02EN viii 3.4.1 Location of setting jumpers ................................................................ ............................ 3 - 9 3.4.2 Factory default setting ................................................................................................ .... 3 - 10 3.4.3 Jumper configuration ..............................[...]

C141-E045-0 2EN ix 5.2.2 Command block registers ............................................................................................... 5 - 8 5.2.3 Control block registers ................................................................................................ ... 5 - 13 5.3 Host Commands ...........................................[...]

C141-E045-02EN x 5.6.4.5 Device terminating an Ultra DMA data in burst ............................................................. 5 - 83 5.6.4.6 Host terminating an Ultra DMA data in burst ................................................................. 5 - 84 5.6.4.7 Initiating an Ultra DMA data out burst ................................ .....[...]

C141-E045-0 2EN xi FIGURES page 1.1 Current fluctuation (Typ.) when power is turned on ....................................................... 1 - 7 2.1 Disk drive outerview ................................................................................................ ...... 2 - 1 2.2 Configuration of disk media heads ............................[...]

C141-E045-02EN xii 5.4 Protocol for command abort ........................................................................................... 5 - 58 5.5 WRITE SECTOR(S) command protocol ................................ ........................................ 5 - 59 5.6 Protocol for the command execution without data transfer ......................[...]

C141-E045-0 2EN xiii TABLES page 1.1 Specifications ................................................................................................ ................. 1 - 4 1.2 Model names and product numbers ................................ ................................................ 1 - 5 1.3 Current and power dissipation ...................[...]

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C141-E045-0 2EN 1 - 1 CHAPTER 1 DEVICE OVERVIEW 1.1 Features 1.2 Device Specifications 1.3 Power Requirements 1.4 Environmental Specifications 1.5 Acoustic Noise 1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate 1.9 Media Defects Overview and features are described in this chapter, and specifications and power requirement are described. The MP[...]

C141-E045-0 2EN 1 - 2 (4) Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed. The average positioning time is 10 ms (at read). 1.1.2 Adaptability (1) Power save mode The power save mode feature for idle operation, stand by and sleep modes makes the disk drive ideal for[...]

C141-E045-0 2EN 1 - 3 (5) Error correction and retry by ECC If a recoverable error occurs, the disk drive itself attempts error recovery. The 18-byte ECC has improved buffer error correction for correctable data errors. (6) Write cache When the disk drive receives a write command, the disk drive posts the command completion at completion of transfe[...]

C141-E045-0 2EN 1 - 4 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specifications of the disk drive. Table 1.1 Specifications MPB3021AT MPB3032AT MPB3043AT MPB3052AT MPB3064AT Formatted Capacity (*1) 2162.76 MB 3243.66 MB 4325.52 MB 5249.66 MB 6488.29 MB Number of Heads 23456 Number of Cylinders (User + Alternate &[...]

C141-E045-0 2EN 1 - 5 1.2.2 Model and product number Table 1.2 lists the model names and product numbers. Table 1.2 Model names and product numbers Model Name Capacity (user area) Mounting Screw Order No. Others MPB3021AT 2162.76 No. 6-32UNC CA01630-B321 MPB3032AT 3243.66 No. 6-32UNC CA01630-B331 MPB3043AT 4325.52 No. 6-32UNC CA01630-B341 MPB3052AT[...]

C141-E04 5-02EN 1 - 6 Table 1.3 Current and power dissipation Typical RMS current (*1) [mA] +12 V +5 V Model MPB 3021AT MPB 3032AT MPB 3043AT MPB 3052AT MPB 3064AT All Models MPB 3021AT MPB 3032AT MPB 3043AT MPB 3052AT MPB 3064AT Spin up 1300 1500 peak 460 600 peak 17.9 Idle (Ready) (*3) 115 140 185 460 3.68 3.98 4.52 R/W (On Track) (*4) 125 150 20[...]

C141-E045-0 2EN 1 - 7 (4) Current fluctuation (Typ.) when power is turned on Note: Maximum current is 1.5 A and is continuance is 1.5 seconds Figure 1.1 Current fluctuation (Typ.) when power is turned on (5) Power on/off sequence The voltage detector circuit monitors +5 V and +12 V. The circuit does not allow a write signal if either voltage is abn[...]

C141-E045-0 2EN 1 - 8 1.4 Environmental Specifications Table 1.4 lists the environmental specifications. Table 1.4 Environmental specifications Temperature • Operating • Non-operating • Thermal Gradient 5°C to 55°C (ambient) 5°C to 60°C (disk enclosure surface) –40°C to 60°C 20°C/h or less Humidity • Operating • Non-operating •[...]

C141-E045-0 2EN 1 - 9 1.6 Shock and Vibration Table 1.6 lists the shock and vibration specification. Table 1.6 Shock and vibration speci fication Vibration (swept sine, one octave per minute) • Operating • Non-operating 5 to 300 Hz, 0.5G-0-peak (without non-recovered errors) 5 to 400 Hz, 4G-0-peak (no damage) Shock (half-sine pulse, 11 ms durat[...]

C141-E045-0 2EN 1 - 10 (4) Data assurance in the event of power failure Except for the data blo ck being written to, the data on the disk media is assured in the event of any power supply abnormalities. This does not include power supply abnormalities during disk media initialization (formatting) or processing of defects (alternative block assignme[...]

C141-E045-02EN 2 - 1 CHAPTER 2 DEVICE CONFIGURATION 2.1 Device Configuration 2.2 System Configuration 2.1 Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors actuators, and a circulating [...]

C141-E045-02EN 2 - 2 (1) Disk The outer diameter of the disk is 95 mm. The inner diameter is 25 mm. The number of disks used varies with the model, as described below. The disks are rated at over 40,000 start/stop operations. MPB3021AT : 1 disk MPB3032AT : 2 disks MPB3043AT : 2 disks MPB3052AT : 3 disks MPB3064AT : 3 disks (2) Head The heads are of[...]

C141-E045-02EN 2 - 3 Spindle 0 1 Actuator MPB3021 Model MPB3032AT Model Spindle 1 2 0 Actuator MPB3052AT Model Spindle 2 3 4 0 1 Actuator MPB3043AT Model Spindle 1 3 2 0 Actuator MPB3064AT Model Spindle 2 3 5 4 0 1 Actuator Figure 2.2 Configuration of disk media heads (3) Spindle motor The disks are rotated by a direct drive Hall-less DC mo tor. (4[...]

C141-E045-02EN 2 - 4 (5) Air circulation system The disk enclosure (DE) is sealed to preve nt dust and dirt from entering. The disk enclosure features a closed loop air circulation system that relies on the blower effect of the rotating disk. This system continuously circulates the air through the circulation filter to maintain the cleanliness of t[...]

C141-E045-02EN 2 - 5 2.2.3 2 drives connection ATA interface AT bus (Host interface) Disk drive #1 Disk drive #0 HA (Host adaptor) Host Note: When the drive that is not conformed to ATA is connected to the disk drive is above configuration, the operation is not guaranteed. Figure 2.4 2 drives configuration IMPORTANT HA (host adapter) consists of ad[...]

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C141-E045-0 2EN 3 - 1 CHAPTER 3 INSTALLATION CONDITIONS 3.1 Dimensions 3.2 Mounting 3.3 Cable Connections 3.4 Jumper Settings 3.1 Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm.[...]

C141-E045-0 2EN 3 - 2 Figure 3.1 Dimensions[...]

C141-E045-0 2EN 3 - 3 3.2 Mounting (1) Orientation Figure 3.2 illustrates the allowable orientations for the disk drive. The mounting angle can vary ±5° from the horizontal. (a) Horizontal mounting (b) Vertical mounting –1 (c) Vertical mounting –2 Figure 3.2 Orientation (2) Frame The disk enclosure (DE) body is connected to signal ground (SG)[...]

C141-E045-0 2EN 3 - 4 Figure 3.3 Limitation of side-mounting Figure 3.4 Mounting frame structure 5.0 or less 4.5 or less 2 B Frame of system cabinet Details of B Details of A Frame of system cabinet Screw Screw PCA DE 2.5 2.5 2.5 A DE Side surface mounting Bottom surface mounting Do not use this screw holes Use these screw holes[...]

C141-E045-0 2EN 3 - 5 (4) Ambient temperature The temperature conditions for a dis k drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. Pay attention to the air flow to prevent the DE surface temperature from exceeding 60°C. Provide air circulation in the cabinet such that the PCA side, in particular, [...]

C141-E045-0 2EN 3 - 6 (5) Service area Figure 3.6 shows how the drive must be accessed (service areas) during and after installation. Figure 3.6 Service area (6) External magnetic fields Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields. [P side] [...]

C141-E045-0 2EN 3 - 7 3.3 Cable Connections 3.3.1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.7 shows the locations of these connectors and terminals. • Power supply connector (CN1) • ATA interface connector (CN1) Figure 3.7 Connector locations ATA interface connector M[...]

C141-E045-0 2EN 3 - 8 3.3.2 Cable connector specifications Table 3.2 lists the recommended specifications for the cable connectors. Table 3.2 Cable connector specifications Name Model Manufacturer Cable socket (closed-end type) FCN-707B040-AU/B Fujitsu Cable socket (through-end type) FCN-707B040-AU/O Fujitsu Signal cable 445-248-40 SPECTERS STRIP C[...]

C141-E045-0 2EN 3 - 9 3.3.4 Power supply connector (CN1) Figure 3.9 shows the pin assignment of the power supply connector (CN1). (Viewed from cable side) 4 3 2 1 +5VDC +5V RETURN +12V RETURN +12VDC 4 3 2 1 Figure 3.9 Power supply connector pins (CN1) 3.4 Jumper Settings 3.4.1 Location of setting jumpers Figure 3.10 shows the location of the jumper[...]

C141-E045-0 2EN 3 - 10 3.4.2 Factory default setting Figure 3.11 shows the default setting position at the factory. (Master device setting) C04 A01 A02 C01 A39 A40 05 06 B01 B02 Figure 3.11 Factory default setting 3.4.3 Jumper configuration (1) Device type Master device (device #0) or slave device (device #1) is selected. 06 B02 05 B01 (a) Master d[...]

C141-E045-0 2EN 3 - 11 06 B02 CSEL connected to the interface Cable selection can be done by the special interface cable. B01 05 Figure 3.13 Jumper setting of Cable Select Figures 3.14 and 3.15 show examples of cable selection using unique interface cables. By connecting the CSEL of the master device to the CSEL Line (conductor) of the cable and co[...]

C141-E0 45-02EN 3 - 12 (3) Special setting 1 (SP1) The number of cylinders reported by the IDENTIFY DEVICE command is selected. (a) Default mode 2 4 6 1 3 5 2 4 6 Slave Device Master Device 1 3 5 2 4 6 1 3 5 Cable Select Model No. of cylinders No. of heads No. of sectors MPB3021AT 4,470 15 63 MPB3032AT 6,704 15 63 MPB3043AT 8,940 15 63 MPB3052AT 10[...]

C141-E045-0 2EN 4 - 1 CHAPTER 4 THEORY OF DEVICE OPERATION 4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration 4.4 Power-on sequence 4.5 Self-calibration 4.6 Read/Write Circuit 4.7 Servo Control This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo contro[...]

C141-E045-02EN 4 - 2 4.2.2 Head Figure 4.1 shows the read/write head structures. The MPB3021AT has 2 read/write heads, the MPB3032AT has 3, MPB3043AT has 4, MPB3052AT has 5, and MPB3064AT has 6. These heads are raised from the disk surface as the spindle motor approaches the rated rotation speed. Spindle 0 1 Actuator MPB3021 Model MPB3032AT Model S[...]

C141-E045-0 2EN 4 - 3 4.2.3 Spindle T he spindle consists of a disk stack assembly and spindle motor. The disk stack assembly is activated by the direct drive sensor-less DC spindle motor, which has a speed of 5,400 rpm ±0.5%. The spindle is controlled with detecting a PHASE signal generated by counter electromotive voltage of the spindle motor at[...]

C141-E045-0 2EN 4 - 4 4.3 Circuit Configuration Figure 4.2 shows the disk drive circuit configuration. (1) Read/write circuit The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) an d read channel (RDC). The PreAMP consists of the write current switch circuit, that flows the write current to the head coil, and the voltage a[...]

C141-E045-0 2EN 4 - 5 Figure 4.2 MPB30xxAT Block diagram[...]

C141-E045-0 2EN 4 - 6 4.4 Power-on Sequence Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below. a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk d[...]

C141-E045-0 2EN 4 - 7 c) b) a) Release heads from actuator lock Confirming spindle motor speed Self-diagnosis 2 • Data buffer write/read test The spindle motor starts. Self-diagnosis 1 • MPU bus test • Inner register write/read test • Work RAM write/read test Start Power on Drive ready state (command waiting state) Execute self-calibration [...]

C141-E045-0 2EN 4 - 8 4.5 Self-calibration The disk drive occasionally performs self-calibration in order t o sense and calibrate mechanical external forces on the actuator, and VCM torque. This enables precise seek and read/write operations. 4.5.1 Self-calibration contents (1) Sensing and compensating for external forces The actuator suffers from [...]

C141-E045-0 2EN 4 - 9 4.5.2 Execution timing of self-calibration Self-calibration is exec uted when: • The power is turned on. • The disk drive receives the RECALIBRATE command from the host. • The self-calibration execution timechart of the disk drive specifies self-calibration. The disk drive performs self-calibration according to the timec[...]

C141-E045-0 2EN 4 - 10 4.6 Read/write Circuit The r ead/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read circuit, and the time base generator in the read channel (RDC). Figure 4.4 is a block diagram of the read/write circuit. 4.6.1 Read/write preamplifier (PreAMP) One PreAMP is mounted on the FPC. The PreA[...]

C141-E045-0 2EN 4 - 11 Figure 4.4 Read/write circuit block diagram[...]

C141-E045-0 2EN 4 - 12 4.6.3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the adaptive equalizer circuit. This clock signal is converted into the NRZ data by the 8/9 GCR decoder circuit [...]

C141-E045-0 2EN 4 - 13 Figure 4.6 PR4 signal transfer[...]

C141-E045-0 2EN 4 - 14 (4) Viterbi detection circuit The sample hold waveform output from the adaptive equalizer circuit is sent to the Viterbi detection circuit. The Viterbi detection circuit demodulates data according to the survivor path sequence. (5) Data separator circuit The data separator circuit generates clocks in synchronization with the [...]

C141-E045-0 2EN 4 - 15 Table 4.3 Write clock frequency and transfer rate of each zone Zone 0 1 2 3 4 5 6 7 Cylinder 0 to 660 661 to 1197 1198 to 1938 1939 to 2672 2673 to 3332 3333 to 3958 3959 to 4747 4748 to 5216 Transfer rate [MB/s] 16.71 16.35 15.82 15.18 14.68 14.15 13.44 13.06 Zone 8 9 10 11 12 13 Cylinder 5217 to 5886 5887 to 6505 6506 to 70[...]

C141-E045-0 2EN 4 - 16 4.7.1 Servo control circuit Figure 4.7 is the block diagram of the servo control circuit. The following describes the functions of the blocks: (5) (1) (2) (3) (4) P. Amp. CSR: Current Sense Resistor VCM: Voice Coil Motor Spindle motor control DSP unit Servo burst capture SVC MPU CSR Driver DAC ADC Position Sense Head VCM curr[...]

C141-E045-0 2EN 4 - 17 c. Seek to specified cylinder Drives the VCM to position the head to the specified cylinder. d. Calibration Senses and stores the thermal offset between heads and the mechanical forces on the actuator, and stores the calibration value. Figure 4.8 Physical sector servo configuration on disk surface[...]

C141-E045-0 2EN 4 - 18 (2) Servo burst capture circuit The four servo signals can be synchronously detected by the STROB signal, full-wave rectified integrated. (3) A/D converter (ADC) The A/D converter (ADC) receives the servo signals are integrated, converts them to digital, and transfers the digital signal to the DSP unit. (4) D/A converter (DAC[...]

C141-E045-0 2EN 4 - 19 4.7.2 Data-surface servo format Figure 4.8 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.8 are described below. (1) Inner guard band The head is in contact with the disk in this space when the spindle starts turning or stops, and the rotational speed of the spindle can b[...]

C141-E045-0 2EN 4 - 20 (1) Write/read recovery This area is used to absorb the write/read transient and to stabilize the AGC. (2) Servo mark This area generates a timing for demodulating the gray code and position-demodulating the servo A to D by detecting the servo mark. (3) Gray code (including index bit) This area is used as cylinder address. Th[...]

C141-E045-0 2EN 4 - 21 d) If the head is stopped at the reference cylinder from there. Track following control starts. (2) Seek operation Upon a data read/write request from the host, the MPU confirms the necessity of access to the disk. If a read or instruction is issued, the MPU seeks the desired track. The MPU feeds the VCM current via the D/A c[...]

C141-E045-0 2EN 4 - 22 e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a specific period, the MPU resets the SVC and starts from the beginning. When a PHASE signal is sent, the SVC enters the acceleration mode. (2) Acceleration mode In this mode, the MPU stops to send the phase switching signal to the SVC. The SVC starts [...]

C141-E045-02EN 5 - 1 CHAPTER 5 INTERFACE 5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands 5.4 Command Protocol 5.5 Ultra DMA feature Set 5.6 Timing[...]

C141-E045-02EN 5 - 2 5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals. INTRQ : INTERRUPT REQUEST IOCS16-: IOCS 16 PDIAG- : PASSED DIAGNOSTIC IORDY : I/O CHANNEL READY DASP- : DEVICE ACTIVE/DEVICE 1 PRESENT DIOW-: I/O WRITE DIOR- : I/O READ DMARQ: DMA REQUEST DMACK-: DMA ACKNOWLEDGE IDD Host DD(15:0) DATA BUS DA [...]

C141-E045-02EN 5 - 3 5.1.2 Signal assignment on the connector Table 5.1 shows the signal assignment on the interface connector. Table 5.1 Signal assignment on the interface connector Pin No. Signal Pin No. Signal 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 RESET– DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND DMARQ DIOW–, STOP D[...]

C141-E045-02EN 5 - 4 [signal] [I/O] [Description] DIOR–, HDMARDY–, HSTROBE I DIOR– is the strobe signal asserted by the host to read device registers or the data port. HDMARDY– is a flow control signal for Ultra DMA data in bursts. This signal is asserted by the host to indicate to the device that the host is ready to receive Ultra DMA data[...]

C141-E045-02EN 5 - 5 [signal] [I/O] [Description] IORDY, DDMARDY–, DSTROBE O This signal is negated to extend the host transfer cycle of any host register access (Read or Write) when the device is not ready to respond to a data transfer request. DDMARDY– is a flow control signal for Ultra DMA data out bursts. This signal is asserted by the devi[...]

C141-E045-02EN 5 - 6 5.2 Logical Interface The device can operate for command execution in either address-specified mode; cylinder - head-sector (CHS) or Logical block address (LBA) mode. The IDENTIFY DEVICE information indicates whether the device supports the LBA mode. When the host system specifies the LBA mode by setting bit 6 in the Device/Hea[...]

C141-E045-02EN 5 - 7 Table 5.2 I/O registers I/O registers Read operation Write operation Command block registers 1000 0 Data Data X'1F0' 1000 1 Error Register Features X'1F1' 1001 0 Sector Count Sector Count X'1F2' 1001 1 Sector Number Sector Number X'1F3' 1010 0 Cylinder Low Cylinder Low X'1F4' 10[...]

C141-E045-02EN 5 - 8 5.2.2 Command block registers (1) Data register (X'1F0') The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or LBA mode. (2) Error register (X'1F1') The Error register indicates the status of the command executed by the device. The[...]

C141-E045-02EN 5 - 9 [Diagnostic code] X'01': No Error Detected. X'03': Data Buffer Compare Error. X'05': ROM Sum Check Error. X'80': Device 1 (slave device) Failed. Error register of the master device is valid under two devices (master and slave) configuration. If the slave device fails, the master device po[...]

C141-E045-02EN 5 - 10 (6) Cylinder Low register (X'1F4') The contents of this register indicates low-order 8 bits of the starting cylinder address for any disk-access. At the end of a command, the contents of this register are updated to the current cylinder number. Under the LBA mode, this register indicates LBA bits 15 to 8. (7) Cylinde[...]

C141-E045-02EN 5 - 11 (9) Status register (X'1F7') The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are [...]

C141-E045-02EN 5 - 12 - Bit 3: Data Request (DRQ) bit. This bit indicates that the device is ready to transfer data of word unit or byte unit between the host system and the device. - Bit 2: Always 0. - Bit 1: Always 0. - Bit 0: Error (ERR) bit. This bit indicates that an error was detected while the previous command was being executed. The Error r[...]

C141-E045-02EN 5 - 13 5.2.3 Control block registers (1) Alternate Status register (X'3F6') The Alternate Status register contains the same information as the Status register of the command block register. The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is n[...]

C141-E045-02EN 5 - 14 5.3.1 Command code and parameters Table 5.3 lists the supported co mmands, command code and the registers that needed parameters are written. Table 5.3 Command code and parameters (1 of 2) Command code (Bit) Parameters used 7654 3210 FR SC SN CY DH READ SECTOR(S) 0010 000 R N Y Y Y Y READ MULTIPLE 1100 0100 N Y Y Y Y READ DMA [...]

C141-E045-02EN 5 - 15 Table 5.3 Command code and parameters (2 of 2) Command code (Bit) Parameters used 7654 3210 FR SC SN CY DH STANDBY IMMEDIATE 1 1 0 1 0 1 1 0 0 0 1 0 0 0 0 0 N N N N D SLEEP 1 1 0 1 0 1 1 0 1 0 0 1 0 1 1 0 N N N N D CHECK POWER MODE 1 1 0 1 0 1 1 0 1 0 0 1 0 0 0 1 N N N N D SMART 1011 0000 Y Y Y Y D FLUSH CACHE 1110 0111 N N N [...]

C141-E045-02EN 5 - 16 5.3.2 Command descriptions The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command completion are shown as following in this subsection. Example: READ SECTOR(S) WITH RETRY At command issuance (I/O registers setting contents) Bit 76543210 1F7 H (CM) 0010[...]

C141-E045-02EN 5 - 17 Note: 1. When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB (most significant bit) and bits of the SN register are the LSB (least significant bit). 2. At error occurrence, the SC register indicates the rema[...]

C141-E045-02EN 5 - 18 At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) × L × DV End head No. /LBA [MSB] 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (ER) End cylinder No. [MSB] / LBA End cylinder No. [LSB] / LBA End sector No. / LBA [LSB] 00 (*1) Error information *1 If the command is termina[...]

C141-E045-02EN 5 - 19 Figure 5.2 shows an example of the execution of the READ MULTIPLE command. • Block count specified by SET MULTIPLE MODE command = 4 (number of sectors in a block ) • READ MULTIPLE command specifies; Number of requested sectors = 9 (Sector Count register = 9) ↓ Number of sectors in incomplete block = remainder of 9/4 =1 S[...]

C141-E045-02EN 5 - 20 Note: If the command is terminated due to an error, the remaining number of sectors for which data was not transferred is set in this register. (3) READ DMA (X'C8' or X'C9') This command operates similarly to the READ SECTOR(S) command except for following events. • The data transfer starts at the timing [...]

C141-E045-02EN 5 - 21 At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) × L × DV End head No. /LBA [MSB] 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (ER) End cylinder No. [MSB] / LBA End cylinder No. [LSB] / LBA End sector No. / LBA [LSB] 00 (*1) Error information *1 If the command is termina[...]

C141-E045-02EN 5 - 22 At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) × L × DV End head No. /LBA [MSB] 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (ER) End cylinder No. [MSB] / LBA End cylinder No. [LSB] / LBA End sector No. / LBA [LSB] 00 (*1) Error information *1 If the command is termina[...]

C141-E045-02EN 5 - 23 At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) × L × DV End head No. /LBA [MSB] 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (ER) End cylinder No. [MSB] / LBA End cylinder No. [LSB] / LBA End sector No. / LBA [LSB] 00 (*1) Error information *1 If the command is termina[...]

C141-E045-02EN 5 - 24 The contents of the command block registers related to addresses after the transfer of a data block containing an erred sector are undefined. To obtain a valid error information, the host should retry data transfer as an individual requests. At command issuance (I/O registers setting contents) 1F7 H (CM) 11000101 1F6 H (DH) ×[...]

C141-E045-02EN 5 - 25 1) Single word DMA transfer mode 2: Sets the FR register = X'03' and SC register = X'12' by the SET FEATURES command 2) Multiword DMA transfer mode 2: Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES command 3) Ultra DMA transfer mode 2: Sets the FR register = X&a[...]

C141-E045-02EN 5 - 26 At command issuance (I/O registers setting contents) 1F7 H (CM) 00111100 1F6 H (DH) × L × DV Start head No. /LBA [MSB] 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (FR) Start cylinder No. [MSB] / LBA Start cylinder No. [LSB] / LBA Start sector No. / LBA [LSB] Transfer sector count xx R = 0 → with Retry R = 1 → witho[...]

C141-E045-02EN 5 - 27 At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) ××× DV xx 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (ER) xx xx xx xx Error information (10) SEEK (X'7x', x : X'0' to X'F') This command performs a seek operation to the track and selects t[...]

C141-E045-02EN 5 - 28 (11) INITIALIZE DEVICE PARAMETERS (X'91') The host system can set the number of sectors per track and the maximum head number (maximum head number is "number of heads minus 1") per cylinder with this command. Upon receipt of this command, the device sets the BSY bit of Status register and saves the paramete[...]

C141-E045-02EN 5 - 29 At command issuance (I/O registers setting contents) 1F7 H (CM) 11101100 1F6 H (DH) ××× DV xx 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (FR) xx xx xx xx xx At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) ××× DV xx 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H[...]

C141-E045-02EN 5 - 30 Table 5.4 Information to be read by IDENTIFY DEVICE command (1 of 3) Word Value Description 0 X‘0C5A’ General Configuration *1 1 X‘1176’ X‘1A30’ X‘22EC’ X‘2A62’ X‘3462’ Number of cylinders MPB3021AT : X‘1176’ MPB3032AT : X‘1A30’ MPB3043AT : X‘22EC’ MPB3052AT : X‘2A62’ MPB3064AT : X‘346[...]

C141-E045-02EN 5 - 31 Table 5.4 Information to be read by IDENTIFY DEVICE command (2 of 3) Word Value Description 89-127 X‘00’ Reserved 128 X‘00’ Security status not supported 129-159 X‘00’ Reserved 160-255 X‘00’ Reserved *1 Word 0: General configuration Bit 15: 0 = ATA device 0 Bit 14-8: Vendor specific 0 Bit 7: 1 = Removable media[...]

C141-E045-02EN 5 - 32 Table 5.4 Information to be read by IDENTIFY DEVICE command (3 of 3) *8 Word 59: Transfer sector count currently set by READ/WRITE MULTIPLE command Bit 15-9: Reserved Bit 8: Multiple sector transfer 1=Enable Bit 7-0: Transfer sector count currently set by READ/WRITE MULTIPLE without interrupt supports 2, 4, 8, 16 and 32 sector[...]

C141-E045-02EN 5 - 33 (13) IDENTIFY DEVICE DMA (X'EE') When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command. At command issuance (I/O registers setting contents) 1F7 H (CM) 11101110 1F6 H (DH) ××× DV xx 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1[...]

C141-E045-02EN 5 - 34 Table 5.5 Features register values and settable modes Features Register Drive operation mode X‘02’ Enables the write cache function. X‘03’ Specifies the transfer mode. Supports PIO mode 4, single word DMA mode 2, and multiword DMA mode regardless of Sector Count register contents. X‘55’ Disables read cache function[...]

C141-E045-02EN 5 - 35 The host sets X'03' to the Features register. By issuing this command with setting a value to the Sector Count register, the transfer mode can be selected. Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value. However, the IDD can operate with the PIO tr[...]

C141-E045-02EN 5 - 36 At command issuance (I/O registers setting contents) 1F7 H (CM) 11000110 1F6 H (DH) ××× DV xx 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (FR) xx xx xx Sector count/block xx At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) ××× DV xx 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) [...]

C141-E045-02EN 5 - 37 (16) EXECUTE DEVICE DIAGNOSTIC (X'90') This command performs an internal diagnostic test (self-diagnosis) of the device. This command usually sets the DRV bit of the Drive/Head register is to 0 (however, the DV bit is not checked). If two devices are present, both devices execute self-diagnosis. If device 1 is presen[...]

C141-E045-02EN 5 - 38 At command issuance (I/O registers setting contents) 1F7 H (CM) 10010000 1F6 H (DH) ××× DV xx 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (FR) xx xx xx xx xx At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) ××× DV xx 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H[...]

C141-E045-02EN 5 - 39 At command issuance (I/O registers setting contents) 1F7 H (CM) 0010001 R 1F6 H (DH) × L × DV Head No. /LBA [MSB] 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (FR) Cylinder No. [MSB] / LBA Cylinder No. [LSB] / LBA Sector No. / LBA [LSB] Number of sectors to be transferred xx R = 0 → with Retry R = 1 → without Retry [...]

C141-E045-02EN 5 - 40 At command issuance (I/O registers setting contents) 1F7 H (CM) 0011001 R 1F6 H (DH) × L × DV Head No. /LBA [MSB] 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (FR) Cylinder No. [MSB] / LBA Cylinder No. [LSB] / LBA Sector No. / LBA [LSB] Number of sectors to be transferred xx R = 0 → with Retry R = 1 → without Retry [...]

C141-E045-02EN 5 - 41 At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) ××× DV xx 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (ER) xx xx xx xx Error information (21) WRITE BUFFER (X'E8') The host system can overwrite the contents of the sector buffer of the device with a desired da[...]

C141-E045-02EN 5 - 42 (22) IDLE (X'97' or X'E3') Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates an interrupt even if the device has not fully entered the idle mode. If the spindle of [...]

C141-E045-02EN 5 - 43 At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) ××× DV xx 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (ER) xx xx xx xx Error information (23) IDLE IMMEDIATE (X'95' or X'E1') Upon receipt of this command, the device sets the BSY bit of the Status re[...]

C141-E045-02EN 5 - 44 (24) STANDBY (X'96' or X'E2') Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the standby mode. If the devic[...]

C141-E045-02EN 5 - 45 At command issuance (I/O registers setting contents) 1F7 H (CM) X'94' or X'E0' 1F6 H (DH) ××× DV xx 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (FR) xx xx xx xx xx At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) ××× DV xx 1F5 H (CH) 1F4 H (CL) 1[...]

C141-E045-02EN 5 - 46 At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) ××× DV xx 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (ER) xx xx xx xx Error information (27) CHECK POWER MODE (X'98' or X'E5') The host checks the power mode of the device with this command. The host[...]

C141-E045-02EN 5 - 47 At command issuance (I/O registers setting contents) 1F7 H (CM) X'98' or X'E5' 1F6 H (DH) ××× DV xx 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (FR) xx xx xx xx xx At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH) ××× DV xx 1F5 H (CH) 1F4 H (CL) 1[...]

C141-E045-02EN 5 - 48 Table 5.7 Features Register values (subcommands) and functions Features Resister Function X’D0’ SMART Read Attribute Values: A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512- byte attribute value information to the ho[...]

C141-E045-02EN 5 - 49 The host can predict failures in the device by periodically issuing the SMART Return Status subcommand (FR register = DAh) to reference the CL and CH registers. If an attribute value is below the insurance failure threshold value, the device is about to fail or the device is nearing the end of it life . In this case, the host [...]

C141-E045-02EN 5 - 50 The attribute value information is 512-byte data; the format of this data is shown below. The host can access this data using the SMART Read Attribute Values subcommand (FR register = D0h). The insurance failure threshold value data is 512-byte data; the format of this data is shown below. The host can access this data using t[...]

C141-E045-02EN 5 - 51 Table 5.9 Format of insurance failure threshold value data Byte Item 00 01 Data format version number 02 Attribute 1 Attribute ID 03 Insurance failure threshold 04 to 0D Threshold 1 (Threshold of attribute 1) Reserved 0E to 169 Threshold 2 to threshold 30 (The format of each threshold value is the same as that of bytes 02 to 0[...]

C141-E045-02EN 5 - 52 • Attribute ID The attribute ID is defined as follows: Attribute ID Attribute name 0 (Indicates unused attribute data.) 1 Read error rate 2 Throughput performance 3 Spin up time 4 Number of times the spindle motor is activated 5 Number of alternative sectors 7 Seek error rate 8 Seek time performance 9 Power-on time 10 Number[...]

C141-E045-02EN 5 - 53 • Raw attribute value Raw attributes data is retained. • Failure prediction capability flag Bit 0: The attribute value data is saved to a medium before the device enters power saving mode. Bit 1: The device automatically saves the attribute value data to a medium after the previously set operation . Bits 2 to 15: Reserved [...]

C141-E045-02EN 5 - 54 (29) FLUSH CACHE (X ‘E7’) This command is use by the host to request the device to flush the write cache. If the write cache is to be flushed, all data cached shall be written to the media. The BSY bit shall remain set to one until all data has been successfully written or an error occurs. The device should use all error r[...]

C141-E045-02EN 5 - 55 5.3.3 Error posting Table 5.10 lists the defined errors that are valid for each command. Table 5.10 Command code and parameters Command name Error register (X'1F1') Status register (X'1F7') ICRC UNC INDF ABRT TR0NF DRDY DWF ERR READ SECTOR(S) V V V V V V WRITE SECTOR(S) V V V V V READ MULTIPLE V V V V V V W[...]

C141-E045-02EN 5 - 56 5.4 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0. Commands can be executed only when the DRDY bit of the Status register is 1. However, the following command[...]

C141-E045-02EN 5 - 57 Status read Status read *1 When the IDD receives a command that hits the cache data during read-ahead, and transfers data from the buffer without reading from the disk medium. 255 2 1 0 Word IOCS16- IOR- Data Data Reg. Selection INTRQ DRQ Min. 30 µ s (*1) Expanded Command f d d e e c b a Command BSY INTRQ DRDY ~ Parameter wri[...]

C141-E045-02EN 5 - 58 Note: For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 50 µ s after the completion of the sector data transfer. Note that the host does not need to rea[...]

C141-E045-02EN 5 - 59 c) When the device is ready to receive the data of the first sector, the device sets DRQ bit and clears BSY bit. d) The host writes one sector of data through the Data register. e) The device clears the DRQ bit and sets the BSY bit. f) When the drive completes transferring the data of the sector, the device clears BSY bit and [...]

C141-E045-02EN 5 - 60 Note: For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 50 µ s after the completion of the sector data transfer. Note that the host does not need to rea[...]

C141-E045-02EN 5 - 61 5.4.4 Other commands • READ MULTIPLE • SLEEP • WRITE MULTIPLE See the description of each command. 5.4.5 DMA data transfer commands • READ DMA • WRITE DMA Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding[...]

C141-E045-02EN 5 - 62 Status read 255 2 1 0 Word IOR- or IOW- DMACK- DMARQ DRQ Expanded [Single Word DMA transfer] Command BSY INTRQ DRDY ~ Parameter write DRQ Data transfer • • • • • • • • • • • • • • • • • • • • DRQ [Multiword DMA transfer] • • • • DMACK- DMARQ • • • • IOR- or IOW- • • ?[...]

C141-E045-02EN 5 - 63 5.5 Ultra DMA feature set 5.5.1 Overview Ultra D MA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. When this protoc[...]

C141-E045-02EN 5 - 64 5.5.2 Phases of operation An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts. Each Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and the Ultra DMA burst termination phase. In addition, an Ultra DMA burst may be paused dur[...]

C141-E045-02EN 5 - 65 11) The device shall drive the first word of the data transfer onto DD (15:0). This step may occur when the device first drives DD (15:0) in step (10). 12) To transfer the first word of data the devi ce shall negate DSTROBE within t FS after the host has negated STOP and asserted HDMARDY-. The device shall negate DSTROBE no so[...]

C141-E045-02EN 5 - 66 3) The device shall stop generating DSTROBE edges within t RFS of the host negating HDMARDY-. 4) If the host negates HDMARDY- within t SR after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than t SR after the device h[...]

C141-E045-02EN 5 - 67 10) The devic e shall latch the host's CRC data from DD (15:0) on the negating edge of DMACK-. 11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command the de[...]

C141-E045-02EN 5 - 68 10) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (9), the host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5). 11) The host shall negate DMACK- no sooner than t MLI after the device has asserted DSTROBE and negated DMARQ and the host has [...]

C141-E045-02EN 5 - 69 9) The device shall assert DDMARDY- within t LI after the host has negated STOP. After asserting DMARQ and DDMARDY- the device shall not negate either signal until after the first negation of HSTROBE by the host. 10) The host shall drive the first word of the data transfer onto DD (15:0). This step may occur any time during Ul[...]

C141-E045-02EN 5 - 70 b) Device pausing an Ultra DMA data out burst 1) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred. 2) The device shall pause an Ultra DMA burst by negating DDMARDY-. 3) The host shall stop generating HSTROBE edges within t RFS of the device negating DDMARDY-.[...]

C141-E045-02EN 5 - 71 9) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5). 10) The device shall release DDMARDY- w[...]

C141-E045-02EN 5 - 72 11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5). 12) The device shall release DDMARDY- [...]

C141-E045-02EN 5 - 73 I) The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1. Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynominal where DD0 [...]

C141-E045-02EN 5 - 74 5.6 Timing 5.6.1 PIO data transfer Figure 5.9 shows of the data transfer timing between the device and the host system.[...]

C141-E045-02EN 5 - 75 t8 t6 t12 t11 t10 t7 t5 t4 t3 t9 t2i t2 t1 t0 Addresses IORDY IOCS16- Read data DD0-DD15 Write data DD0-DD15 DIOR-/DIOW- Symbol Timing parameter Min. Max. Unit t0 Cycle time 120 — ns t1 Data register selection setup time for DIOR-/DIOW- 25 — ns t2 Pulse width of DIOR-/DIOW- 70 — ns t2i Recovery time of DIOR-/DIOW- 25 —[...]

C141-E045-02EN 5 - 76 5.6.2 Single word DMA data transfer Figure 5.10 show the single word DMA data transfer timing between the device and the host system. tF tE tH tG tJ tD tI tC t0 Read data DD0-DD15 Write data DD0-DD15 DIOR-/DIOW- DMACK- DMARQ Symbol Timing parameter Min. Max. Unit t0 Cycle time 240 — ns tC Delay time from DMACK assertion to D[...]

C141-E045-02EN 5 - 77 5.6.3 Multiword data transfer Figure 5.11 shows the multiword DMA data transfer timing between the device and the host system. tF tE tH tG tJ tD tI tC t0 Read data DD0-DD15 Write data DD0-DD15 DIOR-/DIOW- DMACK- DMARQ tK Symbol Timing parameter Min. Max. Unit t0 Cycle time 120 — ns tC Delay time from DMACK assertion to DMARQ[...]

C141-E045-02EN 5 - 78 5.6.4 Ultra DMA data transfer Figures 5.12 through 5.21 define the timings associated with all phases of Ultra DMA bursts. Table 5.12 con tains the values for the timings for each of the Ultra DMA Modes. 5.6.4.1 Initiating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. N[...]

C141-E045-02EN 5 - 79 5.6.4.2 Ultra DMA data burst timing requirements Table 5.12 Ultra DMA data burst timing requirements (1 of 2) NAM E MODE 0 (in ns) MODE 1 (in ns) MODE 2 (in ns) COMMENT MIN MAX MIN MAX MIN MAX t CYC 114 75 55 Cycle time (from STROBE edge to STROBE edge) t2 CYC 235 156 117 Two cycle time (from rising edge to next rising edge or[...]

C141-E045-02EN 5 - 80 Table 5.12 Ultra DMA data burst timing requ irements (2 of 2) NAM E MODE 0 (in ns) MODE 1 (in ns) MODE 2 (in ns) COMMENT MIN MAX MIN MAX MIN MAX t IORDYZ 20 20 20 Pull-up time before allowing IORDY to be released t ZIORDY 000 Minimum time device shall wait before driving IORDY t ACK 20 20 20 Setup and hold times for DMACK- (be[...]

C141-E045-02EN 5 - 81 5.6.4.3 Sustained Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the hos[...]

C141-E045-02EN 5 - 82 5.6.4.4 Host pausing an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: 1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than t RP after HDMARDY- is negated. 2) If the t SR timing is not satisfied, the host may receive zero, one or t[...]

C141-E045-02EN 5 - 83 5.6.4.5 Device terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.15 Device terminating an Ultra DMA data in burst[...]

C141-E045-02EN 5 - 84 5.6.4.6 Host terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.16 Host terminating an Ultra DMA data in burst[...]

C141-E045-02EN 5 - 85 5.6.4.7 Initiating an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Figure 5.17 Initiating an Ultra DMA data out burst[...]

C141-E045-02EN 5 - 86 5.6.4.8 Sustained Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable a[...]

C141-E045-02EN 5 - 87 5.6.4.9 Device pausing an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of th e Ultra DMA Modes. Notes: 1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t RP after DDMARDY- is negated. 2) If the t SR timing is not satisfied, the device may receive zero,[...]

C141-E045-02EN 5 - 88 5.6.4.10 Host terminating an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTRO BE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.20 Host terminating an Ultra DMA data out burst[...]

C141-E045-02EN 5 - 89 5.6.4.11 Device terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.21 Device terminating an Ultra DMA data out burst[...]

C141-E045-02EN 5 - 90 5.6.5 Power-on and reset Figure 5.22 shows power-on and reset (hardware and software reset) timing. (1) Only master device is present *1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset. Clear Reset *1 tP tN tM BSY DASP- Power-on RESET- Software reset (2) Master and slave devices are present ([...]

C141-E045-0 2EN 6 - 1 CHAPTER 6 OPERATIONS 6.1 Device Response to the Reset 6.2 Address Translation 6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache 6.6 Write Cache 6.1 Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when th e power of the IDD is turned on or the IDD receives a reset or diagnos[...]

C141-E045-0 2EN 6 - 2 6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1). The master device recognizes presence of the slave device when it confirms assertion of the DASP- signal. Then, the[...]

C141-E045-0 2EN 6 - 3 6.1.2 Response to hardware reset Response to RESET- (hardware reset through the interface) is similar to the power-on reset. Upon receipt of hardware reset, the master device checks a DASP- signal for up to 450 ms to confirm presence of a slave device. The master device recognizes the presence of the slave device when it confi[...]

C141-E045-0 2EN 6 - 4 6.1.3 Resp onse to software reset The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 31 seconds to see if the slave device has completed the self-diagnosis successfully. After the slave device receives the software reset, th[...]

C141-E045-0 2EN 6 - 5 6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAG- signal for up to 6 seconds to see if the slave device has completed the self-diagnosis successfully. The master device does not check the DASP- signal. A[...]

C141-E045-0 2EN 6 - 6 6.2 Address Translation When the IDD receives any command which involves access to the disk medium, the IDD always implements the address translation from the logical address (a host-specified address) to the physical address (logical to physical address translation). Following subsections explains the CHS translation mode. 6.[...]

C141-E045-0 2EN 6 - 7 6.2.2 Logical address (1) CHS mode Logical address assignment starts from physical cylinder (PC) 0, physical head (PH) 0, and physical sector (PS) 1 and is assigned by calculating the number of sectors per track which is specified by the INITIALIZE DEVICE PARAMETERS command. The head address is advanced at the subsequent secto[...]

C141-E045-0 2EN 6 - 8 (2) LBA mode Logical address assignment in the LBA mode starts from physical cylinder 0, physical head 0, and physical sector 1. The logical address is advanced at the subsequent sector from the last sector of the current track. The first physical sector of the subsequent physical track is the consecutive logical sector from t[...]

C141-E045-0 2EN 6 - 9 Regardless of whether the power down is enabled, the device enters the idle mode. The device also enters the idle mode in the same way after power-on sequence is completed. (1) Active mode In this mode, all the electric circuit in the device are active or the device is under seek, read or write operation. A device e nters the [...]

C141-E045-0 2EN 6 - 10 • STANDBY command • STANDBY IMMEDIATE command • INITIALIZE DEVICE PARAMETERS command • CHECK POWER MODE command (4) Sleep mode The power consumption of the drive is minimal in this mode. The drive enters only the standby mode from the sleep mode. The only method to return from the standby mode is to execute a software[...]

C141-E045-0 2EN 6 - 11 6.4.1 Spare area Following two types of spare area are provided for every physical head. 1) Spare cylinder for sector slip: used for alternating defective sectors at formatting in shipment (11 cylinders/head) 2) Spare cylinder for alternative assignment: used for alternative assignment by automatic alternative assignment. (4 [...]

C141-E045-0 2EN 6 - 12 (2) Alternate cylinder assignment A defective sector is assigned to the spare sector in the alternate cylinder. This processing is performed when the automatic alternate processing is performed. Figure 6.8 shows an example where (physical) sector 5 is detective on head 0 in cylinder 0. 5 7 6 4 3 1 300 299 2 Index Cylinder 0 H[...]

C141-E045-0 2EN 6 - 13 (3) Automatic alternate assignment The device performs the automatic assignment at following case. 1) When ECC correction performance is increased during read erro r retry, a read error is recovered. Before automatic alternate assignment, the device performs rewriting the corrected data to the erred sector and rereading. If n[...]

C141-E045-0 2EN 6 - 14 6.5.2 Caching operation Caching operation is performed only at issuance of the following commands. The device transfers data from the data buffer to the host system at issuance of following command if following data exist in the data buffer. • All sectors to be processed by the command • A part of data including load sect[...]

C141-E045-0 2EN 6 - 15 (3) Invalidating caching data Caching data in the data buffer is invalidated in the following case. 1) Following command is issued to the same data block as caching data. • WRITE SECTOR(S) • WRITE DMA • WRITE MULTIPLE 2) Command other than following commands is issued (all caching data are invalida ted) • READ SECTOR [...]

C141-E045-0 2EN 6 - 16 1) Sets the host address pointer (HAP) and the disk address pointer (DAP) to the lead of segment. Segment only for read DAP HAP 2) Transfers the requested data that already read to the host system with reading the requested data from the disk media. Read-requested data Stores the read-requested data upto this point Empty area[...]

C141-E045-0 2EN 6 - 17 (3) Sequential read When the disk drive receives the read command that targets the sequential address to the previous read command, the disk drive starts the read-ahead operation. a. Sequential command just after non-sequential command When the previously executed read command is an non-sequential command and the la st sector[...]

C141-E045-0 2EN 6 - 18 4) The disk drive performs the read-ahead operation for all area of segment with overwriting the requested data. Finally, the cache data in the buffer is as follows. Start LBA Last LBA DAP HAP Read-ahead data b. Sequential hit When the previously exe cuted read command is the sequential command and the last sector address of [...]

C141-E045-0 2EN 6 - 19 3) After completion of data transfer of hit data, the disk drive performs the read-ahead operation for the data area of which the disk drive transferred hit data. Read-ahead data 4) Finally, the cache data in the buffer is as follows. Read-ahead data c. Non-sequential read command just after sequential read command When non-s[...]

C141-E045-0 2EN 6 - 20 1) In the case that the contents of the data buffer is as follows for example and the previous command is a sequential read command, the disk drive sets the HAP to the address of which the hit data is stored. HAP (set to hit position for data transfer) Last position at previous read command Last position at previous read comm[...]

C141-E045-0 2EN 6 - 21 1) The disk drive sets the HAP to the address where the partially hit data is stored, and sets the DAP to the address just after the partially hit data. HAP DAP Partially hit data Lack data 2) The disk drive starts transferring partially hit data and reads lack data from the disk media at the same time. However, the disk driv[...]

C14 1-E045-02EN 6 - 22 6.6 Write Cache The write cache function of the drive makes a high speed processing in the case that data to be written by a write command is logically sequent the data of previous command and random write operation is performed. When the drive receives a write command, the drive starts transferring data of sectors requested [...]

C141-E045-0 2EN 6 - 23 At the time that the drive has stopped the command execution after the error recovery has failed, the write cache function is disabled automatically. The releasing the disable state can be done by the SET FEATURES command. When the power of the drive is turned on after the power is turned off once, the status of the write cac[...]

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