IBM DS-2000 инструкция обслуживания

WARRANTY INFORMATION Qua Tech Inc. warrants the DS-200 0 to b e free of defects for one (1 ) year from the date o f purchase. Qua Tech Inc. will repair or replace any board that fails to perform under normal operating condition s and in accordance with the procedures outlined in thi s document during the warranty period. Any damage tha t results fr[...]

TABLE OF CONTENTS WARRANTY INFORMATION . . . . . . . . . . . . i LIST OF FIGURES . . . . . . . . . . . . . ii i I. INTRODUCTION . . . . . . . . . . . . . . . . 1 II. BOARD DESCRIPTION . . . . . . . . . . . . . 1 III. 16550 FUNCTIONAL DESCRIPTION . . . . . . . . 3 A. INTERRUPT ENABLE REGISTER . . . . . . . . 4 B. INTERRUPT IDENTIFICATION REGISTER . [...]

LIST OF FIGURES Figure 1. DS-2000 board layout . . . . . . . . . 2 Figure 2. 16550 internal registers . . . . . . . 3 Figure 3. Interrupt enable register . . . . . . 4 Figure 4. Interrupt identification register . . 5 Figure 5. Interrupt source identification . . . 6 Figure 6. FIFO control register . . . . . . . . 7 Figure 7. FIFO receiver trigger [...]

I. INTRODUCTION The DS-2000 is a dual channel asynchronous seria l communication adapter which utilizes balanced differential drivers and receivers to provide RS-422-A communications. It is capable of reliable communication s over long distances (4000 feet) within noisy industria l environment. Data is communicated through two D- 9 connectors which[...]

FUNCTIONAL DESCRIPTION Figure 1. DS-2000 board layout . ii i[...]

FUNCTIONAL DESCRIPTION III. 1655 0 FUNCTIONAL DESCRIPTION The 16550 is an upgrade of the standard 1645 0 Asynchronous Communications Element (ACE). Designed t o be compatible with the 16450, the 16550 enters th e character mode on reset and in this mode will appear as a 16450 to user software. An additional mode, FIFO mode , can be selected to redu[...]

FUNCTIONAL DESCRIPTION A. INTERRUPT ENABLE REGISTER +------- + D7 | 0 | +------- + D6 | 0 | +------- + D5 | 0 | +------- + D4 | 0 | +------- + D3 | EDSSI |----- MODEM statu s +------- + D2 | ELSI |----- Receiver line statu s +------- + D1 | ETBEI |----- Transmitter holding register empty +------- + D0 | ERBFI |----- Received data available +-------[...]

FUNCTIONAL DESCRIPTION B. INTERRUPT IDENTIFICATION REGISTER +------ + D7 | FFE |----- FIFO enable (FIFO only ) +------ + D6 | 0 | +------ + D5 | 0 | +------ + D4 | 0 | +------ + D3 | IID2 |-- + +------+ | D2 | IID1 | +-- Interrupt identification +------+ | D1 | IID0 |-- + +------ + D0 | IP |----- Interrupt pending +------ + Figure 4. Interrupt iden[...]

FUNC TIONAL DESCRIPTION +-------------------+----------+---------------------- + | IID2 IID1 IID0 IP | Priority | Interrupt Type | +-------------------+----------+---------------------- + | x x x 1 | N/A | None | | 0 1 1 0 | Highest | Receiver Line Status | | 0 1 0 0 | Second | Received Data Ready | | 1 1 0 0 | Second | Character Timeout | | | | (F[...]

FUNCTIONAL DESCRIPTION C. FIFO CONTROL REGISTER +------ + D7 | RXT1 |-- + +------+ +-- Receiver trigger D6 | RXT0 |-- + +------ + D5 | x |-- + +------+ +-- Reserved D4 | x |-- + +------ + D3 | DMAM |----- DMA mode select +------ + D2 | XRST |----- Transmit FIFO reset +------ + D1 | RRST |----- Receive FIFO reset +------ + D0 | FE |----- FIFO enable[...]

FUNCTIONAL DESCRIPTION RRST - Receive FIFO Reset : When set (logic 1), all bytes in the receiver FIFO are cleared and the counter is reset. Th e shift register is not cleared. RRST is self - clearing . FE - FIFO Enable : When set (logic 1), enables transmitter and receiver FIFOs. When cleared (logic 0), al l bytes in both FIFOs are cleared. This bi[...]

FUNCTIONAL DESCRIPTION STKP - Stick Parity : Forces parity to logic 1 or logic 0 if parity i s enabled. See EPS, PEN, and figure 9 . EPS - Even Parity Select : Selects even or odd parity if parity is enabled . See STKP, PEN, and figure 9 . PEN - Parity Enable : Enables parity on transmission and verification on reception. See EPS, STKP, and figure [...]

FUNCTIONAL DESCRIPTION E. MODEM CONTROL REGISTER +------ + D7 | 0 | +------ + D6 | 0 | +------ + D5 | 0 | +------ + D4 | LOOP |----- Loopback enable +------ + D3 | OUT2 |----- Output 2 +------ + D2 | OUT1 |----- Output 1 +------ + D1 | RTS |----- Request to send +------ + D0 | DTR |----- Data terminal ready +------ + Figure 11. MODEM control regist[...]

FUNCTIONAL DESCRIPTION F. LINE STATUS REGISTER +------ + D7 | FFRX |----- Error in FIFO RCVR (FIFO only ) +------ + D6 | TEMT |----- Transmitter empty +------ + D5 | THRE |----- Transmitter holding register empty +------ + D4 | BI |----- Break interrupt +------ + D3 | FE |----- Framing error +------ + D2 | PE |----- Parity error +------ + D1 | OE |[...]

FUNCTIONAL DESCRIPTION Bits BI, FE, PE, and OE are the sources of receiver line status interrupts. The bits are reset by reading the line status register. In FIFO mode, these bit s are associated with a specific character in the FIFO and the exception is revealed only when that character reaches the top of the FIFO . BI - Break Interrupt : Indicate[...]

FUNCTIONAL DESCRIPTION G. MODEM STATUS REGISTER +------ + D7 | DCD |----- Data carrier detect +------ + D6 | RI |----- Ring indicator +------ + D5 | DSR |----- Data set ready +------ + D4 | CTS |----- Clear to send +------ + D3 | DDCD |----- Delta data carrier detect +------ + D2 | TERI |----- Trailing edge ring indicator +------ + D1 | DDSR |-----[...]

FUNCTIONAL DESCRIPTION H. SCRATCHPAD REGISTER This register is not used by the 16550. It may b e used by the programmer for data storage . IV. FIFO INTERRUPT MODE OPERATION 1. The receive data interrupt is issued when the FIFO reaches the trigger level. The interrupt i s cleared as soon as the FIFO falls below the trigger level . 2. The interrupt i[...]

B AUD RATE SELECTION J1 J 1 +-----------+ +----------- + 1| o o+ o |4 1| o--o o | 4 2| o o+ o |5 2| o o--o | 5 +-----------+ +----------- + (a) ÷1 input clock (b) ÷2 input clock J1 J 1 +-----------+ +----------- + 1| o o--o |4 1| o+ o--o | 4 2| o--o o |5 2| o+ o--o | 5 +-----------+ +----------- + (c) ÷5 input clock (d) ÷10 input clock Figure 1[...]

ADDRESSING VI. ADDRESSING Each channel of the DS-2000 uses 8 consecutive I/O address locations. The base addresses are independen t but must begin on an even 8-byte boundary (xxx0H - xxx7H or xxx8H - xxxFH). The numbers xxx are controlled by th e Programmable Option Select (POS) and address decoders t o provide complete 16-bit addressing for each c[...]

PROGRAMM ABLE OPTION SELECT The remaining POS registers are used for address and interrupt selections. These registers are programmed by the user through the IBM installation utility supplied with the PS/2. These registers are read/write but should not be written to by user software. The bit definition s of these registers are given in figures 16(a[...]

PROGRAMMABLE OPTION SELECT +-------------------------+------------------- + | ADSx3 ADSx2 ADSx1 ADSx0 | Base address | +-------------------------+------------------- + | 0 0 0 0 | 3F8H (Serial 1) | | 0 0 0 1 | 2F8H (Serial 2) | | 0 0 1 0 | 3220H (Serial 3) | | 0 0 1 1 | 3228H (Serial 4) | | 0 1 0 0 | 4220H (Serial 5) | | 0 1 0 1 | 4228H (Serial 6) [...]

OUT PUT CONFIGURATIONS IX. OUTPUT CONFIGURATIONS Two sets of jumpers are implemented on the DS-200 0 to control the auxiliary driver/receiver set. Jumpers J 2 and J3 perform identical functions on channels 1 and 2 respectively . The function of J2 and J3 is to control the source of the data exchanged on the auxiliary communication lines. The output[...]

OUTPUT CONFIGURATIONS The other function of J2 and J3 is to configure th e communication channel in half or full duplex mode. Hal f duplex operation is achieved by connecting pins 4 and 8 of the jumper block (figure 23). This allows th e transmitter to be enabled and disabled using the data terminal ready (DTR) output in the modem contro l register[...]

OUTPUT CONFIGURATIONS +----------- + | RI +-+ +------ + | DCD +-+ +-+ inv. +- + | DSR +-+ | +------+ | (4,5,6 for channel 1 , | DTR +-+----+----o o o 1,2,3 for channel 2 ) | | J4 | +---------- + | RCLK +-----------+ | AUXIN | RS-422 +--- + | | +--+--+---------+ Receiver +--- - | | 5 6| 7| 8| +---------- + | CTS +----o o+ o+ o+ Enable | RTS +----o o[...]

OUTPUT CONFIGURATIONS AUXIN ------+ +------ RCLK CTS --+ | | +-- DTR +------------------- + 5 | o---o o+ o | 8 1 | o---o o+ o | 4 +------------------- + RTS --+ | | +-- driver enable AUXOUT ------+ +------ XCLK J2 _ Channel 1 J3 _ Channel 2 Figure 21. Jumper configuration showing : (1) RTS transmission (2) CTS reception (3) XCLK/RCLK loopback (4) F[...]

EX TERNAL CONNECTIONS X. EXTERNAL CONNECTIONS Connections to peripheral equipment are made via a female D-9 connector. A pin-out of the D-9 connector and a detailed description of each output signal i s illustrated in figures 24 and 25 . Figure 24. D-9 output configuration . +-----+------------+---------------------------------- + | PIN | SIGNAL | [...]

INSTALLATION XI. INSTALLATION Make sure there is a copy of th e original reference diskette available . This diskette must be modified t o accept any option adapters . 1. Turn unit off . 2. Remove system cover as instructed in the IBM Quick Reference Guide . 3. Insert adapter into any vacant slot following th e guidelines for installing an optional[...]