Intel 80C188XL инструкция обслуживания

80C186XL/80C188XL Microprocessor User ’ s Manual[...]

80C186XL/80C188XL Microprocessor User’s Manual 1995[...]

Informat ion in this docume nt is provided solely to enable use of Intel products. Intel assumes no liability whatsoe ver, includin g infringe ment of any pat ent or copyrigh t, for sale and use of In tel pro ducts exce pt as pr ovid ed in Int el’s Terms and Con ditio ns of Sale for such produ cts. Intel Co rporation ma kes no war ranty for the u[...]

iii CONTEN TS CHAPTER 1 INTRODUCTION 1.1 HOW TO USE THIS MANUAL.... ...................... ....................... ...................... ........... ..... 1-2 1.2 RELATED DOCUMENTS ........... ................. ...................... ...................... ...................... 1-3 1.3 ELECTRONIC SUPPORT SYSTEMS ......... ................ .......[...]

CONTENTS iv 2.3 INTERRUPTS AND EXCEPTI ON HANDLING ............ ....................... ........... ........... ... 2-39 2.3.1 Interru pt/Exc eption Processi ng ........ ........... ....................... ...................... ...............2-39 2.3.1.1 Non-Mas kab le Interrupts .............. ...................... ...................... ......[...]

v CONTENTS CHAPTER 4 PERIPHERAL CONTROL BLOCK 4.1 PERIPHERAL CONTROL REGISTERS ........... ....................... ................ ...................... 4-1 4.2 PCB RELOCATION REGISTER ............ ...................... ............ ........... ........... ................ 4-1 4.3 RESERVED LOCATIONS ............... ....................... ......[...]

CONTENTS vi 6.4.5 Memory or I/O Bus Cycle Decodi ng .................. ........... ........... ........... ............ .........6-17 6.4.6 Progra mming Con s ideratio ns ................. ...................... ...................... .....................6-17 6.5 CHIP-SELECTS AND BUS HOL D ............... ...................... ...................[...]

vii CONTENTS 8.4 PROGRAMMING THE INTERRUPT CONTROL UNIT ...................... ...................... ... 8-11 8.4.1 Interru pt Contro l Regis ters ............... ...... ...................... ...................... .....................8-12 8.4.2 Interru pt Requ est Register ............... ...... ...................... ...................... ...[...]

CONTENTS viii 10.1.3 DMA Requests ........... ........... ................. ...................... ...................... .....................10-3 10.1.4 Extern a l Requ e sts ...................... ....................... ...................... ....................... ......... 1 0-4 10.1.4.1 Sourc e Synchron i zation .................... .......[...]

ix CONTENTS 11.3.1.4 Trans cendenta l Instruction s .................... ................. ........... ........... ........... .... 11-5 11.3.1.5 Const ant Ins tructions .................... ...................... ...................... .....................11-6 11.3.1.6 Processor Co ntrol Instru ctions .......... ....................... ..........[...]

CONTENTS x FIGURES Figure Pa ge 2-1 Simplif ied Function al Bloc k Diagram of the 80C186 Family CPU ............... ...... ..... ......2-2 2-2 Physical Addre s s Generati on .................... ...................... ................. ..... ...... ...... ........... 2-3 2-3 General Reg i sters .............. ....................... ...............[...]

xi CONTENTS FIGURES Figure Pa ge 3-15 Generating a Normally No t-Ready Bus Signal ................ ...................... .....................3-16 3-16 Generating a Normally Re ady Bus Signa l ...... ....................... ...................... ...............3-17 3-17 Normally Not -Ready Sy stem Timing .............. ........... ............ ..[...]

CONTENTS xii FIGURES Figure Pa ge 6-11 Wait State and Ready Con trol Functions ....... ....................... ...................... ...............6-16 6-12 Using Chi p-Selects Durin g HOLD ............. ........... ........... ........... ................. ...............6-18 6-13 Typical Syst em .............. ...................... ...........[...]

xiii CONTENTS FIGURES Figure Pa ge 10-3 Source-Sy nchronized Transfe rs ................ ..... ....................... ...................... ...............10-5 10-4 Destinat ion-Synchroni z ed Tra nsfers .............. ....................... ...................... ...............10-6 10-5 Two-Channe l DMA M odule ................. ..............[...]

CONTENTS xiv TABLES Table Pa ge 1-1 Comparis on of 80C186 Mod ular Core Family Products ........ ........... ........... ........... ...... 1-2 1-2 Relate d Docume nts and Software .................. ....................... ...................... .................1-3 2-1 Implicit Us e of Gen eral Reg isters ................... .....................[...]

xv CONTENTS TABLES Table Pa ge C-1 Instruction Format Vari ables.......... ............ ...................... ...................... ...................... C-1 C-2 Instruction Opera nds ..................... ....................... ...................... ........... ............ .......... C-2 C-3 Flag Bit Fun ctions ............... ........... ..[...]

CONTENTS xvi EXA MPLES Examp le Page 5-1 Initiali zing the Power Management Unit for Power-Save Mode .................. ...... .........5-14 6-1 Initiali zing the Chip -Select Unit ............ ........... ....................... ...................... ...............6-20 7-1 Initiali zing the Refre s h Cont rol Unit ...................... ........[...]

1 Introduction[...]

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1-1 CHAPTER 1 INTRO DUCTION The 8086 micropro cessor was first introduced in 1978 and g ained rapid support as the microco m- puter engine of cho ice. There are literally millions of 8086/8088-based systems in the world to- day. The amo unt of software written for the 8086/8088 is rivaled by n o other architecture. By the early 1980’s, howev er, [...]

INTRODUCTION 1-2 The 80C186 Mod ular Core family is the direct result of ten years of Intel develop ment. It offers the designer the p eace of mind of a well-established architecture with the benef its of state-of-the- art tec hnolo gy. 1.1 HOW TO USE THIS MANUAL This manual uses phrases such as 80C186 Modular Core Family or 80C188 Modula r Core , [...]

1-3 INTRODUCTION Each chap ter covers a specific section of t he device, beg i nning with the CPU core. Each perip h- eral chapter includ es programmin g ex amples intended to aid in you r under standing of device o p- eration. Please read the comments carefu l ly, as not all of the examples include all the code necessary for a specific ap plicat i[...]

INTRODUCTION 1-4 1.3 ELECTRONIC SUPP ORT SYSTEM S Intel’s FaxBack* service and app li cation BB S provide up-to -date technical information. Intel also maintains several fo rums on Compu S erve and offer s a variety of infor mati on on the World Wide Web. These systems are av ailable 24 hours a day, 7 days a week, providing technical infor- matio[...]

1-5 INTRODUCTION The fo l lowing catalog s and informatio n are available at the ti me of publication: 1. Solutions OEM subscription form 2. Microcontr oller and flash catalog 3. Developmen t tools catalog 4. Systems catalog 5. Multimedia catalog 6. Multib us and iRMX ® software catalog an d BBS file listings 7. Micropro cessor, PCI, and periph er[...]

INTRODUCTION 1-6 1.3.2.1 How to Find Ap BUILDER Software a nd Hypertext Doc uments on the BBS The latest Ap BUILDER files and hypertext man uals and data sheets are available first from the BBS. To access the files, comp l ete these steps: 1. Ty pe F from the BBS Main menu. The BB S displays the Intel App s Files menu. 2. Ty pe L and press <Ente[...]

1-7 INTRODUCTION 1.5 PRODUCT LITERATURE You can order product literature f rom the followin g Intel literature cen ters. 1-800-468-8118, ext. 28 3 U.S. and Canada 708-296-93 33 U.S. (from overseas) 44(0)17 93-431155 Europe (U.K.) 44(0)1793-421333 Germany 44(0)1793-421777 France 81(0)120-47-88- 32 Japan (fax only) 1.6 TRAINING CLASSES In the U.S. an[...]

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2 Overview of the 80C186 Family Architecture[...]

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2-1 CHAPTER 2 OVERVIEW OF THE 80C186 FAMI LY ARCHITECTU RE The 80C1 86 Modular Micro processor Cor e shares a common base architecture with the 8086, 8088 , 80186, 8018 8, 80286, Intel386™ and Intel486™ pro cessors. The 80C186 Modu lar Core maintains full ob ject-code co mpatibility with the 808 6/8088 family of 16- bit micropro ces sors, while[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-2 Figure 2-1. Simplifie d Functio nal Bl ock Diagram of the 80C1 86 Fami ly CPU 2.1.1 Execution Unit The Execution U nit executes all instructions, provides data and addr es ses to the Bus Interface Unit and manipu l ates the general registers and the Processor Status Word. The 16-bit ALU within the Exe[...]

2-3 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE The Execution Unit does not con nect directly to the system bus. It o btains instructions from a queue mainta ined by the Bus Interface Un it. When an instruction req uires access to memory or a peripheral device, th e Execution Unit requests the Bus Interface Unit to read and wr ite data . Ad- dresse[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-4 During per iods when the Execution Unit is busy executing instructions, the Bus Interface Unit sequentially prefetches instructions from memo ry. As long as the prefetch queue is partially full, the Execu tion Unit fetches instructions. 2.1.3 General Regi sters The 80C186 Modular Core family CPU has e[...]

2-5 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE The data registers can be addressed by their upper or lower halves. Each data reg ister can be used interchang eably as a 16-bit register or two 8-bit reg i sters. The pointer registers are always acces s- ed as 16-bit values. Th e CPU can use data registers without constraint in most arithmetic and l[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-6 Figure 2-4 . Segment Registe r s 2.1.5 Instruction Pointer The Bus Interface Unit updates the 16-bit Instr uction Pointer (IP) register so it contains the offset of the next instruction to be fetched. Programs do not have direct access to the Instruction Pointer, but it can change, b e s aved o r be r[...]

2-7 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE 2.1.6 Flags The 80C186 Modu lar Core family has six status f l ag s (see F igure 2-5) that the Execution Unit posts as the result of arithmetic or logical operation s. Program branch instru ctions allow a pro- gram to alter its execution depending on con ditions flagged by a prior operation. Different[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-8 2.1.7 Memory Segmentation Programs f or the 80 C186 Modular Core family view the 1 Mby te memory space as a gro up of user-defin ed se gments. A segment is a lo gical unit of memory th at can be up to 6 4 Kbytes long. Each segmen t i s co mpo sed of con tig uou s memory locatio ns. Segmen ts are indep[...]

2-9 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE Figure 2-5 . Processor Stat us Word Register Name: Processor Status Word Register Mnemonic: PSW (FLAGS) Register Function: Posts CPU statu s inf ormation. Bit Mnemo nic B it Name Res et State Func tion OF O verf low Flag 0 If OF is set, an arithmetic overflow has occurred. DF Direction Flag 0 If DF is[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-10 Figure 2 -6. Segm ent Locations in P hysical Memory The four segm ent registers point to four “currently ad dressable” segments (see Figure 2-7). The curren t ly add ressable segments pro vide a work space consis ting of 64 Kbytes for co de, a 64 Kbytes for stack and 128 Kbytes for data storag e.[...]

2-11 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE Figure 2-7. Curren tly Address able Seg ments The segment register is automatically selected according to th e rules in Table 2-2. All information in one segment ty pe generally shares the same lo gical attributes (e.g., code or data). This leads to programs that are shorter, faster and better struct[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-12 Figure 2 -8. Logi cal and Physica l Address Physical Address Segment Base Logical Addresses 2C4H 2C3H 2C2H 2C1H 2C0H 2BFH 2BEH 2BDH 2BCH 2BBH 2BAH 2B9H 2B8H 2B7H 2B6H 2B5H 2B4H 2B3H 2B2H 2B1H 2B0H Segment Base Offset (3H) Offset (13H) A1038-0A[...]

2-13 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE Instructions are always fetched from the current code segmen t. The IP register contain s the in- struction’s off s et from th e beginning of the segment. Stack instruction s always o perate on the cur- rent stack segment. The Stack Pointer (SP) register contains the offset of the top of the stack [...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-14 Figure 2 -9 . Dynam ic Code Relocation To be dynamically reloc at able, a pro gram must not load or alter its segment registers and must not transfer directly to a lo cation o utside the curr ent code segment. All program off sets must be relative to the segment registers. This allows the pro gram to[...]

2-15 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE 2.1.10 Stack Implementation Stacks in the 80C186 Modu lar Core family reside in memo ry space. They are located by the Stack Segment reg ister (SS) and the Stack Pointer (SP). A system can have multiple stacks, but only one stack i s directly addre s sable at a time. A stack can be up to 64 Kb ytes l[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-16 Figure 2-10. St ack Operati on A1013-0 A 1060 1062 105E 105B 105A 1058 1056 1054 1052 1050 22 00 44 66 88 AA 34 45 89 CD 33 11 55 77 99 BB 12 67 AB EF Not presently on stack Bottom of stack POP AX POP BX TOS SS SP BB AA 10 50 1060 1062 105E 105B 105A 1058 1056 1054 1052 1050 22 00 44 66 88 AA 3[...]

2-17 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE 2.2 SOFTWARE OVERV IEW All 80C186 Modular Core family m embers execute the same instruction s . This includes all the 8086 /8088 instruction s plus several addition s and enhancem ents (see Append ix A, “8 0C186 In- struction Set Additions and E xtensions”). The following sections describe the in[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-18 2.2.1.1 Data Tra nsfer Inst r uctions The instruction set contains 14 data transfer instructions. Th es e instructions move single by tes and words b etw een m emory and registers. They also m ove single b ytes and words between the AL or AX register and I/O ports. Table 2-3 lists the four types of d[...]

2-19 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE Figure 2-11. F lag Storage Format 2.2.1.2 Arithmeti c Instructi ons The arithmetic in structions (see Table 2-4) op erate on four types of n u m bers: • Unsign ed binary • Signed bin ary (integers) • Unsigned p acked decimal • Unsign ed unpacked d ecimal A1014-0A U = Undefined; Value is indet[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-20 Table 2-5 shows the interpr etations of variou s bit patterns according to number type. Binary nu m- bers can be 8 or 16 bits long . Decimal numbers are stored in bytes, two digits per by te for pack ed decimal and one digit per byte fo r unpacked decim al. The processor assumes that the operand s in[...]

2-21 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE 2.2.1.3 Bit Manipulatio n Instructio ns There are three grou ps of instructions for manipulating bits within byte s and words. These three groups are logical, shifts and rotates. Table 2-6 lists the bit manipulation instructions and their function s. Logical instructions include the Boolean oper ator[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-22 Individual bits in bytes and words can also be rotated. The pr ocessor does not discard the bits ro- tated out of an operand. The bits circle back to the other end of the operand. The num ber of bits to be rotated is taken f rom the count op erand, which can specify either an immediate value o r the [...]

2-23 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE String instruction s automatically update the SI reg i ster, the DI re gister, or both, bef ore processing the next string element. The Direction Flag (DF) determines whether the ind ex registers are auto- incremented (DF = 0 ) or auto-decremen ted (DF = 1). The processor adjusts th e DI, SI, or both[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-24 Uncond i tional transfer instructions can t ransfer co ntrol either to a tar get instruction within the curren t code segment ( i ntrasegment transfer) or to a different cod e segment (intersegmen t trans- fer). The assembler terms an intrasegmen t transfer SHORT or NEAR and an intersegm ent trans- f[...]

2-25 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE Table 2-9 . Progra m Transfer Instructio ns Conditional Transfers JA/JNBE Jum p if above/not below nor equal JAE/JNB Jum p if above or equal/not be low JB/JNAE Jum p if below/not above nor equal JBE/JNA Jum p if below or equal/not above JC Jump if car ry JE/JZ Jump if equal/ zero JG/JNLE Jump if grea[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-26 Iteration control instruction s can be used to regulate the repetition of software loops. These in- structions use the CX register as a counter. Like the conditional transf ers, the iteration control in- structions are self-r elative and can transfer o nly to targets that are within –128 to +127 by[...]

2-27 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE 2.2.1.6 Processor Con tr ol Instructi ons Processor control instr uctions (see Table 2-11) allow programs to control var ious CPU functions. Seven of these instructions up date flags, four of them are used to synchr onize the microp rocessor with external events, and the remaining instruction causes [...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-28 Immediate operand s are constant d ata contained in an in struction. Imm ediate data can be either 8 or 16 b i ts in leng t h. Immediate operands ar e available directly from the inst ruction qu eue and can be accessed quickly. As with a register operand, no bus cycles need to be run to get an imme- [...]

2-29 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE Figure 2-12 . Memory Address Comp utation The displacement is an 8- or 16-bit n u mber contained in the instruction. The displacement gen- erally i s derived from th e position of th e operand ’s name (a variable or label) in the prog ram. The programmer can modify this value or ex plicit ly specif[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-30 The BX or BP register can be specified as the base register for an e ffective a ddress calculation. Similarly, either the SI or the DI register can be specified as the inde x register. The displacement value is a constant. The contents of the base and ind ex registers can change du ring execu t ion. [...]

2-31 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE Figure 2 -14. Reg ister Indirect Address ing Figure 2 -15. Bas ed Addressing Based add res sing pro vides a s imple way to ad dress data s tructures that may be located in different places in memory (see Figure 2-1 6). A base register can be pointed at the structure. Elements of the structure can the[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-32 Figure 2-16. Acc essing a Structure with Based Add ressing With indexed addressing, the effective add ress is calculated by summing a displacement and the contents of an index register (SI or DI, s ee Figure 2-1 7). Indexed ad dressing is often used to ac- cess elements in an array (see Figur e 2-1 8[...]

2-33 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE Figure 2-17. In dexed Addressing Figure 2-1 8. Accessin g an Array with Indexed Addre ssing EA DI SI Opcode Mod R/M Displacement or + A1020-0A Displacement EA High Address Index Register 14 Array (8) Array (7) Array (6) Array (5) Array (4) Array (3) Array (2) Array (1) Array (0) Displacement EA Index[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-34 Based in dex addressing gen erates an effective address that i s the sum of a base register , an index register and a displacement (see Figure 2-1 9). The two address componen ts can be determ ined at execution ti me, making this a v ery flexible addressing mo de. Figure 2 -19 . Base d Index Addressi[...]

2-35 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE Figure 2- 20. Acce ssing a Stacked Array with Base d Index Addressing Displacement EA High Address Index Register 6 12 Base Register Displacement EA Index Register 6 Base Register Array (6) Array (5) Array (4) Array (3) Array (2) Array (1) Array (0) Parm 2 Parm 1 IP Old BP Old BX Old AX Count Temp St[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-36 Figure 2-21. String Operand 2.2.2.3 I/O Port Addressin g Any memory o peran d addressing modes can be used to access an I/O port if the p ort is memor y- mapped. String instructions can also be used to transfer data to memo ry-mapped ports with an appro priate hardware interface. Two addressing modes[...]

2-37 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE 2.2.2.4 Data Ty pes Use d in the 80C186 Modu lar Core Family The 80C1 86 Modu lar Co re family supp orts the data types described in Tab le 2-1 2 an d illustrated in Figure 2 -23. In general, ind ividual data elements must fit within defined segment limits. Table 2-12. Su pported Data Types Type D es[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-38 Figure 2 -23. 80 C186 Modular Core Fami ly Supported Data Typ es 15 +1 87 0 0 16 +2 23 24 +3 31 NOTE: *Directly supported if the system contains an 80C187. 15 14 +1 87 0 0 15 +1 87 0 0 7 0 7 0 BCD Digit n BCD Digit 1 BCD Digit 0 0 ASCII Character n ASCII Character 1 ASCII Character 0 15 +1 87 0 0 16 [...]

2-39 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE 2.3 INTERRUPTS AND EXCEPTION HAND LING Interru pts and exception s alter program execu t ion in re s ponse to an exter nal event or an error condition . An interrupt han dles asynchrono us external events, for ex ample an NMI. Exception s result directly from the execution of an instruction, usually [...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-40 Figure 2-25. I nterrupt Vecto r Table When an interru pt is acknowledg ed, a common event sequence (Fig ure 2-26) allows the proces- sor to execu te the interrupt service ro utine. 1. The processor saves a partial machine status by pushing th e Processor Status Word onto the stack. Memory Address [...]

2-41 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE 2. The Trap Flag bit and Interrupt Enable bit are cleared in the Processor Status Word. This prevent s maskable interrupts or single step ex ceptions from interrupting the processor during the in terrupt service ro utine. 3. The current CS and IP are pushed onto the stack. 4. The CPU fetches the new [...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-42 Figure 2-2 6. Interrupt Sequ ence 2.3.1 .1 Non-Maskable Interrupts The Non-Mask able Interrupt (NMI) is the highest priority interrup t . It is usually reserved for a catastrophic ev ent such as impending po wer failure. An NMI cannot be preven ted (or ma s ked) by software. When th e NMI input is as[...]

2-43 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE 2.3.1.2 Maskab le Interrupts Maskable inter rup ts are the mo st com mon way to serv ice external har dware interr upts. Software can glo bally enable or disable maskable interru pts. This is done by setting or clearing t he Inter- rupt Enable b it in the Processor Status Word. The Interru pt Control[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-44 Breakpoint Interrupt — Type 3 The Breakpo i nt Interrupt is a single-byte v ersi on of the INT instruction . It is commonly used by software debu ggers to set breakpoints in RAM. Because the instruction is only one byte long, it can substitute for any instruction. Interrupt on Overflow — Type 4 T[...]

2-45 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE 2.3.2 Software Interrupts A Software I nterrupt is cau sed by execu ting an “I NT n ” instru ction. The n p arameter corr espond s to the specific interrupt type to be executed. The interrup t type can be any number between 0 and 255. If the n parameter corresponds to an i nterrup t type associat[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-46 2.3.4 Interrupt Response Time Interrupt r es ponse time is the time fr om the CPU recognizing an interru pt u ntil the fir st instruction in the service routine is executed . Interrupt response time is less for inter rupts or exception s which sup ply their own vector type. The maskable interrupt has[...]

2-47 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE Only the single step exception can occu r concurrently with another excep tion. At most, two ex- ceptions can occur at the same in structio n bou ndary and one of tho se excep tions must be the sin- gle step. Single step is a special case; i t is discussed on page 2-48. Ignoring single step (for now)[...]

OVERVIEW OF THE 80C18 6 FAMILY ARCHITECTURE 2-48 Single step priority is a special case. If an interrupt (NMI or maskable) occu rs at the same instruc- tion boun dary as a sing le s tep , th e interr upt vector is taken first, then is followed immediately b y the sing le step vector. However, the single step service routine is executed before the i[...]

2-49 OVERVIEW OF THE 80C1 86 FAMILY ARCHITECTURE Figure 2 -30. Simultan eous NMI, Single Step a nd Maskable Interrupt A1034-0A NMI Push PSW, CS, IP Fetch Divide Error Vector IRET Divide Timer Interrupt Push PSW, CS, IP Fetch Single Step Vector Push PSW, CS, IP Fetch Single Step Vector IRET Execute Single Step Service Routine Execute Single[...]

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3 Bus Interface Unit[...]

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3-1 CHAPTER 3 BUS INTERF ACE UNIT The Bus Interface Unit ( BIU) generates bus cycles that prefetch instructions from memory, pass data to and fr om the execution unit, and pass data to an d from th e integrated peripheral units. The BIU driv es addr ess, data, status an d control infor mation to define a b us cycle. The start o f a bus cycle presen[...]

BUS INTERFACE UNIT 3-2 Figure 3-1 . Physical Da ta Bus Models Byte transfers to ev en ad dresses transfer inf orm ation over the lower half o f the data b us (see Fig- ure 3-2). A0 low enab les the lower bank, while BHE hig h disables the upper bank. The data value from the upper bank is ign ored during a bus read cycle. BHE high prevents a write o[...]

3-3 BUS INTERFACE UNIT Figure 3- 2. 16-Bit Data Bus Byte Transfers Even Byte Transfer Odd Byte Transfer A19:1 D15:8 D7:0 A0 (Low) BHE (High) A19:1 D15:8 D7:0 A0 (High) BHE (Low) Y (X) Y + 1 X + 1 Y X Y + 1 (X + 1) A1104-0A[...]

BUS INTERFACE UNIT 3-4 Figure 3-3. 16-Bit Data Bus Even Word Transfers During a byte read oper ation, the BIU floats the en t ire 16-bit data bus, even though the transfer occurs on only one h alf of the bus. This action simplifies the decoding r equirements for read-only devices (e.g., ROM, EP ROM, Flash). During th e byte read, an extern al devic[...]

3-5 BUS INTERFACE UNIT Figure 3-4 . 16-Bit Da ta Bus Odd Word Tra nsfers 3.2.2 8-Bit Data Bus The memo ry address space on an 8-b it data bus is physically implem ented as one bank of 1 Mbyte (see Figure 3-1 on page 3-2). Add ress lines A19:0 select a specific byte within the b ank. Unlike transfers with a 16-bit bus, by t e an d word tran sfers (t[...]

BUS INTERFACE UNIT 3-6 For word tran sfers, the word address defines the f irst byte transferre d. The second byte tr ansfer occurs from the word address plus one. Figure 3-5 illustr ates a word transfer on an 8- bit bus in- terface. Figure 3-5 . 8-Bit Data Bus Word T ransfers 3.3 MEMORY AND I/ O INTERFACES The CPU can interface with 8- and 16 -bit[...]

3-7 BUS INTERFACE UNIT 3.3.1 16-Bit Bus Memory a nd I/O Requirements A 16-bit bus has certain as sumptions that mu st be met to operate proper ly. Memor y used to store instru ct ion oper ands (i.e., the program) and immediate data must be 16 bits wide. Instruction prefetch bus cycles requ i re that both ba nks be used. The lower ba nk contains the[...]

BUS INTERFACE UNIT 3-8 Figure 3 -6. Typi cal Bus Cycle Figure 3-7 . T-State Relation to CLKOUT Figure 3-8 shows the BIU state diagram. Typically a bus cycle consists of four consecutive T- states labeled T1, T2, T3 and T4. A TI (idle) state occu rs when no bu s cycle is pending. Multiple T3 states occur to gener ate wai t states. The TW symbol rep [...]

3-9 BUS INTERFACE UNIT The address/status phase starts just before T1 and continues through T1. The data phase starts at T2 and con t inues through T4. Fig ure 3-9 illustrates the T- state relationship of the two p hases. Figure 3 -8. BIU State Diag ram Bus Ready Request Pending HOLD Deasserted Bus Not Ready Halt Bus Cycle Bus Ready No [...]

BUS INTERFACE UNIT 3-10 Figure 3-9 . T-State and Bu s Phases 3.4.1 Address/Sta tus Phase Figure 3-1 0 shows signal timing relationships for the addr ess/status phase of a b us cycle. A bus cycle begins with the tran sition of ALE and S2:0 . These signals transition during phase 2 of the T-state just prio r to T1. Either T4 or TI precedes T1 , depen[...]

3-11 BUS INTERFACE UNIT Figure 3-10. Ad dress/Statu s Phase Signal Relationship s ALE AD15:0 A19:16 CLKOUT S2:0 BHE T4 or TI T1 T2 1 4 2 3 5 6 Valid Valid NOTES:  1. T CHLH T CHSV : Clock high to ALE high, S2:0 valid. 2. T CLAV : Clock low to address valid, BHE valid. 3. T AVLL : Address valid to ALE low (address setup to ALE). 4.[...]

BUS INTERFACE UNIT 3-12 Figure 3-11 . Demultiplex ing Addres s Informat ion Table 3-1 . Bus Cycle Type s Status B it Op eration S2 S1 S0 0 0 0 Interrupt Acknowledge 001 I / O R e a d 0 1 0 I/O Write 0 1 1 Halt 1 0 0 Instruct ion Prefet ch 1 0 1 Memory Read 1 1 0 Memory Write 1 1 1 Idle (passive) 4 I I STB 8 8 O O ALE Latched Address Signals Sign[...]

3-13 BUS INTERFACE UNIT 3.4.2 Data Phase Figure 3-1 2 shows the timing relationships for the data phase of a bus cycle. Th e only bus cycle type that does not h ave a data phase is a bus halt. During the data phase, the bus transfers info r- mation between the internal units and the memor y or per i p heral device selected during the ad- dress/stat[...]

BUS INTERFACE UNIT 3-14 Figure 3 -12. Data Phase Signal Relat ionships AD15:0 Write AD15:0 Read S2:0 CLKOUT T2 T3 or TW T4 or TI RD/ WR 1 4 2 3 5 6 7 Valid Read Data Valid Write Data NOTES : 1. T CLRL/CLWL, T CLOV : Clock low to valid RD/WR active, write data valid. 2. T CLSH : Clock low to status inactive. 3. T DVCL : Data [...]

3-15 BUS INTERFACE UNIT Figure 3-13. T ypical Bu s Cycle with Wait States Figure 3 -14. ARDY and SRDY Pin Block Diagram ALE S2:0 A19:16 AD15:0 READY WR CLKOUT T1 T2 T3 TW TW T4 Valid Address Address Valid Write Data A1040-0A DQ ARDY BUS READY CLKOUT Rising Edge DQ Falling Edge SRDY A1041-0A[...]

BUS INTERFACE UNIT 3-16 A normally not-ready system is one in which ARDY and SRDY remain low at all times except to signal a ready co ndition. For any bus cycle, only the selected d evice drives either read y input high to comp lete the bus cycle. The circuit shown in F igure 3-15 ill ustrates a simple circuit to generate a nor mally not-ready sign[...]

3-17 BUS INTERFACE UNIT Figure 3-1 6. Generat ing a Normally Ready Bus Signal The ARDY input ha s two major timing concerns that can affect whethe r a normally ready or nor- mally not-r eady signal may be required . Two latches capture the state of the ARDY input ( s ee Figure 3-14 on page 3-15). The first latch captures ARDY on the phase 2 clock e[...]

BUS INTERFACE UNIT 3-18 Figure 3 -17. Norma lly Not-Ready System Timing A valid not-ready input can be generated as late as phase 1 of T3 to insert w ait states in a normally ready system. A normally not-read y system must run wait states if the not-ready condition can not be met in time. Figu re 3-18 illustrates the minimum and maximum t iming nec[...]

3-19 BUS INTERFACE UNIT Figure 3 -18. Norma lly Ready System Timings Conditions causing the BIU to become idle in clude the following. • The instruction pref etch queue is full. • An effective address calculation is in progress. • The bus cy cle inherently requ ires idle states (e.g., interrupt ack nowledge, locke d opera- tions). • Instruc[...]

BUS INTERFACE UNIT 3-20 An idle bus state m ay o r may not dr ive the bus. An idle bus state following a bu s read cycle con- tinues to float the bus. An idle bus state follo w ing a bus write cycle continues to driv e t he bus. The BIU drives no con trol strobes active in an idle state except to indicate the start of another bu s cycle. 3.5 BUS CY[...]

3-21 BUS INTERFACE UNIT T OE , T ACC and T CE d efine the maximum data access requirements for the mem ory device. These device parameters must be l ess than the value calculated in the equ at ion column. An equal to or greater than result ind icat es that wait states must be inserted into the bus cycle. T DF determines the maximum time the memory [...]

BUS INTERFACE UNIT 3-22 3.5.1.1 Refresh Bus Cycles A refresh b us cycle operates similar ly to a normal read bus cycle except for the following : • For a 16-b it data bus, address bit A0 and BHE drive to a 1 (high) and the data value on the bus is ignored. • For an 8-b i t data bus, address b it A0 drives to a 1 (high) and RFSH is driven active[...]

3-23 BUS INTERFACE UNIT Figure 3- 21. Typ ical Write Bus Cycle Figure 3-2 2 illustrates a typical 16-bit interface conn ection to a read/write device. Write bus cy- cles have many parameters that must be eva lu ated in deter mining th e compatibility of a memory (or I/O) device. Table 3-5 lists some critical write bus cycle parameters. Table 3- 4. [...]

BUS INTERFACE UNIT 3-24 Most memory and per ipheral devices latch data on the rising edge of the write strobe. Address, chip-select and d ata must be v alid (set up) prior to the rising edge of W R . T AW , T CW an d T DW de- fine the minimum data se t up requirem ents . The value calculated by their respective eq uations must be greater than the d[...]

3-25 BUS INTERFACE UNIT The minimum device data hold time (fro m WR high) is defined by T DH . The calculated value must be greater than the minimum device requ irements; however, the value can be changed only by decreasing the clock rate. T WC and T WP define the minimum time (maximum freq uency ) a device can process write bus cy- cles. T WR dete[...]

BUS INTERFACE UNIT 3-26 Figure 3-2 3. Interrupt Ackn owledge Bus Cycle T1 T2 T3 T4 CLKOUT ALE TI TI T1 T2 T3 AD15:0 [AD7:0] RD, WR BHE DEN DT/R LOCK S2:0 INTA0 INTA1 A19:16 [A15:8] NOTE: Vector Type is read from AD7:0 only. INTA occurs during T2 in slave mode. Note A15:8 are unknown A19:16 are driven low Note Note T4 A1048-0A[...]

3-27 BUS INTERFACE UNIT Figure 3-24 sho ws a typical 82C59A interface example. Bus ready must be provided to terminate both bus cycles in the interrupt acknowledge sequence. NOTE Due to an intern al condition, ex ternal ready i s ignored if the device is configur ed in Cascade mode an d the Peripheral Control Block (PCB) is located at 0000H in I/O [...]

BUS INTERFACE UNIT 3-28 3.5.4 HALT Bus Cycle Suspending the CPU reduces device power consumptio n and potentially reduces interru pt latency time. The HLT in struction initiates two events: 1. Suspends the Ex ecution Unit. 2. Instructs the BIU to execute a HALT b us cycle. After executing a HALT bus cycle, the BIU suspends operation until one of th[...]

3-29 BUS INTERFACE UNIT Figure 3-2 5. HALT Bus Cycle Table 3 -6. HALT Bus Cycle Pin States Pin(s) Pin S tate AD15:0 ( AD7:0 f or 8-bit) Float A15:8 (8-b it) Drive Address A19:16 Drive 8H or Zero BHE (16-b it) Drive Last V alue RD , WR , DEN , DT/R , RFSH (8-bit), S2: 0 Drive One 011 CLKOUT ALE S2:0 AD15:0 [AD7:0] [A15:8] A19:16 NOTES:  1. The[...]

BUS INTERFACE UNIT 3-30 3.5.5 Temporarily Exiti ng the HALT Bus State A DMA request, refresh request or bus hold req uest causes the BIU to exit the HALT bus state temporar i ly. This can o ccur only w hen in the Active or Idle power managemen t mode. The BIU returns to the HALT bus state after it comp let es the desired bus operation. However, the[...]

3-31 BUS INTERFACE UNIT Figure 3-2 7. Returning to HALT After a Refresh Bus Cycle CLKOUT AD15:0 [AD7:0] ALE [A15:8] A19:16 Address Note 1 Note 2 Note 3 NOTES:  1. Previous bus cycle value. 2. Only occurs for BHE on the first refresh bus cycle after entering HALT. 3. BHE = 1 for 16-bit device, RFSH = 0 for 8-bit device. S2:0 BHE RFSH [...]

BUS INTERFACE UNIT 3-32 Figure 3-28 . Returning to HALT After a DM A Bus Cycle 3.5.6 Exiting HALT An NMI or an y unmasked INT n interrupt causes the BIU to ex it HALT. The first bus operation s to occur after exiting HALT are read cycles to reload the CS :IP registers. Figure 3-29 shows how the HALT bus state is exited when an NMI or INT n o ccurs.[...]

3-33 BUS INTERFACE UNIT Figure 3 -29 . Exiti ng HALT 3.6 SYSTEM DE SIGN ALTERNATIVE S Most system d es igns require no signals other than those already provided by the BIU. Howev er, heavily load ed bus co nditions, slow mem ory or peripher al device perfor mance an d off-b oard de- vice interfaces may not be supported directly without modify ing t[...]

BUS INTERFACE UNIT 3-34 3.6.1 Buffering the Data Bus The BIU generates two contr ol sign als, DEN an d DT/R , to contro l bidirectional buffers or trans- ceivers. The timing relationship of DEN and DT/R is shown in Figure 3-30. The following con- ditions requ ire transceivers: • The capacitive lo ad on the address/data bus gets too large. • The[...]

3-35 BUS INTERFACE UNIT Figure 3-3 1. Buffered AD Bus Syste m In a fully b uffered system, DEN directly drives the transceiver o utput enable. A partially buff ered system requires that DEN be qualified with another signal to prevent the transceiver from going active for local bus accesses. Figure 3 -32 illustrates how to use chip-selects to qualif[...]

BUS INTERFACE UNIT 3-36 Figure 3-32 . Qualifying DEN with Chip-Selects 3.6.2 Synchronizing Software and Hardware Even ts The executio n sequen ce of a p rogr am and hardware events occur ring within a system are often asynchro nous to each other. In some systems there may be a requir ement to suspend progr am ex- ecution u ntil an event (or even ts[...]

3-37 BUS INTERFACE UNIT The WAIT instruction suspend s program execution until one of two events occurs: an interrupt is generated, o r the TEST inpu t pin is sampled low. Unlike interrupts, the TEST input pin doe s not require th at program execu t io n b e transferred to a new location (i.e., an interrupt routine is not executed ). In pro cessing[...]

BUS INTERFACE UNIT 3-38 In general, p refix bytes (such as LOCK) are considered extensions o f the instructio ns they pre- cede. Inter rupts, DMA requ ests and refresh req uests that occur dur ing execution o f the prefix are not acknowledged until the instruction following the prefix com pletes (except for instruction s that are serv i cing in t e[...]

3-39 BUS INTERFACE UNIT Figure 3- 33. Queue Status Ti ming 3.7 MULTI-MASTER BUS SYSTE M DESIGNS The BIU suppor ts protocols for tr ansferring control of the local bus between itself and other de- vices capable of acting as bus masters. To suppor t such a protocol, the BIU uses a hold requ es t input (HOLD) and a hold acknowledge output (HLDA) as bu[...]

BUS INTERFACE UNIT 3-40 Figure 3 -34. Ti ming Sequence Ente ring HOLD 3.7.1.1 HOLD Bus La tency The duration between the time that the external device asserts HOLD and the time that the BIU asserts HLDA is known as bus laten cy . In Figure 3-34 , the two-clock delay between HOLD and HLDA represents the shortest bus latency . Normally this occurs on[...]

3-41 BUS INTERFACE UNIT The major factors that influence bu s latency are listed below (in order fro m l ongest delay to short- est delay). 1. Bus Not Ready — As long as the bus remains no t ready, a bus hold requ est cannot be serviced. 2. Locked Bus Cycle — A s long as LOCK remains asserted, a bus hold request cannot be serviced. Performin g [...]

BUS INTERFACE UNIT 3-42 Figure 3-35 . Refresh Request Du r ing HOLD The devic e requesting a bu s hold must be able to detect a HLDA pu lse that is one clock in dura- tion. A bus lockup (ha ng) condition can result if the requesting device fails to detect the short HLDA pulse and continues to wait for HLDA to be asserted while the BIU waits for HOL[...]

3-43 BUS INTERFACE UNIT Figure 3-3 6. Latching HLDA The removal of HOLD must be detected for at l east one clo ck c ycle to all ow the BIU to regain the bus and execute a refresh bu s cycle. Sho uld HOLD go active before the refresh bus cycle i s complete, the BIU will release the b us and gen erate HLDA. 3.7.2 Exiting HOLD Figure 3-3 7 shows the t[...]

BUS INTERFACE UNIT 3-44 Figure 3-3 7. Exitin g HOLD 3.8 BUS CYCLE P RIORITIES The BIU arbitrates req uests for bus cycles from th e Execution Unit, the integrated p eripherals (e.g., Interru pt Control Unit) and external bus masters (i.e., bus hold requests). The list below summarizes the pr i orities for all b us cycle requests (fro m highest to l[...]

3-45 BUS INTERFACE UNIT 6. Internal er ror (e.g ., divide error, over flow) interrupt vector ing sequence. 7. Hardware (e. g., INT0, DMA) i nterrupt vector ing sequence. 8. 80C187 Math Copro cessor error interrup t vectoring sequence. 9 . DMA bus cycles. 10. General instruction execution. Th is category includes read/write operations following a pi[...]

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4 Peripheral Control Block[...]

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4-1 CHAPTER 4 PERIPHERAL CO NTROL BL OCK All integrated perip herals in the 80C186 Mod ular Core family are con trolled by sets of register s within an integr ated Peripheral Control Block (P CB). The periph eral control registers are physi- cally located in the periph eral devices th ey control, bu t they are addr essed as a single block of regist[...]

PERIPHERAL CONTROL BLOCK 4-2 Figure 4-1 . PCB Relocation Register Register Name: PCB Relocati on Reg ister Register Mnemonic: RELREG Register Function: Relocates the PCB within mem ory or I/O space. Bit Mnemo nic Bit Name Reset State Fu nct ion ET Escape Trap 0 If ET is set, the CPU will trap when an ESC instruction is execut ed. SL Slave/Master 0 [...]

4-3 PERIPHERAL CONTROL BLOCK Table 4-1. Peripheral Control Block PCB Offset Funct ion PCB Offset Functio n PCB Offset Fun cti on PCB Offset Fu nct ion 00H Reserved 40H Reserved 80H Reserved C0H D0SRC L 02H Reserved 42H Reserved 82H Reserved C2H D0SRC H 04H Reserved 44H Reserved 84H Reserved C4H D0DSTL 06H Reserved 46H Reserved 86H Reserved C6H D0DS[...]

PERIPHERAL CONTROL BLOCK 4-4 4.3 RESERVE D LOCATIONS Many locations within the Peripheral Contr ol Block are not assigned to any peripheral. Unused locations are r ese rved. Reading from these location s yields an undefined result. If reserved reg- isters are written (for example, during a block MOV instruction) they must be set to 0H. NOTE Failure[...]

4-5 PERIPHERAL CONTROL BLOCK 4.4.3 F-Bus Operation The F-Bus functions d ifferently than the external data bus for by te and word accesses. All write transfers on the F-Bus occur as wo rds, regardless of how they are encoded. For examp le, the in- struction OUT DX, AL (DX is even) will write the entire AX register to the Peripheral Control Block re[...]

PERIPHERAL CONTROL BLOCK 4-6 4.4.3.1 Writing the PCB Re location Register Whenever map ping the Peripheral Contr ol Block to anoth er location, the user sh o uld pr ogram the Relocation Register with a byte write (i.e., OUT DX , AL). Internally, the Relocation Register is written with 16 bits of the AX register, while exter nally the Bus Interface [...]

4-7 PERIPHERAL CONTROL BLOCK As an examp le, to relocate the Peripheral Con trol Block to the me mory range 1 0000-100FFH, the user would program the PCB Relocation Register with th e value 1100H. Since the Relocation Register is part of the Periph eral Control Block , it relocates to word 10000H plus its fixed offset. NOTE Due to an intern al cond[...]

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5 Clock Generation and Power Management[...]

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5-1 CHAPTER 5 CLOCK G ENERATION AND POWER MANAGEMENT The clo ck generation and dis tribution circuits prov i de unifo rm clock signals for the Execution Unit, the Bu s Interface Un it and all integrated peripherals. Th e 80C186 Modular Core Family processors have ad ditional logic that contro ls the clock signals to provide power management functio[...]

CLOCK GENERATION AND POWER MANAGEMENT 5-2 5.1.1.1 Oscillator Opera tion A phase shift oscillator operates through positive feedb ack, where a non-inver ted, amplified ver- sion of th e input conn ects back to the inpu t. A 3 60° phase shift around the loop wi ll sustain the feedback in the oscillator. The on-chip inverter provides a 180 ° phase s[...]

5-3 CLOCK GENERATION AND POWER MANAGEMENT Choose C 1 an d L 1 comp onent values in the third overtone crystal circuit to satisfy the fo ll owing condition s: • The LC compon ents form an equivalent ser ies resonant circuit at a freq uency below the fund amental frequency . This criterion makes the circuit indu ct ive at the fundamental frequ ency[...]

CLOCK GENERATION AND POWER MANAGEMENT 5-4 To examine th e parallel resonant frequ ency, refer to Figur e 5-3(c), an equivalen t circuit to Figure 5-3(b). The capacitance con nected to L 1 is 200 pF in par al lel with 20 pF. The equivalen t capaci- tance is still abou t 20 0 pF ( with in 10 %) and the equation in Figur e 5-4 (a) now yields the par a[...]

5-5 CLOCK GENERATION AND POWER MANAGEMENT 5.1.1.2 Selec ting Crystal s When specifying crystals, consider these parameters: • Resonance and Load Capacitance — Crystals car ry a parallel or series resonance specifi- cation. The two typ es do not dif fer in constru ct ion, just in t est conditions and expected circuit application. Parallel reson [...]

CLOCK GENERATION AND POWER MANAGEMENT 5-6 An impo rtant consideration when u sing crystals is that the oscillator st art correctly over the volt- age and temper ature ranges expected in operation. Observe oscillator startup in the lab oratory. Varying th e load capacitors (within abou t ± 50%) can optimize startup chara cteristics versus sta- bili[...]

5-7 CLOCK GENERATION AND POWER MANAGEMENT Reset may be either cold (power-up) or warm. Figure 5-6 illu strates a cold reset. Assert the RES input dur ing power supply and oscillator startup. The processor’s pins assume their reset pin states a maximum of 28 X1 per iods after X1 and V CC stabilize. Assert RES 4 additional X1 peri- ods after the de[...]

CLOCK GENERATION AND POWER MANAGEMENT 5-8 Figure 5-6. Cold Reset Wa veform RES AD15:0, S2:0 RD, WR, DEN DT/R, LOCK V cc cc V cc and X1 stable to RES high, approximately 32 X1 periods. UCS, LCS MCS3:0, NCS TMR OUT0 TMR OUT1 PCS6:0  NOTE: CLKOUT synchronization occurs 1 1/2 X1 periods after RES is sampled low. X1 CLKOUT A19[...]

5-9 CLOCK GENERATION AND POWER MANAGEMENT Figure 5-7. Wa rm Reset W aveform At the second falling CLKOUT edge after samp li n g RES inactive, the processor deasserts RE- SET. Bus activity starts 6½ CLKOUT periods after recognition of RES in the logic high state. If an alternate bus master asserts HOLD during reset, the processor immediately assert[...]

CLOCK GENERATION AND POWER MANAGEMENT 5-10 Figure 5-8. Clock Synchron iza tion at Res et 5.2 POWER MANAGEME NT Many VLSI devices available tod ay use dynamic circuitr y. A dynamic circuit uses a capacitor (usually parasitic gate or diffusion capacitan ce) to st o re information. The stored char ge decays over time due to leakage curr ents in th e s[...]

5-11 CLOCK GENERATION AND POWER MANAGEMENT 5.2.1 Power-Save Mode Power-Save mo de is a means for reducing o perating current. Power- S ave mode en ables a pro- grammable clock divider in the clock generation circuit. NOTE Power-Save mode can be used to stretch bus cycles as an alternative to wait states. Possible clock divisor s ettings are 1 ( und[...]

CLOCK GENERATION AND POWER MANAGEMENT 5-12 Figure 5-9 . Power-Save Register Register Name: Power Save Reg ister Register Mnemonic: PWRS AV Register Function: Enables and sets clock di vision factor. Bit Mnemonic Bit Name Reset State Fu nction PSEN Power Save Enable 0H Setting this bit enables Power Save mode and divides the internal operat ing cloc[...]

5-13 CLOCK GENERATION AND POWER MANAGEMENT Figure 5-10. Po wer-Save Cloc k Transition 5.2.1.2 Leav ing Power-Save Mode Power-Save mo de continues until one o f three even ts occurs: execution clears the PSEN bit in the Power-Save Register, an unmasked interr upt occurs o r an NMI occurs. When the PSEN bit clears, the clock retur ns to its undivided[...]

CLOCK GENERATION AND POWER MANAGEMENT 5-14 Examp le 5-1. Initializ ing the P ower Manageme nt Unit for Power-Save M ode $mod186 name example_PSU_code ;FUNCTION: This function reduces CPU power consumption ; by dividing the CPU operating frequency by a ; divisor. ; SYNTAX: extern void far power _save(int divisor); ; INPUTS: divisor - This variab le [...]

6 Chip-Select Unit[...]

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6-1 CHAPTER 6 CHIP-SELECT UNIT Every system require s some fo rm of component-selection m echanism to enab l e the C P U to ac- cess a specific memory or peripheral device. The signal that selects the memory or periph eral de- vice is referred to as a chip-select. Besides selecting a s pecific device, each chip-select can be used to control the num[...]

CHIP-SELECT UNIT 6-2 Figure 6-1 . Common Chip-S elect Generation Method s 6.3 CHIP-SELECT UNI T FUNCTIONAL OVERV IEW The Chip-Select Unit (CSU) decodes bus cycle address and status information an d enables the appropriate chip-select. Figure 6-3 illustrates the timing of a chip-select during a bus cycle. Note that the ch ip-select goes active in th[...]

6-3 CHIP-SELECT UNIT Figure 6 -2. Chip-Se lect Bloc k Diagram = Block Size UCS = Block Size LCS MCS3 MCS2 MCS1 MCS0 = Base Base + 0 Base + 128 Base + 256 Base + 384 Base + 512 Base + 640 Base + 768 PCS0 PCS1 PCS2 PCS3 PCS4 = Base PCS5 PCS6 MUX  A/B A B A1 A2 EX Control Bit Internal Address Bit Memory/ I/O Selector MS Internal Addr[...]

CHIP-SELECT UNIT 6-4 UCS Mapped only to the upper memory address space; selects the BOOT memory device (EPROM or Flash memo ry types). LCS Mapped only to the lower mem ory address space; selects a static memory (SRAM) device that stores the interrupt vector table, local stack, lo cal data, a n d scratch pad data. MCS3:0 Mapped only to memory add re[...]

6-5 CHIP-SELECT UNIT By combin i ng LCS , UCS and MCS3:0 , you can cover up to 786 Kb ytes of memor y address space. Methods such as those shown in Figure 6-1 on page 6-2 can be used to decode the remaining 256 Kbytes. The PCS6:0 chip-selects access a contiguous, 89 6-byte block of memo ry or I/O address space. Each chip -s e l ect g oes active for[...]

CHIP-SELECT UNIT 6-6 6.4 PROGRAMMING Four registers determine the ope rating char acter istics of the chip-selects. The Peripheral Control Block defines the location of the Chip- Select Unit registers. Table 6-1 lists the registers and their associated progr amming names. The contr ol registers (Figures 6-5 throu gh 6-7) define the base address an [...]

6-7 CHIP-SELECT UNIT Figure 6 -5. UMCS Registe r Definition Register Name: UCS Control Re giste r Register Mnemonic: UMCS Register Function: Controls the op eration o f the UCS chip-select. Bit Mnemonic Bit Name Reset State Fu nction U17:10 Start Address 0FFH Defines the start ing address for the chip-s elect. During memory bus cycles, U17:1 0 are [...]

CHIP-SELECT UNIT 6-8 Figure 6 -6. LMCS Regis ter Definition Register Name: LCS Con trol Regist er Register Mnemonic: LMCS Register Function: Controls the op eration o f the LCS chip-select. Bit Mnemonic Bit Name Reset State Fu nction U17:10 Ending Address 00H Defines the ending address for the chip-select. During memory bus cycles, U17:1 0 are comp[...]

6-9 CHIP-SELECT UNIT Figure 6 -7. MMCS Registe r Definition Register Name: MCS Con trol Regist er Register Mnemonic: MMCS Register Function: Controls the op eration o f the MCS chip-selects. Bit Mnemonic Bit Name Reset State Fu nction U19:13 Start Address XXH Defines the start ing address for the block of MCS chip-select s. During memory bus cycles[...]

CHIP-SELECT UNIT 6-10 Figure 6- 8. PACS Register Defi nition Register Name: PCS Co ntrol Register Register Mnemonic: PACS Register Function: Controls the op eration o f the PCS chip-selects. Bit Mnemonic Bit Name Reset State Fu nction U19:13 Start Address XXH Defines the start ing address for the block of PCS chip-select s. During memory or I/O bus[...]

6-11 CHIP-SELECT UNIT Figure 6-9 . MPCS Register Definition Register Name: MCS an d PCS Alternate Con trol Regi ster Register Mnemonic: MPCS Register Function: Controls operati on of the MCS and PCS chip- selects. Bit Mnemonic Bit Name Reset State Fu nction M6:0 Block Size XXH Defines the block siz e for the MCS chip-selects. Table 6-5 on page 6-14[...]

CHIP-SELECT UNIT 6-12 The UMCS and LMCS registers can be programm ed in any sequence. To pro gram th e MCS and PCS chip-selects, follow this sequence: 1. Program the MPCS register 2. Program the MMCS register to enable the MCS chip-selects. 3. Program the PACS register to enable the PCS chip-selects. 6.4.2 Programming the Active Ranges The active r[...]

6-13 CHIP-SELECT UNIT 6.4.2 .2 LCS Active Range The LCS starting add ress is fixed at zero in m emory address space; its ending address is the pr o- grammed block size m inus one. Tab le 6.3 defin es the acceptable valu es for the field (U17:1 0) in the LMCS register th at determines the LCS block size and ending address. 6.4.2 .3 MCS Active Ra nge[...]

CHIP-SELECT UNIT 6-14 Figure 6 -10. MCS3:0 Active Rang es Table 6- 5. MCS Blo ck Size and Start Address Restrictions MPCS Block Si ze Bit s Block Size (Kbytes) MMCS Sta rt Add ress Restriction s M6 M5 M4 M3 M2 M1 M0 0000001 8 None 000001 X 1 6 U13 must be zero. 00001 X X 3 2 U14:13 must be z ero. 0001 X X X 6 4 U15:13 must be z ero. 0 0 1 XXXX 1 2 [...]

6-15 CHIP-SELECT UNIT 6.4.2.4 PCS Active Range Each PCS chip-select starts at an offset abo ve the base address progr ammed in the PACS register and is active for 1 28 bytes. The base address can start on any 1 Kbyte memory or I/O address location. Tab le 6-6 lists the active range for each PCS chip-select. 6.4.3 Bus Wait State and Re ady Control N[...]

CHIP-SELECT UNIT 6-16 Figure 6 -11. Wa it State and Ready Co ntrol Functions The R2 control b it determines whether the bu s cycle completes normally (r equires bus ready) or unconditionally ( ignor es bus ready ). The R1:0 bits defin e the numb er of wait states to insert into the bus cycle. For devices requir ing three or fewer wait states, you c[...]

6-17 CHIP-SELECT UNIT For examp le, assume MCS3 overlaps UCS . MCS3 is programmed f or two wait states and re- quires bus ready, while UCS is programmed for no wait states and ignores bus ready. An access to the overlapped regio n has two wait states and requires bus read y (the values program med in the R2:0 bits in the MPCS register). Be cautious[...]

CHIP-SELECT UNIT 6-18 6.5 CHIP-SELECTS AND BUS HOLD The Chip-Select Un it decodes only internally generated ad dress and bus state information. An ex- ternal bus master cannot make use of the Chip-Select Unit. During HLDA, all ch i p-selects remain inactive. The circuit shown in Figure 6-12 allows an e xternal bus master to access a device during b[...]

6-19 CHIP-SELECT UNIT Figure 6 -13. Typ ical System L a t c h Processor ALE AD Bus Addr Bus PCS1 DRQ CE D R A M 256K ARDY 20 MCS3:0 UCS PCS0 LCS SRAM 32K Floppy Disk Control CE CE EPROM 128K CE DRQ DACK A0 A19:16 AD15:0 SRDY 4 A1138-0A[...]

CHIP-SELECT UNIT 6-20 Exam ple 6-1. Initializ ing the Chip-Select Unit $ TITLE (Chip-Select Unit Initialization) $ MOD186XREF NAME CSU_EXAMPLE_1 ; External reference from this module $ include(PCBMAP.INC ;File declares register ;locations and names. ; Module equates ; Configuration equates INTRDY EQU 0004H ;Internal bus ready mod ifier EXTRDY EQU 0[...]

6-21 CHIP-SELECT UNIT Example 6-1. In itializing the Chip -Select Unit (Continued ) DRAM_BASE EQU 256 ;window start address in Kbytes DRAM_SIZE EQU 256 ;window size in Kbytes DRAM_WAIT EQU 0 ;wait states DRAM_RDY EQU INTRDY ;ignore bus ready ;The MPCS register is used to program both the MCS and PCS chip-selec ts. ;Below are the equates for the I/O[...]

CHIP-SELECT UNIT 6-22 Example 6-1. In itializing the Chip -Select Unit (Continued ) mov dx, MPCS_REG ;ready for PCS lines 4-6 mov ax, MPCS_VAL ;as well as MCS programming out dx, al mov dx, MMCS_REG ;set up DRAM chip-selects mov ax, MMCS_VAL out dx, al mov dx, PACS_REG ;set up I/O chip-select mov ax, PACS_VAL out dx, al CODE ENDS ; ;Power-on reset [...]

7 Refresh Control Unit[...]

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7-1 CHAPTER 7 REFRESH CO NTROL UNIT The Ref re s h Control Unit (RCU) simplifies dynamic memory con t roller design with its in tegrat- ed address and clock counters. Figur e 7-1 shows the relationship between the Bus Interface Unit and the Refresh Control Unit. Integr at ing the Refresh Control Unit into the process or allows an external DRAM cont[...]

REFRESH CONTROL UNIT 7-2 7.1 THE ROLE OF THE REFRE SH CONTROL UNIT Like a DMA controller, the Refresh Con trol Unit runs bus cycles independen t of CPU execution. Unlike a DMA co ntroller, however, the Refresh Control Un it does n ot run bus cycle bu rsts nor does it transfer data. The DRAM refresh process freshens individual DRAM rows in “dummy [...]

7-3 REFRESH CONTROL UNIT Figure 7-2. Re fresh Control Unit Operation Flow Chart The nine-b it refr esh clock co unter does not wait u ntil the BI U services the refresh r equest to co n- tinue cou nting. This operation ensures that refresh requests occur at the correct interval. Other- wise, the time between r efresh requests would be a function of[...]

REFRESH CONTROL UNIT 7-4 The BIU does not queue DRAM refresh requ es ts. If the Refresh Control Unit generates ano ther request before the BIU handle s the present req uest, the BIU loses the present request. Howev er, the addr ess associated with the request is not lost. The refresh address ch anges only after the BIU runs a refresh bus cycle. If [...]

7-5 REFRESH CONTROL UNIT 7.5 REFRESH BUS CYCLES Refresh bus cycles look exactly like or dinar y memory read bus cycles ex cept fo r the con trol sig- nals listed in Table 7-1. These signals can be ANDed in a DRAM controller to detect a refresh bus cycle. The 16-bit bu s pro cessor drives both the BHE and A0 pins high during refresh cy cl es. The 8-[...]

REFRESH CONTROL UNIT 7-6 Figure 7 -4. Suggeste d DRAM Control Signal Tim ing Relati onships The cycle begins with presentation of the row address. RAS should go active on the falling edge of T2. At the rising edge of T2, the address lines should switch to a colum n address. CAS goe s active on the falling edg e o f T3. Refresh cycles do not req uir[...]

7-7 REFRESH CONTROL UNIT 7.7 PROGRAMMING THE RE FRESH CONTROL UNIT Given a specific processor operating frequency and information ab out the DRAMs in the system, the user can program the Refresh Control Unit registers. 7.7.1 Calculating the Refre sh Inter val DRAM data sheets show DRAM refresh requirem ents a s a num b er of refresh cycles necessar[...]

REFRESH CONTROL UNIT 7-8 7.7.2.1 Refresh Base Address Registe r The Refresh Base Address Register (Figure 7-6) programs the base (upper seven bits) of the re- fresh add ress. Seven-bit mapping places the refresh address at any 4 Kbyte boundary within the 1 Mbyte a ddre ss sp ace. Wh en th e partial ref resh address from the 9 -bit address counter ([...]

7-9 REFRESH CONTROL UNIT Figure 7 -7. Refresh Cloc k Interval Registe r 7.7.2.3 Refresh Control Register Figure 7-8 shows the Refresh Contro l Register. The user may read or write the REN bit at any time to turn the Refr es h Control Unit on or off. The lower nine bits contain the cu rrent nine-b i t down- counter valu e. The user cannot program th[...]

REFRESH CONTROL UNIT 7-10 Figure 7-8 . Refresh Control Register 7.7.3 Programming Exa mple Example 7-1 contains sample co de to initialize the Refresh Control Unit. Example 5-2 on page 5-14 shows the additional code to reprogram the Refresh Control Unit upo n entering Po wer-Save mode. Register Name: Refresh Control Re gister Register Mnemonic: RFC[...]

7-11 REFRESH CONTROL UNIT Exam ple 7-1. Initializ ing the Refresh Control Unit $mod186 name example_80C186_RCU_code ; FUNCTION: This function initializes the DRAM Refresh ; Control Unit to refresh the DRAM starting at dram_addr ; at clock_time intervals. ; SYNTAX: ; extern void far config_rcu(int dram_addr, int clock_time) ; ; INPUTS: dram_addr - B[...]

REFRESH CONTROL UNIT 7-12 Example 7-1. Initial izing the Refresh Co ntrol Unit (Continued) 7.8 REFRESH OPE RATION AND BUS HOLD When anoth er b us master controls th e bus, the processor keeps HLDA active as long as the HOLD input remains activ e. If the Refresh Control Unit gener ates a refresh request during bus hold, the pro ces sor drives the HL[...]

7-13 REFRESH CONTROL UNIT Figure 7 -9 . Regain ing Bus Control to Run a DRA M Refresh Bus Cy cle HLDA CLKOUT HOLD NOTES:  1. HLDA is deasserted; signaling need to run DRAM refresh cycles less than T CLHAV .  2. External bus master terminates use of the bus. 3. HOLD deasserted; greater than T HVCL . 4. Hold may be reasserted after one cl[...]

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8 Interrupt Control Unit[...]

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8-1 CHAPTER 8 INTERRU PT CONTROL UNIT The 80C186 Modular Core has a single maskable interrup t input. (See “Interr upts and Excep tion Handling” on pag e 2-39. ) The Interrup t Contro l Unit (ICU) expands th e interr upt capabilities be- yond a single inp ut. T o fulfill this function, th e Interrupt Control Unit operates in either of two modes[...]

INTERRUPT CONTROL UNIT 8-2 Interrupts eliminate the need for polling by signalling the CPU that a peripheral device requires servicing. Th e C PU then stops executing the main task, saves its state and transfers executio n to the perip heral-servicing code (the interrupt handler ). At the end of the interr upt handler, the CPU’s original state is[...]

8-3 INTERRUPT CONTROL UNIT 8.2.1.1 Interrupt Maskin g There are circu mst ances in which a pro grammer may need to d isable an interrupt so urce tempo- rarily (fo r example, while executin g a ti me-critical section of cod e or servicing a high-pr iority task). This temp orary disabling is called interrup t masking. All interru pts from th e Interr[...]

INTERRUPT CONTROL UNIT 8-4 The priority of each source is pro grammable. The Interrupt Con trol register enables the programmer to assign each source a priority that differ s from the default. The prior ity must still be between zero (h ighest) and seven (lowest) . I nterrup t sources can be programmed to share a priority. The I nterrupt Control Un[...]

8-5 INTERRUPT CONTROL UNIT 8.3 FUNCTIONAL OPERATION IN MAS TER MODE This section cove rs the process in which the In terrupt Contro l Unit receives interrup ts and asserts the maskable inter rupt requ es t to the CPU. 8.3.1 Typical Interru pt Sequence When the Interr upt Control Unit first detects an interrupt, it sets the corresponding bit in the [...]

INTERRUPT CONTROL UNIT 8-6 8.3.2.1 Priority Re solution Example This example illustrates prior ity resolution. Assume these initial conditions: • the Interr upt Control Unit h as been initialized • no interrupts are pending • no In-Service b its are set • the Interr upt Enable b it is set • all interrupts are unmasked • the defau lt pri[...]

8-7 INTERRUPT CONTROL UNIT 8.3.2.2 Interrupts That Sha r e a Single Source Multiple interru pt requests can share a single interrupt input to the Interrup t Control Unit. (For example, the three timers share a single input.) Althou gh these interrupts share an input, each ha s its own interrupt vector. (For example, when a Timer 0 interrup t occurs[...]

INTERRUPT CONTROL UNIT 8-8 Figure 8 -2. Using External 8259A Module s in Cascade Mode 8.3.3.1 Specia l Fully Nested Mode Special fully nested mode is an optional feature normally used with cascade mode. It is applicable only to I NT0 and INT1. In special f ully nested mode, an interrupt req uest is serviced even if its In-Service bit is set. In cas[...]

8-9 INTERRUPT CONTROL UNIT 8.3.4 Interrupt Acknowledge Sequence During the interru pt acknowledge sequence, the Inter rupt C ontrol Unit passes the interrupt type to the CPU. The CPU then multiplies the interrupt type by four to derive the interrupt vector ad- dress in the interrupt vector table. (“Interrupt/Exception Pro ces sing” on page 2-39[...]

INTERRUPT CONTROL UNIT 8-10 8.3.6 Edge and Level Trigger ing The exter nal interrupts (INT3:0) can b e programmed f or either ed ge or level triggerin g (see “In- terrupt Control Regi sters” on page 8-12). Both types of triggering are active high. An edge-trig- gered interrupt is generated by a zero-to-on e transition on an external interr upt [...]

8-11 INTERRUPT CONTROL UNIT Figure 8-3. Inte rrupt Contro l Unit Late ncy and Response Time 8.4 PROGRAMMING THE INTE RRUPT CONTROL UNIT Table 8-3 lists th e Interrupt Control U nit registers in master mod e with their Peripher al Control Block offset add ress es. The remainder o f this section describes the fun ctions of the registers. Table 8 -3. [...]

INTERRUPT CONTROL UNIT 8-12 8.4.1 Interrupt Control Registers Each interru pt source has its own Interrupt Control register. The Interrup t Control register allows you to defin e the behavior of each interrupt source. Figure 8-4 shows the registers for the timer s and DMA chann els, Figure 8-5 shows th e registers for INT3:2, and Figure 8-6 shows t[...]

8-13 INTERRUPT CONTROL UNIT Figure 8-4. Interrupt Control Registe r for Internal Sources Register Name: Interrupt Co ntrol Register (int ernal sources) Register Mnemonic: TCUCON, DMA0CON, DMA1CON Register Function: Control register fo r the inte rnal interrupt sou rces Bit Mnemonic Bit Name Reset State Fu nction MSK Int errupt Mask 1 Clear to enabl[...]

INTERRUPT CONTROL UNIT 8-14 . Figure 8-5. Interrupt Control Registe r for Noncasc adable External Pi ns Register Name: Interrupt Co ntrol Register (non -cascadable pi ns) Register Mnemonic: I2CON, I3CON Register Function: Control register for the non-cascadable external internal in terrupt pins Bit Mnemonic Bit Name Reset State Fu nction LVL Level-[...]

8-15 INTERRUPT CONTROL UNIT Figure 8 -6. Interrupt Control Register for Cascada ble Interrupt Pins Register Name: Interrupt Co ntrol Register (cascad able pins) Register Mnemonic: I0CON, I1CON Register Function: Control regist er for the cascada ble external interrupt pins Bit Mnemonic Bit Name Reset State Fu nction SFNM Spec ial Fully Nested Mode [...]

INTERRUPT CONTROL UNIT 8-16 8.4.2 Interrupt Request Register The Interrup t Request register (Figure 8- 7) has one bit for each interrup t s ource. When a source requests an interrupt, its Interrupt Requ es t bit is set (without regard to whether the interru pt is masked). Th e Interrupt Req uest b i t is cleared when the inter rupt is acknowledged[...]

8-17 INTERRUPT CONTROL UNIT Figure 8-8 . Interrupt Mask Re gister 8.4.4 Priority Mask Register The Priority Mask register (Figure 8-9) contains a three-leve l field that holds a priority value. This register allows you to mask interrupts based on their priority levels. Write a priority value to the PM2:0 field to specify t h e lowest priority inter[...]

INTERRUPT CONTROL UNIT 8-18 Figure 8-9 . Priority Mask Regis ter 8.4.5 In-Service Regis ter The In-Service register has a bit for each interrupt source. The bits ind icate which source’s inter- rupt hand lers are currently executing. The In-Serv ice bit i s set when an interrupt is acknowl- edged; the interrup t handler must clear it with an En d[...]

8-19 INTERRUPT CONTROL UNIT Figure 8-1 0. In-Serv ice Register 8.4.6 Poll and Poll Status R egisters The Poll and Poll Status registers allow you to poll the I nterrup t Control Unit and service inter- rupts throu gh software. You can read these registers to determine whether an interrupt is pending and, if so, the inter rupt type. The registers co[...]

INTERRUPT CONTROL UNIT 8-20 Reading the Poll register (Figure 8-11) acknowledges the pending interru pt, just as if th e C PU had started the in terrupt vectoring seq uence. The Interrupt Co ntrol Unit updates the Interrup t Re- quest, In-Ser vice, Poll, and Poll Status registers, as it does in the norm al i nterrupt ackno wl edge sequence. Ho weve[...]

8-21 INTERRUPT CONTROL UNIT Figure 8 -12. Poll Status Register 8.4.7 End-of-Interrupt (EOI) Register The End- of- Interrupt reg ister (Figure 8-1 3) i ssues an End-of -Inter rup t (EOI) command to the I n- terrupt Co ntrol Unit, which clears the In-Service bit f or the associated interrupt. An interrupt han- dler typically end s with an EOI command[...]

INTERRUPT CONTROL UNIT 8-22 Figure 8-1 3. End-of-Interrupt Register 8.4.8 Interrupt Status Register The Interrupt Status register (Figure 8 -14) contains the DMA Halt bit and one bit for each timer interrupt. The CPU sets the DMA Halt bit to suspend DMA transfers while an NMI is processed. Software can also r ead and write this bit. See “Suspensi[...]

8-23 INTERRUPT CONTROL UNIT Figure 8-14 . Interrupt Status Regi ster NOTE Do not write to the DHLT bit while Timer/Counter Unit interrupts are enabled . A conflict with the intern al use of the reg ister may cause incorrect processing of timer interru pts. The DHLT bit does not function when the interrupt controller is in slave mode. 8.5 SLAVE MODE[...]

INTERRUPT CONTROL UNIT 8-24 Figure 8 -15. Interrupt Co ntrol Unit in Slave Mode 8259A/ 82C59A INT INTA Cascade Address Decode INT0 INTA Select 80186 Modular Core V CC IRQ A1194-A0[...]

8-25 INTERRUPT CONTROL UNIT Figure 8-1 6. Interrup t Sources in Sla ve Mode 8.5.1 Slave Mode P rogramming Some reg isters differ between Slave mod e and Master m ode. Slave m ode adds th e Interrup t Vec- tor Reg ister; it does not support the Poll, Poll Status Registers, INT3 and I NT2 Contro l registers; and it replaces the Timer, INT1 and INT0 C[...]

INTERRUPT CONTROL UNIT 8-26 8.5.1.1 Interrupt Vecto r Register The Interrup t Vector Register is used only in Slave mode. In Master mode, the interr upt vector types are fixed ; in Slave m ode they are programmab le. The Interrupt Vector Register is used to specify the five most-signif icant bits of the interrupt vector type. The three least-signif[...]

8-27 INTERRUPT CONTROL UNIT Figure 8-1 7. Interrupt Vector Regis ter (Slave Mode Only) 8.5.1.2 End-Of-Interru pt Register The End- of-Interrupt (EOI) register has the same fu nction in Slave m ode as in Master mo de. However, non-spe cific EOI commands are not suppo rted, so the NSPEC bit is omitted from the register. Only sp ecific EOI commands ca[...]

INTERRUPT CONTROL UNIT 8-28 Figure 8-1 8. End-of- Interrupt Register i n Slave Mode 8.5.1.3 Other Regis ters The Priority Mask regi s ter is identical in Slave mode and Master mode. Th e Interrupt Request, Interrupt Mask, and In-Service registers retain the same fu nction , bu t indiv idual b its differ to ac- commod ate t he addition of the indivi[...]

8-29 INTERRUPT CONTROL UNIT 8.5.2 Interrupt Vectorin g in Slave Mode In Slav e mode, the ex t ernal 8259A module acts as the m as ter interrupt con troller. Therefore, in- terrupt ackn owledge cycles are required for every interrupt, includ ing those from integrated pe- ripherals. Du ring the first interr upt acknowledge cy cle, the external 825 9A[...]

INTERRUPT CONTROL UNIT 8-30 External interrupt ack nowledge cycles must be run for every maskable interrupt. Therefo re, the interrup t response time for every interru pt will be 5 5 clocks, as sho wn in Figure 8-21. Figure 8-2 1. Interrup t Response Tim e in Slave Mode 8.5.3 Initializing the Interrupt Control Unit for Master Mode Follow these step[...]

8-31 INTERRUPT CONTROL UNIT 5. Set the mask bit in th e Interrupt Mask register for any interrupts that you wish to disab le. Example 8-1 shows sample code to initialize the Interrup t C ontrol Unit. Exam ple 8-1. Initializing the Interrupt Control Unit for Maste r Mode $mod186 name example_80C186_ICU_initialization ; ;This routine configures the i[...]

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9 Timer/Counter Unit[...]

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9-1 CHAPTER 9 TIMER/COUNT ER UNIT The Timer/Counter Unit can be used in many application s . Some of these applications include a real-time clock, a squar e-wave generator and a digital one-shot. All of these can be implemented in a system design. A real-time clock can be used to update time-dependent memory variables. A square-wave gen erator can [...]

TIMER/COUNTER UNIT 9-2 Figure 9-1. Timer/Counter Unit Block Diagram Transition Latch/ Synchronizer Transition Latch/ Synchronizer Timer 0 Registers Timer 1 Registers Timer 2 Registers Output Latch Output Latch T0 Out T1 Out Counter Element CPU Interrupt Latch CPU Clock T0 In T1 In A1292-0A[...]

9-3 TIMER/COUNTER UNIT Figure 9 -2. Counte r Element Multiple xing and Timer Inp ut Synchronization T1IN T1OUT NOTES: 1. T0IN resolution time (setup time met). 2. T1IN resolution time (setup time not met). 3. Modified count value written into Timer 0 count register. 4. T1IN resolution time, count value written into Timer 1 count registe[...]

TIMER/COUNTER UNIT 9-4 Figure 9-3 . Timers 0 and 1 Flow Chart Timer Enabled (EN = 1) ? Clear Count Register Start No Yes No Yes Lo to Hi transition on input pin since last service ? Done External Clocking (EXT = 1) ? Retrigger (RTG = 1) ? Yes No No Yes Yes Did Timer 2 Reach Maxcount Last Service State[...]

9-5 TIMER/COUNTER UNIT Figure 9 -3. Tim ers 0 and 1 F low Chart (Continued) No (Use"B") No Counter =  Compare "A" ? Alternating Maxcount Regs (ALT = 1) ? Using Maxcount A (RIU = 0) ? Yes No No Yes (Use"A") Counter =  Compare "B" ? Counter =  Compare "A" ? Co[...]

TIMER/COUNTER UNIT 9-6 When conf igured for internal clocking, the Tim er/C ounter Unit uses the in put pins either to en- able timer counting or to retrigger the associated timer. Extern ally, a timer increments o n low-to- high transition s on its input pin (up to ¼ C LKOUT frequen cy). Timers 0 and 1 each have a s ingle output pin. Timer outp u[...]

9-7 TIMER/COUNTER UNIT Figure 9 -5. Time r 0 and Timer 1 Contro l Registers Register Na me: Timer 0 and 1 Control Registers Register Mnemonic: T0CON, T 1CON Register Function: Defines Ti mer 0 an d 1 operation . Bit Mnemoni c Bit Name Reset State Functio n EN Ena ble 0 Set to enable the timer. This bit can be written only when the INH bit is set. I[...]

TIMER/COUNTER UNIT 9-8 Figure 9-5. Timer 0 and Tim er 1 Control Registers (Co ntinued) Register Na me: Timer 0 and 1 Control Registers Register Mnemonic: T0CON, T 1CON Register Function: Defines Ti mer 0 an d 1 operation . Bit Mnemonic Bit Name Reset State Fu nction RTG Retrigge r X Th is bit specifies the act ion caused by a low-to-high transition[...]

9-9 TIMER/COUNTER UNIT Figure 9-6 . Timer 2 Control Regis ter Register Na me: Timer 2 Control Register Register Mnemonic: T2CON Register Function: Defines Ti mer 2 ope ration. Bit Mnemonic Bit Name Reset State Fu nction EN Enable 0 Set to enable the timer. This bit can be written only when the I NH bit is set. INH Inhibit X Set to enable writes to [...]

TIMER/COUNTER UNIT 9-10 Figure 9 -7. Timer Coun t Registers Register Name: Timer Count Re gister Register Mnemonic: T0CNT, T1CNT, T2CNT Register Function: Contains the current timer coun t. Bit Mnemonic Bit Name Reset State Fu nction TC15:0 Timer Count Value XXXXH Contains the current count of the associated timer. 15 0 T C 1 3 T C 1[...]

9-11 TIMER/COUNTER UNIT Figure 9-8. Timer Maxcount Comp are Registers 9 .2.1 Initialization Sequence When initializing the Timer / Counter Unit, t he followin g sequence is suggested: 1. If timer in t errup ts will be used, pr ogram interrupt v ectors into the Interrup t Vect or Table. 2. Clear the Timer Count register. This must be d one befo re t[...]

TIMER/COUNTER UNIT 9-12 9 .2.2 Clock Sourc es The 16-bit Timer Co unt register increments once for each t imer event. A timer even t can be a low-to-hig h transition o n a timer inpu t pin ( Timers 0 and 1), a pulse gener ated ever y fourth CPU clock (all timers) or a timeout of Timer 2 ( Tim ers 0 and 1). Up to 65536 (2 16 ) ev ents can be count- [...]

9-13 TIMER/COUNTER UNIT The timer cou nting from its initial count ( usually zero) to its maximum coun t (either Maxco unt Compare A or B) and resetting to zero defines one timing cycle. A Maxcount Compare value of 0 implies a maximum cou nt of 65 536 , a Maxcount Compare value of 1 implies a maximum count of 1, etc. Only equiv al ence between the [...]

TIMER/COUNTER UNIT 9-14 When the EXT bit is clear and the RTG bit is set, every low-to- high tran sition on the timer input pin causes the Count reg ister to reset to zero. After the timer is enabled , counting begins only after the first low-to-h igh transition on the input pin. If another low-to-hig h t r ansit io n occurs before the end of the t[...]

9-15 TIMER/COUNTER UNIT Figure 9-9 . TxOUT Sign al Timing In dual maximum count mode, the timer outpu t pin indicates which Maxcount Compar e register is currently in use. A low outp ut indicates Maxcount Compar e B, and a high output indicates Maxcoun t Co mpar e A (see Figure 9-4 on page 9-6). If prog rammed to run con tinuously, a r epet- itive [...]

TIMER/COUNTER UNIT 9-16 The inpu t pins for Timers 0 and 1 provide an alternate metho d for enabling and disabling timer counting . When using internal clocking , the input pin can be programmed either to enable the tim- er or to reset the timer co unt, depending on the state o f the Retrigger (RTG) bit in the contro l reg- ister. When used as an e[...]

9-17 TIMER/COUNTER UNIT 9 .3.2 Sy nchronization and Maximum Frequency All timer inputs ar e latched and synchron ized with the CPU clock. B ecause of the internal logic required to synchronize th e external signals, and th e multiplexing of the counter element, the Timer/Counter Unit can op erate only up to ¼ of the CLKOUT frequency . Clocking at [...]

TIMER/COUNTER UNIT 9-18 Examp le 9-1. Configuring a Real-Tim e Clock $mod186 name example_80186_family_timer_code ;FUNCTION: This function sets up the timer and interrupt controller ; to cause the timer to generate an interrupt every ; 10 milliseconds and to service interrupts to ; implement a real time clock. ; ; Timer 2 is used in this example be[...]

9-19 TIMER/COUNTER UNIT Example 9-1. Con figuring a Real-Time Clock (Continued) lib_80186 segment public ’code’ assume cs:lib_80186, ds:data public _set_time _set_time proc far push bp ;save caller’s bp mov bp, sp ;get current top of stack hour equ word ptr[bp+6] ;get parameters off stack minute equ word ptr[bp+8] second equ word ptr[bp+10] T[...]

TIMER/COUNTER UNIT 9-20 Example 9-1. Con figuring a Real-Time Clock (Continued) sti ;enable interrupts pop si ;restore saved registers pop dx pop ax pop bp ;restore caller’s bp ret _set_time endp timer_2_interrupt_routine proc far push ax ;save registers used push dx cmp _msec, 99 ;has 1 sec passed? jae bump_second ;if a bove or equal... inc _mse[...]

9-21 TIMER/COUNTER UNIT Exam ple 9-2. Configuring a Square-W ave Generator $mod186 name example_timer1_square_wave_code ;FUNCTION: This function generates a square wave of given ; frequency and duty cycle on Timer 1 output pin. ; ; SYNTAX: extern void far clock(int mark, int space) ; ; INPUTS: mark - This is the mark (1) time. ; space - This is the[...]

TIMER/COUNTER UNIT 9-22 Exampl e 9-2. Configu ring a Square-Wa ve Generator (Contin ued) Examp le 9-3. Configuring a Digi tal One-Shot pop dx ;restore saved registers pop bx pop ax pop bp ;restore caller’s bp ret _clock endp lib_80186 ends end $mod186 name example_timer1_1_shot_code ; FUNCTION: This function generates an active-low one-shot pulse[...]

9-23 TIMER/COUNTER UNIT Example 9-3. Configurin g a Digital One-Shot (Conti nued) _CMPB equ word ptr[bp+6] ;get parameter off the stack push ax ;save registers that will be push dx ;modified mov dx, T1CNT ;Clear Timer 1 Cou nter xor ax, ax out dx, al mov dx, T1CMPA ;set time before t_shot to 0 mov ax, 1 out dx, al mov dx, T1CMPB ;set pulse time mov[...]

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10 Direct Memory Access Unit[...]

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10-1 CHAPTER 10 DIRECT MEMOR Y ACCESS UNIT In many applicatio ns, large blocks of data must be transferred between memory and I/O space. A disk drive, for example, usually read s and writes data in b locks that may be th ousands of bytes long. If the CPU were required to hand le each byte of the transfer, the main tasks would suffer a severe perfo [...]

DIRECT MEMORY ACCESS UNIT 10-2 When the DMA requ est is granted, the Bus In terface Unit provides the bu s signals for the DMA transfer, while th e DMA channel provides the ad dress information for the source an d destination devices. The DMA Unit does n ot p rovid e a discrete DMA acknowledge signal, unlike other D MA contro l ler chips (an acknow[...]

10-3 DIRECT MEMORY ACCESS UNIT 10.1.1.1 DMA Transfer Directions The source an d destination ad dress es for a DMA transfer are programmable and can b e in either memory or I/O space. DMA tran sfers can be programmed for any of the follow ing four d irec- tions: • from memor y space to I/O space • from I/O space to me mory space • from memory [...]

DIRECT MEMORY ACCESS UNIT 10-4 10.1.4 External Requests External DMA requests ar e asserted on the DRQ pins. The DRQ p ins are sampled on th e falli ng edge of CLKOUT. It takes a minimum of four clocks befor e the DMA cycle is initiated by the BIU (see Figure 10-2). The DMA request is cleared four clocks before the end of the DMA cycle (effectively[...]

10-5 DIRECT MEMORY ACCESS UNIT 10.1.4.1 Source Synchroniz atio n A typical source-syn chronized transfer is shown in Figu re 1 0-3. Most DMA-driven p eripherals deassert their DRQ line only after the DMA transfer has begun. The DRQ signal must be deas- serted at least four clocks before the end of the D MA transfer ( at the T1 state of the dep osi [...]

DIRECT MEMORY ACCESS UNIT 10-6 Figure 10-4 . Destination-S ynchroniz ed Trans fers 10.1.5 Internal Requests Internal DMA requests can come fro m either Timer 2 or the system software. 10.1.5.1 Timer 2-Initiated Tra nsfers When program med for Timer 2-initiated transfers, the DMA channel perform s one D MA transfer every time th at Timer 2 reaches i[...]

10-7 DIRECT MEMORY ACCESS UNIT 10.1.6 DMA Transfer Counts Each DMA Unit maintains a prog rammable 16-b it transfer count v alue that controls the total numb er of transfers th e channel runs. Th e transfer count is decremented by one af ter each transfer (regardless of data size). The DMA channe l can be programmed to terminate transfers when the t[...]

DIRECT MEMORY ACCESS UNIT 10-8 10.1.8 DMA Unit Int errupts Each DMA channel can be programmed to generate an interrupt request when its transfer count reaches zero. 10.1.9 DMA Cycles and the BIU The DMA Unit uses the Bus Interface Unit to perform its transfers. When the DMA Unit has a pending r equest, it signals the BIU. If the BIU h as no other h[...]

10-9 DIRECT MEMORY ACCESS UNIT The last point is extr emely importan t when the two channels use different synchronization. For example, con s ider the case in which chann el 1 is programm ed for high priority and destination synchro nization and channel 0 is pr ogrammed for lo w priority and so urce synchro nization. If a DMA request occurs for bo[...]

DIRECT MEMORY ACCESS UNIT 10-10 Figure 1 0-6. Exampl es of DMA Priority 10.1.10. 1.2 Rotating Priority Channel prior it y rotates when the chan nels are program med as both high or both low priority . The highest priority is initially assigned to channel 1 of the module. After a chan nel perfor ms a trans- fer, it is assi gned the lower priority. W[...]

10-11 DIRECT MEMORY ACCESS UNIT Two 16-bit Periph eral Control Block regi sters d efine each of the 20-bit pointers. Figures 10.7 and 10.8 show th e layout of the DMA Source Pointer ad dress registers, and Figu res 10.9 and 10.10 show the layout o f the DMA Destination Pointer address registers. The DSA19:16 and DDA19:16 (h igh-order ad dress bits)[...]

DIRECT MEMORY ACCESS UNIT 10-12 Figure 10-8 . DMA Source Pointer (Low-Orde r Bits) The address space referenced by the source and destination poin ter s is progr ammed in the DMA Control Register for the channel (see Figure 10- 11 on page 10- 15) . The SMEM and DMEM bits contro l the ad dress space (memory or I/O) for source pointer an d de stinati[...]

10-13 DIRECT MEMORY ACCESS UNIT Figure 1 0-9 . DMA Destin ation Pointer (High-Order Bits) Register Name: DMA Destinati on Ad dress Pointer (Hi gh) Register Mnemonic: DxDSTH Register Function: Contains the upper 4 bits of the D MA Destination poi nter. Bit Mnemoni c Bit Name Reset State Function DDA19:16 DMA Destination Address XXXXH DDA19:16 are dr[...]

DIRECT MEMORY ACCESS UNIT 10-14 Figure 10-10 . DMA Destination Pointer (L ow-O rder Bits) 10.2.1.2 Selecting By te or Word Si z e Trans fers The WORD bit in the DMA Contro l Register (Figure 10- 11) con tr ols the d ata size for a channel. When WORD is set, the channel transfers data in 16-b i t words. By te transfers are selected by clearing th e [...]

10-15 DIRECT MEMORY ACCESS UNIT Figure 1 0-11. DMA Contro l Register Register Name: DMA Control Regist er Register Mnemonic: DxCO N Register Function: Controls DMA chan nel pa rameters. Bit Mnemonic Bit Name Reset State Fu nction DMEM Destination Address Space Select X Selects memory or I/O space for the destination pointer. Set DMEM to select memo[...]

DIRECT MEMORY ACCESS UNIT 10-16 Figure 10 -11. DMA Control R egister (Cont inued) Register Name: DMA Control Regist er Register Mnemonic: DxCO N Register Function: Controls DMA chan nel pa rameters. Bit Mnemonic Bi t Nam e Reset State Fu nction TC Term inal Count X Set TC to terminate transfe rs on Terminal Count. This bit is ignored for unsynchron[...]

10-17 DIRECT MEMORY ACCESS UNIT Figure 10 -11. DMA Control R egister (Cont inued) 10.2.1.3 Selecting t he Source of DMA Requests DMA requests can com e from either an internal source ( Timer 2) or an external source. Internal DMA requests are selected by setting the IDRQ bit in the DMA Control Register (see Figure 10-11 on page 10-15) for the chann[...]

DIRECT MEMORY ACCESS UNIT 10-18 10.2.1.4 Arming the DMA Channel Each DMA channel mu s t be armed befo re it can recognize DMA requests. A channel is armed by setting its STRT (Start) bit in the DMA Contro l Register (Figure 10-11 on page 1 0 -15). The STRT bit can be modified only if the CHG (Change Start) bit is set at the same time. The C HG bit [...]

10-19 DIRECT MEMORY ACCESS UNIT Figure 10 -12. Transfer Co unt Regist er The TC bit, when set, instructs the DMA ch annel to disarm itself (by clearing the STRT bit) when the transf er count reaches zero. If the TC bit is cleared, the chann el continues to perform transfer s regardless of the state of th e Transfer Coun t Reg ister. Unsync hron ize[...]

DIRECT MEMORY ACCESS UNIT 10-20 10.2.2 Suspension of DMA Transfer s Whenever the CPU receives an NMI, all DMA activity is suspended at the end of th e current transfer. The CPU suspends DMA activity by setting the DHLT bit in the Interrupt Status Regis- ter (Figur e 8-14 on page 8-23 ). When an IRET instruction is executed, the CPU clears the DHLT [...]

10-21 DIRECT MEMORY ACCESS UNIT 10.3.2 DMA Latency DMA Latency is the delay between a DMA request being asserted and the DMA cycle being run. The DMA latency f or a channel is contro ll ed by many factor s: • Bus H OLD — Bus HOLD takes preced ence over internal DMA requests. Using bus HOLD will degrade DMA latency . • LOCKed Instructions — [...]

DIRECT MEMORY ACCESS UNIT 10-22 10.3.4 Generating a DMA Acknowle dge The DMA channels do not provide a d istinct DMA acknowledge sign al. A chip-select line can be prog rammed to activ at e f or the memory or I/O range that requires th e acknowled ge. The chip- select must be programmed to activate only when a DMA is in pro gress . Latched status l[...]

10-23 DIRECT MEMORY ACCESS UNIT Exam ple 10-1 . Initializing the DMA Unit $MOD186 name DMA_EXAMPLE_1 ; This example shows code necessary to set up two DMA channels. ; One channel performs an unsynchronized transfer from memory to memory. ; The second channel is used by a hard disk controller located in ; I/O space. ; It is assumed that the constant[...]

DIRECT MEMORY ACCESS UNIT 10-24 Exampl e 10-1. Initializ ing the DMA Unit (Continued) MOV DX, D0DSTH MOV AX, BX ; GET HIGH NIBBLE OUT DX, AX ; THE POINTER ADDRESSES HAVE BEEN SET UP. NOW WE SET UP THE TRANSFER COUNT. MOV AX, 29 ; THE MESSAGE IS 29 BYTES LONG. MOV DX, D0TC ; XFER COUNT REG OUT DX, AX ; NOW WE NEED TO SET THE PARAMETERS FOR THE CHANN[...]

10-25 DIRECT MEMORY ACCESS UNIT Exampl e 10-1. Initializ ing the DMA Unit (Continued) MOV AX, 512 ; THE DISK READS IN 512 BYTE SECTORS MOV DX, D1TC ; XFER COUNT REG OUT DX, AX ; NOW WE NEED TO SET THE PARAMETERS FOR THE CHANNEL AS FOLL OWS: ; ; DESTINATION SOURCE ; ----------- ------ ; MEMORY SPACE I/O SPACE ; INCREMENT PTR CONSTANT PTR ; ; TERMINA[...]

DIRECT MEMORY ACCESS UNIT 10-26 Example 10-2. Timed DMA Transfers $mod186 name DMA_EXAMPLE_1 ; This example sets up the DMA Unit to perform a transfer from me mory to ; I/O space every 22 uS. The data is sent to an A/D converter. ; It is assumed that the constants for PCB register addresses are ; defined elsewhere with EQUates. CODE_SEG SEGMENT ASS[...]

10-27 DIRECT MEMORY ACCESS UNIT Example 10-2. Timed DMA Transf ers (Continued) ; NOW WE NEED TO SET THE PARAMETERS FOR THE CHANNEL AS FOLLOWS: ; ; DESTINATION SOURCE ; ----------- ------ ; I/O SPACE MEMORY SPACE ; CONSTANT PTR INCREMENT PTR ; ; TERMINATE ON TC, INTERRUPT, SOURCE SYNCHRONIZE, INTERNAL REQUESTS, ; LOW PRIORITY RELATIVE TO CHANNEL 1, [...]

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11 Math Coprocessing[...]

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11-1 CHAPTER 11 MATH C OPROCESSING The 80C186 Mod ular Core Family meets the need for a general-pur pose embedded microproces- sor. In most data control ap plicat ions, efficient data mov ement and control instruc tions are fore- most and ar ithmetic performed on the data is simple. However, some ap plications do require more powerf ul arithmetic i[...]

MATH COPROCESSING 11-2 The core has an Escape Trap (ET) bit in the P CB Relocation Register (Figur e 4-1 on page 4-2) to contro l the availability of math coprocessing. If the ET bit is set, an attempted numerics execution results in a Typ e 7 interrupt. The 80C18 7 will n ot work wit h the 8-bit bus ver sion of the processor because all 80C187 acc[...]

11-3 MATH COPROCESSING 11.3.1.1 Data Transfe r Instruction s Data transfer instructio ns move op erands between elements of the 80C187 reg ister stack or be- tween stack top an d memory. Instruc tions can co nver t any d ata type to tempo rary real and load it onto the stack in a single operation . Conversely, instru cti ons can convert a temporar [...]

MATH COPROCESSING 11-4 Available data types include temp orary real, long real, sho rt real, short integ er and word integer. The 80 C1 87 performs autom atic type conver sion to temporary re al. Table 11-2. 8 0C187 Arithmetic Ins tructions Additio n Divisi on FADD Add real FDIV Divide real FADDP Ad d real and pop FDIV P Divide real and pop FIADD I[...]

11-5 MATH COPROCESSING 11.3.1.3 Comparison Instruc tion s Each com parison instruction (see Table 11-3) analyzes the stack top element, of t en in relationship to ano t her operan d. Then it repor ts the result in the Status Wor d condition code. Th e basic oper- ations are compare, t est (compar e wi th zero) and examin e (report tag, sign and n o[...]

MATH COPROCESSING 11-6 11.3.1.5 Constant Ins tructions Each constant instruction ( s ee Table 11-5) loads a common ly used constant onto the stack. The values have full 80 -bit precision and are accurate to about 19 decimal digi t s. Since a temporary real constant o ccup ies 10 me mory bytes, the constant instructions, on ly 2 bytes long , sav e m[...]

11-7 MATH COPROCESSING 11.3.2 80C187 Data Types The micropro ces sor/math coprocessor combination supports seven data types: • Word Integer — A signed 16-bit numeric value. All operations assume a 2’ s complement representation. • Short Integ er — A signed 32-bit numeric value (doub le word). All operation s assume a 2’s complemen t rep[...]

MATH COPROCESSING 11-8 Figure 11-1. 8 0C187-Sup ported Data Types Increasing Significance Word Integer Packed Decimal Short Real Temporary Real (Two's Complement) Short Integer Long Integer Long Real S 0 Magnitude 15 S 0 31 Magnitude (Two's Complement) (Two's Complement) S 0 63 Magnitude 72 79 Magnitude S 0 Biased Exponent Significan[...]

11-9 MATH COPROCESSING Figure 11-2 . 80C186 Modular Core Family/80C187 Sy stem Configuration ALE PEREQ RESET PEREQ 80C187 CKM NPS2 80C186 Modular Core Latch D15:0 External Oscillator CLKOUT RESET WR RD NCS ERROR NPS1 CLK NPWR NPRD BUSY BUSY ERROR 1 2 A2 A1 CMD0 CMD1 EN AD15:0 A1529-0A[...]

MATH COPROCESSING 11-10 11.4.1 Clocking the 80C187 The micropr ocessor and math copr ocess or operate asynchron ously, and their clock rates may dif- fer. The 80C187 has a CKM pin that determines whether it uses the inp ut cl ock directly or divided by two. Direct clocking works up to 12.5 MHz, which makes it convenient to feed the clock input from[...]

11-11 MATH COPROCESSING Bus cycles involving the 80C187 Math Coprocessor behave ex actly like other I/O bus cycles with respect to the processor’s co ntrol pins. See “System Design Tips” for inform ati on on integrating the 80C18 7 into the ov erall syst em. 11.4.3 System Design Tips All 80C187 operatio ns require that bus ready be asserted. [...]

MATH COPROCESSING 11-12 Figure 11- 3. 80C187 Configura tion with a Partially Buffe red Bus ALE PEREQ RESET PEREQ EN 80C187 CKM NPS2 80C186 Modular Core Latch D15:0 External Oscillator CLKOUT RESET WR RD CLK NPRD BUSY BUSY ERROR TO E D15:8 TO E Buffer Buffer A15:0 D7:0 ERROR 1 NPS1 NPWR NCS CS DEN DT/R A1 A2 CMD0 CMD1 AD15:0 2 A1530-0 A[...]

11-13 MATH COPROCESSING 11.4.4 Exception Trapping The 80C187 d etects six error condition s that can occur durin g instruction execu tion. The 80C18 7 can ap ply default fix- ups or signal ex ceptions to th e microprocessor’s ERROR pin . The processor tests ERR OR at the beginn ing of n umerics in s tructions, so it tr aps an exception on the nex[...]

MATH COPROCESSING 11-14 Figure 11 -4. 80C18 7 Exception Trapp ing via Processor In terrupt Pin INT x CLKOUT D15:0 CMD1 CMD0 PEREQ BUSY ALE A19:A16 AD15:0 RESET CKM NPS2 Q D Q D EN D15:0 A19:0 A2 A1 80C187 RESET 80C186 Modular Core BUSY PEREQ '74 '74 CLK Latch ERROR NPWR WR RD NCS CS x C Q S ERROR NPS1 NPRD C S A d d r e?[...]

11-15 MATH COPROCESSING Example 11-1. I nitialization Sequ ence for 80C187 Math Coprocessor $mod186 name example_80C187_init ; ;FUNCTION: This function initializes the 80C187 numerics coprocessor. ; ;SYNTAX: extern unsigned char far 187_init(void); ; ;INPUTS: None ; ;OUTPUTS: unsigned char - 0000h -> False -> coprocessor not initialized ; fff[...]

MATH COPROCESSING 11-16 Example 11-2. Floating Poi nt Math Routine Using FSINCOS $mod186 $modc187 name example_80C187_proc ;DESCRIPTION: This code section uses the 80C187 FSINCOS transcendental ; instruction to convert the locus of a point from polar ; to Cartesian coordinates. ; ;VARIABLES: The variables consist of the radius, r, and the angle, th[...]

12 ONCE Mode[...]

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12-1 CHAPTER 12 ONCE MODE ONCE (pronounced “ahn ce”) Mode provides the ability to three-state all output, bidirectional, or weakly held high/low pin s except OSCOUT. To allow device operation with a crystal network, OSCOUT does not three-state. ONCE Mode electrically isolates the device from the rest of the board logic. This isolation all ows a[...]

ONCE MODE 12-2 Figure 1 2-1. Enteri ng/Leaving ONCE Mode RES UCS LCS All output, bidirectional, weakly held pins except OSCOUT NOTES: 1. Entering ONCE Mode. 2. Latching ONCE Mode. 3. Leaving ONCE Mode (assuming 2 occurred). 1 2 3 A1532-0A[...]

A 80C186 Instruction Set Additions and Extensions[...]

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A-1 APPENDIX A 80C186 INST RUCT ION SET ADDITIO NS AND EXTENSIONS The 80C18 6 Mo dular Core family instruction set differ s from the orig inal 808 6/8088 instru ction set in two ways. First, several instructions that were n ot available in the 8086/8088 instruction set have been added. Second, several 80 86/8088 instruc t ions have been en hanced f[...]

80C186 INST RU CTION SET ADDITIONS AND EXTENSIONS A-2 A.1.2 Stri ng Instructions INS source_string, port INS (in string) perf orms block input from an I/O port to memor y. The port address is placed in the DX register. The memory addr es s is placed in the DI register. This instruction uses the ES segment reg i ster (which cannot b e o verridd en).[...]

A-3 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS Figure A-1. Formal De finition of ENTER ENTER treats a reentrant p roced ure as a proce dure calling another pro cedure at the same lexical level. A reentran t procedure can ad dress only its own variables and variables of higher-level call- ing procedu res. ENTER ensures this by copy ing only sta[...]

80C186 INST RU CTION SET ADDITIONS AND EXTENSIONS A-4 Figure A-2. Variable Access in Nested Procedure s The first ENTER, executed in the Main Program , al locates dynamic storage space for M ain, but no pointers are co pied. The only word in the display points to itself bec aus e no previous value exists to return to after LEAVE is executed (see Fi[...]

A-5 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS Figure A-4 . Stack Frame for Procedure A at Lev el 2 After Procedu re A calls Procedure B, ENTER creates the display for Procedure B. Th e first word of the display points to the prev i ous value of BP (BPA). The second word points to the value of BP for MAIN (BPM). The third word po i nts to the [...]

80C186 INST RU CTION SET ADDITIONS AND EXTENSIONS A-6 Figure A-5. Stack Fra me for Procedure B at Level 3 Calle d from A A1004-0A Old BP BP SP 15 0 BPM BPM BPM Display B Dynamic Storage B BPA BPM BPA BPA BPB[...]

A-7 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS Figure A-6. Stack Fra me for Procedure C at Level 3 Calle d from B LEAVE LEAVE reverses the action of the mo s t recent ENTER instruction . It collapses the last stack frame created. First, LEAVE copies the current BP to the Stack Pointer, releasing the stack space allocated to the cu rrent proced[...]

80C186 INST RU CTION SET ADDITIONS AND EXTENSIONS A-8 BOUND register, address BOUND verifies that the signed value in the specified r egis ter lies wi thin specified limits. If the value does not lie within the bounds, an ar ray bounds exceptio n (type 5) occurs. BOUND is useful for check ing array bound s before attempting to access an array eleme[...]

A-9 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS A.2.2 Arithmetic Instructions IMUL desti nation, source, data IMUL (integer immediate multiply, sig ned) allows a value to be multip lied by an immediate op- erand. IMUL requires three oper ands. The first, destination , i s the register where the result will be placed. The seco nd, sou rce , is t[...]

80C186 INST RU CTION SET ADDITIONS AND EXTENSIONS A-10 A.2.3.2 Rotate Instruc tions ROL destination, co unt ROL (immediate rotate left) rotates the destination byte or word left by an immediate value. ROL has two operan ds. The first, d estination , is the effective ad dress to be ro tated. The secon d, count , is an immediate byte value representi[...]

B Input Synchronization[...]

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B-1 APPENDIX B INPUT SYNCH RONIZATIO N Many input signals to an embed ded processor are asynchro n ous. Asynchr onous signals do not re- quire a specified setup or h old time to ensur e the device d oes not incur a failure. Ho wever, asyn- chron ous setup and hold times are specified in the data sheet to en su re recognition . Associated with each [...]

INPUT SYNCHRONIZATION B-2 A synchronization failure can occur when the output of the first latch does not meet the setup and hold requ irements of the input of the second latch. The rate o f failur e is determ in ed by the actual size of the samp ling window of the data latch and by the amount of time be tween the strobe sig- nals of the two latche[...]

C Instruction Set Descriptions[...]

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C-1 APPENDIX C INSTRUCT IO N SET DESCRIPT IONS This appendix pro vides reference info rmation for the 80C186 Modular Core family instruction set. Tables C-1 through C- 3 defin e the variables u s ed in Table C-4, wh ich lists the instruction s with their descriptions and operations. Table C-1. Instruc tion Format Variables Variable Description dest[...]

INSTRUCTION SET DESCRIPTIONS C-2 Table C-2. Instruc tion Operand s Operand Descrip tion reg An 8- or 16-bit general regist er. reg16 An 16-bit general register. seg-reg A segment register. accum Register AX or AL immed A constant in the range 0–FFFFH. immed8 A constant in the range 0–FFH. mem An 8- or 16-bit memor y location. mem16 A 16-bit mem[...]

C-3 INSTRUCTION SET DESCRIPTIONS Table C-3. Fla g Bit Functi ons Name F unctio n AF Auxiliary Flag: Set on carry from or borrow to the low order four bits of AL; cleared other wise. CF Carry Flag: Set on high-order bit carry or borrow; cleared otherwise. DF Direction Flag: Causes string instruct ions to auto decr ement the appropriate index registe[...]

INSTRUCTION SET DESCRIPTIONS C-4 Table C-4. Instruction Se t Name Description Operation Flags Affected AAA ASCII Ad just fo r Add ition : AAA Changes the contents of register A L to a valid unpacked decimal number; the high-order half-byt e is zeroed. Instructi o n Operan d s : none if (( AL) and 0FH) > 9 or ( AF) = 1 then ( AL) ← ( AL) + 6 ( [...]

C-5 INSTRUCTION SET DESCRIPTIONS AAS ASCII Ad just for Sub tracti on : AAS Corrects the result of a previous subtractio n of two val id unpacked decimal operands (the destination operand must have been specified as register AL). Changes the c ontent of AL to a valid unpacked decimal number; the high-order half-byte is zeroed. Instruction Op eran ds[...]

INSTRUCTION SET DESCRIPTIONS C-6 ADD Additi on : ADD dest , src Sums two operands, which may be bytes or words, rep laces the destination operand. Both operands may be signed or unsigned binary numbers (see AAA and DAA) . Instructi o n Operan d s : ADD reg, reg ADD reg, mem ADD me m, reg ADD reg, immed ADD mem, immed ADD accum , immed (dest) ← (d[...]

C-7 INSTRUCTION SET DESCRIPTIONS BOUND Detect Value Out of Range : BOUND dest , src Provides array bounds chec king in hardware. The calculated array index is placed in one of the gener al purpose registers, and the upper and lower bounds of the array are placed in two consecutive m emory locations. The contents of the register are com pared with t[...]

INSTRUCTION SET DESCRIPTIONS C-8 CBW Con vert Byte to Word : CBW Extends the sign of the byte in register AL throughout register AH. Use t o produce a double-lengt h (word) dividend from a byte prior to performing byte division. Instructi o n Operan d s : none if ( AL) < 80H then ( AH) ← 0 else ( AH) ← FFH AF – CF – DF – IF – OF – [...]

C-9 INSTRUCTION SET DESCRIPTIONS CLI Clear Interrupt-en abl e Flag : CLI Zeroes the interrupt-enab le flag (IF). When the int errupt-enable flag is cleared, the 8086 and 8088 do not recognize an external int errupt request that appears on the INT R line; in other words maskable interrupts are disabled. A non-maskable interrupt appearing on NMI line[...]

INSTRUCTION SET DESCRIPTIONS C-10 CMP Comp are : CMP dest , src Subtracts the s ource from the desti- nation, which may be bytes or words, but does not return the resu lt. The operands are unchanged, but the flags are updated and can be tested by a subsequent con ditional jump instruction. Th e comparison ref lected in the flags is that of the dest[...]

C-11 INSTRUCTION SET DESCRIPTIONS CWD Convert W o rd to Dou blew ord : CWD Extends the sign of the word in register AX throughout register DX. Use t o produce a double-length (doubleword) dividend from a word prior to performing word division. Instruction Op eran ds : none if ( AX) < 8000H then (DX) ← 0 else (DX) ← FFFFH AF – CF – DF –[...]

INSTRUCTION SET DESCRIPTIONS C-12 DEC Decrement : DEC dest Subtracts one from the dest ination operand. The operand may be a byte or a word and is treated as an unsigned binary num ber (see AAA and DAA). Instructi o n Operan d s: DEC reg DEC mem (dest) ← (dest) – 1 AF CF – DF – IF – OF PF SF TF – ZF Table C-4. Instruc tion Set (Continue[...]

C-13 INSTRUCTION SET DESCRIPTIONS DIV Divide : DIV src Performs an unsigned division of the accumulator (and it s extension) by t he source operand. If the source operand is a byte, it is divided into the two-by te dividend assumed to be in registers AL and AH. The byte quotient is returned in AL, and the byte remainder is ret urned in AH. If the s[...]

INSTRUCTION SET DESCRIPTIONS C-14 ENTER Procedure Entry : ENTER locals, levels Executes the calling sequence for a high-level language. It saves the current frame point er in BP, copies the frame pointers from procedures below the current call (to a llow access to local variables in these procedures) and allocates space on the stack for the local v[...]

C-15 INSTRUCTION SET DESCRIPTIONS HLT Halt : HLT Causes the CPU to enter the halt state. The process or leaves the halt state upon activation of the RESET line, upon receipt of a non-mask able interrupt request on NMI, or upon receipt of a maskab le interrupt request on INTR (if interrupts are ena bled). Instructi on Operands : none None AF – CF [...]

INSTRUCTION SET DESCRIPTIONS C-16 IDIV Integer Divi d e : IDIV src Performs a signed division of the accumulator (and its extension) by the source operand. If the source operand is a byte, it is divided into the double- length dividend assumed to be in registers AL and AH; the single-length quotient is returned in AL, and the single-length remainde[...]

C-17 INSTRUCTION SET DESCRIPTIONS IMUL In teger M ultip ly : IMUL src Performs a signed mu ltiplication of the source operand and the accumulator. If the source is a byte, then it is multiplied by register AL, and the double-length result is returned in AH and AL. If the source is a word, then it is multiplied by register AX, and the double-length [...]

INSTRUCTION SET DESCRIPTIONS C-18 INC Increment : INC dest Adds one t o the destinat ion operand. The operand may be byte or a word and is treated as an unsigned binary number (see AAA a nd DAA). Instructi on Operand s : INC reg INC mem (dest) ← (dest) + 1 AF CF – DF – IF – OF PF SF TF – ZF INS In String : INS dest-string, port Performs b[...]

C-19 INSTRUCTION SET DESCRIPTIONS INT Interrupt : INT interrupt-type Activates the in terru pt procedur e specified by the int errupt-type operand. De crements the stack pointer by two, pushes the flags onto the stack, and clears the trap (TF) and interrupt-enable (IF) flags to disable single-step and maskable interrupts. The flags are store d in t[...]

INSTRUCTION SET DESCRIPTIONS C-20 INTO Interrupt o n Overflow : INTO Generates a soft ware interrupt if the overflow flag (OF) is set; otherwise control proceeds to the following instruction without act ivating an interrupt procedure. INTO address es the target interrupt proc edure (its type is 4) through the interrupt pointer at location 10H; it c[...]

C-21 INSTRUCTION SET DESCRIPTIONS JAE JNB Jump on Above or Equal : Jump on Not Belo w : JAE disp8 JNB disp8 Transfers control to t he target locat ion if the tested condition (CF = 0) is true. Instructi on Operands : JAE short -label JNB short-label if (CF) = 0 then (IP) ← (IP) + dis p8 (s ign-ext t o 16 bits) AF – CF – DF – IF – OF – P[...]

INSTRUCTION SET DESCRIPTIONS C-22 JCXZ Jump if CX Zero : JCXZ disp8 Transfers cont rol to the targ et location if CX is 0. Useful at the beginning of a loop to bypass the loop if CX has a zero value, i.e., to execute the loop zero times. Instructi on Operand s : JCXZ short- label if (CX) = 0 then (IP) ← (IP) + disp8 (sign-ext to 16 bits) AF – C[...]

C-23 INSTRUCTION SET DESCRIPTIONS JL JNGE Jump on Less Th an : Jump on Not Greater Than or Eq u al : JL disp8 JNGE disp8 Transfers control to t he target locat ion if the condition tested (SF ≠ OF) is true . Instructi on Operands : JL short-label JNGE short-label if (SF) ≠ (OF) then (IP) ← (IP) + dis p8 (sign-ext to 16 bits) AF – CF – DF [...]

INSTRUCTION SET DESCRIPTIONS C-24 JNE JNZ Jump on Not Equ al : Jump o n Not Zero : JNE disp 8 JNZ disp8 Transfers cont rol to the targ et location if the tested condition (ZF = 0) is true. Instructi on Operand s : JNE short -label JNZ short-label if (ZF ) = 0 then (IP) ← (IP ) + disp8 (sign-ext to 16 bits) AF – CF – DF – IF – OF – PF ?[...]

C-25 INSTRUCTION SET DESCRIPTIONS JO Jump on Overflow : JO disp8 Transfers control to t he target locat ion if the tested condition (OF = 1) is true. Instruction Op eran ds : JO short- labe l if (OF) = 1 then (IP) ← (I P) + disp8 (s ign-ext to 16 bits) AF – CF – DF – IF – OF – PF – SF – TF – ZF – JP JPE Jump on Parity : Jump on [...]

INSTRUCTION SET DESCRIPTIONS C-26 LDS Load Pointer Usi ng DS : LDS dest, src Transfers a 32-bit pointer variable from the source operand, which must be a memory operand, to the dest ination operand and regist er DS. The offs et word of the po inter is transferred to th e destination operand, which may be any 16-bit general register. The segment wor[...]

C-27 INSTRUCTION SET DESCRIPTIONS LES Load P ointer U sing E S : LES dest, src Transfers a 32-bit pointer variable from the source operand to the destination operand and register ES. The offset word of the pointer is transf erred to the destination op erand. The s egment word of the pointer is transferred to register ES. Instruction Op eran ds : LE[...]

INSTRUCTION SET DESCRIPTIONS C-28 LODS Lo ad Stri ng (Byte or Wo rd) : LODS src-string Transfers t he byte or word string element addressed by SI to register AL or AX and updates SI to point to the next e lement in the string. This instruction is not ordinarily repeat ed since the ac cumulator would be overwritten by each repetition, and only the l[...]

C-29 INSTRUCTION SET DESCRIPTIONS LOOPNE LOOP NZ Loop Whi le Not Equal : Loop W hile Not Zero : LOOPNE disp8 LOOP NZ disp8 Decrements CX by 1 and transfers control to t he target loca tion if CX is not 0 and if ZF is clear; otherwise the next sequenti al instruction is ex ecute d. Instruction Op eran ds : LOOPNE shor t-label LOOPNZ short-label (CX)[...]

INSTRUCTION SET DESCRIPTIONS C-30 MOVS Move String : MOVS dest-string, src -st ring Transfers a byte or a word from the source string (addressed by SI ) to the destination string (addresse d by DI) and updates SI and DI to point to the next string element. When used in conjunction with REP, MOVS performs a memory -to-memory block transfer. Instruct[...]

C-31 INSTRUCTION SET DESCRIPTIONS NEG Negate : NEG dest Subtracts the dest ination operand, which may be a byte or a word, from 0 and returns the result to the desti- nation. This forms the tw o's complement of the num ber, effect ively reversing the s ign of an integer. If t he operand is zero, its sign is not changed. Attempt ing to negate a[...]

INSTRUCTION SET DESCRIPTIONS C-32 OR Logical O R : OR dest,src Performs the logical "inclusive or" of the two operands (bytes or words) and returns the result to the dest ination operand. A bit in the result is set if either or both corresponding bits in t he original operands are s et; otherwise the result bit is cleared. Instructi o n O[...]

C-33 INSTRUCTION SET DESCRIPTIONS OUTS Out St rin g : OUTS port, src_st ring Performs block o utput from memory to an I/O port. The port address is placed in the DX re gister. T he mem ory address is placed in the SI register. This instruction uses the DS segm ent register, but this may be changed with a segment ov erride instruc tion. A fter the d[...]

INSTRUCTION SET DESCRIPTIONS C-34 POPA Po p All : POPA Pops all data, pointer, and index registers off of the stack. The SP value popped is discarded. Instructi o n Operan d s : none (DI) ← ((S P) + 1: (SP)) (SP) ← (S P) + 2 (SI) ← ((SP) + 1:(SP)) (SP) ← (S P) + 2 (BP) ← (( SP) + 1:(SP)) (SP) ← (S P) + 2 (BX) ← (( SP) + 1:(SP)) (SP) ?[...]

C-35 INSTRUCTION SET DESCRIPTIONS PUSHA Push All : PUSHA Pushes all data, pointer, and index registers onto the stack . The order in which the registers are saved is: AX, CX, DX, BX, SP, BP, SI, and DI. The SP value pushed is the SP value before the first register ( AX) is pushed. Instruction Op eran ds : none temp ← (SP) (SP) ← (S P) – 2 ((S[...]

INSTRUCTION SET DESCRIPTIONS C-36 RCL Rotate Thro u gh Carry Left : RCL dest, count Rotates the bits in the byte or word destination operand to the left by the number of bits specified in the count operand. The c arry flag (CF) is treated as "part of" the destination operand; that is, its value is rotated into the low- order bit of the de[...]

C-37 INSTRUCTION SET DESCRIPTIONS REP REPE REPZ REPNE REPNZ Repeat : Repeat Wh ile Eq ual : Repeat Wh ile Zero : Repeat Wh ile Not Equal : Repeat Wh ile Not Zero : Controls subsequent string instruction repetition. The different mnem on ics are provided to improve program clarity. REP is used in conjunction with the MOVS (M ove String) and STOS (St[...]

INSTRUCTION SET DESCRIPTIONS C-38 RET Return : RET optional-pop-value Transfers cont rol from a procedure back to the instruction following the CALL that activated t he procedure. The assem bler generates an intra- segment RET if the programme r has defined the procedure near, or an intersegment RE T if the procedure has been defined as far. RET po[...]

C-39 INSTRUCTION SET DESCRIPTIONS ROR Rotate Rig h t : ROR dest, count Operates s imilar t o ROL except that the bits in the destination byte or word are rotated righ t instead of left . Instruction Op eran ds : ROR reg, n ROR mem, n ROR reg, CL ROR mem, CL (temp) ← count do while (tem p) ≠ 0 (CF) ← low-order bit of (des t) (dest) ← (des t)[...]

INSTRUCTION SET DESCRIPTIONS C-40 SHL SAL Shift Logical Left : Shift Arith met ic Lef t : SHL dest, count SAL dest, count Shifts the des tination byte or word left by the number of bits specified in the count operand. Zeros are shifted in on the right. If the sign bit retains its original value, then OF is cleared. Instructi o n Operan d s : SHL re[...]

C-41 INSTRUCTION SET DESCRIPTIONS SBB Sub tract With Borro w : SBB dest, src Subtracts the sourc e from the desti- nation, subtracts one if CF is set, and returns the result to the destination operand. Both operands m ay be bytes or words. Both operands may be signed or unsigned binary numbers (see AAS and DAS) Instruction Op eran ds : SBB reg, reg[...]

INSTRUCTION SET DESCRIPTIONS C-42 SCAS Scan Stri n g : SCAS dest-string Subtracts the des tination string element (byte or word) addressed by DI from the co ntent of AL ( byte st ring) or AX (word string) and updates the flags, but does not alt er the destination string or t he accum ulator. SCAS also updates DI to point to the next string element [...]

C-43 INSTRUCTION SET DESCRIPTIONS SHR Shif t Lo gical Righ t : SHR dest, src Shifts the bits in the destina tion operand (byte or word) to t he right by the number of bits specified in the count operand. Zeros are shifted in on the left. If the sign bit retains its original value, then OF is cleared. Instruction Op eran ds : SHR reg, n SHR mem, n S[...]

INSTRUCTION SET DESCRIPTIONS C-44 STI Set Interrupt-en able Flag : STI Sets IF to 1, enabling process or recognition of maskable interrupt requests appearing on the INTR l ine. Note however, that a pending int errupt will not actually be recognized unt il the instruction f ollowing ST I has exe cuted. Instructi o n Operan d s : none (IF) ← 1 AF ?[...]

C-45 INSTRUCTION SET DESCRIPTIONS SUB Subtract : SUB dest, src The source operand is subtract ed from the destination oper and, and th e result replaces the destination operand. The operands may be bytes or words. Both operands may be signed or unsigned binary numbers (see AAS and DAS). Instruction Op eran ds : SUB reg, reg SUB reg, mem SUB mem, re[...]

INSTRUCTION SET DESCRIPTIONS C-46 WAIT W ait : WAIT Causes the CPU t o enter the wa it state while its test line is not active. Instructi o n Operan d s : none None AF – CF – DF – IF – OF – PF – SF – TF – ZF – XCHG Exchan ge : XCHG dest, src Switches the contents of the source and destination operands (byt es or words). When used [...]

C-47 INSTRUCTION SET DESCRIPTIONS XLAT Transl ate : XLAT translate-table Replaces a byte in the AL regist er with a byte from a 256-byte, user-c oded translation table. Register BX is assumed to point to the beginning of the table. The byte in AL is used as an index into the table and is replaced by the byte at the offset in the table corre- spondi[...]

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D Instruction Set Opcodes and Clock Cycles[...]

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D-1 APPENDIX D INSTRUC TION SET OPCO DES AND CLOCK C YCLES This appen dix provides reference information for the 80C186 Modu lar Core family instruction set. Table D-1 def ines the variables used in Table D-2, w hich lists the instru ctions with the ir for- mats and execution times. Table D-3 is a guide for decod ing machine instructions. Table D-4[...]

INSTRUCTION SET OPCODES AND CLOCK CYCLES D-2 Table D-2. Inst ruction Set Summary Function Format C locks Notes DATA TRANSFER INSTRUCTIONS MOV = Move register to r egister/me mory 1 0 0 0 1 0 0 w mod reg r /m 2/12 register/me mory to re gister 1 0 0 0 1 0 1 w mod reg r / m 2/9 immediate to register/memory 1 1 0 0 0 1 1 w mod 000 r /m data data if w=[...]

D-3 INSTRUCTION SET OPCODES AND CLOCK CYCLES DATA TRANSFER INSTRUCTIONS (Continued) LEA = Load EA to r egister 1 0 0 0 1 1 0 1 mod reg r /m 6 LDS = Load pointer to DS 1 1 0 0 0 1 0 1 mod reg r/m (mod ?11) 18 LES = Load pointer to ES 1 1 0 0 0 1 0 0 mod reg r/m (mod ?11) 18 ENTER = Build stack frame 1 1 0 0 1 0 0 0 data-low data-high L L = 0 15 L = [...]

INSTRUCTION SET OPCODES AND CLOCK CYCLES D-4 ARITHMETIC INSTRUCTIONS (Cont inued) SUB = Subtr act reg/memo ry with register to either 0 0 1 0 1 0 d w mod reg r / m 3/10 immediate fr om register/memory 1 0 0 0 0 0 s w mod 101 r /m data data if sw=01 4/16 immediate fr om accumulator 0 0 0 1 1 1 0 w data data if w=1 3/4 (1) SBB = Subtr act with borrow[...]

D-5 INSTRUCTION SET OPCODES AND CLOCK CYCLES ARITHMETIC INSTRUCTIONS (Cont inued) AAM = A SCII adjust for multip ly 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 19 DIV = Divide (unsigned) 1 1 1 1 0 1 1 w mod 110 r/m register-byt e 29 register-wor d 38 memory-b yte 35 memory-wo r d 44 IDIV = Integer divide ( signed) 1 1 1 1 0 1 1 w mod 111 r /m register-byt e 29[...]

INSTRUCTION SET OPCODES AND CLOCK CYCLES D-6 BIT MANIPULATION INSTRUCTIONS ( Continued) TEST = And function to f l ags, no result register/me mory and r egister 1 0 0 0 0 1 0 w mod reg r/m 3/10 immediate da ta and register/m emory 1 1 1 1 0 1 1 w mod 000 r /m data data if w=1 4/10 immediate da ta and accumulator 1 0 1 0 1 0 0 w data data if w=1 3/4[...]

D-7 INSTRUCTION SET OPCODES AND CLOCK CYCLES PROGRAM TRANSFER INSTRUCTIONS Conditio nal Trans fers — jump if: JE/JZ = equal/zero 0 1 1 1 0 1 0 0 disp 4/13 (2) JL/JNGE = less/ not greater or equal 0 1 1 1 1 1 0 0 disp 4/13 (2) JLE/JNG = less or eq ual/not greater 0 1 1 1 1 1 1 0 disp 4/13 (2) JB/JNAE = below/not above or equal 0 1 1 1 0 0 1 0 disp[...]

INSTRUCTION SET OPCODES AND CLOCK CYCLES D-8 PROGRAM TRANSFER INSTRUCTIONS (Continued) RET = Return from pro cedure within segment 1 1 0 0 0 0 1 1 16 within segment a dding immed to SP 1 1 0 0 0 0 1 0 data-low data-high 18 intersegmen t 1 1 0 0 1 0 1 1 22 intersegmen t adding imm ed to SP 1 1 0 0 1 0 1 0 data-low data-high 25 JMP = Unconditional ju[...]

D-9 INSTRUCTION SET OPCODES AND CLOCK CYCLES PROCESSOR CONTROL INSTRUCTIONS CLC = Clear carry 1 1 1 1 1 0 0 0 2 CMC = Complement carry 1 1 1 1 0 1 0 1 2 STC = Set carry 1 1 1 1 1 0 0 1 2 CLD = Clear direction 1 1 1 1 1 1 0 0 2 STD = Set direction 1 1 1 1 1 1 0 1 2 CLI = Clear inter rupt 1 1 1 1 1 0 1 0 2 STI = Se t interrupt 1 1 1 1 1 0 1 1 2 HLT =[...]

INSTRUCTION SET OPCODES AND CLOCK CYCLES D-10 09 0000 10 01 mod reg r /m (disp-lo),(disp-h i) or reg16/me m16,reg16 0A 0000 1010 mod reg r/m (disp-lo),(disp-h i ) or reg8,reg8/mem 8 0B 0000 1011 mod reg r/m (disp-lo),(disp-h i ) or reg16,reg16/m em16 0C 0000 11 00 data-8 or AL, imme d8 0D 0000 11 01 data-lo data-hi or AX,immed16 0E 0000 1110 push C[...]

D-11 INSTRUCTION SET OPCODES AND CLOCK CYCLES 2E 0010 1110 DS: (segment override pr efix) 2F 0010 1111 das 30 0011 00 00 mod reg r /m (disp-lo),(disp-h i) xor reg8/mem8,re g8 31 0011 00 01 mod reg r /m (disp-lo),(disp-h i) xor reg16/mem16, reg16 32 0011 00 10 mod reg r /m (disp-lo),(disp-h i) xor reg8,reg8/mem 8 33 0011 00 11 mod reg r /m (disp-lo)[...]

INSTRUCTION SET OPCODES AND CLOCK CYCLES D-12 53 0101 00 11 push BX 54 0101 01 00 push SP 55 0101 01 01 push BP 56 0101 01 10 push SI 57 0101 01 11 push DI 58 0101 10 00 pop AX 59 0101 10 01 pop CX 5A 0101 1010 pop DX 5B 0101 1011 pop B X 5C 0101 11 00 pop SP 5D 0101 11 01 pop BP 5E 0101 1110 pop S I 5F 0101 1111 pop DI 60 0110 00 00 pusha 61 0110 [...]

D-13 INSTRUCTION SET OPCODES AND CLOCK CYCLES 7E 0111 11 10 IP-inc-8 jle/jng short-label 7F 0111 1111 IP -inc-8 jnle/jg short-label 80 1000 00 00 mod 000 r /m (disp-lo),(disp-h i ), data-8 add reg8/mem 8,immed8 mod 001 r / m (disp-lo),(disp-h i ), data-8 or reg8/mem8,imm ed8 mod 010 r / m (disp-lo),(disp-h i ), data-8 adc reg8/mem 8,immed8 mod 011 [...]

INSTRUCTION SET OPCODES AND CLOCK CYCLES D-14 87 1000 01 11 mod reg r /m (disp-lo),(disp-h i) xchg reg16,reg 16/mem16 88 1000 01 00 mod reg r /m (disp-lo),(disp-h i) mov reg8/mem 8,reg8 89 1000 10 01 mod reg r /m (disp-lo),(disp-h i) mov reg16/me m16,reg16 8A 1000 1010 mod reg r/m (disp-lo),(disp-h i ) mov reg8,reg8/mem 8 8B 1000 1011 mod reg r/m ([...]

D-15 INSTRUCTION SET OPCODES AND CLOCK CYCLES AA 1010 10 10 stos dest- str8 AB 1010 10 11 stos dest- str16 AC 1010 11 00 lods src-str 8 AD 1010 11 01 lods src-str16 AE 1010 11 10 scas dest-str8 AF 1010 11 11 scas dest-str16 B0 1011 0000 data-8 mov AL,immed8 B1 1011 0001 data-8 mov CL,immed8 B2 1011 0010 data-8 mov DL,immed8 B3 1011 0011 data-8 mov [...]

INSTRUCTION SET OPCODES AND CLOCK CYCLES D-16 mod 111 r / m data-8 sar reg16/mem16, immed8 C2 1100 00 10 data-lo data-hi ret immed16 (intrase gment) C3 1100 00 11 ret (intrasegment) C4 1100 01 00 mod reg r /m (disp-lo),( disp-hi) les reg16,me m16 C5 1100 01 01 mod reg r /m (disp-lo),( disp-hi) lds reg16,me m16 C6 1100 01 10 mod 000 r /m (disp-lo),([...]

D-17 INSTRUCTION SET OPCODES AND CLOCK CYCLES D1 1101 00 01 mod 000 r /m (disp-lo),( disp-hi) rol reg16/mem16,1 mod 001 r / m (disp-lo),(disp-h i) ror reg1 6/mem16,1 D1 1101 00 01 mod 010 r /m (disp-lo),( disp-hi) rcl reg16/me m16,1 mod 011 r / m (disp-lo),(disp-h i) rcr reg16/mem16,1 mod 100 r /m (disp-lo),(disp-h i ) sal/shl reg16/mem16, 1 mod 10[...]

INSTRUCTION SET OPCODES AND CLOCK CYCLES D-18 E1 1110 0001 IP -inc-8 loope/loopz short-label E2 1110 0010 IP -inc-8 loop short-label E3 1110 0011 IP-inc-8 jcxz short-label E4 1110 0100 data-8 in AL,immed8 E5 1110 0101 data-8 in A X,immed8 E6 1110 0110 data-8 out AL, immed8 E7 1110 0111 data-8 out AX,imm ed8 E8 1110 1000 IP -inc-lo IP-inc-hi call ne[...]

D-19 INSTRUCTION SET OPCODES AND CLOCK CYCLES F8 1111 1000 clc F9 1111 1001 stc FA 1111 10 10 cli FB 1111 10 11 sti FC 1111 11 00 cld FD 1111 1101 std FE 1111 11 10 mod 000 r /m (disp-lo),(disp-h i) inc mem16 mod 001 r / m (disp-lo),(disp-h i) dec mem16 mod 010 r / m — FE 1111 11 10 mod 011 r / m — mod 100 r / m — mod 101 r / m — mod 110 r [...]

INSTRUCTION SET OPCODES AND CLOCK CYCLES D-20 Table D-4. Mnemon ic Encodi ng Matrix (Left Half) x0 x1 x2 x 3 x4 x5 x6 x7 0x ADD b,f,r/m ADD w,f,r/m ADD b,t,r/m ADD w,t,r/m ADD b,ia ADD w,ia PUSH ES POP ES 1x ADC b,f,r/m ADC w,f,r/m ADC b,t,r/m ADC w,t,r/m ADC b,i ADC w,i PUSH SS POP SS 2x AND b,f,r/m AND w,f,r/m AND b,t,r/m AND w,t,r/m AND b,i AND [...]

D-21 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-4. Mnemon ic Encoding Matrix (Righ t Half) x8 x9 xA xB xC xD xE xF OR b,f,r/m OR w,f,r/m OR b,t,r/m OR w,t,r/m OR b,i OR w,i PUSH CS 0x SBB b,f,r/m SBB w,f,r/m SBB b,t,r/m SBB w,t,r/m SBB b,i SBB w,i PUSH DS POP DS 1x SUB b,f,r/m SUB w,f,r/m SUB b,t,r/m SUB w,t,r/m SUB b,i SUB w,i SEG =CS DAS 2x[...]

INSTRUCTION SET OPCODES AND CLOCK CYCLES D-22 Table D-5. Abbreviations for Mnemonic Encoding Matrix Abbr Defi nition Abbr De finiti on Ab br Def initio n Abbr D efinit ion b byte operation ia immedia te to accumulator m memory t to CPU register d direct id indirect r/ m EA is second byte v variable f from CPU reg ister is immediate byte , sign exte[...]

Index[...]

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Index -1 80C18 7 Math Cop rocessor, 10-2 –1 0-8 accessing, 10-10–10-11 arithm etic instructio ns, 10-3 – 10-4 bus cycles, 10-11 clockin g , 10-1 0 code exampl e s, 10-13–10-1 6 comparison instructions, 10- 5 constant instructio ns, 10-6 data transfer instru c tions, 10-3 data types, 1 0-7–10-8 design con siderations, 10-10–1 0-11 examp [...]

INDEX Inde x-2 and ch ip-selects, 6-5 HALT state, exi ting, 3- 3 0 idle states, 3-18 instruction p refe tch, 3-20 interrupt ackno wledg e (INTA) cycles, 3-6, 3-25 –3-26, 8-9 and ch ip-selects, 6-5 interrupt a cknowledg e cycles, 8-2 9 operatio n, 3 -7–3-20 priorities, 3 -44–3-45, 7-2 read cycles, 3-2 0 –3-21 refresh cycles, 3-22, 7 - 4, 7-5[...]

Index -3 INDEX Data sheets, obtaining from BBS, 1-5 Data transfers, 3 -1–3-6 instruct io ns, 2-18 PCB consideratio ns, 4-5 PSW flag sto rage formats, 2-19 See also Bus cycles Data types, 2-37–2-38 DI register, 2-1, 2-5, 2-13, 2-22, 2-23, 2-30, 2-32, 2-34 Digital o ne-shot, cod e example, 9-17–9-23 Direct Memory Access (DMA) Unit, 10-1–10-27[...]

INDEX Inde x-4 F Fault exceptio ns, 2 -43 FaxBack service, 1-4 F-Bus and P CB, 4-5 operation, 4-5 Flags‚ Se e Processor Status Word (PSW) Floati ng Poin t, defined, 2-3 7 H HALT bus cycle‚ See Bus c ycles HOLD/HLDA pro tocol‚ S ee Bus hold pro tocol Hypertex t manuals, o btaining from BBS, 1-5 I I/O devi c es interfacing with , 3-6–3-7 memo[...]

Index -5 INDEX maskable, 2-43 masking, 8 -3, 8-12, 8-16 priority -based, 8-17 multip lexed, 8 - 7 nest ing, 8-4 NMI, 2-42 nonmaskable, 2-45 overview, 8 -1, 8-2 prio rity, 2 -46–2-49, 8 -3 default , 8-3 resoluti o n, 8-5, 8 - 6 processing, 2-39–2 -42 reserved, 2-39 response time, 2-46 selecting ed ge- or lev e l-triggerin g, 8-12 slave mode sour[...]

INDEX Inde x-6 Poll ing, 8-1, 8 -9 POPA instru c tion, A-1 Power co nsumption‚ r e ducing, 3-28 Power manag ement, 5-10–5-14 Power management mod e s and HAL T bus cy c les, 3- 30 Powerd own mod e , 7-2 Power-Save mode, 5-11–5-1 4 , 7-2 and DRAM refresh rate, 5-13 and refresh interval, 7-7 contro l register, 5-12 entering , 5-11 exitin g , 5-[...]

Index -7 INDEX SI regi s ter, 2 -1, 2- 5, 2-13, 2- 22, 2-23 , 2-30, 2-3 2, 2-34 Sign Flag (SF), 2-7, 2-9 Single-step trap (Type 1 exception), 2-43 Software code example 80C1 87 fl oating-p oint routin e, 10-16 80C1 87 initi alization, 1 0-13–10-1 5 digital o ne-shot, 9-17 – 9-23 DMA in itialization, 10-2 2–10-27 ICU initialization, 8-31 real-[...]

INDEX Inde x-8 and PCB accesses, 4-4 and RE ADY input, 3-13 Word integer, defin ed , 10-7 World Wide Web, 1 -6 Write b us cycle, 3-22 Z Zero Flag (ZF), 2-7, 2-9 , 2-23[...]