Jameco Electronics Rabbit 2000 инструкция обслуживания

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Rabbit 3000 ® Microprocessor User ’ s Manual 019–0108 • 040731– O ®[...]

Rabbit 3 000 Micr oproces sor Rabbit Semiconductor 2932 Spaf ford Street Davis, Cali forni a 95616-6800 USA T el ephone: (530) 757-8400 Fax: (530) 757-8402 www .ra bbitsemi conductor .com Rabbit 3000 Microproce ssor User ’ s Manual Part Number 019-010 8 • 0 40731 –O • P rin ted in U. S.A. ©2002–2004 R abbit Se miconducto r • All r ight[...]

User ’ s Ma nua l T ABLE OF C ONTENT S Chapter 1. Introduction 1 1.1 Features and Specif i cation s Rabbit 300 0 ................. ....................... ................. .......................... ...........2 1.2 Summary of Rabbit 300 0 Advantages ..................... ................. ....................... ................. ........... ..[...]

Rabbit 3 000 Micr oproces sor 3.5 Interru pt Structure .......... ........... ................. ....................... ................. ......................... ........ ............ ... 44 3.5.1 In terrupt Priority ..................... ................. ...................... ................. ............................ ............... 44 3.[...]

User ’ s Ma nua l 8.5 Memory Bank Control Reg isters . ............................ ....................... ................. ...................... .. .........120 8.5.1 Option al A16, A19 I nversions by Segm ent (/CS1 Enable) .............. ................. ......................121 8.6 Allocation of Extended Code and Data .............. .....[...]

Rabbit 3 000 Micr oproces sor Chapter 14. Rabbit 3 000 Clocks 209 14.1 Low-Power Design ....... ............................ ............................ ....................... ................. .................. 210 Chapter 15. EMI Control 21 1 15.1 Power Sup ply Connections and Board Layout .................... ................. ...............[...]

User ’ s Ma nua l 19.16 Block Mo ve Instructions ................ ............................ ....................... ................ .............. ......... .....256 19.17 Contro l Instruc tions - Jumps an d Calls ...................... ........... ............ ................ ..................... .......257 19.18 Miscellaneous Instructions[...]

Rabbit 3 000 Micr oproces sor[...]

User ’ s Ma nua l 1 1. I NTRO DUCTION Rabbit Semiconductor was formed expressly to design a a better microprocessor f or use in small and medium-scale controllers. The first microprocessor was the Rabbit 2000 . The second microprocessor , now available, is the Rabbit 3000 . Rabbit microprocessor design- ers have had yea rs of experience using Z 8[...]

2 Rabbit 3 000 Micr oproces sor 1.1 Feat ures and Specifi cations Rabbit 3000 • 128-pin LQFP package . Operating voltage 1.8 V to 3.6 V . Clock speed to 54+ MHz. All specifications are given for both industria l and commercial temper ature and voltage ranges. Rabbit microprocessors are low-cost. • Industrial specifications are for 3.3 V ±10% a[...]

User ’ s Ma nua l 3 A Rabbit that is s laved to a ma ster processor c an operate entirely wit h volatile RAM, depending on the master for a cold program boot. • There are 56 parallel I/O line s (shared with se rial port s). Some I/O lines ar e timer syn- chronized, which permits precisely timed e dges and pulses to be generated under com- bined[...]

4 Rabbit 3 000 Micr oproces sor • A built-in clock doubler allows ½-frequency crystals to be used. • The built-in main clock oscillator use s an external cr ystal or a cera mic resonator . T ypical crystal or resonator freque ncies are in the r ange of 1.8 MHz to 30 MHz. Since precision timing is ava ilable from the sep arate 32.768 kHz oscill[...]

User ’ s Ma nua l 5 Figure 1- 1. Rabbit 3000 Bl ock Diagram CPU External Interface Data Buffer Memory Management/ Control Address Buffer Memory Chip Interface Parallel Ports Port A Port B Port C Port D Port E Port F Port G Global Power Save & Clock Distribution Fast Oscillator T imer A T imer B Real-T ime Clock 32.768 kHz Clock Input W atchdo[...]

6 Rabbit 3 000 Micr oproces sor 1.2 Summary of Rabbit 3000 Advant ages • The glueless architecture makes it is easy to design the hardware system. • There are a lot of serial ports a nd they c an communicate very fast. • Precision pulse and edge gene ration is a standard fea ture. • EMI is at extremely low levels. • Interrupts can have mu[...]

User ’ s Ma nua l 7 1.3 Differences Rabbit 3000 vs. Rabbit 2000 For the benefit of rea ders who are familia r with the Rabbit 2000 microprocessor the Rab- bit 3000 is contrasted with the Rabbit 2000 in t he table below . Feature Rabbit 3000 Rabbit 2000 Maximum clock speed 54 MHz 30 MHz Maximum crystal frequency main oscillator (may be doubled in [...]

8 Rabbit 3 000 Micr oproces sor Serial ports with sup p ort for SDLC/HDLC IrDA communicati ons 2N o n e Maximum asy nchronous baud rate clock sp eed/8 clock spe ed/32 Input capture unit 2 None Feature Rabbit 3000 Rabbit 2000[...]

User ’ s Ma nua l 9 2. R ABBIT 3000 D ES IGN F EA TURES The Rabbit 3000 is an evolutionary design. The processor and instruction set are nearly identical to the immediate predecessor processor , the Rabbit 2000. Both the Rabbit 3000 and the Rabbit 2000 follow in broad outline the instruction set and the register layout of the Z80 and Z180. Compar[...]

10 Rabbit 3 000 Micr oproces sor 2.1 The Rabbit 8-bit Processor vs. Other Processors The Rabbit 3000 processor has been designed with the objective of creating practical sys- tems to solve real world problems in an economical fashion. A cursory comparison of the Rabbit 3000 compared to other processors w ith similar capabilities may miss certain Ra[...]

User ’ s Ma nua l 11 The Rabbit is an 8-bit processor with an 8-bit external data bus and an 8-bit internal data bus. Because the Rabbit makes the m ost of its external 8-bit bus and because it has a com- pact instruction set, its performance is as good as many 16-bit processors. W e hesitate to compare the Rabbit to 32-bit processors, but there [...]

12 Rabbit 3 000 Micr oproces sor important for RS-485 communication because a half duplex line driver cannot have the direction of transmission reversed until the last data bit has been sent. In many UAR T s, including those on the Z180, it is dif ficult to gener a te an interrupt after the last bit is sent. A so called address bit can be transmitt[...]

User ’ s Ma nua l 13 2.2.5 P arallel I/O There are 56 parallel i nput/output lines divided among seven 8-bit ports designated A through G . Most of the port lines h ave alternate f unctions, such as serial data or chip select strobes. Paralle l Ports D, E, F , and G ha ve the c apability of time r -synchronized outputs. The output registers are c[...]

14 Rabbit 3 000 Micr oproces sor 2.2. 6 Slave P ort The slave port is designed to allow the Rabbit to be a slave to another processor , which could be another Rabbit. The port is shared with Parallel Port A and is a bidirectional data port. The master can read a ny of three register s selected via two select lines that form the register address and[...]

User ’ s Ma nua l 15 2.2.7 Aux iliary I/O Bus The Rabbit 300 0 instruction set supp orts memory access and I/O access. Memory access takes place in a 1 megabyte memory space. I/O access takes place in a 64K I/O space. In a traditio nal microprocessor de sign the same a d dress and data lines are used for both mem- ory and I/O spaces. Sharing addr[...]

16 Rabbit 3 000 Micr oproces sor Figure 2-4. Rabbit Timers A and B 2.2.9 I nput Capture Channels The input capture channels are used to deter mine the time at which an event takes place. An event is signaled by a rising or falling edge (or optionally by either edge ) on one of 16 input pins that can be selected as input for either of the two channe[...]

User ’ s Ma nua l 17 and stop condition, for example a rising edge could be the start condition and a falling edge the stop condition. However , optionally , the start and stop condition can be inp ut from separate pins. The input capture channels can be used to measure t he width of fast pulses. This is done by starting the counter on the first [...]

18 Rabbit 3 000 Micr oproces sor length of the pulses. When the duty cy cle is greater then 1/1024 the pulses are spread into group s distributed 2 56 counts apart i n the 1024 frame. Th e pulse width modu lation output s can be passed through a filter and used as a 1 0-bit D/A conv erter . The outp uts can also be used to directly drive devi ces t[...]

User ’ s Ma nua l 19 reset pin, and to a programmable output pin that is used to signal the PC that at tention is needed. W i th proper precautions in design and so ftwar e , it is possible to use Serial Port A as both a programming port and as a user-defined serial port, although this will not be nec- essary in most cases. Rabbit Semiconductor s[...]

20 Rabbit 3 000 Micr oproces sor[...]

User ’ s Ma nua l 21 3. D ET AILS ON R ABBIT M ICROPROCESS OR F EATURE S 3.1 Processor Registers The Rabbit’ s registers are nearly identical to those of the Z180 or the Z80. The figure below shows the register layout. The XPC and IP registers are ne w . The EIR register is the same as the Z80 I register , and is used to point to a table of int[...]

22 Rabbit 3 000 Micr oproces sor The Rabbit (and the Z80/Z180) processor has tw o accumulators—the A register serves as an 8-bit accumulator for 8-bit operations such as ADD or AND . The 16-bit register HL regis- ter serves as an accum ulator for 16-bit operations such as ADD HL,DE , which adds the 16- bit register DE to the 16-bit accumu lator H[...]

User ’ s Ma nua l 23 3.2 Memory Mapping Although the Rabbit memory mapping scheme is fa irly complex, the user rarely needs to worry about it because the details are ha ndled by the Dynamic C development system. Except for a handful of specia l instructions (see Section 19.5, “16-bit Load and Store 20- bit Address”.), the Rabbit instructions [...]

24 Rabbit 3 000 Micr oproces sor Figure 3-3. Exa mple of Memory Mapping Operation The names given to the segments in the figure are evoc ative of the common uses for each segment. The r oot segment is mapped to the base of flash memory and contains the startup code as well as other code that ma y happen to be stored there. The data segme nt us age [...]

User ’ s Ma nua l 25 the root segment or it may contain data variables. The stack segment is normally 4K long and it holds the system stack. The XPC segment is normally used to execute code that is not stored in the root segment or the data segment. Special instructions support executing code that is visible in the XPC segment. The memory inte rf[...]

26 Rabbit 3 000 Micr oproces sor 3.2.1 E xtended Code Sp ace A crucial element of the Rabbit memory mappi ng scheme is t he ability to execute pro- grams containing up to a megabyte of code in an ef ficient manner . This ability is absent in a pure 16-bit address processor , and it is poorly supported by the Z180 through i ts me m or y mapping unit[...]

User ’ s Ma nua l 27 than the XPC segment, can call other code in the root using short jumps and calls. Code in the XPC segment can also call code in the root using short jumps and call s. However , a long call must be used when code in the XPC segment is called. Functions located in the root have an efficiency advantage because a long call and a[...]

28 Rabbit 3 000 Micr oproces sor fetching an instruction from memory and fetching or storing data in memory . When enabled separate I and D space make available the combined root and data segment, typi- cally 52k bytes for root code in the I space. I n t he D space, the root code s egment part of the D space is typically used for constant da ta map[...]

User ’ s Ma nua l 29 not have split I and D space and memory acc esses to these segme nt s do not distinguish between I and D space . The advantage of having more root code space is that root code executes faster bec ause short calls using a 16 bit address are used to ca ll it. This compares to long calls that have a 20 bit address for extended c[...]

30 Rabbit 3 000 Micr oproces sor Figure 3-7. Schemes for Data Memor y Windows A third approach is to plac e the data and root code in RAM in the root segment, freeing the data segment to be a window to extended memory . This requires copying the root code to RAM at startup time. Copying root code to RAM is not necessarily that burdensome since the [...]

User ’ s Ma nua l 31 ded applications. Some applica tions may require large data a rrays or tables that will require additional data memory . For this pur pose Dynamic C supports a type of extended data memory that allows the use of add itional data memory , even extending far beyond a megabyte. Requirements for stack memory depend on the type of[...]

32 Rabbit 3 000 Micr oproces sor 3.3 I nstruction S et Outline “Load Immediate Data to a Register” on pa ge 33 “Load or Store Data from or to a Constant Address” on page 33 “Load or Store Data Using an Index Register” on page 34 “Register -to-Register Move” on page 35 “Register Exchanges” on page 35 “Push and Pop Instructions?[...]

User ’ s Ma nua l 33 • Input/output instructions are now accomplis hed by normal memory acc ess instructions prefixed by a n op code byte to indicate access t o an I/O space. There are two I/O spaces, internal peripher a ls and external I/O devices. Some Z80 and Z180 instructions have been deleted and are not supported by the Rabbit (see Chapte[...]

34 Rabbit 3 000 Micr oproces sor 3.3.3 Loa d or St ore Dat a Using an Index Register An index register is a 16-bit register , usually IX, I Y , SP or HL, that is used for the address of a byte or word to be fetched from or stor ed to memory . Sometimes an 8-bit of fset is added to the address e i ther as a signed or unsi gned number . The 8-bit of [...]

User ’ s Ma nua l 35 3.3.4 Regi s ter-to-Register Mov e Any of the 8-bit registers, A, B, C, D, E, H, and L, can be moved to any other 8-bit regis- ter , for example: LD A,c LD d,b LD e,l The alternate 8-bit registers can be a destination, for e xample: LD a’,c LD d’,b These instructions are unique to the Rabbit and require 2 bytes and four c[...]

36 Rabbit 3 000 Micr oproces sor 3.3.6 Push and Pop Inst ruction s There are instructions to push and pop the 16-bit registers AF , HL, DC, BC, IX, and IY . The registers AF', HL', DE', and BC' can be popped. Popping the alternate registers is exclusive to the Rabbit, and is not allowed on the Z80 / Z180. Examples POP HL PUSH BC[...]

User ’ s Ma nua l 37 The BOOL instruction is a specia l instruction de signed to help test the HL register . BOOL sets HL to the value 1 if HL is non zero, otherw i se, if HL is zero its value is not changed. The flags are set according to the result. BOOL can also operate on IX and IY . BOOL HL ; set HL to 1 if non- zero, set flags to match HL B[...]

38 Rabbit 3 000 Micr oproces sor The SBC instruction can also be used to perform a sign extension. ; extend sign of l to HL LD A,l rla ; sign to carry SBC A,a ; a is all 1’s if sign negative LD h,a ; sign extended The multiply inst ruction perf orms a signed m ultiply that generates a 32- bit signed result. MUL ; signed multiply of BC and DE, ; r[...]

User ’ s Ma nua l 39 3.3.8 Input/Output Instructions The Rabbit uses an entirely different sche me for accessing input/output devices. Any memory access instruction may be prefixed by one of two pref i xes, one for internal I/O space and one for ext e rnal I/O spac e. When so prefixed, the memory instruction is turned into an I/O i ns truction t [...]

40 Rabbit 3 000 Micr oproces sor 3.4 How to Do It in Assembly Language—Tip s and T r icks 3.4.1 Ze ro HL in 4 Clocks BOOL HL ; 2 clocks, clears carry, HL is 1 or 0 RR HL ; 2 clocks, 4 total - get rid of possible 1 This sequence requires four clocks compare d t o six clocks for LD HL,0 . 3.4.2 Exchange s Not Dire ctly Imp lemented HL<->HL&ap[...]

User ’ s Ma nua l 41 3.4.4 Comp arisons of Integers Unsigned integers may be compared by testing the zero a nd carry flags after a subtract operation. The zero flag is set if the number s are equal. W ith the SBC instruction the carry cleared is set if the number subtracted is less than or equal to the number it is subtracted from. 8-bit unsigned[...]

42 Rabbit 3 000 Micr oproces sor Some simplifications are possible if one of the unsigned numbers being compared is a constant. Note that the carry has a reve rse sense from SBC . In the following examples, the pseudo-code in the form LD DE,(65535-B) does not indicate a load of DE with the address pointed to by 65535-B , but simpl y indicates the d[...]

User ’ s Ma nua l 43 A>B (!S & !V & !Z) v (S & V) A<B (S & !V) v (!S & V & !Z) A==B A>=B A<=B Another method of doing signed compare is to first map the signed i ntegers onto unsigned integers by inverting bit 15. This is shown in Figure 3-8. Once the mapping has been pe r- formed by inverting bit 15 on both nu[...]

44 Rabbit 3 000 Micr oproces sor 3.5 Interrupt S tructure When an interrupt occurs on the Rabbit, the return address is pushed on the stack, and con- trol is transf erred to the address of the inte rrupt service routine. The addre ss of the inter- rupt service routine has two parts: the uppe r byte of the a ddress comes from a special register and [...]

User ’ s Ma nua l 45 the same prior ity , this introduc es inte rrupt late ncy while the ne xt routine is wait ing for the previous routine to a llow more interrupts to take pl ace. If a number of devic e s have inter- rupt service routines, and all interrupts are of the same priority , then pe ndi ng interrupts can not ta ke place unt il at leas[...]

46 Rabbit 3 000 Micr oproces sor 3.5.2 M ultiple Ex ternal Int errupting Devices The Rabbit 3000 has two distinct external interrupt request lines. If there are more tha n two external c auses of i nterrupts, then th ese lines must be shared between m ultiple devices. The interrupt line is edge-sensitive , meaning that it re quests an interrupt onl[...]

User ’ s Ma nua l 47 The privileged instructions to manipulat e the IP register are listed below . IPSET 0 ; shift IP left and set prio rity 00 in bits 1,0 IPSET 1 IPSET 2 IPSET 3 IPRES ; rotate IP right 2 bits, re storing previous priority RETI ; pops IP from stack and the n pops return address POP IP ; pop IP register from stack 3.5.4 C ritical[...]

48 Rabbit 3 000 Micr oproces sor 3.5.6 Computed Long Calls and Jumps The instruction to set the XPC is privileged to so that a computed long call or jump can be made. This would be done by the following sequence. LD xpc,a JP (HL) In this case, A has the new XPC, and HL ha s the new PC. This code should normally be executed in the root segment so as[...]

User ’ s Ma nua l 49 4. R ABBIT C AP ABILITIE S This chapt er des cri bes the v ariou s capabili ties of the Rabbi t that may not be ob vious from the technical des c ription. 4.1 Precisely T imed Output P ulses The Rabbit can output precise pu lses under software contr ol. The effect of interr upt latency is avoided because the interrupt always [...]

50 Rabbit 2 000 Micr oproces sor Pulse width modulated outputs—The mi nimum pul se width is 10 µs. If the repetition rate is 10 ms, then a new pulse with 1000 dif ferent widths can be generated at the ra te of 100 times per second. Asynchronous communications serial output—A synchronous output data can be gener- ated with a new pulse every 10 [...]

User ’ s Ma nua l 51 4.2 Open-Drain Output s Used for Key Scan The Parallel Port D outputs can be individually programm ed to be open drain. This is use- ful for scanning a switch matrix, as shown in Figure 4-2. A row is driven low , then the col- umns are scanned for a low input line, which indi c ates a key is closed. This is repeated for each [...]

52 Rabbit 2 000 Micr oproces sor 4.3 Cold Boot Most microprocessors start executing at a fixed address, often a ddress ze ro, af ter a res et or power-on condition. The Rabbit has tw o mode pins (SMODE0, SMODE 1—see Figure 5- 1). The logic state of these two pins determines the startup procedure af t er a reset. If bot h pins are grounded, then t[...]

User ’ s Ma nua l 53 4.4 The Slave Port The slave port all ows a Rabbit to act as a slav e to another proc essor , which c an also be a Rabbit. The slave has to have only a processo r chip, a RAM chip, and clock and reset sig- nals that can be supplied by the master . Th e master can cold boot and download a program to the slave. The master does [...]

54 Rabbit 2 000 Micr oproces sor Of the three registers seen by e ach side for each direction of communication, the first reg- ister , slave register zero, has a s pecial func tion because an interrupt ca n only be generated by a write to this register , which then causes an interrupt to take place on the other side of the link if the interrupt is [...]

User ’ s Ma nua l 55 5. P IN A SS IGNMENT S AN D F UNCTI ONS[...]

56 Rabbit 3 000 Micr oproces sor 5.1 LQFP Package 5.1.1 P inout Rabbit 3000 (A T56C55-IL1 T , I L2T) 128-pin Low-Profile Quad Flat Pack (LQFP) 14 × 14 Body , 0.4 mm pitch Figure 5-1. Package Outline and Pin Ass ignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 96 95 94 93 92 91 90 89 88 87 86 85 84 83 [...]

User ’ s Ma nua l 57 5.1.2 Mechanic al Dimensions a nd Land Pattern Figure 5-2 shows the mechanical dimens ions of the Rabbit 3000 LQFP package. Figure 5-2. Mechanical Dimensions Rabbit LQFP Pac kage 14.00 ± 0.10 mm 16.00 ± 0.25 mm + 0.10 mm  0.15 mm 0.60 0.18 ± 0.05 mm 0.40 mm 14.00 ± 0.10 mm 16.00 ± 0.25 mm 1.00 mm The same pin dimensio[...]

58 Rabbit 3 000 Micr oproces sor Figure 5-3 shows the PC board land pattern for the Rabbit 3000 chip in a 128-pin LQFP package. This land pattern is ba s ed on the IPC-SM-782 standard deve l oped by the Surf ace Mount Land Patterns Committee and specified in S urface Mount Design and Land Pat- tern S tandard , IPC, Northbrook, IL, 1999. Figure 5-3.[...]

User ’ s Ma nua l 59 5.2 Ball Grid Array Package 5.2.1 Pinout Rabbit 3000 (A T56C55-IZ1 T , I Z2T) 128-pin Thin Map Ball Grid Array (TFBGA) 10 × 10 Body , 0.8 mm pitch Figure 5-4. Ball Grid Array Pinout Looking Through the T op of Package 1 2 3 4 56 7 8 9 10 11 12 A B C D E F G H J K L M VDDIO VSSIO PF5 PB6 PB2 XT ALA2 P A6 P A2 PF3 PF1 PF0 PF7 [...]

60 Rabbit 3 000 Micr oproces sor 5.2.2 Me chanical Dimens ions and Land Pattern The design considerations in T a ble 5-3 are ba sed on 5 mi l design rules a nd assume a single conductor between solder lands. T able 5-2. Ball and Lan d Size Dimensions Nominal Ball Dia met er (mm) T olerance Va r i a t i o n (mm) Ball Pitch (mm) Nominal Land Dia met [...]

User ’ s Ma nua l 61 Figure 5-5. BGA Packag e Outline A B C D E F G H J K L M 12 11 10 9 87 6 5 4 3 2 1 A B C D E F G H J K L M 12 11 10 9 8 7 6 5 4 3 2 1 0.80 10.00 ± 0.05 0.80 10.00 ± 0.05 0.20~0.30 1.20 (max.) Ball Pitch: Ball Diameter: 0.80 mm 0.3 mm (0.25~0.35) TOP VIEW BOTTOM VIEW[...]

62 Rabbit 3 000 Micr oproces sor 5.3 Rabbit Pin Desc riptions T able 5-1 lists all the pins on the device, along with their direction, function, and pin num- ber on the package. T able 5-1. Rabbit Pin Desc riptions Pin Group Pin Name Direction Function Pin Num bers LQFP Pin Num bers TFBGA Hardware CLK Output Internal Clock 2 B1 CLK32K Input 32 kHz [...]

User ’ s Ma nua l 63 I/O ports P A[7:0] Input / Output I/O Port A 1 11–104 D7, A8, B8, C8, D8, A9, B9, C 9 I/O port s (continued) PB [7:0] Input / Outpu t I/O Port B 123–1 16 C4, A 5 , B5, C5, D5, A6, B6, C 6 PC[7:0] 4 In / 4 Out I /O Port C 66–71, 74, 75 L1 1, M11, M12, L12, K12, K1 1, J10, H12 PD[7:0] Input / Output I/O Port D 52–59 K7,[...]

64 Rabbit 3 000 Micr oproces sor 5.4 Bus Timi ng The exter nal bus has esse ntially the sa me timing for memory cycl es or I/O c ycles. A m em- ory cycle begins with the chip select and the address lines. One clock late r , the output enable is asserted for a read. The output data and the write enable ar e asser ted for a write. Figure 5-6. Bus Tim[...]

User ’ s Ma nua l 65 5.5 Description of Pin s with Alternate Function s T able 5-2. Pins With Alternate Functions Pin Name Output Function Input Function Input Capture Optio n P A[7:0] SLA VE D[7:0], ID[7:0] SLA VE D[7:0], I D[7:0] PB7 SLA VEA TTN, IA5 PB6 IA 4 /ASCS * PB5 IA 3 SD1 PB4 IA 2 SD0 PB3 IA 1 /SRD PB2 IA 0 /SWR PB1 CLKA CLKA PB0 CLKB C[...]

66 Rabbit 3 000 Micr oproces sor PF7 PWM3 AQD2A yes PF6 PWM2 AQD2B PF5 PWM1 AQD1A yes PF4 PWM0 AQD1B PF3 QD2A yes PF2 QD2B PF1 CLKC QD1A , CLKC yes PF0 CLKD QD1B, CLKD PG7 APWM 1 * RXE yes PG6 TXE PG5 RCLKE RCLKE, ARXE * yes PG4 TCLKE TCLKE, AR CLKE * PG3 APWM 0 * RXF PG2 TXF PG1 RCLKF RCLKF , ARXF * PG0 TCLKF T CLKF , ARCLKF * * Introd uced with R[...]

User ’ s Ma nua l 67 The alternate output functions identified in T able 5-2 are configured by setting the appro- priate bits in t he Paralle Port x Function Register . T able 5-3. Parallel Port x Alterna te Functions Parallel P ort x Function Register (PCFR) (Address = 0x0055) (PDFR) (Address = 0x 0065) (PEFR) ( Address = 0x0075 ) (PFFR) (Addres[...]

68 Rabbit 3 000 Micr oproces sor 5.6 DC Characteristics St resses beyond those listed in T able 5-5 may cause permanent damage. The ratings are stress ratings only , and functional opera t ion of the Rabbit 3000 chip at these or any other conditions beyond those indicated in this secti on is not i mplied. Exposure to the absolute maximum rating con[...]

User ’ s Ma nua l 69 5.7 I/O Buffer Sourcing and Sinking Limit Unless otherwise specified, the Ra bbit I/O buf fers are capable of sourcing and sinking 6.8 mA of current pe r pin at full AC switching spe eds. The limit s are rela ted to the maxi- mum sustained current permitted by the metallization on the die.[...]

70 Rabbit 3 000 Micr oproces sor[...]

User ’ s Ma nua l 71 6. R ABBIT I NTERN AL I/O R EGIST ERS[...]

72 Rabbit 3 000 Micr oproces sor T able 6-1. Rabbi t 3000 Pe ripherals and Interrupt Service V ectors On-Chip Periphe ral ISR St arting Address System Man agement {IIR[ 7:1], 0, 0x00} Memory Manage ment No interru pts Slave Port {IIR[ 7:1] , 0, 0x8 0} Pa ra llel P ort A No in terrup ts Pa ra llel P ort F No in terrup ts Pa ra llel P ort B No in ter[...]

User ’ s Ma nua l 73 6.1 Default V alues for all the Peripheral Control Registe rs The default values for all of the per i pheral control registers are shown in T able 6-2. The registers within the CPU affected by re set ar e the Stack Pointer (SP), the Program Counter (PC), the IIR register , the EIR register , and the IP r egist er . The IP reg[...]

74 Rabbit 3 000 Micr oproces sor Global Rev ision Reg ister GREV 0x2F R 0xx 00000 Port A D ata Reg ister P ADR 0x30 R/W xxxxxxxx Port B Data Re gister PBDR 0x40 R/W 00xxxxxx Port B Data Direct ion Reg ister PBDDR 0x47 W 1 1000000 Port C Data Re gister PCDR 0x50 R/W x0x1x1x1 Port C Funct ion Regi s t er PCFR 0x55 W x0x0x0x0 Port D D ata Reg ister PD[...]

User ’ s Ma nua l 75 Port E B it 7 Reg ister PEB7R 0x7F W xxxxxxxx Port F Data Regis ter PFDR 0x38 R/W xxxxxxxx Port F Control Regis ter PFC R 0x3C W xx00xx00 Port F Function Register PFFR 0x3D W xxxxxxxx Port F D rive Cont rol Reg ister PFDCR 0x3E W xxxxxx xx Port F D ata Dir ection Regi ster PFDDR 0x3F W 00000000 Port G D ata Reg ister PGDR 0x4[...]

76 Rabbit 3 000 Micr oproces sor PWM MSB 0 Regist er P WM0R 0x89 W xxxxxxxx PWM LSB 1 Register PWL1R 0x8A W xxxxxxxx PWM MSB 1 Regist er P WM1R 0x8B W xxxxxxxx PWM LSB 2 Register PWL2R 0x8C W xxxxxxxx PWM MSB 2 Regist er P WM2R 0x8D W xxxxxxxx PWM LSB 3 Register PWL3R 0x8E W xxxxxxxx PWM MSB 3 Regist er P WM3R 0x8F W xxxxxxxx Quad Decode C trl/S t [...]

User ’ s Ma nua l 77 T i mer A T ime Con stant 5 Register T A T5R 0xAB W xxxxxxxx T i mer A T ime Con stant 6 Register T A T6R 0xAD W xxxxxxxx T i mer A T ime Con stant 7 Register T A T7R 0xA F W xxxxxxxx T i mer B Control /S tatus Reg ister TBCSR 0xB0 R /W xxxxx0 00 T i mer B Control Regis ter TBCR 0xB 1 W xxxx0000 T i mer B MSB 1 Regi ster TBM1[...]

78 Rabbit 3 000 Micr oproces sor Serial Por t D Addr ess Reg ister SDAR 0xF1 R/W xxxxxxxx Serial Por t D Lon g Sto p Register SDLR 0xF2 R /W xxxxxxxx Serial Por t D S tatus Reg ister SDSR 0xF3 R 0xx00000 Serial Por t D Co ntrol Regi ster SDCR 0xF4 W xx000000 Serial Por t D Exte nded Regi ster SDER 0xF5 W 00000000 Serial Por t E Data Register SEDR 0[...]

User ’ s Ma nua l 79 7. M ISCEL LANEO US F UNCTIONS 7.1 Processor Identifica tion Four read-only registers are provide d t o al low software to ide ntify the Rabbit mi cropro- cessor and recognize the f e atures and capabilities of the chip. Five bits in each of these registers are unique to each version of the ch ip. One register is reserved for[...]

80 Rabbit 3 000 Micr oproces sor 7.2 Rabbit Oscillat ors and Clocks The Rabbit 3000 usually requires two separate clocks. The main clock normally dri ves the processor core and most of the peripheral devic e s, and the 32.768 kHz clock drives the battery-backable time-date c l ock and other circuitry . Main C l o ck An oscillator buf fer is built i[...]

User ’ s Ma nua l 81 32. 768 kHz Cl oc k The 32.768 kHz clock is primarily used to clock the on-chip real-time clock. In addition, it is also used to support remote cold boot via Serial Port A, drivi ng the 2400 baud commu- nications used to initiate the co ld boot. A nother function of the 32.768 kHz oscillator is to drive the low powe r sleepy [...]

82 Rabbit 3 000 Micr oproces sor T able 7-5. Global Control /S tatus Regi ster Global Control/St atus Reg ister (GCSR) (Addre ss = 0x00) Bit (s) Va l u e Description 7:6 (rd-only) 00 No Reset or W atchdog T imer time-out since the last read. 01 The W atchdog T imer timed out. These b its are cleared by a read of this register . 10 This bit combinat[...]

User ’ s Ma nua l 83 7.3 Cl ock Doubler The clock doubler is provided to allow a lower frequency c rystal to b e used for the main oscillator and to provide an added range of clock fre quenc y adjustability . The clock dou- bler is controlled via the Global Clock Double Register as shown in T able 7-7. The clock doubler uses an on-chip delay circ[...]

84 Rabbit 3 000 Micr oproces sor When the clock doubler is used and there is no subsequent division of the clock, the output clock will be asymme tric, as shown in Figur e 7-2. Figure 7-2. Eff ect of Clock Doubler The doubled-clock low time is subject to wide (50%) variation since it depends on process parameters, temperature, and voltage. The t im[...]

User ’ s Ma nua l 85 variation in period on alternate clocks. This does not affect the no-wait states memory access time sinc e two adjacent clocks are a l ways used. However , the maximum allowed clock speed must be slightly reduced if the clock is supplied via the clock doubler . The only signals clocked on the falling edge of the clock are the[...]

86 Rabbit 3 000 Micr oproces sor 7.4 Cl ock Spectrum Spr eader When enabled the spe ctrum spreader stretc hes and c om presses the clocks in a complex pattern that results in spreading the energy in the clock harmonics over a wide range of frequencies. The spectrum spreader has a normal and a strong setting. W ith either setting the peak spectral s[...]

User ’ s Ma nua l 87 7.5 Chip Select Options for Low Power Some types of flash memory and RAM cons ume power whenever the chip selec t is enabled even if no signals are changing. The chip select behavior of the R abbit 3000 can be modified to reduce unnecessary power c onsum ption when the Rabbit 3000 is running at a reduced clock spee d. The sho[...]

88 Rabbit 3 000 Micr oproces sor When operating in the 32 kHz mode, it is also po ssible to further divide the clock to a fre- quency as low as 2 kHz, further re ducing execution speed and current consumption. It is anticipated that th ese m easures w ould re duce operating current consumption t o as low as 20 µ A plus some additional leakage that[...]

User ’ s Ma nua l 89 Figur e 7-4. Short Ch ip Select Memory Read Figure 7-5. Se lf- Timed Chip Select Me mory Read Cycle clock ADDR DATA T1 T2 Valid MEMO Ex B MEMC Sx B 32 kHz A DDR DA T A T1 T2 Va lid Va lid ME MO E x B ME MC S x B ~1 0 0 n s[...]

90 Rabbit 3 000 Micr oproces sor 7.6 Output Pin s CLK, ST A TUS, /WDT OUT , /BUFEN Certain output pins can have alternate assignments as specified in T able 7-9. T able 7-9. Global Output Control Regist er (GOCR = 0x0E) Bit (s) Va l u e Description 7:6 00 C LK pin is driven with peripheral clock. 01 CLK pin is driven wi th peripheral cl ock div ide[...]

User ’ s Ma nua l 91 7.7 Ti me/Date Clock (Real-T ime Clock) The time/date clock (R TC) is a 48-bit (ripple) counter that is dri ven by the 32.768 kHz oscillator . The R TC is a modified ripple counte r composed of six separate 8-bit counters. The carries are fed into all six 8-bit counters at the same time and then ripple for 8 bits. The time fo[...]

92 Rabbit 3 000 Micr oproces sor T able 7 - 10. Real-Time Clock R TCxR Data Registers Real-Time Clock x Holding Register (RTC0R) R/W (Address = 0x02) (RTC1R) (Addre ss = 0x03) (RTC2R) (Addre ss = 0x04) (RTC3R) (Addre ss = 0x05) (RTC4R) (Addre ss = 0x06) (RTC5R) (Addre ss = 0x07) Bit (s) Va l u e Description 7:0 Read The current value o f the 48-bit[...]

User ’ s Ma nua l 93 7.8 W atchdo g T imer The watchdog timer is a 17-bit counter . In normal operation it is driven by the 32.768 kHz clock. When the watchdog timer reaches any of several values corresponding to a delay of from 0.25 to 2 seconds, it “times out.” When it times out, it emits a 1-clock pulse from the watchdog output pin and it [...]

94 Rabbit 3 000 Micr oproces sor The code to do this may also hit the watc hdog with a 0.25-second period to speed up the reset. Such watchdog code must be written so that it is highly unli kely that a crash will incorporate the code and continue to hit the watchdog in an endless loop. The following suggestions will help. 1. Place a jump to self be[...]

User ’ s Ma nua l 95 7.9 System Reset The Rabbit 3000 contains a master reset input (pin 46), which initializes everything in the device except for the Real- T ime Clock (R TC). This r eset is dela yed until the comple tion of any write cycles in progress to preven t potential corruption of memory . If no write cycles are in progress the re set t[...]

96 Rabbit 3 000 Micr oproces sor T able 7 -14. Rabbi t 3000 Reset Sequence and S tate of I/O Pins Pin Name Dir ection /RE SET Lo w * Recognized by CPU Post-Rese t † /RESET Input Low or Hi gh High CLK Outpu t High Operational CLK32K Input Not Affected Not Af fected RESOUT Output High Low XT ALA1 In p ut Not Affected Not Affected XT ALA2 Output Not[...]

User ’ s Ma nua l 97 7.10 Rabbi t Interrupt S tructure An interrupt causes a call to be executed, pushing the PC on the stack and starting to exe- cute code at the interrupt vector address. Th e interrupt vector addresses have a f ixed lower byte value for all interrupts. The upper byte is adjust able by setting the registers EIR and IIR for exte[...]

98 Rabbit 3 000 Micr oproces sor In the case of the external interrupts the only action that wi ll clear the interrupt re quest is for the inte rrupt to take place, which automa tically cl ears the re quest. A special ac tion must be taken in the interrupt service routine for the other interr upts . T able 7-15. Interrupts—Pri ority and Action t [...]

User ’ s Ma nua l 99 7.10.1 Exte rnal Inte rrupt s There are two exter nal in terrupts. Each interrupt has 2 input pins that can be used to trig- ger the interrupt. The inputs have a pulse catche r that can detect rising, falling or either ris- ing or falling edges. Figure 7-6. External Interrupt Line Logic The external interrupts take place on a[...]

100 Rabbit 3000 Micropro cessor 7.10.2 Interrupt V ectors: INT0 - EIR,0x00 /INT1 - EIR,0x08 When it is desired to expand the number of in terrupts for additional peripheral devices, the user should use the interrupt routine to dispatch interrupts to other virtual interrupt rou- tines. Each additional interrupting device will have to signal the proc[...]

User ’ s Ma nua l 101 7.1 1 Boot strap Operation The device provides the option of bootstrap from any of three sources: f r om the Slave Port, from Serial Port A in clocked serial mode, or from Serial Port A in asynchronous mode. This is controlled by the state of the SMODE pins after reset. Bootstrap operation is disabled if (SMODE1, SMODE0) = ([...]

102 Rabbit 3000 Micropro cessor Serial Port A is selected for bootstrap opera tion as a clocke d serial port when SMODE = 10. In this case bit 7 of Parallel Port C is used for the serial data and bit 1 of Parallel P ort B is used for the serial clock. Note that the se rial clock must be externally supplied for boot- strap operation. This precludes [...]

User ’ s Ma nua l 103 7.12 Pulse Wid th Modulator The Pulse W idth Modulator consists of a te n-bit free running counter , and four width reg- isters. Each PWM output is High for "n + 1" counts out of the 1024-clock count cycle, where "n" is the value held in the width register . The PWM output High tim e can option- ally be s[...]

104 Rabbit 3000 Micropro cessor T able 7-17. PW M LSB x Register PWM LSB x Register (PWL0R) (Add r ess = 0 x88) (PW L1R) (Addre ss = 0x8A) (PW L2R) (Addre ss = 0x8C) (PW L 3R) (A d dress = 0x8E) Bit (s) Va l u e Description 7:6 write The least significant two bits f or the Pulse W idth Modulator count are sto red. 5:1 T hese bi t s are igno red. 0 [...]

User ’ s Ma nua l 105 7.13 Input Captur e The two-channel Input Capture can be used to time input signals from various port pins. Each Input Capture channel consists of a sixt een-bit counter that is clocked by the output of T imer A8, and c an be connected to one or two out of sixteen parallel port pins. The Input Capture channel captures the st[...]

106 Rabbit 3000 Micropro cessor Each Input Capture counter opera t es in one of three modes, or can be disabled. The counter is never automatically reset, but must be reset by a software command. Although it does not generate an interrupt, there is a status bit which is set when the counter over- flows (counts from 0xFFFF to 0x0000) so that softwar[...]

User ’ s Ma nua l 107 T able 7-19. Input Capture Control/ S tatus Register Input Capture Control/St atus Register (ICCSR) (Address = 0x56) Bit (s) Va l u e Description 7:2 (read) These status bits (but not the interrupt enab le bits) are clear ed by the read of this register , as is the Input Captu re Interrupt. 7 0 The Input Capture 2 S tart con[...]

108 Rabbit 3000 Micropro cessor T able 7-20. Input Capture Control Regi ster Input Capture Control Register (ICCR) (Address = 0 x57) Bit (s) Va l u e Description 7:2 T hese bi t s are igno red. 1:0 00 Input Capture i nterrup ts are dis abled. 01 Input Capture in t er rupt use Inter rupt Pr iority 1 . 10 Input Capture in t er rupt use Inter rupt Pr [...]

User ’ s Ma nua l 109 T able 7-22. Input Capture Source x Register Input Capture Source x Regis t er (ICS1R) (Address = 0 x59) (ICS2R) (Add re ss = 0x5D) Bit (s) Va l u e Description 7:6 00 Parallel Po r t C used for St art condition input. 01 P ara llel Port D used for Start condition input. 10 P ara llel Port F used for Start co ndition input. [...]

11 0 Rabbit 3000 Micropro cessor 7.14 Quadrature Decoder The two-channel Quadratur e Decoder accepts i nputs, via Port F , from two external optical incremental encoder modules. Each c hannel of the Quadrature Decoder acc epts an in- phase (I) and a quadrature-phase (Q) signal and provides 8-bit counters to track shaft rota- tion and provide interr[...]

User ’ s Ma nua l 111 The Quadrature Decoder generate s an interrupt when the counter increments from 0xFF to 0x00 or when the counter decrements from 0x00 to 0xFF . The timing for the interrupt is shown below . Note that the status bits in the QDCSR are se t coinc ident with the inte rrupt, and the interrupt (and status bits) are clear ed by rea[...]

11 2 Rabbit 3000 Micropro cessor T able 7-25. Quadrature Decoder Contro l/Status Re gist er Quad D ecode Control/Status Register (QDCSR) ( Address = 0x90) Bit (s) Va l u e Description 7 0 Q u adrature Decoder 2 did not increment fr om 0xFF . (read-only) 1 Quadrature Decoder 2 incremented from 0 x FF to 0x00. This bit is cleared by a read of his re [...]

User ’ s Ma nua l 11 3 T able 7-26. Quadrature Decoder Control Register Quad Decode C o ntrol Register (QDCR) (Addre ss = 0x91) Bit (s) Va l u e Description 7:6 00 Disable Quadratur e Decoder 2 inputs. W riting a new value to t hese bits wi ll not cause Quadrature Decod er 2 to incr ement or decrement. 01 This bit combination is reserved and shou[...]

11 4 Rabbit 3000 Micropro cessor[...]

User ’ s Ma nua l 11 5 8. M EMOR Y I NTERF ACE AN D M APPING 8.1 Interface for S t atic Memory Chip s St atic memory chips generally have address lines , data line, a chip select line, an output enable line and a write enable. T h e Rabbit 3000 has these same lines that can connect directly to a number of static memory chips. The chip selects are[...]

11 6 Rabbit 3000 Micropro cessor Figure 8- 2. T ypica l Memory Chip Co nnection Rabbit 30 00 DA T A LINES (8) ADDRESS LINES (20) /CS /WE /OE /CS0 /CS1 /CS2 /OE0 /OE1 /WE0 /WE1 ST A TIC /CS /WE /OE MEMOR Y FLAS H ST A TIC MEMOR Y RAM[...]

User ’ s Ma nua l 11 7 8.2 Memory Mapping Overview See Section 3.2, “Memory Mapping,” for a discussion of Rabbit memory mapping. Figure 8-3 shows an overview of the Rabbit memory mapping. The task of the memory mapping unit is to accept 16-bit addresses and translate them to 20-bit addresses. The memory interf ace unit accepts the 20-bit addr[...]

11 8 Rabbit 3000 Micropro cessor Figure 8-4. Memory Seg ments The memory manage ment unit accepts a 16-bit address from the processor and translates it into a 20-bit address. The procedure to do this works as follows. 1. It is determined which segment the 16-bit address belongs to by inspec ti ng the upper 4 bits of the address. Every address must [...]

User ’ s Ma nua l 11 9 8.4 Memory Interface Unit The 20-bit memory addresses generated by the memory-mapping unit feed into the mem- ory interface unit. The m emory interf ace unit ha s a separate write-only control register for each 256K quadrant of the 1M physical memory . This control register specifies how mem- ory access requests to that qua[...]

120 Rabbit 3000 Micropro cessor 8.5 Memory Bank Control Registers T able 8-3 describes the operation of the four memory bank control register s . The registers are write-only . Each register controls one quadrant in the 1M address space. Bits 7,6—The n umbe r of wait states used in acces s to this quadr ant. W ithout wait states, read r equires 2[...]

User ’ s Ma nua l 121 Bit 3—Inhibits the write pulse to memory accessed in this quadran t. Useful for pr otecting flash mem- ory from an inadvertent write pu lse, which will not actually write to th e flash because it is protected by lock codes, but wi ll temporarily disable the flas h memory and crash the system if the memor y is used for code[...]

122 Rabbit 3000 Micropro cessor The Memory T iming Control Register (MTCR) enables the extended timing for the memory output enables and write enables. See Figure 7-2 for details on how the timing of the mem- ory read and write st robes is affected when using the early output enable and write enable options. Figure 16 -3 shows extended output en ab[...]

User ’ s Ma nua l 123 The Breakpoint/Debug controller allows the RST 28 instruction to be used as a software breakpoint. Normally the RST 28 instruct ion causes a call to a particular location in mem- ory , but the operation of this instruction is modified when the breakpoint/debug feat ure is enabled. The RST 28 instruction is treated as a NOP i[...]

124 Rabbit 3000 Micropro cessor 8.7 Instruction and Dat a Space Support Instruction and Data space (I and D space ) support is accomplished by optionally i nvert- ing address lines A16 and/or A19 when the pr ocessor accesses D space , but n ot inverting those lines when the processor accesses I sp ace. The MMIDR re gis ter (see T able 8-8) is used [...]

User ’ s Ma nua l 125 are mapped into contiguous regions of memory to create a continuous root code segment starting at the bottom of physical me m ory in flash. In the I spac e the division between the root segment and the data segment is irrele vant because the DA T A SEG regist er contains zero and the division between the segments defined by [...]

126 Rabbit 3000 Micropro cessor Figure 8-6. Use of Physic al Memory Sep arate I & D Space M odel In Figure 8-6 a rrows indicate the di rection in which variables and constants are allocated as the compile or assemble proceeds. Each of these arrow s starts at a constant location in physical memory . This is important because the Dynamic C debugg[...]

User ’ s Ma nua l 127 8.8 How the Compiler Compiles to Memory The compiler actually generates c ode for root code and constants and extended code and extended constants. It allocates space f or data variables, but does not generate data bits to be stored in memory . In any but the smallest programs, most of th e code is compiled to extended memor[...]

128 Rabbit 3000 Micropro cessor[...]

User ’ s Ma nua l 129 9. P ARAL LEL P ORT S The Rabbit has seven 8-bit parallel ports designated A, B, C, D, E, F , and G . The pins used for the par allel ports a re als o share d with num erous other functions as shown in T able 5-2. The important properties of the ports are summarized be low . • Port A—Shared with the slave port data inter[...]

130 Rabbit 3000 Micropro cessor 9.1 Para ll el Port A Parallel Por t A has a single r ead/write regist er: This register should not be used if the slave port or auxiliary I/O bus is enabled. The slave port control register is used to cont rol whether Parallel Port A is configured as slave databus, auxiliary I/O data bus, pa rallel Input or parallel[...]

User ’ s Ma nua l 131 9.2 Parall el Port B Parallel Port B, has eight pins that can progr ammed individually to be inputs and outputs. After reset, Parallel Port B comes up as six inputs (PB[5:0] ) and two outp uts (PB7 and PB6). The output value on pins PB6 and PB7 (package pins 99, 100) will be low . When the auxiliary I/O bus is enabled, Paral[...]

132 Rabbit 3000 Micropro cessor 9.3 Para ll el Port C Parallel Port C, shown in T able 9-6, has four inputs and four outputs. The even-numbered ports, PC0, PC2, PC4, and PC6, are outputs. The odd-numbered ports, PC1, PC3, PC5, and PC7, are inputs. When the data register is read, bits 1,3,5,7 return the value of the volt- age on the pin. Bits 0,2,4,[...]

User ’ s Ma nua l 133 9.4 Parall el Port D Parallel Port D, shown in Figure 9-1, has eight pins that can be programmed individually to be inputs or outputs. When programmed as outputs, the pins can be individually selected to be open-drain outputs or standard outputs. Port D pins can be addressed by bit if desired. The output registers are cascad[...]

134 Rabbit 3000 Micropro cessor Figure 9-1. Parallel P ort D Block Diagram PD7 PD4 I/O Data perclk /2 Timer A1 Tim er B1 Timer B2 perclk/ 2 Timer A1 Tim er B1 Timer B2 PD3 PD0 AT X A AT X B ARXA ARXB PD5 PD6 inputs Driver—opti on a l open dra in[...]

User ’ s Ma nua l 135 T able 9 - 8. Parallel Port D Register function s Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PDDR (R/W) adr = 0x060 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PDDCR (W) adr = 0x066 out = open drain out = open drain out = open drain out = open drain out = open drain out = open drain out = open drain out = open drain PDFR ( W) adr =[...]

136 Rabbit 3000 Micropro cessor The following registers are described in T a bl e 9-8 and in T able 9-9. • PDDR—Paralle l Port D data re gister . Read /W rite. • PDDDR—Parallel Port D data direction regi ster . A "1" makes the corresponding pin an output. W rite only . • PDDCR—Parallel Port D drive control regi ster . A "[...]

User ’ s Ma nua l 137 9.5 Parall el Port E Parallel Port E, shown in Figure 9-2, has ei ght I/O pins that can be individually pro- grammed as inputs or outputs. PE7 is used as the slave port chip se l ect when the slave port is enabled. Each of the port E outputs can be c onfigured as an I / O strobe. In a ddi tion, four of the port E lines can b[...]

138 Rabbit 3000 Micropro cessor The following registers are described in T a bl e 9-1 1 and in T a ble 9-12. • PEDR—Port E data register . Reads value at pins. W rites to port E preload register . • PEDDR—Port E data direction register . Set to "1" to make corresponding pin an out- put. This register is zeroed on reset. • PEFR?[...]

User ’ s Ma nua l 139 T able 9-1 1. Parallel Port E Register functi ons Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEDR (R /W) adr = 0x070 PE7 PE6 PE5 PE4 PE3 P E2 PE1 PE0 PEFR ( W) adr = 0x075 alt /I7 alt /I6 alt /I5 alt /I 4 alt /I3 alt /I2 alt /I1 alt /I0 PEDDR (W) adr = 0x077 dir = out dir = out dir = out dir = out dir = out dir = out di[...]

140 Rabbit 3000 Micropro cessor 9.6 Para ll el Port F Parallel Por t F is a byte-wide port with each bit programmable for data direction and drive. These are simple inputs and outputs controlled and reported in the Port F Data Register . As outputs, the bits of the port are buf fered, with the data writte n to the Port F Data Re gis- ter transfe rr[...]

User ’ s Ma nua l 141 The following registers are described in T a bl e 9-14 and in T able 9-15. • PFDR—Port F data register . Reads value at pins. W rites to port F preload register . • PFCR—Parallel Port F control regist er . This re gist er is used to control the clocking of the upper and lower nibble of the final output register of th[...]

142 Rabbit 3000 Micropro cessor The functionality of the Parallel Port F pins is not affected for pulse width modulation out- puts and serial clock outputs, except that th e Parallel Port F function and direction regis- ters should be set up before a conflicting function on Parallel Port A is in use, since writing to these registers also writes to [...]

User ’ s Ma nua l 143 9.7 Parall el Port G Parallel Port G is a byte-wide port with e ach bit programmable for data direc t ion and drive. These a r e simple inputs and outputs c ont rolled and reported in the Port G Data R eg- ister . As outputs, the bit s of the port a re buf fered, with the data written to t he Port G Data Register transferred[...]

144 Rabbit 3000 Micropro cessor The following registers are described in T a bl e 9-17 and in T able 9-18. • PGDR—Port G data register . Reads value at pins. W rites to port G prel oad register . • PGCR—Parallel Port G control register . This re gister is used to control the clocking of the upper and lower nibble of the final output registe[...]

User ’ s Ma nua l 145 10. I/O B ANK C ONTROL R EGIST ERS The pins of Port E can be se t ind ividually to be I/O strobes. Each of the eight possible I/O strobes has a control register that controls th e nature of the strobe and the number of wait states that will be inserted in the I/O bus cycle. W rites can also be suppressed for a ny of the stro[...]

146 Rabbit 3000 Micropro cessor T able 10-1 shows how the eight I/O bank control registers are organized. T able 10-1. I/O Bank x Control Register I/O Bank x Control Regis ter (IB0CR) (Address = 0 x0080) (IB1CR) (Address = 0x00 81) (IB2CR) (Address = 0x00 82) (IB3CR) (Address = 0x00 83) (IB4CR) (Address = 0x00 84) (IB5CR) (Address = 0x00 85) (IB6CR[...]

User ’ s Ma nua l 147 The eight I/O bank c ontrol registers determine th e number of I/O wait st ates applied to an external I/O ac cess within the zone control l ed by each regi ster even if the associated strobes are not enabled. Note that the /IORD and /IOWR signals reflec t these registers as well. The control over the generation of wa it sta[...]

148 Rabbit 3000 Micropro cessor[...]

User ’ s Ma nua l 149 1 1. T IMERS There are two ti mers—T imer A and T imer B. T imer A is intended mainly f or generat ing the clock for various periphera l s, baud clock for the serial ports, a periodic clock f or clocking Parallel Ports D and E, or for gene rating per i odic interrupts. T imers A1–A7 are general-purpose timers, and T ime [...]

150 Rabbit 3000 Micropro cessor 1 1 .1 Timer A T imer A consists of ten separa te count down tim ers A1–A10 as shown in Figure 1 1-1. T imers A1 and A2–A10 a r e 8-bit countdown regi sters as shown in Figure 11-2. The reload register can contain any number in the range from 0 to 255. The counter divides by (n+1). For example, if the reload regi[...]

User ’ s Ma nua l 151 For seven of the cou nters (A1–A7), the terminal count condition is reported in a status regis- ter and can be programmed to generate an interrupt. The re is one interrupt vector for T imer A and a common interrupt priority . A common st atus register (T ACSR) has a bi t for each timer that indicates if the output pulse fo[...]

152 Rabbit 3000 Micropro cessor The following table summa rizes T imer A ’ s capabilitie s. The control/ status register for Ti mer A (T ACSR) is laid out as shown in T able 11-3. T able 1 1-2. T imer A Capabiliti es Timer Casc ade Interrupt Dedicat ed Connection A1 none yes Parallel P orts D-G , T imer B A2 from A1 y es Serial Port E A3 from A1 [...]

User ’ s Ma nua l 153 4 (write) 0 A4 interrupt disa bled. 1 A4 interrupt enabled. 3 (read) 0 A3 counter has no t reached its terminal cou nt. 1 A3 count don e. This status bit is clear ed by a read of this register . 3 (write) 0 A3 interrupt disa bled. 1 A3 interrupt enabled. 2 (read) 0 A2 counter has no t reached its terminal cou nt. 1 A2 count [...]

154 Rabbit 3000 Micropro cessor The control register (T ACR) is laid out as shown in T able 1 1-4. The T imer A Prescale Re gister (T APR) specifies the ma in clock for T imer A. This wil l affect all of the timer A countdown timers. By default T imer A is clocked by peripheral clock divided by two. The prescale register ( T APR) is laid out as sho[...]

User ’ s Ma nua l 155 The time constant regist er for each timer (T A TxR) is simply an 8-bit data register hol ding a number between 0 and 255. This time constant will take effect the next tim e that the T imer A counter counts down to zero. The timer counts modulo (divide-by) n+1, where n is the progra mmed time consta nt. The time cons tant re[...]

156 Rabbit 3000 Micropro cessor 1 1 .2 Timer B Figure 1 1-1 shows a block diagram of Tim er B. The T imer B counter can be driven directly by perclk/2, by that clock divided by 8, or by the out put of T imer A1. T imer B has a continuously running 10-bit counter . The counter i s compared against two match regis- ters, the B1 ma tch register a nd t[...]

User ’ s Ma nua l 157 The control/status register for T imer B (TBCSR) is laid out as shown in T able 1 1-7. The control register for T imer B (TBCR) is laid out as shown in T able 1 1-8. T able 1 1-7. Ti mer B Control and St atus Register Timer B Contr o l and St atus Re gister (TBCSR ) (Address = 0x00B0) Bit(s) Va l u e Desc ription 7:3 These b[...]

158 Rabbit 3000 Micropro cessor The MSB x registers for T imer B (T B M1R/TBM2R) are laid out as shown in T able 1 1-9. The LSB x registers for T imer B (TBL1R/TBL2R) are laid out as shown in T able 1 1-10. T able 1 1-9. Ti mer B Count MSB x Register s Timer B Count MSB x Register (TBM1R) (Address = 0xB2) (TBM2R) (Addre ss = 0xB4) Bit (s) Va l u e [...]

User ’ s Ma nua l 159 1 1.2.1 Using T imer B Normally the prescaler is set to divide perc lk/2 by a number that provides a counting rate appropriate to the problem. For example, if the clock is 22.1 184 MHz, then pe rclk/2 is 1 1.0592 MHz. A T imer B clock rate of 1 1.0592 MH z will cause a complete cycle of the 10-bit clock in 92.6 µ s. Normall[...]

160 Rabbit 3000 Micropro cessor T imer B can be used f or various purposes. The 10-bit counter can be read to record the time at which a n event t akes place. If the e vent creates an interrupt, the time r can be re ad in the interrupt routine. The known time of execution of the interrupt routine can be sub- tracted. The varia ble interrupt lat enc[...]

User ’ s Ma nua l 161 12. R ABBI T S ERIA L P OR T S The Rabbit 3000 has 6 on-chi p serial por ts designat ed A , B, C, D, E, and F . All the ports can per- form asynchronous serial communication s at high baud rates. Ports A-D can operate as clocked ports. Ports A and B can be swi tched to al ternate p ins. Ports E and F supp ort SDLC/ H DLC syn[...]

162 Rabbit 3000 Micropro cessor Figure 12-1 shows a block diagram of the serial ports. Figure 12-1. Block Diagram of Rabbit Serial Ports Serial Port F TXF Serial Trans mit Out RXF Serial T ransmit In TCLKF Optional external transmit clock RCLKF Optional external receive clock T able 12-1. Serial Port Signals (conti nued) Seria l P ort Si gnal Name [...]

User ’ s Ma nua l 163 The individual serial ports are capable of operating at baud rates in excess of 500,000 bps in the asynchronous mode, and 8 times faster th an that in the synchronous mode. Either 7 or 8 data bits may be tran smitted and received in the asynchronous mode. The so-called "9th" bit or address bit mode of operation is [...]

164 Rabbit 3000 Micropro cessor 12.1 Serial Port Registe r Layout Figure 12-2 shows a functional block diagram of a serial port. Each serial port has a data register , a control register and a status regis ter . W riting to the data register starts transmis- sion. The least significant bit (LSB) is always tr ansmitted first. This is true for both a[...]

User ’ s Ma nua l 165 The clock in put to the serial port unit mu st be 8 or 16 (selectable) times th e baud rate in the asynchron ous mode and 2 times the baud rate for the clocked serial mode when the internal clock is used. T imers A2–A7 s u pply the inp u t clock for Serial Po rts A– F . Thes e timers ca n divide t he frequency by any n u[...]

166 Rabbit 3000 Micropro cessor 12.2 Serial Port Registe r s Each serial po rt has 6 registers shown in t he ta bl e s below . The status, control and extended registers may have somewhat different formats for different serial ports. T able 12-2. Seri al Port A Registers Register Name Mnemonic I/O A d dress R/W Reset Serial Port A Data Regi ster SA[...]

User ’ s Ma nua l 167 T able 12-5. Seri al Port D Registers Register Name Mnemonic I/O A d dress R/W Reset Serial Port D Data Regi ster SDDR 0xF0 R/W xxxxxxxx Serial Por t D Addr ess Regi ster SDAR 0xF1 W xxxxxx xx Serial Por t D Long S top Regist er SDLR 0xF2 W xxxxxxxx Serial Por t D S tatus Reg ister SDSR 0xF3 R 0xx0 0000 Serial Por t D Co ntr[...]

168 Rabbit 3000 Micropro cessor T able 12-8. Data Register All Port s Serial Po rt x Data Register ( SADR) (Ad dress = 0xC0) (SBDR) (Address = 0xD0) (SCDR) ( Address = 0xE0) (SDDR) (Address = 0xF0) (SEDR) (Address = 0xC8) (SFDR) (Address = 0xD8) Bit (s) Va l u e Description 7:0 Read Returns the contents of the receive buf fer . W rite Loads the tra[...]

User ’ s Ma nua l 169 T able 12-10. Lon g Stop Regist er All Por ts Serial Port x Long Stop Register (SALR) (Address = 0xC2) (SBLR) (Address = 0xD2) (SCLR) (Address = 0xE2) (SDLR) (Addres s = 0xF2) (SELR) (Add r ess = 0xCA) (SFLR) (Address = 0xDA) Bit (s) Va l u e Description 7:0 Read R eturn s the contents of the receive buf f er . W rite Loads [...]

170 Rabbit 3000 Micropro cessor T able 12-1 1. S tatus Register Asynchronous Mode Only (All Ports) Serial P ort x St a t us Register (S ASR) (Add ress = 0xC3) (SBSR) (Address = 0xD3) (SCSR) (Address = 0x E3) (SDSR) (Address = 0xF3) (SESR) (Address = 0xCB) (SFSR) ( Address = 0xDB) Bit (s) Va l u e Description (Async mode only) 7 0 The receive data r[...]

User ’ s Ma nua l 171 T able 12-12. Stat us Register Clocked Serial (Ports A-D only) Serial P ort x St a t us Register (SASR) (Addr ess = 0xC3) (SBSR) (Address = 0x D3) (SCSR) (Address = 0x E3) (SDSR) ( Ad dre ss = 0xF3) Bit (s) Va l u e Descr iption (Clocked s erial mode only) 7 0 The receive data register is empty 1 There is a byte in the recei[...]

172 Rabbit 3000 Micropro cessor T able 12-13. S tatus Regi ster HDLC Mode (Ports E and F only) Serial P ort x St a t us Register (SESR) (Address = 0x CB) (SFSR) (Addr ess = 0xD3) Bit (s) Va l u e Description (HDLC mode only) 7 0 The receive data register is empty 1 There is a byte in the receive buf fer . Th e serial port will r equest an interru p[...]

User ’ s Ma nua l 173 T able 12-14. Serial Port Control Register Port s A and B Serial Po rt x Control Re gister (SAC R) (Address = 0xC4) (SBCR) (Address = 0xD4) Bit (s) Va l u e Description 7:6 00 No operation. These bits are ign ored in the Async mo de. 01 In clocked serial mode, start a b yte receive operation. 10 In clocked serial mode, start[...]

174 Rabbit 3000 Micropro cessor T able 12-15. Serial Port Control Register Port s C and D Serial Po rt x Control Re gister ( S CCR) ( Address = 0xE4 ) (SDCR) (Address = 0xF4) Bit (s) Va l u e Description 7:6 00 N o operation. Thes e bits are ignored in th e async mode. 01 In clocked serial mo de, st art a b yte receive operation. 10 In clocked seri[...]

User ’ s Ma nua l 175 T able 12-16. Serial Port Control Register Ports E and F Serial Po rt x Control Re gister (S ECR) (Address = 0xCC) (SFCR) (Addr ess = 0xDC) Bit (s) Va l u e Description 7:6 00 N o operation. Thes e bits are ignored in th e Async mode. 01 In HDLC mode, force receiver in Flag Search mo de. 10 No operation. 1 1 In HDLC mode, tr[...]

176 Rabbit 3000 Micropro cessor T able 12-17. Extended Register Asynchronous Mode All Port s Serial P ort x Extende d Register (S AER) (Ad dress = 0xC5) (SBER) (Address = 0xD5) (SCER) (Addr ess = 0xE5) (SDER) (Address = 0xF5) (SEER) (Ad dr ess = 0xCD) (SFER) (Add r ess = 0xDD) Bit (s) Va l u e Description (Async mode only) 7:5 xxx These bits are ig[...]

User ’ s Ma nua l 177 T able 12 -18. Extended Register Clocked Serial Mode (Ports A-D only) Serial P ort x Extende d Register (S AER) (Ad dress = 0xC5) (SBER) (Address = 0xD5) (SCER) (Addr ess = 0xE5) (SDER) (Address = 0xF5) Bit (s) Va l u e Descr iption (Clocked s erial mode only) 7 0 N o rmal clocked serial operation . 1 Timer s ynchronized cl [...]

178 Rabbit 3000 Micropro cessor T able 12-19. Extended Register HDLC Mode (Ports E and F only) Serial P ort x Extende d Register (SEE R) (Ad dress = 0xCD) (SFER) (Add r ess = 0xDD) Bit (s) Va l u e Description (HDLC mode only) 7:5 000 N RZ data encoding for HDLC receiver and transmitter . 010 N RZI d ata encoding for HDLC receiver an d transmitter [...]

User ’ s Ma nua l 179 12.3 Serial Port Interr upt A common inte rrupt vec tor is used for the re ceive and trans mit interrupts. There is a sepa- rate i nterrupt re quest fli p-flop for the recei ver and transm itter . If either of these f lip-flops is set, a serial port interrupt is requested. Th e flip-flops are set by a rising edge only . T he[...]

180 Rabbit 3000 Micropro cessor 12.4 T ransmit Serial Dat a Ti ming On transmit , if the int errupts are e nabled , an inte rrupt is reque sted when the transmit regis- ter becomes empty and, in addition, an interrupt occurs when the shift register and trans- mit register both become empty , that is, when the transmitter becomes idle. The shift reg[...]

User ’ s Ma nua l 181 12.5 Receiv e Serial Dat a T iming When the receiver is ready to rec e ive data, a falling edge indicates that a start bit must be detected. The fa l ling edge is detec ted as a dif fere nt R x i nput be tween two dif ferent clocks, the clock being 8x or 16x the baud rate. Once th e start bit has be en detected, data bits ar[...]

182 Rabbit 3000 Micropro cessor 12.6 Clocked Serial Port s Ports A–D can operate in clocked mode. The data line a nd clock line are driven as shown in Figure 12-4. The data and clock are provided as 8-bit bursts with the LSB shifted out and/or received f irst. By default the tr ansmit shi ft regist er advanc es on the falling edge of the clock an[...]

User ’ s Ma nua l 183 with new incoming da ta. Similar ly , writing the data to the S xAR register causes the tran s- mitter to start a byte transmit operation, eliminating the need for the software to issue the St art T ransmit command. The effect of these codes is different, depending on whether the mode is internal clock or external clock. T o[...]

184 Rabbit 3000 Micropro cessor answer its interr upts within 20 µ s. There will be no slow down if the receiver can answer its interrupt within 1/2 clock or 1.25 µs. If it can answer within 1.5 clocks, or 2.75 µ s, the data rate will slow to 44,444 byt es per second. If it can answer in 2.5 clocks or 6.25 µ s, the data rate slows to 40,000 byt[...]

User ’ s Ma nua l 185 12.7 Cl ocked Serial T iming 12.7.1 Clocked Serial T iming With Internal Clock For synchronous serial communication, the seri al clock c an be either generated by the Rabbit or by an external device. The timing diagram in Figure 12-6 below can be applied to both full-duplex and half- dupl e x clocked se rial communication wh[...]

186 Rabbit 3000 Micropro cessor Figure 12-8 shows the timing relationship among perclk , t he external serial clock, and data receive. Note that RxA is sampled by the rising edge of perclk . Figure 12-8. Synchronous Ser ial Data Receive Ti ming with External Clock (Mode 00) When cloc king the Rabbit externally , the m aximum seri al clock fre quenc[...]

User ’ s Ma nua l 187 12.8 Synchrono us Communications on Por t s E and F Serial Port E and F are a dual-function serial ports that can be used in either asynchronous or HDLC mode. Four bytes of buffering are ava ilable for both receiver and transmitter to reduce interrupt overhea d. An int errupt is gene rated whenever at least one byte is avai [...]

188 Rabbit 3000 Micropro cessor the current receive f r ame is not needed (because it is addressed to a different station, for example) a Flag Search command is available . Thi s c ommand forces the receiver to ignore the incoming data st re am until a nother Fl ag is r eceived. I n the transmit ter , the CRC gener- ator is pre set and the opening [...]

User ’ s Ma nua l 189 In HDLC mode the internal clock come s from th e output of T imer A2. This timer output i s divided by sixteen to form the trans mit clock, and is f e d to the D i gital Phase-Locked Loop (DPLL) to form the receive clock. The DPLL i s basically just a divide-by-16 counter that uses the timing o f the tra nsitions on the rece[...]

190 Rabbit 3000 Micropro cessor clock rate must be very small, and depends on the longest possible run of zeros in the received frame. NRZI encoding guar antees at least one transition every six bits (with the inserted zeros). Since the DP LL can adjust by two counts every bit cell, the maximum di f- ference between the sending da ta r ate and the [...]

User ’ s Ma nua l 191 W ith NRZ and NRZI encoding all transiti ons occur on bit-cell boundaries and the data should be sampled in t he middle of the bit cell. If a t ransition occurs after the expected bit- cell boundary (but before the midpoint) the DPLL needs to lengthen the count to line up the bit-cell boundaries. This c orresponds to the “[...]

192 Rabbit 3000 Micropro cessor 12.9 Serial Port Softwa re Suggestions The receiver a nd transmitt er share th e same inte rrupt vector , but it is possible to make the receive and transmi t interr upt servi ce routines (ISRs) separate by dispatching the interrupt to either of two dif ferent routines. This is desirable to make the ISR less complex [...]

User ’ s Ma nua l 193 LD (HL),A ; 6 update the in pointer IOI LD A,(SCDR) ; 11 get data register port C, clears interrupt request IPRES ; 4 restore the interrupt priority ; 68 clocks to here ; to level before interrupt took place ; more interrupts could now take place , ; but receiver data is in registers ; now handle the rest of the receiver int[...]

194 Rabbit 3000 Micropro cessor 2. Clear bit 4 of the Parallel Port C function register so that the output no longer comes from the serial port. Of course, this s hould not be done until the transmitter is idle. A similar procedure can be used if the serial port is set up t o use alternate outp ut pins on port D. Only Serial Ports A and B can use a[...]

User ’ s Ma nua l 195 Figure 12-9 illustrates the standard asynchronous serial output patterns. Figure 12-9. Asynchronous Se r ial Output Patte rns 12.9.6 Parity , Ex tra S top Bit s with 7-Dat a-Bit Charac ters If only 7 data bits are being sent, se nding an add itional pa ri ty or signal bit is e asil y solved by sending 8 bits and alwa ys sett[...]

196 Rabbit 3000 Micropro cessor 12.9.8 Supporting 9th Bi t Communic ation Protocols This section describes how 9th bit communi cat ion protocols work. 9th bit c omm unication protocols are supported by processors such as the 8051 and the Z180, and by companie s such as Cimentrics T echnology . The data bytes have an extra 9th bit appended wher e a [...]

User ’ s Ma nua l 197 the receiving interrupt service routine to detect t his gap, it is suggested that dummy char- acters be transmitted to help detect the gap. This can be done in the following manner . The trans mitter starts tr ansmitti ng dummy charact ers when the fir st charac ter interrupt is receive d. Each time the re is an interr upt, [...]

198 Rabbit 3000 Micropro cessor[...]

User ’ s Ma nua l 199 13. R ABBIT S LAVE P ORT When a Rabbit microprocessor is configured a s a sl ave, Parallel Port A and cer t ain other data lines are used as communication lines between the slave and the master . The slave unit is a Rabbit configured as a slave. The ma ster can be another Rabbit or a ny other type of processor . Rabbits conf[...]

200 Rabbit 3000 Micropro cessor A status register can be read by either the slave or t he master . The status register has full/ empty bits for each of the six regist ers. A da t a register is c onsi dered full when it i s written to by whichever side is capable of writing to it. If the same register is then read by either side it is c onsidered to[...]

User ’ s Ma nua l 201 The following table explains the parameters used in Figure 13-2. The two SPD0R re gister s have spec ial f unctiona lity not sha red by the other data re gister s. If the master writes to SPD0R, an inbound interrupt flip-flop i s set. If slave port interrupts are enabl e d, t he slave processor will t ake a slav e port int e[...]

202 Rabbit 3000 Micropro cessor Figure 13-3. Sla ve Port Handshaking and In terrupts Figure 13-4 shows a sample connection of two sl ave Rabbits to a master Rabbit. The m as- ter drives the slave reset line for both slaves and provides the main processor clock from its own clock. There is no requirement that the master and slave share a clock, but [...]

User ’ s Ma nua l 203 Figure 13-4. T ypical Connection Slave Rabbit to Master Rabbit The slave port lines are shown in Figure 13-1. The function of these lines is described below . • SD0–SD7—These are bidirectional data lines, and are ge nerally connected to the data bus of the master processor . Multiple sl aves can be connected to the dat[...]

204 Rabbit 3000 Micropro cessor • /SLA VEA TTN—This l ine is set low (asserted) if the slave writes to the SPD0R register . This line is set high if the master writ es anythi ng to the slave status registe r . This line is usually connected to cause the master t o be interrupted when it goes low . The data lines of the slave port are shared wit[...]

User ’ s Ma nua l 205 If the user for some reason wants to depart from the suggested protocols and poll a register while waiting for the other side to write someth ing to the register , the user should be aware that all the bits might not change at the exac t same time when the result changes, and a transitional value could be re ad from the regi[...]

206 Rabbit 3000 Micropro cessor Bits 1,0— This 2- bit f ield se ts the pr iority o f th e sl ave por t int errupt. Th e in terr upt is di sable d by (0,0). T able 13-3 describes the slave port status register . The stat us register has 6 bits that are set if the particular register is full . That me ans that the registe r has been written by the [...]

User ’ s Ma nua l 207 require a speciality processor . The slave proc essor ca n process data to perform pattern recognition or to extract a spec i fic parameter f r om a data stream. 13.3.2 Maste r-Slave M essaging Pr o t ocol In this protocol the master sends messages to the slave and receives an acknowledgeme n t message. The protocol can be p[...]

208 Rabbit 3000 Micropro cessor for this.) Once the software is loa ded into th e slave, the sla ve can begin t o perform its function. As a simple example, suppose that the slave is to be used as a four-port UAR T . It has the capability to send or receive char acters on any of its four serial ports. Leaving aside the question of setup for paramet[...]

User ’ s Ma nua l 209 14. R ABBIT 3000 C LOCKS The Rabbit 3000 normally uses two clocks, the main cloc k and the 32.768 kHz clock. The 32.768 kHz clock is needed for the batter y-backable clock, the watchdog timer , and the cold-boot function. The main oscillator provid es the run-time clock for the microproces- sor . Figure 14-1 shows the main o[...]

210 Rabbit 3000 Micropro cessor 14.1 Low-Power Design The power consumption is proportional to the clock frequency and to the square of the operating voltage. Thus, operating at 3.3 V inst ead of 5 V will r e duce the power consump- tion by a factor of 10.9/25, or 43% of the power required at 5 V . The clock speed is reduced proportionally to the v[...]

User ’ s Ma nua l 21 1 15. EMI C ONTR OL EMI or electromagnetic interference from unint entional radiation is of concern to the microprocessor system designer . One concern is passing the tests sometim es required by the U.S. Federal Comm unications Commiss ion (FCC) or by the European EMC Directive. For exampl e, in th e U.S. the FC C requires t[...]

212 Rabbit 3000 Micropro cessor 15.1 Po wer Supply Connections and B oard Layout Refer to T echnica l Note TN221, PC B oard Layout Suggestions for the Rabbi t 3000 Microprocessor , for recommendations on laying out a PC board to minmize EMI emsis- sions. 15.2 Using the Clock Spectrum Spreader The spectrum spreader is very powerful for reducing EMI [...]

User ’ s Ma nua l 213 When the spectrum spreader is engaged, the frequency is modulate d, and individual clock cycles may be shortened or lengthened by an amount that depends on whether the clock doubler is engaged and whether the spectrum sp reader is set to th e normal or strong set- ting. The frequency modulation amplitude and the change in cl[...]

214 Rabbit 3000 Micropro cessor so low as to be undetectable, except perhaps for e xt remely weak stations. The effect of a pure harmonic on TV reception is to create a he rringbone pattern created by a harmonic falling within the station’ s band. If the spread er is engaged the pattern will disappear unless the station is very weak, in which cas[...]

User ’ s Ma nua l 215 16. A C T IMING S PE CIFICA TIONS The Rabbit 3000 processor may be operated at voltages between 1.8 V and 3.6 V , and at temperatures from –40°C to +85°C with use possible use over the extended range -55°C to +105°C. For long life it is desirable not to ex ceed a die temperature of 125°C. Most users will operate the R[...]

216 Rabbit 3000 Micropro cessor Figure 16-1 illustrates the parameters us ed to describe memory acc ess time. Figure 16-1. Parameters Us ed to Describe Memory Access Time T able 16-2 lists the delays in gross memor y access time f or several values of V DD . When the spectrum spreader is enabled with the clock doubler , every other clock cycle is s[...]

User ’ s Ma nua l 217 Figure 16-2 and Figure 16-3 illustrate the memo ry read and writ e cycles. The Rabbit 3000 operate s at 2 clocks per bu s cyc le plus any wait states that might be specified. Figure 16 -2. Memory Rea d and Write Cycl es T adr T adr Memory Read (no wait states) CLK A[19:0] Memory Write (no extra wait states) CLK A[19:0] valid[...]

218 Rabbit 3000 Micropro cessor The following memory read time dela ys were measure d. The measurements were take n at the 50% points unde r the following conditio ns. • T = -40°C to 85°C, V = 3.3 V • Internal clock to nonloaded CLK pin delay ≤ 1 ns @ 85°C/3.0 V The following memory wr ite time delays were measured. The measurements were t[...]

User ’ s Ma nua l 219 Figure 16- 3. Memory Read and W rite Cycles —Early Output E nable and Write Enab le T iming T adr T adr Memory Read (no wait states) CLK A[19:0] Memory Write (no extra wait states) CLK A[19:0] valid T1 T2 T1 Tw T2 valid T OEx T OEx D[7:0] valid T hold T setup /CSx /OEx T CSx T CSx valid D[7:0] T DHZV T DVHZ /CSx /WEx T CSx[...]

220 Rabbit 3000 Micropro cessor Figure 16-4 illustrates the sour ces that create memory a ccess time de lays. Figure 16- 4. Sources of Memory Access Time Delays The gross memory access time is 2T , where T is the clock period. T o calculate the actual memory access time, subtract the clock t o address output time, the da ta in se tup time, and the [...]

User ’ s Ma nua l 221 The required memory output ena ble access time is more comp licated since it is af fected by the clock doubler delays. The clock doubler se t up register creates a nominal delay time ranging from 6 to 20 ns, resulting in a nominal clock low time ranging from 6 to 20 ns. The clock low time depends on internal delays, and is s[...]

222 Rabbit 3000 Micropro cessor The following factors have to be taken into account wh en cal culating the output enable access time required. • The gross output enable acc ess ti me is T + m inimum clock low tim e (i t is ass u med that the early output enable option is enabled) This is reduced by the spectrum spreader loss, the time from clock [...]

User ’ s Ma nua l 223 16.2 I/O Acc ess T ime Figure 16-6 illustrates the I/O read and write cycles. Figur e 16-6. I/O Read and Write Cycles—No E xtra Wait S tates NOTE: /IOCSx ca n be pro grammed to be act ive low (de fault) or act ive high. T adr T adr External I/O Read (no extra wait states) CLK A[15:0] External I/O Write (no extra wait state[...]

224 Rabbit 3000 Micropro cessor The following I/O read time delays were mea sured. The measurements were take n at the 50% points unde r the following conditio ns. • T = -40°C to 85°C, V = 3.3 V • Internal clock to nonloaded CLK pin delay ≤ 1 ns @ 85°C/3.0 V The following I/O write time delays were measur ed. The measurements were take n a[...]

User ’ s Ma nua l 225 16.3 Further Di sc ussion of Bu s and Clock Timing The clock doubler is normally used, except in situations where low-fre qu ency systems are specifically being used. The clock doubler works by oring the clock with a delayed ver- sion of itself. The nominal delay varies from 6 to 20 ns, and is settable under program con- tro[...]

226 Rabbit 3000 Micropro cessor Figure 16-7. Clock Doubler and Memory Timing Oscillator Oscillator de layed and invert ed Doubled clock Delay time 48% 52% P 0.48P 0.52P 0.48P 0.52P Data out Example Wri te Cycle write pulse early write pu l se option Example Read Cycle addr e s s, /CS addr e ss, / CS output enb early output enb option V alid data ou[...]

User ’ s Ma nua l 227 16.4 Max i mum Clock Speeds The Rabbit 3000 is rated for a minimum clock pe riod of 17 ns (commercial specifications) and 18 ns (industrial specifications). The comme rcial rating calls for a ±5% voltage varia- tion from 3.3 V and a temperature range from - 40 to + 70°C. The industrial ratings stretch the voltage variation[...]

228 Rabbit 3000 Micropro cessor Example The spreader and doubler a r e enabled, with 8 ns nominal delay in the doubler . The high and low clock are equal to within 1 ns. This violates the duty cycle requirement by 3 ns since (clock low - clock high) can be as sm all as -1 ns, but the requirement is that i t not be less than 2 ns. Thus, 3 ns must be[...]

User ’ s Ma nua l 229 16.5 Power and Current Consumption W ith the Rabbit 3000 it is possi ble to design systems that perform their task with very low power consumption. Unlike c om petitive proce ssors, the Rabbit 3000 has short chip select features designed to minimize power consumpt ion by external memorie s, which can easily become the domina[...]

230 Rabbit 3000 Micropro cessor Figure 16 -9. Rabbit 3000 System Current v s. Frequency at 3.3 V Figur e 16-10. Rabbit 300 0 System Curre nt vs. Frequency at 3.3 V (enlar g ed vie w over 0–16 MH z range) 0 20 40 60 80 100 120 0 1 0 2 03 04 0 5 06 0 Cl oc k F re que nc y (M H z) I (mA) x tal=25.80 x tal=14.74 x tal=11.05 xt a l = 3 . 6 8 0 5 10 15[...]

User ’ s Ma nua l 231 Lowering the ope rating voltage will grea tly re duce cur rent consump tion and powe r . Drop- ping to 2.7 V from 3.3 V will result in 70% current consumption and 60% of the power . Further dropp ing to 1.8 V will reduce cu rrent to 40% and power to 20% co mpared to 3.3 V . Naturally this complicates the selection of memorie[...]

232 Rabbit 3000 Micropro cessor 16.6 Current Consumption Mechanisms The following mechanisms contribute to the current consumption of the Rabbit 3000 while it is ope rating. 1. A current proportional to voltage and clock frequency that results from the char ging of internal and external ca pacitances. At 3.3 V (see (2) below) approximately 57% of t[...]

User ’ s Ma nua l 233 16.7 S leepy Mode Curr ent Consumption In sleepy mode the unit operates from the 32.768 kHz clock, which may be divided down to as slow as 2.048 kHz. The current consumption is given by: I total (µA) = 0.32 × V × f + 0 .23 × V c × f + 5 × V c where f is in kHz, V is the operating voltage, and V c = V × [(V/2) - 0.7]. [...]

234 Rabbit 3000 Micropro cessor 16.8 Memory Cur rent Consumption Since there are many different memories availa ble, let’ s look at an exa m ple using one of the recommended flash and SRAM memories. Flash memory —SST part SST39LF512020, 256K × 8, 45 ns access time. Standby current: ni l. • Static Current (chip select low): 3.5 mA @ 3.3 V •[...]

User ’ s Ma nua l 235 16.9 Battery-Backed Clock Current Consumption When using the suggested tiny logic oscillator , the osci llator and clock consume current as shown in Figure 16-12 below . N ormall y a resistor is placed in the battery circuit to limit the current to a b out 3 µ A, which results in a vol tage setpoint of about 1.7 V . When op[...]

236 Rabbit 3000 Micropro cessor 16.10 Reduced-Power Ext ernal Main Oscillator The circuit in Figure 16-13 can be used to ge nera te the main clock using less power than with the bui lt-in oscillator buf fer . The power c onsumption is less beca use of the c urrent- limiting resist ors that cannot be used with the built-in buf fer . The 2.2 k Ω se[...]

User ’ s Ma nua l 237 17. R ABBIT BIOS AND V IR TUAL D RIVER When a program is compiled by Dynamic C for a R abbit tar get, the V irtual D rive r is auto- matically inc orporated into the progra m. V irtual Driver is the name given to some initi al- ization routines and a group of services pe rformed by the periodic interrupt. The Rabbit BIOS, so[...]

238 Rabbit 3000 Micropro cessor 17.1.2 BIOS Assumptions The BIOS makes certain assumptions concerni ng the physical configuration of the proces- sor . Proc essors are expected to have RAM connected to /CS1, /WE1, and /OE1. Flash is expected to be connected to /CS0, /WE0, and /OE0. (See the Rabbit 3000 Designer ’ s Handbook Memory Planning chapter[...]

User ’ s Ma nua l 239 gram consistency checking or beca use a part of the program that should be executing peri- odically is not executing and the watchdog times out. The V i rtual Driver ’ s periodic interrupt hits the hardw are watchdog timer with a 2 second time-out. If the periodic interrupt stops wo rking, then t he watchdog will time out [...]

240 Rabbit 3000 Micropro cessor[...]

User ’ s Ma nua l 241 18. O THER R ABBI T S OFTW ARE 18.1 Po wer Management Support The power consumption and speed of opera tion can be throttled up and down with rough synchronism. This is done by changing the cloc k speed or the cl ock doubler . The range of control is quite wide: the speed can vary by a factor of 16 when the main clock is dri[...]

242 Rabbit 3000 Micropro cessor 18.2 Read ing and Writing I/O Re gist e rs The Rabbit has two I/O spa ces: internal I / O registers and external I/O registers. 18.2.1 Using Assembly La nguage The fastest way to read and wr i te I/O register s in Dyna m ic C is to use a short segment of assembly language inserted in the C program. Access is the same[...]

User ’ s Ma nua l 243 18.3 Shadow Registers Many of the registers of the Rabbit’ s internal I/O devices are write-onl y . This saves gates on the chip, making possible greater capability at lower cost. W rite-only registers are ea s- ier to use if a memory location, called a shadow register , is associated with each write- only register . T o m[...]

244 Rabbit 3000 Micropro cessor ld hl,PDDDRShadow ; point to shadow register ld de,PDDDR ; set de to point to I/O reg set 5,(hl) ; set bit 5 of sh adow register ; use ldd instruction for atomic trans fer ioi ldd ; (io de)<-(hl) side effect: hl--, de-- In this ca se, the ldd instruction when used with an I/O pref ix provides a convenient data mov[...]

User ’ s Ma nua l 245 T wo library functions are provi ded to read and write the real- time clock: unsigned long int read_rtc(void) ; // read bits 15-46 rtc void write_rtc(unsigned long int time) ; // write bits 15-46 // note: bits 0-14 and bit 47 are zero ed However , it is not intended tha t the real-time c lock be read and wri tten frequent ly[...]

246 Rabbit 3000 Micropro cessor[...]

User ’ s Ma nua l 247 19. R ABBI T I NSTRUC TIONS Summ ary “Load Immediate Data” on page 250 “Load & Store to Immediate Address” on page 250 “8-bit Indexed Load and Store” on page 250 “16-bit Indexed Loads and Stores” on page 250 “16-bit Load and Store 20-bit Address” on page 251 “Register to Register Moves” on page 25[...]

248 Rabbit 3000 Micropro cessor Spreadsheet Conventions AL TD (“A” Column) Symbol Key IOI and IOE (“I” Column) Symbol Key Flag Register Ke y Flag Descriptio n f AL TD selects alternate flags fr AL TD selects alternate flags and reg ister r AL TD selects alternate register s AL TD operation is a special case Flag Descript ion b IOI and IOE a[...]

User ’ s Ma nua l 249 Symbol s Rabbit Z180 Mean ing b b Bit select: 000 = bit 0 , 00 1 = bit 1, 010 = bit 2 , 01 1 = bit 3, 100 = bit 4 , 10 1 = bit 5, 1 10 = bit 6, 1 1 1 = bit 7 cc cc Condition code select: 00 = NZ, 01 = Z, 10 = NC, 1 1 = C d d 7-bit (signed) displacement. Expr essed in two’ s complement. dd ww W ord register s elect destinat[...]

250 Rabbit 3000 Micropro cessor 19.1 Load Immediate Dat a Instruction clk A I S Z V C Oper ation LD IX,mn 8 - - - - IX = mn LD IY,mn 8 - - - - IY = mn LD dd,mn 6 r - - - - dd = mn LD r,n 4 r - - - - r = n 19.2 Load & Store to I m mediate Address Instruction clk A I S Z V C Oper ation LD (mn),A 10 d - - - - (mn) = A LD A,(mn) 9 r s - - - - A = ([...]

User ’ s Ma nua l 251 19.5 16-bit Load and S to r e 20-bit Address Instruction clk A I S Z V C Oper ation LDP (HL),HL 12 - - - - (HL) = L; (HL+1) = H. (Adr [19:16] = A[3:0]) LDP (IX),HL 12 - - - - (IX) = L; (IX+1) = H. (Adr [19:16] = A[3:0]) LDP (IY),HL 12 - - - - (IY) = L; (IY+1) = H. (Adr [19:16] = A[3:0]) LDP HL,(HL) 10 - - - - L = (HL); H = ([...]

252 Rabbit 3000 Micropro cessor 19.7 E xchange Instr uctions Instruction clk A I S Z V C Oper ation EX (SP),HL 15 r - - - - H <- > (SP+1); L <-> (SP) EX (SP),IX 15 - - - - IXH <-> (SP+1); IXL <-> (SP) EX (SP),IY 15 - - - - IYH < -> (SP+1); IYL <-> (SP) EX AF,AF’ 2 - - - - AF < -> AF’ EX DE’,HL 2 s - -[...]

User ’ s Ma nua l 253 ADD IY,yy 4 f - - - * IY = IY + yy -- yy=BC, DE, IY, SP ADD SP,d 4 f - - - * SP = SP + d -- d=0 to 255 AND HL,DE 2 fr * * L 0 HL = HL & DE AND IX,DE 4 f * * L 0 IX = IX & DE AND IY,DE 4 f * * L 0 IY = IY & DE BOOL HL 2 fr * * 0 0 if ( HL != 0) HL = 1, set flags to match HL BOOL IX 4 f * * 0 0 if ( IX != 0) IX = 1[...]

254 Rabbit 3000 Micropro cessor CP* n 4 f * * V * A - n CP* r 2 f * * V * A - r OR (HL) 5 fr s * * L 0 A = A | (HL) OR (IX+d) 9 fr s * * L 0 A = A | (IX+d) OR (IY+d) 9 fr s * * L 0 A = A | (IY+d) OR n 4 fr * * L 0 A = A | n OR r 2 fr * * L 0 A = A | r SBC* (IX+d) 9 fr s * * V * A = A - (IX+d) - CY SBC* (IY+d) 9 fr s * * V * A = A - (IY+d) - CY SBC*[...]

User ’ s Ma nua l 255 19.13 8-bit Fast A Register Operations Instruction clk A I S Z V C Oper ation CPL 2 r - - - - A = ~A NEG 4 fr * * V * A = 0 - A RLA 2 fr - - - * {CY, A} = {A,CY} RLCA 2 fr - - - * A = {A[6,0],A[7]}; CY = A[7] RRA 2 fr - - - * {A,C Y} = {CY,A} RRCA 2 fr - - - * A = {A[0],A[7,1]}; CY = A[0] 19.14 8-bit Shift s and Rot ates Ins[...]

256 Rabbit 3000 Micropro cessor SLA r 4 fr * * L * r = {r[6,0],0}; CY = r[7] SRA (HL) 10 f b * * L * (HL) = {(HL)[7],(HL)[7,1]}; CY = (HL)[0] SRA (IX+d) 13 f b * * L * (IX+ d) = {(IX+d)[7], (IX+ d)[7,1]}; CY = (IX+d)[0] SRA (IY+d) 13 f b * * L * (IY+ d) = {(IY+d)[7], (IY+ d)[7,1]}; CY = (IY+d)[0] SRA r 4 fr * * L * r = {r[7],r[7,1]}; CY = r[0] SRL [...]

User ’ s Ma nua l 257 19.17 Control Instructi ons - Jump s and Cal ls Instruction clk A I S Z V C Oper ation CALL mn 12 - - - - (SP- 1) = PCH; (SP-2) = PCL; PC = mn; SP = SP-2 DJNZ j 5 r - - - - B = B-1; if {B != 0} PC = PC + j JP (HL) 4 - - - - PC = HL JP (IX) 6 - - - - PC = IX JP (IY) 6 - - - - PC = IY JP f,mn 7 - - - - if { f} PC = mn JP mn 7 [...]

258 Rabbit 3000 Micropro cessor 19.19 Privi leged Instructi ons The privileged instructions are described in th is section. Privilege means that an interrupt cannot take place between the privileged instruction and the following instruction. The three instruc tions below ar e privileged. LD SP,HL ; load the stack pointer LD SP,IY LD SP,IX The instr[...]

User ’ s Ma nua l 259 20. D IFFE RENCES R ABBIT VS . Z80/Z180 I NSTR UCTIO NS The Rabbit is highly code compatible with th e Z80 and Z180, and it is easy to port non I/O dependent code . The main areas o f i ncompatibility are instructions that ar e concerned with I/O or particular hardware implementations. The more important instructions that we[...]

260 Rabbit 3000 Micropro cessor The following instructions use dif ferent register names. LD A,EIR LD EIR,A ; was R register LD IIR,A LD A,IIR ; was I register The following Z80/Z180 instructions have been dropped and are not supported. Alterna- tive Rabbit instructions are provided. Z80/Z180 Instruc tions Dropped Rabbit Instructions to Use CALL CC[...]

User ’ s Ma nua l 261 21. I NSTRUCTIONS IN A LPHABETICAL O RDER W ITH B INARY E NCODING Spreadsheet Conventions AL TD (“A” Column) Symbol Key Flag De scription f AL TD sele ct s alternate flag s fr AL TD sel ects alternate flags and regist er r AL TD sele ct s alternate reg i st er s AL TD operati on is a special case IOI and IOE (“I” Col[...]

262 Rabbit 3000 Micropro cessor Symbol s Rabbit Z180 M eaning bb Bit s elect: 000 = bit 0, 001 = bit 1, 010 = bit 2, 01 1 = bit 3, 100 = bit 4, 101 = bit 5, 1 10 = bit 6, 1 1 1 = bit 7 cc cc Condition c ode select: 00 = NZ, 01 = Z, 10 = NC, 11 = C dd 7-bit (s igned) di splacement. Expres sed in two’ s complement . dd ww W ord reg ister sele ct de[...]

User ’ s Ma nua l 263 Instruction Byte 1 Byte 2 Byte 3 Byte 4 clk A I S Z V C ADC A,(HL) 10001110 5 fr s * * V * ADC A,(IX+d) 11011101 10001110 ----d--- 9 fr s * * V * ADC A,(IY+d) 11111101 10001110 ----d--- 9 fr s * * V * ADC A,n 11001110 ----n--- 4 fr * * V * ADC A,r 10001-r- 2 fr * * V * ADC HL,ss 11101101 01ss1010 4 fr * * V * ADD A,(HL) 1000[...]

264 Rabbit 3000 Micropro cessor EX AF,AF' 00001000 2 - - - - EX DE,HL 11101011 2 s - - - - EX DE',HL 11100011 2 s - - - - EX DE,HL' 01110110 11100011 4 s - - - - EX DE',HL' 01110110 11100011 4 s - - - - EXX 11011001 2 - - - - INC (HL) 00110100 8 f b * * V - INC (IX+d) 11011101 00110100 ----d--- 12 f b * * V - INC (IY+d) 111[...]

User ’ s Ma nua l 265 LD A,(BC) 00001010 6 r s - - - - LD A,(DE) 00011010 6 r s - - - - LD A,(mn) 00111010 ----n--- ----m--- 9 r s - - - - LD A,EIR 11101101 01010111 4 fr * * - - LD A,IIR 11101101 01011111 4 fr * * - - LD A,XPC 11101101 01110111 4 r - - - - LD dd,(mn) 11101101 01dd1011 ----n--- ----m--- 13 r s - - - - LD dd',BC 11101101 01dd[...]

266 Rabbit 3000 Micropro cessor LDP HL,(HL) 11101101 01101100 10 - - - - LDP HL,(IX) 11011101 01101100 10 - - - - LDP HL,(IY) 11111101 01101100 10 - - - - LDP HL,(mn) 11101101 01101101 ----n--- ----m--- 13 - - - - LDP IX,(mn) 11011101 01101101 ----n--- ----m--- 13 - - - - LDP IY,(mn) 11111101 01101101 ----n--- ----m--- 13 - - - - LJP nbr,mn 1100011[...]

User ’ s Ma nua l 267 RR r 11001011 00011-r- 4 fr * * L * RRA 00011111 2 fr - - - * RRC (HL) 11001011 00001110 10 f b * * L * RRC (IX+d) 11011101 11001011 ----d--- 00001110 13 f b * * L * RRC (IY+d) 11111101 11001011 ----d--- 00001110 13 f b * * L * RRC r 11001011 00001-r- 4 fr * * L * RRCA 00001111 2 fr - - - * RST v 11-v-111 [v=2,3,4,5,7 only] [...]

268 Rabbit 3000 Micropro cessor[...]

User ’ s Ma nua l 269 A PPENDI X A. T HE R ABBIT P ROGRAMMING P ORT The programming port provides a standard phys ical and electrical interf ace between a Rabbit-based system and the Dynamic C progr amming platform. A specia l interface cable and converter connects a PC serial port to the programming port. The programming port is implemented by m[...]

270 Rabbit 3000 Micropro cessor A.1 Use of the Programming Port as a Diagnostic/Setup Port The programming port, which is already in place, ca n serve as a convenient communica- tions port for field setup, diagnosis o r other occasional communication need (for example, as a diagnostic port). There are sever al ways th at the port c an be automatic [...]

User ’ s Ma nua l 271 an asynchronous signal suitable for the PC. Since the tar get controls the clock for both send and receive, the data tr ansmi ssion proceeds at a rate controlled by the target board under development. This scheme does not allow for an interrupt, and it is not desirable to use up an external interrupt for this purpose. The se[...]

272 Rabbit 3000 Micropro cessor T able A-1. Preliminary Crystal Fre quencies, Memory Access Times, and Baud Rates Crystal Frequency (MHz) Doubled Frequency (MH z) Doubled Period (ns) Access Time (ns) Divis or for 1 15,200 b aud 1.843 2 3.6864 271 522 4 3.686 4 7.3728 136 257 8 7.372 8 14.745 6 68 124 16 9.216 18 .432 54 97 20 1 1.0592 22.1 184 45 7[...]

User ’ s Ma nua l 273 A PPENDIX B. R ABBIT 3000 R EVIS IONS Since its release, the Rabbit 3000 microprocessor ha s gone thro ugh one revision. The r e vi- sion reflects bug fixes, improvements, and the introduction of new features. All Rabbit 3000 revisions are pin-compatible, and transparen tly replace pr evious versions of the chip. The Rabbit [...]

274 Rabbit 3000 Micropro cessor 2. First revisi on (Rabbit 3000A) —A vailable in two packa ges and identified by IL2T for the LQFP package and IZ2T for the TFBGA package. This version began shipping in August 2003. All the bugs in the original Rabbit 3000 were fixed. The Rabbit 3000A contains a number of new features a nd i mprovements. (a) A new[...]

User ’ s Ma nua l 275 (l) The quadrature decoder hardware can be configured to use a 10-bit counter in place of the existing 8-bit counter . (m) An option was added to a lt e rnatively multi plex P W M out puts, slave chip select (/SCS), and Serial Ports E and F trans mit and receive clocks on other pins. (n) The Schmitt trigger IC normally requi[...]

276 Rabbit 3000 Micropro cessor B.1 Discussion of Fixes and Improvement s T able B-1 lists t he bug fixes, improvements, a nd additions for the various revisions of the Rabbit 3000. T able B-1. Summary of Rabbit 3000 Improvements and Fixes Desc ription Rabbit 3000 (IL1 T/IZ1 T) Rabbit 3000A (IL2T/IZ2T) ID Registers for version/revisi on identificat[...]

User ’ s Ma nua l 277 B.1.1 Rabbit Internal I/O Regi sters T able B-2 summarizes the reset state of the new I/O register s a dded in the Rabbit 3 000A revision. T able B-3 summarizes the reset state of the exist ing I/O re gi sters with new features. T able B-2. Res et State of New Rabbit 3000A I/O Register s Register N ame Mnemonic I/O Address R[...]

278 Rabbit 3000 Micropro cessor External Interru pt User Enable Register IUER 0x0398 W 00000 000 T imer A User Enable Register T AUER 0x03A0 W 00000 000 T imer B User Enable Register TBU ER 0x03B0 W 00 000000 Serial Port A User Enable Register SAUER 0x03C0 W 00000 000 Serial Port B User Enable Register SBUE R 0x 03D0 W 00000000 Serial Port C User E[...]

User ’ s Ma nua l 279 T able B-3. Reset S tate of I/O Registers Modif ied in Rabbi t 3000A Register N ame Mne monic I/O Address R/W Rabbit 3000 Reset Rabbit 3000A Rese t Global Power Sa ve Control Register GPSCR 0x000D W 00 00x000 000000 00 Global Revis ion Regi s t er GREV 0x002 F R 0x x00000 0xx00001 MMU Expanded C ode Regis ter MECR 0x0018 R/W[...]

280 Rabbit 3000 Micropro cessor B.1.2 Pe ripheral and ISR Addres s T able B-4. Rabbit 3000 I/O Address Ranges and Interrupt Servi ce V ectors On-Chip Periphe ral I/O Address Range ISR St arting Address System Man agement 0x0000– 0x000F {R[7:1], 0 , 0x00} Memory Management 0x0010–0x00 1F and 0x0400–0x 04FF No interrupts Slave Port 0x0020– 0x[...]

User ’ s Ma nua l 281 SYSCALL in struct ion n/a {IIR[7: 1], 0, 0x60} RST 38 instruction n/a {IIR[7:1 ], 0, 0x70} Secondary W atchd og 0x000C {IIR[ 7:1], 0, 0x10} Stack Limit V iolation n/a {IIR[7:1], 1, 0xB0} W rite Pro tection V iolation n/a {IIR[7:1] , 0, 0x9 0} System Mo de V iolati on n/a {IIR[7:1] , 1, 0x8 0} T able B-4. Rabbit 3000 I/O Addr[...]

282 Rabbit 3000 Micropro cessor B.1.3 Revisio n-Level I D Regist er T wo read-only re gi sters are provided to allow software to identify the Rabbit micropr oces- sor and recognize the fea tures and capabiliti es of the chip. Five bits in each of these regis- ters are unique to each ver si on of the chi p. One register identifies the CPU (GCPU), an[...]

User ’ s Ma nua l 283 B.1.4 System/Us er Mode By default, all of the hardware is accessibl e by the progra mm er . However , if a c ont rol bit in the Enable Dual Mode Register (EDMR) is set to one, two operating modes, System and User , become available. The System m ode is just li ke the normal operating mode, but the User mode restricts progra[...]

284 Rabbit 3000 Micropro cessor B.1.5 Memory Protection The ability to inhibit writ es to physical memory was added. The sixteen 64 KB physical memory blocks can be individually protected, and two of those blocks can additionally be subdivided and protected at a granularity of 4 KB. When a write is attempted, a ne w Priority 3 write-protection inte[...]

User ’ s Ma nua l 285 T able B-7. W rite Protect Low Regist er Write Prote ct Low Regist er (WP LR) (Address = 0x04 60) Bit(s) Va l u e Desc ription 7 0 Disable 64K write-pro tect for phy sical address 0x70000–0 x7 FF FF . 1 Enable 64K write-pr otect for physical ad dress 0x7 0000– 0x7FFFF . 6 0 Disable 64K write-pro tect for phy sical addres[...]

286 Rabbit 3000 Micropro cessor T able B-8. W rite Protect Hi gh Regist er Write Protec t High Regist er (W PHR) (Ad dress = 0x0461) Bit(s) Va l u e Desc ription 7 0 Disable 64K write-pro tect for phy sical address 0xF0000–0x FF F FF . 1 Enable 64K write-pr otect for physical ad dress 0xF 0000–0x FFFFF . 6 0 Disable 64K write-pro t ect for phys[...]

User ’ s Ma nua l 287 T able B- 10. Write Prot ect Segment x Low Register Write Protec t Segment x Low Register ( W PSA LR) (Addr ess = 0 x0481) (WPSB LR) (Address = 0x04 85) Bit(s) Va l u e Desc ription 7 0 Disable 4K wri te-protect for addres s of fset 0x7000–0x7F FF in WP S egment x 1 Enable 4K wr ite-protect f o r address of fset 0x700 0–[...]

288 Rabbit 3000 Micropro cessor T able B-1 1. W rite Pr otect Segment x High Regi ster Write Protect Segment x High Register (W PSAHR) (Address = 0x0482) (WPSBHR) (Address = 0 x0486) Bit (s) Va l u e De scription 7 0 Disable 4K write -protect fo r address offset 0xF00 0–0xFF FF in WP Seg ment x 1 Enable 4K write -protect f or address of fset 0xF0[...]

User ’ s Ma nua l 289 B.1.6 St ac k Protect io n St ack overflow and underflow ca n now be dete cted. Low and high stack l imits can be s et on 256-byte boundaries. When a stack-relative memory a ccess occurs within 16 bytes of these limits (or outside of them), a new Priority 3 stack violation interrupt occurs. The 16- byte buf fer exists to all[...]

290 Rabbit 3000 Micropro cessor The stack protection registers are listed in T able B-12, T a bl e B-13, and T able B-14. T able B-12. S tack Limit Contr ol Register St ack Limit Control Regist er (STKCR) (Address = 0 x0444) Bit(s) Va l u e Desc ription 7:1 These bits are reserved and should be written with zeros. 0 0 Disable stack-limit checking. [...]

User ’ s Ma nua l 291 B.1.7 RAM Segment Relocation Normally when instruction/da ta separation is enabled, instructions are stored in flash memory and data ar e stored in RAM me mory . This can present a problem for the Interrupt Service Routine area, which often re qui res run-time modification. The RAM Segment Register (RAMSR) allows a 1, 2, or [...]

292 Rabbit 3000 Micropro cessor B.1.8 Se condary W atchdog T imer The secondary watchdog timer (SWDT) is an eight-bit modulo n + 1 counter clocked by the 32.768 kHz clock. The timer is off by default, and is enabled by writing a 0x5F to the WDTCR. The secondary watchdog timer register (SW D TR) holds the time constant value. Depending on the value [...]

User ’ s Ma nua l 293 B.1.9 New Opcodes Eight new opcodes were added to the Ra bbit 3000A. UMA and UMS allow multiply-and- add and multiply-a nd-subtract oper ations on lar ge integer s, and were added to speed up common cryptographic math used in public-k ey calculations. The remaining six expand the block copy operations available, especia l ly[...]

294 Rabbit 3000 Micropro cessor B.1.9.2 New Block Copy Opcodes The LDxR family of block move opcodes ha s been expanded. In the Rabbit 3000 proces- sor , block copy operations could only be done between memory a dd r esses, or from mem- ory to an I/O address. In addition, the de stination I/O address would increment (or decrement if using LDDR) aft[...]

User ’ s Ma nua l 295 B.1.10 Exp anded I/O Memory Addre ssing In the Rabbit 3000, only the lower 8 bits of an I/ O address were decoded. T o provide room for new peripherals, this was expanded to 16 bits. T o ensure backwards compatibility , the processor always comes up in 8-bit I/O addr ess mode; the 16-bit I/ O address mode needs to be enabled[...]

296 Rabbit 3000 Micropro cessor B.1.1 1 Exte rnal I/O Improve ment s Three new feature s have been added to the exte rnal I/O strobes: the ability to invert the strobe signal, the ability to shor ten a read st robe by one clock, a nd the ability t o direct a strobe to either the alternate I/O bus (if ena bl ed) or the memory bus. The new control bi[...]

User ’ s Ma nua l 297 B.1.12 S hort Chip Sel ect T iming for Writ es The Rabbit 3000 provided the ability to produce shor ter chip select strobes for reads when in a reduced-speed mode. A ne w feature has been added to produce short chip select strobes for writes as well, and can be controlled by the GPCSR register . The new control bit for the s[...]

298 Rabbit 3000 Micropro cessor B.1.12.1 Clock Select an d Power Save M odes T able B-24 outlines the power save modes available in the Rabbit 3000A. The GCSR is shown in T able B-23 for reference. T able B-23. Global Control /S tatus Regi ster Global Control/St atus Reg ister (GCSR) (Addre ss = 0x00) Bit (s) Va l u e Description 7:6 (rd-only) 00 N[...]

User ’ s Ma nua l 299 B.1.12.2 Sh ort Chip Select T iming When short chip se lects are enabl e d for read cy c l es, the chip select signals are active only for the las t part of the bus cycl e. W ait state s are inserted betwe en T1 and T2, so this will have no effect on the duration of t he chip sele ct signals in this mode. The timing diagra m[...]

300 Rabbit 3000 Micropro cessor Figure B-4. Short Chip Se lect T iming: CLK/6, Read Operation Figure B-5. Short Chip Se lect T iming: CLK/4, Read Operation o s c illa t o r ADD R DAT A T1 T2 Va lid /O E x /C S x cl o ck di vi d e - b y -6 mo de o s c illa t o r ADD R DAT A T1 T2 Va l i d /O E x /CS x cl ock di vid e -b y -4 m o d e[...]

User ’ s Ma nua l 301 Figure B-6. Short Chip Se lect T i ming: CLK/2, Read Ope ration osci l l ato r ADD R DAT A T1 T2 V alid /O Ex /CSx cl ock di vid e -b y- 2 m o d e[...]

302 Rabbit 3000 Micropro cessor When opera ting fro m the 32 kHz oscillator , the same opti ons are available, b ut the timing is somewha t diff erent. This is illustrat ed in the diagrams bel ow for the f our dif ferent ca ses. In these case the chip selects are one c lock cycle (of the 32 kHz clock) long. Figure B-7. Short Chip Select Timing: 2 k[...]

User ’ s Ma nua l 303 Figure B-9. Short Chip Select Timing: 8 kHz, Read O peration Figure B- 10. Short Chip Sele ct T iming: 16 kH z, Read Operat ion 32 kHz ADD R DAT A T1 T2 V alid /O Ex /CSx cl ock 8 k H z o p er a t i on 32 kH z ADD R DAT A T1 T2 V alid /O Ex /CSx cl ock 16 kHz op e rati o n[...]

304 Rabbit 3000 Micropro cessor Figure B-1 1. S hort Chip Select Timing: 32 kHz, R ead Operation 32 kH z ADD R DAT A T1 T2 V alid /O Ex /CSx cl ock 32 kHz op e rati o n[...]

User ’ s Ma nua l 305 In the case of write cycles, the chip selec t signals ar e active only around the trailing edge of the write s ignal. W ait s tates are i nserted between T1 a nd T2, and this will have no ef fect on the duration of the chip sel ect signals in this mode . The timing diagra ms below illus- trate the a ctual timi ng for the dif[...]

306 Rabbit 3000 Micropro cessor Figure B- 13. Short Chip Select Timing: CLK/6, Write O peration Figure B- 14. Short Chip Select Timing: CLK/4, Write O peration osc i llato r ADD R DAT A T1 TWA V a lid /W E x /C S x cl oc k divi d e - b y -6 m o d e T2 o s c illa t o r ADD R DAT A T1 TW A Valid /W E x /C S x cl ock di vi d e -b y -4 mo d e T2[...]

User ’ s Ma nua l 307 Figure B- 15. Short Chip Select Timing: CLK/2, Write Op eration o s cilla t o r ADD R DAT A T1 TW A V alid /W Ex /C Sx cl ock di v id e -b y -2 m o d e T2[...]

308 Rabbit 3000 Micropro cessor The timing diagra ms below illustr ate the actual t iming for the 32KHz c ases of write cycles. In these c ases the chip select s are ac tive for one clock cycle before and one cl ock cycl e after the trailing e dge of t he write signal. Figure B-16. Short Chip Selec t Timing: 2 kHz, Write Operation Figure B-17. Shor[...]

User ’ s Ma nua l 309 Figure B-18. Short Chip Select T iming: 8 kHz , W rite O p eration Figure B-19. S ho rt Chip Selec t Timing: 16 kHz, Write Operation 32 kHz ADD R DAT A T1 TW A V alid /W Ex /C Sx cl ock 8 kH z op e r atio n T2 32 kHz ADD R DAT A T1 TW A V alid /W Ex /C Sx cl ock 16 kHz op e r at io n T2[...]

310 Rabbit 3000 Micropro cessor Figure B-20. Short Chip Se lect Timing: 32 kHz, Write Operation 32 kHz ADD R DAT A T1 TW A V alid /W Ex /C Sx cl ock 32 kHz op e r at io n T2[...]

User ’ s Ma nua l 31 1 B.1.13 Pulse Wid th Modulator Improvement s Several new features ha ve been added to the pulse width modul ator . First, a new PWM interrupt can be set up to be requested on eve r y PWM cycle, every other cyc le, every fourth cycle, or every eighth cyc l e. The set up for this interrupt is done in the PWL0R and PWL1R regist[...]

312 Rabbit 3000 Micropro cessor T able B-25. PWM LSB 0 Register PWM LSB 0 Register (PWL0R) (Addr ess = 0x00 88) Bit(s) Va l u e Desc ription 7:6 write The least significant two b its fo r th e Pulse W idth Modulator cou nt are stored. 5:4 00 Normal PWM operati on. 01 Suppress PWM outp ut seven out of eigh t iterat ions of PW M counter . 10 Suppress[...]

User ’ s Ma nua l 313 T able B-27. PWM LSB 2 and 3 Registers PWM LSB x Register (PWL2R) (Address = 0x008C) (PWL3R) (Address = 0x008E) Bit(s) Va l u e Desc ription 7:6 write The least significant two b its fo r th e Pulse W idth Modulator cou nt are stored. 5:4 00 Normal PWM operati on. 01 Suppress PWM outp ut seven out of eigh t iterat ions of PW[...]

314 Rabbit 3000 Micropro cessor B.1.14 Quad rature Decoder Improv ement s The quadrature decoder c ounters can now be expa nded to 10 bi ts instead of 8 bits. This is controlled by bit 5 in QDCR, listed in Table B -28. The additional two bits can be read in the QDCxHR registers, listed in Table B-29. NOTE: Bit 5 of QDCR was al ways wri tt en wit h [...]

User ’ s Ma nua l 315 Figure B-22. Quadrature Decode, 8-bit and 10-bit Counter T iming Cn t (8 b i t) In te r rup t I i n pu t Q inpu t 00 01 02 03 04 05 06 07 08 07 06 05 04 03 02 01 00 FF FF Cn t (1 0 b i t) 000 001 002 003 004 005 006 00 7 008 007 006 005 004 003 002 001 000 3FF 3FF[...]

316 Rabbit 3000 Micropro cessor B.2 Pins wi th Alternate Functions The Rabbit 3000A provides greater flexibility for multipl exing I/O functions to other pins. The following alternate connections were introduc ed in the Rabbit 3 000A for these peripherals, and are indicated by an aster i sk in T able 5- 2. • Slave por t CS /ASCS: Alternate slave [...]

User ’ s Ma nua l 317 A PPEND IX C. S YSTEM /U SER M ODE The Rabbit 3000A is the first Rabbit microproce s s or to incorpora te a “system/user mode.” The purpose of the System/User mode is to provide two tiers of control in the CPU: sys- tem , which provides full access to all processor resources; and user , a mo re restricted mode. T able C-[...]

318 Rabbit 3000 Micropro cessor C.1 Sys tem/User Mode Opcodes Seven new opcodes have been added to suppor t the System/User mode, and are listed in T able C-2. All but IDET are placed in previously empty opcode table assignments. IDET shares the value of LD E,E in the opcode table, and will pe rform that operation when the System/User mode is di sa[...]

User ’ s Ma nua l 319 C.2 Syst em/User Mode Registers T able C-3 lists the new I/O registers added to support the Syst em/User mode. The Enable Dual Mode Register (EDMR) is used to enable and disable the System/User mode. All other I /O registers li sted in the ta ble are “User mode enabl e” registers for each peripheral. On startup, U s er m[...]

320 Rabbit 3000 Micropro cessor The I/O banks on Port E (enabled for the User mode by IBUER) have a slightly dif ferent operation in the User mode. Disabling user access to a given I/O bank not only causes writes to the corresponding IBxCR register to be ignored in the User mode, but also inhib- its the strobe associated with that I/O bank. Access [...]

User ’ s Ma nua l 321 C.3 Interrup ts When enabled fo r User mode access, a periphera l interrupt (if it is capable of generating an interrupt) can only be requested at Interr upt Priority Level -2 or - 1. Interrupts (and RST s and SYSCALL ) all enter the Sys tem mode automatical ly . There will be time s, however , that an interrupt should be ha[...]

322 Rabbit 3000 Micropro cessor C.3.1 Pe ripheral Inter rupt Prioritiza tion Most interrupts can be programmed to occur at any of t hree priority levels, but several are restricted to Level 3 (t he highest priority) onl y . The interrupts restrict ed to Level 3 are sys- tem mode violation, stack limit violation, wr ite protection violati on, and th[...]

User ’ s Ma nua l 323 T able C-5. Int errupts—Priori ty and Actio n to Clear Requests Prior i t y Interrupt Source Action required t o clear the int errupt Highest System Mode V iolation Automatically cleared by the interr upt acknowledge. Stack Limit V iolation Automatically cleared by the interrupt acknowled ge. W rite Protection V iolation A[...]

324 Rabbit 3000 Micropro cessor C.4 Using the System/User Mode The System/User mode is designed to work with new features in the Rabbit 3000A (memory protection, stack protection, etc.) to provide a seamless framework for protec t ion of critical code. How e ver , there a re many le vels at which the Syst em/User mode can be used; some examples are[...]

User ’ s Ma nua l 325 C.4.2 Mixed Syst em/User Mode Operation This mode is sim ilar to the previous mode, but with some portions of the progra m written for the System mode—for example, periphera l interrupts where lat ency is critical. By keeping the System mode c ode sections small, potential syst em cras hes are still mini- mized. An overvie[...]

326 Rabbit 3000 Micropro cessor C.4.3 Complete Operati ng System This section describes a “full” use of the System/User mode—separa ting all comm on functions into a S ystem mode “ operating system” while letting the application-spe cific code run in the User mode.By default, the Sy stem mode handles all peripherals and inter- rupts, as w[...]

User ’ s Ma nua l 327 A PPENDI X D. R ABBI T 3000A I NTERN AL I/O R EGISTERS T able D-1 provides a list of all the Rabbit 3000A internal I/O registers. T able D-1. Rabbit 3000A Internal I/O Registers Register Name Mnemonic I/O A d dress R/W Reset Global Cont rol/S tatus Register GCSR 0x0000 R/W 1 1000000 Real T ime Clock Con trol Re gister R TCCR[...]

328 Rabbit 3000 Micropro cessor Memory Bank 0 Control Regis ter MB0CR 0x0014 W 00001000 Memory Bank 1 Control Regis ter MB1CR 0x0015 W xxxxxxxx Memory Bank 2 Control Regis ter MB2CR 0x0016 W xxxxxxxx Memory Bank 3 Control Regis ter MB3CR 0x0017 W xxxxxxxx MMU Expanded Code Regist er MECR 0x0018 R/W 00000000 Memory T iming Cont rol Regi ster MTCR 0x[...]

User ’ s Ma nua l 329 I/O Bank Us er Enable Reg ister IBUER 0x0380 W 00000000 PWM User Enable Regist er PWUER 0x0388 W 00000000 Quad Decode Us er Enable Reg ister QDUER 0x0390 W 00000000 External Interrupt User En able Regi ster IUE R 0x0398 W 00000000 T i mer A User Enable Register T AUER 0x03 A0 W 00000000 T i mer B User Enable R egist er TBUER[...]

330 Rabbit 3000 Micropro cessor Port D Bi t 2 Reg i s ter PDB2R 0x006A W xxxxxxxx Port D Bi t 3 Reg i s ter PDB3R 0x006 B W xxxxxxxx Port D Bi t 4 Reg i s ter PDB4R 0x006 C W xxxxxxxx Port D Bi t 5 Reg i s ter PDB5R 0x006D W xxxxxxxx Port D Bi t 6 Reg i s ter PDB6R 0x006E W xxxxxxxx Port D Bi t 7 Reg i s ter PDB7R 0x006F W xxxxxxxx Port E Da ta Reg[...]

User ’ s Ma nua l 331 I/O Bank 2 Control Register IB2C R 0x008 2 W 00000000 I/O Bank 3 Control Register IB3C R 0x008 3 W 00000000 I/O Bank 4 Control Register IB4C R 0x008 4 W 00000000 I/O Bank 5 Control Register IB5C R 0x008 5 W 00000000 I/O Bank 6 Control Register IB6C R 0x008 6 W 00000000 I/O Bank 7 Control Register IB7C R 0x008 7 W 00000000 PW[...]

332 Rabbit 3000 Micropro cessor Interrupt 0 Co ntrol Re gister I0CR 0x0098 W xx000000 Interrupt 1 Co ntrol Re gister I1CR 0x0099 W xx000000 T i mer A Control /S tatus Regi ster T ACSR 0x00A0 R/W 00000000 T i m er A Prescal e Register T APR 0x00A1 W xxxxxxx1 T i mer A T ime Con stant 1 Register T A T1R 0x00A3 W xxxxxxxx T i mer A Control Register T [...]

User ’ s Ma nua l 333 Serial Por t B Ad dress Regis ter SBAR 0x00D 1 W xxxxxxxx Serial Por t B Long St op Regis ter SBLR 0x00D2 W xxxxxxxx Serial Por t B S tatus Registe r SBS R 0x00D3 R 0xx000 00 Serial Por t B Control Reg ister SBCR 0x00 D4 W xx000000 Serial Por t B Ext ended Reg ister SBER 0x00 D5 W 00000000 Serial Por t C Data Regis ter SCDR [...]

334 Rabbit 3000 Micropro cessor[...]

User ’ s Ma nua l 335 N OTIC E TO U SE RS RABBIT SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR US E AS CRITICAL COM- PONENTS IN LIFE-SUPPOR T DEVICES OR SYSTEMS UNLESS A SPECIF IC WRITTEN AGREE- MENT REGARDING SUCH INTENDED USE IS ENTERED INTO BE TWEEN THE CUSTOMER AND RABBIT SEMICONDUCTOR PRIOR TO USE. Life-support devices or systems are devices[...]

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User ’ s Ma nua l 337 I NDEX Numerics 5 V tolerant inputs ................ 11 A assembly language instructions ...... 40, 41, 42, 4 3 reading/writing to I /O regis- ters ...................... ........ 242 asynchro nous I/O .................. 50 B BGA package mechanical dimensions ..... 60 outline .......... ........... .......... 61 bootstrap o [...]

338 Rabbit 3000 Micropro cessor M memory A16, A19 inversions (/ CS1 enable) ........ ............ ..... 121 access time .................. ..... 215 access time delays ........... 220 access times with clock double r ............. ........... 221 allocation of extend ed code and data spa ce ............. 123 breakpoint/debug co ntrol- ler .........[...]

User ’ s Ma nua l 339 PDDDR ............. ............ .. 133 PDDR ................ ...... 133, 135 PDFR ................ .............. 133 PEBxR ......... ................... 138 PECR ........... ........... 138, 139 PEDDR ............. .............. 138 PEDR ................ ...... 138, 139 PEFR ................. .............. 138 PFCR .....[...]

340 Rabbit 3000 Micropro cessor S seco nd ary wat chdog ti m er .. 2 92 serial ports ..................... 11, 161 9th bit protoco ls ............... 196 address registers .............. 168 baud rates ... ........... ........... 163 breaks .. ................. ........... 194 clocked se rial ports (Ports A – D) ............... ................. [...]