Lucent Technologies MN102H75K инструкция обслуживания

MICR OCOMPUTER MN102H MN102H75K/F75K/85K/F85K LSI User’ s Manual Pub .No .22385-011E[...]

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PanaXSerie s is a t rademark o f Matsushita Elect ric Industr ial Co., L td. The other corporat ion names, logotyp e and product names written in this book are trademark s or registe red trademarks of their corresp ondin g corp oratio ns. Request fo r your spec ial attent ion and precau tions in us ing the tech nical informat ion and sem iconduct o[...]

Contents MN102H75 K/F75K LSI Use r Manual Panasonic Semiconductor Develo pment Company 3 Panas onic Contents About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Using This Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

Contents Panasonic Semicond uctor Dev elopment Com pany MN102H75 K/F75K LSI User Manual 4 Panas onic 4.5.1 Setting Up an Ev ent Counter Using T imer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.5.2 Setting Up an Interv al T imer Using T imers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

Contents MN102H75 K/F75K LSI Use r Manual Panasonic Semiconductor Develo pment Company 5 Panas onic 6.4.2 Single Channel/Single Co n version T iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6.4.3 Multiple Channel/Single Con v ersi on T iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

Contents Panasonic Semicond uctor Dev elopment Com pany MN102H75 K/F75K LSI User Manual 6 Panas onic 7.13.3 Controlling Shutter ing Ef fects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 7.13.4 Controlling Line Sh uttering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

Contents MN102H75 K/F75K LSI Use r Manual Panasonic Semiconductor Develo pment Company 7 Panas onic 11 I/O P or t s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 11.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

Contents Panasonic Semicond uctor Dev elopment Com pany MN102H75 K/F75K LSI User Manual 8 Panas onic B.4.2 Circuit Requireme nts for the T arg et Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 B.4.3 Microcontroller Hardw are Used in Onb oard Serial Programming . . . . . . . . . . . . . . . . . . . . [...]

List of T able s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 9 Panas onic List of T ables 1-1 General Specif ications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1-2 Block Diagram Ex planation . . . . . . . . [...]

List of Table s Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 10 Panas onic 8-5 IR Remote Signal Recei ver Re gisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 8-6 HEAMA and 5-/6-Bit Data Puls e W idths . . . . . . . . . . . . . . . . . . . [...]

List of Figur es MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 11 Panas onic List of Figures 1-1 Con vention al vs. MN102H Series Cod e Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1-2 Three-Stage Pipeline . . . . . . . . . . . . . . . . . . . . . . [...]

List of F igures Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 12 Panas onic 4-20 One-Shot Pulse Outpu t T iming (16-Bit T imers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4-21 External Count Dir ection Control T iming (16-Bit T imers) . . . . . . . . . . [...]

List of Figur es MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 13 Panas onic 5-12 Serial Interface C lock T iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 5-13 Master T ransmitter T iming in I 2 C Mode (with A CK) . . . .[...]

List of F igures Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 14 Panas onic 7-31 Shuttered Area Setup Exam ples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 7-32 Shutter Mov ement Setup Examples. . . . . . . . . . . . . . . . . . . . .[...]

List of Figur es MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 15 Panas onic 11-16 P30/CLH and P33/C LL (Port 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 11-17 P34/VREF (Port 3) . . . . . . . . . . . . . . . . . . . . . . . .[...]

About This Manual Using This Manual Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 16 Panas onic Abou t This Manual This manual is intended fo r assembly-lan guage programming engineers. It describ es the inte rnal conf iguration and hardware fu nctions of the MN102H75 K and MN102H85 K microcont rollers . Exc[...]

About This Manual Related Documents MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 17 Panas onic Related Documents ■ MN102H S eries LSI Us er Manua l (Describes the core hardw are.) ■ MN102H S eries In struction Ma nual (Describes the instruction set.) ■ MN102H Series C Compiler User Manual: Usag[...]

General Description MN102H Series Overview Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 18 Panasonic 1 General Description 1.1 MN102H S eries Over view The 16-bit MN102H seri es is the hi gh-speed l inear addr essing v ersio n of the MN10200 series. The n ew arch it ecture in this series is designed for C-l[...]

General Description MN102H Se ries Feature s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 19 Panasonic ■ Single-byte basic instr uction lengt h The MN102H series has r eplaced general re gisters with eight internal CPU re gisters di vided function ally i nto four address re gisters (A0 - A3) and fo[...]

General Description MN102H Series Feature s Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 20 Panasonic ■ Fast interrupt response MN102H series de vices can stop execu ting instructions, e ven those with long e xecution c ycles, to service interrupts immediately . After an interrupt occurs, the pro gram bra[...]

General Description MN1 02H Seri es De scriptio n MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 21 Panasonic ■ Outstanding po wer savings The MN102H ser ies contai ns separate b uses for ins tructions, data, and peripher al functions, whic h distr i butes and reduce s load capacitance, dr a- matical[...]

General Description MN102 H Serie s Descrip tion Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 22 Panasonic NX: Exte nsion ne gativ e flag If the most significant bit of the result of an operation has the value 1, this flag is set; if that bit is 0, th is flag is reset. ZX: Ext ension z ero flag If all bits [...]

General Description MN1 02H Seri es De scriptio n MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 23 Panasonic ■ Internal regis ters, memory , and spec ial function re gisters Note: 1. This all o cation is a r ep resent a t i ve example. Actual mem ory , periph eral, SF R, and I/ O po rt configur a ti[...]

General Description MN102 H Serie s Descrip tion Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 24 Panasonic ■ Addre ss spa ce The memory in the MN102H series is conf igured as linear address space. The instruction and data ar eas are not separated, so the basic segments are intern al R OM, internal RAM, an[...]

General Description MN1 02H Seri es De scriptio n MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 25 Panasonic ■ Interrupt contr oller An interrupt con troller e xternal to the core co ntrols all nonmaskable and maskable interrupts e xcept reset. There are a maximum of sixteen interr upt classes (clas[...]

General Description General Specifications Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 26 Panasonic 1.4 Gener al Spec ifi cations T able 1-1 General Specific ations P arameter Spec ification Structure Internal multiplier (16-bit × 16-bit = 32-bit) and saturate calculator Load/store architecture Eight regi[...]

General Description General Specifications MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 27 Panasonic Timer/counters F our 8-bit timers: ♦ Cascading function (forming 16- or 32-bit timers) ♦ Timer output ♦ Selectable clock source (internal or ex ternal) ♦ Serial interface cloc k generation ♦[...]

General Description Block Diagram Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 28 Panasonic 1.5 Block Diagram Figure 1-8 F unctional Block Diagram A1 A0 A3 A2 D1 D0 D3 D2 MDR T1 T2 Clock generator Clock source Instruction execution controller Instruction decoder Quick decoder Interrupt controller Instructio[...]

General Description Block Diagram MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 29 Panasonic T able 1-2 Bloc k Diagram Explan ation Bloc k Description Clock generator An oscillation circuit connected to a n e x ternal cr ystal supplies the clock to all blocks withi n the CPU. Program counter The progr[...]

General Description Pin Descriptions Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 30 Panasonic 1.6 Pin Descriptions 1.6.1 MN102 H85K Pin Description Notes: 1. Pins marked with an as terisk (*) are N-channel , open-drain pins. 2. Pin 2 5 i s V DD in the MN102H 85K and V PP in the MN1 02HF85K. Figure 1-9 M N1[...]

General Description Pin D escrip tions MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 31 Panasonic 1.6.2 MN102 H75K Pin Description Notes: 1. Pins marked with an aste risk (*) are N-chann el, open-drain pins. 2. Pin 41 is V DD in the MN102H75K a nd V PP in the MN102HF75K. Figure 1-10 M N102H75K Pin Con[...]

General Description Pin Descriptions Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 32 Panasonic T able 1-3 Pin Functions Bloc k Pin Name I/O Pin Count Description Po w e r V DD I 1 V oltage supply V SS I 2 Ground reference AV DD I 1 Analog volt age supply V DD /V PP I1 V oltage supply: V DD in mask ROM v er [...]

General Description Pin D escrip tions MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 33 Panasonic I/O ports MN102H75K/HF75K: total 66 pins MN102H85K/HF85K: total 50 pins P00 – P07 I/O 8 General-pur pose por t 0 I/O P10 – P17 I/O 8 General-pur pose por t 1 I/O P20 – P27 I/O 8 General-pur pose por[...]

General Description Pin Descriptions Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 34 Panasonic ■ Consideration s f or pow er suppl y , c lock, and res et pins ■ Connection th e PLL circu it The MN102H75K/85 K contains an internal PLL circuit. T o use this circuit, yo u must connect it to an external (la[...]

General Description Bus Interface MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 35 Panasonic 1.7 Bus Int erface 1.7.1 Descrip tion The b us interface op erates in external e xtension mode. Figure 1-15 pr ovides the memory space fo r the MCU in this mode. Figure 1-15 M emory Space in Ex ternal Extensi [...]

General Description Bus Interface Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 36 Panasonic 1.7.2 Bus Interface Control Registe rs The ex ternal memory wa i t regis ter (EXWMD) and memo ry mode regi ster 1 (MEMMD1) control the bus interf ace. EXWMD: External Memory W ait Regi ster x’00FF8 0’ EW[33: 30],[...]

Inter r upts Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 37 Panasonic 2 Inte rru pts 2.1 Des cription The most important f actor in real-time cont rol is an MCU’ s speed in servicing interrupt s. The MN102 H75K/85K has an extremely fas t interru pt response time due to its ability to a[...]

Interrupts Description Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 38 Panasonic Figure 2-2 In terrupt V ector Gro up and Class Assignments Group Interrupt V ector Priority Level Register Address Group 0 Group 1 Watchdog timer Group 2 Undefined instruction Group 3 Error interrupt Class 0 00FC42 (R/W) 00FC44[...]

Inter r upts Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 39 Panasonic Figure 2-3 Inte rrupt Servicing Time T able 2-2 Handler Pr epr ocessing Sequence Assemb ler Bytes Cyc les Push registers add -8,A3 mov A0,(A3) movx D0,(4,A3) 2 2 3 1 2 3 Interrupt ACK mov (FC0E),D0 31 Generate header a[...]

Interrupts Interrupt Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 40 Panasonic 2.2 Interrupt Setup Exampl es 2.2.1 Setting Up an Ex ternal Pin Interr upt In this example, an interru pt occurs on a falling-ed ge signal from the IRQ0 (P00) external interrupt pin, and the interrupt priority lev [...]

Inter r upts Interrupt Setup Exa mples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 41 Panasonic 3. Enable interrupts by writing a 1 to the interrupt enable flag (IE) in the PSW and setting th e interrupt masking level (IM[2:0]) to 7 (b’111’). No w if a falling edge occurs on IRQ0 (P00) , an inte[...]

Interrupts Interrupt Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 42 Panasonic 2.2.2 Setting U p a W atchdog T imer Inter rupt The watchd og time r int err upt is provided fo r detec ting a nd hand ling racing. Norm a l ope ra tion is not guarant ee d if t he progr am ret urns afte r a watc h[...]

Inter r upts Interrupt Setup Exa mples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 43 Panasonic The main program normally gen- erates and branches to the inter- rupt star t address. If the CPU accepts an interrupt, th e program br anches to address x’080 008’. The oscillator delay timer shares t[...]

Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 44 Panasonic 2.3 Interrupt Contr ol Registers A control re gister is assigned to each interrupt v ector group. Except for the class 0 reg isters (WDICR, PIICR, and EIICR), t he control r egisters allo w you to enable and set[...]

Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 45 Panasonic XnICL (System Interrupt) IR: Interrupt requ est flag 0: No interrupt requested 1: Interrupt reques ted ID: Interrupt det ect flag 0: Interru pt undetected 1: Interrupt detected The follo wing is an exam[...]

Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 46 Panasonic T able 2-4 Inte rrupt Contr ol Register s Register Address R/W Description IAGR x’00FC0E ’ R Acc epted interru pt group number reg ister WDICR x’00FC4 2’ R/W W atchdog i nterr upt contr ol registe r PIIC[...]

Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 47 Panasonic ADM3ICL ADM3ICH ADM2ICL ADM2ICH ADM1ICL ADM1ICH ADM0ICL ADM0ICH x’00FC78’ x’00FC79’ x’00FC7A’ x’00FC7B’ x’00FC7C’ x’00FC7D’ x’00FC7E’ x’00FC7F’ R/W R/W R/W R/W R/W R/W R/[...]

Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 48 Panasonic IA GR: Accept ed Inte rrupt Group Numb er Regis te r x’00 FC0E ’ IA GR returns the group number of an accepted interru pt, indicated in the 6-bit GN f ield. When the interrupt h andler has to calculates the [...]

Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 49 Panasonic PIICR: Undefin ed Instruction Int err upt Cont rol Regi ster x’00 FC44 ’ PIICR is an 8-bit access re gister . PIID : Undefined i nstruction interrupt detec t flag 0: Interru pt undetected 1: Interru[...]

Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 50 Panasonic IQ0ICH: External Interrupt 0 Inte rr upt Control Regis ter (High) x ’00F C49’ IQ0ICH sets the priority level for and enables external interrupt 0. It is an 8-bit access register . Use the MO VB instruction t[...]

Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 51 Panasonic IQ2ICL: Ex ternal Interrupt 2 Interrupt Control Register (Low ) x’ 00F C50’ IQ2ICL requ ests and v erifies interrup t requests for e xternal interrupt 2. It is an 8-bit access reg ister . Use the MO[...]

Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 52 Panasonic IQ3ICH: External Interrupt 3 Inte rr upt Control Regis ter (High) x ’00F C53’ IQ3ICH enables ex ternal interrupt 3. It is an 8-bit access re gister . Use the MO VB instruction to access it. The priority leve[...]

Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 53 Panasonic IQ5ICL: Ex ternal Interrupt 5 Interrupt Control Register (Low ) x ’00FC5A’ IQ5ICL requ ests and v erifies interrup t requests for e xternal interrupt 5. It is an 8-bit access reg ister . Use the MO [...]

Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 54 Panasonic TM4CBI CH: Timer 4 Compar e/Capture B Interr upt Contr ol Register ( High) x’00FC61’ TM4CBICH sets the priority le vel for and enables timer 4 compare/capture B interrupts. It is an 8-bit access re gister . [...]

Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 55 Panasonic TM4UDICL: Timer 4 Underfl ow I nterrupt Control Regis ter (Lo w) x’00 FC64 ’ TM4UDICL detects and requests timer 4 und erflow interrupts. It is an 8- bit access register . Use the MO VB instruction [...]

Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 56 Panasonic VBIICH: VBI (1) Inte rrupt Control Re gister (High ) x’00 FC67 ’ VBIICH enables VBI (1) interru pts. It is an 8-bit access re gister . Use the MO VB instruction to access it. The priority level for VBI (1) i[...]

Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 57 Panasonic TM5CAI CL: Ti mer 5 Co mpare/Cap ture A Interr upt Con trol Register (Low) x’00FC6A ’ TM5CAICL detects and requ ests timer 5 compare/capture interr upts. It is an 8-bit access re gist er . Use the M[...]

Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 58 Panasonic TM5UDICH: Timer 5 Underflo w Interrupt Control Reg ister (High) x’00FC6D’ TM5UDICH enables timer 5 underflo w interrupt s. It is an 8-bit access reg- ister . Use the MO VB instruction to access it. The prior[...]

Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 59 Panasonic TM2UDICL: Timer 2 Underfl ow I nterrupt Control Regis ter (Lo w) x’00 FC70 ’ TM2UDICL re gister detects and request s timer 2 underflo w interrupts. It is an 8-bit access re gist er . Use the MO VB [...]

Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 60 Panasonic TM1UDICH: Timer 1 Underflo w Interrupt Control Reg ister (High) x’00 FC73 ’ TM1UDICH enables timer 1 underflo w interrupt s. It is an 8-bit access reg- ister . Use the MO VB instruction to access it. The pri[...]

Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 61 Panasonic RMCICL: Remo te Sig nal Rece ive Inter ru pt Co ntro l Reg iste r (Low ) x’00F C76’ RMCICL detects and requests remote signal recei ve interrupts. It is an 8- bit access register . Use the MO VB ins[...]

Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 62 Panasonic ADM3ICH: Address 3 Matc h Interrupt Contro l Register (High) x’00 FC79 ’ ADM3ICH sets the prio rit y level for and enables address match 3 in ter- rupts. It is an 8-bit access reg ister . Use the MO VB instr[...]

Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 63 Panasonic ADM1ICL: Address 1 Match Inte rr upt Control R egiste r (Lo w) x’00FC7C’ ADM1ICL detects and requests address match 1 interrupts. It is an 8-bit access register . Use the MO VB instruction to access[...]

Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 64 Panasonic ADM0ICH: Address 0 Matc h Interrupt Contro l Register (High) x’00 FC7F ’ ADM0ICH enables address match 0 interru pts. It is an 8-bit access reg is- ter . Use the MO VB instruction to access it. The priority [...]

Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 65 Panasonic SCT0ICL: Serial 0 T ransmis sion End Interrupt Co ntrol Regis ter (Lo w) x’00 FC82 ’ SCT0ICL detects and requests serial 0 transmission end interrupts. I t is an 8-bit access register . Use the MO V[...]

Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 66 Panasonic SCR0ICH: Serial 0 Reception End Inte rrupt Control Re gister (High) x ’00 FC85 ’ SCR0ICH enables serial 0 reception end interrupts. It is an 8-bit access register . Use the MO VB instruction to access it. Th[...]

Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 67 Panasonic VBIVWICL: VBIVSYNC (2) In terrupt Control Regis ter (Low) x’00FC8A’ VBIVWICL detects and requests VB IVSYNC (2) interrupts. It is an 8-bit access register . Use the MO VB instruction to access it. V[...]

Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 68 Panasonic TM3UDICH: Timer 3 Underflo w Interrupt Control Reg ister (High) x’00FC8D’ TM3UDICH enables timer 3 underflo w interrupt s. It is an 8-bit access reg- ister . Use the MO VB instruction to access it. The prior[...]

Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 69 Panasonic OSDCICL: OSD (T e xt) Interrupt Con trol Regi ster (Lo w) x’00F C92’ OSDCICL detects and requests OSD (tex t) interrupts. It is an 8-bit access register . Use the MO VB instruction to access it. OSD[...]

Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 70 Panasonic SCT1ICH: Serial 1 T ransmiss ion En d Interrupt Control Register (High) x’00F C99’ SCT1ICH sets the prio rity le vel for and enab les serial 1 transmiss ion end interrupts. It is an 8-bit access re gister . [...]

Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 71 Panasonic I2CICL: I 2 C Inter ru pt Co ntro l Regi ste r (Low) x’00FC9C’ I2CICL detects and requests I 2 C interru pts. It is an 8-bit access reg is ter . Use the MO VB instruction to access it. I2CIR : I 2 C[...]

Low-Power Modes CPU Mode s Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 72 Panasonic 3 Low-P ower Modes The MN102H75K/85 K provides tw o ways to reduce p ower consump tion, con- trolling CP U operating an d standb y m o des to cut overall consump tion and shutting d own unused funct ions by sto pp in g the [...]

Low-P owe r Mod es CPU Modes MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 73 Panasonic 3.1.2 Exiting from S LO W Mode to NORMAL Mode The MN102H75K/85K rec ov ers from pow er up and reset in SLOW mode. F or nor mal opera- tion, the progr am must s witch the MCU from SLO W to NOR- MAL mode. The MN102H7[...]

Low-Power Modes CPU Mode s Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 74 Panasonic 3.1.3 Notes on In v oking a nd Exiting STOP and HAL T Modes ■ When in v oking ST OP and HAL T modes... T o reduce po wer consumption before in voking the ST O P or HAL T mode, stop current f lo w from out put pins and sta[...]

Low-P owe r Mod es Turning I ndividual Func tions On an d Off MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 75 Panasonic 3.2 T urning Individual Functions On and Off Y ou c annot set the PLL fun ction control bit during NORMAL mode . Y ou must set it f rom the SLO W mode. T o turn off the OSD b loc k [...]

Low-Power Modes CPU Cont rol Regist er Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 76 Panasonic 3.3 CPU Control Register CPUM: CPU Mode Control Register x’00 FC00 ’ This r egis ter controls the in v oking of all of the CPU modes. NWDEN: W atchdog timer reset 0: Enable watchdog tim er 1: Disable and cle[...]

Time rs 8-Bit Timer Desc ription MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 77 Panasonic 4T i m e r s 4.1 8-Bit Timer De scription The MN102H75K/85 K contains four 8-bit timers that can serve as interv al timers, e vent timer/counters, clock generato rs (divide-by-2 outpu t of the underflo w), refe[...]

Timers 8-Bit Timer Fe atures Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 78 Panasonic 4.2 8-Bit Timer Features T able 4-1 8-Bit Timer Func tions and Fe atures Funct ion/Feature Timer 0 Timer 1 Timer 2 Timer 3 Interrupt request flag(s) T M0UDICL register (TM0UDIR bit) TM1UDICL register (TM1UDIR bit) TM2U DI[...]

Time rs 8-Bit Timer Block Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 79 Panasonic 4.3 8-Bit Ti mer Block Diagrams Figure 4-3 Ti mer 0 Block Dia gram Figure 4-4 Ti mer 1 Block Dia gram (FE10) (FE00) TM0MD (FE20) B OSC /4 B OSC /64 B OSC /412 TM0I pin Multiplexer 0 1 2 3 Timer 0 underflow in[...]

Timers 8-Bit Timer Block Diagrams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 80 Panasonic Figure 4-5 Ti mer 2 Block Dia gram Figure 4-6 Ti mer 3 Block Dia gram (FE12) (FE02) TM2MD (FE22) Timer 2 underflow interrupt 0 1 2 3 Underflow Reload Timer 2 base register TM2BR TM2LD TM2EN TM2S0 TM2S1 Load Count 8 T[...]

Time rs 8-Bit Timer Timing MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 81 Panasonic 4.4 8-Bit Timer Timing Figure 4-7 Ev ent Timer Input Timing (8-Bit Timers) Figure 4-8 Cloc k Output and Interv al Timer Timin g (8-Bit Timer s) Load value TMnIO input BC value Time Load value TMnIO input 1 TMnIO outp[...]

Timers 8-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 82 Panasonic 4.5 8-Bit Timer Setup Examples 4.5.1 Setting Up an Event Counte r Using T imer 0 In this example, timer 0 generates an underflow interrupt on the fourth rising edge of the TM0 IO signal. The e vent counter continues [...]

Time rs 8-Bit Timer Setup Examples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 83 Panasonic TM0UDICL (e xample) x’00 FC74 ’ TM0UDICH (e xample) x’00 FC75 ’ 4. Set the divide-by ratio for timer 0. Since the timer will count 4 TM0IO cycles, write x’03’ to the timer 0 base register (T M0BR)[...]

Timers 8-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 84 Panasonic 4.5.2 Setting Up an Interva l T imer Usin g T ime rs 1 and 2 In this ex ample, timers 1 and 2 are cascaded to di vide B OSC /4 b y 60,000 an d generate an underflo w interrupt. 1. Disable timer 1 and 2 count ing in t[...]

Time rs 8-Bit Timer Setup Examples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 85 Panasonic TM2UDICH (e xample) x’00 FC71 ’ TM2UDICL (e xample) x’00 FC70 ’ TM1UDICH (e xample) x’00 FC73 ’ TM1UDICL (e xample) x’00 FC72 ’ 3. Set the divide-by ratio for timer 0. Since the timer will cou[...]

Timers 8-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 86 Panasonic TM2MD (e xample) x’00 FE22 ’ In the bank and l inear address- ing v ersions of the MN102 series, it was necessary to set TM0EN and TM0LD to 0 between steps 4 and 5, to ensure stable oper ation. This is unnecessar[...]

Time rs 8-Bit Timer Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 87 Panasonic 4.6 8-Bit Timer Control Register s T able 4-2 s ho ws the re gister s used to co ntrol the 8-bit timers. A binary co unter (TMnBC), a time base counter (TMnB R), and a timer m ode reg ister (TMnMD) is asso[...]

Timers 16-Bit Timer Description Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 88 Panasonic 4.7 16-Bit Timer Description The MN102H75K/85 K contains two 16-b it up/d own ti mers, timers 5 an d 6. Associated with each timer are tw o compare/capture registers that can capture and compare the up / do wn counter [...]

Time rs 16-Bit Timer Fe atures MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 89 Panasonic 4.8 16-Bit Timer Features T able 4-3 16-Bit Timer Functions a nd Featu res Function/Fe ature Timer 4 Timer 5 Interrupt request flag(s) TM4UDIR bit of TM4UDICL TM4CAICL bit of TM4CAIR TM4CBICL bit of TM4CBIR TM5UD[...]

Timers 16-Bit Timer Block Diagrams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 90 Panasonic 4.9 16-Bit Timer Bloc k Diagrams 4.10 16-Bit Timer Timing Figure 4- 15 Timer 4 Blo ck Diagram Figure 4- 16 Timer 5 Blo ck Diagram Figure 4-17 Sin gle-Phase PWM Output Timing (16-Bi t Timer s) TM4IC pin Timer 0 under[...]

Time rs 16- Bit Time r Timing MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 91 Panasonic Figure 4-18 Si ngle-Phase PWM Outp ut Timing with Data Chang e (16-Bit Time rs) Figure 4-19 T w o-Phase PWM Ou tput Timi ng (16- Bit T imers) Figure 4-2 0 One-Shot Puls e Output Timing (16- Bit Timers) CA TMnIOA T[...]

Timers 16-Bit Timer Timing Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 92 Panasonic Figure 4- 21 Extern al Count Direction Control Timing ( 16-Bit Ti mers) Figure 4 -22 Even t Timer I nput Timing (16-Bit Timers) Figure 4-23 Sin gle-Phase Ca pture I nput Timing (16-Bit Timers) T MnIB T MnIA CA BC value Time[...]

Time rs 16- Bit Time r Timing MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 93 Panasonic Figure 4- 24 T wo-Phase Capture I nput T iming (16-B it Timers) Figure 4-25 T wo-Phase 4x Encoder Timing (16-Bit Timers) Figure 4-26 T wo-Phase 1x Encoder Timing (16-Bit Timers) TMnIB TMnIA TMnCA 0033 (Example) 5A[...]

Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 94 Panasonic 4.11 16-Bit Timer Setup Examples 4.11.1 Setting Up an Event Counte r Using T imer 4 In this example, timer 4 coun ts the TM4IB input sig nal (B OSC /4 = 6 MHz or less) and generat es an in terrup t on th e second an[...]

Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 95 Panasonic TM4CA (e xample) x’00 FE84 ’ 3. Set the phase dif ference for timer 4. F or a 2-c ycle phase dif ference, write x’0001’ to timer 4 compare/capture re gi ster B (TM4CB). (The v alid range is -1 ≤ [...]

Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 96 Panasonic 4.11.2 Setting U p a Sing le-Phase PWM Outp ut Signal Using Ti me r 4 In this example, timer 4 is used to divide B OSC by 5 a nd generate a f iv e-cyc le, single-phase PWM signal. The duty of this signal is 2:3. T o[...]

Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 97 Panasonic P2DIR (e xample) x’00FFE 2’ ■ T o set up time r 4: Use the MO V instruction for this setup and only use 16-bit write operations . This step stops the TM4BC count and clears both TM 4BC and the S-R fl[...]

Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 98 Panasonic 6. Set the TM4NLD bit of the TM4MD register to 1 and th e TM4EN bit to 0. This enables TM4BC and the S-R flip-flop. This step ensures stable opera- tion. If it is omitted, the binary co un ter may not count the firs[...]

Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 99 Panasonic Figur e 4-30 bel o w sho ws the out put wa vefor ms for TM4O A. Both A and B interrupts can occur, b ut B interrupts can only occur if the TM4CB setting is from 0 to less than TM4C A. This is because when [...]

Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 100 Panasonic T wo potential types of errors are inherent with PWM o utput. First, because of the circuit conf iguration, direction errors can occur . The output circuit is conf igured with T flip-flops, so that even if one tran[...]

Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 101 Panasonic 4.11.3 Setting Up a T wo-Ph ase PWM Output Sign al Using Ti me r 4 In this e xample, timer 4 is used to di vide timer 0 underflo w by 5 and g enerate a fi ve- cycle, two-phase PWM s ignal. The phase dif f[...]

Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 102 Panasonic P2DIR (e xample) x’00FFE 2’ ■ T o set up time r 0: 1. Disable timer 0 count ing in the timer 0 mode regis ter (TM0MD). This st ep is unnecessary immediately after a reset, si nce TM0MD resets to 0. TM0MD (e x[...]

Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 103 Panasonic ■ T o set up time r 4: Use the MO V instruction for this setup and only use 16-bit write operations . This step stops the TM4BC count and clears both TM 4BC and the S-R flip-flop to 0. 1. Set the operat[...]

Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 104 Panasonic 6. Set the TM4NLD bit of the TM4MD register to 1 and th e TM4EN bit to 0. This enables TM4BC and the S-R flip-flop. This step ensures stable opera- tion. If it is omitted, the binary co un ter may not count the fir[...]

Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 105 Panasonic W ith PWM output, the duty cycle can chan ge dynami cally , which can cau s e the PWM wa veform t o skip a pu lse (see the sin g le buf fering section of fi gure 4-34 belo w). T o pr event th ese misses, [...]

Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 106 Panasonic 4.11.4 Setting U p a Sing le-Phase Capture Input Using Timer 4 In this example, timer 4 is used to divide B OSC /4 by 6 5,536 and measure ho w long the TM4IA inp ut signal stays high . An interr upt occur s on capt[...]

Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 107 Panasonic change an y other operati ng modes du ring t his step. When TM4MD[1:0] = b’10’ (dur- ing capture), TM4CA and TM4CB become read-only regis- ters. T o write to TM4CA or TM4C B, you mus t first se t TM4M[...]

Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 108 Panasonic 4.11.5 Setting Up a T wo-Ph ase Capture Inp ut Using Tim er 4 In this e xample, timer 4 is used to di vide the timer 0 underflow by 65,536 and measure the numbe r of cy cles from the rising edge of the T M4IA input[...]

Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 109 Panasonic TM0BR (e xample) x’00 FE10 ’ Do not change the cloc k source once you select it. Selecting t he clock source while you set up the count operati on control will corrupt the value in the binar y counter[...]

Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 110 Panasonic ■ T o service the inte rrupts and calculate the signal wi dth: 1. Run the interrupt service routine. Th e rout ine must determine the int errupt group, then clear th e interrupt request flag. Ignore the flags whe[...]

Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 111 Panasonic 4.11.6 Setting Up a 4x T wo-Phase Encod er Input Using Timer 5 In this ex ample, timer 5 inputs a 4 x two-phase en coded signal that makes it count up and do wn. An interrupt occurs when the counter reach[...]

Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 112 Panasonic ■ T o set up time r 5: Use the MO V instruction for this setup and only use 16-bit write operations . This step stops the TM5BC count and clears both TM 5BC and the S-R flip-flop to 0. 1. Set the operating mode i[...]

Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 113 Panasonic ■ T o service the inte rrupts: Run the interrupt s ervice routine. The routi ne must determine the in terrupt group, then clear the interru pt request flag. T imer 5 can input a two-phase encoder s ig n[...]

Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 114 Panasonic 4.11.7 Sett ing Up a 1 x T wo- Phase Encod er Input U s i n g Ti m e r 5 In this ex ample, timer 5 inputs a 1 x two-phase en coded signal that makes it count up and do wn. An interrupt occurs when the counter reach[...]

Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 115 Panasonic ■ T o set up time r 5: Use the MO V instruction for this setup and only use 16-bit write operations . This step stops the TM5BC count and clears both TM 5BC and the S-R flip-flop to 0. 1. Set the operat[...]

Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 116 Panasonic ■ T o service the inte rrupts: Run the interrupt s ervice routine. The routi ne must determine the in terrupt group, then clear the interru pt request flag. T imer 5 can input a two-phase encoder s ig nal. T imer[...]

Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 117 Panasonic 4.11.8 Setting U p a On e-Shot Pulse Ou tput Using T imer 5 In this e xample, timer 5 o utputs a one-s hot pulse. Th e pulse width is t wo clo ck cycles. ■ T o set up the o utput port: Set the P4MD2 bit[...]

Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 118 Panasonic ■ T o set up time r 5: Use the MO V instruction for this setup and only use 16-bit write operations . This step stops the TM5BC count and clears both TM 5BC and the S-R flip-flop to 0. 1. Set the operating mode i[...]

Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 119 Panasonic T imer 5 can output a one-shot pulse. T imer 5 do es no t o pera te in STOP mo de , when B OSC is o ff. If you use an e xternal clock, it mus t be synchro nized t o B OSC . Figur e 4-48 sho ws an e xample[...]

Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 120 Panasonic 4.11.9 Setting Up an Extern al Coun t Direction Contr oller Using T im er 5 In this ex ample, timer 5 counts B OSC /4 and the T M5IA pin controls the count direction (up o r down). An in terrupt occurs when the cou[...]

Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 121 Panasonic ■ T o set up time r 5: Use the MO V instruction for this setup and only use 16-bit write operations . This step stops the TM5BC count and clears both TM 5BC and the S-R flip-flop to 0. 1. Set the operat[...]

Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 122 Panasonic ■ T o service the inte rrupts: Run the interrupt s ervice routine. The routi ne must determine the in terrupt group, then clear the interru pt request flag. Either the TM5IA or TM5IB signal can contr ol the timer[...]

Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 123 Panasonic 4.11.10 S etting Up Extern al Reset Contro l Using T imer 5 In this example, timer 5 is reset by an e xternal signal while countin g up. ■ T o set up time r 5: Use the MO V instruction to set this data [...]

Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 124 Panasonic TM5CA (e xample) x’00 FE94 ’ 3. Set the TM5NLD bit of the TM5MD register to 1 and th e TM5EN bit to 0. This enables TM5BC and the S-R flip-flop. This step ensures stable opera- tion. If it is omitted, the bin a[...]

Time rs 16-Bit Timer Con trol Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 125 Panasonic 4.12 16-Bi t Timer Con trol Registers T able 4-6 sho ws the register s used to control the 16 -bit timers. A binary counter (TMnBC), a compare/captu re re gister A (TMnCA), a compare/capture re gister B[...]

Timers 16-Bit Timer Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 126 Panasonic TM4MD/TM5M D: Time r n Mode Re gister x’00F E80’/x’00FE9 0’ TMnEN: TMnBC coun t 0: Disa ble 1: Enable TMnNLD: TM nBC , T flip-flop , and S-R fli p-flop ope ration selec t 0: Set all to 0 (in itialize) 1:[...]

Serial Interfaces Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 127 Panasonic 5 Serial Interfaces 5.1 Des cription The MN102H75K/85 K contains two g eneral-pur pose serial interfaces with syn- chronous serial, U AR T , and I 2 C modes. The maxi mum baud rate in synchr onous serial mode i s[...]

Serial Interfaces Connecting the Serial Interfaces Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 128 Panasonic 5.3 Connecting the Serial Interfaces Figures 5-2, 5-3, and 5 -4 illustrate six different methods of connectin g the serial interface. 5.3.1 Synchronous S erial Mode Co nnections See section 11, “I[...]

Serial Interfaces UART Mode Baud Ra tes MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 129 Panasonic 5.4 U ART Mode Baud Rates In U AR T mode, the serial inter face transfer clock is set to 16 times the baud rate clock. The e xpression belo w is the formula for calculating the baud rate for the U AR T [...]

Serial Interfaces Serial Interfac e Timing Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 130 Panasonic 5.5.2 U ART Mode Timing In these timing charts, the character leng th is 8 bits, the parity is none, and the stop bit is 2-b it. Figure 5-6 Sync hr onous Serial Rec eption Timin g Figure 5-7 U ART T ransmis[...]

Serial Interfaces Serial Inter face Setup Examples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 131 Panasonic 5.6 Seri al Inte rface S etup Ex ample s 5.6.1 Setting U p U ART T rans mission Using S erial Interface 0 Y ou must use an 8-bit timer to set the tr ans fer cloc k. See sec- tion 5.6.3, “Se[...]

Serial Interfaces Ser ial In terfac e Se tup Ex amples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 132 Panasonic ■ T o set up seria l interface 0: 1. Config ure the t ransmissi on sett ings in the se rial port 0 contro l re gister (SC0CTR). Since the tran sfer clock is timer 0 divided by 8, select timer [...]

Serial Interfaces Serial Inter face Setup Examples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 133 Panasonic ■ T ransmission s e quence: 1. Write the first data byte to SC0TRB. Once th is data is in the register , trans- missio n begi ns, syn chronized to ti mer 0. 2. When an interrupt occurs, the[...]

Serial Interfaces Ser ial In terfac e Se tup Ex amples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 134 Panasonic 5.6.2 Setting Up Synchr onous Serial Re ception Using Serial Interface 0 This e xample illustrates serial reception in the synchr onous serial mod e with the following settings : ♦ LSB fi rst [...]

Serial Interfaces Serial Inter face Setup Examples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 135 Panasonic 5.6.3 Setting Up the Ser ial Interface Clock This e xample demonstr ates how to set up a 19,200 bps transfer clock for the U AR T inte rfac e by usin g timer 1 to di vide B OSC /4 by 39. The [...]

Serial Interfaces Ser ial In terfac e Se tup Ex amples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 136 Panasonic Do not change the cloc k source once you select it. Selecting t he clock source while you set up the count operati on control will corrupt the value in the binar y counter . 3. Set the TM1LD bit[...]

Serial Interfaces Serial Inter face Setup Examples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 137 Panasonic 5.6.4 Setting U p I 2 C T r ansmissio n Using Serial Inte rface 0 This example illustrates the microco ntroller as a master transmitter in the I 2 C mode, usin g the SBO0 and SBT0 pins. ■ T[...]

Serial Interfaces Ser ial In terfac e Se tup Ex amples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 138 Panasonic Reception must be enabled f or the circuit to det ect a stop sequence. 2. When you perfor m step 1, the SBT0 output sign al goes high. One cyc le later , the SB O0 output s ignal also goes high,[...]

Serial Interfaces Serial Inter face Setup Examples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 139 Panasonic 5.6.5 Setting U p I 2 C Recep tion Using Seria l Interface 0 This e xample illustrates the microcontroller as a master recei ver in the I 2 C mode, using th e SBO 0 a nd SBT 0 pins. When init[...]

Serial Interfaces Ser ial In terfac e Co ntrol Regist ers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 140 Panasonic 5.7 Serial I nterf ace Con tr ol Registe rs Three reg isters control each of the serial interfaces: the serial port control re gister (SCnCTR), the serial transmit/receiv e bu ffer (SCnTRB), [...]

Serial Interfaces Serial Interface Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 141 Panasonic SCnICM: Serial por t n I 2 C mode sel ect 0: I 2 C mo de off 1: I 2 C mo de on SCnLN: Se rial por t n char acter length 0: 7-bi t 1: 8- bit SCnPTY[2: 0]: Serial por t n parity bit sele ct 0[...]

Serial Interfaces Ser ial In terfac e Co ntrol Regist ers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 142 Panasonic SC0STR/SC1STR: Serial P or t n Status R egister x’0 0FD83’/x’00F D8B’ SCnSTR contains the error d etection and status flags for the serial inter- faces. SCnTBY : Serial por t n transm[...]

Analog-to- Digital Converter Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 143 Panasonic 6 Analo g-to-Dig ital C on ver ter 6.1 Des cription The MN102H75K/85 K contains an 8-bit char ge redistrib ution A/D con v erter (ADC) that can process up to 12 channels. The ref erence clock is select[...]

Analog-to-Digital Converter Bloc k Diag ram Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 144 Panasonic 6.3 Block Diagram 6.4 A/D Con version Timing 6.4.1 Se lecting the ADC Clock Source Calculate the A/D con version time as follo ws: con version time (s) = [ 12 (cycles) × (B OS C c ycle) (s) × di vide-by [...]

Analog-to- Digital Converter A/D Conver sion Timing MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 145 Panasonic 6.4.2 Sin gle Channe l/Single Con version T imin g When ANMD[1:0] = b’00’, th e ADC con verts one ADIN input signal a single time. An interrupt o ccurs when the con ver sion ends. Load t[...]

Analog-to-Digital Converter A/D Conversion Timing Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 146 Panasonic 6.4.4 Sin gle Channe l/Continuo us Con version T iming When ANMD[1:0] = b’10’, th e ADC con verts one ADIN input signal contin- uously . An interrupt occurs each time the con version ends. Load t[...]

Analog-to- Digital Converter ADC Setup Ex amples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 147 Panasonic 6.5 ADC Set up Examples 6.5.1 Setting Up Softw are-Controlled Single -Channel A/D Con v ersion This example illustrates si ng le-channel con version controlled by the software. The ADIN6 pin in[...]

Analog-to-Digital Converter ADC Setup Exam ples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 148 Panasonic AN6BUF (e x ample) x’00FF1 4’ 6.5.2 Setting Up Hardware- Controlle d Intermit tent Three-Channel A/D Con ver sion This example illustrates multip le-channel con version controlled by the hardware. [...]

Analog-to- Digital Converter ADC Setup Ex amples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 149 Panasonic ■ T o set up the i nput port: Set the P0DIR[5:3] bi ts of the port 0 I/O cont rol register (P0DIR) to 0. This sets the ADIN2 (P05), ADIN1 (P04 ), and ADIN0 (P03) pins (P11) to general-purpo s[...]

Analog-to-Digital Converter ADC Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 150 Panasonic 6.6 ADC Cont r ol Re gisters The ADC contains thirteen re gisters—one control re gister (ANCTR) and twelv e data b uf f ers (each asso ciated with one of the ADIN pins). ANCTR controls the operatin[...]

Analog-to- Digital Converter ADC Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 151 Panasonic ANCTR: ADC Control Register x’00FF0 0’ ANNCH[3:0]: Channel select f o r multiple-channel con version 0000 : Con ver t AD I N0 0111: Con v ert ADI N0 – ADIN7 0001: Con vert ADIN0 – ADI[...]

Analog-to-Digital Converter Cautions abo ut Analog-to-Digita l Converter Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 152 Panasonic 6.7 Cautions about Analog-to-Digital Con ver ter The type of th is Analog-to-Digital Con verter is a sample-hold one, and so the current tempor arily flo ws in con version to c[...]

On-Screen Display Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 153 Panasonic 7 On-Screen Displa y If you use the OSD function, the DMA function ex ecutes for both the te xt and graphics la yers, e ven if y our program does not use one of these la yers . T o pre- v ent error , program data[...]

On-Screen Display Bloc k Diag ram Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 154 Panasonic 7.3 Block Diagram Figure 7-1 O SD Block Diagram VSYNC Vertical position counter 10-bit VPOL OSD HSYNC HPOL CANH Field detector EOMON EOSEL OSDXI,O OSCSEL1,0 OSC1,2 4 MHz 48 MHz PLL R/W R/W SYSCLK CPU System clock IR[...]

On-Screen Display Power-Saving Considerations in the OSD Blo ck MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 155 Panasonic 7.4 P ower -Sav ing Considerations in the OSD Bloc k T able 7-2 sho ws bits that can decrease the power consumption of the OSD block. This section e xplains ho w to use these bit[...]

On-Screen Display OSD O per ation Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 156 Panasonic 7.5 OSD Operation This sect ion descr ibes the basi c operation of the OSD block. The remainder of section 7 pro v i des more det ai le d specif ications. 7.5.1 OSD C lock The OSD clock source is pro grammable to ei[...]

On-Screen Display OSD Opera tion MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 157 Panasonic ■ Graphi cs la yer The graphics layer contains tiled images. In the 16-color mode, each 4-bit dot on a tile can display one of 16 colo rs. Each tile can use either of two av ailable co lor palettes, allowing[...]

On-Screen Display OSD O per ation Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 158 Panasonic 7.5.7 Co n ditions for V RAM Writes ■ T ext layer Set CHP , CVP , GHP , and GVP f or ev ery line in the VRAM. If you do not, a soft ware processing error may occur . 1. The lead data for each line must be the colo[...]

On-Screen Display Standa rd and Exten ded Display Mode s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 159 Panasonic 7.6 Standard and Extended Di spla y Modes T wo modes are a vailable for the graphics and cursor layers, standard and e xtended. In e xtended mode, the cursor l ayer can displ ay four gr[...]

On-Screen Display Standard and Extended Dis play Mode s Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 160 Panasonic In standard mode, STC 0 is the only cursor tile co de register that is enabled. Use the cursor horizontal p os ition register (SHP , x’00F1 2’) and the cursor vertical position register (SV[...]

On-Screen Display Display Setup Examples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 161 Panasonic 7.7 Display Setup Examples 7.7.1 Se tting Up the Graph ics Layer This sect ion sho ws ho w to set up the graphics display data in the VRAM. ■ Register settings RAMEND (x’0 07F04’) = x’80FF’ ([...]

On-Screen Display Display Setu p Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 162 Panasonic Figure 7 -4 Graph ics Displ ay Ex ample Line 1 HSZ= 1 (2x) VP = x'3' VSZ = 3 (6x) HSZ = 0 (1x) Repeated tile Line 2 HP = x'4' VP = x'58' VP = x'40' VSZ = 0 (1x) GTC = [...]

On-Screen Display Display Setup Examples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 163 Panasonic 7.7.2 Se tting Up the T ext Layer This section sh ows ho w to set up the text display data in th e VRAM. ■ Register settings RAMEND (x’0 07F04’) = x’80FF’ (T ex t RAM end ad dress: x’9F FF?[...]

On-Screen Display Display Setu p Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 164 Panasonic The te xt displa y starts one dot to the right of the HP setting. Figure 7-5 T e xt Displa y Exampl e Line 1 HSZ = 2 (3x) VP = x'3' VSZ = 3 (6x) HSZ=0 (1x) Line 2 HP = x'4' VP = x'70[...]

On-Screen Display VRAM MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 165 Panasonic 7.8 VRAM 7.8. 1 VRAM Oper ati on ■ T ext Layer CC: Charac ter Code ID Code: 0 0 CCH[9:0] Specifi es the address of one o f 1024 character s stored in the R OM. COL: Color Control Code (Norm al Mo de) ID Code: 10 BSHAD[...]

On-Screen Display VRAM Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 166 Panasonic BLINK Specifies character blink ing. 0: Disa ble 1: Enable BCOL[3:0] Specifi es the backgroun d color (1 of 16 color s). CCOL[3 :0] Specifi es the fore ground (character) color (1 of 16 colors). COL: Color Control Co de (Close[...]

On-Screen Display VRAM MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 167 Panasonic CHP: Char acter H orizontal P osition C ontrol Co de ID Code: 1 1 CHSZ[1:0] Specifies the H size of the characters on the next line. 00: 1 dot = 1 VCLK peri od 01: 1 dot = 2 VCLK peri ods 10: 1 dot = 3 VCLK peri ods 11:[...]

On-Screen Display VRAM Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 168 Panasonic GCB[3:0] Specif i es the number o f times (up to 16) a blank or graphi c til e is repeated. GPRT Specifies grap hics color palette 1 or 2 . 0: Palette 1 1: Palette 2 GTC[8:0 ] Specifies the ad dress of one of 51 2 graphic tile[...]

On-Screen Display VRAM MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 169 Panasonic 7.8.2 VRAM Organiz ation Notes: 1. A ll addre sses are e xpressed in he x notation. Other v alues are de cimal. 2. G RAMEND: Graph ics RAM end ad dress (programma ble to any address) 3. CRAM END: T ext RAM end address ([...]

On-Screen Display VRAM Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 170 Panasonic A. GE XTE = 1 B. GE XTE = 0 Figure 7-7 Graphic s VRAM Organ ization for T w o Modes GRAMEND − 3F GRAMEND − 3E GRAMEND − 3D GRAMEND − 3C GRAMEND − 3B GRAMEND − 3A GRAMEND − 2F GRAMEND − 2E GRAMEND − 3 GRAMEND [...]

On-Screen Display VRAM MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 171 Panasonic 7.8.3 Ca utions about the number of displa y code set to VRAM When the display lines are adjoine d or over lapped, and the n umber of the ab ov e display cod e is extremely fe wer than that o f the below one, f irst lin[...]

On-Screen Display ROM Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 172 Panasonic 7.9 ROM 7.9.1 R OM Or ganizatio n Notes: 1. A ll addre sses are e xpressed in he x notation. Other v alues are de cimal. 2. G R OM END: Graphics R OM end ad dress (prog r ammable to any addr ess) 3. CR OMEND: T ext ROM end addr[...]

On-Screen Display ROM MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 173 Panasonic 7.9.2 Graph ics ROM Organ izatio n in Different Color Modes The graphics layer supports up to sixteen colors, in the 16-color mode, but also supports 2-, 4- , and 8-color modes. The smaller the number of colors, the less[...]

On-Screen Display ROM Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 174 Panasonic Figure 7-11 G raphics R OM in the Fou r Color Modes (1 6W x 16H Tiles) ROMEND − 80 × N + 1 ROMEND − 180 ROMEND − 160 ROMEND − 140 ROMEND − 120 ROMEND − 100 ROMEND − E0 ROMEND − C0 ROMEND − A0 ROMEND − 80 RO[...]

On-Screen Display ROM MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 175 Panasonic Figure 7-12 G raphics R OM in the Fou r Color Modes (1 6W x 18H Tiles) ROMEND − 90 × N + 1 ROMEND − 1B0 ROMEND − 18C ROMEND − 168 ROMEND − 144 ROMEND − 120 ROMEND − FC ROMEND − D8 ROMEND − B4 ROMEND ?[...]

On-Screen Display ROM Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 176 Panasonic Figure 7- 13 Graphics R OM Orga nization in 16-Color Mo de (16W x 16H Tiles) Figure 7-14 G raphics R OM Orga nization in 8-Color Mo de (16W x 16 H Tiles) Figure 7-15 G raphics R OM Orga nization in 4-Color Mo de (16W x 16 H Til[...]

On-Screen Display ROM MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 177 Panasonic Figure 7- 17 Graphics R OM Orga nization in 16-Color Mo de (16W x 18H Tiles) Figure 7-18 G raphics R OM Orga nization in 8-Color Mo de (16W x 18 H Tiles) Figure 7-19 G raphics R OM Orga nization in 4-Color Mo de (16W x 1[...]

On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 178 Panasonic 7.10 S etting Up t he O SD 7.10.1 Setting U p the OS D Display Colo rs This section des cribes how to set up the display colors for the OSD. ■ T o set up the c olor palettes: Write your settings to the color pa[...]

On-Screen Display Setting Up the OSD MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 179 Panasonic ■ T o set up the te xt displa y color s: Write to the fields described below . ♦ CCOL[3:0] (CO L bits 3 to 0 in the RAM dat a) sets the color of th e charac- ter . T his v alue is in re fer ence to t h[...]

On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 180 Panasonic T r ansluce ncy Selecting YS palette output, by setting the YSPL T bit of OSD1 (x’007F06’) to 1, disab les the PR YM bit. With this setting, you must also set the TRPT and TRPTF bits to 1. Y ou ca n specify t[...]

On-Screen Display Setting Up the OSD MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 181 Panasonic T able 7-9 RGB, YM, and YS Output Contr ol Settings YSPL T PR YM TP RT TR PTF RGB Y M YS W avefor m in figure 7-21 0 0 0 0 Co lor pal et tes 0 and F output low Col or palette s 0 and F output low Color pal[...]

On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 182 Panasonic Figure 7-21 OSD Signal W avef orm TV Graphics la yer Color palette 1 (YM3 = 1, YM2 = 0, YM1 = 0, YM0 = 1) Color palette 0 (YM3 = 0, YM2 = 0, YM1 = 0, YM0 = 1) Color palette 2 (YM3 = 0, YM2 = 0, YM1 = 0, YM0 = 0) [...]

On-Screen Display Setting Up the OSD MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 183 Panasonic Figure 7-22 OSD Sig nal Output Switches *** YM3 Bit 15 *** R 1 1 *** R 2 2 *** R 3 3 *** G0 4 *** G 1 5 *** G 2 6 *** G 3 7 *** B 0 8 *** B1 9 *** B 2 1 0 *** B 3 11 *** YM 0 1 2 *** YM 1 1 3 *** YM 2 1 4 [...]

On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 184 Panasonic 7.10.2 T ext La yer Function s This section describes the cha racter enhancement functions a vailable in the te xt layer . ■ Outlining In both no rmal and closed-caption modes, writing a 1 to bit 9 (FRAME) of t[...]

On-Screen Display Setting Up the OSD MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 185 Panasonic ■ Bo x shadowing In normal mode, writing a 1 to b it 12 (BSHAD1) o f the COL s etting in the VRAM causes a box shado w to appear around all ch aracters follo wing that COL. If COL bit 11 (BSHAD0) is 0, t[...]

On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 186 Panasonic ■ Italicizin g In closed-caption mod e, writ ing a 1 to bit 10 (IT ALIC) of the CO L settin g in the VRAM italicizes all characters follo wing that COL. Figure 7 -26 sho ws an examp le of an italicized characte[...]

On-Screen Display Setting Up the OSD MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 187 Panasonic 7.10.3 Display S izes ■ Graphic ti le siz es The settings shown are f or interlaced displays . In progressive di s plays, the v er tical size settings (GVSZ[1:0]) are as f ollows: 01 = 1x, 10 = 2x, and 1[...]

On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 188 Panasonic ■ Characte r sizes The settings sho wn are for interlaced displa ys. In progressiv e displa ys, the v er tical size sett ings (CVSZ[1:0]) are as f ollows: 01 = 1x, 10 = 2x, and 11 = 3x. The 00 setting is re ser[...]

On-Screen Display Setting Up the OSD MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 189 Panasonic 7.10.4 Setting U p the OS D Display P osition This sect ion descr ibes ho w to control th e positioni ng of t he OSD. ■ T o set up the h orizontal pos ition: Cursor ♦ Write the horizontal position of t[...]

On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 190 Panasonic ■ T o set up the v ertical position: Cursor ♦ Write the vertical position of the cursor to th e SVP[9 :0] field (x’007F14 ’). ♦ V alid range: x’3 F0 ’ − (no . of H scan lines) ≥ SHP ≥ x’03?[...]

On-Screen Display DMA and Inte rrupt Timing MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 191 Panasonic 7.11 DMA and Interrupt Timing This sect ion descr ibes ho w the MN102H75K/85K han dles the ti ming of di rect memory access (DMA) transfers of OSD data and OSD interrupts. ■ DMA If you use the OSD[...]

On-Screen Display DMA and Inte rrupt Timing Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 192 Panasonic Figure 7-30 DMA an d Interrupt Timing f or the OSD Text DMA Text interrupt Graphics interrupt 12Ts 4nTs 5Ts 4nTs Scan line 1 Television Screen Graphics DMA Graphics interrupt Line G1 Graphics DMA Text DMA [...]

On-Screen Display Selecting the OSD Dot Clock MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 193 Panasonic 7.12 Selecting the O SD Dot Cloc k This sect ion descr ibes ho w to set up the OS D dot clock. ■ Selecting th e cloc k source The source for the OSD dot clock is pro grammable to either the 4-MH[...]

On-Screen Display Controlling the Shuttering Effect Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 194 Panasonic 7.13 Contr olling the Shuttering Effect The MN102H75K/ 85K OSD achi e ve s a shut tering eff ect using four pro- grammable shutters — two v er tical and tw o h orizo ntal. W ith this feature, you[...]

On-Screen Display Controlling the Shu ttering Effect MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 195 Panasonic Figure 7-3 1 Shuttered Area Se tup Examples HSHT0 VSHT1 VSHT0 HSHT1 VSON0 = VSON1 = 1: V shutters 0 and 1 on HSON0 = HSON1 = 1: H shutters 0 and 1 on VSP0 = 0: V shutter 0 shutters below VS[...]

On-Screen Display Controlling the Shuttering Effect Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 196 Panasonic 7.13.2 Controlling Shu tter Mov ement Enabling the shu tter mo vement function in the re gisters allows the shut tered ar ea to e xpand or co ntract ov er time, pro ducing a wipe-in or wip e-out ef[...]

On-Screen Display Controlling the Shu ttering Effect MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 197 Panasonic Figure 7- 32 Shutter Mo vement Setup Examp les T elevision screen VSM0 = 1: V shutter 0 movement enabled VSM1 = 0: V shutter 1 movement disabled HSM0 = HSM1 = 1: Movement enabled for H shut[...]

On-Screen Display Controlling the Shuttering Effect Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 198 Panasonic 7.13.3 Controlling S huttering Effects Through register set tings, yo u can inde pendently control s hutter ing for t e xt, te xt backgroun d, graphi cs, and col or backgroun d. Y ou can also ou tp[...]

On-Screen Display Controlling the Shu ttering Effect MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 199 Panasonic ■ T o shutter the co lor bac kground: Set the color backg rou nd shutter con trol bit, COLBSHT , of the shut ter cont rol re gister , SHTC (x’00 7F28’) to 1. This fu nction e xists on[...]

On-Screen Display Controlling the Shuttering Effect Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 200 Panasonic 7.13.4 Controlling L ine Shuttering It is po ssible t o cancel s hutterin g of indi vidual lines on the text and graph ics layers s o that they will be dis p layed on both shuttered and non -shutte[...]

On-Screen Display Field Detection Circuit MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 201 Panasonic 7.14 Field Detection Cir cuit 7.14.1 Block Diagr am 7.14.2 D escription The 7-bit field counter in this block reset s e very HSYNC interval to count the system clock. At each VSYNC interval, the 4 MSB[...]

On-Screen Display Field Detection Circuit Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 202 Panasonic 7.14.3 Considera tions for Interlaced Displays ■ Switch ing the displ ay start field The OSD is constructed so the display start p osition is the field (f ield 1) where the EOMON bit is 1. Ho wev er , inte[...]

On-Screen Display OSD Regis ters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 203 Panasonic 7.15 OSD Re gisters All registers in OSD block canno t be written by byte (by word only). Read by byte is poss ible. CROMEND: T ext ROM End Add ress Re gister x’007F0 0’ A[17:8] holds the programmabl e por[...]

On-Screen Display OSD Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 204 Panasonic is x’900F ’ to x’9FFF ’, with a programmabl e range from x’0 0’ to x’ FF’. STC0: Cursor Tile Code Register 0 x’00 7F10’ SPR T0: Cursor 0 color palette s elect 0: Graphics color palette 1 1: Graphic[...]

On-Screen Display OSD Regis ters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 205 Panasonic STC3: Cursor Tile Code Register 3 x’007E2E’ SPR T3: Cursor 3 color palette s elect 0: Graphics color palette 1 1: Graphics color palette 2 STC3[8:0]: Cu rsor 3 T ile Code Use the same R OM data as that use[...]

On-Screen Display OSD Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 206 Panasonic 00: 1 dot = 1 VCLK peri od 01: 1 dot = 2 VCLK peri ods 10: 1 dot = 3 VCLK peri ods 11: 1 dot = 4 VCLK peri ods GISHT : Graphics initial s hutter control 0: Shutter control on 1: Shutter control of f GIHP[9:0]: G ra ph[...]

On-Screen Display OSD Regis ters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 207 Panasonic CIVSZ[1:0]: T e xt initia l ver tical s ize CIVP[9:0] : T ext initial v er tical pos ition EV OD: Displa y Start Field Contro l Regis ter x’007F0 E’ EOSEL: Ev en/odd field s elect 0: Select the smaller cou[...]

On-Screen Display OSD Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 208 Panasonic OSD1: OSD Regi ster 1 x’00 7F06’ A write to the OS D bit of OSD1 takes eff ect on the ne xt leading edge of VSYNC. If y ou are turning the OSD on, the OSD star ts operating on the next VSYNC after the program writ[...]

On-Screen Display OSD Regis ters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 209 Panasonic OSD2: OSD Regi ster 2 x’007F0 8’ SPEXT: Cursor ex tended mo de select 0: Standar d mode (16 x 16 pixel s) 1: E xt end ed mo de (32 x 32 pixels) GTHT : Graphi c tile height se lect 0: 16 pix els high 1: 18 [...]

On-Screen Display OSD Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 210 Panasonic OSD3: OSD Regi ster 3 x’007F 0A’ BLINK: Characte r bli nking c ontrol Controls blinking for text-layer characters with BLINK set in the COL code. 0: Don’t blink 1: Blink CANH: V er tic al po si ti on cont rol fo[...]

On-Screen Display OSD Regis ters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 211 Panasonic VSHT1: V er tical Shutter 1 Register x ’007F2 2’ VSON1: V er tical shu tter 1 on/o ff 0: Off 1: On VSP1: V er tical shutter 1 shuttering dire ction 0: Sh ut ter b e low 1: Sh utter a bove VSMP1: V er tical[...]

On-Screen Display OSD Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 212 Panasonic HSHT1: Horizo ntal Shutter 1 Regis ter x’007F26’ HSON: Horizo ntal shut ter 1 on/off 0: Off 1: On HSP1: Horiz ontal s hutter 1 shuttering dir e ction 0: Shut ter to the righ t 1: Shut ter to the left HSMP1: Horizo[...]

On-Screen Display OSD Regis ters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 213 Panasonic CPT0 – CPTF: T ext P alet te Colors 0 – 15 Re gisters x’007F80 ’ – x’007F9 E’ These reg isters contain the colors used in the text layer . When digital out- put is selected, CPTnYM0 is output as [...]

On-Screen Display OSD Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 214 Panasonic BBSHD: Blac k Bo x Shadowing R egi ste r x’007F A4’ This re gister con t ains the color used as black in bo x shad o wing. When dig- ital output is selected, BBSHD YM0 is output as YM, BBSHDB0 as B, BBSHDG0 as G, [...]

On-Screen Display OSD Regis ters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 215 Panasonic GPT20 – GPT2F: Graphics P alette 2 Colors 0 – 15 Registers x’007FE0’ – x’007FFE’ These re gisters contain one of tw o sets of colors used in the graphics laye r . When digit al outp ut is s elect[...]

IR Remote Signal Receiver Description Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 216 Panasonic 8 IR Remo te Signal Receiver 8.1 Des cription The MN102H75K/85K contains a remote signal receiv er that processes signals in two formats: Househo ld Electrical Appliance Manuf acturers Association (HEAMA) format[...]

IR Remote Signal Receiver Block Diagram MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 217 Panasonic 8.2 Block Diagram Figure 8 -1 IR Remot e Signal Receiver B loc k Diagram 54 3 2 1 0 MUX CK CK 765 4 3210 MUX CK MUX R CK 4 RMTC: x’007E04’ Frequency division counter PWM3 (375 kHz, 2.7 s) Clock supp[...]

IR Remote Signal Receiver IR Remote Signal Receiver Oper ation Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 218 Panasonic 8.3 IR Remote Signal Re ceiver Operation 8.3.1 O perating Modes The IR remote signal recei ver has three operatin g modes: HEAMA, 5-/6- bit, and HEAMA – 5-/6 -bit automatic detect . Se[...]

IR Remote Signal Receiver IR Remo te Signal Receiver Operation MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 219 Panasonic 8.3.3 8-B it Data Reception Resetting the 8-bit data reception counter allows the microcontroller to receiv e 8- bit data, eith er with or without a leader . The software can rese[...]

IR Remote Signal Receiver IR Remote Signal Receiver Oper ation Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 220 Panasonic 8.3.4 I dentifying the Data F o rmat The microcontrol ler determines the l ogic le v els o f the data by testin g the interval between remote signal edges. T able 8-1 shows the in terv a[...]

IR Remote Signal Receiver IR Remo te Signal Receiver Operation MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 221 Panasonic 8.3.5 G enerating Inter rupts The IR remote signal recei ver has fou r interrupt v ectors: leader detection , trailer detection, 8-bit data reception detection, and pin ed ge det [...]

IR Remote Signal Receiver IR Remote Signal Receiver Oper ation Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 222 Panasonic 8.3.6 Co ntrolling the SL O W Mode Use bit 7 (SP) in the RMLD reg- ister to toggle the noise filter sampling frequency between PWM6/PWM8 and PWM3/ PWM5. The MN 102H series micr ocon trol[...]

IR Remote Signal Receiver IR Remo te Signal Receiver Control Regis ters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 223 Panasonic 8.4 IR Remot e Signal Receiver Control Regis- ters All re gisters in RMC block cann ot be writ ten by byte (by w ord only). Read by byte is poss ible. RMTC: Remo te Si gn[...]

IR Remote Signal Receiver IR Remote Signal Receiver Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 224 Panasonic All re gisters in RMC block cann ot be writ ten by byte (by w ord only). Read by byte is poss ible. RMIR: Remote Sig nal Interrupt Con trol Regi ster x’007EA 2’ RMIR controls [...]

IR Remote Signal Receiver IR Remo te Signal Receiver Control Regis ters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 225 Panasonic RMIS: Remote Signa l Interrupt Status Register x’00 7EA0 ’ RMIR in dicates th e detection and oper ation st atus of r emote si gnal in ter- rupts. It is a 16-bit acce[...]

IR Remote Signal Receiver IR Remote Signal Receiver Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 226 Panasonic RMLD: Remote Sig nal Lead er V alue Set Register x’007EA C’ RMLD is a 16-bit access re gister . fPWM1 = fSYSCLK/23, fPWM3 = fSYSCLK/25, fPWM5 = fSYSCLK/27, fPWM6 = fSYSCLK/28,[...]

Closed-Caption Decoder Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 227 Panasonic 9 Closed-Caption D ecoder 9.1 Des cription The MN102H75K/85K contain s two identical closed-cap tion decoder circuits, CCD0 and CCD1. The d ecoders extract encod ed captions from com posite video signals. F [...]

Closed-Caption Decoder Functional Des cription Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 228 Panasonic 9.3 Functional Description 9.3.1 An alog-to-Digital Co n verter The const an ts shown in figures 9-2 to 9-4 ar e re comm e nded values only . Operatio n at t hese va lues is not guara nte e d. The analo[...]

Closed-Caption Decoder Functional Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 229 Panasonic 9.3.2 Cl amping Circuit This bl ock clam ps the in put v ideo si gna l (CVB S0, CV BS1 ). The clamping circuit internal to the M N102H75K/85K provides three current sources — high, medium, and l[...]

Closed-Caption Decoder Functional Des cription Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 230 Panasonic T able 9-5 pro vides th e re gisters used to control and mo nitor the clamp ing cir cuit. See the page number ind icated for re gist er and bit descriptions. 9.3.3 Sy nc Separator Ci rcuit A lo w-pass f[...]

Closed-Caption Decoder Functional Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 231 Panasonic Figure 9-6 Sync Separator Ci rcuit Blo ck Diagram LPF MING CLMODE[1:0] CLM Clamp control pulse signal ADDA T A[7:0] NFSW[1:0] LPF1OUT[6:0] LPFOUT[6:0] SCMING[9:0] MINP Minimum sync tip load pulse [...]

Closed-Caption Decoder Functional Des cription Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 232 Panasonic 9.3.3.1 HSYNC Se parator The HSYNC separator e xtracts the HSYNC signal from the co mposite sync signal u sing the s amplin g clock gen erated b y the sy nc separato r clock pu lse gen- erator . This ci[...]

Closed-Caption Decoder Functional Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 233 Panasonic 9.3.3 .2 VSYNC Separator The VSYNC separator e xtracts the VSYNC signal from the co mposite signal. Like the HSYNC separator , i t contains programmab l e method s for eli minatin g noise. The VC [...]

Closed-Caption Decoder Functional Des cription Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 234 Panasonic T able 9-7 pro vides the registers used to control and moni tor the data slicer . See the page number ind icated for re gist er and bit descriptions. 9.3.5 Co ntroller and Sam pling Circu it The control[...]

Closed-Caption Decoder Functional Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 235 Panasonic 9.3.5.1 CRI Detection for Sampling Clock Generation The decoder cap tures the caption data on the rising edge of the CRI pulse. T o achie ve this, it contains a circuit to accurately detect th e C[...]

Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 236 Panasonic 9.4 Closed-C aption Decoder Register s All registers in Closed-caption Decoder block cannot be written by byte (by word only). Read by byt e is po ssible. T able 9-9 Close d-Caption Decod e[...]

Closed-Caption Decoder Close d-Cap tio n Deco der Re gist ers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 237 Panasonic For desig ns using the closed -cap- tion de coder, alw ays tie the FCC NT register to x’0008’ . FCCNT : VBI Decoding Format Select Reg ister x’007E0 0’ (FCCNTW x’007E20?[...]

Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 238 Panasonic MAXMIN: CRI Int er v al Max imum and Minimum Regis ter x’007E0 2’ (MAXMI NW x’00 7E22’) MAX[7:0]: M aximum v alue during the CRI i n ter val V alid range: x’00’ to x’F F ’ M[...]

Closed-Caption Decoder Close d-Cap tio n Deco der Re gist ers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 239 Panasonic HNUM: HSYNC Count Register x’00 7E06’ (HNUMW x’007E26’) This register allo ws you to time the interrupt occurring after the line 21 data capture to a line o ther than line [...]

Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 240 Panasonic CRIF A: CRI F requency Wi dth Register A x’00 7E0C ’ (CRIF A W x’007E2C’) The CRIF A and CRIFB re gisters store the CRI cycles fro m rising edge to rising edge, for monitoring wheth[...]

Closed-Caption Decoder Close d-Cap tio n Deco der Re gist ers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 241 Panasonic CRI1E: CRI Cap ture Stop Ti ming Control Reg ister 1 x’007E12’ (CRI 1EW x’0 07E3 2’) CRI1E[10: 0]: Stop position f or CRI capture 1 V alid rang e: x’000’ to x’ 7FF’[...]

Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 242 Panasonic DA T A E : Data Cap ture Stop Timing Co ntrol Register x’ 007E1 A’ (D A T AEW x’007E3A’) D A T AE[10:0]: Stop po sition f or data capture Set this value high enough to allow the las[...]

Closed-Caption Decoder Close d-Cap tio n Deco der Re gist ers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 243 Panasonic FQSEL: F requency Select R egister x’00 7EC2 ’ (FQSEL W x’007EE2’) In this register , set the sam pli ng cycle for separating the HSYNC and VSYNC signals from the composite[...]

Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 244 Panasonic Use this register to specify the position for capturing the pedestal level v alue used during pe destal clamping . Specify a number of ADC clocks after th e leadi ng edge of HSYNC. The v al[...]

Closed-Caption Decoder Close d-Cap tio n Deco der Re gist ers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 245 Panasonic BSP[5:0]: Sy nc separ ator l e vel f or pedestal clampin g Sync separator level = (sync tip le vel/2) + BSP[5:0] . The valid range is x’00’ t o x’3F’. PSP[5:0]: Sy nc separ[...]

Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 246 Panasonic HSEP1: HSYNC Separ ator Control Register 1 x’007EC E’ (HSEP1W x’007 EEE’) HSFREQ[10:0 ]: Correction HSYNC frequency Set the correction HSYNC cycle in this field in HSYNC separator s[...]

Closed-Caption Decoder Close d-Cap tio n Deco der Re gist ers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 247 Panasonic HDISTW: Sy nc Separ ator Detection Control Re gister 2 x’ 007ED 6’ HDISTWW x’00 7EF6’) HDISTW[8:0]: HSYNC c ount sett ing the in terval f or sync sepa ration d etection In [...]

Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 248 Panasonic CLPCND1: Clamping Control Si gnal Statu s Register 1 x’007EDC’ (CLPCND W x’007EFC’) This re gister is for monitoring the status of the clamping current sour ce switch sho wn in fi g[...]

Pulse Width Modulator Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 249 Panasonic 10 Pulse Width Modulator 10.1 De scripti on F or inf or mation on the SLO W mode, see section 3.1, “CPU Modes.” The MN102H75K/ 85K contai ns se ven 8-b it puls e width mo dulators (PWMs) with a mini mum p[...]

Pulse Width Modu lator Bloc k Diag ram Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 250 Panasonic Not using internal pullup func- tion,Figuer10-2 connect the e x ter nal pullup registance 10.2 Block Diagram 10.3 PWM Da ta Regist ers All registers in PWM function can not be written by by te (be word only). R[...]

I/O Ports Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 251 Panasonic 11 I/O P orts 11.1 De scripti on The MN102H75K/85 K contains 50 pins th at form gen eral-purp ose I/O port s. Ports 0, 1 , 2, 3, 4, and 5 are 8-b it ports , and port 6 is a 2-bi t por t. All of these pi ns hav e alternat[...]

I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 252 Panas onic 11.2 I/ O P ort Circuit Dia g rams Figure 11- 1 P00/RMIN/IRQ0 (P or t 0) P0PUP0 0: Pullup off 1: Pullup on P0MD0 0: P00/IRQ0 1: RMIN/IRQ0 P0DIR0 0: Port input 1: Port output P0OUT0 Pin P0IN0 RMIN Schmidt trigge[...]

I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 253 Panasonic Figure 11-2 P03/ADIN0 to P0 7/ADIN4 (P or t 0) P0PUPn 0: Pullup off 1: Pullup on P0MDn 0: P03, P04, P05, P06, P07, 1: ADIN0, ADIN1, ADIN2, ADIN3, ADIN4 ADIN0, ADIN1, ADIN2, ADIN3, ADIN4 P0DIRn 0: Port inpu[...]

I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 254 Panas onic Figure 11-3 P10/ADIN5/IRQ1, P11/ ADIN6/IRQ2, and P12/ADIN7/IRQ3 ( P or t 1) P1PUPn 0: Pullup off 1: Pullup on P1MD(2n) 0: P10/IRQ1, P11/IRQ2, P12/IRQ3 1: ADIN5, ADIN6, ADIN7 P1DIRn 0: Port input 1: Port output [...]

I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 255 Panasonic Figure 11-4 P1 3/ADIN8/WDOUT and P14/ADIN9/ST OP (P or t 1) 0: Pullup off 1: Pullup on P1MD(2n+1) P1PUPn P1DIRn 0: Port input 1: Port output P1OUTn Pin 0: Port low output 1: Port high output P1INn ADIN8, A[...]

I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 256 Panas onic Figure 11-5 P15/AD IN10/PWM0 an d P16/ADIN11 /PWM1 (P ort 1) P1PUPn 0: Pullup off 1: Pullup on P1MD(2n+1) 00: P15,P16 01: PWM0,PWM1 10: ADIN10,ADIN11 PWM0,PWM1 P1DIRn 0: Port input 1: Port output Pin P1INn P1OU[...]

I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 257 Panasonic Figure 11-6 /PWM2 (P ort 1), P20/PWM3, P21 /PWM4, P22/PWM5, and P2 3/PWM6 (P ort 2) P1PUPn P2PUPn 0: Pullup off 1: Pullup on P1MD(2n) P2MD(2n) 0: P17, P20, P21, P22, P23 1: PWM2, PWM3, PWM4, PWM5, PWM6 Low[...]

I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 258 Panas onic Figure 11- 7 P24/TM4IC/SBT1 (P ort 2) P2PUP4 0: Pullup off 1: Pullup on 00: P24 01: SBT1 10: TM4IC TM4IC input SBT1 input P2MD9 P2DIR4 0: Port input 1: Port output P2OUT4 Pin P2IN4 0: Port low output 1: Port hi[...]

I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 259 Panasonic Figure 11-8 P27/TM0IO (P or t 2) P2PUP7 0: Pullup off 1: Pullup on P2MD14 0: P27 1: TM0IO P2DIR7 0: Port input 1: Port output P2OUT7 Pin P2IN7 0: Port low output 1: Port high output M 0 1 U X TM0IO input T[...]

I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 260 Panas onic Figure 11-9 P3 5/D AROUT/ R, P36/D A GOUT/G, P37/D ABOUT/B (P ort 3), and P40/D A YMOUT/YM (P or t 4) P3PUPn P4PUPn 0: Pullup off 1: Pullup on 0: DAC output 1: Digital output P3MDn P4MDn 0: P35, P36, P37, P40 1[...]

I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 261 Panasonic Figure 11-1 0 P25/TM4IOB/SBI1/SBD1 and P 26/TM4IO A/SBO1 (P ort 2) P2PUP5 0: Pullup off 1: Pullup on P2MD11 00: P25 01: SBI1,SBD1 P2DIR5 0: Port input 1: Port output 0: 3-line (SBI1,SBD1,SBT1) 1: 2-line (S[...]

I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 262 Panas onic Figure 11-1 1 P55 and P5 6 (P ort 5) P5PUP5 0: Pullup off 1: Pullup on P5MD5 0: P55 1: SBO0 P5DIR5 0: Port input 1: Port output 0: Push-pull 1: Open-drain (For I 2 C mode) (PCNT0) bit 12 ODASCI0 P5OUT5 P5IN5 P5[...]

I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 263 Panasonic Figure 11-12 P 57/SBT0 (P or t 5) P5PUP7 0: Pullup off 1: Pullup on 0: P57 1: SBT0 P5OUT7 P5IN7 SBT0 input 0: Port low outut 1: Port high output Pin P5MD7 P5DIR7 0: Port input 1: Port output 0: Push-pull 1[...]

I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 264 Panas onic Figure 11-1 3 P02/SCL1 (P or t 0) and P61/ SCL0 (P ort 6) P0PUP2 0: Pullup off 1: Pullup on 0: Pullup off 1: Pullup on P0MD2 0: P02 1: SCL1 P0DIR2 0: Port input 1: Port output P0OUT2 SCL output P0IN2 P6IN1 SCL [...]

I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 265 Panasonic Figure 11-14 P01/SD A1 (P ort 1) and P60/SD A0 (P ort 6) P0PUP1 0: Pullup off 1: Pullup on 0: Pullup off 1: Pullup on P0MD1 0: P01 1: SDA1 P0DIR1 0: Port input 1: Port output P0OUT1 SDA output P0IN1 P6IN0 [...]

I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 266 Panas onic Figure 11-15 P31/CVBS0 and P32/CVBS1 (Port 3) P3PUPn 0: Pullup off 1: Pullup on P3MDn 0: P31,P32 1: CVBS0,CVBS1 CVBS0,CVBS1 P3DIRn 0: Port input 1: Port output P3OUTn Pin P3INn 0: Port low output 1: Port high o[...]

I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 267 Panasonic Figure 11-16 P30/CLH and P3 3/CLL (P ort 3) P3PUPn 0: Pullup off 1: Pullup on 0: P30, P33 1: CLH, CLL CLH, CLL P3MD2 P3DIRn 0: Port input 1: Port output P3OUTn Pin P3INn 0: Port low output 1: Port high out[...]

I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 268 Panas onic Figure 11-17 P34/VREF (P or t 3) P3PUP4 0: Pullup off 1: Pullup on P3MD4 0: P34 1: VREF VREF P3DIR4 0: Port input 1: Port output P3OUT4 Pin P3IN4 0: Port low output 1: Port high output P34/VREF[...]

I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 269 Panasonic Figure 11-18 P 41/TM1IO , P42/TM5IO A, and P4 3/TM5IOB/HI 0 (P or t 4) Figure 11-19 P44/TM5IC/HI1 (P ort 4) P4PUPn 0: Pullup off 1: Pullup on P4DIRn 0: P41,P42,P43 1: TM1IO,TM5IOA,TM5IOB P4MDn 0: Port inpu[...]

I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 270 Panas onic Figure 11-20 P45/OSDXO and P46/OSDXI (P or t 4) P4PUP6 (0: Cut,1: Connect) 0: Pullup off 1: Pullup on LCCNT is the OSDXI/O oscillation control signal from the OSD. 0: Disable 1: Enable P4MD5 0: P45/P46 1: OSDXI[...]

I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 271 Panasonic Figure 11-21 P47/HSYNC (P or t 4) P4PUP7 0: Pullup off 1: Pullup on P4MD7 0: P47 1: HSYNC P4DIR7 0: Port input 1: Port output P4OUT7 Pin 0: Port low output 1: Port high output P4IN7 Schmidt trigger HSYNC P[...]

I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 272 Panas onic Figure 11-22 P50/SYSCLK (P or t 5) P5PUP0 0: Pullup off 1: Pullup on P5MD0 0: P50 1: SYSCLK SYSCLK or divided SYSCLK output P5DIR0 0: Port input 1: Port output P5OUT0 Pin P5IN0 0: Port low output 1: Port high o[...]

I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 273 Panasonic Figure 11-23 P51/YS (P or t 5) P5PUP1 0: Pullup off 1: Pullup on P5MD1 0: P51 1: YS YSOUT P5IN1 P5DIR1 0: Port input 1: Port output P5OUT1 Pin 0: Port low output 1: Port high output M 0 1 U X P51/YS[...]

I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 274 Panas onic Figure 11-24 P52/IRQ4/VI0 (P or t 5) P5PUP2 0: Pullup off 1: Pullup on P5MD2 0: P52 1: IRQ4/VI0 P5DIR2 0: Port input 1: Port output P5OUT2 Pin 0: Port low output 1: Port high output P5IN2 Schmidt trigger IRQ4/V[...]

I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 275 Panasonic Figure 11 -25 P53/RST (P ort 5) P5PUP3 0: Pullup off 1: Pullup on P5OUT3 0: Port low output 1: Port high output P5DIR3 0: Port input 1: Port output P5IN3/ NTGTRST Pin Schmidt trigger P53/ RST[...]

I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 276 Panas onic Figure 11-26 P54/IRQ5/VSYNC (P ort 5) P5PUP4 0: Pullup off 1: Pullup on P5MD4 P5DIR4 0: Port input 1: Port output P5OUT4 Pin 0: Port low output 1: Port high output 0: P54/IRQ5 1: IRQ5/VSYNC P5IN4 Schmidt trigge[...]

I/O Ports I/O Port C ontrol Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 277 Panasonic 11.3 I/ O P ort Contr ol Register s Do not activ ate the pullup resis- tors when the pins are in output mode. This wil l cause incorrect output v oltage lev els and increase power and current con- sumptio[...]

I/O Ports I/O Port Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 278 Panas onic P0IN – P5IN: P or ts 0 – 5 Input Registers x’00FF D0’ – x’00FFD5’ P7IN – P8IN: P or ts 7 – 8 Input Registers x’00FFD8’ – x’00FFD A’ P6IN: P or t 6 Input Register x’00FFD 6’ The Pn[...]

I/O Ports I/O Port C ontrol Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 279 Panasonic P0MD: P ort 0 Output M ode Regi ster x’00FFF 0’ P0MD is an 8-bit access reg ister . P0MD7: P07 function s witch 0: P07 1: ADIN4 P0MD6: P06 function s witch 0: P06 1: ADIN3 P0MD5: P05 function s witch [...]

I/O Ports I/O Port Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 280 Panas onic P1MD: P ort 1 Output M ode Regi ster x’00 FFF2’ P1MD is a 16-bit access reg is ter . P1MD14 : P17 outpu t s witch 0: P17 1: PWM2 P1MD[1 3:12]: P16 o utput and function s witch 00: P1 6 01: ADIN11 10: PW M1 1[...]

I/O Ports I/O Port C ontrol Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 281 Panasonic P2MD: P ort 2 Output M ode Regi ster x’00FFF 4’ P2MD is a 16-bit access reg is ter . P2MD14 : P27 func tion s witch T o use TM0IO as an output p in, set this b it to 1 and set th e P2DIR7 bit to 1. 0:[...]

I/O Ports I/O Port Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 282 Panas onic P3MD: P ort 3 Output M ode Regi ster x’00 FFF6’ P3MD is an 8-bit access reg ister . P3MD7: P37 output switch If you set this field to 1, select D AB OUT or B in the RGBC bit of ODS 1. 0: P37 1: D ABOUT or B [...]

I/O Ports I/O Port C ontrol Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 283 Panasonic P4MD: P ort 4 Output M ode Regi ster x’00FFF 8’ P4MD is an 8-bit access reg ister . P4MD7: P47 function s witch 0: P47/NHSYNC 1: NHSYNC P4MD6 This bit exists, but contains no funct ion. P4MD5: P45 fun[...]

I/O Ports I/O Port Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 284 Panas onic P5MD: P ort 5 Output M ode Regi ster x’00FFF A’ P5MD is an 8-bit access reg ister . P5MD7: P57 output switch T o use SBT0 as an input pin , set this f ield to 0 and se t the P5DIR7 bit to 0. 0: P57 1: SBT0 P[...]

I/O Ports I/O Port C ontrol Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 285 Panasonic PCNT0: P or t Control Re gister 0 x’00 FF90’ PCNT0 is a 16-bit access register . Enable PWM (set PCNT1 bit 1 to 1) if you are outputt ing f SY- SCLK /2 14 . SCLKF[1:0]: SYS C LK frequency sel ect 00: [...]

I/O Ports I/O Port Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 286 Panas onic T o turn off the OSD b loc k to sa ve powe r : 1. Write a 0 to OSD (OSD1, b it 10). 2. W ait f or the ne xt VSYNC input. 3. Write a 0 to OSDPOFF (PCNT0, bit 7), turning the cloc k off . If you tur n th e clo ck [...]

I/O Ports I/O Port C ontrol Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 287 Panasonic PCNT2: P or t Control Re gister 2 x’00 FF92’ Alwa ys set bits 7 to 3 of PCNT2 to 0. Y ou cannot read from or write to the registers associated with a function that is disabled. P7P8 CNT: P o r ts 7 an[...]

ROM Correction Description Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 288 Panasonic 12 R OM Correction 12.1 De scripti on The R OM correction func t ion can co rrect the p rog ram data in an y address within the 256-kilobyte R OM. (It cannot correct OSD R OM data.) A maxim um o f sixteen addresses can b e[...]

ROM Correction Block Diagram MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 289 Panasonic 12.2 Block Diagram Figur e 12- 3 i s a blo ck di agr am of the R O M cor rect ion ci rcu i t. A match detect io n circuit constantly monitor s the R OM address specified by the CPU instruction pointer (IP). When t[...]

ROM Correction ROM Correction Control Re gisters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 290 Panasonic 12.4 R OM Correction Contr ol Registers T able 12-1 sho ws the organization o f the address match and data re gisters for R OM correction. Write a R OM address to be corrected t o an AMCHIHn an d AMCH[...]

ROM Correction ROM Corr ection Control Re gisters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 291 Panasonic R OMCEN12 : Addres s 12 R OM correct ion enab le 0: Disa ble 1: Enable R OMCEN11 : Addres s 11 R OM correct ion enab le 0: Disa ble 1: Enable R OMCEN10 : Addres s 10 R OM correct ion enab le 0[...]

ROM Correction ROM Correction Control Re gisters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 292 Panasonic AMCHIH0 – AMCHIHF: ROM C orrection Addres s Match Re gister n (H igh) AMCHIHn is an 8-bit access re gister . CHAD[23:16]: Co rrection ad dress bits A2 3 to A16 (A23 = MSB) AMCHIL0 – AMCHILF: R OM [...]

I 2 C Bus Controller Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 293 Panasonic 13 I 2 C Bus Controller 13.1 De scripti on The MN102H75K/85 K contains one I 2 C b us controller , fully complian t with the I 2 C specif ication, that can control o ne of two I 2 C b u s connections. An I 2 C[...]

I 2 C Bus Controller Description Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 294 Panasonic Figure 13-2 sho ws an e xample of an I 2 C bus con figurati on usi ng tw o micro con- trollers. Both I 2 C b us lines, SD A and SCL are bidirectional lines, connected to a positive supply v oltage vi a a pullup resis[...]

I 2 C Bus Controller Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 295 Panasonic Figure 13-3 sho ws the MN102H75K/85K op eration sequence in each o f these modes. In all modes , the I 2 C bus controller gener ates an interrupt af ter each data byte transfer , then the software loads the ne[...]

I 2 C Bus Controller Bloc k Diag ram Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 296 Panasonic 13.2 Block Diagram 13.3 Functional Description The I 2 C b us controlle r contains the regis ters sho wn in tabl e 13-3. See the page number indicated for reg ister and bit descriptions. ■ Arbitration and b us [...]

I 2 C Bus Controller Functional Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 297 Panasonic ■ Register settings con ver sions to I 2 C pr otocol The I 2 C b us controller con verts the data in the I2CDTRM register to the I 2 C protoco l. ■ T ransfe r modes c hanges A write to the I2CDT[...]

I 2 C Bus Controller Setting Up the I 2 C Bus Con nection Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 298 Panasonic 13.4 S etting Up t he I 2 C Bus Connection Set the I 2 C connection in the I2CSEL0 and I2CSEL1 b its of the PCNT0 re gis ter (x’00FF90’). Since the SCL0, SD A0, SCL1, and SD A1 pins also [...]

I 2 C Bus Controller SDA and SCL W a veform Char acteristics MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 299 Panasonic 13.5 SD A and SCL W avef orm Cha racteri stics Figur e 13-6 and t able 13- 5 pro vide the timing def initions and sp ecif ications for the for the MN102H75K/8 5K I 2 C bus interface[...]

I 2 C Bus Controller I 2 C In terf ace Se tup Ex amples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 300 Panasonic 13.6 I 2 C Int erfac e Set up Exampl es 13.6.1 Setting Up a T ransition from Master Transmitter to Mas- ter Receiver This e xample demonstrates ho w to set up a data transfer when changing from[...]

I 2 C Bus Controller I 2 C Interfac e Setup Example s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 301 Panasonic 13.6.1.3 Setting Up the Second I nterrupt When the microcontro ller recei v es th e data x’85’ from the sla v e de vice, it returns an A CK = 0 sign al and the I 2 C bus controller gen[...]

I 2 C Bus Controller I 2 C In terf ace Se tup Ex amples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 302 Panasonic 13.6.2 Setting Up a T r ansition from Slave Receiver to Slave T ransmitter This e xample demonstrates ho w to set up a data transfer when changing from slav e recei ver to sla ve transmitter . [...]

I 2 C Bus Controller I 2 C Interfac e Setup Example s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 303 Panasonic 13.6.2.3 Setting Up the Second I nterrupt The master sends an A CK = 0 signal, so the m icrocontroller must send the ne xt data byte. Set up the transm is sion data as follows: ■ T o set[...]

I 2 C Bus Controller I 2 C Bu s Inte rfac e Regis ters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 304 Panasonic 13.7 I 2 C Bus Int erface R egister s All registers in I 2 C bloo k cannot be wri tten by byte ( by wo rd onl y). Read by byt e is possible. I2CDTRM: I 2 C T ra nsmissi on Data Registe r x’007[...]

I 2 C Bus Controller I 2 C Bus Interface Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 305 Panasonic I2CDREC: I 2 C Recepti on Data Register x’00 7E42’ The I2CDREC re gis ter contains the status bits for monitoring the d evice and the reception data. I2CDREC is a read-o nly re gister . M[...]

I 2 C Bus Controller I 2 C Bu s Inte rfac e Regis ters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 306 Panasonic I2CCLK: I 2 C Cloc k Control Register x’007E4 6’ T o conform to the specification, the clock signal must be between 0 and 100 kHz. T o sat- isfy this requirement, always set I2CCLK to x’03[...]

H Counter Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 307 Panasonic 14 H Counter 14.1 De scripti on The MN102H75K/85K contain s two H coun ter circuits that can be u sed to count the HSYNC signal. Each H counter consists of a 1 0-bit counter and 10-bit regis ter . 14.2 Block Diagram 14.3[...]

H Counter H Counter Operation Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 308 Panasonic Figure 14-3 shows the input timing for the count sou rce and reset signals. Nev er input a count so urce signal in less th an 2 45 ns (t 1 ) af ter the reset signal input. Otherwise, the signal may be counted as pa rt o[...]

H Counter H Counter Operation MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 309 Panasonic The H counter counts the HSYNC signal for the interv al set in the HCCNT0 (x’007EB 0’) or HCCNT1 (x’007EB 2’) re gister , latc hes t he co un t value i n th e 10 - bit register , then clears the co unter [...]

H Counter H Counter Control Re gisters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 310 Panasonic 14.4 H Counter Contr ol Register s All registers in H Counter block cannot be written by by te (by word only). Read by byte is po ssibl e . HCCNT0: H Counter Control Re gister 0 x’00 7EB0 ’ SEDG0: P olarity[...]

H Counter H Counter Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 311 Panasonic HCD0: H Counter D ata Re gister 0 x’00 7EB4 ’ HCD[90:00]: Count from HI0 source signal This f ield stor es the HI0 clock source cou n t. It becomes x’3FF’ on o ver- flo w . HCD1: H Counter D ata R[...]

Register Map Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 312 Panasonic Appendix A Register Map T able A-1 Re gister Map: x ’007E00’ to x ’007FFF’ (Registers in this area cannot be written b y by te onl y b y word .) 20 MSBs 4 LSBs Description F E D C B A9876543210 007E00 CRI4 FQW CRI3 FQW CRI2 FQW [...]

Register Map MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 313 Panasonic T able A- 2 Registe r Map: x’00F C00’ to x’00FD FF’ 20 MSBs 4 LSBs Description F E D C B A9876543210 00FC00 IA GR CPUM Spec ial function registers 00FC10 00FC20 00FC30 00FC40 IQ1 ICH IQ1 ICL IQ0 ICH IQ0 ICL EI ICR PI ICR [...]

Register Map Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 314 Panasonic T able A-3 Re gister Map: x ’00FE00’ to x ’00FFFF ’ 20 MSBs 4 LSBs Description F E D C B A9876543210 00FE00 TM3 BC TM2 BC TM1 BC TM0 BC 8-bit timer registers 00FE10 TM3 BR TM2 BR TM1 BR TM0 BR 00FE20 TM3 MD TM2 MD TM1 MD TM0 MD [...]

Register Map MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 315 Panasonic[...]

MN102HF75K Flash EEPRO M Version Description Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 316 Panasonic Appendix B MN102HF 75K Flash EEPR OM V er sion B.1 Descri ption The MN102HF75K and MN102HF85K are electrically pro grammable, 256- kilobyte f l ash R OM v ersions of the MN102 H75K and MN102H85 K. The y a[...]

MN102HF75K Flash EEPROM Ve rsion Benefits MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 317 Panasonic B.2 Benefits Because you can maintain and upgr ade the program in the MN102HF75K/85K up to an d immediat ely fol lo wing pro duct re lease, th is ve rsion of the de vice shortens time-to-mark et by as[...]

MN102HF75K Flash EEPRO M Version Using the PROM Writer Mo de Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 318 Panasonic Check th e follo wing web page of our microcomputer di visio n for the writer matching info rmation. http:// www .mec p anasonic.co.j p/sc/di vision/micom T able B-2 PROM Writer Hard wa re[...]

MN102HF75K Flash EEPROM Ve rsion Using the Onboard Serial Programming M ode MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 319 Panasonic B.4 Using the Onboar d Serial Program ming Mode The seri al programm ing mode i s primari ly used to pr ogram the flash R OM in de vices that are already installed on[...]

MN102HF75K Flash EEPRO M Version Using the O nboard Se rial Pro gramming Mo de Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 320 Panasonic B.4. 1 Config uring the Syste m fo r Onboard Serial Prog ramming The work station containin g the program data sends the program t o the seri al writer through an IC card[...]

MN102HF75K Flash EEPROM Ve rsion Using the Onboard Serial Programming M ode MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 321 Panasonic B.4.2 Circuit R equirements for the T arget Boa rd ■ Duri ng pro gram ming , the s e rial w rite r s upp lie s V PP to the microcon troller . Instal l a switch o n [...]

MN102HF75K Flash EEPRO M Version Using the O nboard Se rial Pro gramming Mo de Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 322 Panasonic B.4.3 Microcont roller Hardware Used in O nboard Serial Pro- grammin g B.4.3.1 Seria l Writer Interface Descrip tion The microcontroller con t ains the follo wing interfa[...]

MN102HF75K Flash EEPROM Ve rsion Using the Onboard Serial Programming M ode MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 323 Panasonic B.4.4 Microcont roller Memo ry Map Used During On board Serial Progra mming B.4. 4.1 Flash R OM Ad dr ess Space ■ Serial write r load pr ogram area This k ilobyte o[...]

MN102HF75K Flash EEPRO M Version Using the O nboard Se rial Pro gramming Mo de Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 324 Panasonic ■ Branch in struction to inte rrupt service r outine Normally , interrupt servicing starts at address x’0x 80008’, b ut the soft branch instruction in the s erial w[...]

MN102HF75K Flash EEPROM Ve rsion Using the Onboard Serial Programming M ode MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 325 Panasonic B.4.6 Setting Up the Onbo ard Serial Pr ogramming Mod e T o enter s erial pro gramming m ode, the micro controller mu st be i n write mo de. This section describes th[...]

MN102HF75K Flash EEPRO M Version Using the O nboard Se rial Pro gramming Mo de Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 326 Panasonic ■ Start routin e f or the load pr ogram Condi tions: 1. After the load program initiates a res e t start, SB D must be low and SBT high . 2. After the program waits t W[...]

MN102HF75K Flash EEPROM Ve rsion Using the Onboard Serial Programming M ode MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 327 Panasonic B.4.7 Branching to the Us er Program B.4.7.1 B ranc hing to the Reset Start Routine When the reset starts, the s erial writer load program init ializes o nly if SBD i[...]

MN102HF75K Flash EEPRO M Version Reprogram ming Flow Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 328 Panasonic B.5 Repr ogramming Flow Figur e B-12 sho ws the flo w for reprog ramming (erasing and programming) t he flash memory . Always program a fter eras in g is compl eted.Er asing is sometimes no t done[...]

page Line defini- Description of Changes tion Former version New version Cover Pub number C 22385-010E 22385-011E Colophon C September, 2001 1st Edition October, 2001 1st Edition 1st Printing Sales office C Latest version MN102H75K/F75K/85K/F85K LSI User's Manual Description Record of Changes (Ver.1.0 to 1.1) <Definition> A: add D: delet[...]

MN102H75K/F75K/85K/F85K LSI User’s Manual Modified Points From MN102H75K/F75K To MN102H75K/F75K/85K/F85K MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 1 Panasonic page Before Modify page Af ter Modify P16 This manual is intended for assembly-lan guage programming engineers. It describes the internal[...]

Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 2 Panasonic P30 1.6 Pin De scriptions 1.6.1 MN102H85K Pin Description Notes : 1. Pins marked with an as terisk (*) are N-channel, open-drain pins. 2. Pin 25 is V DD in the MN102H85K and V PP in the MN102HF85K. Figure 1-9 MN102H85K Pin Configuration in Single-Chi [...]

MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 3 Panasonic P33 The MN102H75K contains an inter nal PLL circ uit. T o use this circuit, you must connect it to an external (lag-lead) f ilter . P34 The MN102 H75K/85K contains an i nternal PLL cir cuit. T o us e this circuit, you must connect it to an exte[...]

Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 4 Panasonic P77 The MN102H75K contains four 8-bit timers t hat can serve as inte rv al timers, event timer/counters, cl ock generators ( di vide-by-2 output of the underflow), reference clocks for the serial interfaces, or start timers for A/D con versions. The c[...]

MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 5 Panasonic P307 The MN102H75K contains two H counter cir cuits that can b e used to count the HSYNC signal. Each H counter consists of a 10-bit counter and 10-bit register P307 The MN102H75K/85K contains two H coun ter circuits that can be used to count t[...]

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Issued by Matsushita Electric Industrial Co., Ltd.  Matsushita E lectric I ndustrial Co., Ltd. MN10 2H75 K/F75K /85K /F85K LSI U ser ’s M anual October ,2001 1st E d ition 1 st Printi ng[...]

Semiconductor Company, Matsushita Electric Industrial Co., Ltd. Nagaokakyo, Kyoto, 617-8520 Japan Tel: (075) 951-8151 http://www.panasonic.co.jp/semicon/ SALES OFFICES ■ NORTH AMERICA ● U.S.A. Sales Office: Panasonic Industrial Company [PIC] • New Jersey Office: Two Panasonic Way Secaucus, New Jersey 07094 U.S.A. Tel: 1-201-348-5257 Fax:1-201[...]